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Generate the Verilog code corresponding to this FIRRTL code module PE_451 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_195
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<8>, clock
reg c2 : SInt<8>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h0), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node _c1_T = bits(io.in_d, 7, 0)
node _c1_T_1 = asSInt(_c1_T)
connect c1, _c1_T_1
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node _c2_T = bits(io.in_d, 7, 0)
node _c2_T_1 = asSInt(_c2_T)
connect c2, _c2_T_1
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h0), _T_4)
node _T_6 = or(UInt<1>(0h1), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_451( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_195 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_7 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<8>(0h90))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<6>(0h20))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<6>(0h21))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<6>(0h22))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<6>(0h23))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 5, 0)
node _source_ok_T_25 = shr(io.in.a.bits.source, 6)
node _source_ok_T_26 = eq(_source_ok_T_25, UInt<1>(0h1))
node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27)
node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<6>(0h3f))
node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29)
node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 5, 0)
node _source_ok_T_31 = shr(io.in.a.bits.source, 6)
node _source_ok_T_32 = eq(_source_ok_T_31, UInt<1>(0h0))
node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33)
node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<6>(0h3f))
node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35)
node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<9>(0h100))
wire _source_ok_WIRE : UInt<1>[11]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_30
connect _source_ok_WIRE[6], _source_ok_T_36
connect _source_ok_WIRE[7], _source_ok_T_37
connect _source_ok_WIRE[8], _source_ok_T_38
connect _source_ok_WIRE[9], _source_ok_T_39
connect _source_ok_WIRE[10], _source_ok_T_40
node _source_ok_T_41 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[2])
node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[3])
node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[4])
node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[5])
node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[6])
node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[7])
node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[8])
node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[9])
node source_ok = or(_source_ok_T_49, _source_ok_WIRE[10])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<6>(0h20))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<6>(0h21))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<6>(0h22))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<6>(0h23))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 5, 0)
node _T_64 = shr(io.in.a.bits.source, 6)
node _T_65 = eq(_T_64, UInt<1>(0h1))
node _T_66 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_67 = and(_T_65, _T_66)
node _T_68 = leq(uncommonBits_4, UInt<6>(0h3f))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_72 = cvt(_T_71)
node _T_73 = and(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = asSInt(_T_73)
node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0)))
node _T_76 = or(_T_70, _T_75)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 5, 0)
node _T_77 = shr(io.in.a.bits.source, 6)
node _T_78 = eq(_T_77, UInt<1>(0h0))
node _T_79 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_80 = and(_T_78, _T_79)
node _T_81 = leq(uncommonBits_5, UInt<6>(0h3f))
node _T_82 = and(_T_80, _T_81)
node _T_83 = eq(_T_82, UInt<1>(0h0))
node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_85 = cvt(_T_84)
node _T_86 = and(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = asSInt(_T_86)
node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0)))
node _T_89 = or(_T_83, _T_88)
node _T_90 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_91 = eq(_T_90, UInt<1>(0h0))
node _T_92 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_93 = cvt(_T_92)
node _T_94 = and(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = asSInt(_T_94)
node _T_96 = eq(_T_95, asSInt(UInt<1>(0h0)))
node _T_97 = or(_T_91, _T_96)
node _T_98 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_99 = eq(_T_98, UInt<1>(0h0))
node _T_100 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_101 = cvt(_T_100)
node _T_102 = and(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = asSInt(_T_102)
node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0)))
node _T_105 = or(_T_99, _T_104)
node _T_106 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_107 = eq(_T_106, UInt<1>(0h0))
node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_109 = cvt(_T_108)
node _T_110 = and(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = asSInt(_T_110)
node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0)))
node _T_113 = or(_T_107, _T_112)
node _T_114 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_115 = eq(_T_114, UInt<1>(0h0))
node _T_116 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_117 = cvt(_T_116)
node _T_118 = and(_T_117, asSInt(UInt<1>(0h0)))
node _T_119 = asSInt(_T_118)
node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0)))
node _T_121 = or(_T_115, _T_120)
node _T_122 = and(_T_11, _T_24)
node _T_123 = and(_T_122, _T_37)
node _T_124 = and(_T_123, _T_50)
node _T_125 = and(_T_124, _T_63)
node _T_126 = and(_T_125, _T_76)
node _T_127 = and(_T_126, _T_89)
node _T_128 = and(_T_127, _T_97)
node _T_129 = and(_T_128, _T_105)
node _T_130 = and(_T_129, _T_113)
node _T_131 = and(_T_130, _T_121)
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_131, UInt<1>(0h1), "") : assert_1
node _T_135 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_135 :
node _T_136 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_137 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_138 = and(_T_136, _T_137)
node _T_139 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_140 = shr(io.in.a.bits.source, 2)
node _T_141 = eq(_T_140, UInt<6>(0h20))
node _T_142 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_143 = and(_T_141, _T_142)
node _T_144 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_145 = and(_T_143, _T_144)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_146 = shr(io.in.a.bits.source, 2)
node _T_147 = eq(_T_146, UInt<6>(0h21))
node _T_148 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_149 = and(_T_147, _T_148)
node _T_150 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_152 = shr(io.in.a.bits.source, 2)
node _T_153 = eq(_T_152, UInt<6>(0h22))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_157 = and(_T_155, _T_156)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_158 = shr(io.in.a.bits.source, 2)
node _T_159 = eq(_T_158, UInt<6>(0h23))
node _T_160 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_161 = and(_T_159, _T_160)
node _T_162 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_163 = and(_T_161, _T_162)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 5, 0)
node _T_164 = shr(io.in.a.bits.source, 6)
node _T_165 = eq(_T_164, UInt<1>(0h1))
node _T_166 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_167 = and(_T_165, _T_166)
node _T_168 = leq(uncommonBits_10, UInt<6>(0h3f))
node _T_169 = and(_T_167, _T_168)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 5, 0)
node _T_170 = shr(io.in.a.bits.source, 6)
node _T_171 = eq(_T_170, UInt<1>(0h0))
node _T_172 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_173 = and(_T_171, _T_172)
node _T_174 = leq(uncommonBits_11, UInt<6>(0h3f))
node _T_175 = and(_T_173, _T_174)
node _T_176 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_177 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_178 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_179 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_180 = or(_T_139, _T_145)
node _T_181 = or(_T_180, _T_151)
node _T_182 = or(_T_181, _T_157)
node _T_183 = or(_T_182, _T_163)
node _T_184 = or(_T_183, _T_169)
node _T_185 = or(_T_184, _T_175)
node _T_186 = or(_T_185, _T_176)
node _T_187 = or(_T_186, _T_177)
node _T_188 = or(_T_187, _T_178)
node _T_189 = or(_T_188, _T_179)
node _T_190 = and(_T_138, _T_189)
node _T_191 = or(UInt<1>(0h0), _T_190)
node _T_192 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_193 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_194 = cvt(_T_193)
node _T_195 = and(_T_194, asSInt(UInt<13>(0h1000)))
node _T_196 = asSInt(_T_195)
node _T_197 = eq(_T_196, asSInt(UInt<1>(0h0)))
node _T_198 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_199 = cvt(_T_198)
node _T_200 = and(_T_199, asSInt(UInt<13>(0h1000)))
node _T_201 = asSInt(_T_200)
node _T_202 = eq(_T_201, asSInt(UInt<1>(0h0)))
node _T_203 = or(_T_197, _T_202)
node _T_204 = and(_T_192, _T_203)
node _T_205 = or(UInt<1>(0h0), _T_204)
node _T_206 = and(_T_191, _T_205)
node _T_207 = asUInt(reset)
node _T_208 = eq(_T_207, UInt<1>(0h0))
when _T_208 :
node _T_209 = eq(_T_206, UInt<1>(0h0))
when _T_209 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_206, UInt<1>(0h1), "") : assert_2
node _T_210 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_211 = shr(io.in.a.bits.source, 2)
node _T_212 = eq(_T_211, UInt<6>(0h20))
node _T_213 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_214 = and(_T_212, _T_213)
node _T_215 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_216 = and(_T_214, _T_215)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_217 = shr(io.in.a.bits.source, 2)
node _T_218 = eq(_T_217, UInt<6>(0h21))
node _T_219 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_220 = and(_T_218, _T_219)
node _T_221 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_222 = and(_T_220, _T_221)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_223 = shr(io.in.a.bits.source, 2)
node _T_224 = eq(_T_223, UInt<6>(0h22))
node _T_225 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_226 = and(_T_224, _T_225)
node _T_227 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_228 = and(_T_226, _T_227)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_229 = shr(io.in.a.bits.source, 2)
node _T_230 = eq(_T_229, UInt<6>(0h23))
node _T_231 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_232 = and(_T_230, _T_231)
node _T_233 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_234 = and(_T_232, _T_233)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 5, 0)
node _T_235 = shr(io.in.a.bits.source, 6)
node _T_236 = eq(_T_235, UInt<1>(0h1))
node _T_237 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_238 = and(_T_236, _T_237)
node _T_239 = leq(uncommonBits_16, UInt<6>(0h3f))
node _T_240 = and(_T_238, _T_239)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 5, 0)
node _T_241 = shr(io.in.a.bits.source, 6)
node _T_242 = eq(_T_241, UInt<1>(0h0))
node _T_243 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_244 = and(_T_242, _T_243)
node _T_245 = leq(uncommonBits_17, UInt<6>(0h3f))
node _T_246 = and(_T_244, _T_245)
node _T_247 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_248 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_249 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_250 = eq(io.in.a.bits.source, UInt<9>(0h100))
wire _WIRE : UInt<1>[11]
connect _WIRE[0], _T_210
connect _WIRE[1], _T_216
connect _WIRE[2], _T_222
connect _WIRE[3], _T_228
connect _WIRE[4], _T_234
connect _WIRE[5], _T_240
connect _WIRE[6], _T_246
connect _WIRE[7], _T_247
connect _WIRE[8], _T_248
connect _WIRE[9], _T_249
connect _WIRE[10], _T_250
node _T_251 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_252 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_253 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_254 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_255 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_256 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_257 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_258 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_259 = mux(_WIRE[7], _T_251, UInt<1>(0h0))
node _T_260 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_261 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_262 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_263 = or(_T_252, _T_253)
node _T_264 = or(_T_263, _T_254)
node _T_265 = or(_T_264, _T_255)
node _T_266 = or(_T_265, _T_256)
node _T_267 = or(_T_266, _T_257)
node _T_268 = or(_T_267, _T_258)
node _T_269 = or(_T_268, _T_259)
node _T_270 = or(_T_269, _T_260)
node _T_271 = or(_T_270, _T_261)
node _T_272 = or(_T_271, _T_262)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_272
node _T_273 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_274 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_275 = and(_T_273, _T_274)
node _T_276 = or(UInt<1>(0h0), _T_275)
node _T_277 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_278 = cvt(_T_277)
node _T_279 = and(_T_278, asSInt(UInt<13>(0h1000)))
node _T_280 = asSInt(_T_279)
node _T_281 = eq(_T_280, asSInt(UInt<1>(0h0)))
node _T_282 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_283 = cvt(_T_282)
node _T_284 = and(_T_283, asSInt(UInt<13>(0h1000)))
node _T_285 = asSInt(_T_284)
node _T_286 = eq(_T_285, asSInt(UInt<1>(0h0)))
node _T_287 = or(_T_281, _T_286)
node _T_288 = and(_T_276, _T_287)
node _T_289 = or(UInt<1>(0h0), _T_288)
node _T_290 = and(_WIRE_1, _T_289)
node _T_291 = asUInt(reset)
node _T_292 = eq(_T_291, UInt<1>(0h0))
when _T_292 :
node _T_293 = eq(_T_290, UInt<1>(0h0))
when _T_293 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_290, UInt<1>(0h1), "") : assert_3
node _T_294 = asUInt(reset)
node _T_295 = eq(_T_294, UInt<1>(0h0))
when _T_295 :
node _T_296 = eq(source_ok, UInt<1>(0h0))
when _T_296 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_297 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_298 = asUInt(reset)
node _T_299 = eq(_T_298, UInt<1>(0h0))
when _T_299 :
node _T_300 = eq(_T_297, UInt<1>(0h0))
when _T_300 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_297, UInt<1>(0h1), "") : assert_5
node _T_301 = asUInt(reset)
node _T_302 = eq(_T_301, UInt<1>(0h0))
when _T_302 :
node _T_303 = eq(is_aligned, UInt<1>(0h0))
when _T_303 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_304 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_305 = asUInt(reset)
node _T_306 = eq(_T_305, UInt<1>(0h0))
when _T_306 :
node _T_307 = eq(_T_304, UInt<1>(0h0))
when _T_307 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_304, UInt<1>(0h1), "") : assert_7
node _T_308 = not(io.in.a.bits.mask)
node _T_309 = eq(_T_308, UInt<1>(0h0))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_309, UInt<1>(0h1), "") : assert_8
node _T_313 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_313, UInt<1>(0h1), "") : assert_9
node _T_317 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _T_321 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_322 = shr(io.in.a.bits.source, 2)
node _T_323 = eq(_T_322, UInt<6>(0h20))
node _T_324 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_325 = and(_T_323, _T_324)
node _T_326 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_327 = and(_T_325, _T_326)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_328 = shr(io.in.a.bits.source, 2)
node _T_329 = eq(_T_328, UInt<6>(0h21))
node _T_330 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_331 = and(_T_329, _T_330)
node _T_332 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_333 = and(_T_331, _T_332)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_334 = shr(io.in.a.bits.source, 2)
node _T_335 = eq(_T_334, UInt<6>(0h22))
node _T_336 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_337 = and(_T_335, _T_336)
node _T_338 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_339 = and(_T_337, _T_338)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_340 = shr(io.in.a.bits.source, 2)
node _T_341 = eq(_T_340, UInt<6>(0h23))
node _T_342 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_343 = and(_T_341, _T_342)
node _T_344 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_345 = and(_T_343, _T_344)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 5, 0)
node _T_346 = shr(io.in.a.bits.source, 6)
node _T_347 = eq(_T_346, UInt<1>(0h1))
node _T_348 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_349 = and(_T_347, _T_348)
node _T_350 = leq(uncommonBits_22, UInt<6>(0h3f))
node _T_351 = and(_T_349, _T_350)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 5, 0)
node _T_352 = shr(io.in.a.bits.source, 6)
node _T_353 = eq(_T_352, UInt<1>(0h0))
node _T_354 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_355 = and(_T_353, _T_354)
node _T_356 = leq(uncommonBits_23, UInt<6>(0h3f))
node _T_357 = and(_T_355, _T_356)
node _T_358 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_359 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_360 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_361 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_362 = or(_T_321, _T_327)
node _T_363 = or(_T_362, _T_333)
node _T_364 = or(_T_363, _T_339)
node _T_365 = or(_T_364, _T_345)
node _T_366 = or(_T_365, _T_351)
node _T_367 = or(_T_366, _T_357)
node _T_368 = or(_T_367, _T_358)
node _T_369 = or(_T_368, _T_359)
node _T_370 = or(_T_369, _T_360)
node _T_371 = or(_T_370, _T_361)
node _T_372 = and(_T_320, _T_371)
node _T_373 = or(UInt<1>(0h0), _T_372)
node _T_374 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_375 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_376 = cvt(_T_375)
node _T_377 = and(_T_376, asSInt(UInt<13>(0h1000)))
node _T_378 = asSInt(_T_377)
node _T_379 = eq(_T_378, asSInt(UInt<1>(0h0)))
node _T_380 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_381 = cvt(_T_380)
node _T_382 = and(_T_381, asSInt(UInt<13>(0h1000)))
node _T_383 = asSInt(_T_382)
node _T_384 = eq(_T_383, asSInt(UInt<1>(0h0)))
node _T_385 = or(_T_379, _T_384)
node _T_386 = and(_T_374, _T_385)
node _T_387 = or(UInt<1>(0h0), _T_386)
node _T_388 = and(_T_373, _T_387)
node _T_389 = asUInt(reset)
node _T_390 = eq(_T_389, UInt<1>(0h0))
when _T_390 :
node _T_391 = eq(_T_388, UInt<1>(0h0))
when _T_391 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_388, UInt<1>(0h1), "") : assert_10
node _T_392 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_393 = shr(io.in.a.bits.source, 2)
node _T_394 = eq(_T_393, UInt<6>(0h20))
node _T_395 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_396 = and(_T_394, _T_395)
node _T_397 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_398 = and(_T_396, _T_397)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_399 = shr(io.in.a.bits.source, 2)
node _T_400 = eq(_T_399, UInt<6>(0h21))
node _T_401 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_402 = and(_T_400, _T_401)
node _T_403 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_404 = and(_T_402, _T_403)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_405 = shr(io.in.a.bits.source, 2)
node _T_406 = eq(_T_405, UInt<6>(0h22))
node _T_407 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_408 = and(_T_406, _T_407)
node _T_409 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_410 = and(_T_408, _T_409)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_411 = shr(io.in.a.bits.source, 2)
node _T_412 = eq(_T_411, UInt<6>(0h23))
node _T_413 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_414 = and(_T_412, _T_413)
node _T_415 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_416 = and(_T_414, _T_415)
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 5, 0)
node _T_417 = shr(io.in.a.bits.source, 6)
node _T_418 = eq(_T_417, UInt<1>(0h1))
node _T_419 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_420 = and(_T_418, _T_419)
node _T_421 = leq(uncommonBits_28, UInt<6>(0h3f))
node _T_422 = and(_T_420, _T_421)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 5, 0)
node _T_423 = shr(io.in.a.bits.source, 6)
node _T_424 = eq(_T_423, UInt<1>(0h0))
node _T_425 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_426 = and(_T_424, _T_425)
node _T_427 = leq(uncommonBits_29, UInt<6>(0h3f))
node _T_428 = and(_T_426, _T_427)
node _T_429 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_430 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_431 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_432 = eq(io.in.a.bits.source, UInt<9>(0h100))
wire _WIRE_2 : UInt<1>[11]
connect _WIRE_2[0], _T_392
connect _WIRE_2[1], _T_398
connect _WIRE_2[2], _T_404
connect _WIRE_2[3], _T_410
connect _WIRE_2[4], _T_416
connect _WIRE_2[5], _T_422
connect _WIRE_2[6], _T_428
connect _WIRE_2[7], _T_429
connect _WIRE_2[8], _T_430
connect _WIRE_2[9], _T_431
connect _WIRE_2[10], _T_432
node _T_433 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_434 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_435 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_436 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_437 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_438 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_439 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_440 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_441 = mux(_WIRE_2[7], _T_433, UInt<1>(0h0))
node _T_442 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_443 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_444 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_445 = or(_T_434, _T_435)
node _T_446 = or(_T_445, _T_436)
node _T_447 = or(_T_446, _T_437)
node _T_448 = or(_T_447, _T_438)
node _T_449 = or(_T_448, _T_439)
node _T_450 = or(_T_449, _T_440)
node _T_451 = or(_T_450, _T_441)
node _T_452 = or(_T_451, _T_442)
node _T_453 = or(_T_452, _T_443)
node _T_454 = or(_T_453, _T_444)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_454
node _T_455 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_456 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_457 = and(_T_455, _T_456)
node _T_458 = or(UInt<1>(0h0), _T_457)
node _T_459 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_460 = cvt(_T_459)
node _T_461 = and(_T_460, asSInt(UInt<13>(0h1000)))
node _T_462 = asSInt(_T_461)
node _T_463 = eq(_T_462, asSInt(UInt<1>(0h0)))
node _T_464 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_465 = cvt(_T_464)
node _T_466 = and(_T_465, asSInt(UInt<13>(0h1000)))
node _T_467 = asSInt(_T_466)
node _T_468 = eq(_T_467, asSInt(UInt<1>(0h0)))
node _T_469 = or(_T_463, _T_468)
node _T_470 = and(_T_458, _T_469)
node _T_471 = or(UInt<1>(0h0), _T_470)
node _T_472 = and(_WIRE_3, _T_471)
node _T_473 = asUInt(reset)
node _T_474 = eq(_T_473, UInt<1>(0h0))
when _T_474 :
node _T_475 = eq(_T_472, UInt<1>(0h0))
when _T_475 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_472, UInt<1>(0h1), "") : assert_11
node _T_476 = asUInt(reset)
node _T_477 = eq(_T_476, UInt<1>(0h0))
when _T_477 :
node _T_478 = eq(source_ok, UInt<1>(0h0))
when _T_478 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_479 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_480 = asUInt(reset)
node _T_481 = eq(_T_480, UInt<1>(0h0))
when _T_481 :
node _T_482 = eq(_T_479, UInt<1>(0h0))
when _T_482 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_479, UInt<1>(0h1), "") : assert_13
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(is_aligned, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_486 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_486, UInt<1>(0h1), "") : assert_15
node _T_490 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_491 = asUInt(reset)
node _T_492 = eq(_T_491, UInt<1>(0h0))
when _T_492 :
node _T_493 = eq(_T_490, UInt<1>(0h0))
when _T_493 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_490, UInt<1>(0h1), "") : assert_16
node _T_494 = not(io.in.a.bits.mask)
node _T_495 = eq(_T_494, UInt<1>(0h0))
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_T_495, UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_495, UInt<1>(0h1), "") : assert_17
node _T_499 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_499, UInt<1>(0h1), "") : assert_18
node _T_503 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_503 :
node _T_504 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_505 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_506 = and(_T_504, _T_505)
node _T_507 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_508 = shr(io.in.a.bits.source, 2)
node _T_509 = eq(_T_508, UInt<6>(0h20))
node _T_510 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_511 = and(_T_509, _T_510)
node _T_512 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_513 = and(_T_511, _T_512)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_514 = shr(io.in.a.bits.source, 2)
node _T_515 = eq(_T_514, UInt<6>(0h21))
node _T_516 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_517 = and(_T_515, _T_516)
node _T_518 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_519 = and(_T_517, _T_518)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_520 = shr(io.in.a.bits.source, 2)
node _T_521 = eq(_T_520, UInt<6>(0h22))
node _T_522 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_523 = and(_T_521, _T_522)
node _T_524 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_525 = and(_T_523, _T_524)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_526 = shr(io.in.a.bits.source, 2)
node _T_527 = eq(_T_526, UInt<6>(0h23))
node _T_528 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_529 = and(_T_527, _T_528)
node _T_530 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_531 = and(_T_529, _T_530)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 5, 0)
node _T_532 = shr(io.in.a.bits.source, 6)
node _T_533 = eq(_T_532, UInt<1>(0h1))
node _T_534 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_535 = and(_T_533, _T_534)
node _T_536 = leq(uncommonBits_34, UInt<6>(0h3f))
node _T_537 = and(_T_535, _T_536)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 5, 0)
node _T_538 = shr(io.in.a.bits.source, 6)
node _T_539 = eq(_T_538, UInt<1>(0h0))
node _T_540 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_541 = and(_T_539, _T_540)
node _T_542 = leq(uncommonBits_35, UInt<6>(0h3f))
node _T_543 = and(_T_541, _T_542)
node _T_544 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_545 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_546 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_547 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_548 = or(_T_507, _T_513)
node _T_549 = or(_T_548, _T_519)
node _T_550 = or(_T_549, _T_525)
node _T_551 = or(_T_550, _T_531)
node _T_552 = or(_T_551, _T_537)
node _T_553 = or(_T_552, _T_543)
node _T_554 = or(_T_553, _T_544)
node _T_555 = or(_T_554, _T_545)
node _T_556 = or(_T_555, _T_546)
node _T_557 = or(_T_556, _T_547)
node _T_558 = and(_T_506, _T_557)
node _T_559 = or(UInt<1>(0h0), _T_558)
node _T_560 = asUInt(reset)
node _T_561 = eq(_T_560, UInt<1>(0h0))
when _T_561 :
node _T_562 = eq(_T_559, UInt<1>(0h0))
when _T_562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_559, UInt<1>(0h1), "") : assert_19
node _T_563 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_564 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_565 = and(_T_563, _T_564)
node _T_566 = or(UInt<1>(0h0), _T_565)
node _T_567 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_568 = cvt(_T_567)
node _T_569 = and(_T_568, asSInt(UInt<13>(0h1000)))
node _T_570 = asSInt(_T_569)
node _T_571 = eq(_T_570, asSInt(UInt<1>(0h0)))
node _T_572 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_573 = cvt(_T_572)
node _T_574 = and(_T_573, asSInt(UInt<13>(0h1000)))
node _T_575 = asSInt(_T_574)
node _T_576 = eq(_T_575, asSInt(UInt<1>(0h0)))
node _T_577 = or(_T_571, _T_576)
node _T_578 = and(_T_566, _T_577)
node _T_579 = or(UInt<1>(0h0), _T_578)
node _T_580 = asUInt(reset)
node _T_581 = eq(_T_580, UInt<1>(0h0))
when _T_581 :
node _T_582 = eq(_T_579, UInt<1>(0h0))
when _T_582 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_579, UInt<1>(0h1), "") : assert_20
node _T_583 = asUInt(reset)
node _T_584 = eq(_T_583, UInt<1>(0h0))
when _T_584 :
node _T_585 = eq(source_ok, UInt<1>(0h0))
when _T_585 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_586 = asUInt(reset)
node _T_587 = eq(_T_586, UInt<1>(0h0))
when _T_587 :
node _T_588 = eq(is_aligned, UInt<1>(0h0))
when _T_588 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_589 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_590 = asUInt(reset)
node _T_591 = eq(_T_590, UInt<1>(0h0))
when _T_591 :
node _T_592 = eq(_T_589, UInt<1>(0h0))
when _T_592 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_589, UInt<1>(0h1), "") : assert_23
node _T_593 = eq(io.in.a.bits.mask, mask)
node _T_594 = asUInt(reset)
node _T_595 = eq(_T_594, UInt<1>(0h0))
when _T_595 :
node _T_596 = eq(_T_593, UInt<1>(0h0))
when _T_596 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_593, UInt<1>(0h1), "") : assert_24
node _T_597 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_598 = asUInt(reset)
node _T_599 = eq(_T_598, UInt<1>(0h0))
when _T_599 :
node _T_600 = eq(_T_597, UInt<1>(0h0))
when _T_600 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_597, UInt<1>(0h1), "") : assert_25
node _T_601 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_601 :
node _T_602 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_603 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_604 = and(_T_602, _T_603)
node _T_605 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_606 = shr(io.in.a.bits.source, 2)
node _T_607 = eq(_T_606, UInt<6>(0h20))
node _T_608 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_609 = and(_T_607, _T_608)
node _T_610 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_611 = and(_T_609, _T_610)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_612 = shr(io.in.a.bits.source, 2)
node _T_613 = eq(_T_612, UInt<6>(0h21))
node _T_614 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_615 = and(_T_613, _T_614)
node _T_616 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_617 = and(_T_615, _T_616)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_618 = shr(io.in.a.bits.source, 2)
node _T_619 = eq(_T_618, UInt<6>(0h22))
node _T_620 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_621 = and(_T_619, _T_620)
node _T_622 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_623 = and(_T_621, _T_622)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_624 = shr(io.in.a.bits.source, 2)
node _T_625 = eq(_T_624, UInt<6>(0h23))
node _T_626 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_627 = and(_T_625, _T_626)
node _T_628 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_629 = and(_T_627, _T_628)
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 5, 0)
node _T_630 = shr(io.in.a.bits.source, 6)
node _T_631 = eq(_T_630, UInt<1>(0h1))
node _T_632 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_633 = and(_T_631, _T_632)
node _T_634 = leq(uncommonBits_40, UInt<6>(0h3f))
node _T_635 = and(_T_633, _T_634)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 5, 0)
node _T_636 = shr(io.in.a.bits.source, 6)
node _T_637 = eq(_T_636, UInt<1>(0h0))
node _T_638 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_639 = and(_T_637, _T_638)
node _T_640 = leq(uncommonBits_41, UInt<6>(0h3f))
node _T_641 = and(_T_639, _T_640)
node _T_642 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_643 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_644 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_645 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_646 = or(_T_605, _T_611)
node _T_647 = or(_T_646, _T_617)
node _T_648 = or(_T_647, _T_623)
node _T_649 = or(_T_648, _T_629)
node _T_650 = or(_T_649, _T_635)
node _T_651 = or(_T_650, _T_641)
node _T_652 = or(_T_651, _T_642)
node _T_653 = or(_T_652, _T_643)
node _T_654 = or(_T_653, _T_644)
node _T_655 = or(_T_654, _T_645)
node _T_656 = and(_T_604, _T_655)
node _T_657 = or(UInt<1>(0h0), _T_656)
node _T_658 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_659 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_660 = and(_T_658, _T_659)
node _T_661 = or(UInt<1>(0h0), _T_660)
node _T_662 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_663 = cvt(_T_662)
node _T_664 = and(_T_663, asSInt(UInt<13>(0h1000)))
node _T_665 = asSInt(_T_664)
node _T_666 = eq(_T_665, asSInt(UInt<1>(0h0)))
node _T_667 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_668 = cvt(_T_667)
node _T_669 = and(_T_668, asSInt(UInt<13>(0h1000)))
node _T_670 = asSInt(_T_669)
node _T_671 = eq(_T_670, asSInt(UInt<1>(0h0)))
node _T_672 = or(_T_666, _T_671)
node _T_673 = and(_T_661, _T_672)
node _T_674 = or(UInt<1>(0h0), _T_673)
node _T_675 = and(_T_657, _T_674)
node _T_676 = asUInt(reset)
node _T_677 = eq(_T_676, UInt<1>(0h0))
when _T_677 :
node _T_678 = eq(_T_675, UInt<1>(0h0))
when _T_678 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_675, UInt<1>(0h1), "") : assert_26
node _T_679 = asUInt(reset)
node _T_680 = eq(_T_679, UInt<1>(0h0))
when _T_680 :
node _T_681 = eq(source_ok, UInt<1>(0h0))
when _T_681 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_682 = asUInt(reset)
node _T_683 = eq(_T_682, UInt<1>(0h0))
when _T_683 :
node _T_684 = eq(is_aligned, UInt<1>(0h0))
when _T_684 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_685 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_686 = asUInt(reset)
node _T_687 = eq(_T_686, UInt<1>(0h0))
when _T_687 :
node _T_688 = eq(_T_685, UInt<1>(0h0))
when _T_688 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_685, UInt<1>(0h1), "") : assert_29
node _T_689 = eq(io.in.a.bits.mask, mask)
node _T_690 = asUInt(reset)
node _T_691 = eq(_T_690, UInt<1>(0h0))
when _T_691 :
node _T_692 = eq(_T_689, UInt<1>(0h0))
when _T_692 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_689, UInt<1>(0h1), "") : assert_30
node _T_693 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_693 :
node _T_694 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_695 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_696 = and(_T_694, _T_695)
node _T_697 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_698 = shr(io.in.a.bits.source, 2)
node _T_699 = eq(_T_698, UInt<6>(0h20))
node _T_700 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_701 = and(_T_699, _T_700)
node _T_702 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_703 = and(_T_701, _T_702)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_704 = shr(io.in.a.bits.source, 2)
node _T_705 = eq(_T_704, UInt<6>(0h21))
node _T_706 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_707 = and(_T_705, _T_706)
node _T_708 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_709 = and(_T_707, _T_708)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_710 = shr(io.in.a.bits.source, 2)
node _T_711 = eq(_T_710, UInt<6>(0h22))
node _T_712 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_713 = and(_T_711, _T_712)
node _T_714 = leq(uncommonBits_44, UInt<2>(0h3))
node _T_715 = and(_T_713, _T_714)
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_716 = shr(io.in.a.bits.source, 2)
node _T_717 = eq(_T_716, UInt<6>(0h23))
node _T_718 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_719 = and(_T_717, _T_718)
node _T_720 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_721 = and(_T_719, _T_720)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 5, 0)
node _T_722 = shr(io.in.a.bits.source, 6)
node _T_723 = eq(_T_722, UInt<1>(0h1))
node _T_724 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_725 = and(_T_723, _T_724)
node _T_726 = leq(uncommonBits_46, UInt<6>(0h3f))
node _T_727 = and(_T_725, _T_726)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 5, 0)
node _T_728 = shr(io.in.a.bits.source, 6)
node _T_729 = eq(_T_728, UInt<1>(0h0))
node _T_730 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_731 = and(_T_729, _T_730)
node _T_732 = leq(uncommonBits_47, UInt<6>(0h3f))
node _T_733 = and(_T_731, _T_732)
node _T_734 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_735 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_736 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_737 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_738 = or(_T_697, _T_703)
node _T_739 = or(_T_738, _T_709)
node _T_740 = or(_T_739, _T_715)
node _T_741 = or(_T_740, _T_721)
node _T_742 = or(_T_741, _T_727)
node _T_743 = or(_T_742, _T_733)
node _T_744 = or(_T_743, _T_734)
node _T_745 = or(_T_744, _T_735)
node _T_746 = or(_T_745, _T_736)
node _T_747 = or(_T_746, _T_737)
node _T_748 = and(_T_696, _T_747)
node _T_749 = or(UInt<1>(0h0), _T_748)
node _T_750 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_751 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_752 = and(_T_750, _T_751)
node _T_753 = or(UInt<1>(0h0), _T_752)
node _T_754 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_755 = cvt(_T_754)
node _T_756 = and(_T_755, asSInt(UInt<13>(0h1000)))
node _T_757 = asSInt(_T_756)
node _T_758 = eq(_T_757, asSInt(UInt<1>(0h0)))
node _T_759 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_760 = cvt(_T_759)
node _T_761 = and(_T_760, asSInt(UInt<13>(0h1000)))
node _T_762 = asSInt(_T_761)
node _T_763 = eq(_T_762, asSInt(UInt<1>(0h0)))
node _T_764 = or(_T_758, _T_763)
node _T_765 = and(_T_753, _T_764)
node _T_766 = or(UInt<1>(0h0), _T_765)
node _T_767 = and(_T_749, _T_766)
node _T_768 = asUInt(reset)
node _T_769 = eq(_T_768, UInt<1>(0h0))
when _T_769 :
node _T_770 = eq(_T_767, UInt<1>(0h0))
when _T_770 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_767, UInt<1>(0h1), "") : assert_31
node _T_771 = asUInt(reset)
node _T_772 = eq(_T_771, UInt<1>(0h0))
when _T_772 :
node _T_773 = eq(source_ok, UInt<1>(0h0))
when _T_773 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_774 = asUInt(reset)
node _T_775 = eq(_T_774, UInt<1>(0h0))
when _T_775 :
node _T_776 = eq(is_aligned, UInt<1>(0h0))
when _T_776 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_777 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_778 = asUInt(reset)
node _T_779 = eq(_T_778, UInt<1>(0h0))
when _T_779 :
node _T_780 = eq(_T_777, UInt<1>(0h0))
when _T_780 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_777, UInt<1>(0h1), "") : assert_34
node _T_781 = not(mask)
node _T_782 = and(io.in.a.bits.mask, _T_781)
node _T_783 = eq(_T_782, UInt<1>(0h0))
node _T_784 = asUInt(reset)
node _T_785 = eq(_T_784, UInt<1>(0h0))
when _T_785 :
node _T_786 = eq(_T_783, UInt<1>(0h0))
when _T_786 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_783, UInt<1>(0h1), "") : assert_35
node _T_787 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_787 :
node _T_788 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_789 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_790 = and(_T_788, _T_789)
node _T_791 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0)
node _T_792 = shr(io.in.a.bits.source, 2)
node _T_793 = eq(_T_792, UInt<6>(0h20))
node _T_794 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_795 = and(_T_793, _T_794)
node _T_796 = leq(uncommonBits_48, UInt<2>(0h3))
node _T_797 = and(_T_795, _T_796)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0)
node _T_798 = shr(io.in.a.bits.source, 2)
node _T_799 = eq(_T_798, UInt<6>(0h21))
node _T_800 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_801 = and(_T_799, _T_800)
node _T_802 = leq(uncommonBits_49, UInt<2>(0h3))
node _T_803 = and(_T_801, _T_802)
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_804 = shr(io.in.a.bits.source, 2)
node _T_805 = eq(_T_804, UInt<6>(0h22))
node _T_806 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_807 = and(_T_805, _T_806)
node _T_808 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_809 = and(_T_807, _T_808)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_810 = shr(io.in.a.bits.source, 2)
node _T_811 = eq(_T_810, UInt<6>(0h23))
node _T_812 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_813 = and(_T_811, _T_812)
node _T_814 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_815 = and(_T_813, _T_814)
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 5, 0)
node _T_816 = shr(io.in.a.bits.source, 6)
node _T_817 = eq(_T_816, UInt<1>(0h1))
node _T_818 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_819 = and(_T_817, _T_818)
node _T_820 = leq(uncommonBits_52, UInt<6>(0h3f))
node _T_821 = and(_T_819, _T_820)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 5, 0)
node _T_822 = shr(io.in.a.bits.source, 6)
node _T_823 = eq(_T_822, UInt<1>(0h0))
node _T_824 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_825 = and(_T_823, _T_824)
node _T_826 = leq(uncommonBits_53, UInt<6>(0h3f))
node _T_827 = and(_T_825, _T_826)
node _T_828 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_829 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_830 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_831 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_832 = or(_T_791, _T_797)
node _T_833 = or(_T_832, _T_803)
node _T_834 = or(_T_833, _T_809)
node _T_835 = or(_T_834, _T_815)
node _T_836 = or(_T_835, _T_821)
node _T_837 = or(_T_836, _T_827)
node _T_838 = or(_T_837, _T_828)
node _T_839 = or(_T_838, _T_829)
node _T_840 = or(_T_839, _T_830)
node _T_841 = or(_T_840, _T_831)
node _T_842 = and(_T_790, _T_841)
node _T_843 = or(UInt<1>(0h0), _T_842)
node _T_844 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_845 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_846 = and(_T_844, _T_845)
node _T_847 = or(UInt<1>(0h0), _T_846)
node _T_848 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_849 = cvt(_T_848)
node _T_850 = and(_T_849, asSInt(UInt<13>(0h1000)))
node _T_851 = asSInt(_T_850)
node _T_852 = eq(_T_851, asSInt(UInt<1>(0h0)))
node _T_853 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_854 = cvt(_T_853)
node _T_855 = and(_T_854, asSInt(UInt<13>(0h1000)))
node _T_856 = asSInt(_T_855)
node _T_857 = eq(_T_856, asSInt(UInt<1>(0h0)))
node _T_858 = or(_T_852, _T_857)
node _T_859 = and(_T_847, _T_858)
node _T_860 = or(UInt<1>(0h0), _T_859)
node _T_861 = and(_T_843, _T_860)
node _T_862 = asUInt(reset)
node _T_863 = eq(_T_862, UInt<1>(0h0))
when _T_863 :
node _T_864 = eq(_T_861, UInt<1>(0h0))
when _T_864 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_861, UInt<1>(0h1), "") : assert_36
node _T_865 = asUInt(reset)
node _T_866 = eq(_T_865, UInt<1>(0h0))
when _T_866 :
node _T_867 = eq(source_ok, UInt<1>(0h0))
when _T_867 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_868 = asUInt(reset)
node _T_869 = eq(_T_868, UInt<1>(0h0))
when _T_869 :
node _T_870 = eq(is_aligned, UInt<1>(0h0))
when _T_870 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_871 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_872 = asUInt(reset)
node _T_873 = eq(_T_872, UInt<1>(0h0))
when _T_873 :
node _T_874 = eq(_T_871, UInt<1>(0h0))
when _T_874 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_871, UInt<1>(0h1), "") : assert_39
node _T_875 = eq(io.in.a.bits.mask, mask)
node _T_876 = asUInt(reset)
node _T_877 = eq(_T_876, UInt<1>(0h0))
when _T_877 :
node _T_878 = eq(_T_875, UInt<1>(0h0))
when _T_878 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_875, UInt<1>(0h1), "") : assert_40
node _T_879 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_879 :
node _T_880 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_881 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_882 = and(_T_880, _T_881)
node _T_883 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0)
node _T_884 = shr(io.in.a.bits.source, 2)
node _T_885 = eq(_T_884, UInt<6>(0h20))
node _T_886 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_887 = and(_T_885, _T_886)
node _T_888 = leq(uncommonBits_54, UInt<2>(0h3))
node _T_889 = and(_T_887, _T_888)
node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0)
node _T_890 = shr(io.in.a.bits.source, 2)
node _T_891 = eq(_T_890, UInt<6>(0h21))
node _T_892 = leq(UInt<1>(0h0), uncommonBits_55)
node _T_893 = and(_T_891, _T_892)
node _T_894 = leq(uncommonBits_55, UInt<2>(0h3))
node _T_895 = and(_T_893, _T_894)
node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0)
node _T_896 = shr(io.in.a.bits.source, 2)
node _T_897 = eq(_T_896, UInt<6>(0h22))
node _T_898 = leq(UInt<1>(0h0), uncommonBits_56)
node _T_899 = and(_T_897, _T_898)
node _T_900 = leq(uncommonBits_56, UInt<2>(0h3))
node _T_901 = and(_T_899, _T_900)
node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0)
node _T_902 = shr(io.in.a.bits.source, 2)
node _T_903 = eq(_T_902, UInt<6>(0h23))
node _T_904 = leq(UInt<1>(0h0), uncommonBits_57)
node _T_905 = and(_T_903, _T_904)
node _T_906 = leq(uncommonBits_57, UInt<2>(0h3))
node _T_907 = and(_T_905, _T_906)
node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_58 = bits(_uncommonBits_T_58, 5, 0)
node _T_908 = shr(io.in.a.bits.source, 6)
node _T_909 = eq(_T_908, UInt<1>(0h1))
node _T_910 = leq(UInt<1>(0h0), uncommonBits_58)
node _T_911 = and(_T_909, _T_910)
node _T_912 = leq(uncommonBits_58, UInt<6>(0h3f))
node _T_913 = and(_T_911, _T_912)
node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_59 = bits(_uncommonBits_T_59, 5, 0)
node _T_914 = shr(io.in.a.bits.source, 6)
node _T_915 = eq(_T_914, UInt<1>(0h0))
node _T_916 = leq(UInt<1>(0h0), uncommonBits_59)
node _T_917 = and(_T_915, _T_916)
node _T_918 = leq(uncommonBits_59, UInt<6>(0h3f))
node _T_919 = and(_T_917, _T_918)
node _T_920 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_921 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_922 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_923 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_924 = or(_T_883, _T_889)
node _T_925 = or(_T_924, _T_895)
node _T_926 = or(_T_925, _T_901)
node _T_927 = or(_T_926, _T_907)
node _T_928 = or(_T_927, _T_913)
node _T_929 = or(_T_928, _T_919)
node _T_930 = or(_T_929, _T_920)
node _T_931 = or(_T_930, _T_921)
node _T_932 = or(_T_931, _T_922)
node _T_933 = or(_T_932, _T_923)
node _T_934 = and(_T_882, _T_933)
node _T_935 = or(UInt<1>(0h0), _T_934)
node _T_936 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_937 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_938 = and(_T_936, _T_937)
node _T_939 = or(UInt<1>(0h0), _T_938)
node _T_940 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_941 = cvt(_T_940)
node _T_942 = and(_T_941, asSInt(UInt<13>(0h1000)))
node _T_943 = asSInt(_T_942)
node _T_944 = eq(_T_943, asSInt(UInt<1>(0h0)))
node _T_945 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_946 = cvt(_T_945)
node _T_947 = and(_T_946, asSInt(UInt<13>(0h1000)))
node _T_948 = asSInt(_T_947)
node _T_949 = eq(_T_948, asSInt(UInt<1>(0h0)))
node _T_950 = or(_T_944, _T_949)
node _T_951 = and(_T_939, _T_950)
node _T_952 = or(UInt<1>(0h0), _T_951)
node _T_953 = and(_T_935, _T_952)
node _T_954 = asUInt(reset)
node _T_955 = eq(_T_954, UInt<1>(0h0))
when _T_955 :
node _T_956 = eq(_T_953, UInt<1>(0h0))
when _T_956 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_953, UInt<1>(0h1), "") : assert_41
node _T_957 = asUInt(reset)
node _T_958 = eq(_T_957, UInt<1>(0h0))
when _T_958 :
node _T_959 = eq(source_ok, UInt<1>(0h0))
when _T_959 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_960 = asUInt(reset)
node _T_961 = eq(_T_960, UInt<1>(0h0))
when _T_961 :
node _T_962 = eq(is_aligned, UInt<1>(0h0))
when _T_962 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_963 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_964 = asUInt(reset)
node _T_965 = eq(_T_964, UInt<1>(0h0))
when _T_965 :
node _T_966 = eq(_T_963, UInt<1>(0h0))
when _T_966 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_963, UInt<1>(0h1), "") : assert_44
node _T_967 = eq(io.in.a.bits.mask, mask)
node _T_968 = asUInt(reset)
node _T_969 = eq(_T_968, UInt<1>(0h0))
when _T_969 :
node _T_970 = eq(_T_967, UInt<1>(0h0))
when _T_970 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_967, UInt<1>(0h1), "") : assert_45
node _T_971 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_971 :
node _T_972 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_973 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_974 = and(_T_972, _T_973)
node _T_975 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0)
node _T_976 = shr(io.in.a.bits.source, 2)
node _T_977 = eq(_T_976, UInt<6>(0h20))
node _T_978 = leq(UInt<1>(0h0), uncommonBits_60)
node _T_979 = and(_T_977, _T_978)
node _T_980 = leq(uncommonBits_60, UInt<2>(0h3))
node _T_981 = and(_T_979, _T_980)
node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0)
node _T_982 = shr(io.in.a.bits.source, 2)
node _T_983 = eq(_T_982, UInt<6>(0h21))
node _T_984 = leq(UInt<1>(0h0), uncommonBits_61)
node _T_985 = and(_T_983, _T_984)
node _T_986 = leq(uncommonBits_61, UInt<2>(0h3))
node _T_987 = and(_T_985, _T_986)
node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0)
node _T_988 = shr(io.in.a.bits.source, 2)
node _T_989 = eq(_T_988, UInt<6>(0h22))
node _T_990 = leq(UInt<1>(0h0), uncommonBits_62)
node _T_991 = and(_T_989, _T_990)
node _T_992 = leq(uncommonBits_62, UInt<2>(0h3))
node _T_993 = and(_T_991, _T_992)
node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0)
node _T_994 = shr(io.in.a.bits.source, 2)
node _T_995 = eq(_T_994, UInt<6>(0h23))
node _T_996 = leq(UInt<1>(0h0), uncommonBits_63)
node _T_997 = and(_T_995, _T_996)
node _T_998 = leq(uncommonBits_63, UInt<2>(0h3))
node _T_999 = and(_T_997, _T_998)
node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_64 = bits(_uncommonBits_T_64, 5, 0)
node _T_1000 = shr(io.in.a.bits.source, 6)
node _T_1001 = eq(_T_1000, UInt<1>(0h1))
node _T_1002 = leq(UInt<1>(0h0), uncommonBits_64)
node _T_1003 = and(_T_1001, _T_1002)
node _T_1004 = leq(uncommonBits_64, UInt<6>(0h3f))
node _T_1005 = and(_T_1003, _T_1004)
node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_65 = bits(_uncommonBits_T_65, 5, 0)
node _T_1006 = shr(io.in.a.bits.source, 6)
node _T_1007 = eq(_T_1006, UInt<1>(0h0))
node _T_1008 = leq(UInt<1>(0h0), uncommonBits_65)
node _T_1009 = and(_T_1007, _T_1008)
node _T_1010 = leq(uncommonBits_65, UInt<6>(0h3f))
node _T_1011 = and(_T_1009, _T_1010)
node _T_1012 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_1013 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_1014 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_1015 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_1016 = or(_T_975, _T_981)
node _T_1017 = or(_T_1016, _T_987)
node _T_1018 = or(_T_1017, _T_993)
node _T_1019 = or(_T_1018, _T_999)
node _T_1020 = or(_T_1019, _T_1005)
node _T_1021 = or(_T_1020, _T_1011)
node _T_1022 = or(_T_1021, _T_1012)
node _T_1023 = or(_T_1022, _T_1013)
node _T_1024 = or(_T_1023, _T_1014)
node _T_1025 = or(_T_1024, _T_1015)
node _T_1026 = and(_T_974, _T_1025)
node _T_1027 = or(UInt<1>(0h0), _T_1026)
node _T_1028 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1029 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_1030 = cvt(_T_1029)
node _T_1031 = and(_T_1030, asSInt(UInt<13>(0h1000)))
node _T_1032 = asSInt(_T_1031)
node _T_1033 = eq(_T_1032, asSInt(UInt<1>(0h0)))
node _T_1034 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1035 = cvt(_T_1034)
node _T_1036 = and(_T_1035, asSInt(UInt<13>(0h1000)))
node _T_1037 = asSInt(_T_1036)
node _T_1038 = eq(_T_1037, asSInt(UInt<1>(0h0)))
node _T_1039 = or(_T_1033, _T_1038)
node _T_1040 = and(_T_1028, _T_1039)
node _T_1041 = or(UInt<1>(0h0), _T_1040)
node _T_1042 = and(_T_1027, _T_1041)
node _T_1043 = asUInt(reset)
node _T_1044 = eq(_T_1043, UInt<1>(0h0))
when _T_1044 :
node _T_1045 = eq(_T_1042, UInt<1>(0h0))
when _T_1045 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1042, UInt<1>(0h1), "") : assert_46
node _T_1046 = asUInt(reset)
node _T_1047 = eq(_T_1046, UInt<1>(0h0))
when _T_1047 :
node _T_1048 = eq(source_ok, UInt<1>(0h0))
when _T_1048 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1049 = asUInt(reset)
node _T_1050 = eq(_T_1049, UInt<1>(0h0))
when _T_1050 :
node _T_1051 = eq(is_aligned, UInt<1>(0h0))
when _T_1051 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1052 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1053 = asUInt(reset)
node _T_1054 = eq(_T_1053, UInt<1>(0h0))
when _T_1054 :
node _T_1055 = eq(_T_1052, UInt<1>(0h0))
when _T_1055 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1052, UInt<1>(0h1), "") : assert_49
node _T_1056 = eq(io.in.a.bits.mask, mask)
node _T_1057 = asUInt(reset)
node _T_1058 = eq(_T_1057, UInt<1>(0h0))
when _T_1058 :
node _T_1059 = eq(_T_1056, UInt<1>(0h0))
when _T_1059 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1056, UInt<1>(0h1), "") : assert_50
node _T_1060 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1061 = asUInt(reset)
node _T_1062 = eq(_T_1061, UInt<1>(0h0))
when _T_1062 :
node _T_1063 = eq(_T_1060, UInt<1>(0h0))
when _T_1063 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1060, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1064 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1065 = asUInt(reset)
node _T_1066 = eq(_T_1065, UInt<1>(0h0))
when _T_1066 :
node _T_1067 = eq(_T_1064, UInt<1>(0h0))
when _T_1067 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1064, UInt<1>(0h1), "") : assert_52
node _source_ok_T_50 = eq(io.in.d.bits.source, UInt<8>(0h90))
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_51 = shr(io.in.d.bits.source, 2)
node _source_ok_T_52 = eq(_source_ok_T_51, UInt<6>(0h20))
node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53)
node _source_ok_T_55 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_57 = shr(io.in.d.bits.source, 2)
node _source_ok_T_58 = eq(_source_ok_T_57, UInt<6>(0h21))
node _source_ok_T_59 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59)
node _source_ok_T_61 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_63 = shr(io.in.d.bits.source, 2)
node _source_ok_T_64 = eq(_source_ok_T_63, UInt<6>(0h22))
node _source_ok_T_65 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65)
node _source_ok_T_67 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0)
node _source_ok_T_69 = shr(io.in.d.bits.source, 2)
node _source_ok_T_70 = eq(_source_ok_T_69, UInt<6>(0h23))
node _source_ok_T_71 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71)
node _source_ok_T_73 = leq(source_ok_uncommonBits_9, UInt<2>(0h3))
node _source_ok_T_74 = and(_source_ok_T_72, _source_ok_T_73)
node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 5, 0)
node _source_ok_T_75 = shr(io.in.d.bits.source, 6)
node _source_ok_T_76 = eq(_source_ok_T_75, UInt<1>(0h1))
node _source_ok_T_77 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_78 = and(_source_ok_T_76, _source_ok_T_77)
node _source_ok_T_79 = leq(source_ok_uncommonBits_10, UInt<6>(0h3f))
node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79)
node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 5, 0)
node _source_ok_T_81 = shr(io.in.d.bits.source, 6)
node _source_ok_T_82 = eq(_source_ok_T_81, UInt<1>(0h0))
node _source_ok_T_83 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83)
node _source_ok_T_85 = leq(source_ok_uncommonBits_11, UInt<6>(0h3f))
node _source_ok_T_86 = and(_source_ok_T_84, _source_ok_T_85)
node _source_ok_T_87 = eq(io.in.d.bits.source, UInt<8>(0ha0))
node _source_ok_T_88 = eq(io.in.d.bits.source, UInt<8>(0ha1))
node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<8>(0ha2))
node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<9>(0h100))
wire _source_ok_WIRE_1 : UInt<1>[11]
connect _source_ok_WIRE_1[0], _source_ok_T_50
connect _source_ok_WIRE_1[1], _source_ok_T_56
connect _source_ok_WIRE_1[2], _source_ok_T_62
connect _source_ok_WIRE_1[3], _source_ok_T_68
connect _source_ok_WIRE_1[4], _source_ok_T_74
connect _source_ok_WIRE_1[5], _source_ok_T_80
connect _source_ok_WIRE_1[6], _source_ok_T_86
connect _source_ok_WIRE_1[7], _source_ok_T_87
connect _source_ok_WIRE_1[8], _source_ok_T_88
connect _source_ok_WIRE_1[9], _source_ok_T_89
connect _source_ok_WIRE_1[10], _source_ok_T_90
node _source_ok_T_91 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE_1[2])
node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE_1[3])
node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE_1[4])
node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE_1[5])
node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE_1[6])
node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE_1[7])
node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE_1[8])
node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE_1[9])
node source_ok_1 = or(_source_ok_T_99, _source_ok_WIRE_1[10])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1068 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1068 :
node _T_1069 = asUInt(reset)
node _T_1070 = eq(_T_1069, UInt<1>(0h0))
when _T_1070 :
node _T_1071 = eq(source_ok_1, UInt<1>(0h0))
when _T_1071 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1072 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1073 = asUInt(reset)
node _T_1074 = eq(_T_1073, UInt<1>(0h0))
when _T_1074 :
node _T_1075 = eq(_T_1072, UInt<1>(0h0))
when _T_1075 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1072, UInt<1>(0h1), "") : assert_54
node _T_1076 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1077 = asUInt(reset)
node _T_1078 = eq(_T_1077, UInt<1>(0h0))
when _T_1078 :
node _T_1079 = eq(_T_1076, UInt<1>(0h0))
when _T_1079 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1076, UInt<1>(0h1), "") : assert_55
node _T_1080 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1081 = asUInt(reset)
node _T_1082 = eq(_T_1081, UInt<1>(0h0))
when _T_1082 :
node _T_1083 = eq(_T_1080, UInt<1>(0h0))
when _T_1083 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1080, UInt<1>(0h1), "") : assert_56
node _T_1084 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1085 = asUInt(reset)
node _T_1086 = eq(_T_1085, UInt<1>(0h0))
when _T_1086 :
node _T_1087 = eq(_T_1084, UInt<1>(0h0))
when _T_1087 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1084, UInt<1>(0h1), "") : assert_57
node _T_1088 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1088 :
node _T_1089 = asUInt(reset)
node _T_1090 = eq(_T_1089, UInt<1>(0h0))
when _T_1090 :
node _T_1091 = eq(source_ok_1, UInt<1>(0h0))
when _T_1091 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1092 = asUInt(reset)
node _T_1093 = eq(_T_1092, UInt<1>(0h0))
when _T_1093 :
node _T_1094 = eq(sink_ok, UInt<1>(0h0))
when _T_1094 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1095 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1096 = asUInt(reset)
node _T_1097 = eq(_T_1096, UInt<1>(0h0))
when _T_1097 :
node _T_1098 = eq(_T_1095, UInt<1>(0h0))
when _T_1098 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1095, UInt<1>(0h1), "") : assert_60
node _T_1099 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1100 = asUInt(reset)
node _T_1101 = eq(_T_1100, UInt<1>(0h0))
when _T_1101 :
node _T_1102 = eq(_T_1099, UInt<1>(0h0))
when _T_1102 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1099, UInt<1>(0h1), "") : assert_61
node _T_1103 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1104 = asUInt(reset)
node _T_1105 = eq(_T_1104, UInt<1>(0h0))
when _T_1105 :
node _T_1106 = eq(_T_1103, UInt<1>(0h0))
when _T_1106 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1103, UInt<1>(0h1), "") : assert_62
node _T_1107 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1108 = asUInt(reset)
node _T_1109 = eq(_T_1108, UInt<1>(0h0))
when _T_1109 :
node _T_1110 = eq(_T_1107, UInt<1>(0h0))
when _T_1110 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1107, UInt<1>(0h1), "") : assert_63
node _T_1111 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1112 = or(UInt<1>(0h0), _T_1111)
node _T_1113 = asUInt(reset)
node _T_1114 = eq(_T_1113, UInt<1>(0h0))
when _T_1114 :
node _T_1115 = eq(_T_1112, UInt<1>(0h0))
when _T_1115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1112, UInt<1>(0h1), "") : assert_64
node _T_1116 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1116 :
node _T_1117 = asUInt(reset)
node _T_1118 = eq(_T_1117, UInt<1>(0h0))
when _T_1118 :
node _T_1119 = eq(source_ok_1, UInt<1>(0h0))
when _T_1119 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1120 = asUInt(reset)
node _T_1121 = eq(_T_1120, UInt<1>(0h0))
when _T_1121 :
node _T_1122 = eq(sink_ok, UInt<1>(0h0))
when _T_1122 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1123 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1124 = asUInt(reset)
node _T_1125 = eq(_T_1124, UInt<1>(0h0))
when _T_1125 :
node _T_1126 = eq(_T_1123, UInt<1>(0h0))
when _T_1126 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1123, UInt<1>(0h1), "") : assert_67
node _T_1127 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1128 = asUInt(reset)
node _T_1129 = eq(_T_1128, UInt<1>(0h0))
when _T_1129 :
node _T_1130 = eq(_T_1127, UInt<1>(0h0))
when _T_1130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1127, UInt<1>(0h1), "") : assert_68
node _T_1131 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1132 = asUInt(reset)
node _T_1133 = eq(_T_1132, UInt<1>(0h0))
when _T_1133 :
node _T_1134 = eq(_T_1131, UInt<1>(0h0))
when _T_1134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1131, UInt<1>(0h1), "") : assert_69
node _T_1135 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1136 = or(_T_1135, io.in.d.bits.corrupt)
node _T_1137 = asUInt(reset)
node _T_1138 = eq(_T_1137, UInt<1>(0h0))
when _T_1138 :
node _T_1139 = eq(_T_1136, UInt<1>(0h0))
when _T_1139 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1136, UInt<1>(0h1), "") : assert_70
node _T_1140 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1141 = or(UInt<1>(0h0), _T_1140)
node _T_1142 = asUInt(reset)
node _T_1143 = eq(_T_1142, UInt<1>(0h0))
when _T_1143 :
node _T_1144 = eq(_T_1141, UInt<1>(0h0))
when _T_1144 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1141, UInt<1>(0h1), "") : assert_71
node _T_1145 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1145 :
node _T_1146 = asUInt(reset)
node _T_1147 = eq(_T_1146, UInt<1>(0h0))
when _T_1147 :
node _T_1148 = eq(source_ok_1, UInt<1>(0h0))
when _T_1148 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1149 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1150 = asUInt(reset)
node _T_1151 = eq(_T_1150, UInt<1>(0h0))
when _T_1151 :
node _T_1152 = eq(_T_1149, UInt<1>(0h0))
when _T_1152 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1149, UInt<1>(0h1), "") : assert_73
node _T_1153 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1154 = asUInt(reset)
node _T_1155 = eq(_T_1154, UInt<1>(0h0))
when _T_1155 :
node _T_1156 = eq(_T_1153, UInt<1>(0h0))
when _T_1156 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1153, UInt<1>(0h1), "") : assert_74
node _T_1157 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1158 = or(UInt<1>(0h0), _T_1157)
node _T_1159 = asUInt(reset)
node _T_1160 = eq(_T_1159, UInt<1>(0h0))
when _T_1160 :
node _T_1161 = eq(_T_1158, UInt<1>(0h0))
when _T_1161 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1158, UInt<1>(0h1), "") : assert_75
node _T_1162 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1162 :
node _T_1163 = asUInt(reset)
node _T_1164 = eq(_T_1163, UInt<1>(0h0))
when _T_1164 :
node _T_1165 = eq(source_ok_1, UInt<1>(0h0))
when _T_1165 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1166 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1167 = asUInt(reset)
node _T_1168 = eq(_T_1167, UInt<1>(0h0))
when _T_1168 :
node _T_1169 = eq(_T_1166, UInt<1>(0h0))
when _T_1169 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1166, UInt<1>(0h1), "") : assert_77
node _T_1170 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1171 = or(_T_1170, io.in.d.bits.corrupt)
node _T_1172 = asUInt(reset)
node _T_1173 = eq(_T_1172, UInt<1>(0h0))
when _T_1173 :
node _T_1174 = eq(_T_1171, UInt<1>(0h0))
when _T_1174 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1171, UInt<1>(0h1), "") : assert_78
node _T_1175 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1176 = or(UInt<1>(0h0), _T_1175)
node _T_1177 = asUInt(reset)
node _T_1178 = eq(_T_1177, UInt<1>(0h0))
when _T_1178 :
node _T_1179 = eq(_T_1176, UInt<1>(0h0))
when _T_1179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1176, UInt<1>(0h1), "") : assert_79
node _T_1180 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1180 :
node _T_1181 = asUInt(reset)
node _T_1182 = eq(_T_1181, UInt<1>(0h0))
when _T_1182 :
node _T_1183 = eq(source_ok_1, UInt<1>(0h0))
when _T_1183 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1184 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1185 = asUInt(reset)
node _T_1186 = eq(_T_1185, UInt<1>(0h0))
when _T_1186 :
node _T_1187 = eq(_T_1184, UInt<1>(0h0))
when _T_1187 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1184, UInt<1>(0h1), "") : assert_81
node _T_1188 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1189 = asUInt(reset)
node _T_1190 = eq(_T_1189, UInt<1>(0h0))
when _T_1190 :
node _T_1191 = eq(_T_1188, UInt<1>(0h0))
when _T_1191 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1188, UInt<1>(0h1), "") : assert_82
node _T_1192 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1193 = or(UInt<1>(0h0), _T_1192)
node _T_1194 = asUInt(reset)
node _T_1195 = eq(_T_1194, UInt<1>(0h0))
when _T_1195 :
node _T_1196 = eq(_T_1193, UInt<1>(0h0))
when _T_1196 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1193, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<29>(0h0)
connect _WIRE_4.bits.source, UInt<9>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1197 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1198 = asUInt(reset)
node _T_1199 = eq(_T_1198, UInt<1>(0h0))
when _T_1199 :
node _T_1200 = eq(_T_1197, UInt<1>(0h0))
when _T_1200 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1197, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<9>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1201 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1202 = asUInt(reset)
node _T_1203 = eq(_T_1202, UInt<1>(0h0))
when _T_1203 :
node _T_1204 = eq(_T_1201, UInt<1>(0h0))
when _T_1204 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1201, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1205 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1206 = asUInt(reset)
node _T_1207 = eq(_T_1206, UInt<1>(0h0))
when _T_1207 :
node _T_1208 = eq(_T_1205, UInt<1>(0h0))
when _T_1208 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1205, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1209 = eq(a_first, UInt<1>(0h0))
node _T_1210 = and(io.in.a.valid, _T_1209)
when _T_1210 :
node _T_1211 = eq(io.in.a.bits.opcode, opcode)
node _T_1212 = asUInt(reset)
node _T_1213 = eq(_T_1212, UInt<1>(0h0))
when _T_1213 :
node _T_1214 = eq(_T_1211, UInt<1>(0h0))
when _T_1214 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1211, UInt<1>(0h1), "") : assert_87
node _T_1215 = eq(io.in.a.bits.param, param)
node _T_1216 = asUInt(reset)
node _T_1217 = eq(_T_1216, UInt<1>(0h0))
when _T_1217 :
node _T_1218 = eq(_T_1215, UInt<1>(0h0))
when _T_1218 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1215, UInt<1>(0h1), "") : assert_88
node _T_1219 = eq(io.in.a.bits.size, size)
node _T_1220 = asUInt(reset)
node _T_1221 = eq(_T_1220, UInt<1>(0h0))
when _T_1221 :
node _T_1222 = eq(_T_1219, UInt<1>(0h0))
when _T_1222 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1219, UInt<1>(0h1), "") : assert_89
node _T_1223 = eq(io.in.a.bits.source, source)
node _T_1224 = asUInt(reset)
node _T_1225 = eq(_T_1224, UInt<1>(0h0))
when _T_1225 :
node _T_1226 = eq(_T_1223, UInt<1>(0h0))
when _T_1226 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1223, UInt<1>(0h1), "") : assert_90
node _T_1227 = eq(io.in.a.bits.address, address)
node _T_1228 = asUInt(reset)
node _T_1229 = eq(_T_1228, UInt<1>(0h0))
when _T_1229 :
node _T_1230 = eq(_T_1227, UInt<1>(0h0))
when _T_1230 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1227, UInt<1>(0h1), "") : assert_91
node _T_1231 = and(io.in.a.ready, io.in.a.valid)
node _T_1232 = and(_T_1231, a_first)
when _T_1232 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1233 = eq(d_first, UInt<1>(0h0))
node _T_1234 = and(io.in.d.valid, _T_1233)
when _T_1234 :
node _T_1235 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1236 = asUInt(reset)
node _T_1237 = eq(_T_1236, UInt<1>(0h0))
when _T_1237 :
node _T_1238 = eq(_T_1235, UInt<1>(0h0))
when _T_1238 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1235, UInt<1>(0h1), "") : assert_92
node _T_1239 = eq(io.in.d.bits.param, param_1)
node _T_1240 = asUInt(reset)
node _T_1241 = eq(_T_1240, UInt<1>(0h0))
when _T_1241 :
node _T_1242 = eq(_T_1239, UInt<1>(0h0))
when _T_1242 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1239, UInt<1>(0h1), "") : assert_93
node _T_1243 = eq(io.in.d.bits.size, size_1)
node _T_1244 = asUInt(reset)
node _T_1245 = eq(_T_1244, UInt<1>(0h0))
when _T_1245 :
node _T_1246 = eq(_T_1243, UInt<1>(0h0))
when _T_1246 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1243, UInt<1>(0h1), "") : assert_94
node _T_1247 = eq(io.in.d.bits.source, source_1)
node _T_1248 = asUInt(reset)
node _T_1249 = eq(_T_1248, UInt<1>(0h0))
when _T_1249 :
node _T_1250 = eq(_T_1247, UInt<1>(0h0))
when _T_1250 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1247, UInt<1>(0h1), "") : assert_95
node _T_1251 = eq(io.in.d.bits.sink, sink)
node _T_1252 = asUInt(reset)
node _T_1253 = eq(_T_1252, UInt<1>(0h0))
when _T_1253 :
node _T_1254 = eq(_T_1251, UInt<1>(0h0))
when _T_1254 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1251, UInt<1>(0h1), "") : assert_96
node _T_1255 = eq(io.in.d.bits.denied, denied)
node _T_1256 = asUInt(reset)
node _T_1257 = eq(_T_1256, UInt<1>(0h0))
when _T_1257 :
node _T_1258 = eq(_T_1255, UInt<1>(0h0))
when _T_1258 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1255, UInt<1>(0h1), "") : assert_97
node _T_1259 = and(io.in.d.ready, io.in.d.valid)
node _T_1260 = and(_T_1259, d_first)
when _T_1260 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<257>, clock, reset, UInt<257>(0h0)
regreset inflight_opcodes : UInt<1028>, clock, reset, UInt<1028>(0h0)
regreset inflight_sizes : UInt<1028>, clock, reset, UInt<1028>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<257>
connect a_set, UInt<257>(0h0)
wire a_set_wo_ready : UInt<257>
connect a_set_wo_ready, UInt<257>(0h0)
wire a_opcodes_set : UInt<1028>
connect a_opcodes_set, UInt<1028>(0h0)
wire a_sizes_set : UInt<1028>
connect a_sizes_set, UInt<1028>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1261 = and(io.in.a.valid, a_first_1)
node _T_1262 = and(_T_1261, UInt<1>(0h1))
when _T_1262 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1263 = and(io.in.a.ready, io.in.a.valid)
node _T_1264 = and(_T_1263, a_first_1)
node _T_1265 = and(_T_1264, UInt<1>(0h1))
when _T_1265 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1266 = dshr(inflight, io.in.a.bits.source)
node _T_1267 = bits(_T_1266, 0, 0)
node _T_1268 = eq(_T_1267, UInt<1>(0h0))
node _T_1269 = asUInt(reset)
node _T_1270 = eq(_T_1269, UInt<1>(0h0))
when _T_1270 :
node _T_1271 = eq(_T_1268, UInt<1>(0h0))
when _T_1271 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1268, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<257>
connect d_clr, UInt<257>(0h0)
wire d_clr_wo_ready : UInt<257>
connect d_clr_wo_ready, UInt<257>(0h0)
wire d_opcodes_clr : UInt<1028>
connect d_opcodes_clr, UInt<1028>(0h0)
wire d_sizes_clr : UInt<1028>
connect d_sizes_clr, UInt<1028>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1272 = and(io.in.d.valid, d_first_1)
node _T_1273 = and(_T_1272, UInt<1>(0h1))
node _T_1274 = eq(d_release_ack, UInt<1>(0h0))
node _T_1275 = and(_T_1273, _T_1274)
when _T_1275 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1276 = and(io.in.d.ready, io.in.d.valid)
node _T_1277 = and(_T_1276, d_first_1)
node _T_1278 = and(_T_1277, UInt<1>(0h1))
node _T_1279 = eq(d_release_ack, UInt<1>(0h0))
node _T_1280 = and(_T_1278, _T_1279)
when _T_1280 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1281 = and(io.in.d.valid, d_first_1)
node _T_1282 = and(_T_1281, UInt<1>(0h1))
node _T_1283 = eq(d_release_ack, UInt<1>(0h0))
node _T_1284 = and(_T_1282, _T_1283)
when _T_1284 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1285 = dshr(inflight, io.in.d.bits.source)
node _T_1286 = bits(_T_1285, 0, 0)
node _T_1287 = or(_T_1286, same_cycle_resp)
node _T_1288 = asUInt(reset)
node _T_1289 = eq(_T_1288, UInt<1>(0h0))
when _T_1289 :
node _T_1290 = eq(_T_1287, UInt<1>(0h0))
when _T_1290 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1287, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1291 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1292 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1293 = or(_T_1291, _T_1292)
node _T_1294 = asUInt(reset)
node _T_1295 = eq(_T_1294, UInt<1>(0h0))
when _T_1295 :
node _T_1296 = eq(_T_1293, UInt<1>(0h0))
when _T_1296 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1293, UInt<1>(0h1), "") : assert_100
node _T_1297 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1298 = asUInt(reset)
node _T_1299 = eq(_T_1298, UInt<1>(0h0))
when _T_1299 :
node _T_1300 = eq(_T_1297, UInt<1>(0h0))
when _T_1300 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1297, UInt<1>(0h1), "") : assert_101
else :
node _T_1301 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1302 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1303 = or(_T_1301, _T_1302)
node _T_1304 = asUInt(reset)
node _T_1305 = eq(_T_1304, UInt<1>(0h0))
when _T_1305 :
node _T_1306 = eq(_T_1303, UInt<1>(0h0))
when _T_1306 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1303, UInt<1>(0h1), "") : assert_102
node _T_1307 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1308 = asUInt(reset)
node _T_1309 = eq(_T_1308, UInt<1>(0h0))
when _T_1309 :
node _T_1310 = eq(_T_1307, UInt<1>(0h0))
when _T_1310 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1307, UInt<1>(0h1), "") : assert_103
node _T_1311 = and(io.in.d.valid, d_first_1)
node _T_1312 = and(_T_1311, a_first_1)
node _T_1313 = and(_T_1312, io.in.a.valid)
node _T_1314 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1315 = and(_T_1313, _T_1314)
node _T_1316 = eq(d_release_ack, UInt<1>(0h0))
node _T_1317 = and(_T_1315, _T_1316)
when _T_1317 :
node _T_1318 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1319 = or(_T_1318, io.in.a.ready)
node _T_1320 = asUInt(reset)
node _T_1321 = eq(_T_1320, UInt<1>(0h0))
when _T_1321 :
node _T_1322 = eq(_T_1319, UInt<1>(0h0))
when _T_1322 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1319, UInt<1>(0h1), "") : assert_104
node _T_1323 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1324 = orr(a_set_wo_ready)
node _T_1325 = eq(_T_1324, UInt<1>(0h0))
node _T_1326 = or(_T_1323, _T_1325)
node _T_1327 = asUInt(reset)
node _T_1328 = eq(_T_1327, UInt<1>(0h0))
when _T_1328 :
node _T_1329 = eq(_T_1326, UInt<1>(0h0))
when _T_1329 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1326, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_14
node _T_1330 = orr(inflight)
node _T_1331 = eq(_T_1330, UInt<1>(0h0))
node _T_1332 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1333 = or(_T_1331, _T_1332)
node _T_1334 = lt(watchdog, plusarg_reader.out)
node _T_1335 = or(_T_1333, _T_1334)
node _T_1336 = asUInt(reset)
node _T_1337 = eq(_T_1336, UInt<1>(0h0))
when _T_1337 :
node _T_1338 = eq(_T_1335, UInt<1>(0h0))
when _T_1338 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1335, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1339 = and(io.in.a.ready, io.in.a.valid)
node _T_1340 = and(io.in.d.ready, io.in.d.valid)
node _T_1341 = or(_T_1339, _T_1340)
when _T_1341 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<257>, clock, reset, UInt<257>(0h0)
regreset inflight_opcodes_1 : UInt<1028>, clock, reset, UInt<1028>(0h0)
regreset inflight_sizes_1 : UInt<1028>, clock, reset, UInt<1028>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<29>(0h0)
connect _c_first_WIRE.bits.source, UInt<9>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<9>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<257>
connect c_set, UInt<257>(0h0)
wire c_set_wo_ready : UInt<257>
connect c_set_wo_ready, UInt<257>(0h0)
wire c_opcodes_set : UInt<1028>
connect c_opcodes_set, UInt<1028>(0h0)
wire c_sizes_set : UInt<1028>
connect c_sizes_set, UInt<1028>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<29>(0h0)
connect _WIRE_10.bits.source, UInt<9>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1342 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<29>(0h0)
connect _WIRE_12.bits.source, UInt<9>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1343 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1344 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1345 = and(_T_1343, _T_1344)
node _T_1346 = and(_T_1342, _T_1345)
when _T_1346 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<9>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<29>(0h0)
connect _WIRE_14.bits.source, UInt<9>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1347 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1348 = and(_T_1347, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<29>(0h0)
connect _WIRE_16.bits.source, UInt<9>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1349 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1350 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1351 = and(_T_1349, _T_1350)
node _T_1352 = and(_T_1348, _T_1351)
when _T_1352 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_WIRE.bits.source, UInt<9>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<9>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<9>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<9>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<9>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<29>(0h0)
connect _WIRE_18.bits.source, UInt<9>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1353 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1354 = bits(_T_1353, 0, 0)
node _T_1355 = eq(_T_1354, UInt<1>(0h0))
node _T_1356 = asUInt(reset)
node _T_1357 = eq(_T_1356, UInt<1>(0h0))
when _T_1357 :
node _T_1358 = eq(_T_1355, UInt<1>(0h0))
when _T_1358 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1355, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<9>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<9>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<257>
connect d_clr_1, UInt<257>(0h0)
wire d_clr_wo_ready_1 : UInt<257>
connect d_clr_wo_ready_1, UInt<257>(0h0)
wire d_opcodes_clr_1 : UInt<1028>
connect d_opcodes_clr_1, UInt<1028>(0h0)
wire d_sizes_clr_1 : UInt<1028>
connect d_sizes_clr_1, UInt<1028>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1359 = and(io.in.d.valid, d_first_2)
node _T_1360 = and(_T_1359, UInt<1>(0h1))
node _T_1361 = and(_T_1360, d_release_ack_1)
when _T_1361 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1362 = and(io.in.d.ready, io.in.d.valid)
node _T_1363 = and(_T_1362, d_first_2)
node _T_1364 = and(_T_1363, UInt<1>(0h1))
node _T_1365 = and(_T_1364, d_release_ack_1)
when _T_1365 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1366 = and(io.in.d.valid, d_first_2)
node _T_1367 = and(_T_1366, UInt<1>(0h1))
node _T_1368 = and(_T_1367, d_release_ack_1)
when _T_1368 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<9>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1369 = dshr(inflight_1, io.in.d.bits.source)
node _T_1370 = bits(_T_1369, 0, 0)
node _T_1371 = or(_T_1370, same_cycle_resp_1)
node _T_1372 = asUInt(reset)
node _T_1373 = eq(_T_1372, UInt<1>(0h0))
when _T_1373 :
node _T_1374 = eq(_T_1371, UInt<1>(0h0))
when _T_1374 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1371, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<29>(0h0)
connect _WIRE_20.bits.source, UInt<9>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1375 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1376 = asUInt(reset)
node _T_1377 = eq(_T_1376, UInt<1>(0h0))
when _T_1377 :
node _T_1378 = eq(_T_1375, UInt<1>(0h0))
when _T_1378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1375, UInt<1>(0h1), "") : assert_109
else :
node _T_1379 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1380 = asUInt(reset)
node _T_1381 = eq(_T_1380, UInt<1>(0h0))
when _T_1381 :
node _T_1382 = eq(_T_1379, UInt<1>(0h0))
when _T_1382 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1379, UInt<1>(0h1), "") : assert_110
node _T_1383 = and(io.in.d.valid, d_first_2)
node _T_1384 = and(_T_1383, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<29>(0h0)
connect _WIRE_22.bits.source, UInt<9>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1385 = and(_T_1384, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<29>(0h0)
connect _WIRE_24.bits.source, UInt<9>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1386 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1387 = and(_T_1385, _T_1386)
node _T_1388 = and(_T_1387, d_release_ack_1)
node _T_1389 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1390 = and(_T_1388, _T_1389)
when _T_1390 :
node _T_1391 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<29>(0h0)
connect _WIRE_26.bits.source, UInt<9>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1392 = or(_T_1391, _WIRE_27.ready)
node _T_1393 = asUInt(reset)
node _T_1394 = eq(_T_1393, UInt<1>(0h0))
when _T_1394 :
node _T_1395 = eq(_T_1392, UInt<1>(0h0))
when _T_1395 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1392, UInt<1>(0h1), "") : assert_111
node _T_1396 = orr(c_set_wo_ready)
when _T_1396 :
node _T_1397 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1398 = asUInt(reset)
node _T_1399 = eq(_T_1398, UInt<1>(0h0))
when _T_1399 :
node _T_1400 = eq(_T_1397, UInt<1>(0h0))
when _T_1400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1397, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_15
node _T_1401 = orr(inflight_1)
node _T_1402 = eq(_T_1401, UInt<1>(0h0))
node _T_1403 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1404 = or(_T_1402, _T_1403)
node _T_1405 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1406 = or(_T_1404, _T_1405)
node _T_1407 = asUInt(reset)
node _T_1408 = eq(_T_1407, UInt<1>(0h0))
when _T_1408 :
node _T_1409 = eq(_T_1406, UInt<1>(0h0))
when _T_1409 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1406, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<29>(0h0)
connect _WIRE_28.bits.source, UInt<9>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1410 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1411 = and(io.in.d.ready, io.in.d.valid)
node _T_1412 = or(_T_1410, _T_1411)
when _T_1412 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_7( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [8:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [8:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [8:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [8:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_wo_ready_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_wo_ready_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_4_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_5_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [4098:0] _c_opcodes_set_T_1 = 4099'h0; // @[Monitor.scala:767:54]
wire [4098:0] _c_sizes_set_T_1 = 4099'h0; // @[Monitor.scala:768:52]
wire [11:0] _c_opcodes_set_T = 12'h0; // @[Monitor.scala:767:79]
wire [11:0] _c_sizes_set_T = 12'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [511:0] _c_set_wo_ready_T = 512'h1; // @[OneHot.scala:58:35]
wire [511:0] _c_set_T = 512'h1; // @[OneHot.scala:58:35]
wire [1027:0] c_opcodes_set = 1028'h0; // @[Monitor.scala:740:34]
wire [1027:0] c_sizes_set = 1028'h0; // @[Monitor.scala:741:34]
wire [256:0] c_set = 257'h0; // @[Monitor.scala:738:34]
wire [256:0] c_set_wo_ready = 257'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [8:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 9'h90; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [6:0] _source_ok_T_1 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_7 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_13 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_19 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 7'h20; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 7'h21; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 7'h22; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 7'h23; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[5:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_25 = io_in_a_bits_source_0[8:6]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_31 = io_in_a_bits_source_0[8:6]; // @[Monitor.scala:36:7]
wire _source_ok_T_26 = _source_ok_T_25 == 3'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = _source_ok_T_31 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire _source_ok_T_37 = io_in_a_bits_source_0 == 9'hA0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire _source_ok_T_38 = io_in_a_bits_source_0 == 9'hA1; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire _source_ok_T_39 = io_in_a_bits_source_0 == 9'hA2; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31]
wire _source_ok_T_40 = io_in_a_bits_source_0 == 9'h100; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31]
wire _source_ok_T_41 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_49 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_4 = _uncommonBits_T_4[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_5 = _uncommonBits_T_5[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_10 = _uncommonBits_T_10[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_11 = _uncommonBits_T_11[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_16 = _uncommonBits_T_16[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_17 = _uncommonBits_T_17[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_22 = _uncommonBits_T_22[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_23 = _uncommonBits_T_23[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_28 = _uncommonBits_T_28[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_29 = _uncommonBits_T_29[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_34 = _uncommonBits_T_34[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_35 = _uncommonBits_T_35[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_40 = _uncommonBits_T_40[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_41 = _uncommonBits_T_41[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_46 = _uncommonBits_T_46[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_47 = _uncommonBits_T_47[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_52 = _uncommonBits_T_52[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_53 = _uncommonBits_T_53[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_58 = _uncommonBits_T_58[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_59 = _uncommonBits_T_59[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_64 = _uncommonBits_T_64[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_65 = _uncommonBits_T_65[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_50 = io_in_d_bits_source_0 == 9'h90; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_50; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [6:0] _source_ok_T_51 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_57 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_63 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_69 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_52 = _source_ok_T_51 == 7'h20; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_56; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_58 = _source_ok_T_57 == 7'h21; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_62; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_64 = _source_ok_T_63 == 7'h22; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_68; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_70 = _source_ok_T_69 == 7'h23; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_74; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[5:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_75 = io_in_d_bits_source_0[8:6]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_81 = io_in_d_bits_source_0[8:6]; // @[Monitor.scala:36:7]
wire _source_ok_T_76 = _source_ok_T_75 == 3'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_5 = _source_ok_T_80; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_82 = _source_ok_T_81 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_6 = _source_ok_T_86; // @[Parameters.scala:1138:31]
wire _source_ok_T_87 = io_in_d_bits_source_0 == 9'hA0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_87; // @[Parameters.scala:1138:31]
wire _source_ok_T_88 = io_in_d_bits_source_0 == 9'hA1; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_88; // @[Parameters.scala:1138:31]
wire _source_ok_T_89 = io_in_d_bits_source_0 == 9'hA2; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_89; // @[Parameters.scala:1138:31]
wire _source_ok_T_90 = io_in_d_bits_source_0 == 9'h100; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_90; // @[Parameters.scala:1138:31]
wire _source_ok_T_91 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_92 = _source_ok_T_91 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_93 = _source_ok_T_92 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_94 = _source_ok_T_93 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_99 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1339 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1339; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1339; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [8:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_1412 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1412; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1412; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1412; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [8:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [256:0] inflight; // @[Monitor.scala:614:27]
reg [1027:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [1027:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [256:0] a_set; // @[Monitor.scala:626:34]
wire [256:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [1027:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [1027:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [11:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [11:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [11:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [11:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [11:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [11:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [11:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [11:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [11:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [1027:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [1027:0] _a_opcode_lookup_T_6 = {1024'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [1027:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[1027:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [1027:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [1027:0] _a_size_lookup_T_6 = {1024'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [1027:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1027:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [511:0] _GEN_2 = 512'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [511:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [511:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire _T_1265 = _T_1339 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1265 ? _a_set_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1265 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1265 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [11:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [11:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [11:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [4098:0] _a_opcodes_set_T_1 = {4095'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1265 ? _a_opcodes_set_T_1[1027:0] : 1028'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [4098:0] _a_sizes_set_T_1 = {4095'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1265 ? _a_sizes_set_T_1[1027:0] : 1028'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [256:0] d_clr; // @[Monitor.scala:664:34]
wire [256:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [1027:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [1027:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1311 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [511:0] _GEN_5 = 512'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1311 & ~d_release_ack ? _d_clr_wo_ready_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire _T_1280 = _T_1412 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1280 ? _d_clr_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire [4110:0] _d_opcodes_clr_T_5 = 4111'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1280 ? _d_opcodes_clr_T_5[1027:0] : 1028'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [4110:0] _d_sizes_clr_T_5 = 4111'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1280 ? _d_sizes_clr_T_5[1027:0] : 1028'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [256:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [256:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [256:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [1027:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [1027:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [1027:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [1027:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [1027:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [1027:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [256:0] inflight_1; // @[Monitor.scala:726:35]
wire [256:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [1027:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [1027:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [1027:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [1027:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [1027:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [1027:0] _c_opcode_lookup_T_6 = {1024'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [1027:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[1027:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [1027:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [1027:0] _c_size_lookup_T_6 = {1024'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [1027:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1027:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [256:0] d_clr_1; // @[Monitor.scala:774:34]
wire [256:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [1027:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [1027:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1383 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1383 & d_release_ack_1 ? _d_clr_wo_ready_T_1[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire _T_1365 = _T_1412 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1365 ? _d_clr_T_1[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire [4110:0] _d_opcodes_clr_T_11 = 4111'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1365 ? _d_opcodes_clr_T_11[1027:0] : 1028'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [4110:0] _d_sizes_clr_T_11 = 4111'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1365 ? _d_sizes_clr_T_11[1027:0] : 1028'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 9'h0; // @[Monitor.scala:36:7, :795:113]
wire [256:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [256:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [1027:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [1027:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [1027:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [1027:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e11_s53_5 :
output io : { flip op : UInt<2>, flip a : UInt<65>, flip b : UInt<65>, flip c : UInt<65>, mulAddA : UInt<53>, mulAddB : UInt<53>, mulAddC : UInt<106>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<13>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<6>, highAlignedSigC : UInt<55>, bit0AlignedSigC : UInt<1>}}
node rawA_exp = bits(io.a, 63, 52)
node _rawA_isZero_T = bits(rawA_exp, 11, 9)
node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0))
node _rawA_isSpecial_T = bits(rawA_exp, 11, 10)
node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3))
wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}
node _rawA_out_isNaN_T = bits(rawA_exp, 9, 9)
node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T)
connect rawA.isNaN, _rawA_out_isNaN_T_1
node _rawA_out_isInf_T = bits(rawA_exp, 9, 9)
node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0))
node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1)
connect rawA.isInf, _rawA_out_isInf_T_2
connect rawA.isZero, rawA_isZero
node _rawA_out_sign_T = bits(io.a, 64, 64)
connect rawA.sign, _rawA_out_sign_T
node _rawA_out_sExp_T = cvt(rawA_exp)
connect rawA.sExp, _rawA_out_sExp_T
node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0))
node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T)
node _rawA_out_sig_T_2 = bits(io.a, 51, 0)
node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2)
connect rawA.sig, _rawA_out_sig_T_3
node rawB_exp = bits(io.b, 63, 52)
node _rawB_isZero_T = bits(rawB_exp, 11, 9)
node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0))
node _rawB_isSpecial_T = bits(rawB_exp, 11, 10)
node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3))
wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}
node _rawB_out_isNaN_T = bits(rawB_exp, 9, 9)
node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T)
connect rawB.isNaN, _rawB_out_isNaN_T_1
node _rawB_out_isInf_T = bits(rawB_exp, 9, 9)
node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0))
node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1)
connect rawB.isInf, _rawB_out_isInf_T_2
connect rawB.isZero, rawB_isZero
node _rawB_out_sign_T = bits(io.b, 64, 64)
connect rawB.sign, _rawB_out_sign_T
node _rawB_out_sExp_T = cvt(rawB_exp)
connect rawB.sExp, _rawB_out_sExp_T
node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0))
node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T)
node _rawB_out_sig_T_2 = bits(io.b, 51, 0)
node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2)
connect rawB.sig, _rawB_out_sig_T_3
node rawC_exp = bits(io.c, 63, 52)
node _rawC_isZero_T = bits(rawC_exp, 11, 9)
node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0))
node _rawC_isSpecial_T = bits(rawC_exp, 11, 10)
node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3))
wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}
node _rawC_out_isNaN_T = bits(rawC_exp, 9, 9)
node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T)
connect rawC.isNaN, _rawC_out_isNaN_T_1
node _rawC_out_isInf_T = bits(rawC_exp, 9, 9)
node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0))
node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1)
connect rawC.isInf, _rawC_out_isInf_T_2
connect rawC.isZero, rawC_isZero
node _rawC_out_sign_T = bits(io.c, 64, 64)
connect rawC.sign, _rawC_out_sign_T
node _rawC_out_sExp_T = cvt(rawC_exp)
connect rawC.sExp, _rawC_out_sExp_T
node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0))
node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T)
node _rawC_out_sig_T_2 = bits(io.c, 51, 0)
node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2)
connect rawC.sig, _rawC_out_sig_T_3
node _signProd_T = xor(rawA.sign, rawB.sign)
node _signProd_T_1 = bits(io.op, 1, 1)
node signProd = xor(_signProd_T, _signProd_T_1)
node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp)
node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<12>(0h838)))
node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1)
node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2)
node _doSubMags_T = xor(signProd, rawC.sign)
node _doSubMags_T_1 = bits(io.op, 0, 0)
node doSubMags = xor(_doSubMags_T, _doSubMags_T_1)
node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp)
node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1)
node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1)
node posNatCAlignDist = bits(sNatCAlignDist, 12, 0)
node _isMinCAlign_T = or(rawA.isZero, rawB.isZero)
node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0)))
node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1)
node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0))
node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<6>(0h35))
node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1)
node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2)
node _CAlignDist_T = lt(posNatCAlignDist, UInt<8>(0ha1))
node _CAlignDist_T_1 = bits(posNatCAlignDist, 7, 0)
node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<8>(0ha1))
node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2)
node _mainAlignedSigC_T = not(rawC.sig)
node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig)
node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<111>(0h7fffffffffffffffffffffffffff), UInt<111>(0h0))
node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2)
node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3)
node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist)
node _reduced4CExtra_T = shl(rawC.sig, 0)
wire reduced4CExtra_reducedVec : UInt<1>[14]
node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0)
node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T)
connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1
node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4)
node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T)
connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1
node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8)
node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T)
connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1
node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12)
node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T)
connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1
node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16)
node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T)
connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1
node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20)
node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T)
connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1
node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 27, 24)
node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T)
connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1
node _reduced4CExtra_reducedVec_7_T = bits(_reduced4CExtra_T, 31, 28)
node _reduced4CExtra_reducedVec_7_T_1 = orr(_reduced4CExtra_reducedVec_7_T)
connect reduced4CExtra_reducedVec[7], _reduced4CExtra_reducedVec_7_T_1
node _reduced4CExtra_reducedVec_8_T = bits(_reduced4CExtra_T, 35, 32)
node _reduced4CExtra_reducedVec_8_T_1 = orr(_reduced4CExtra_reducedVec_8_T)
connect reduced4CExtra_reducedVec[8], _reduced4CExtra_reducedVec_8_T_1
node _reduced4CExtra_reducedVec_9_T = bits(_reduced4CExtra_T, 39, 36)
node _reduced4CExtra_reducedVec_9_T_1 = orr(_reduced4CExtra_reducedVec_9_T)
connect reduced4CExtra_reducedVec[9], _reduced4CExtra_reducedVec_9_T_1
node _reduced4CExtra_reducedVec_10_T = bits(_reduced4CExtra_T, 43, 40)
node _reduced4CExtra_reducedVec_10_T_1 = orr(_reduced4CExtra_reducedVec_10_T)
connect reduced4CExtra_reducedVec[10], _reduced4CExtra_reducedVec_10_T_1
node _reduced4CExtra_reducedVec_11_T = bits(_reduced4CExtra_T, 47, 44)
node _reduced4CExtra_reducedVec_11_T_1 = orr(_reduced4CExtra_reducedVec_11_T)
connect reduced4CExtra_reducedVec[11], _reduced4CExtra_reducedVec_11_T_1
node _reduced4CExtra_reducedVec_12_T = bits(_reduced4CExtra_T, 51, 48)
node _reduced4CExtra_reducedVec_12_T_1 = orr(_reduced4CExtra_reducedVec_12_T)
connect reduced4CExtra_reducedVec[12], _reduced4CExtra_reducedVec_12_T_1
node _reduced4CExtra_reducedVec_13_T = bits(_reduced4CExtra_T, 53, 52)
node _reduced4CExtra_reducedVec_13_T_1 = orr(_reduced4CExtra_reducedVec_13_T)
connect reduced4CExtra_reducedVec[13], _reduced4CExtra_reducedVec_13_T_1
node reduced4CExtra_lo_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1])
node reduced4CExtra_lo_lo = cat(reduced4CExtra_lo_lo_hi, reduced4CExtra_reducedVec[0])
node reduced4CExtra_lo_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3])
node reduced4CExtra_lo_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5])
node reduced4CExtra_lo_hi = cat(reduced4CExtra_lo_hi_hi, reduced4CExtra_lo_hi_lo)
node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_lo_lo)
node reduced4CExtra_hi_lo_hi = cat(reduced4CExtra_reducedVec[9], reduced4CExtra_reducedVec[8])
node reduced4CExtra_hi_lo = cat(reduced4CExtra_hi_lo_hi, reduced4CExtra_reducedVec[7])
node reduced4CExtra_hi_hi_lo = cat(reduced4CExtra_reducedVec[11], reduced4CExtra_reducedVec[10])
node reduced4CExtra_hi_hi_hi = cat(reduced4CExtra_reducedVec[13], reduced4CExtra_reducedVec[12])
node reduced4CExtra_hi_hi = cat(reduced4CExtra_hi_hi_hi, reduced4CExtra_hi_hi_lo)
node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo)
node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo)
node _reduced4CExtra_T_2 = shr(CAlignDist, 2)
node reduced4CExtra_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), _reduced4CExtra_T_2)
node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 36, 24)
node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 7, 0)
node _reduced4CExtra_T_5 = shl(UInt<4>(0hf), 4)
node _reduced4CExtra_T_6 = xor(UInt<8>(0hff), _reduced4CExtra_T_5)
node _reduced4CExtra_T_7 = shr(_reduced4CExtra_T_4, 4)
node _reduced4CExtra_T_8 = and(_reduced4CExtra_T_7, _reduced4CExtra_T_6)
node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 0)
node _reduced4CExtra_T_10 = shl(_reduced4CExtra_T_9, 4)
node _reduced4CExtra_T_11 = not(_reduced4CExtra_T_6)
node _reduced4CExtra_T_12 = and(_reduced4CExtra_T_10, _reduced4CExtra_T_11)
node _reduced4CExtra_T_13 = or(_reduced4CExtra_T_8, _reduced4CExtra_T_12)
node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_6, 5, 0)
node _reduced4CExtra_T_15 = shl(_reduced4CExtra_T_14, 2)
node _reduced4CExtra_T_16 = xor(_reduced4CExtra_T_6, _reduced4CExtra_T_15)
node _reduced4CExtra_T_17 = shr(_reduced4CExtra_T_13, 2)
node _reduced4CExtra_T_18 = and(_reduced4CExtra_T_17, _reduced4CExtra_T_16)
node _reduced4CExtra_T_19 = bits(_reduced4CExtra_T_13, 5, 0)
node _reduced4CExtra_T_20 = shl(_reduced4CExtra_T_19, 2)
node _reduced4CExtra_T_21 = not(_reduced4CExtra_T_16)
node _reduced4CExtra_T_22 = and(_reduced4CExtra_T_20, _reduced4CExtra_T_21)
node _reduced4CExtra_T_23 = or(_reduced4CExtra_T_18, _reduced4CExtra_T_22)
node _reduced4CExtra_T_24 = bits(_reduced4CExtra_T_16, 6, 0)
node _reduced4CExtra_T_25 = shl(_reduced4CExtra_T_24, 1)
node _reduced4CExtra_T_26 = xor(_reduced4CExtra_T_16, _reduced4CExtra_T_25)
node _reduced4CExtra_T_27 = shr(_reduced4CExtra_T_23, 1)
node _reduced4CExtra_T_28 = and(_reduced4CExtra_T_27, _reduced4CExtra_T_26)
node _reduced4CExtra_T_29 = bits(_reduced4CExtra_T_23, 6, 0)
node _reduced4CExtra_T_30 = shl(_reduced4CExtra_T_29, 1)
node _reduced4CExtra_T_31 = not(_reduced4CExtra_T_26)
node _reduced4CExtra_T_32 = and(_reduced4CExtra_T_30, _reduced4CExtra_T_31)
node _reduced4CExtra_T_33 = or(_reduced4CExtra_T_28, _reduced4CExtra_T_32)
node _reduced4CExtra_T_34 = bits(_reduced4CExtra_T_3, 12, 8)
node _reduced4CExtra_T_35 = bits(_reduced4CExtra_T_34, 3, 0)
node _reduced4CExtra_T_36 = bits(_reduced4CExtra_T_35, 1, 0)
node _reduced4CExtra_T_37 = bits(_reduced4CExtra_T_36, 0, 0)
node _reduced4CExtra_T_38 = bits(_reduced4CExtra_T_36, 1, 1)
node _reduced4CExtra_T_39 = cat(_reduced4CExtra_T_37, _reduced4CExtra_T_38)
node _reduced4CExtra_T_40 = bits(_reduced4CExtra_T_35, 3, 2)
node _reduced4CExtra_T_41 = bits(_reduced4CExtra_T_40, 0, 0)
node _reduced4CExtra_T_42 = bits(_reduced4CExtra_T_40, 1, 1)
node _reduced4CExtra_T_43 = cat(_reduced4CExtra_T_41, _reduced4CExtra_T_42)
node _reduced4CExtra_T_44 = cat(_reduced4CExtra_T_39, _reduced4CExtra_T_43)
node _reduced4CExtra_T_45 = bits(_reduced4CExtra_T_34, 4, 4)
node _reduced4CExtra_T_46 = cat(_reduced4CExtra_T_44, _reduced4CExtra_T_45)
node _reduced4CExtra_T_47 = cat(_reduced4CExtra_T_33, _reduced4CExtra_T_46)
node _reduced4CExtra_T_48 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_47)
node reduced4CExtra = orr(_reduced4CExtra_T_48)
node _alignedSigC_T = shr(mainAlignedSigC, 3)
node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0)
node _alignedSigC_T_2 = andr(_alignedSigC_T_1)
node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0))
node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3)
node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0)
node _alignedSigC_T_6 = orr(_alignedSigC_T_5)
node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra)
node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7)
node alignedSigC_hi = asUInt(_alignedSigC_T)
node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8)
connect io.mulAddA, rawA.sig
connect io.mulAddB, rawB.sig
node _io_mulAddC_T = bits(alignedSigC, 106, 1)
connect io.mulAddC, _io_mulAddC_T
node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 51, 51)
node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1)
node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 51, 51)
node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4)
node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5)
node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 51, 51)
node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8)
node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9)
connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10
node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN)
connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T
connect io.toPostMul.isInfA, rawA.isInf
connect io.toPostMul.isZeroA, rawA.isZero
connect io.toPostMul.isInfB, rawB.isInf
connect io.toPostMul.isZeroB, rawB.isZero
connect io.toPostMul.signProd, signProd
connect io.toPostMul.isNaNC, rawC.isNaN
connect io.toPostMul.isInfC, rawC.isInf
connect io.toPostMul.isZeroC, rawC.isZero
node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<7>(0h35)))
node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1)
node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1)
node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2)
connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3
connect io.toPostMul.doSubMags, doSubMags
connect io.toPostMul.CIsDominant, CIsDominant
node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 5, 0)
connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T
node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 161, 107)
connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T
node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0)
connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T | module MulAddRecFNToRaw_preMul_e11_s53_5( // @[MulAddRecFN.scala:71:7]
input [1:0] io_op, // @[MulAddRecFN.scala:74:16]
input [64:0] io_a, // @[MulAddRecFN.scala:74:16]
input [64:0] io_b, // @[MulAddRecFN.scala:74:16]
input [64:0] io_c, // @[MulAddRecFN.scala:74:16]
output [52:0] io_mulAddA, // @[MulAddRecFN.scala:74:16]
output [52:0] io_mulAddB, // @[MulAddRecFN.scala:74:16]
output [105:0] io_mulAddC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16]
output [12:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16]
output [5:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16]
output [54:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16]
);
wire [1:0] io_op_0 = io_op; // @[MulAddRecFN.scala:71:7]
wire [64:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7]
wire [64:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7]
wire [64:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7]
wire [7:0] _reduced4CExtra_T_6 = 8'hF; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_5 = 8'hF0; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_11 = 8'hF0; // @[primitives.scala:77:20]
wire [5:0] _reduced4CExtra_T_14 = 6'hF; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_15 = 8'h3C; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_16 = 8'h33; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_21 = 8'hCC; // @[primitives.scala:77:20]
wire [6:0] _reduced4CExtra_T_24 = 7'h33; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_25 = 8'h66; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_26 = 8'h55; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_31 = 8'hAA; // @[primitives.scala:77:20]
wire [105:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30]
wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58]
wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42]
wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire signProd; // @[MulAddRecFN.scala:97:42]
wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire doSubMags; // @[MulAddRecFN.scala:102:42]
wire CIsDominant; // @[MulAddRecFN.scala:110:23]
wire [5:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47]
wire [54:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20]
wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48]
wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
wire [12:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
wire [5:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
wire [54:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire [52:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
wire [52:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
wire [105:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
wire [11:0] rawA_exp = io_a_0[63:52]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawA_isZero_T = rawA_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawA_isSpecial_T = rawA_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [12:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_isNaN_T = rawA_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawA_out_isInf_T = rawA_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawA_out_sign_T = io_a_0[64]; // @[rawFloatFromRecFN.scala:59:25]
assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [51:0] _rawA_out_sig_T_2 = io_a_0[51:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [11:0] rawB_exp = io_b_0[63:52]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawB_isZero_T = rawB_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawB_isSpecial_T = rawB_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [12:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_isNaN_T = rawB_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawB_out_isInf_T = rawB_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawB_out_sign_T = io_b_0[64]; // @[rawFloatFromRecFN.scala:59:25]
assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [51:0] _rawB_out_sig_T_2 = io_b_0[51:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [11:0] rawC_exp = io_c_0[63:52]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawC_isZero_T = rawC_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawC_isSpecial_T = rawC_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [12:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] _reduced4CExtra_T = rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isNaN_T = rawC_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawC_out_isInf_T = rawC_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawC_out_sign_T = io_c_0[64]; // @[rawFloatFromRecFN.scala:59:25]
assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [51:0] _rawC_out_sig_T_2 = io_c_0[51:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _signProd_T_1 = io_op_0[1]; // @[MulAddRecFN.scala:71:7, :97:49]
assign signProd = _signProd_T ^ _signProd_T_1; // @[MulAddRecFN.scala:97:{30,42,49}]
assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42]
wire [13:0] _sExpAlignedProd_T = {rawA_sExp[12], rawA_sExp} + {rawB_sExp[12], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [14:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[13], _sExpAlignedProd_T} - 15'h7C8; // @[MulAddRecFN.scala:100:{19,32}]
wire [13:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[13:0]; // @[MulAddRecFN.scala:100:32]
wire [13:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32]
wire _doSubMags_T = signProd ^ rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _doSubMags_T_1 = io_op_0[0]; // @[MulAddRecFN.scala:71:7, :102:49]
assign doSubMags = _doSubMags_T ^ _doSubMags_T_1; // @[MulAddRecFN.scala:102:{30,42,49}]
assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42]
wire [14:0] _GEN = {sExpAlignedProd[13], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42]
wire [14:0] _sNatCAlignDist_T = _GEN - {{2{rawC_sExp[12]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [13:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[13:0]; // @[MulAddRecFN.scala:106:42]
wire [13:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42]
wire [12:0] posNatCAlignDist = sNatCAlignDist[12:0]; // @[MulAddRecFN.scala:106:42, :107:42]
wire _isMinCAlign_T = rawA_isZero | rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 14'sh0; // @[MulAddRecFN.scala:106:42, :108:69, :130:11]
wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}]
wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _CIsDominant_T_1 = posNatCAlignDist < 13'h36; // @[MulAddRecFN.scala:107:42, :110:60]
wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}]
assign CIsDominant = _CIsDominant_T & _CIsDominant_T_2; // @[MulAddRecFN.scala:110:{9,23,39}]
assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23]
wire _CAlignDist_T = posNatCAlignDist < 13'hA1; // @[MulAddRecFN.scala:107:42, :114:34]
wire [7:0] _CAlignDist_T_1 = posNatCAlignDist[7:0]; // @[MulAddRecFN.scala:107:42, :115:33]
wire [7:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 8'hA1; // @[MulAddRecFN.scala:114:{16,34}, :115:33]
wire [7:0] CAlignDist = isMinCAlign ? 8'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16]
wire [53:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [110:0] _mainAlignedSigC_T_2 = {111{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53]
wire [164:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}]
wire [164:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}]
wire [164:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}]
wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_7_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_8_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_9_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_10_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_11_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_12_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_13_T_1; // @[primitives.scala:123:57]
wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_7; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_8; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_9; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_10; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_11; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_12; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_13; // @[primitives.scala:118:30]
wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_0_T_1 = |_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_1_T_1 = |_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_2_T_1 = |_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_3_T_1 = |_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_4_T_1 = |_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_5_T_1 = |_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[27:24]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_6_T_1 = |_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_7_T = _reduced4CExtra_T[31:28]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_7_T_1 = |_reduced4CExtra_reducedVec_7_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_7 = _reduced4CExtra_reducedVec_7_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_8_T = _reduced4CExtra_T[35:32]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_8_T_1 = |_reduced4CExtra_reducedVec_8_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_8 = _reduced4CExtra_reducedVec_8_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_9_T = _reduced4CExtra_T[39:36]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_9_T_1 = |_reduced4CExtra_reducedVec_9_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_9 = _reduced4CExtra_reducedVec_9_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_10_T = _reduced4CExtra_T[43:40]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_10_T_1 = |_reduced4CExtra_reducedVec_10_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_10 = _reduced4CExtra_reducedVec_10_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_11_T = _reduced4CExtra_T[47:44]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_11_T_1 = |_reduced4CExtra_reducedVec_11_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_11 = _reduced4CExtra_reducedVec_11_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_12_T = _reduced4CExtra_T[51:48]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_12_T_1 = |_reduced4CExtra_reducedVec_12_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_12 = _reduced4CExtra_reducedVec_12_T_1; // @[primitives.scala:118:30, :120:54]
wire [1:0] _reduced4CExtra_reducedVec_13_T = _reduced4CExtra_T[53:52]; // @[primitives.scala:123:15]
assign _reduced4CExtra_reducedVec_13_T_1 = |_reduced4CExtra_reducedVec_13_T; // @[primitives.scala:123:{15,57}]
assign reduced4CExtra_reducedVec_13 = _reduced4CExtra_reducedVec_13_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] reduced4CExtra_lo_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] reduced4CExtra_lo_lo = {reduced4CExtra_lo_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_lo_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_lo_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] reduced4CExtra_lo_hi = {reduced4CExtra_lo_hi_hi, reduced4CExtra_lo_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_lo_lo}; // @[primitives.scala:124:20]
wire [1:0] reduced4CExtra_hi_lo_hi = {reduced4CExtra_reducedVec_9, reduced4CExtra_reducedVec_8}; // @[primitives.scala:118:30, :124:20]
wire [2:0] reduced4CExtra_hi_lo = {reduced4CExtra_hi_lo_hi, reduced4CExtra_reducedVec_7}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_hi_hi_lo = {reduced4CExtra_reducedVec_11, reduced4CExtra_reducedVec_10}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_hi_hi_hi = {reduced4CExtra_reducedVec_13, reduced4CExtra_reducedVec_12}; // @[primitives.scala:118:30, :124:20]
wire [3:0] reduced4CExtra_hi_hi = {reduced4CExtra_hi_hi_hi, reduced4CExtra_hi_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20]
wire [13:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20]
wire [5:0] _reduced4CExtra_T_2 = CAlignDist[7:2]; // @[MulAddRecFN.scala:112:12, :124:28]
wire [64:0] reduced4CExtra_shift = $signed(65'sh10000000000000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56]
wire [12:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[36:24]; // @[primitives.scala:76:56, :78:22]
wire [7:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[7:0]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _reduced4CExtra_T_7 = _reduced4CExtra_T_4[7:4]; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_8 = {4'h0, _reduced4CExtra_T_7}; // @[primitives.scala:77:20, :120:54]
wire [3:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:0]; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_10 = {_reduced4CExtra_T_9, 4'h0}; // @[primitives.scala:77:20, :120:54]
wire [7:0] _reduced4CExtra_T_12 = _reduced4CExtra_T_10 & 8'hF0; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_13 = _reduced4CExtra_T_8 | _reduced4CExtra_T_12; // @[primitives.scala:77:20]
wire [5:0] _reduced4CExtra_T_17 = _reduced4CExtra_T_13[7:2]; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_18 = {2'h0, _reduced4CExtra_T_17 & 6'h33}; // @[primitives.scala:77:20, :123:57]
wire [5:0] _reduced4CExtra_T_19 = _reduced4CExtra_T_13[5:0]; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_20 = {_reduced4CExtra_T_19, 2'h0}; // @[primitives.scala:77:20, :123:57]
wire [7:0] _reduced4CExtra_T_22 = _reduced4CExtra_T_20 & 8'hCC; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_23 = _reduced4CExtra_T_18 | _reduced4CExtra_T_22; // @[primitives.scala:77:20]
wire [6:0] _reduced4CExtra_T_27 = _reduced4CExtra_T_23[7:1]; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_28 = {1'h0, _reduced4CExtra_T_27 & 7'h55}; // @[primitives.scala:77:20]
wire [6:0] _reduced4CExtra_T_29 = _reduced4CExtra_T_23[6:0]; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_30 = {_reduced4CExtra_T_29, 1'h0}; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_32 = _reduced4CExtra_T_30 & 8'hAA; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_33 = _reduced4CExtra_T_28 | _reduced4CExtra_T_32; // @[primitives.scala:77:20]
wire [4:0] _reduced4CExtra_T_34 = _reduced4CExtra_T_3[12:8]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _reduced4CExtra_T_35 = _reduced4CExtra_T_34[3:0]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_36 = _reduced4CExtra_T_35[1:0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_37 = _reduced4CExtra_T_36[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_38 = _reduced4CExtra_T_36[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_39 = {_reduced4CExtra_T_37, _reduced4CExtra_T_38}; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_40 = _reduced4CExtra_T_35[3:2]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_41 = _reduced4CExtra_T_40[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_42 = _reduced4CExtra_T_40[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_43 = {_reduced4CExtra_T_41, _reduced4CExtra_T_42}; // @[primitives.scala:77:20]
wire [3:0] _reduced4CExtra_T_44 = {_reduced4CExtra_T_39, _reduced4CExtra_T_43}; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_45 = _reduced4CExtra_T_34[4]; // @[primitives.scala:77:20]
wire [4:0] _reduced4CExtra_T_46 = {_reduced4CExtra_T_44, _reduced4CExtra_T_45}; // @[primitives.scala:77:20]
wire [12:0] _reduced4CExtra_T_47 = {_reduced4CExtra_T_33, _reduced4CExtra_T_46}; // @[primitives.scala:77:20]
wire [13:0] _reduced4CExtra_T_48 = {1'h0, _reduced4CExtra_T_1[12:0] & _reduced4CExtra_T_47}; // @[primitives.scala:77:20, :124:20]
wire reduced4CExtra = |_reduced4CExtra_T_48; // @[MulAddRecFN.scala:122:68, :130:11]
wire [161:0] _alignedSigC_T = mainAlignedSigC[164:3]; // @[MulAddRecFN.scala:120:100, :132:28]
wire [161:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}]
wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32]
wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32]
wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}]
wire _alignedSigC_T_3 = ~reduced4CExtra; // @[MulAddRecFN.scala:130:11, :134:47]
wire _alignedSigC_T_4 = _alignedSigC_T_2 & _alignedSigC_T_3; // @[MulAddRecFN.scala:134:{39,44,47}]
wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}]
wire _alignedSigC_T_7 = _alignedSigC_T_6 | reduced4CExtra; // @[MulAddRecFN.scala:130:11, :135:{39,44}]
wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44]
wire [162:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16]
assign io_mulAddA_0 = rawA_sig[52:0]; // @[rawFloatFromRecFN.scala:55:23]
assign io_mulAddB_0 = rawB_sig[52:0]; // @[rawFloatFromRecFN.scala:55:23]
assign _io_mulAddC_T = alignedSigC[106:1]; // @[MulAddRecFN.scala:132:12, :143:30]
assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30]
wire _io_toPostMul_isSigNaNAny_T = rawA_sig[51]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[51]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 | _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46]
wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[51]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23]
assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6 | _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46]
assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58]
assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN | rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42]
wire [14:0] _io_toPostMul_sExpSum_T = _GEN - 15'h35; // @[MulAddRecFN.scala:106:42, :158:53]
wire [13:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[13:0]; // @[MulAddRecFN.scala:158:53]
wire [13:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53]
wire [13:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[12], rawC_sExp} : _io_toPostMul_sExpSum_T_2; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[12:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12]
assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[5:0]; // @[MulAddRecFN.scala:112:12, :161:47]
assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47]
assign _io_toPostMul_highAlignedSigC_T = alignedSigC[161:107]; // @[MulAddRecFN.scala:132:12, :163:20]
assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20]
assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48]
assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48]
assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLBusBypassBar :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}}
output io : { flip bypass : UInt<1>, pending : UInt<1>}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_50
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
wire x1_nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}
invalidate x1_nodeOut.d.bits.corrupt
invalidate x1_nodeOut.d.bits.data
invalidate x1_nodeOut.d.bits.denied
invalidate x1_nodeOut.d.bits.sink
invalidate x1_nodeOut.d.bits.source
invalidate x1_nodeOut.d.bits.size
invalidate x1_nodeOut.d.bits.param
invalidate x1_nodeOut.d.bits.opcode
invalidate x1_nodeOut.d.valid
invalidate x1_nodeOut.d.ready
invalidate x1_nodeOut.a.bits.corrupt
invalidate x1_nodeOut.a.bits.data
invalidate x1_nodeOut.a.bits.mask
invalidate x1_nodeOut.a.bits.address
invalidate x1_nodeOut.a.bits.source
invalidate x1_nodeOut.a.bits.size
invalidate x1_nodeOut.a.bits.param
invalidate x1_nodeOut.a.bits.opcode
invalidate x1_nodeOut.a.valid
invalidate x1_nodeOut.a.ready
connect auto.out_0, nodeOut
connect auto.out_1, x1_nodeOut
connect nodeIn, auto.in
regreset in_reset : UInt<1>, clock, reset, UInt<1>(0h1)
connect in_reset, UInt<1>(0h0)
reg bypass_reg : UInt<1>, clock
node bypass = mux(in_reset, io.bypass, bypass_reg)
regreset flight : UInt<2>, clock, reset, UInt<2>(0h0)
node _T = and(nodeIn.a.ready, nodeIn.a.valid)
node _r_beats1_decode_T = dshl(UInt<2>(0h3), nodeIn.a.bits.size)
node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 1, 0)
node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1)
node r_beats1_decode = shr(_r_beats1_decode_T_2, 2)
node _r_beats1_opdata_T = bits(nodeIn.a.bits.opcode, 2, 2)
node r_beats1_opdata = eq(_r_beats1_opdata_T, UInt<1>(0h0))
node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0))
regreset r_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _r_counter1_T = sub(r_counter, UInt<1>(0h1))
node r_counter1 = tail(_r_counter1_T, 1)
node a_first = eq(r_counter, UInt<1>(0h0))
node _r_last_T = eq(r_counter, UInt<1>(0h1))
node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0))
node a_last = or(_r_last_T, _r_last_T_1)
node r_3 = and(a_last, _T)
node _r_count_T = not(r_counter1)
node r_4 = and(r_beats1, _r_count_T)
when _T :
node _r_counter_T = mux(a_first, r_beats1, r_counter1)
connect r_counter, _r_counter_T
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<32>(0h0)
connect _WIRE.bits.mask, UInt<4>(0h0)
connect _WIRE.bits.address, UInt<9>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1 = and(_WIRE_1.ready, _WIRE_1.valid)
node _r_beats1_decode_T_3 = dshl(UInt<2>(0h3), _WIRE_1.bits.size)
node _r_beats1_decode_T_4 = bits(_r_beats1_decode_T_3, 1, 0)
node _r_beats1_decode_T_5 = not(_r_beats1_decode_T_4)
node r_beats1_decode_1 = shr(_r_beats1_decode_T_5, 2)
node _r_beats1_opdata_T_1 = bits(_WIRE_1.bits.opcode, 2, 2)
node r_beats1_opdata_1 = eq(_r_beats1_opdata_T_1, UInt<1>(0h0))
node r_beats1_1 = mux(UInt<1>(0h0), r_beats1_decode_1, UInt<1>(0h0))
regreset r_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _r_counter1_T_1 = sub(r_counter_1, UInt<1>(0h1))
node r_counter1_1 = tail(_r_counter1_T_1, 1)
node b_first = eq(r_counter_1, UInt<1>(0h0))
node _r_last_T_2 = eq(r_counter_1, UInt<1>(0h1))
node _r_last_T_3 = eq(r_beats1_1, UInt<1>(0h0))
node b_last = or(_r_last_T_2, _r_last_T_3)
node r_3_1 = and(b_last, _T_1)
node _r_count_T_1 = not(r_counter1_1)
node r_4_1 = and(r_beats1_1, _r_count_T_1)
when _T_1 :
node _r_counter_T_1 = mux(b_first, r_beats1_1, r_counter1_1)
connect r_counter_1, _r_counter_T_1
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<32>(0h0)
connect _WIRE_2.bits.address, UInt<9>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_2 = and(_WIRE_3.ready, _WIRE_3.valid)
node _r_beats1_decode_T_6 = dshl(UInt<2>(0h3), _WIRE_3.bits.size)
node _r_beats1_decode_T_7 = bits(_r_beats1_decode_T_6, 1, 0)
node _r_beats1_decode_T_8 = not(_r_beats1_decode_T_7)
node r_beats1_decode_2 = shr(_r_beats1_decode_T_8, 2)
node r_beats1_opdata_2 = bits(_WIRE_3.bits.opcode, 0, 0)
node r_beats1_2 = mux(UInt<1>(0h0), r_beats1_decode_2, UInt<1>(0h0))
regreset r_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _r_counter1_T_2 = sub(r_counter_2, UInt<1>(0h1))
node r_counter1_2 = tail(_r_counter1_T_2, 1)
node c_first = eq(r_counter_2, UInt<1>(0h0))
node _r_last_T_4 = eq(r_counter_2, UInt<1>(0h1))
node _r_last_T_5 = eq(r_beats1_2, UInt<1>(0h0))
node c_last = or(_r_last_T_4, _r_last_T_5)
node r_3_2 = and(c_last, _T_2)
node _r_count_T_2 = not(r_counter1_2)
node r_4_2 = and(r_beats1_2, _r_count_T_2)
when _T_2 :
node _r_counter_T_2 = mux(c_first, r_beats1_2, r_counter1_2)
connect r_counter_2, _r_counter_T_2
node _T_3 = and(nodeIn.d.ready, nodeIn.d.valid)
node _r_beats1_decode_T_9 = dshl(UInt<2>(0h3), nodeIn.d.bits.size)
node _r_beats1_decode_T_10 = bits(_r_beats1_decode_T_9, 1, 0)
node _r_beats1_decode_T_11 = not(_r_beats1_decode_T_10)
node r_beats1_decode_3 = shr(_r_beats1_decode_T_11, 2)
node r_beats1_opdata_3 = bits(nodeIn.d.bits.opcode, 0, 0)
node r_beats1_3 = mux(r_beats1_opdata_3, r_beats1_decode_3, UInt<1>(0h0))
regreset r_counter_3 : UInt<1>, clock, reset, UInt<1>(0h0)
node _r_counter1_T_3 = sub(r_counter_3, UInt<1>(0h1))
node r_counter1_3 = tail(_r_counter1_T_3, 1)
node d_first = eq(r_counter_3, UInt<1>(0h0))
node _r_last_T_6 = eq(r_counter_3, UInt<1>(0h1))
node _r_last_T_7 = eq(r_beats1_3, UInt<1>(0h0))
node d_last = or(_r_last_T_6, _r_last_T_7)
node r_3_3 = and(d_last, _T_3)
node _r_count_T_3 = not(r_counter1_3)
node r_4_3 = and(r_beats1_3, _r_count_T_3)
when _T_3 :
node _r_counter_T_3 = mux(d_first, r_beats1_3, r_counter1_3)
connect r_counter_3, _r_counter_T_3
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_4 = and(_WIRE_5.ready, _WIRE_5.valid)
regreset r_counter_4 : UInt<1>, clock, reset, UInt<1>(0h0)
node _r_counter1_T_4 = sub(r_counter_4, UInt<1>(0h1))
node r_counter1_4 = tail(_r_counter1_T_4, 1)
node e_first = eq(r_counter_4, UInt<1>(0h0))
node _r_last_T_8 = eq(r_counter_4, UInt<1>(0h1))
node _r_last_T_9 = eq(UInt<1>(0h0), UInt<1>(0h0))
node e_last = or(_r_last_T_8, _r_last_T_9)
node r_3_4 = and(e_last, _T_4)
node _r_count_T_4 = not(r_counter1_4)
node r_4_4 = and(UInt<1>(0h0), _r_count_T_4)
when _T_4 :
node _r_counter_T_4 = mux(e_first, UInt<1>(0h0), r_counter1_4)
connect r_counter_4, _r_counter_T_4
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<32>(0h0)
connect _WIRE_6.bits.mask, UInt<4>(0h0)
connect _WIRE_6.bits.address, UInt<9>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<32>(0h0)
connect _WIRE_8.bits.mask, UInt<4>(0h0)
connect _WIRE_8.bits.address, UInt<9>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<2>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<32>(0h0)
connect _WIRE_10.bits.address, UInt<9>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_5 = bits(_WIRE_11.bits.opcode, 2, 2)
node _T_6 = bits(_WIRE_11.bits.opcode, 1, 1)
node c_request = and(_T_5, _T_6)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<32>(0h0)
connect _WIRE_12.bits.address, UInt<9>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_7 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_8 = eq(_T_7, UInt<1>(0h0))
node _T_9 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node c_response = or(_T_8, _T_10)
node _T_11 = bits(nodeIn.d.bits.opcode, 2, 2)
node _T_12 = bits(nodeIn.d.bits.opcode, 1, 1)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node d_request = and(_T_11, _T_13)
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_14.bits.sink, UInt<1>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_16.bits.sink, UInt<1>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _a_inc_T = and(nodeIn.a.ready, nodeIn.a.valid)
node _a_inc_T_1 = and(_a_inc_T, a_first)
node a_inc = and(_a_inc_T_1, UInt<1>(0h1))
wire _b_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _b_inc_WIRE.bits.corrupt, UInt<1>(0h0)
connect _b_inc_WIRE.bits.data, UInt<32>(0h0)
connect _b_inc_WIRE.bits.mask, UInt<4>(0h0)
connect _b_inc_WIRE.bits.address, UInt<9>(0h0)
connect _b_inc_WIRE.bits.source, UInt<1>(0h0)
connect _b_inc_WIRE.bits.size, UInt<2>(0h0)
connect _b_inc_WIRE.bits.param, UInt<2>(0h0)
connect _b_inc_WIRE.bits.opcode, UInt<3>(0h0)
connect _b_inc_WIRE.valid, UInt<1>(0h0)
connect _b_inc_WIRE.ready, UInt<1>(0h0)
wire _b_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _b_inc_WIRE_1.bits, _b_inc_WIRE.bits
connect _b_inc_WIRE_1.valid, _b_inc_WIRE.valid
connect _b_inc_WIRE_1.ready, _b_inc_WIRE.ready
node _b_inc_T = and(_b_inc_WIRE_1.ready, _b_inc_WIRE_1.valid)
node _b_inc_T_1 = and(_b_inc_T, b_first)
node b_inc = and(_b_inc_T_1, UInt<1>(0h1))
wire _c_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_inc_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_inc_WIRE.bits.data, UInt<32>(0h0)
connect _c_inc_WIRE.bits.address, UInt<9>(0h0)
connect _c_inc_WIRE.bits.source, UInt<1>(0h0)
connect _c_inc_WIRE.bits.size, UInt<2>(0h0)
connect _c_inc_WIRE.bits.param, UInt<3>(0h0)
connect _c_inc_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_inc_WIRE.valid, UInt<1>(0h0)
connect _c_inc_WIRE.ready, UInt<1>(0h0)
wire _c_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_inc_WIRE_1.bits, _c_inc_WIRE.bits
connect _c_inc_WIRE_1.valid, _c_inc_WIRE.valid
connect _c_inc_WIRE_1.ready, _c_inc_WIRE.ready
node _c_inc_T = and(_c_inc_WIRE_1.ready, _c_inc_WIRE_1.valid)
node _c_inc_T_1 = and(_c_inc_T, c_first)
node c_inc = and(_c_inc_T_1, c_request)
node _d_inc_T = and(nodeIn.d.ready, nodeIn.d.valid)
node _d_inc_T_1 = and(_d_inc_T, d_first)
node d_inc = and(_d_inc_T_1, d_request)
wire _e_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _e_inc_WIRE.bits.sink, UInt<1>(0h0)
connect _e_inc_WIRE.valid, UInt<1>(0h0)
connect _e_inc_WIRE.ready, UInt<1>(0h0)
wire _e_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _e_inc_WIRE_1.bits, _e_inc_WIRE.bits
connect _e_inc_WIRE_1.valid, _e_inc_WIRE.valid
connect _e_inc_WIRE_1.ready, _e_inc_WIRE.ready
node _e_inc_T = and(_e_inc_WIRE_1.ready, _e_inc_WIRE_1.valid)
node _e_inc_T_1 = and(_e_inc_T, e_first)
node e_inc = and(_e_inc_T_1, UInt<1>(0h0))
node inc = cat(a_inc, d_inc)
node _a_dec_T = and(nodeIn.a.ready, nodeIn.a.valid)
node _a_dec_T_1 = and(_a_dec_T, a_last)
node a_dec = and(_a_dec_T_1, UInt<1>(0h0))
wire _b_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _b_dec_WIRE.bits.corrupt, UInt<1>(0h0)
connect _b_dec_WIRE.bits.data, UInt<32>(0h0)
connect _b_dec_WIRE.bits.mask, UInt<4>(0h0)
connect _b_dec_WIRE.bits.address, UInt<9>(0h0)
connect _b_dec_WIRE.bits.source, UInt<1>(0h0)
connect _b_dec_WIRE.bits.size, UInt<2>(0h0)
connect _b_dec_WIRE.bits.param, UInt<2>(0h0)
connect _b_dec_WIRE.bits.opcode, UInt<3>(0h0)
connect _b_dec_WIRE.valid, UInt<1>(0h0)
connect _b_dec_WIRE.ready, UInt<1>(0h0)
wire _b_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _b_dec_WIRE_1.bits, _b_dec_WIRE.bits
connect _b_dec_WIRE_1.valid, _b_dec_WIRE.valid
connect _b_dec_WIRE_1.ready, _b_dec_WIRE.ready
node _b_dec_T = and(_b_dec_WIRE_1.ready, _b_dec_WIRE_1.valid)
node _b_dec_T_1 = and(_b_dec_T, b_last)
node b_dec = and(_b_dec_T_1, UInt<1>(0h0))
wire _c_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_dec_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_dec_WIRE.bits.data, UInt<32>(0h0)
connect _c_dec_WIRE.bits.address, UInt<9>(0h0)
connect _c_dec_WIRE.bits.source, UInt<1>(0h0)
connect _c_dec_WIRE.bits.size, UInt<2>(0h0)
connect _c_dec_WIRE.bits.param, UInt<3>(0h0)
connect _c_dec_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_dec_WIRE.valid, UInt<1>(0h0)
connect _c_dec_WIRE.ready, UInt<1>(0h0)
wire _c_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_dec_WIRE_1.bits, _c_dec_WIRE.bits
connect _c_dec_WIRE_1.valid, _c_dec_WIRE.valid
connect _c_dec_WIRE_1.ready, _c_dec_WIRE.ready
node _c_dec_T = and(_c_dec_WIRE_1.ready, _c_dec_WIRE_1.valid)
node _c_dec_T_1 = and(_c_dec_T, c_last)
node c_dec = and(_c_dec_T_1, c_response)
node _d_dec_T = and(nodeIn.d.ready, nodeIn.d.valid)
node _d_dec_T_1 = and(_d_dec_T, d_last)
node d_dec = and(_d_dec_T_1, UInt<1>(0h1))
wire _e_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _e_dec_WIRE.bits.sink, UInt<1>(0h0)
connect _e_dec_WIRE.valid, UInt<1>(0h0)
connect _e_dec_WIRE.ready, UInt<1>(0h0)
wire _e_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _e_dec_WIRE_1.bits, _e_dec_WIRE.bits
connect _e_dec_WIRE_1.valid, _e_dec_WIRE.valid
connect _e_dec_WIRE_1.ready, _e_dec_WIRE.ready
node _e_dec_T = and(_e_dec_WIRE_1.ready, _e_dec_WIRE_1.valid)
node _e_dec_T_1 = and(_e_dec_T, e_last)
node e_dec = and(_e_dec_T_1, UInt<1>(0h1))
node dec = cat(a_dec, d_dec)
node _next_flight_T = bits(inc, 0, 0)
node _next_flight_T_1 = bits(inc, 1, 1)
node _next_flight_T_2 = add(_next_flight_T, _next_flight_T_1)
node _next_flight_T_3 = bits(_next_flight_T_2, 1, 0)
node _next_flight_T_4 = add(flight, _next_flight_T_3)
node _next_flight_T_5 = tail(_next_flight_T_4, 1)
node _next_flight_T_6 = bits(dec, 0, 0)
node _next_flight_T_7 = bits(dec, 1, 1)
node _next_flight_T_8 = add(_next_flight_T_6, _next_flight_T_7)
node _next_flight_T_9 = bits(_next_flight_T_8, 1, 0)
node _next_flight_T_10 = sub(_next_flight_T_5, _next_flight_T_9)
node next_flight = tail(_next_flight_T_10, 1)
connect flight, next_flight
node _io_pending_T = gt(flight, UInt<1>(0h0))
connect io.pending, _io_pending_T
node _T_14 = eq(next_flight, UInt<1>(0h0))
node _T_15 = or(in_reset, _T_14)
when _T_15 :
connect bypass_reg, io.bypass
node _stall_T = neq(bypass, io.bypass)
node _stall_T_1 = and(nodeIn.a.ready, nodeIn.a.valid)
node _stall_beats1_decode_T = dshl(UInt<2>(0h3), nodeIn.a.bits.size)
node _stall_beats1_decode_T_1 = bits(_stall_beats1_decode_T, 1, 0)
node _stall_beats1_decode_T_2 = not(_stall_beats1_decode_T_1)
node stall_beats1_decode = shr(_stall_beats1_decode_T_2, 2)
node _stall_beats1_opdata_T = bits(nodeIn.a.bits.opcode, 2, 2)
node stall_beats1_opdata = eq(_stall_beats1_opdata_T, UInt<1>(0h0))
node stall_beats1 = mux(stall_beats1_opdata, stall_beats1_decode, UInt<1>(0h0))
regreset stall_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _stall_counter1_T = sub(stall_counter, UInt<1>(0h1))
node stall_counter1 = tail(_stall_counter1_T, 1)
node stall_first = eq(stall_counter, UInt<1>(0h0))
node _stall_last_T = eq(stall_counter, UInt<1>(0h1))
node _stall_last_T_1 = eq(stall_beats1, UInt<1>(0h0))
node stall_last = or(_stall_last_T, _stall_last_T_1)
node stall_done = and(stall_last, _stall_T_1)
node _stall_count_T = not(stall_counter1)
node stall_count = and(stall_beats1, _stall_count_T)
when _stall_T_1 :
node _stall_counter_T = mux(stall_first, stall_beats1, stall_counter1)
connect stall_counter, _stall_counter_T
node stall = and(_stall_T, stall_first)
node _nodeOut_a_valid_T = eq(stall, UInt<1>(0h0))
node _nodeOut_a_valid_T_1 = and(_nodeOut_a_valid_T, nodeIn.a.valid)
node _nodeOut_a_valid_T_2 = and(_nodeOut_a_valid_T_1, bypass)
connect nodeOut.a.valid, _nodeOut_a_valid_T_2
node _nodeOut_a_valid_T_3 = eq(stall, UInt<1>(0h0))
node _nodeOut_a_valid_T_4 = and(_nodeOut_a_valid_T_3, nodeIn.a.valid)
node _nodeOut_a_valid_T_5 = eq(bypass, UInt<1>(0h0))
node _nodeOut_a_valid_T_6 = and(_nodeOut_a_valid_T_4, _nodeOut_a_valid_T_5)
connect x1_nodeOut.a.valid, _nodeOut_a_valid_T_6
node _nodeIn_a_ready_T = eq(stall, UInt<1>(0h0))
node _nodeIn_a_ready_T_1 = mux(bypass, nodeOut.a.ready, x1_nodeOut.a.ready)
node _nodeIn_a_ready_T_2 = and(_nodeIn_a_ready_T, _nodeIn_a_ready_T_1)
connect nodeIn.a.ready, _nodeIn_a_ready_T_2
connect nodeOut.a.bits, nodeIn.a.bits
connect x1_nodeOut.a.bits, nodeIn.a.bits
node _nodeOut_d_ready_T = and(nodeIn.d.ready, bypass)
connect nodeOut.d.ready, _nodeOut_d_ready_T
node _nodeOut_d_ready_T_1 = eq(bypass, UInt<1>(0h0))
node _nodeOut_d_ready_T_2 = and(nodeIn.d.ready, _nodeOut_d_ready_T_1)
connect x1_nodeOut.d.ready, _nodeOut_d_ready_T_2
node _nodeIn_d_valid_T = mux(bypass, nodeOut.d.valid, x1_nodeOut.d.valid)
connect nodeIn.d.valid, _nodeIn_d_valid_T
wire nodeIn_d_bits_out : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}
connect nodeIn_d_bits_out, nodeIn.d.bits
connect nodeIn_d_bits_out, nodeOut.d.bits
wire nodeIn_d_bits_out_1 : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}
connect nodeIn_d_bits_out_1, nodeIn.d.bits
connect nodeIn_d_bits_out_1, x1_nodeOut.d.bits
node _nodeIn_d_bits_T = mux(bypass, nodeIn_d_bits_out, nodeIn_d_bits_out_1)
connect nodeIn.d.bits.corrupt, _nodeIn_d_bits_T.corrupt
connect nodeIn.d.bits.data, _nodeIn_d_bits_T.data
connect nodeIn.d.bits.denied, _nodeIn_d_bits_T.denied
connect nodeIn.d.bits.sink, _nodeIn_d_bits_T.sink
connect nodeIn.d.bits.source, _nodeIn_d_bits_T.source
connect nodeIn.d.bits.size, _nodeIn_d_bits_T.size
connect nodeIn.d.bits.param, _nodeIn_d_bits_T.param
connect nodeIn.d.bits.opcode, _nodeIn_d_bits_T.opcode
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<32>(0h0)
connect _WIRE_18.bits.mask, UInt<4>(0h0)
connect _WIRE_18.bits.address, UInt<9>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<2>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
connect _WIRE_19.valid, UInt<1>(0h0)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<32>(0h0)
connect _WIRE_20.bits.address, UInt<9>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
connect _WIRE_21.ready, UInt<1>(0h1)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_22.bits.sink, UInt<1>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
connect _WIRE_23.ready, UInt<1>(0h1)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<32>(0h0)
connect _WIRE_24.bits.mask, UInt<4>(0h0)
connect _WIRE_24.bits.address, UInt<128>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<2>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
connect _WIRE_25.ready, UInt<1>(0h1)
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<32>(0h0)
connect _WIRE_26.bits.address, UInt<128>(0h0)
connect _WIRE_26.bits.source, UInt<1>(0h0)
connect _WIRE_26.bits.size, UInt<2>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
connect _WIRE_27.valid, UInt<1>(0h0)
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_28.bits.sink, UInt<1>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
connect _WIRE_29.valid, UInt<1>(0h0)
wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_30.bits.corrupt, UInt<1>(0h0)
connect _WIRE_30.bits.data, UInt<32>(0h0)
connect _WIRE_30.bits.mask, UInt<4>(0h0)
connect _WIRE_30.bits.address, UInt<9>(0h0)
connect _WIRE_30.bits.source, UInt<1>(0h0)
connect _WIRE_30.bits.size, UInt<2>(0h0)
connect _WIRE_30.bits.param, UInt<2>(0h0)
connect _WIRE_30.bits.opcode, UInt<3>(0h0)
connect _WIRE_30.valid, UInt<1>(0h0)
connect _WIRE_30.ready, UInt<1>(0h0)
wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_31.bits, _WIRE_30.bits
connect _WIRE_31.valid, _WIRE_30.valid
connect _WIRE_31.ready, _WIRE_30.ready
connect _WIRE_31.ready, UInt<1>(0h1)
wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_32.bits.corrupt, UInt<1>(0h0)
connect _WIRE_32.bits.data, UInt<32>(0h0)
connect _WIRE_32.bits.address, UInt<9>(0h0)
connect _WIRE_32.bits.source, UInt<1>(0h0)
connect _WIRE_32.bits.size, UInt<2>(0h0)
connect _WIRE_32.bits.param, UInt<3>(0h0)
connect _WIRE_32.bits.opcode, UInt<3>(0h0)
connect _WIRE_32.valid, UInt<1>(0h0)
connect _WIRE_32.ready, UInt<1>(0h0)
wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_33.bits, _WIRE_32.bits
connect _WIRE_33.valid, _WIRE_32.valid
connect _WIRE_33.ready, _WIRE_32.ready
connect _WIRE_33.valid, UInt<1>(0h0)
wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_34.bits.sink, UInt<1>(0h0)
connect _WIRE_34.valid, UInt<1>(0h0)
connect _WIRE_34.ready, UInt<1>(0h0)
wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_35.bits, _WIRE_34.bits
connect _WIRE_35.valid, _WIRE_34.valid
connect _WIRE_35.ready, _WIRE_34.ready
connect _WIRE_35.valid, UInt<1>(0h0)
extmodule plusarg_reader_102 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_103 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLBusBypassBar( // @[BusBypass.scala:66:9]
input clock, // @[BusBypass.scala:66:9]
input reset, // @[BusBypass.scala:66:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [8:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [8:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input io_bypass // @[BusBypass.scala:67:16]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[BusBypass.scala:66:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[BusBypass.scala:66:9]
wire [8:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[BusBypass.scala:66:9]
wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[BusBypass.scala:66:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[BusBypass.scala:66:9]
wire auto_out_1_a_ready_0 = auto_out_1_a_ready; // @[BusBypass.scala:66:9]
wire auto_out_1_d_valid_0 = auto_out_1_d_valid; // @[BusBypass.scala:66:9]
wire [2:0] auto_out_1_d_bits_opcode_0 = auto_out_1_d_bits_opcode; // @[BusBypass.scala:66:9]
wire [1:0] auto_out_1_d_bits_param_0 = auto_out_1_d_bits_param; // @[BusBypass.scala:66:9]
wire [1:0] auto_out_1_d_bits_size_0 = auto_out_1_d_bits_size; // @[BusBypass.scala:66:9]
wire auto_out_1_d_bits_source_0 = auto_out_1_d_bits_source; // @[BusBypass.scala:66:9]
wire auto_out_1_d_bits_sink_0 = auto_out_1_d_bits_sink; // @[BusBypass.scala:66:9]
wire auto_out_1_d_bits_denied_0 = auto_out_1_d_bits_denied; // @[BusBypass.scala:66:9]
wire [31:0] auto_out_1_d_bits_data_0 = auto_out_1_d_bits_data; // @[BusBypass.scala:66:9]
wire auto_out_1_d_bits_corrupt_0 = auto_out_1_d_bits_corrupt; // @[BusBypass.scala:66:9]
wire auto_out_0_a_ready_0 = auto_out_0_a_ready; // @[BusBypass.scala:66:9]
wire auto_out_0_d_valid_0 = auto_out_0_d_valid; // @[BusBypass.scala:66:9]
wire [2:0] auto_out_0_d_bits_opcode_0 = auto_out_0_d_bits_opcode; // @[BusBypass.scala:66:9]
wire [1:0] auto_out_0_d_bits_param_0 = auto_out_0_d_bits_param; // @[BusBypass.scala:66:9]
wire [1:0] auto_out_0_d_bits_size_0 = auto_out_0_d_bits_size; // @[BusBypass.scala:66:9]
wire auto_out_0_d_bits_denied_0 = auto_out_0_d_bits_denied; // @[BusBypass.scala:66:9]
wire auto_out_0_d_bits_corrupt_0 = auto_out_0_d_bits_corrupt; // @[BusBypass.scala:66:9]
wire io_bypass_0 = io_bypass; // @[BusBypass.scala:66:9]
wire [4:0] _r_beats1_decode_T_3 = 5'h3; // @[package.scala:243:71]
wire [4:0] _r_beats1_decode_T_6 = 5'h3; // @[package.scala:243:71]
wire [3:0] _b_inc_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _b_inc_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _b_dec_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _b_dec_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61]
wire [8:0] _b_inc_WIRE_bits_address = 9'h0; // @[Bundles.scala:264:74]
wire [8:0] _b_inc_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:264:61]
wire [8:0] _c_inc_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_inc_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _b_dec_WIRE_bits_address = 9'h0; // @[Bundles.scala:264:74]
wire [8:0] _b_dec_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:264:61]
wire [8:0] _c_dec_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_dec_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [4:0] _r_beats1_decode_T = 5'hC; // @[package.scala:243:71]
wire [4:0] _stall_beats1_decode_T = 5'hC; // @[package.scala:243:71]
wire [1:0] _r_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76]
wire [1:0] _r_beats1_decode_T_5 = 2'h0; // @[package.scala:243:46]
wire [1:0] _r_beats1_decode_T_8 = 2'h0; // @[package.scala:243:46]
wire [1:0] _b_inc_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _b_inc_WIRE_bits_size = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _b_inc_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _b_inc_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _c_inc_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_inc_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _b_dec_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _b_dec_WIRE_bits_size = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _b_dec_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _b_dec_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _c_dec_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_dec_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _stall_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76]
wire [31:0] auto_out_0_d_bits_data = 32'h0; // @[BusBypass.scala:66:9]
wire [31:0] nodeOut_d_bits_data = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] _b_inc_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _b_inc_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _c_inc_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_inc_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _b_dec_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _b_dec_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _c_dec_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_dec_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] nodeIn_d_bits_out_data = 32'h0; // @[BusBypass.scala:97:53]
wire [3:0] auto_in_a_bits_mask = 4'hF; // @[Nodes.scala:27:25]
wire [3:0] auto_out_1_a_bits_mask = 4'hF; // @[Nodes.scala:27:25]
wire [3:0] auto_out_0_a_bits_mask = 4'hF; // @[Nodes.scala:27:25]
wire [3:0] nodeIn_a_bits_mask = 4'hF; // @[Nodes.scala:27:25]
wire [3:0] nodeOut_a_bits_mask = 4'hF; // @[Nodes.scala:27:25]
wire [3:0] x1_nodeOut_a_bits_mask = 4'hF; // @[Nodes.scala:27:25]
wire [1:0] auto_in_a_bits_size = 2'h2; // @[Nodes.scala:27:25]
wire [1:0] auto_out_1_a_bits_size = 2'h2; // @[Nodes.scala:27:25]
wire [1:0] auto_out_0_a_bits_size = 2'h2; // @[Nodes.scala:27:25]
wire [1:0] nodeIn_a_bits_size = 2'h2; // @[Nodes.scala:27:25]
wire [1:0] nodeOut_a_bits_size = 2'h2; // @[Nodes.scala:27:25]
wire [1:0] x1_nodeOut_a_bits_size = 2'h2; // @[Nodes.scala:27:25]
wire [2:0] auto_in_a_bits_param = 3'h0; // @[BusBypass.scala:66:9]
wire [2:0] auto_out_1_a_bits_param = 3'h0; // @[BusBypass.scala:66:9]
wire [2:0] auto_out_0_a_bits_param = 3'h0; // @[BusBypass.scala:66:9]
wire [2:0] nodeIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] _b_inc_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _b_inc_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _c_inc_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_inc_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_inc_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_inc_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _b_dec_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _b_dec_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _c_dec_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_dec_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_dec_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_dec_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [1:0] _r_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46]
wire [1:0] _r_beats1_decode_T_4 = 2'h3; // @[package.scala:243:76]
wire [1:0] _r_counter1_T_1 = 2'h3; // @[Edges.scala:230:28]
wire [1:0] _r_beats1_decode_T_7 = 2'h3; // @[package.scala:243:76]
wire [1:0] _r_counter1_T_2 = 2'h3; // @[Edges.scala:230:28]
wire [1:0] _r_counter1_T_4 = 2'h3; // @[Edges.scala:230:28]
wire [1:0] _stall_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46]
wire _r_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_last = 1'h1; // @[Edges.scala:232:33]
wire r_beats1_opdata_1 = 1'h1; // @[Edges.scala:97:28]
wire r_counter1_1 = 1'h1; // @[Edges.scala:230:28]
wire b_first = 1'h1; // @[Edges.scala:231:25]
wire _r_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire b_last = 1'h1; // @[Edges.scala:232:33]
wire r_counter1_2 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _r_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire c_last = 1'h1; // @[Edges.scala:232:33]
wire _r_last_T_7 = 1'h1; // @[Edges.scala:232:43]
wire d_last = 1'h1; // @[Edges.scala:232:33]
wire r_counter1_4 = 1'h1; // @[Edges.scala:230:28]
wire e_first = 1'h1; // @[Edges.scala:231:25]
wire _r_last_T_9 = 1'h1; // @[Edges.scala:232:43]
wire e_last = 1'h1; // @[Edges.scala:232:33]
wire c_response = 1'h1; // @[Edges.scala:82:41]
wire _stall_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire stall_last = 1'h1; // @[Edges.scala:232:33]
wire auto_in_a_bits_source = 1'h0; // @[BusBypass.scala:66:9]
wire auto_in_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9]
wire auto_out_1_a_bits_source = 1'h0; // @[BusBypass.scala:66:9]
wire auto_out_1_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9]
wire auto_out_0_a_bits_source = 1'h0; // @[BusBypass.scala:66:9]
wire auto_out_0_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9]
wire auto_out_0_d_bits_source = 1'h0; // @[BusBypass.scala:66:9]
wire auto_out_0_d_bits_sink = 1'h0; // @[BusBypass.scala:66:9]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17]
wire x1_nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire x1_nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire r_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire r_beats1 = 1'h0; // @[Edges.scala:221:14]
wire r_4 = 1'h0; // @[Edges.scala:234:25]
wire r_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire _r_beats1_opdata_T_1 = 1'h0; // @[Edges.scala:97:37]
wire r_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire _r_last_T_2 = 1'h0; // @[Edges.scala:232:25]
wire r_3_1 = 1'h0; // @[Edges.scala:233:22]
wire _r_count_T_1 = 1'h0; // @[Edges.scala:234:27]
wire r_4_1 = 1'h0; // @[Edges.scala:234:25]
wire _r_counter_T_1 = 1'h0; // @[Edges.scala:236:21]
wire r_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire r_beats1_opdata_2 = 1'h0; // @[Edges.scala:102:36]
wire r_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire _r_last_T_4 = 1'h0; // @[Edges.scala:232:25]
wire r_3_2 = 1'h0; // @[Edges.scala:233:22]
wire _r_count_T_2 = 1'h0; // @[Edges.scala:234:27]
wire r_4_2 = 1'h0; // @[Edges.scala:234:25]
wire _r_counter_T_2 = 1'h0; // @[Edges.scala:236:21]
wire r_beats1_decode_3 = 1'h0; // @[Edges.scala:220:59]
wire r_beats1_3 = 1'h0; // @[Edges.scala:221:14]
wire r_4_3 = 1'h0; // @[Edges.scala:234:25]
wire _r_last_T_8 = 1'h0; // @[Edges.scala:232:25]
wire r_3_4 = 1'h0; // @[Edges.scala:233:22]
wire _r_count_T_4 = 1'h0; // @[Edges.scala:234:27]
wire r_4_4 = 1'h0; // @[Edges.scala:234:25]
wire _r_counter_T_4 = 1'h0; // @[Edges.scala:236:21]
wire c_request = 1'h0; // @[Edges.scala:68:40]
wire _b_inc_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _b_inc_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _b_inc_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74]
wire _b_inc_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _b_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _b_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _b_inc_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61]
wire _b_inc_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _b_inc_T = 1'h0; // @[Decoupled.scala:51:35]
wire _b_inc_T_1 = 1'h0; // @[Edges.scala:311:26]
wire b_inc = 1'h0; // @[Edges.scala:311:37]
wire _c_inc_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_inc_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_inc_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_inc_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_inc_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_inc_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_inc_T = 1'h0; // @[Decoupled.scala:51:35]
wire _c_inc_T_1 = 1'h0; // @[Edges.scala:312:26]
wire c_inc = 1'h0; // @[Edges.scala:312:37]
wire _e_inc_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _e_inc_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _e_inc_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _e_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _e_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _e_inc_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _e_inc_T = 1'h0; // @[Decoupled.scala:51:35]
wire _e_inc_T_1 = 1'h0; // @[Edges.scala:314:26]
wire e_inc = 1'h0; // @[Edges.scala:314:37]
wire a_dec = 1'h0; // @[Edges.scala:317:36]
wire _b_dec_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _b_dec_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _b_dec_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74]
wire _b_dec_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _b_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _b_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _b_dec_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61]
wire _b_dec_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _b_dec_T = 1'h0; // @[Decoupled.scala:51:35]
wire _b_dec_T_1 = 1'h0; // @[Edges.scala:318:26]
wire b_dec = 1'h0; // @[Edges.scala:318:36]
wire _c_dec_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_dec_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_dec_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_dec_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_dec_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_dec_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_dec_T = 1'h0; // @[Decoupled.scala:51:35]
wire _c_dec_T_1 = 1'h0; // @[Edges.scala:319:26]
wire c_dec = 1'h0; // @[Edges.scala:319:36]
wire _e_dec_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _e_dec_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _e_dec_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _e_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _e_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _e_dec_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _e_dec_T = 1'h0; // @[Decoupled.scala:51:35]
wire _e_dec_T_1 = 1'h0; // @[Edges.scala:321:26]
wire e_dec = 1'h0; // @[Edges.scala:321:36]
wire stall_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire stall_beats1 = 1'h0; // @[Edges.scala:221:14]
wire stall_count = 1'h0; // @[Edges.scala:234:25]
wire nodeIn_d_bits_out_source = 1'h0; // @[BusBypass.scala:97:53]
wire nodeIn_d_bits_out_sink = 1'h0; // @[BusBypass.scala:97:53]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[BusBypass.scala:66:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[BusBypass.scala:66:9]
wire [8:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[BusBypass.scala:66:9]
wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[BusBypass.scala:66:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[BusBypass.scala:66:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire x1_nodeOut_a_ready = auto_out_1_a_ready_0; // @[BusBypass.scala:66:9]
wire x1_nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [8:0] x1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [31:0] x1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire x1_nodeOut_d_valid = auto_out_1_d_valid_0; // @[BusBypass.scala:66:9]
wire [2:0] x1_nodeOut_d_bits_opcode = auto_out_1_d_bits_opcode_0; // @[BusBypass.scala:66:9]
wire [1:0] x1_nodeOut_d_bits_param = auto_out_1_d_bits_param_0; // @[BusBypass.scala:66:9]
wire [1:0] x1_nodeOut_d_bits_size = auto_out_1_d_bits_size_0; // @[BusBypass.scala:66:9]
wire x1_nodeOut_d_bits_source = auto_out_1_d_bits_source_0; // @[BusBypass.scala:66:9]
wire x1_nodeOut_d_bits_sink = auto_out_1_d_bits_sink_0; // @[BusBypass.scala:66:9]
wire x1_nodeOut_d_bits_denied = auto_out_1_d_bits_denied_0; // @[BusBypass.scala:66:9]
wire [31:0] x1_nodeOut_d_bits_data = auto_out_1_d_bits_data_0; // @[BusBypass.scala:66:9]
wire x1_nodeOut_d_bits_corrupt = auto_out_1_d_bits_corrupt_0; // @[BusBypass.scala:66:9]
wire nodeOut_a_ready = auto_out_0_a_ready_0; // @[BusBypass.scala:66:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [127:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_0_d_valid_0; // @[BusBypass.scala:66:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_0_d_bits_opcode_0; // @[BusBypass.scala:66:9]
wire [1:0] nodeOut_d_bits_param = auto_out_0_d_bits_param_0; // @[BusBypass.scala:66:9]
wire [1:0] nodeOut_d_bits_size = auto_out_0_d_bits_size_0; // @[BusBypass.scala:66:9]
wire nodeOut_d_bits_denied = auto_out_0_d_bits_denied_0; // @[BusBypass.scala:66:9]
wire nodeOut_d_bits_corrupt = auto_out_0_d_bits_corrupt_0; // @[BusBypass.scala:66:9]
wire _io_pending_T; // @[BusBypass.scala:84:27]
wire auto_in_a_ready_0; // @[BusBypass.scala:66:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[BusBypass.scala:66:9]
wire [1:0] auto_in_d_bits_param_0; // @[BusBypass.scala:66:9]
wire [1:0] auto_in_d_bits_size_0; // @[BusBypass.scala:66:9]
wire auto_in_d_bits_source_0; // @[BusBypass.scala:66:9]
wire auto_in_d_bits_sink_0; // @[BusBypass.scala:66:9]
wire auto_in_d_bits_denied_0; // @[BusBypass.scala:66:9]
wire [31:0] auto_in_d_bits_data_0; // @[BusBypass.scala:66:9]
wire auto_in_d_bits_corrupt_0; // @[BusBypass.scala:66:9]
wire auto_in_d_valid_0; // @[BusBypass.scala:66:9]
wire [2:0] auto_out_1_a_bits_opcode_0; // @[BusBypass.scala:66:9]
wire [8:0] auto_out_1_a_bits_address_0; // @[BusBypass.scala:66:9]
wire [31:0] auto_out_1_a_bits_data_0; // @[BusBypass.scala:66:9]
wire auto_out_1_a_valid_0; // @[BusBypass.scala:66:9]
wire auto_out_1_d_ready_0; // @[BusBypass.scala:66:9]
wire [2:0] auto_out_0_a_bits_opcode_0; // @[BusBypass.scala:66:9]
wire [127:0] auto_out_0_a_bits_address_0; // @[BusBypass.scala:66:9]
wire [31:0] auto_out_0_a_bits_data_0; // @[BusBypass.scala:66:9]
wire auto_out_0_a_valid_0; // @[BusBypass.scala:66:9]
wire auto_out_0_d_ready_0; // @[BusBypass.scala:66:9]
wire io_pending; // @[BusBypass.scala:66:9]
wire _nodeIn_a_ready_T_2; // @[BusBypass.scala:90:28]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[BusBypass.scala:66:9]
assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_address = nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire _nodeIn_d_valid_T; // @[BusBypass.scala:96:24]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[BusBypass.scala:66:9]
wire [2:0] _nodeIn_d_bits_T_opcode; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[BusBypass.scala:66:9]
wire [1:0] _nodeIn_d_bits_T_param; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[BusBypass.scala:66:9]
wire [1:0] _nodeIn_d_bits_T_size; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[BusBypass.scala:66:9]
wire _nodeIn_d_bits_T_source; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[BusBypass.scala:66:9]
wire _nodeIn_d_bits_T_sink; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[BusBypass.scala:66:9]
wire _nodeIn_d_bits_T_denied; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[BusBypass.scala:66:9]
wire [31:0] _nodeIn_d_bits_T_data; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[BusBypass.scala:66:9]
wire _nodeIn_d_bits_T_corrupt; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[BusBypass.scala:66:9]
wire _nodeOut_a_valid_T_2; // @[BusBypass.scala:88:42]
assign auto_out_0_a_valid_0 = nodeOut_a_valid; // @[BusBypass.scala:66:9]
assign auto_out_0_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[BusBypass.scala:66:9]
assign auto_out_0_a_bits_address_0 = nodeOut_a_bits_address; // @[BusBypass.scala:66:9]
assign auto_out_0_a_bits_data_0 = nodeOut_a_bits_data; // @[BusBypass.scala:66:9]
wire _nodeOut_d_ready_T; // @[BusBypass.scala:94:32]
assign auto_out_0_d_ready_0 = nodeOut_d_ready; // @[BusBypass.scala:66:9]
wire [2:0] nodeIn_d_bits_out_opcode = nodeOut_d_bits_opcode; // @[BusBypass.scala:97:53]
wire [1:0] nodeIn_d_bits_out_param = nodeOut_d_bits_param; // @[BusBypass.scala:97:53]
wire [1:0] nodeIn_d_bits_out_size = nodeOut_d_bits_size; // @[BusBypass.scala:97:53]
wire nodeIn_d_bits_out_denied = nodeOut_d_bits_denied; // @[BusBypass.scala:97:53]
wire nodeIn_d_bits_out_corrupt = nodeOut_d_bits_corrupt; // @[BusBypass.scala:97:53]
wire _nodeOut_a_valid_T_6; // @[BusBypass.scala:89:42]
assign auto_out_1_a_valid_0 = x1_nodeOut_a_valid; // @[BusBypass.scala:66:9]
assign auto_out_1_a_bits_opcode_0 = x1_nodeOut_a_bits_opcode; // @[BusBypass.scala:66:9]
assign auto_out_1_a_bits_address_0 = x1_nodeOut_a_bits_address; // @[BusBypass.scala:66:9]
assign auto_out_1_a_bits_data_0 = x1_nodeOut_a_bits_data; // @[BusBypass.scala:66:9]
wire _nodeOut_d_ready_T_2; // @[BusBypass.scala:95:32]
assign auto_out_1_d_ready_0 = x1_nodeOut_d_ready; // @[BusBypass.scala:66:9]
wire [2:0] nodeIn_d_bits_out_1_opcode = x1_nodeOut_d_bits_opcode; // @[BusBypass.scala:97:53]
wire [1:0] nodeIn_d_bits_out_1_param = x1_nodeOut_d_bits_param; // @[BusBypass.scala:97:53]
wire [1:0] nodeIn_d_bits_out_1_size = x1_nodeOut_d_bits_size; // @[BusBypass.scala:97:53]
wire nodeIn_d_bits_out_1_source = x1_nodeOut_d_bits_source; // @[BusBypass.scala:97:53]
wire nodeIn_d_bits_out_1_sink = x1_nodeOut_d_bits_sink; // @[BusBypass.scala:97:53]
wire nodeIn_d_bits_out_1_denied = x1_nodeOut_d_bits_denied; // @[BusBypass.scala:97:53]
wire [31:0] nodeIn_d_bits_out_1_data = x1_nodeOut_d_bits_data; // @[BusBypass.scala:97:53]
wire nodeIn_d_bits_out_1_corrupt = x1_nodeOut_d_bits_corrupt; // @[BusBypass.scala:97:53]
reg in_reset; // @[BusBypass.scala:79:27]
reg bypass_reg; // @[BusBypass.scala:80:25]
wire bypass = in_reset ? io_bypass_0 : bypass_reg; // @[BusBypass.scala:66:9, :79:27, :80:25, :81:21]
reg [1:0] flight; // @[Edges.scala:295:25]
wire _T = nodeIn_a_ready & nodeIn_a_valid; // @[Decoupled.scala:51:35]
wire r_3; // @[Edges.scala:233:22]
assign r_3 = _T; // @[Decoupled.scala:51:35]
wire _a_inc_T; // @[Decoupled.scala:51:35]
assign _a_inc_T = _T; // @[Decoupled.scala:51:35]
wire _a_dec_T; // @[Decoupled.scala:51:35]
assign _a_dec_T = _T; // @[Decoupled.scala:51:35]
wire _stall_T_1; // @[Decoupled.scala:51:35]
assign _stall_T_1 = _T; // @[Decoupled.scala:51:35]
wire _r_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire _stall_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire r_beats1_opdata = ~_r_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg r_counter; // @[Edges.scala:229:27]
wire _r_last_T = r_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _r_counter1_T = {1'h0, r_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire r_counter1 = _r_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~r_counter; // @[Edges.scala:229:27, :231:25]
wire _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27]
wire _r_counter_T = ~a_first & r_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
wire _T_3 = nodeIn_d_ready & nodeIn_d_valid; // @[Decoupled.scala:51:35]
wire r_3_3; // @[Edges.scala:233:22]
assign r_3_3 = _T_3; // @[Decoupled.scala:51:35]
wire _d_inc_T; // @[Decoupled.scala:51:35]
assign _d_inc_T = _T_3; // @[Decoupled.scala:51:35]
wire _d_dec_T; // @[Decoupled.scala:51:35]
assign _d_dec_T = _T_3; // @[Decoupled.scala:51:35]
wire [4:0] _r_beats1_decode_T_9 = 5'h3 << nodeIn_d_bits_size; // @[package.scala:243:71]
wire [1:0] _r_beats1_decode_T_10 = _r_beats1_decode_T_9[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _r_beats1_decode_T_11 = ~_r_beats1_decode_T_10; // @[package.scala:243:{46,76}]
wire r_beats1_opdata_3 = nodeIn_d_bits_opcode[0]; // @[Edges.scala:106:36]
reg r_counter_3; // @[Edges.scala:229:27]
wire _r_last_T_6 = r_counter_3; // @[Edges.scala:229:27, :232:25]
wire [1:0] _r_counter1_T_3 = {1'h0, r_counter_3} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire r_counter1_3 = _r_counter1_T_3[0]; // @[Edges.scala:230:28]
wire d_first = ~r_counter_3; // @[Edges.scala:229:27, :231:25]
wire _r_count_T_3 = ~r_counter1_3; // @[Edges.scala:230:28, :234:27]
wire _r_counter_T_3 = ~d_first & r_counter1_3; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_request = nodeIn_d_bits_opcode[2] & ~(nodeIn_d_bits_opcode[1]); // @[Edges.scala:71:{36,40,43,52}]
wire _a_inc_T_1 = _a_inc_T & a_first; // @[Decoupled.scala:51:35]
wire a_inc = _a_inc_T_1; // @[Edges.scala:310:{26,37}]
wire _d_inc_T_1 = _d_inc_T & d_first; // @[Decoupled.scala:51:35]
wire d_inc = _d_inc_T_1 & d_request; // @[Edges.scala:71:40, :313:{26,37}]
wire [1:0] inc = {a_inc, d_inc}; // @[Edges.scala:310:37, :313:37, :315:18]
wire _a_dec_T_1 = _a_dec_T; // @[Decoupled.scala:51:35]
wire _d_dec_T_1 = _d_dec_T; // @[Decoupled.scala:51:35]
wire d_dec = _d_dec_T_1; // @[Edges.scala:320:{26,36}]
wire [1:0] dec = {1'h0, d_dec}; // @[Edges.scala:320:36, :322:18]
wire _next_flight_T = inc[0]; // @[Edges.scala:315:18, :324:40]
wire _next_flight_T_1 = inc[1]; // @[Edges.scala:315:18, :324:40]
wire [1:0] _next_flight_T_2 = {1'h0, _next_flight_T} + {1'h0, _next_flight_T_1}; // @[Edges.scala:324:40]
wire [1:0] _next_flight_T_3 = _next_flight_T_2; // @[Edges.scala:324:40]
wire [2:0] _next_flight_T_4 = {1'h0, flight} + {1'h0, _next_flight_T_3}; // @[Edges.scala:295:25, :324:{30,40}]
wire [1:0] _next_flight_T_5 = _next_flight_T_4[1:0]; // @[Edges.scala:324:30]
wire _next_flight_T_6 = dec[0]; // @[Edges.scala:322:18, :324:56]
wire _next_flight_T_7 = dec[1]; // @[Edges.scala:322:18, :324:56]
wire [1:0] _next_flight_T_8 = {1'h0, _next_flight_T_6} + {1'h0, _next_flight_T_7}; // @[Edges.scala:324:56]
wire [1:0] _next_flight_T_9 = _next_flight_T_8; // @[Edges.scala:324:56]
wire [2:0] _next_flight_T_10 = {1'h0, _next_flight_T_5} - {1'h0, _next_flight_T_9}; // @[Edges.scala:324:{30,46,56}]
wire [1:0] next_flight = _next_flight_T_10[1:0]; // @[Edges.scala:324:46]
assign _io_pending_T = |flight; // @[Edges.scala:295:25]
assign io_pending = _io_pending_T; // @[BusBypass.scala:66:9, :84:27]
wire _stall_T = bypass != io_bypass_0; // @[BusBypass.scala:66:9, :81:21, :86:25]
wire stall_done = _stall_T_1; // @[Decoupled.scala:51:35]
wire stall_beats1_opdata = ~_stall_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg stall_counter; // @[Edges.scala:229:27]
wire _stall_last_T = stall_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _stall_counter1_T = {1'h0, stall_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire stall_counter1 = _stall_counter1_T[0]; // @[Edges.scala:230:28]
wire stall_first = ~stall_counter; // @[Edges.scala:229:27, :231:25]
wire _stall_count_T = ~stall_counter1; // @[Edges.scala:230:28, :234:27]
wire _stall_counter_T = ~stall_first & stall_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
wire stall = _stall_T & stall_first; // @[Edges.scala:231:25]
wire _nodeOut_a_valid_T = ~stall; // @[BusBypass.scala:86:40, :88:21]
wire _nodeOut_a_valid_T_1 = _nodeOut_a_valid_T & nodeIn_a_valid; // @[BusBypass.scala:88:{21,28}]
assign _nodeOut_a_valid_T_2 = _nodeOut_a_valid_T_1 & bypass; // @[BusBypass.scala:81:21, :88:{28,42}]
assign nodeOut_a_valid = _nodeOut_a_valid_T_2; // @[BusBypass.scala:88:42]
wire _nodeOut_a_valid_T_3 = ~stall; // @[BusBypass.scala:86:40, :88:21, :89:21]
wire _nodeOut_a_valid_T_4 = _nodeOut_a_valid_T_3 & nodeIn_a_valid; // @[BusBypass.scala:89:{21,28}]
wire _nodeOut_a_valid_T_5 = ~bypass; // @[BusBypass.scala:81:21, :89:45]
assign _nodeOut_a_valid_T_6 = _nodeOut_a_valid_T_4 & _nodeOut_a_valid_T_5; // @[BusBypass.scala:89:{28,42,45}]
assign x1_nodeOut_a_valid = _nodeOut_a_valid_T_6; // @[BusBypass.scala:89:42]
wire _nodeIn_a_ready_T = ~stall; // @[BusBypass.scala:86:40, :88:21, :90:21]
wire _nodeIn_a_ready_T_1 = bypass ? nodeOut_a_ready : x1_nodeOut_a_ready; // @[BusBypass.scala:81:21, :90:34]
assign _nodeIn_a_ready_T_2 = _nodeIn_a_ready_T & _nodeIn_a_ready_T_1; // @[BusBypass.scala:90:{21,28,34}]
assign nodeIn_a_ready = _nodeIn_a_ready_T_2; // @[BusBypass.scala:90:28]
assign nodeOut_a_bits_address = {119'h0, nodeIn_a_bits_address}; // @[BusBypass.scala:91:18]
assign _nodeOut_d_ready_T = nodeIn_d_ready & bypass; // @[BusBypass.scala:81:21, :94:32]
assign nodeOut_d_ready = _nodeOut_d_ready_T; // @[BusBypass.scala:94:32]
wire _nodeOut_d_ready_T_1 = ~bypass; // @[BusBypass.scala:81:21, :89:45, :95:35]
assign _nodeOut_d_ready_T_2 = nodeIn_d_ready & _nodeOut_d_ready_T_1; // @[BusBypass.scala:95:{32,35}]
assign x1_nodeOut_d_ready = _nodeOut_d_ready_T_2; // @[BusBypass.scala:95:32]
assign _nodeIn_d_valid_T = bypass ? nodeOut_d_valid : x1_nodeOut_d_valid; // @[BusBypass.scala:81:21, :96:24]
assign nodeIn_d_valid = _nodeIn_d_valid_T; // @[BusBypass.scala:96:24]
assign _nodeIn_d_bits_T_opcode = bypass ? nodeIn_d_bits_out_opcode : nodeIn_d_bits_out_1_opcode; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign _nodeIn_d_bits_T_param = bypass ? nodeIn_d_bits_out_param : nodeIn_d_bits_out_1_param; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign _nodeIn_d_bits_T_size = bypass ? nodeIn_d_bits_out_size : nodeIn_d_bits_out_1_size; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign _nodeIn_d_bits_T_source = ~bypass & nodeIn_d_bits_out_1_source; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign _nodeIn_d_bits_T_sink = ~bypass & nodeIn_d_bits_out_1_sink; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign _nodeIn_d_bits_T_denied = bypass ? nodeIn_d_bits_out_denied : nodeIn_d_bits_out_1_denied; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign _nodeIn_d_bits_T_data = bypass ? 32'h0 : nodeIn_d_bits_out_1_data; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign _nodeIn_d_bits_T_corrupt = bypass ? nodeIn_d_bits_out_corrupt : nodeIn_d_bits_out_1_corrupt; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign nodeIn_d_bits_opcode = _nodeIn_d_bits_T_opcode; // @[BusBypass.scala:98:21]
assign nodeIn_d_bits_param = _nodeIn_d_bits_T_param; // @[BusBypass.scala:98:21]
assign nodeIn_d_bits_size = _nodeIn_d_bits_T_size; // @[BusBypass.scala:98:21]
assign nodeIn_d_bits_source = _nodeIn_d_bits_T_source; // @[BusBypass.scala:98:21]
assign nodeIn_d_bits_sink = _nodeIn_d_bits_T_sink; // @[BusBypass.scala:98:21]
assign nodeIn_d_bits_denied = _nodeIn_d_bits_T_denied; // @[BusBypass.scala:98:21]
assign nodeIn_d_bits_data = _nodeIn_d_bits_T_data; // @[BusBypass.scala:98:21]
assign nodeIn_d_bits_corrupt = _nodeIn_d_bits_T_corrupt; // @[BusBypass.scala:98:21]
always @(posedge clock) begin // @[BusBypass.scala:66:9]
if (reset) begin // @[BusBypass.scala:66:9]
in_reset <= 1'h1; // @[BusBypass.scala:79:27]
flight <= 2'h0; // @[Edges.scala:295:25]
r_counter <= 1'h0; // @[Edges.scala:229:27]
r_counter_3 <= 1'h0; // @[Edges.scala:229:27]
stall_counter <= 1'h0; // @[Edges.scala:229:27]
end
else begin // @[BusBypass.scala:66:9]
in_reset <= 1'h0; // @[BusBypass.scala:79:27]
flight <= next_flight; // @[Edges.scala:295:25, :324:46]
if (_T) // @[Decoupled.scala:51:35]
r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21]
if (_T_3) // @[Decoupled.scala:51:35]
r_counter_3 <= _r_counter_T_3; // @[Edges.scala:229:27, :236:21]
if (_stall_T_1) // @[Decoupled.scala:51:35]
stall_counter <= _stall_counter_T; // @[Edges.scala:229:27, :236:21]
end
if (in_reset | next_flight == 2'h0) // @[Edges.scala:324:46]
bypass_reg <= io_bypass_0; // @[BusBypass.scala:66:9, :80:25]
always @(posedge)
TLMonitor_50 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
assign auto_in_a_ready = auto_in_a_ready_0; // @[BusBypass.scala:66:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[BusBypass.scala:66:9]
assign auto_out_1_a_valid = auto_out_1_a_valid_0; // @[BusBypass.scala:66:9]
assign auto_out_1_a_bits_opcode = auto_out_1_a_bits_opcode_0; // @[BusBypass.scala:66:9]
assign auto_out_1_a_bits_address = auto_out_1_a_bits_address_0; // @[BusBypass.scala:66:9]
assign auto_out_1_a_bits_data = auto_out_1_a_bits_data_0; // @[BusBypass.scala:66:9]
assign auto_out_1_d_ready = auto_out_1_d_ready_0; // @[BusBypass.scala:66:9]
assign auto_out_0_a_valid = auto_out_0_a_valid_0; // @[BusBypass.scala:66:9]
assign auto_out_0_a_bits_opcode = auto_out_0_a_bits_opcode_0; // @[BusBypass.scala:66:9]
assign auto_out_0_a_bits_address = auto_out_0_a_bits_address_0; // @[BusBypass.scala:66:9]
assign auto_out_0_a_bits_data = auto_out_0_a_bits_data_0; // @[BusBypass.scala:66:9]
assign auto_out_0_d_ready = auto_out_0_d_ready_0; // @[BusBypass.scala:66:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLInterconnectCoupler_pbus_to_device_named_uart_0 :
input clock : Clock
input reset : Reset
output auto : { control_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
inst fragmenter of TLFragmenter_UART
connect fragmenter.clock, clock
connect fragmenter.reset, reset
wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate tlOut.d.bits.corrupt
invalidate tlOut.d.bits.data
invalidate tlOut.d.bits.denied
invalidate tlOut.d.bits.sink
invalidate tlOut.d.bits.source
invalidate tlOut.d.bits.size
invalidate tlOut.d.bits.param
invalidate tlOut.d.bits.opcode
invalidate tlOut.d.valid
invalidate tlOut.d.ready
invalidate tlOut.a.bits.corrupt
invalidate tlOut.a.bits.data
invalidate tlOut.a.bits.mask
invalidate tlOut.a.bits.address
invalidate tlOut.a.bits.source
invalidate tlOut.a.bits.size
invalidate tlOut.a.bits.param
invalidate tlOut.a.bits.opcode
invalidate tlOut.a.valid
invalidate tlOut.a.ready
wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate tlIn.d.bits.corrupt
invalidate tlIn.d.bits.data
invalidate tlIn.d.bits.denied
invalidate tlIn.d.bits.sink
invalidate tlIn.d.bits.source
invalidate tlIn.d.bits.size
invalidate tlIn.d.bits.param
invalidate tlIn.d.bits.opcode
invalidate tlIn.d.valid
invalidate tlIn.d.ready
invalidate tlIn.a.bits.corrupt
invalidate tlIn.a.bits.data
invalidate tlIn.a.bits.mask
invalidate tlIn.a.bits.address
invalidate tlIn.a.bits.source
invalidate tlIn.a.bits.size
invalidate tlIn.a.bits.param
invalidate tlIn.a.bits.opcode
invalidate tlIn.a.valid
invalidate tlIn.a.ready
connect tlOut, tlIn
wire controlXingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate controlXingOut.d.bits.corrupt
invalidate controlXingOut.d.bits.data
invalidate controlXingOut.d.bits.denied
invalidate controlXingOut.d.bits.sink
invalidate controlXingOut.d.bits.source
invalidate controlXingOut.d.bits.size
invalidate controlXingOut.d.bits.param
invalidate controlXingOut.d.bits.opcode
invalidate controlXingOut.d.valid
invalidate controlXingOut.d.ready
invalidate controlXingOut.a.bits.corrupt
invalidate controlXingOut.a.bits.data
invalidate controlXingOut.a.bits.mask
invalidate controlXingOut.a.bits.address
invalidate controlXingOut.a.bits.source
invalidate controlXingOut.a.bits.size
invalidate controlXingOut.a.bits.param
invalidate controlXingOut.a.bits.opcode
invalidate controlXingOut.a.valid
invalidate controlXingOut.a.ready
wire controlXingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate controlXingIn.d.bits.corrupt
invalidate controlXingIn.d.bits.data
invalidate controlXingIn.d.bits.denied
invalidate controlXingIn.d.bits.sink
invalidate controlXingIn.d.bits.source
invalidate controlXingIn.d.bits.size
invalidate controlXingIn.d.bits.param
invalidate controlXingIn.d.bits.opcode
invalidate controlXingIn.d.valid
invalidate controlXingIn.d.ready
invalidate controlXingIn.a.bits.corrupt
invalidate controlXingIn.a.bits.data
invalidate controlXingIn.a.bits.mask
invalidate controlXingIn.a.bits.address
invalidate controlXingIn.a.bits.source
invalidate controlXingIn.a.bits.size
invalidate controlXingIn.a.bits.param
invalidate controlXingIn.a.bits.opcode
invalidate controlXingIn.a.valid
invalidate controlXingIn.a.ready
connect controlXingOut, controlXingIn
connect fragmenter.auto.anon_in, tlOut
connect fragmenter.auto.anon_out.d, controlXingIn.d
connect controlXingIn.a.bits, fragmenter.auto.anon_out.a.bits
connect controlXingIn.a.valid, fragmenter.auto.anon_out.a.valid
connect fragmenter.auto.anon_out.a.ready, controlXingIn.a.ready
connect tlIn, auto.tl_in
connect auto.control_xing_out, controlXingOut
extmodule plusarg_reader_20 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_21 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLInterconnectCoupler_pbus_to_device_named_uart_0( // @[LazyModuleImp.scala:138:7]
input clock, // @[LazyModuleImp.scala:138:7]
input reset, // @[LazyModuleImp.scala:138:7]
input auto_control_xing_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_control_xing_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_control_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_control_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_control_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [11:0] auto_control_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_control_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_control_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_control_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_control_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_control_xing_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_control_xing_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_control_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_control_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [11:0] auto_control_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_control_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_in_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire tlOut_d_valid; // @[MixedNode.scala:542:17]
wire [63:0] tlOut_d_bits_data; // @[MixedNode.scala:542:17]
wire [7:0] tlOut_d_bits_source; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_d_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_d_bits_opcode; // @[MixedNode.scala:542:17]
wire tlOut_a_ready; // @[MixedNode.scala:542:17]
wire auto_control_xing_out_a_ready_0 = auto_control_xing_out_a_ready; // @[LazyModuleImp.scala:138:7]
wire auto_control_xing_out_d_valid_0 = auto_control_xing_out_d_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_control_xing_out_d_bits_opcode_0 = auto_control_xing_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_control_xing_out_d_bits_size_0 = auto_control_xing_out_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [11:0] auto_control_xing_out_d_bits_source_0 = auto_control_xing_out_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_control_xing_out_d_bits_data_0 = auto_control_xing_out_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [28:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[LazyModuleImp.scala:138:7]
wire auto_control_xing_out_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34]
wire auto_control_xing_out_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34]
wire auto_control_xing_out_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34]
wire auto_tl_in_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34]
wire auto_tl_in_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34]
wire auto_tl_in_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34]
wire tlOut_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34]
wire tlOut_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34]
wire tlOut_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34]
wire tlIn_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34]
wire tlIn_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34]
wire tlIn_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34]
wire controlXingOut_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34]
wire controlXingOut_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34]
wire controlXingOut_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34]
wire controlXingIn_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34]
wire controlXingIn_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34]
wire controlXingIn_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34]
wire [1:0] auto_control_xing_out_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34]
wire [1:0] auto_tl_in_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34]
wire [1:0] tlOut_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34]
wire [1:0] tlIn_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34]
wire [1:0] controlXingOut_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34]
wire [1:0] controlXingIn_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34]
wire controlXingOut_a_ready = auto_control_xing_out_a_ready_0; // @[MixedNode.scala:542:17]
wire controlXingOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] controlXingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] controlXingOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [1:0] controlXingOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [11:0] controlXingOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [28:0] controlXingOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] controlXingOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] controlXingOut_a_bits_data; // @[MixedNode.scala:542:17]
wire controlXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire controlXingOut_d_ready; // @[MixedNode.scala:542:17]
wire controlXingOut_d_valid = auto_control_xing_out_d_valid_0; // @[MixedNode.scala:542:17]
wire [2:0] controlXingOut_d_bits_opcode = auto_control_xing_out_d_bits_opcode_0; // @[MixedNode.scala:542:17]
wire [1:0] controlXingOut_d_bits_size = auto_control_xing_out_d_bits_size_0; // @[MixedNode.scala:542:17]
wire [11:0] controlXingOut_d_bits_source = auto_control_xing_out_d_bits_source_0; // @[MixedNode.scala:542:17]
wire [63:0] controlXingOut_d_bits_data = auto_control_xing_out_d_bits_data_0; // @[MixedNode.scala:542:17]
wire tlIn_a_ready; // @[MixedNode.scala:551:17]
wire tlIn_a_valid = auto_tl_in_a_valid_0; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[MixedNode.scala:551:17]
wire [7:0] tlIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[MixedNode.scala:551:17]
wire [28:0] tlIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[MixedNode.scala:551:17]
wire [7:0] tlIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[MixedNode.scala:551:17]
wire [63:0] tlIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[MixedNode.scala:551:17]
wire tlIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[MixedNode.scala:551:17]
wire tlIn_d_ready = auto_tl_in_d_ready_0; // @[MixedNode.scala:551:17]
wire tlIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [7:0] tlIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] tlIn_d_bits_data; // @[MixedNode.scala:551:17]
wire [2:0] auto_control_xing_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_control_xing_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_control_xing_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [11:0] auto_control_xing_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7]
wire [28:0] auto_control_xing_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_control_xing_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_control_xing_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_control_xing_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
wire auto_control_xing_out_a_valid_0; // @[LazyModuleImp.scala:138:7]
wire auto_control_xing_out_d_ready_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
assign tlIn_a_ready = tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_valid = tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_opcode = tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_size = tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_source = tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_data = tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [7:0] tlOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [28:0] tlOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] tlOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] tlOut_a_bits_data; // @[MixedNode.scala:542:17]
wire tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire tlOut_a_valid; // @[MixedNode.scala:542:17]
wire tlOut_d_ready; // @[MixedNode.scala:542:17]
assign auto_tl_in_a_ready_0 = tlIn_a_ready; // @[MixedNode.scala:551:17]
assign tlOut_a_valid = tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_opcode = tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_param = tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_size = tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_source = tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_address = tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_mask = tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_data = tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_corrupt = tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_d_ready = tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_tl_in_d_valid_0 = tlIn_d_valid; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_opcode_0 = tlIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_size_0 = tlIn_d_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_source_0 = tlIn_d_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_data_0 = tlIn_d_bits_data; // @[MixedNode.scala:551:17]
wire controlXingIn_a_ready = controlXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire controlXingIn_a_valid; // @[MixedNode.scala:551:17]
assign auto_control_xing_out_a_valid_0 = controlXingOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] controlXingIn_a_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_control_xing_out_a_bits_opcode_0 = controlXingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] controlXingIn_a_bits_param; // @[MixedNode.scala:551:17]
assign auto_control_xing_out_a_bits_param_0 = controlXingOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [1:0] controlXingIn_a_bits_size; // @[MixedNode.scala:551:17]
assign auto_control_xing_out_a_bits_size_0 = controlXingOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [11:0] controlXingIn_a_bits_source; // @[MixedNode.scala:551:17]
assign auto_control_xing_out_a_bits_source_0 = controlXingOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [28:0] controlXingIn_a_bits_address; // @[MixedNode.scala:551:17]
assign auto_control_xing_out_a_bits_address_0 = controlXingOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] controlXingIn_a_bits_mask; // @[MixedNode.scala:551:17]
assign auto_control_xing_out_a_bits_mask_0 = controlXingOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] controlXingIn_a_bits_data; // @[MixedNode.scala:551:17]
assign auto_control_xing_out_a_bits_data_0 = controlXingOut_a_bits_data; // @[MixedNode.scala:542:17]
wire controlXingIn_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_control_xing_out_a_bits_corrupt_0 = controlXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire controlXingIn_d_ready; // @[MixedNode.scala:551:17]
assign auto_control_xing_out_d_ready_0 = controlXingOut_d_ready; // @[MixedNode.scala:542:17]
wire controlXingIn_d_valid = controlXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] controlXingIn_d_bits_opcode = controlXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] controlXingIn_d_bits_size = controlXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [11:0] controlXingIn_d_bits_source = controlXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] controlXingIn_d_bits_data = controlXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_valid = controlXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_opcode = controlXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_param = controlXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_size = controlXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_source = controlXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_address = controlXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_mask = controlXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_data = controlXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_corrupt = controlXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_d_ready = controlXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
TLFragmenter_UART fragmenter ( // @[Fragmenter.scala:345:34]
.clock (clock),
.reset (reset),
.auto_anon_in_a_ready (tlOut_a_ready),
.auto_anon_in_a_valid (tlOut_a_valid), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_opcode (tlOut_a_bits_opcode), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_param (tlOut_a_bits_param), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_size (tlOut_a_bits_size), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_source (tlOut_a_bits_source), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_address (tlOut_a_bits_address), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_mask (tlOut_a_bits_mask), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_data (tlOut_a_bits_data), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_corrupt (tlOut_a_bits_corrupt), // @[MixedNode.scala:542:17]
.auto_anon_in_d_ready (tlOut_d_ready), // @[MixedNode.scala:542:17]
.auto_anon_in_d_valid (tlOut_d_valid),
.auto_anon_in_d_bits_opcode (tlOut_d_bits_opcode),
.auto_anon_in_d_bits_size (tlOut_d_bits_size),
.auto_anon_in_d_bits_source (tlOut_d_bits_source),
.auto_anon_in_d_bits_data (tlOut_d_bits_data),
.auto_anon_out_a_ready (controlXingIn_a_ready), // @[MixedNode.scala:551:17]
.auto_anon_out_a_valid (controlXingIn_a_valid),
.auto_anon_out_a_bits_opcode (controlXingIn_a_bits_opcode),
.auto_anon_out_a_bits_param (controlXingIn_a_bits_param),
.auto_anon_out_a_bits_size (controlXingIn_a_bits_size),
.auto_anon_out_a_bits_source (controlXingIn_a_bits_source),
.auto_anon_out_a_bits_address (controlXingIn_a_bits_address),
.auto_anon_out_a_bits_mask (controlXingIn_a_bits_mask),
.auto_anon_out_a_bits_data (controlXingIn_a_bits_data),
.auto_anon_out_a_bits_corrupt (controlXingIn_a_bits_corrupt),
.auto_anon_out_d_ready (controlXingIn_d_ready),
.auto_anon_out_d_valid (controlXingIn_d_valid), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_opcode (controlXingIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_size (controlXingIn_d_bits_size), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_source (controlXingIn_d_bits_source), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_data (controlXingIn_d_bits_data) // @[MixedNode.scala:551:17]
); // @[Fragmenter.scala:345:34]
assign auto_control_xing_out_a_valid = auto_control_xing_out_a_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_control_xing_out_a_bits_opcode = auto_control_xing_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
assign auto_control_xing_out_a_bits_param = auto_control_xing_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7]
assign auto_control_xing_out_a_bits_size = auto_control_xing_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_control_xing_out_a_bits_source = auto_control_xing_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7]
assign auto_control_xing_out_a_bits_address = auto_control_xing_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7]
assign auto_control_xing_out_a_bits_mask = auto_control_xing_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7]
assign auto_control_xing_out_a_bits_data = auto_control_xing_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7]
assign auto_control_xing_out_a_bits_corrupt = auto_control_xing_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
assign auto_control_xing_out_d_ready = auto_control_xing_out_d_ready_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_a_ready = auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_valid = auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_opcode = auto_tl_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_size = auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_source = auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_data = auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_116 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_196
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_116( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_196 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e8_s24_67 :
output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<49>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}}
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags)
node _sigSum_T = bits(io.mulAddResult, 48, 48)
node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1))
node _sigSum_T_2 = tail(_sigSum_T_1, 1)
node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC)
node _sigSum_T_4 = bits(io.mulAddResult, 47, 0)
node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4)
node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC)
node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags)
node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T)
node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1)
node CDom_sExp = asSInt(_CDom_sExp_T_2)
node _CDom_absSigSum_T = bits(sigSum, 74, 25)
node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T)
node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 25, 24)
node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2)
node _CDom_absSigSum_T_4 = bits(sigSum, 72, 26)
node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4)
node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5)
node _CDom_absSigSumExtra_T = bits(sigSum, 24, 1)
node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T)
node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1)
node _CDom_absSigSumExtra_T_3 = bits(sigSum, 25, 1)
node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3)
node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4)
node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist)
node CDom_mainSig = bits(_CDom_mainSig_T, 49, 21)
node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 23, 0)
node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 3)
wire CDom_reduced4SigExtra_reducedVec : UInt<1>[7]
node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0)
node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T)
connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1
node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4)
node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T)
connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1
node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8)
node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T)
connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1
node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12)
node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T)
connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1
node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16)
node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T)
connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1
node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20)
node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T)
connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1
node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 26, 24)
node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T)
connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1
node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1])
node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec[0])
node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3])
node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5])
node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo)
node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo)
node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2)
node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3)
node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _CDom_reduced4SigExtra_T_4)
node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 6, 1)
node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 3, 0)
node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_6, 1, 0)
node _CDom_reduced4SigExtra_T_8 = bits(_CDom_reduced4SigExtra_T_7, 0, 0)
node _CDom_reduced4SigExtra_T_9 = bits(_CDom_reduced4SigExtra_T_7, 1, 1)
node _CDom_reduced4SigExtra_T_10 = cat(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9)
node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 2)
node _CDom_reduced4SigExtra_T_12 = bits(_CDom_reduced4SigExtra_T_11, 0, 0)
node _CDom_reduced4SigExtra_T_13 = bits(_CDom_reduced4SigExtra_T_11, 1, 1)
node _CDom_reduced4SigExtra_T_14 = cat(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13)
node _CDom_reduced4SigExtra_T_15 = cat(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14)
node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_5, 5, 4)
node _CDom_reduced4SigExtra_T_17 = bits(_CDom_reduced4SigExtra_T_16, 0, 0)
node _CDom_reduced4SigExtra_T_18 = bits(_CDom_reduced4SigExtra_T_16, 1, 1)
node _CDom_reduced4SigExtra_T_19 = cat(_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18)
node _CDom_reduced4SigExtra_T_20 = cat(_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19)
node _CDom_reduced4SigExtra_T_21 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_20)
node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_21)
node _CDom_sig_T = shr(CDom_mainSig, 3)
node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0)
node _CDom_sig_T_2 = orr(_CDom_sig_T_1)
node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra)
node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra)
node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4)
node notCDom_signSigSum = bits(sigSum, 51, 51)
node _notCDom_absSigSum_T = bits(sigSum, 50, 0)
node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T)
node _notCDom_absSigSum_T_2 = bits(sigSum, 50, 0)
node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags)
node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1)
node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4)
wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[26]
node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0)
node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T)
connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2)
node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T)
connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4)
node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T)
connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6)
node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T)
connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8)
node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T)
connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10)
node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T)
connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12)
node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T)
connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14)
node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T)
connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16)
node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T)
connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18)
node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T)
connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20)
node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T)
connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22)
node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T)
connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24)
node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T)
connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26)
node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T)
connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28)
node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T)
connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30)
node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T)
connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32)
node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T)
connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34)
node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T)
connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36)
node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T)
connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38)
node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T)
connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40)
node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T)
connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42)
node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T)
connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44)
node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T)
connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46)
node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T)
connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48)
node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T)
connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 50, 50)
node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T)
connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1
node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1])
node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0])
node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4])
node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3])
node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo)
node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7])
node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6])
node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9])
node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11])
node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo)
node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo)
node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo)
node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14])
node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13])
node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[18], notCDom_reduced2AbsSigSum_reducedVec[17])
node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[16])
node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo)
node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[21], notCDom_reduced2AbsSigSum_reducedVec[20])
node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[19])
node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[23], notCDom_reduced2AbsSigSum_reducedVec[22])
node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[25], notCDom_reduced2AbsSigSum_reducedVec[24])
node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo)
node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo)
node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo)
node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo)
node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0)
node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1)
node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2)
node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3)
node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4)
node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5)
node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6)
node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7)
node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8)
node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9)
node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10)
node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11)
node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12)
node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13)
node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14)
node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15)
node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16)
node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17)
node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18)
node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19)
node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20)
node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21)
node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22)
node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23)
node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24)
node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25)
node _notCDom_normDistReduced2_T_26 = mux(_notCDom_normDistReduced2_T_1, UInt<5>(0h18), UInt<5>(0h19))
node _notCDom_normDistReduced2_T_27 = mux(_notCDom_normDistReduced2_T_2, UInt<5>(0h17), _notCDom_normDistReduced2_T_26)
node _notCDom_normDistReduced2_T_28 = mux(_notCDom_normDistReduced2_T_3, UInt<5>(0h16), _notCDom_normDistReduced2_T_27)
node _notCDom_normDistReduced2_T_29 = mux(_notCDom_normDistReduced2_T_4, UInt<5>(0h15), _notCDom_normDistReduced2_T_28)
node _notCDom_normDistReduced2_T_30 = mux(_notCDom_normDistReduced2_T_5, UInt<5>(0h14), _notCDom_normDistReduced2_T_29)
node _notCDom_normDistReduced2_T_31 = mux(_notCDom_normDistReduced2_T_6, UInt<5>(0h13), _notCDom_normDistReduced2_T_30)
node _notCDom_normDistReduced2_T_32 = mux(_notCDom_normDistReduced2_T_7, UInt<5>(0h12), _notCDom_normDistReduced2_T_31)
node _notCDom_normDistReduced2_T_33 = mux(_notCDom_normDistReduced2_T_8, UInt<5>(0h11), _notCDom_normDistReduced2_T_32)
node _notCDom_normDistReduced2_T_34 = mux(_notCDom_normDistReduced2_T_9, UInt<5>(0h10), _notCDom_normDistReduced2_T_33)
node _notCDom_normDistReduced2_T_35 = mux(_notCDom_normDistReduced2_T_10, UInt<4>(0hf), _notCDom_normDistReduced2_T_34)
node _notCDom_normDistReduced2_T_36 = mux(_notCDom_normDistReduced2_T_11, UInt<4>(0he), _notCDom_normDistReduced2_T_35)
node _notCDom_normDistReduced2_T_37 = mux(_notCDom_normDistReduced2_T_12, UInt<4>(0hd), _notCDom_normDistReduced2_T_36)
node _notCDom_normDistReduced2_T_38 = mux(_notCDom_normDistReduced2_T_13, UInt<4>(0hc), _notCDom_normDistReduced2_T_37)
node _notCDom_normDistReduced2_T_39 = mux(_notCDom_normDistReduced2_T_14, UInt<4>(0hb), _notCDom_normDistReduced2_T_38)
node _notCDom_normDistReduced2_T_40 = mux(_notCDom_normDistReduced2_T_15, UInt<4>(0ha), _notCDom_normDistReduced2_T_39)
node _notCDom_normDistReduced2_T_41 = mux(_notCDom_normDistReduced2_T_16, UInt<4>(0h9), _notCDom_normDistReduced2_T_40)
node _notCDom_normDistReduced2_T_42 = mux(_notCDom_normDistReduced2_T_17, UInt<4>(0h8), _notCDom_normDistReduced2_T_41)
node _notCDom_normDistReduced2_T_43 = mux(_notCDom_normDistReduced2_T_18, UInt<3>(0h7), _notCDom_normDistReduced2_T_42)
node _notCDom_normDistReduced2_T_44 = mux(_notCDom_normDistReduced2_T_19, UInt<3>(0h6), _notCDom_normDistReduced2_T_43)
node _notCDom_normDistReduced2_T_45 = mux(_notCDom_normDistReduced2_T_20, UInt<3>(0h5), _notCDom_normDistReduced2_T_44)
node _notCDom_normDistReduced2_T_46 = mux(_notCDom_normDistReduced2_T_21, UInt<3>(0h4), _notCDom_normDistReduced2_T_45)
node _notCDom_normDistReduced2_T_47 = mux(_notCDom_normDistReduced2_T_22, UInt<2>(0h3), _notCDom_normDistReduced2_T_46)
node _notCDom_normDistReduced2_T_48 = mux(_notCDom_normDistReduced2_T_23, UInt<2>(0h2), _notCDom_normDistReduced2_T_47)
node _notCDom_normDistReduced2_T_49 = mux(_notCDom_normDistReduced2_T_24, UInt<1>(0h1), _notCDom_normDistReduced2_T_48)
node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_25, UInt<1>(0h0), _notCDom_normDistReduced2_T_49)
node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1)
node _notCDom_sExp_T = cvt(notCDom_nearNormDist)
node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T)
node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1)
node notCDom_sExp = asSInt(_notCDom_sExp_T_2)
node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist)
node notCDom_mainSig = bits(_notCDom_mainSig_T, 51, 23)
node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 12, 0)
node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0)
wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[7]
node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0)
node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T)
connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1
node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2)
node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T)
connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1
node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4)
node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T)
connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1
node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6)
node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T)
connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1
node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8)
node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T)
connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1
node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10)
node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T)
connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1
node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 12, 12)
node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T)
connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1
node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1])
node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec[0])
node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3])
node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5])
node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo)
node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo)
node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1)
node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3)
node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _notCDom_reduced4SigExtra_T_4)
node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 6, 1)
node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 3, 0)
node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 1, 0)
node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_7, 0, 0)
node _notCDom_reduced4SigExtra_T_9 = bits(_notCDom_reduced4SigExtra_T_7, 1, 1)
node _notCDom_reduced4SigExtra_T_10 = cat(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9)
node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 2)
node _notCDom_reduced4SigExtra_T_12 = bits(_notCDom_reduced4SigExtra_T_11, 0, 0)
node _notCDom_reduced4SigExtra_T_13 = bits(_notCDom_reduced4SigExtra_T_11, 1, 1)
node _notCDom_reduced4SigExtra_T_14 = cat(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13)
node _notCDom_reduced4SigExtra_T_15 = cat(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14)
node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_5, 5, 4)
node _notCDom_reduced4SigExtra_T_17 = bits(_notCDom_reduced4SigExtra_T_16, 0, 0)
node _notCDom_reduced4SigExtra_T_18 = bits(_notCDom_reduced4SigExtra_T_16, 1, 1)
node _notCDom_reduced4SigExtra_T_19 = cat(_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18)
node _notCDom_reduced4SigExtra_T_20 = cat(_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19)
node _notCDom_reduced4SigExtra_T_21 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_20)
node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_21)
node _notCDom_sig_T = shr(notCDom_mainSig, 3)
node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0)
node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1)
node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra)
node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3)
node _notCDom_completeCancellation_T = bits(notCDom_sig, 26, 25)
node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0))
node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum)
node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T)
node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB)
node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC)
node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB)
node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC)
node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB)
node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T)
node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB)
node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2)
node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0))
node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB)
node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5)
node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC)
node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags)
node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8)
connect io.invalidExc, _io_invalidExc_T_9
node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC)
connect io.rawOut.isNaN, _io_rawOut_isNaN_T
connect io.rawOut.isInf, notNaN_isInfOut
node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0))
node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation)
node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1)
connect io.rawOut.isZero, _io_rawOut_isZero_T_2
node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd)
node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC)
node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1)
node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0))
node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3)
node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd)
node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC)
node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6)
node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min)
node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC)
node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9)
node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10)
node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0))
node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0))
node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13)
node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign)
node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15)
node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16)
connect io.rawOut.sign, _io_rawOut_sign_T_17
node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
connect io.rawOut.sExp, _io_rawOut_sExp_T
node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
connect io.rawOut.sig, _io_rawOut_sig_T | module MulAddRecFNToRaw_postMul_e8_s24_67( // @[MulAddRecFN.scala:169:7]
input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16]
input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16]
input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16]
input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16]
input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16]
output io_invalidExc, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16]
output io_rawOut_sign, // @[MulAddRecFN.scala:172:16]
output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16]
output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16]
);
wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfB_0 = io_fromPreMul_isInfB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroB_0 = io_fromPreMul_isZeroB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7]
wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7]
wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7]
wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7]
wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7]
wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29]
wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45]
wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26]
wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46]
wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16]
wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57]
wire _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:278:48]
wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44]
wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25]
wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50]
wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26]
wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25]
wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42]
wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32]
wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47]
wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47]
wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47]
wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28]
wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28]
wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12]
wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69]
wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43]
wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}]
wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43]
wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43]
wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20]
wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}]
wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46]
wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46]
wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23]
wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23]
wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71]
wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21]
wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}]
wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}]
wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19]
wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}]
wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37]
wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24]
wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}]
wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36]
wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}]
wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57]
wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15]
assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}]
assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20]
wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51]
wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20]
wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22]
wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20]
wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20]
wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20]
wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73]
wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25]
wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25]
wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}]
wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}]
wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}]
wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61]
wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36]
wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20]
wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19]
wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}]
wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}]
wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41]
wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41]
wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15]
assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20]
wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20]
wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20]
wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70]
wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70]
wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70]
wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76]
wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}]
wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46]
wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46]
wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27]
wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}]
wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20]
wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}]
wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15]
assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20]
wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70]
wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20]
wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22]
wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20]
wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20]
wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20]
wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11]
wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28]
wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28]
wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}]
wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}]
wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39]
wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21]
wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54]
wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36]
wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36]
wire _GEN_0 = io_fromPreMul_isInfA_0 | io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :264:49]
wire notNaN_isInfProd; // @[MulAddRecFN.scala:264:49]
assign notNaN_isInfProd = _GEN_0; // @[MulAddRecFN.scala:264:49]
wire _io_invalidExc_T_5; // @[MulAddRecFN.scala:275:36]
assign _io_invalidExc_T_5 = _GEN_0; // @[MulAddRecFN.scala:264:49, :275:36]
assign notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :264:49, :265:44]
assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44]
wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0 | io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :267:32]
wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:{32,58}]
wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26]
wire _io_invalidExc_T = io_fromPreMul_isInfA_0 & io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :272:31]
wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0 | _io_invalidExc_T; // @[MulAddRecFN.scala:169:7, :271:35, :272:31]
wire _io_invalidExc_T_2 = io_fromPreMul_isZeroA_0 & io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :273:32]
wire _io_invalidExc_T_3 = _io_invalidExc_T_1 | _io_invalidExc_T_2; // @[MulAddRecFN.scala:271:35, :272:57, :273:32]
wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10]
wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36]
wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :274:36, :275:61]
wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :275:61, :276:35]
assign _io_invalidExc_T_9 = _io_invalidExc_T_3 | _io_invalidExc_T_8; // @[MulAddRecFN.scala:272:57, :273:57, :276:35]
assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57]
assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 | io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48]
assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48]
wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14]
wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}]
assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42]
assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25]
wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27]
wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31]
wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T | _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:{27,54}, :286:31]
wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}]
wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36]
wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36]
wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48]
wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37]
wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10]
wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31]
wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}]
wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17]
wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17]
assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49]
assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50]
assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26]
assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26]
assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25]
assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25]
assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IBuf_3 :
input clock : Clock
input reset : Reset
output io : { flip imem : { flip ready : UInt<1>, valid : UInt<1>, bits : { btb : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, replay : UInt<1>}}, flip kill : UInt<1>, pc : UInt<40>, btb_resp : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, inst : { flip ready : UInt<1>, valid : UInt<1>, bits : { xcpt0 : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, xcpt1 : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, replay : UInt<1>, rvc : UInt<1>, inst : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}, raw : UInt<32>}}[1]}
regreset nBufValid : UInt<1>, clock, reset, UInt<1>(0h0)
reg buf : { btb : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, replay : UInt<1>}, clock
reg ibufBTBResp : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, clock
node pcWordBits = bits(io.imem.bits.pc, 1, 1)
wire nReady : UInt<2>
connect nReady, UInt<2>(0h0)
node _nIC_T = add(io.imem.bits.btb.bridx, UInt<1>(0h1))
node _nIC_T_1 = mux(io.imem.bits.btb.taken, _nIC_T, UInt<2>(0h2))
node _nIC_T_2 = sub(_nIC_T_1, pcWordBits)
node nIC = tail(_nIC_T_2, 1)
node _nICReady_T = sub(nReady, nBufValid)
node nICReady = tail(_nICReady_T, 1)
node _nValid_T = mux(io.imem.valid, nIC, UInt<1>(0h0))
node _nValid_T_1 = add(_nValid_T, nBufValid)
node nValid = tail(_nValid_T_1, 1)
node _io_imem_ready_T = geq(nReady, nBufValid)
node _io_imem_ready_T_1 = and(io.inst[0].ready, _io_imem_ready_T)
node _io_imem_ready_T_2 = geq(nICReady, nIC)
node _io_imem_ready_T_3 = sub(nIC, nICReady)
node _io_imem_ready_T_4 = tail(_io_imem_ready_T_3, 1)
node _io_imem_ready_T_5 = geq(UInt<1>(0h1), _io_imem_ready_T_4)
node _io_imem_ready_T_6 = or(_io_imem_ready_T_2, _io_imem_ready_T_5)
node _io_imem_ready_T_7 = and(_io_imem_ready_T_1, _io_imem_ready_T_6)
connect io.imem.ready, _io_imem_ready_T_7
when io.inst[0].ready :
node _nBufValid_T = geq(nReady, nBufValid)
node _nBufValid_T_1 = eq(nBufValid, UInt<1>(0h0))
node _nBufValid_T_2 = or(_nBufValid_T, _nBufValid_T_1)
node _nBufValid_T_3 = sub(nBufValid, nReady)
node _nBufValid_T_4 = tail(_nBufValid_T_3, 1)
node _nBufValid_T_5 = mux(_nBufValid_T_2, UInt<1>(0h0), _nBufValid_T_4)
connect nBufValid, _nBufValid_T_5
node _T = geq(nReady, nBufValid)
node _T_1 = and(io.imem.valid, _T)
node _T_2 = lt(nICReady, nIC)
node _T_3 = and(_T_1, _T_2)
node _T_4 = sub(nIC, nICReady)
node _T_5 = tail(_T_4, 1)
node _T_6 = geq(UInt<1>(0h1), _T_5)
node _T_7 = and(_T_3, _T_6)
when _T_7 :
node _shamt_T = add(pcWordBits, nICReady)
node shamt = tail(_shamt_T, 1)
node _nBufValid_T_6 = sub(nIC, nICReady)
node _nBufValid_T_7 = tail(_nBufValid_T_6, 1)
connect nBufValid, _nBufValid_T_7
connect buf, io.imem.bits
node _buf_data_data_T = shr(io.imem.bits.data, 16)
node _buf_data_data_T_1 = cat(_buf_data_data_T, _buf_data_data_T)
node buf_data_data = cat(_buf_data_data_T_1, io.imem.bits.data)
node _buf_data_T = shl(shamt, 4)
node _buf_data_T_1 = dshr(buf_data_data, _buf_data_T)
node _buf_data_T_2 = bits(_buf_data_T_1, 15, 0)
connect buf.data, _buf_data_T_2
node _buf_pc_T = not(UInt<40>(0h3))
node _buf_pc_T_1 = and(io.imem.bits.pc, _buf_pc_T)
node _buf_pc_T_2 = shl(nICReady, 1)
node _buf_pc_T_3 = add(io.imem.bits.pc, _buf_pc_T_2)
node _buf_pc_T_4 = tail(_buf_pc_T_3, 1)
node _buf_pc_T_5 = and(_buf_pc_T_4, UInt<40>(0h3))
node _buf_pc_T_6 = or(_buf_pc_T_1, _buf_pc_T_5)
connect buf.pc, _buf_pc_T_6
connect ibufBTBResp, io.imem.bits.btb
when io.kill :
connect nBufValid, UInt<1>(0h0)
node _icShiftAmt_T = add(UInt<2>(0h2), nBufValid)
node _icShiftAmt_T_1 = tail(_icShiftAmt_T, 1)
node _icShiftAmt_T_2 = sub(_icShiftAmt_T_1, pcWordBits)
node _icShiftAmt_T_3 = tail(_icShiftAmt_T_2, 1)
node icShiftAmt = bits(_icShiftAmt_T_3, 1, 0)
node _icData_T = bits(io.imem.bits.data, 15, 0)
node _icData_T_1 = cat(_icData_T, _icData_T)
node _icData_T_2 = cat(io.imem.bits.data, _icData_T_1)
node _icData_data_T = shr(_icData_T_2, 48)
node _icData_data_T_1 = cat(_icData_data_T, _icData_data_T)
node _icData_data_T_2 = cat(_icData_data_T_1, _icData_data_T_1)
node icData_data = cat(_icData_data_T_2, _icData_T_2)
node _icData_T_3 = shl(icShiftAmt, 4)
node _icData_T_4 = dshl(icData_data, _icData_T_3)
node icData = bits(_icData_T_4, 95, 64)
node _icMask_T = not(UInt<32>(0h0))
node _icMask_T_1 = shl(nBufValid, 4)
node _icMask_T_2 = dshl(_icMask_T, _icMask_T_1)
node icMask = bits(_icMask_T_2, 31, 0)
node _inst_T = and(icData, icMask)
node _inst_T_1 = not(icMask)
node _inst_T_2 = and(buf.data, _inst_T_1)
node inst = or(_inst_T, _inst_T_2)
node _valid_T = dshl(UInt<1>(0h1), nValid)
node _valid_T_1 = sub(_valid_T, UInt<1>(0h1))
node _valid_T_2 = tail(_valid_T_1, 1)
node valid = bits(_valid_T_2, 1, 0)
node _bufMask_T = dshl(UInt<1>(0h1), nBufValid)
node _bufMask_T_1 = sub(_bufMask_T, UInt<1>(0h1))
node bufMask = tail(_bufMask_T_1, 1)
node _xcpt_T = bits(bufMask, 0, 0)
node xcpt_0 = mux(_xcpt_T, buf.xcpt, io.imem.bits.xcpt)
node _xcpt_T_1 = bits(bufMask, 1, 1)
node xcpt_1 = mux(_xcpt_T_1, buf.xcpt, io.imem.bits.xcpt)
node buf_replay = mux(buf.replay, bufMask, UInt<1>(0h0))
node _ic_replay_T = not(bufMask)
node _ic_replay_T_1 = and(valid, _ic_replay_T)
node _ic_replay_T_2 = mux(io.imem.bits.replay, _ic_replay_T_1, UInt<1>(0h0))
node ic_replay = or(buf_replay, _ic_replay_T_2)
node _T_8 = eq(io.imem.valid, UInt<1>(0h0))
node _T_9 = eq(io.imem.bits.btb.taken, UInt<1>(0h0))
node _T_10 = or(_T_8, _T_9)
node _T_11 = geq(io.imem.bits.btb.bridx, pcWordBits)
node _T_12 = or(_T_10, _T_11)
node _T_13 = asUInt(reset)
node _T_14 = eq(_T_13, UInt<1>(0h0))
when _T_14 :
node _T_15 = eq(_T_12, UInt<1>(0h0))
when _T_15 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IBuf.scala:79 assert(!io.imem.valid || !io.imem.bits.btb.taken || io.imem.bits.btb.bridx >= pcWordBits)\n") : printf
assert(clock, _T_12, UInt<1>(0h1), "") : assert
connect io.btb_resp, io.imem.bits.btb
node _io_pc_T = gt(nBufValid, UInt<1>(0h0))
node _io_pc_T_1 = mux(_io_pc_T, buf.pc, io.imem.bits.pc)
connect io.pc, _io_pc_T_1
inst exp of RVCExpander_3
connect exp.clock, clock
connect exp.reset, reset
connect exp.io.in, inst
connect io.inst[0].bits.inst, exp.io.out
connect io.inst[0].bits.raw, inst
node _replay_T = dshr(ic_replay, UInt<1>(0h0))
node _replay_T_1 = bits(_replay_T, 0, 0)
node _replay_T_2 = eq(exp.io.rvc, UInt<1>(0h0))
node _replay_T_3 = add(UInt<1>(0h0), UInt<1>(0h1))
node _replay_T_4 = tail(_replay_T_3, 1)
node _replay_T_5 = dshr(ic_replay, _replay_T_4)
node _replay_T_6 = bits(_replay_T_5, 0, 0)
node _replay_T_7 = and(_replay_T_2, _replay_T_6)
node replay = or(_replay_T_1, _replay_T_7)
node _full_insn_T = add(UInt<1>(0h0), UInt<1>(0h1))
node _full_insn_T_1 = tail(_full_insn_T, 1)
node _full_insn_T_2 = dshr(valid, _full_insn_T_1)
node _full_insn_T_3 = bits(_full_insn_T_2, 0, 0)
node _full_insn_T_4 = or(exp.io.rvc, _full_insn_T_3)
node _full_insn_T_5 = dshr(buf_replay, UInt<1>(0h0))
node _full_insn_T_6 = bits(_full_insn_T_5, 0, 0)
node full_insn = or(_full_insn_T_4, _full_insn_T_6)
node _io_inst_0_valid_T = dshr(valid, UInt<1>(0h0))
node _io_inst_0_valid_T_1 = bits(_io_inst_0_valid_T, 0, 0)
node _io_inst_0_valid_T_2 = and(_io_inst_0_valid_T_1, full_insn)
connect io.inst[0].valid, _io_inst_0_valid_T_2
node _io_inst_0_bits_xcpt0_T = eq(UInt<1>(0h0), UInt<1>(0h1))
node _io_inst_0_bits_xcpt0_T_1 = mux(_io_inst_0_bits_xcpt0_T, xcpt_1, xcpt_0)
connect io.inst[0].bits.xcpt0, _io_inst_0_bits_xcpt0_T_1
node _io_inst_0_bits_xcpt1_T = add(UInt<1>(0h0), UInt<1>(0h1))
node _io_inst_0_bits_xcpt1_T_1 = tail(_io_inst_0_bits_xcpt1_T, 1)
node _io_inst_0_bits_xcpt1_T_2 = eq(_io_inst_0_bits_xcpt1_T_1, UInt<1>(0h1))
node _io_inst_0_bits_xcpt1_T_3 = mux(_io_inst_0_bits_xcpt1_T_2, xcpt_1, xcpt_0)
node io_inst_0_bits_xcpt1_hi = cat(_io_inst_0_bits_xcpt1_T_3.pf.inst, _io_inst_0_bits_xcpt1_T_3.gf.inst)
node _io_inst_0_bits_xcpt1_T_4 = cat(io_inst_0_bits_xcpt1_hi, _io_inst_0_bits_xcpt1_T_3.ae.inst)
node _io_inst_0_bits_xcpt1_T_5 = mux(exp.io.rvc, UInt<1>(0h0), _io_inst_0_bits_xcpt1_T_4)
wire _io_inst_0_bits_xcpt1_WIRE : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}
wire _io_inst_0_bits_xcpt1_WIRE_1 : UInt<3>
connect _io_inst_0_bits_xcpt1_WIRE_1, _io_inst_0_bits_xcpt1_T_5
node _io_inst_0_bits_xcpt1_T_6 = bits(_io_inst_0_bits_xcpt1_WIRE_1, 0, 0)
connect _io_inst_0_bits_xcpt1_WIRE.ae.inst, _io_inst_0_bits_xcpt1_T_6
node _io_inst_0_bits_xcpt1_T_7 = bits(_io_inst_0_bits_xcpt1_WIRE_1, 1, 1)
connect _io_inst_0_bits_xcpt1_WIRE.gf.inst, _io_inst_0_bits_xcpt1_T_7
node _io_inst_0_bits_xcpt1_T_8 = bits(_io_inst_0_bits_xcpt1_WIRE_1, 2, 2)
connect _io_inst_0_bits_xcpt1_WIRE.pf.inst, _io_inst_0_bits_xcpt1_T_8
connect io.inst[0].bits.xcpt1, _io_inst_0_bits_xcpt1_WIRE
connect io.inst[0].bits.replay, replay
connect io.inst[0].bits.rvc, exp.io.rvc
node _T_16 = dshr(bufMask, UInt<1>(0h0))
node _T_17 = bits(_T_16, 0, 0)
node _T_18 = and(_T_17, exp.io.rvc)
node _T_19 = add(UInt<1>(0h0), UInt<1>(0h1))
node _T_20 = tail(_T_19, 1)
node _T_21 = dshr(bufMask, _T_20)
node _T_22 = bits(_T_21, 0, 0)
node _T_23 = or(_T_18, _T_22)
when _T_23 :
connect io.btb_resp, ibufBTBResp
node _T_24 = or(UInt<1>(0h1), io.inst[0].ready)
node _T_25 = and(full_insn, _T_24)
when _T_25 :
node _nReady_T = add(UInt<1>(0h0), UInt<1>(0h1))
node _nReady_T_1 = tail(_nReady_T, 1)
node _nReady_T_2 = add(UInt<1>(0h0), UInt<2>(0h2))
node _nReady_T_3 = tail(_nReady_T_2, 1)
node _nReady_T_4 = mux(exp.io.rvc, _nReady_T_1, _nReady_T_3)
connect nReady, _nReady_T_4
node _T_26 = add(UInt<1>(0h0), UInt<1>(0h1))
node _T_27 = tail(_T_26, 1)
node _T_28 = add(UInt<1>(0h0), UInt<2>(0h2))
node _T_29 = tail(_T_28, 1)
node _T_30 = mux(exp.io.rvc, _T_27, _T_29)
node _T_31 = shr(inst, 16)
node _T_32 = shr(inst, 32)
node _T_33 = mux(exp.io.rvc, _T_31, _T_32) | module IBuf_3( // @[IBuf.scala:21:7]
input clock, // @[IBuf.scala:21:7]
input reset, // @[IBuf.scala:21:7]
output io_imem_ready, // @[IBuf.scala:22:14]
input io_imem_valid, // @[IBuf.scala:22:14]
input [1:0] io_imem_bits_btb_cfiType, // @[IBuf.scala:22:14]
input io_imem_bits_btb_taken, // @[IBuf.scala:22:14]
input [1:0] io_imem_bits_btb_mask, // @[IBuf.scala:22:14]
input io_imem_bits_btb_bridx, // @[IBuf.scala:22:14]
input [38:0] io_imem_bits_btb_target, // @[IBuf.scala:22:14]
input [4:0] io_imem_bits_btb_entry, // @[IBuf.scala:22:14]
input [7:0] io_imem_bits_btb_bht_history, // @[IBuf.scala:22:14]
input io_imem_bits_btb_bht_value, // @[IBuf.scala:22:14]
input [39:0] io_imem_bits_pc, // @[IBuf.scala:22:14]
input [31:0] io_imem_bits_data, // @[IBuf.scala:22:14]
input [1:0] io_imem_bits_mask, // @[IBuf.scala:22:14]
input io_imem_bits_xcpt_pf_inst, // @[IBuf.scala:22:14]
input io_imem_bits_xcpt_gf_inst, // @[IBuf.scala:22:14]
input io_imem_bits_xcpt_ae_inst, // @[IBuf.scala:22:14]
input io_imem_bits_replay, // @[IBuf.scala:22:14]
input io_kill, // @[IBuf.scala:22:14]
output [39:0] io_pc, // @[IBuf.scala:22:14]
output [1:0] io_btb_resp_cfiType, // @[IBuf.scala:22:14]
output io_btb_resp_taken, // @[IBuf.scala:22:14]
output [1:0] io_btb_resp_mask, // @[IBuf.scala:22:14]
output io_btb_resp_bridx, // @[IBuf.scala:22:14]
output [38:0] io_btb_resp_target, // @[IBuf.scala:22:14]
output [4:0] io_btb_resp_entry, // @[IBuf.scala:22:14]
output [7:0] io_btb_resp_bht_history, // @[IBuf.scala:22:14]
output io_btb_resp_bht_value, // @[IBuf.scala:22:14]
input io_inst_0_ready, // @[IBuf.scala:22:14]
output io_inst_0_valid, // @[IBuf.scala:22:14]
output io_inst_0_bits_xcpt0_pf_inst, // @[IBuf.scala:22:14]
output io_inst_0_bits_xcpt0_gf_inst, // @[IBuf.scala:22:14]
output io_inst_0_bits_xcpt0_ae_inst, // @[IBuf.scala:22:14]
output io_inst_0_bits_xcpt1_pf_inst, // @[IBuf.scala:22:14]
output io_inst_0_bits_xcpt1_gf_inst, // @[IBuf.scala:22:14]
output io_inst_0_bits_xcpt1_ae_inst, // @[IBuf.scala:22:14]
output io_inst_0_bits_replay, // @[IBuf.scala:22:14]
output io_inst_0_bits_rvc, // @[IBuf.scala:22:14]
output [31:0] io_inst_0_bits_inst_bits, // @[IBuf.scala:22:14]
output [4:0] io_inst_0_bits_inst_rd, // @[IBuf.scala:22:14]
output [4:0] io_inst_0_bits_inst_rs1, // @[IBuf.scala:22:14]
output [4:0] io_inst_0_bits_inst_rs2, // @[IBuf.scala:22:14]
output [4:0] io_inst_0_bits_inst_rs3, // @[IBuf.scala:22:14]
output [31:0] io_inst_0_bits_raw // @[IBuf.scala:22:14]
);
wire _exp_io_rvc; // @[IBuf.scala:86:21]
wire io_imem_valid_0 = io_imem_valid; // @[IBuf.scala:21:7]
wire [1:0] io_imem_bits_btb_cfiType_0 = io_imem_bits_btb_cfiType; // @[IBuf.scala:21:7]
wire io_imem_bits_btb_taken_0 = io_imem_bits_btb_taken; // @[IBuf.scala:21:7]
wire [1:0] io_imem_bits_btb_mask_0 = io_imem_bits_btb_mask; // @[IBuf.scala:21:7]
wire io_imem_bits_btb_bridx_0 = io_imem_bits_btb_bridx; // @[IBuf.scala:21:7]
wire [38:0] io_imem_bits_btb_target_0 = io_imem_bits_btb_target; // @[IBuf.scala:21:7]
wire [4:0] io_imem_bits_btb_entry_0 = io_imem_bits_btb_entry; // @[IBuf.scala:21:7]
wire [7:0] io_imem_bits_btb_bht_history_0 = io_imem_bits_btb_bht_history; // @[IBuf.scala:21:7]
wire io_imem_bits_btb_bht_value_0 = io_imem_bits_btb_bht_value; // @[IBuf.scala:21:7]
wire [39:0] io_imem_bits_pc_0 = io_imem_bits_pc; // @[IBuf.scala:21:7]
wire [31:0] io_imem_bits_data_0 = io_imem_bits_data; // @[IBuf.scala:21:7]
wire [1:0] io_imem_bits_mask_0 = io_imem_bits_mask; // @[IBuf.scala:21:7]
wire io_imem_bits_xcpt_pf_inst_0 = io_imem_bits_xcpt_pf_inst; // @[IBuf.scala:21:7]
wire io_imem_bits_xcpt_gf_inst_0 = io_imem_bits_xcpt_gf_inst; // @[IBuf.scala:21:7]
wire io_imem_bits_xcpt_ae_inst_0 = io_imem_bits_xcpt_ae_inst; // @[IBuf.scala:21:7]
wire io_imem_bits_replay_0 = io_imem_bits_replay; // @[IBuf.scala:21:7]
wire io_kill_0 = io_kill; // @[IBuf.scala:21:7]
wire io_inst_0_ready_0 = io_inst_0_ready; // @[IBuf.scala:21:7]
wire [1:0] _replay_T_3 = 2'h1; // @[IBuf.scala:92:63]
wire [1:0] _full_insn_T = 2'h1; // @[IBuf.scala:93:44]
wire [1:0] _io_inst_0_bits_xcpt1_T = 2'h1; // @[IBuf.scala:96:59]
wire [1:0] _nReady_T = 2'h1; // @[IBuf.scala:102:89]
wire [1:0] _nReady_T_3 = 2'h2; // @[IBuf.scala:102:96]
wire _replay_T_4 = 1'h1; // @[IBuf.scala:92:63]
wire _full_insn_T_1 = 1'h1; // @[IBuf.scala:93:44]
wire _io_inst_0_bits_xcpt1_T_1 = 1'h1; // @[IBuf.scala:96:59]
wire _io_inst_0_bits_xcpt1_T_2 = 1'h1; // @[package.scala:39:86]
wire _nReady_T_1 = 1'h1; // @[IBuf.scala:102:89]
wire _io_inst_0_bits_xcpt0_T = 1'h0; // @[package.scala:39:86]
wire [31:0] _icMask_T = 32'hFFFFFFFF; // @[IBuf.scala:71:17]
wire [39:0] _buf_pc_T = 40'hFFFFFFFFFC; // @[IBuf.scala:59:37]
wire [2:0] _nReady_T_2 = 3'h2; // @[IBuf.scala:102:96]
wire _io_imem_ready_T_7; // @[IBuf.scala:44:60]
wire [39:0] _io_pc_T_1; // @[IBuf.scala:82:15]
wire _io_inst_0_valid_T_2; // @[IBuf.scala:94:36]
wire _io_inst_0_bits_xcpt0_T_1_pf_inst; // @[package.scala:39:76]
wire _io_inst_0_bits_xcpt0_T_1_gf_inst; // @[package.scala:39:76]
wire _io_inst_0_bits_xcpt0_T_1_ae_inst; // @[package.scala:39:76]
wire _io_inst_0_bits_xcpt1_WIRE_pf_inst; // @[IBuf.scala:96:81]
wire _io_inst_0_bits_xcpt1_WIRE_gf_inst; // @[IBuf.scala:96:81]
wire _io_inst_0_bits_xcpt1_WIRE_ae_inst; // @[IBuf.scala:96:81]
wire replay; // @[IBuf.scala:92:33]
wire [31:0] inst; // @[IBuf.scala:72:30]
wire io_imem_ready_0; // @[IBuf.scala:21:7]
wire [7:0] io_btb_resp_bht_history_0; // @[IBuf.scala:21:7]
wire io_btb_resp_bht_value_0; // @[IBuf.scala:21:7]
wire [1:0] io_btb_resp_cfiType_0; // @[IBuf.scala:21:7]
wire io_btb_resp_taken_0; // @[IBuf.scala:21:7]
wire [1:0] io_btb_resp_mask_0; // @[IBuf.scala:21:7]
wire io_btb_resp_bridx_0; // @[IBuf.scala:21:7]
wire [38:0] io_btb_resp_target_0; // @[IBuf.scala:21:7]
wire [4:0] io_btb_resp_entry_0; // @[IBuf.scala:21:7]
wire io_inst_0_bits_xcpt0_pf_inst_0; // @[IBuf.scala:21:7]
wire io_inst_0_bits_xcpt0_gf_inst_0; // @[IBuf.scala:21:7]
wire io_inst_0_bits_xcpt0_ae_inst_0; // @[IBuf.scala:21:7]
wire io_inst_0_bits_xcpt1_pf_inst_0; // @[IBuf.scala:21:7]
wire io_inst_0_bits_xcpt1_gf_inst_0; // @[IBuf.scala:21:7]
wire io_inst_0_bits_xcpt1_ae_inst_0; // @[IBuf.scala:21:7]
wire [31:0] io_inst_0_bits_inst_bits_0; // @[IBuf.scala:21:7]
wire [4:0] io_inst_0_bits_inst_rd_0; // @[IBuf.scala:21:7]
wire [4:0] io_inst_0_bits_inst_rs1_0; // @[IBuf.scala:21:7]
wire [4:0] io_inst_0_bits_inst_rs2_0; // @[IBuf.scala:21:7]
wire [4:0] io_inst_0_bits_inst_rs3_0; // @[IBuf.scala:21:7]
wire io_inst_0_bits_replay_0; // @[IBuf.scala:21:7]
wire io_inst_0_bits_rvc_0; // @[IBuf.scala:21:7]
wire [31:0] io_inst_0_bits_raw_0; // @[IBuf.scala:21:7]
wire io_inst_0_valid_0; // @[IBuf.scala:21:7]
wire [39:0] io_pc_0; // @[IBuf.scala:21:7]
reg nBufValid; // @[IBuf.scala:34:47]
wire _io_pc_T = nBufValid; // @[IBuf.scala:34:47, :82:26]
reg [1:0] buf_btb_cfiType; // @[IBuf.scala:35:16]
reg buf_btb_taken; // @[IBuf.scala:35:16]
reg [1:0] buf_btb_mask; // @[IBuf.scala:35:16]
reg buf_btb_bridx; // @[IBuf.scala:35:16]
reg [38:0] buf_btb_target; // @[IBuf.scala:35:16]
reg [4:0] buf_btb_entry; // @[IBuf.scala:35:16]
reg [7:0] buf_btb_bht_history; // @[IBuf.scala:35:16]
reg buf_btb_bht_value; // @[IBuf.scala:35:16]
reg [39:0] buf_pc; // @[IBuf.scala:35:16]
reg [31:0] buf_data; // @[IBuf.scala:35:16]
reg [1:0] buf_mask; // @[IBuf.scala:35:16]
reg buf_xcpt_pf_inst; // @[IBuf.scala:35:16]
reg buf_xcpt_gf_inst; // @[IBuf.scala:35:16]
reg buf_xcpt_ae_inst; // @[IBuf.scala:35:16]
reg buf_replay; // @[IBuf.scala:35:16]
reg [1:0] ibufBTBResp_cfiType; // @[IBuf.scala:36:24]
reg ibufBTBResp_taken; // @[IBuf.scala:36:24]
reg [1:0] ibufBTBResp_mask; // @[IBuf.scala:36:24]
reg ibufBTBResp_bridx; // @[IBuf.scala:36:24]
reg [38:0] ibufBTBResp_target; // @[IBuf.scala:36:24]
reg [4:0] ibufBTBResp_entry; // @[IBuf.scala:36:24]
reg [7:0] ibufBTBResp_bht_history; // @[IBuf.scala:36:24]
reg ibufBTBResp_bht_value; // @[IBuf.scala:36:24]
wire pcWordBits = io_imem_bits_pc_0[1]; // @[package.scala:163:13]
wire [1:0] nReady; // @[IBuf.scala:40:27]
wire [1:0] _nIC_T = {1'h0, io_imem_bits_btb_bridx_0} + 2'h1; // @[IBuf.scala:21:7, :41:64]
wire [1:0] _nIC_T_1 = io_imem_bits_btb_taken_0 ? _nIC_T : 2'h2; // @[IBuf.scala:21:7, :41:{16,64}]
wire [2:0] _GEN = {2'h0, pcWordBits}; // @[package.scala:163:13]
wire [2:0] _nIC_T_2 = {1'h0, _nIC_T_1} - _GEN; // @[IBuf.scala:41:{16,86}]
wire [1:0] nIC = _nIC_T_2[1:0]; // @[IBuf.scala:41:86]
wire [2:0] _GEN_0 = {1'h0, nReady}; // @[IBuf.scala:40:27, :42:25]
wire [2:0] _GEN_1 = {2'h0, nBufValid}; // @[IBuf.scala:34:47, :42:25]
wire [2:0] _nICReady_T = _GEN_0 - _GEN_1; // @[IBuf.scala:42:25]
wire [1:0] nICReady = _nICReady_T[1:0]; // @[IBuf.scala:42:25]
wire [1:0] _nValid_T = io_imem_valid_0 ? nIC : 2'h0; // @[IBuf.scala:21:7, :41:86, :43:19]
wire [2:0] _nValid_T_1 = {1'h0, _nValid_T} + _GEN_1; // @[IBuf.scala:42:25, :43:{19,45}]
wire [1:0] nValid = _nValid_T_1[1:0]; // @[IBuf.scala:43:45]
wire [1:0] _GEN_2 = {1'h0, nBufValid}; // @[IBuf.scala:34:47, :44:47]
wire _T = nReady >= _GEN_2; // @[IBuf.scala:40:27, :44:47]
wire _io_imem_ready_T; // @[IBuf.scala:44:47]
assign _io_imem_ready_T = _T; // @[IBuf.scala:44:47]
wire _nBufValid_T; // @[package.scala:218:33]
assign _nBufValid_T = _T; // @[package.scala:218:33]
wire _io_imem_ready_T_1 = io_inst_0_ready_0 & _io_imem_ready_T; // @[IBuf.scala:21:7, :44:{37,47}]
wire _io_imem_ready_T_2 = nICReady >= nIC; // @[IBuf.scala:41:86, :42:25, :44:73]
wire [2:0] _GEN_3 = {1'h0, nICReady}; // @[IBuf.scala:42:25, :44:94]
wire [2:0] _T_4 = {1'h0, nIC} - _GEN_3; // @[IBuf.scala:41:86, :44:94]
wire [2:0] _io_imem_ready_T_3; // @[IBuf.scala:44:94]
assign _io_imem_ready_T_3 = _T_4; // @[IBuf.scala:44:94]
wire [2:0] _nBufValid_T_6; // @[IBuf.scala:56:26]
assign _nBufValid_T_6 = _T_4; // @[IBuf.scala:44:94, :56:26]
wire [1:0] _io_imem_ready_T_4 = _io_imem_ready_T_3[1:0]; // @[IBuf.scala:44:94]
wire _io_imem_ready_T_5 = ~(_io_imem_ready_T_4[1]); // @[IBuf.scala:44:{87,94}]
wire _io_imem_ready_T_6 = _io_imem_ready_T_2 | _io_imem_ready_T_5; // @[IBuf.scala:44:{73,80,87}]
assign _io_imem_ready_T_7 = _io_imem_ready_T_1 & _io_imem_ready_T_6; // @[IBuf.scala:44:{37,60,80}]
assign io_imem_ready_0 = _io_imem_ready_T_7; // @[IBuf.scala:21:7, :44:60]
wire _nBufValid_T_1 = ~nBufValid; // @[package.scala:218:43]
wire _nBufValid_T_2 = _nBufValid_T | _nBufValid_T_1; // @[package.scala:218:{33,38,43}]
wire [2:0] _nBufValid_T_3 = _GEN_1 - _GEN_0; // @[IBuf.scala:42:25, :48:61]
wire [1:0] _nBufValid_T_4 = _nBufValid_T_3[1:0]; // @[IBuf.scala:48:61]
wire [1:0] _nBufValid_T_5 = _nBufValid_T_2 ? 2'h0 : _nBufValid_T_4; // @[package.scala:218:38]
wire [2:0] _shamt_T = _GEN + _GEN_3; // @[IBuf.scala:41:86, :44:94, :55:32]
wire [1:0] shamt = _shamt_T[1:0]; // @[IBuf.scala:55:32]
wire [1:0] _nBufValid_T_7 = _nBufValid_T_6[1:0]; // @[IBuf.scala:56:26]
wire [15:0] _buf_data_data_T = io_imem_bits_data_0[31:16]; // @[IBuf.scala:21:7, :127:58]
wire [31:0] _buf_data_data_T_1 = {2{_buf_data_data_T}}; // @[IBuf.scala:127:{24,58}]
wire [63:0] buf_data_data = {_buf_data_data_T_1, io_imem_bits_data_0}; // @[IBuf.scala:21:7, :127:{19,24}]
wire [5:0] _buf_data_T = {shamt, 4'h0}; // @[IBuf.scala:55:32, :128:19]
wire [63:0] _buf_data_T_1 = buf_data_data >> _buf_data_T; // @[IBuf.scala:127:19, :128:{10,19}]
wire [15:0] _buf_data_T_2 = _buf_data_T_1[15:0]; // @[IBuf.scala:58:61, :128:10]
wire [39:0] _buf_pc_T_1 = io_imem_bits_pc_0 & 40'hFFFFFFFFFC; // @[IBuf.scala:21:7, :59:35]
wire [2:0] _buf_pc_T_2 = {nICReady, 1'h0}; // @[IBuf.scala:42:25, :59:80]
wire [40:0] _buf_pc_T_3 = {1'h0, io_imem_bits_pc_0} + {38'h0, _buf_pc_T_2}; // @[IBuf.scala:21:7, :59:{68,80}]
wire [39:0] _buf_pc_T_4 = _buf_pc_T_3[39:0]; // @[IBuf.scala:59:68]
wire [39:0] _buf_pc_T_5 = _buf_pc_T_4 & 40'h3; // @[IBuf.scala:59:{68,109}]
wire [39:0] _buf_pc_T_6 = _buf_pc_T_1 | _buf_pc_T_5; // @[IBuf.scala:59:{35,49,109}]
wire [2:0] _icShiftAmt_T = _GEN_1 + 3'h2; // @[IBuf.scala:42:25, :68:34]
wire [1:0] _icShiftAmt_T_1 = _icShiftAmt_T[1:0]; // @[IBuf.scala:68:34]
wire [2:0] _icShiftAmt_T_2 = {1'h0, _icShiftAmt_T_1} - _GEN; // @[IBuf.scala:41:86, :68:{34,46}]
wire [1:0] _icShiftAmt_T_3 = _icShiftAmt_T_2[1:0]; // @[IBuf.scala:68:46]
wire [1:0] icShiftAmt = _icShiftAmt_T_3; // @[IBuf.scala:68:{46,59}]
wire [15:0] _icData_T = io_imem_bits_data_0[15:0]; // @[IBuf.scala:21:7, :69:87]
wire [31:0] _icData_T_1 = {2{_icData_T}}; // @[IBuf.scala:69:{57,87}]
wire [63:0] _icData_T_2 = {io_imem_bits_data_0, _icData_T_1}; // @[IBuf.scala:21:7, :69:{33,57}]
wire [15:0] _icData_data_T = _icData_T_2[63:48]; // @[IBuf.scala:69:33, :120:58]
wire [31:0] _icData_data_T_1 = {2{_icData_data_T}}; // @[IBuf.scala:120:{24,58}]
wire [63:0] _icData_data_T_2 = {2{_icData_data_T_1}}; // @[IBuf.scala:120:24]
wire [127:0] icData_data = {_icData_data_T_2, _icData_T_2}; // @[IBuf.scala:69:33, :120:{19,24}]
wire [5:0] _icData_T_3 = {icShiftAmt, 4'h0}; // @[IBuf.scala:68:59, :121:19]
wire [190:0] _icData_T_4 = {63'h0, icData_data} << _icData_T_3; // @[IBuf.scala:120:19, :121:{10,19}]
wire [31:0] icData = _icData_T_4[95:64]; // @[package.scala:163:13]
wire [4:0] _icMask_T_1 = {nBufValid, 4'h0}; // @[IBuf.scala:34:47, :71:65]
wire [62:0] _icMask_T_2 = 63'hFFFFFFFF << _icMask_T_1; // @[IBuf.scala:71:{51,65}]
wire [31:0] icMask = _icMask_T_2[31:0]; // @[IBuf.scala:71:{51,92}]
wire [31:0] _inst_T = icData & icMask; // @[package.scala:163:13]
wire [31:0] _inst_T_1 = ~icMask; // @[IBuf.scala:71:92, :72:43]
wire [31:0] _inst_T_2 = buf_data & _inst_T_1; // @[IBuf.scala:35:16, :72:{41,43}]
assign inst = _inst_T | _inst_T_2; // @[IBuf.scala:72:{21,30,41}]
assign io_inst_0_bits_raw_0 = inst; // @[IBuf.scala:21:7, :72:30]
wire [3:0] _valid_T = 4'h1 << nValid; // @[OneHot.scala:58:35]
wire [4:0] _valid_T_1 = {1'h0, _valid_T} - 5'h1; // @[OneHot.scala:58:35]
wire [3:0] _valid_T_2 = _valid_T_1[3:0]; // @[IBuf.scala:74:33]
wire [1:0] valid = _valid_T_2[1:0]; // @[IBuf.scala:74:{33,39}]
wire [1:0] _io_inst_0_valid_T = valid; // @[IBuf.scala:74:39, :94:32]
wire [1:0] _bufMask_T = 2'h1 << _GEN_2; // @[OneHot.scala:58:35]
wire [2:0] _bufMask_T_1 = {1'h0, _bufMask_T} - 3'h1; // @[OneHot.scala:58:35]
wire [1:0] bufMask = _bufMask_T_1[1:0]; // @[IBuf.scala:75:37]
wire _xcpt_T = bufMask[0]; // @[IBuf.scala:75:37, :76:61]
wire xcpt_0_pf_inst = _xcpt_T ? buf_xcpt_pf_inst : io_imem_bits_xcpt_pf_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}]
wire xcpt_0_gf_inst = _xcpt_T ? buf_xcpt_gf_inst : io_imem_bits_xcpt_gf_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}]
wire xcpt_0_ae_inst = _xcpt_T ? buf_xcpt_ae_inst : io_imem_bits_xcpt_ae_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}]
assign _io_inst_0_bits_xcpt0_T_1_pf_inst = xcpt_0_pf_inst; // @[package.scala:39:76]
assign _io_inst_0_bits_xcpt0_T_1_gf_inst = xcpt_0_gf_inst; // @[package.scala:39:76]
assign _io_inst_0_bits_xcpt0_T_1_ae_inst = xcpt_0_ae_inst; // @[package.scala:39:76]
wire _xcpt_T_1 = bufMask[1]; // @[IBuf.scala:75:37, :76:61]
wire xcpt_1_pf_inst = _xcpt_T_1 ? buf_xcpt_pf_inst : io_imem_bits_xcpt_pf_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}]
wire xcpt_1_gf_inst = _xcpt_T_1 ? buf_xcpt_gf_inst : io_imem_bits_xcpt_gf_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}]
wire xcpt_1_ae_inst = _xcpt_T_1 ? buf_xcpt_ae_inst : io_imem_bits_xcpt_ae_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}]
wire _io_inst_0_bits_xcpt1_T_3_pf_inst = xcpt_1_pf_inst; // @[package.scala:39:76]
wire _io_inst_0_bits_xcpt1_T_3_gf_inst = xcpt_1_gf_inst; // @[package.scala:39:76]
wire _io_inst_0_bits_xcpt1_T_3_ae_inst = xcpt_1_ae_inst; // @[package.scala:39:76]
wire [1:0] buf_replay_0 = buf_replay ? bufMask : 2'h0; // @[IBuf.scala:35:16, :75:37, :77:23]
wire [1:0] _full_insn_T_5 = buf_replay_0; // @[IBuf.scala:77:23, :93:63]
wire [1:0] _ic_replay_T = ~bufMask; // @[IBuf.scala:75:37, :78:65]
wire [1:0] _ic_replay_T_1 = valid & _ic_replay_T; // @[IBuf.scala:74:39, :78:{63,65}]
wire [1:0] _ic_replay_T_2 = io_imem_bits_replay_0 ? _ic_replay_T_1 : 2'h0; // @[IBuf.scala:21:7, :78:{35,63}]
wire [1:0] ic_replay = buf_replay_0 | _ic_replay_T_2; // @[IBuf.scala:77:23, :78:{30,35}]
wire [1:0] _replay_T = ic_replay; // @[IBuf.scala:78:30, :92:29] |
Generate the Verilog code corresponding to this FIRRTL code module CounterController :
input clock : Clock
input reset : Reset
output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { rd : UInt<5>, data : UInt<64>}}, flip event_io : { event_signal : UInt<1>[45], external_values : UInt<32>[8], flip external_reset : UInt<1>}}
inst counterfile of CounterFile
connect counterfile.clock, clock
connect counterfile.reset, reset
connect counterfile.io.event_io, io.event_io
reg out_reg : { rd : UInt<5>, data : UInt<64>}, clock
regreset out_valid_reg : UInt<1>, clock, reset, UInt<1>(0h0)
node _io_in_ready_T = eq(out_valid_reg, UInt<1>(0h0))
connect io.in.ready, _io_in_ready_T
node _counterfile_io_addr_T = bits(io.in.bits.rs1, 6, 4)
connect counterfile.io.addr, _counterfile_io_addr_T
node _counterfile_io_counter_reset_T = bits(io.in.bits.rs1, 0, 0)
node _counterfile_io_counter_reset_T_1 = and(io.in.ready, io.in.valid)
node _counterfile_io_counter_reset_T_2 = and(_counterfile_io_counter_reset_T, _counterfile_io_counter_reset_T_1)
connect counterfile.io.counter_reset, _counterfile_io_counter_reset_T_2
node _counterfile_io_snapshot_reset_T = bits(io.in.bits.rs1, 1, 1)
node _counterfile_io_snapshot_reset_T_1 = and(io.in.ready, io.in.valid)
node _counterfile_io_snapshot_reset_T_2 = and(_counterfile_io_snapshot_reset_T, _counterfile_io_snapshot_reset_T_1)
connect counterfile.io.snapshot_reset, _counterfile_io_snapshot_reset_T_2
node _counterfile_io_snapshot_T = bits(io.in.bits.rs1, 2, 2)
node _counterfile_io_snapshot_T_1 = and(io.in.ready, io.in.valid)
node _counterfile_io_snapshot_T_2 = and(_counterfile_io_snapshot_T, _counterfile_io_snapshot_T_1)
connect counterfile.io.snapshot, _counterfile_io_snapshot_T_2
node _counterfile_io_config_address_valid_T = bits(io.in.bits.rs1, 3, 3)
node _counterfile_io_config_address_valid_T_1 = and(io.in.ready, io.in.valid)
node _counterfile_io_config_address_valid_T_2 = and(_counterfile_io_config_address_valid_T, _counterfile_io_config_address_valid_T_1)
connect counterfile.io.config_address.valid, _counterfile_io_config_address_valid_T_2
node _counterfile_io_config_address_bits_T = bits(io.in.bits.rs1, 17, 12)
connect counterfile.io.config_address.bits, _counterfile_io_config_address_bits_T
node _counterfile_io_external_T = bits(io.in.bits.rs1, 31, 31)
connect counterfile.io.external, _counterfile_io_external_T
node _T = and(io.out.ready, io.out.valid)
when _T :
connect out_valid_reg, UInt<1>(0h0)
else :
node _T_1 = and(io.in.ready, io.in.valid)
when _T_1 :
connect out_valid_reg, UInt<1>(0h1)
connect out_reg.rd, io.in.bits.inst.rd
connect out_reg.data, UInt<1>(0h0)
connect out_reg.data, counterfile.io.data
connect io.out.valid, out_valid_reg
connect io.out.bits, out_reg | module CounterController( // @[CounterFile.scala:218:7]
input clock, // @[CounterFile.scala:218:7]
input reset, // @[CounterFile.scala:218:7]
output io_in_ready, // @[CounterFile.scala:219:14]
input io_in_valid, // @[CounterFile.scala:219:14]
input [6:0] io_in_bits_inst_funct, // @[CounterFile.scala:219:14]
input [4:0] io_in_bits_inst_rs2, // @[CounterFile.scala:219:14]
input [4:0] io_in_bits_inst_rs1, // @[CounterFile.scala:219:14]
input io_in_bits_inst_xd, // @[CounterFile.scala:219:14]
input io_in_bits_inst_xs1, // @[CounterFile.scala:219:14]
input io_in_bits_inst_xs2, // @[CounterFile.scala:219:14]
input [4:0] io_in_bits_inst_rd, // @[CounterFile.scala:219:14]
input [6:0] io_in_bits_inst_opcode, // @[CounterFile.scala:219:14]
input [63:0] io_in_bits_rs1, // @[CounterFile.scala:219:14]
input [63:0] io_in_bits_rs2, // @[CounterFile.scala:219:14]
input io_in_bits_status_debug, // @[CounterFile.scala:219:14]
input io_in_bits_status_cease, // @[CounterFile.scala:219:14]
input io_in_bits_status_wfi, // @[CounterFile.scala:219:14]
input [31:0] io_in_bits_status_isa, // @[CounterFile.scala:219:14]
input [1:0] io_in_bits_status_dprv, // @[CounterFile.scala:219:14]
input io_in_bits_status_dv, // @[CounterFile.scala:219:14]
input [1:0] io_in_bits_status_prv, // @[CounterFile.scala:219:14]
input io_in_bits_status_v, // @[CounterFile.scala:219:14]
input io_in_bits_status_sd, // @[CounterFile.scala:219:14]
input [22:0] io_in_bits_status_zero2, // @[CounterFile.scala:219:14]
input io_in_bits_status_mpv, // @[CounterFile.scala:219:14]
input io_in_bits_status_gva, // @[CounterFile.scala:219:14]
input io_in_bits_status_mbe, // @[CounterFile.scala:219:14]
input io_in_bits_status_sbe, // @[CounterFile.scala:219:14]
input [1:0] io_in_bits_status_sxl, // @[CounterFile.scala:219:14]
input [1:0] io_in_bits_status_uxl, // @[CounterFile.scala:219:14]
input io_in_bits_status_sd_rv32, // @[CounterFile.scala:219:14]
input [7:0] io_in_bits_status_zero1, // @[CounterFile.scala:219:14]
input io_in_bits_status_tsr, // @[CounterFile.scala:219:14]
input io_in_bits_status_tw, // @[CounterFile.scala:219:14]
input io_in_bits_status_tvm, // @[CounterFile.scala:219:14]
input io_in_bits_status_mxr, // @[CounterFile.scala:219:14]
input io_in_bits_status_sum, // @[CounterFile.scala:219:14]
input io_in_bits_status_mprv, // @[CounterFile.scala:219:14]
input [1:0] io_in_bits_status_xs, // @[CounterFile.scala:219:14]
input [1:0] io_in_bits_status_fs, // @[CounterFile.scala:219:14]
input [1:0] io_in_bits_status_mpp, // @[CounterFile.scala:219:14]
input [1:0] io_in_bits_status_vs, // @[CounterFile.scala:219:14]
input io_in_bits_status_spp, // @[CounterFile.scala:219:14]
input io_in_bits_status_mpie, // @[CounterFile.scala:219:14]
input io_in_bits_status_ube, // @[CounterFile.scala:219:14]
input io_in_bits_status_spie, // @[CounterFile.scala:219:14]
input io_in_bits_status_upie, // @[CounterFile.scala:219:14]
input io_in_bits_status_mie, // @[CounterFile.scala:219:14]
input io_in_bits_status_hie, // @[CounterFile.scala:219:14]
input io_in_bits_status_sie, // @[CounterFile.scala:219:14]
input io_in_bits_status_uie, // @[CounterFile.scala:219:14]
input io_out_ready, // @[CounterFile.scala:219:14]
output io_out_valid, // @[CounterFile.scala:219:14]
output [4:0] io_out_bits_rd, // @[CounterFile.scala:219:14]
output [63:0] io_out_bits_data, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_1, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_2, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_3, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_4, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_5, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_6, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_7, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_8, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_9, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_10, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_11, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_12, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_13, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_14, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_15, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_16, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_17, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_18, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_19, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_20, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_21, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_22, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_23, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_24, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_25, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_26, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_29, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_30, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_31, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_32, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_33, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_34, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_35, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_36, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_37, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_38, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_39, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_40, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_41, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_42, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_43, // @[CounterFile.scala:219:14]
input [31:0] io_event_io_external_values_1, // @[CounterFile.scala:219:14]
input [31:0] io_event_io_external_values_2, // @[CounterFile.scala:219:14]
input [31:0] io_event_io_external_values_3, // @[CounterFile.scala:219:14]
input [31:0] io_event_io_external_values_4, // @[CounterFile.scala:219:14]
input [31:0] io_event_io_external_values_5, // @[CounterFile.scala:219:14]
input [31:0] io_event_io_external_values_6, // @[CounterFile.scala:219:14]
input [31:0] io_event_io_external_values_7, // @[CounterFile.scala:219:14]
output io_event_io_external_reset // @[CounterFile.scala:219:14]
);
wire [63:0] _counterfile_io_data; // @[CounterFile.scala:228:29]
wire io_in_valid_0 = io_in_valid; // @[CounterFile.scala:218:7]
wire [6:0] io_in_bits_inst_funct_0 = io_in_bits_inst_funct; // @[CounterFile.scala:218:7]
wire [4:0] io_in_bits_inst_rs2_0 = io_in_bits_inst_rs2; // @[CounterFile.scala:218:7]
wire [4:0] io_in_bits_inst_rs1_0 = io_in_bits_inst_rs1; // @[CounterFile.scala:218:7]
wire io_in_bits_inst_xd_0 = io_in_bits_inst_xd; // @[CounterFile.scala:218:7]
wire io_in_bits_inst_xs1_0 = io_in_bits_inst_xs1; // @[CounterFile.scala:218:7]
wire io_in_bits_inst_xs2_0 = io_in_bits_inst_xs2; // @[CounterFile.scala:218:7]
wire [4:0] io_in_bits_inst_rd_0 = io_in_bits_inst_rd; // @[CounterFile.scala:218:7]
wire [6:0] io_in_bits_inst_opcode_0 = io_in_bits_inst_opcode; // @[CounterFile.scala:218:7]
wire [63:0] io_in_bits_rs1_0 = io_in_bits_rs1; // @[CounterFile.scala:218:7]
wire [63:0] io_in_bits_rs2_0 = io_in_bits_rs2; // @[CounterFile.scala:218:7]
wire io_in_bits_status_debug_0 = io_in_bits_status_debug; // @[CounterFile.scala:218:7]
wire io_in_bits_status_cease_0 = io_in_bits_status_cease; // @[CounterFile.scala:218:7]
wire io_in_bits_status_wfi_0 = io_in_bits_status_wfi; // @[CounterFile.scala:218:7]
wire [31:0] io_in_bits_status_isa_0 = io_in_bits_status_isa; // @[CounterFile.scala:218:7]
wire [1:0] io_in_bits_status_dprv_0 = io_in_bits_status_dprv; // @[CounterFile.scala:218:7]
wire io_in_bits_status_dv_0 = io_in_bits_status_dv; // @[CounterFile.scala:218:7]
wire [1:0] io_in_bits_status_prv_0 = io_in_bits_status_prv; // @[CounterFile.scala:218:7]
wire io_in_bits_status_v_0 = io_in_bits_status_v; // @[CounterFile.scala:218:7]
wire io_in_bits_status_sd_0 = io_in_bits_status_sd; // @[CounterFile.scala:218:7]
wire [22:0] io_in_bits_status_zero2_0 = io_in_bits_status_zero2; // @[CounterFile.scala:218:7]
wire io_in_bits_status_mpv_0 = io_in_bits_status_mpv; // @[CounterFile.scala:218:7]
wire io_in_bits_status_gva_0 = io_in_bits_status_gva; // @[CounterFile.scala:218:7]
wire io_in_bits_status_mbe_0 = io_in_bits_status_mbe; // @[CounterFile.scala:218:7]
wire io_in_bits_status_sbe_0 = io_in_bits_status_sbe; // @[CounterFile.scala:218:7]
wire [1:0] io_in_bits_status_sxl_0 = io_in_bits_status_sxl; // @[CounterFile.scala:218:7]
wire [1:0] io_in_bits_status_uxl_0 = io_in_bits_status_uxl; // @[CounterFile.scala:218:7]
wire io_in_bits_status_sd_rv32_0 = io_in_bits_status_sd_rv32; // @[CounterFile.scala:218:7]
wire [7:0] io_in_bits_status_zero1_0 = io_in_bits_status_zero1; // @[CounterFile.scala:218:7]
wire io_in_bits_status_tsr_0 = io_in_bits_status_tsr; // @[CounterFile.scala:218:7]
wire io_in_bits_status_tw_0 = io_in_bits_status_tw; // @[CounterFile.scala:218:7]
wire io_in_bits_status_tvm_0 = io_in_bits_status_tvm; // @[CounterFile.scala:218:7]
wire io_in_bits_status_mxr_0 = io_in_bits_status_mxr; // @[CounterFile.scala:218:7]
wire io_in_bits_status_sum_0 = io_in_bits_status_sum; // @[CounterFile.scala:218:7]
wire io_in_bits_status_mprv_0 = io_in_bits_status_mprv; // @[CounterFile.scala:218:7]
wire [1:0] io_in_bits_status_xs_0 = io_in_bits_status_xs; // @[CounterFile.scala:218:7]
wire [1:0] io_in_bits_status_fs_0 = io_in_bits_status_fs; // @[CounterFile.scala:218:7]
wire [1:0] io_in_bits_status_mpp_0 = io_in_bits_status_mpp; // @[CounterFile.scala:218:7]
wire [1:0] io_in_bits_status_vs_0 = io_in_bits_status_vs; // @[CounterFile.scala:218:7]
wire io_in_bits_status_spp_0 = io_in_bits_status_spp; // @[CounterFile.scala:218:7]
wire io_in_bits_status_mpie_0 = io_in_bits_status_mpie; // @[CounterFile.scala:218:7]
wire io_in_bits_status_ube_0 = io_in_bits_status_ube; // @[CounterFile.scala:218:7]
wire io_in_bits_status_spie_0 = io_in_bits_status_spie; // @[CounterFile.scala:218:7]
wire io_in_bits_status_upie_0 = io_in_bits_status_upie; // @[CounterFile.scala:218:7]
wire io_in_bits_status_mie_0 = io_in_bits_status_mie; // @[CounterFile.scala:218:7]
wire io_in_bits_status_hie_0 = io_in_bits_status_hie; // @[CounterFile.scala:218:7]
wire io_in_bits_status_sie_0 = io_in_bits_status_sie; // @[CounterFile.scala:218:7]
wire io_in_bits_status_uie_0 = io_in_bits_status_uie; // @[CounterFile.scala:218:7]
wire io_out_ready_0 = io_out_ready; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_1_0 = io_event_io_event_signal_1; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_2_0 = io_event_io_event_signal_2; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_3_0 = io_event_io_event_signal_3; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_4_0 = io_event_io_event_signal_4; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_5_0 = io_event_io_event_signal_5; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_6_0 = io_event_io_event_signal_6; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_7_0 = io_event_io_event_signal_7; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_8_0 = io_event_io_event_signal_8; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_9_0 = io_event_io_event_signal_9; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_10_0 = io_event_io_event_signal_10; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_11_0 = io_event_io_event_signal_11; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_12_0 = io_event_io_event_signal_12; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_13_0 = io_event_io_event_signal_13; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_14_0 = io_event_io_event_signal_14; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_15_0 = io_event_io_event_signal_15; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_16_0 = io_event_io_event_signal_16; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_17_0 = io_event_io_event_signal_17; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_18_0 = io_event_io_event_signal_18; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_19_0 = io_event_io_event_signal_19; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_20_0 = io_event_io_event_signal_20; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_21_0 = io_event_io_event_signal_21; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_22_0 = io_event_io_event_signal_22; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_23_0 = io_event_io_event_signal_23; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_24_0 = io_event_io_event_signal_24; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_25_0 = io_event_io_event_signal_25; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_26_0 = io_event_io_event_signal_26; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_29_0 = io_event_io_event_signal_29; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_30_0 = io_event_io_event_signal_30; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_31_0 = io_event_io_event_signal_31; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_32_0 = io_event_io_event_signal_32; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_33_0 = io_event_io_event_signal_33; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_34_0 = io_event_io_event_signal_34; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_35_0 = io_event_io_event_signal_35; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_36_0 = io_event_io_event_signal_36; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_37_0 = io_event_io_event_signal_37; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_38_0 = io_event_io_event_signal_38; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_39_0 = io_event_io_event_signal_39; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_40_0 = io_event_io_event_signal_40; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_41_0 = io_event_io_event_signal_41; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_42_0 = io_event_io_event_signal_42; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_43_0 = io_event_io_event_signal_43; // @[CounterFile.scala:218:7]
wire [31:0] io_event_io_external_values_1_0 = io_event_io_external_values_1; // @[CounterFile.scala:218:7]
wire [31:0] io_event_io_external_values_2_0 = io_event_io_external_values_2; // @[CounterFile.scala:218:7]
wire [31:0] io_event_io_external_values_3_0 = io_event_io_external_values_3; // @[CounterFile.scala:218:7]
wire [31:0] io_event_io_external_values_4_0 = io_event_io_external_values_4; // @[CounterFile.scala:218:7]
wire [31:0] io_event_io_external_values_5_0 = io_event_io_external_values_5; // @[CounterFile.scala:218:7]
wire [31:0] io_event_io_external_values_6_0 = io_event_io_external_values_6; // @[CounterFile.scala:218:7]
wire [31:0] io_event_io_external_values_7_0 = io_event_io_external_values_7; // @[CounterFile.scala:218:7]
wire [31:0] io_event_io_external_values_0 = 32'h0; // @[CounterFile.scala:218:7, :219:14, :228:29]
wire io_event_io_event_signal_0 = 1'h0; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_27 = 1'h0; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_28 = 1'h0; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_44 = 1'h0; // @[CounterFile.scala:218:7]
wire _io_in_ready_T; // @[CounterFile.scala:244:20]
wire io_in_ready_0; // @[CounterFile.scala:218:7]
wire [4:0] io_out_bits_rd_0; // @[CounterFile.scala:218:7]
wire [63:0] io_out_bits_data_0; // @[CounterFile.scala:218:7]
wire io_out_valid_0; // @[CounterFile.scala:218:7]
wire io_event_io_external_reset_0; // @[CounterFile.scala:218:7]
reg [4:0] out_reg_rd; // @[CounterFile.scala:231:22]
assign io_out_bits_rd_0 = out_reg_rd; // @[CounterFile.scala:218:7, :231:22]
reg [63:0] out_reg_data; // @[CounterFile.scala:231:22]
assign io_out_bits_data_0 = out_reg_data; // @[CounterFile.scala:218:7, :231:22]
reg out_valid_reg; // @[CounterFile.scala:232:32]
assign io_out_valid_0 = out_valid_reg; // @[CounterFile.scala:218:7, :232:32]
assign _io_in_ready_T = ~out_valid_reg; // @[CounterFile.scala:232:32, :244:20]
assign io_in_ready_0 = _io_in_ready_T; // @[CounterFile.scala:218:7, :244:20]
wire [2:0] _counterfile_io_addr_T = io_in_bits_rs1_0[6:4]; // @[CounterFile.scala:218:7, :245:42]
wire _counterfile_io_counter_reset_T = io_in_bits_rs1_0[0]; // @[CounterFile.scala:218:7, :246:51]
wire _T_1 = io_in_ready_0 & io_in_valid_0; // @[Decoupled.scala:51:35]
wire _counterfile_io_counter_reset_T_1; // @[Decoupled.scala:51:35]
assign _counterfile_io_counter_reset_T_1 = _T_1; // @[Decoupled.scala:51:35]
wire _counterfile_io_snapshot_reset_T_1; // @[Decoupled.scala:51:35]
assign _counterfile_io_snapshot_reset_T_1 = _T_1; // @[Decoupled.scala:51:35]
wire _counterfile_io_snapshot_T_1; // @[Decoupled.scala:51:35]
assign _counterfile_io_snapshot_T_1 = _T_1; // @[Decoupled.scala:51:35]
wire _counterfile_io_config_address_valid_T_1; // @[Decoupled.scala:51:35]
assign _counterfile_io_config_address_valid_T_1 = _T_1; // @[Decoupled.scala:51:35]
wire _counterfile_io_counter_reset_T_2 = _counterfile_io_counter_reset_T & _counterfile_io_counter_reset_T_1; // @[Decoupled.scala:51:35]
wire _counterfile_io_snapshot_reset_T = io_in_bits_rs1_0[1]; // @[CounterFile.scala:218:7, :247:52]
wire _counterfile_io_snapshot_reset_T_2 = _counterfile_io_snapshot_reset_T & _counterfile_io_snapshot_reset_T_1; // @[Decoupled.scala:51:35]
wire _counterfile_io_snapshot_T = io_in_bits_rs1_0[2]; // @[CounterFile.scala:218:7, :248:46]
wire _counterfile_io_snapshot_T_2 = _counterfile_io_snapshot_T & _counterfile_io_snapshot_T_1; // @[Decoupled.scala:51:35]
wire _counterfile_io_config_address_valid_T = io_in_bits_rs1_0[3]; // @[CounterFile.scala:218:7, :249:58]
wire _counterfile_io_config_address_valid_T_2 = _counterfile_io_config_address_valid_T & _counterfile_io_config_address_valid_T_1; // @[Decoupled.scala:51:35]
wire [5:0] _counterfile_io_config_address_bits_T = io_in_bits_rs1_0[17:12]; // @[CounterFile.scala:218:7, :250:57]
wire _counterfile_io_external_T = io_in_bits_rs1_0[31]; // @[CounterFile.scala:218:7, :251:46]
wire _T = io_out_ready_0 & io_out_valid_0; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[CounterFile.scala:218:7]
if (_T | ~_T_1) begin // @[Decoupled.scala:51:35]
end
else begin // @[CounterFile.scala:231:22, :253:24, :255:30]
out_reg_rd <= io_in_bits_inst_rd_0; // @[CounterFile.scala:218:7, :231:22]
out_reg_data <= _counterfile_io_data; // @[CounterFile.scala:228:29, :231:22]
end
if (reset) // @[CounterFile.scala:218:7]
out_valid_reg <= 1'h0; // @[CounterFile.scala:232:32]
else // @[CounterFile.scala:218:7]
out_valid_reg <= ~_T & (_T_1 | out_valid_reg); // @[Decoupled.scala:51:35]
always @(posedge)
CounterFile counterfile ( // @[CounterFile.scala:228:29]
.clock (clock),
.reset (reset),
.io_counter_reset (_counterfile_io_counter_reset_T_2), // @[CounterFile.scala:246:55]
.io_snapshot (_counterfile_io_snapshot_T_2), // @[CounterFile.scala:248:50]
.io_snapshot_reset (_counterfile_io_snapshot_reset_T_2), // @[CounterFile.scala:247:56]
.io_addr (_counterfile_io_addr_T), // @[CounterFile.scala:245:42]
.io_data (_counterfile_io_data),
.io_config_address_valid (_counterfile_io_config_address_valid_T_2), // @[CounterFile.scala:249:62]
.io_config_address_bits (_counterfile_io_config_address_bits_T), // @[CounterFile.scala:250:57]
.io_external (_counterfile_io_external_T), // @[CounterFile.scala:251:46]
.io_event_io_event_signal_1 (io_event_io_event_signal_1_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_2 (io_event_io_event_signal_2_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_3 (io_event_io_event_signal_3_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_4 (io_event_io_event_signal_4_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_5 (io_event_io_event_signal_5_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_6 (io_event_io_event_signal_6_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_7 (io_event_io_event_signal_7_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_8 (io_event_io_event_signal_8_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_9 (io_event_io_event_signal_9_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_10 (io_event_io_event_signal_10_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_11 (io_event_io_event_signal_11_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_12 (io_event_io_event_signal_12_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_13 (io_event_io_event_signal_13_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_14 (io_event_io_event_signal_14_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_15 (io_event_io_event_signal_15_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_16 (io_event_io_event_signal_16_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_17 (io_event_io_event_signal_17_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_18 (io_event_io_event_signal_18_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_19 (io_event_io_event_signal_19_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_20 (io_event_io_event_signal_20_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_21 (io_event_io_event_signal_21_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_22 (io_event_io_event_signal_22_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_23 (io_event_io_event_signal_23_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_24 (io_event_io_event_signal_24_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_25 (io_event_io_event_signal_25_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_26 (io_event_io_event_signal_26_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_29 (io_event_io_event_signal_29_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_30 (io_event_io_event_signal_30_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_31 (io_event_io_event_signal_31_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_32 (io_event_io_event_signal_32_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_33 (io_event_io_event_signal_33_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_34 (io_event_io_event_signal_34_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_35 (io_event_io_event_signal_35_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_36 (io_event_io_event_signal_36_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_37 (io_event_io_event_signal_37_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_38 (io_event_io_event_signal_38_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_39 (io_event_io_event_signal_39_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_40 (io_event_io_event_signal_40_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_41 (io_event_io_event_signal_41_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_42 (io_event_io_event_signal_42_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_43 (io_event_io_event_signal_43_0), // @[CounterFile.scala:218:7]
.io_event_io_external_values_1 (io_event_io_external_values_1_0), // @[CounterFile.scala:218:7]
.io_event_io_external_values_2 (io_event_io_external_values_2_0), // @[CounterFile.scala:218:7]
.io_event_io_external_values_3 (io_event_io_external_values_3_0), // @[CounterFile.scala:218:7]
.io_event_io_external_values_4 (io_event_io_external_values_4_0), // @[CounterFile.scala:218:7]
.io_event_io_external_values_5 (io_event_io_external_values_5_0), // @[CounterFile.scala:218:7]
.io_event_io_external_values_6 (io_event_io_external_values_6_0), // @[CounterFile.scala:218:7]
.io_event_io_external_values_7 (io_event_io_external_values_7_0), // @[CounterFile.scala:218:7]
.io_event_io_external_reset (io_event_io_external_reset_0)
); // @[CounterFile.scala:228:29]
assign io_in_ready = io_in_ready_0; // @[CounterFile.scala:218:7]
assign io_out_valid = io_out_valid_0; // @[CounterFile.scala:218:7]
assign io_out_bits_rd = io_out_bits_rd_0; // @[CounterFile.scala:218:7]
assign io_out_bits_data = io_out_bits_data_0; // @[CounterFile.scala:218:7]
assign io_event_io_external_reset = io_event_io_external_reset_0; // @[CounterFile.scala:218:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_pbus_out_i1_o3_a29d64s7k1z3u :
input clock : Clock
input reset : Reset
output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn.d.bits.corrupt
invalidate anonIn.d.bits.data
invalidate anonIn.d.bits.denied
invalidate anonIn.d.bits.sink
invalidate anonIn.d.bits.source
invalidate anonIn.d.bits.size
invalidate anonIn.d.bits.param
invalidate anonIn.d.bits.opcode
invalidate anonIn.d.valid
invalidate anonIn.d.ready
invalidate anonIn.a.bits.corrupt
invalidate anonIn.a.bits.data
invalidate anonIn.a.bits.mask
invalidate anonIn.a.bits.user.amba_prot.fetch
invalidate anonIn.a.bits.user.amba_prot.secure
invalidate anonIn.a.bits.user.amba_prot.privileged
invalidate anonIn.a.bits.user.amba_prot.writealloc
invalidate anonIn.a.bits.user.amba_prot.readalloc
invalidate anonIn.a.bits.user.amba_prot.modifiable
invalidate anonIn.a.bits.user.amba_prot.bufferable
invalidate anonIn.a.bits.address
invalidate anonIn.a.bits.source
invalidate anonIn.a.bits.size
invalidate anonIn.a.bits.param
invalidate anonIn.a.bits.opcode
invalidate anonIn.a.valid
invalidate anonIn.a.ready
inst monitor of TLMonitor_2
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, anonIn.d.bits.data
connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied
connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink
connect monitor.io.in.d.bits.source, anonIn.d.bits.source
connect monitor.io.in.d.bits.size, anonIn.d.bits.size
connect monitor.io.in.d.bits.param, anonIn.d.bits.param
connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode
connect monitor.io.in.d.valid, anonIn.d.valid
connect monitor.io.in.d.ready, anonIn.d.ready
connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, anonIn.a.bits.data
connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask
connect monitor.io.in.a.bits.user.amba_prot.fetch, anonIn.a.bits.user.amba_prot.fetch
connect monitor.io.in.a.bits.user.amba_prot.secure, anonIn.a.bits.user.amba_prot.secure
connect monitor.io.in.a.bits.user.amba_prot.privileged, anonIn.a.bits.user.amba_prot.privileged
connect monitor.io.in.a.bits.user.amba_prot.writealloc, anonIn.a.bits.user.amba_prot.writealloc
connect monitor.io.in.a.bits.user.amba_prot.readalloc, anonIn.a.bits.user.amba_prot.readalloc
connect monitor.io.in.a.bits.user.amba_prot.modifiable, anonIn.a.bits.user.amba_prot.modifiable
connect monitor.io.in.a.bits.user.amba_prot.bufferable, anonIn.a.bits.user.amba_prot.bufferable
connect monitor.io.in.a.bits.address, anonIn.a.bits.address
connect monitor.io.in.a.bits.source, anonIn.a.bits.source
connect monitor.io.in.a.bits.size, anonIn.a.bits.size
connect monitor.io.in.a.bits.param, anonIn.a.bits.param
connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode
connect monitor.io.in.a.valid, anonIn.a.valid
connect monitor.io.in.a.ready, anonIn.a.ready
wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonOut.d.bits.corrupt
invalidate anonOut.d.bits.data
invalidate anonOut.d.bits.denied
invalidate anonOut.d.bits.sink
invalidate anonOut.d.bits.source
invalidate anonOut.d.bits.size
invalidate anonOut.d.bits.param
invalidate anonOut.d.bits.opcode
invalidate anonOut.d.valid
invalidate anonOut.d.ready
invalidate anonOut.a.bits.corrupt
invalidate anonOut.a.bits.data
invalidate anonOut.a.bits.mask
invalidate anonOut.a.bits.address
invalidate anonOut.a.bits.source
invalidate anonOut.a.bits.size
invalidate anonOut.a.bits.param
invalidate anonOut.a.bits.opcode
invalidate anonOut.a.valid
invalidate anonOut.a.ready
wire x1_anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_anonOut.d.bits.corrupt
invalidate x1_anonOut.d.bits.data
invalidate x1_anonOut.d.bits.denied
invalidate x1_anonOut.d.bits.sink
invalidate x1_anonOut.d.bits.source
invalidate x1_anonOut.d.bits.size
invalidate x1_anonOut.d.bits.param
invalidate x1_anonOut.d.bits.opcode
invalidate x1_anonOut.d.valid
invalidate x1_anonOut.d.ready
invalidate x1_anonOut.a.bits.corrupt
invalidate x1_anonOut.a.bits.data
invalidate x1_anonOut.a.bits.mask
invalidate x1_anonOut.a.bits.address
invalidate x1_anonOut.a.bits.source
invalidate x1_anonOut.a.bits.size
invalidate x1_anonOut.a.bits.param
invalidate x1_anonOut.a.bits.opcode
invalidate x1_anonOut.a.valid
invalidate x1_anonOut.a.ready
wire x1_anonOut_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_anonOut_1.d.bits.corrupt
invalidate x1_anonOut_1.d.bits.data
invalidate x1_anonOut_1.d.bits.denied
invalidate x1_anonOut_1.d.bits.sink
invalidate x1_anonOut_1.d.bits.source
invalidate x1_anonOut_1.d.bits.size
invalidate x1_anonOut_1.d.bits.param
invalidate x1_anonOut_1.d.bits.opcode
invalidate x1_anonOut_1.d.valid
invalidate x1_anonOut_1.d.ready
invalidate x1_anonOut_1.a.bits.corrupt
invalidate x1_anonOut_1.a.bits.data
invalidate x1_anonOut_1.a.bits.mask
invalidate x1_anonOut_1.a.bits.user.amba_prot.fetch
invalidate x1_anonOut_1.a.bits.user.amba_prot.secure
invalidate x1_anonOut_1.a.bits.user.amba_prot.privileged
invalidate x1_anonOut_1.a.bits.user.amba_prot.writealloc
invalidate x1_anonOut_1.a.bits.user.amba_prot.readalloc
invalidate x1_anonOut_1.a.bits.user.amba_prot.modifiable
invalidate x1_anonOut_1.a.bits.user.amba_prot.bufferable
invalidate x1_anonOut_1.a.bits.address
invalidate x1_anonOut_1.a.bits.source
invalidate x1_anonOut_1.a.bits.size
invalidate x1_anonOut_1.a.bits.param
invalidate x1_anonOut_1.a.bits.opcode
invalidate x1_anonOut_1.a.valid
invalidate x1_anonOut_1.a.ready
connect auto.anon_out_0, anonOut
connect auto.anon_out_1, x1_anonOut
connect auto.anon_out_2, x1_anonOut_1
connect anonIn, auto.anon_in
wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[1]
invalidate in[0].a.bits.user.amba_prot.fetch
invalidate in[0].a.bits.user.amba_prot.secure
invalidate in[0].a.bits.user.amba_prot.privileged
invalidate in[0].a.bits.user.amba_prot.writealloc
invalidate in[0].a.bits.user.amba_prot.readalloc
invalidate in[0].a.bits.user.amba_prot.modifiable
invalidate in[0].a.bits.user.amba_prot.bufferable
connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt
connect in[0].a.bits.data, anonIn.a.bits.data
connect in[0].a.bits.mask, anonIn.a.bits.mask
connect in[0].a.bits.user.amba_prot.fetch, anonIn.a.bits.user.amba_prot.fetch
connect in[0].a.bits.user.amba_prot.secure, anonIn.a.bits.user.amba_prot.secure
connect in[0].a.bits.user.amba_prot.privileged, anonIn.a.bits.user.amba_prot.privileged
connect in[0].a.bits.user.amba_prot.writealloc, anonIn.a.bits.user.amba_prot.writealloc
connect in[0].a.bits.user.amba_prot.readalloc, anonIn.a.bits.user.amba_prot.readalloc
connect in[0].a.bits.user.amba_prot.modifiable, anonIn.a.bits.user.amba_prot.modifiable
connect in[0].a.bits.user.amba_prot.bufferable, anonIn.a.bits.user.amba_prot.bufferable
connect in[0].a.bits.address, anonIn.a.bits.address
connect in[0].a.bits.source, anonIn.a.bits.source
connect in[0].a.bits.size, anonIn.a.bits.size
connect in[0].a.bits.param, anonIn.a.bits.param
connect in[0].a.bits.opcode, anonIn.a.bits.opcode
connect in[0].a.valid, anonIn.a.valid
connect anonIn.a.ready, in[0].a.ready
node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0))
connect in[0].a.bits.source, _in_0_a_bits_source_T
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<29>(0h0)
connect _WIRE.bits.source, UInt<7>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
invalidate _WIRE_1.bits.corrupt
invalidate _WIRE_1.bits.data
invalidate _WIRE_1.bits.mask
invalidate _WIRE_1.bits.address
invalidate _WIRE_1.bits.source
invalidate _WIRE_1.bits.size
invalidate _WIRE_1.bits.param
invalidate _WIRE_1.bits.opcode
invalidate _WIRE_1.valid
invalidate _WIRE_1.ready
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.mask, UInt<8>(0h0)
connect _WIRE_2.bits.address, UInt<29>(0h0)
connect _WIRE_2.bits.source, UInt<7>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<2>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
invalidate _WIRE_3.bits.corrupt
invalidate _WIRE_3.bits.data
invalidate _WIRE_3.bits.mask
invalidate _WIRE_3.bits.address
invalidate _WIRE_3.bits.source
invalidate _WIRE_3.bits.size
invalidate _WIRE_3.bits.param
invalidate _WIRE_3.bits.opcode
invalidate _WIRE_3.valid
invalidate _WIRE_3.ready
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<29>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.valid, UInt<1>(0h0)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_8.bits.address, UInt<29>(0h0)
connect _WIRE_8.bits.source, UInt<7>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
invalidate _WIRE_9.bits.corrupt
invalidate _WIRE_9.bits.data
invalidate _WIRE_9.bits.user.amba_prot.fetch
invalidate _WIRE_9.bits.user.amba_prot.secure
invalidate _WIRE_9.bits.user.amba_prot.privileged
invalidate _WIRE_9.bits.user.amba_prot.writealloc
invalidate _WIRE_9.bits.user.amba_prot.readalloc
invalidate _WIRE_9.bits.user.amba_prot.modifiable
invalidate _WIRE_9.bits.user.amba_prot.bufferable
invalidate _WIRE_9.bits.address
invalidate _WIRE_9.bits.source
invalidate _WIRE_9.bits.size
invalidate _WIRE_9.bits.param
invalidate _WIRE_9.bits.opcode
invalidate _WIRE_9.valid
invalidate _WIRE_9.ready
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_10.bits.address, UInt<29>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
invalidate _WIRE_11.bits.corrupt
invalidate _WIRE_11.bits.data
invalidate _WIRE_11.bits.user.amba_prot.fetch
invalidate _WIRE_11.bits.user.amba_prot.secure
invalidate _WIRE_11.bits.user.amba_prot.privileged
invalidate _WIRE_11.bits.user.amba_prot.writealloc
invalidate _WIRE_11.bits.user.amba_prot.readalloc
invalidate _WIRE_11.bits.user.amba_prot.modifiable
invalidate _WIRE_11.bits.user.amba_prot.bufferable
invalidate _WIRE_11.bits.address
invalidate _WIRE_11.bits.source
invalidate _WIRE_11.bits.size
invalidate _WIRE_11.bits.param
invalidate _WIRE_11.bits.opcode
invalidate _WIRE_11.valid
invalidate _WIRE_11.ready
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_12.bits.address, UInt<29>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
connect _WIRE_13.valid, UInt<1>(0h0)
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_14.bits.address, UInt<29>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
connect _WIRE_15.ready, UInt<1>(0h1)
connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt
connect anonIn.d.bits.data, in[0].d.bits.data
connect anonIn.d.bits.denied, in[0].d.bits.denied
connect anonIn.d.bits.sink, in[0].d.bits.sink
connect anonIn.d.bits.source, in[0].d.bits.source
connect anonIn.d.bits.size, in[0].d.bits.size
connect anonIn.d.bits.param, in[0].d.bits.param
connect anonIn.d.bits.opcode, in[0].d.bits.opcode
connect anonIn.d.valid, in[0].d.valid
connect in[0].d.ready, anonIn.d.ready
node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 6, 0)
connect anonIn.d.bits.source, _anonIn_d_bits_source_T
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_16.bits.sink, UInt<1>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
invalidate _WIRE_17.bits.sink
invalidate _WIRE_17.valid
invalidate _WIRE_17.ready
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_18.bits.sink, UInt<1>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
invalidate _WIRE_19.bits.sink
invalidate _WIRE_19.valid
invalidate _WIRE_19.ready
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_20.bits.sink, UInt<1>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
connect _WIRE_21.valid, UInt<1>(0h0)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_22.bits.sink, UInt<1>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
connect _WIRE_23.ready, UInt<1>(0h1)
wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[3]
invalidate out[0].a.bits.user.amba_prot.fetch
invalidate out[0].a.bits.user.amba_prot.secure
invalidate out[0].a.bits.user.amba_prot.privileged
invalidate out[0].a.bits.user.amba_prot.writealloc
invalidate out[0].a.bits.user.amba_prot.readalloc
invalidate out[0].a.bits.user.amba_prot.modifiable
invalidate out[0].a.bits.user.amba_prot.bufferable
connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt
connect anonOut.a.bits.data, out[0].a.bits.data
connect anonOut.a.bits.mask, out[0].a.bits.mask
connect anonOut.a.bits.address, out[0].a.bits.address
connect anonOut.a.bits.source, out[0].a.bits.source
connect anonOut.a.bits.size, out[0].a.bits.size
connect anonOut.a.bits.param, out[0].a.bits.param
connect anonOut.a.bits.opcode, out[0].a.bits.opcode
connect anonOut.a.valid, out[0].a.valid
connect out[0].a.ready, anonOut.a.ready
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.mask, UInt<8>(0h0)
connect _WIRE_24.bits.address, UInt<29>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<2>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
invalidate _WIRE_25.bits.corrupt
invalidate _WIRE_25.bits.data
invalidate _WIRE_25.bits.mask
invalidate _WIRE_25.bits.address
invalidate _WIRE_25.bits.source
invalidate _WIRE_25.bits.size
invalidate _WIRE_25.bits.param
invalidate _WIRE_25.bits.opcode
invalidate _WIRE_25.valid
invalidate _WIRE_25.ready
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.mask, UInt<8>(0h0)
connect _WIRE_26.bits.address, UInt<13>(0h0)
connect _WIRE_26.bits.source, UInt<7>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<2>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
invalidate _WIRE_27.bits.corrupt
invalidate _WIRE_27.bits.data
invalidate _WIRE_27.bits.mask
invalidate _WIRE_27.bits.address
invalidate _WIRE_27.bits.source
invalidate _WIRE_27.bits.size
invalidate _WIRE_27.bits.param
invalidate _WIRE_27.bits.opcode
invalidate _WIRE_27.valid
invalidate _WIRE_27.ready
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.mask, UInt<8>(0h0)
connect _WIRE_28.bits.address, UInt<29>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<2>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
connect _WIRE_29.valid, UInt<1>(0h0)
wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_30.bits.corrupt, UInt<1>(0h0)
connect _WIRE_30.bits.data, UInt<64>(0h0)
connect _WIRE_30.bits.mask, UInt<8>(0h0)
connect _WIRE_30.bits.address, UInt<13>(0h0)
connect _WIRE_30.bits.source, UInt<7>(0h0)
connect _WIRE_30.bits.size, UInt<3>(0h0)
connect _WIRE_30.bits.param, UInt<2>(0h0)
connect _WIRE_30.bits.opcode, UInt<3>(0h0)
connect _WIRE_30.valid, UInt<1>(0h0)
connect _WIRE_30.ready, UInt<1>(0h0)
wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_31.bits, _WIRE_30.bits
connect _WIRE_31.valid, _WIRE_30.valid
connect _WIRE_31.ready, _WIRE_30.ready
connect _WIRE_31.ready, UInt<1>(0h1)
wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_32.bits.corrupt, UInt<1>(0h0)
connect _WIRE_32.bits.data, UInt<64>(0h0)
connect _WIRE_32.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_32.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_32.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_32.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_32.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_32.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_32.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_32.bits.address, UInt<29>(0h0)
connect _WIRE_32.bits.source, UInt<7>(0h0)
connect _WIRE_32.bits.size, UInt<3>(0h0)
connect _WIRE_32.bits.param, UInt<3>(0h0)
connect _WIRE_32.bits.opcode, UInt<3>(0h0)
connect _WIRE_32.valid, UInt<1>(0h0)
connect _WIRE_32.ready, UInt<1>(0h0)
wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_33.bits, _WIRE_32.bits
connect _WIRE_33.valid, _WIRE_32.valid
connect _WIRE_33.ready, _WIRE_32.ready
invalidate _WIRE_33.bits.corrupt
invalidate _WIRE_33.bits.data
invalidate _WIRE_33.bits.user.amba_prot.fetch
invalidate _WIRE_33.bits.user.amba_prot.secure
invalidate _WIRE_33.bits.user.amba_prot.privileged
invalidate _WIRE_33.bits.user.amba_prot.writealloc
invalidate _WIRE_33.bits.user.amba_prot.readalloc
invalidate _WIRE_33.bits.user.amba_prot.modifiable
invalidate _WIRE_33.bits.user.amba_prot.bufferable
invalidate _WIRE_33.bits.address
invalidate _WIRE_33.bits.source
invalidate _WIRE_33.bits.size
invalidate _WIRE_33.bits.param
invalidate _WIRE_33.bits.opcode
invalidate _WIRE_33.valid
invalidate _WIRE_33.ready
wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_34.bits.corrupt, UInt<1>(0h0)
connect _WIRE_34.bits.data, UInt<64>(0h0)
connect _WIRE_34.bits.address, UInt<13>(0h0)
connect _WIRE_34.bits.source, UInt<7>(0h0)
connect _WIRE_34.bits.size, UInt<3>(0h0)
connect _WIRE_34.bits.param, UInt<3>(0h0)
connect _WIRE_34.bits.opcode, UInt<3>(0h0)
connect _WIRE_34.valid, UInt<1>(0h0)
connect _WIRE_34.ready, UInt<1>(0h0)
wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_35.bits, _WIRE_34.bits
connect _WIRE_35.valid, _WIRE_34.valid
connect _WIRE_35.ready, _WIRE_34.ready
invalidate _WIRE_35.bits.corrupt
invalidate _WIRE_35.bits.data
invalidate _WIRE_35.bits.address
invalidate _WIRE_35.bits.source
invalidate _WIRE_35.bits.size
invalidate _WIRE_35.bits.param
invalidate _WIRE_35.bits.opcode
invalidate _WIRE_35.valid
invalidate _WIRE_35.ready
wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_36.bits.corrupt, UInt<1>(0h0)
connect _WIRE_36.bits.data, UInt<64>(0h0)
connect _WIRE_36.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_36.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_36.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_36.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_36.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_36.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_36.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_36.bits.address, UInt<29>(0h0)
connect _WIRE_36.bits.source, UInt<7>(0h0)
connect _WIRE_36.bits.size, UInt<3>(0h0)
connect _WIRE_36.bits.param, UInt<3>(0h0)
connect _WIRE_36.bits.opcode, UInt<3>(0h0)
connect _WIRE_36.valid, UInt<1>(0h0)
connect _WIRE_36.ready, UInt<1>(0h0)
wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_37.bits, _WIRE_36.bits
connect _WIRE_37.valid, _WIRE_36.valid
connect _WIRE_37.ready, _WIRE_36.ready
connect _WIRE_37.ready, UInt<1>(0h1)
wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_38.bits.corrupt, UInt<1>(0h0)
connect _WIRE_38.bits.data, UInt<64>(0h0)
connect _WIRE_38.bits.address, UInt<13>(0h0)
connect _WIRE_38.bits.source, UInt<7>(0h0)
connect _WIRE_38.bits.size, UInt<3>(0h0)
connect _WIRE_38.bits.param, UInt<3>(0h0)
connect _WIRE_38.bits.opcode, UInt<3>(0h0)
connect _WIRE_38.valid, UInt<1>(0h0)
connect _WIRE_38.ready, UInt<1>(0h0)
wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_39.bits, _WIRE_38.bits
connect _WIRE_39.valid, _WIRE_38.valid
connect _WIRE_39.ready, _WIRE_38.ready
connect _WIRE_39.valid, UInt<1>(0h0)
connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt
connect out[0].d.bits.data, anonOut.d.bits.data
connect out[0].d.bits.denied, anonOut.d.bits.denied
connect out[0].d.bits.sink, anonOut.d.bits.sink
connect out[0].d.bits.source, anonOut.d.bits.source
connect out[0].d.bits.size, anonOut.d.bits.size
connect out[0].d.bits.param, anonOut.d.bits.param
connect out[0].d.bits.opcode, anonOut.d.bits.opcode
connect out[0].d.valid, anonOut.d.valid
connect anonOut.d.ready, out[0].d.ready
node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0))
connect out[0].d.bits.sink, _out_0_d_bits_sink_T
wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_40.bits.sink, UInt<1>(0h0)
connect _WIRE_40.valid, UInt<1>(0h0)
connect _WIRE_40.ready, UInt<1>(0h0)
wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_41.bits, _WIRE_40.bits
connect _WIRE_41.valid, _WIRE_40.valid
connect _WIRE_41.ready, _WIRE_40.ready
invalidate _WIRE_41.bits.sink
invalidate _WIRE_41.valid
invalidate _WIRE_41.ready
wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_42.bits.sink, UInt<1>(0h0)
connect _WIRE_42.valid, UInt<1>(0h0)
connect _WIRE_42.ready, UInt<1>(0h0)
wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_43.bits, _WIRE_42.bits
connect _WIRE_43.valid, _WIRE_42.valid
connect _WIRE_43.ready, _WIRE_42.ready
invalidate _WIRE_43.bits.sink
invalidate _WIRE_43.valid
invalidate _WIRE_43.ready
wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_44.bits.sink, UInt<1>(0h0)
connect _WIRE_44.valid, UInt<1>(0h0)
connect _WIRE_44.ready, UInt<1>(0h0)
wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_45.bits, _WIRE_44.bits
connect _WIRE_45.valid, _WIRE_44.valid
connect _WIRE_45.ready, _WIRE_44.ready
connect _WIRE_45.ready, UInt<1>(0h1)
wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_46.bits.sink, UInt<1>(0h0)
connect _WIRE_46.valid, UInt<1>(0h0)
connect _WIRE_46.ready, UInt<1>(0h0)
wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_47.bits, _WIRE_46.bits
connect _WIRE_47.valid, _WIRE_46.valid
connect _WIRE_47.ready, _WIRE_46.ready
connect _WIRE_47.valid, UInt<1>(0h0)
invalidate out[1].a.bits.user.amba_prot.fetch
invalidate out[1].a.bits.user.amba_prot.secure
invalidate out[1].a.bits.user.amba_prot.privileged
invalidate out[1].a.bits.user.amba_prot.writealloc
invalidate out[1].a.bits.user.amba_prot.readalloc
invalidate out[1].a.bits.user.amba_prot.modifiable
invalidate out[1].a.bits.user.amba_prot.bufferable
connect x1_anonOut.a.bits.corrupt, out[1].a.bits.corrupt
connect x1_anonOut.a.bits.data, out[1].a.bits.data
connect x1_anonOut.a.bits.mask, out[1].a.bits.mask
connect x1_anonOut.a.bits.address, out[1].a.bits.address
connect x1_anonOut.a.bits.source, out[1].a.bits.source
connect x1_anonOut.a.bits.size, out[1].a.bits.size
connect x1_anonOut.a.bits.param, out[1].a.bits.param
connect x1_anonOut.a.bits.opcode, out[1].a.bits.opcode
connect x1_anonOut.a.valid, out[1].a.valid
connect out[1].a.ready, x1_anonOut.a.ready
wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_48.bits.corrupt, UInt<1>(0h0)
connect _WIRE_48.bits.data, UInt<64>(0h0)
connect _WIRE_48.bits.mask, UInt<8>(0h0)
connect _WIRE_48.bits.address, UInt<29>(0h0)
connect _WIRE_48.bits.source, UInt<7>(0h0)
connect _WIRE_48.bits.size, UInt<3>(0h0)
connect _WIRE_48.bits.param, UInt<2>(0h0)
connect _WIRE_48.bits.opcode, UInt<3>(0h0)
connect _WIRE_48.valid, UInt<1>(0h0)
connect _WIRE_48.ready, UInt<1>(0h0)
wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_49.bits, _WIRE_48.bits
connect _WIRE_49.valid, _WIRE_48.valid
connect _WIRE_49.ready, _WIRE_48.ready
invalidate _WIRE_49.bits.corrupt
invalidate _WIRE_49.bits.data
invalidate _WIRE_49.bits.mask
invalidate _WIRE_49.bits.address
invalidate _WIRE_49.bits.source
invalidate _WIRE_49.bits.size
invalidate _WIRE_49.bits.param
invalidate _WIRE_49.bits.opcode
invalidate _WIRE_49.valid
invalidate _WIRE_49.ready
wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_50.bits.corrupt, UInt<1>(0h0)
connect _WIRE_50.bits.data, UInt<64>(0h0)
connect _WIRE_50.bits.mask, UInt<8>(0h0)
connect _WIRE_50.bits.address, UInt<29>(0h0)
connect _WIRE_50.bits.source, UInt<7>(0h0)
connect _WIRE_50.bits.size, UInt<3>(0h0)
connect _WIRE_50.bits.param, UInt<2>(0h0)
connect _WIRE_50.bits.opcode, UInt<3>(0h0)
connect _WIRE_50.valid, UInt<1>(0h0)
connect _WIRE_50.ready, UInt<1>(0h0)
wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_51.bits, _WIRE_50.bits
connect _WIRE_51.valid, _WIRE_50.valid
connect _WIRE_51.ready, _WIRE_50.ready
invalidate _WIRE_51.bits.corrupt
invalidate _WIRE_51.bits.data
invalidate _WIRE_51.bits.mask
invalidate _WIRE_51.bits.address
invalidate _WIRE_51.bits.source
invalidate _WIRE_51.bits.size
invalidate _WIRE_51.bits.param
invalidate _WIRE_51.bits.opcode
invalidate _WIRE_51.valid
invalidate _WIRE_51.ready
wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_52.bits.corrupt, UInt<1>(0h0)
connect _WIRE_52.bits.data, UInt<64>(0h0)
connect _WIRE_52.bits.mask, UInt<8>(0h0)
connect _WIRE_52.bits.address, UInt<29>(0h0)
connect _WIRE_52.bits.source, UInt<7>(0h0)
connect _WIRE_52.bits.size, UInt<3>(0h0)
connect _WIRE_52.bits.param, UInt<2>(0h0)
connect _WIRE_52.bits.opcode, UInt<3>(0h0)
connect _WIRE_52.valid, UInt<1>(0h0)
connect _WIRE_52.ready, UInt<1>(0h0)
wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_53.bits, _WIRE_52.bits
connect _WIRE_53.valid, _WIRE_52.valid
connect _WIRE_53.ready, _WIRE_52.ready
connect _WIRE_53.valid, UInt<1>(0h0)
wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_54.bits.corrupt, UInt<1>(0h0)
connect _WIRE_54.bits.data, UInt<64>(0h0)
connect _WIRE_54.bits.mask, UInt<8>(0h0)
connect _WIRE_54.bits.address, UInt<29>(0h0)
connect _WIRE_54.bits.source, UInt<7>(0h0)
connect _WIRE_54.bits.size, UInt<3>(0h0)
connect _WIRE_54.bits.param, UInt<2>(0h0)
connect _WIRE_54.bits.opcode, UInt<3>(0h0)
connect _WIRE_54.valid, UInt<1>(0h0)
connect _WIRE_54.ready, UInt<1>(0h0)
wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_55.bits, _WIRE_54.bits
connect _WIRE_55.valid, _WIRE_54.valid
connect _WIRE_55.ready, _WIRE_54.ready
connect _WIRE_55.ready, UInt<1>(0h1)
wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_56.bits.corrupt, UInt<1>(0h0)
connect _WIRE_56.bits.data, UInt<64>(0h0)
connect _WIRE_56.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_56.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_56.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_56.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_56.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_56.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_56.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_56.bits.address, UInt<29>(0h0)
connect _WIRE_56.bits.source, UInt<7>(0h0)
connect _WIRE_56.bits.size, UInt<3>(0h0)
connect _WIRE_56.bits.param, UInt<3>(0h0)
connect _WIRE_56.bits.opcode, UInt<3>(0h0)
connect _WIRE_56.valid, UInt<1>(0h0)
connect _WIRE_56.ready, UInt<1>(0h0)
wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_57.bits, _WIRE_56.bits
connect _WIRE_57.valid, _WIRE_56.valid
connect _WIRE_57.ready, _WIRE_56.ready
invalidate _WIRE_57.bits.corrupt
invalidate _WIRE_57.bits.data
invalidate _WIRE_57.bits.user.amba_prot.fetch
invalidate _WIRE_57.bits.user.amba_prot.secure
invalidate _WIRE_57.bits.user.amba_prot.privileged
invalidate _WIRE_57.bits.user.amba_prot.writealloc
invalidate _WIRE_57.bits.user.amba_prot.readalloc
invalidate _WIRE_57.bits.user.amba_prot.modifiable
invalidate _WIRE_57.bits.user.amba_prot.bufferable
invalidate _WIRE_57.bits.address
invalidate _WIRE_57.bits.source
invalidate _WIRE_57.bits.size
invalidate _WIRE_57.bits.param
invalidate _WIRE_57.bits.opcode
invalidate _WIRE_57.valid
invalidate _WIRE_57.ready
wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_58.bits.corrupt, UInt<1>(0h0)
connect _WIRE_58.bits.data, UInt<64>(0h0)
connect _WIRE_58.bits.address, UInt<29>(0h0)
connect _WIRE_58.bits.source, UInt<7>(0h0)
connect _WIRE_58.bits.size, UInt<3>(0h0)
connect _WIRE_58.bits.param, UInt<3>(0h0)
connect _WIRE_58.bits.opcode, UInt<3>(0h0)
connect _WIRE_58.valid, UInt<1>(0h0)
connect _WIRE_58.ready, UInt<1>(0h0)
wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_59.bits, _WIRE_58.bits
connect _WIRE_59.valid, _WIRE_58.valid
connect _WIRE_59.ready, _WIRE_58.ready
invalidate _WIRE_59.bits.corrupt
invalidate _WIRE_59.bits.data
invalidate _WIRE_59.bits.address
invalidate _WIRE_59.bits.source
invalidate _WIRE_59.bits.size
invalidate _WIRE_59.bits.param
invalidate _WIRE_59.bits.opcode
invalidate _WIRE_59.valid
invalidate _WIRE_59.ready
wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_60.bits.corrupt, UInt<1>(0h0)
connect _WIRE_60.bits.data, UInt<64>(0h0)
connect _WIRE_60.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_60.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_60.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_60.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_60.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_60.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_60.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_60.bits.address, UInt<29>(0h0)
connect _WIRE_60.bits.source, UInt<7>(0h0)
connect _WIRE_60.bits.size, UInt<3>(0h0)
connect _WIRE_60.bits.param, UInt<3>(0h0)
connect _WIRE_60.bits.opcode, UInt<3>(0h0)
connect _WIRE_60.valid, UInt<1>(0h0)
connect _WIRE_60.ready, UInt<1>(0h0)
wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_61.bits, _WIRE_60.bits
connect _WIRE_61.valid, _WIRE_60.valid
connect _WIRE_61.ready, _WIRE_60.ready
connect _WIRE_61.ready, UInt<1>(0h1)
wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_62.bits.corrupt, UInt<1>(0h0)
connect _WIRE_62.bits.data, UInt<64>(0h0)
connect _WIRE_62.bits.address, UInt<29>(0h0)
connect _WIRE_62.bits.source, UInt<7>(0h0)
connect _WIRE_62.bits.size, UInt<3>(0h0)
connect _WIRE_62.bits.param, UInt<3>(0h0)
connect _WIRE_62.bits.opcode, UInt<3>(0h0)
connect _WIRE_62.valid, UInt<1>(0h0)
connect _WIRE_62.ready, UInt<1>(0h0)
wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_63.bits, _WIRE_62.bits
connect _WIRE_63.valid, _WIRE_62.valid
connect _WIRE_63.ready, _WIRE_62.ready
connect _WIRE_63.valid, UInt<1>(0h0)
connect out[1].d.bits.corrupt, x1_anonOut.d.bits.corrupt
connect out[1].d.bits.data, x1_anonOut.d.bits.data
connect out[1].d.bits.denied, x1_anonOut.d.bits.denied
connect out[1].d.bits.sink, x1_anonOut.d.bits.sink
connect out[1].d.bits.source, x1_anonOut.d.bits.source
connect out[1].d.bits.size, x1_anonOut.d.bits.size
connect out[1].d.bits.param, x1_anonOut.d.bits.param
connect out[1].d.bits.opcode, x1_anonOut.d.bits.opcode
connect out[1].d.valid, x1_anonOut.d.valid
connect x1_anonOut.d.ready, out[1].d.ready
node _out_1_d_bits_sink_T = or(x1_anonOut.d.bits.sink, UInt<1>(0h0))
connect out[1].d.bits.sink, _out_1_d_bits_sink_T
wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_64.bits.sink, UInt<1>(0h0)
connect _WIRE_64.valid, UInt<1>(0h0)
connect _WIRE_64.ready, UInt<1>(0h0)
wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_65.bits, _WIRE_64.bits
connect _WIRE_65.valid, _WIRE_64.valid
connect _WIRE_65.ready, _WIRE_64.ready
invalidate _WIRE_65.bits.sink
invalidate _WIRE_65.valid
invalidate _WIRE_65.ready
wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_66.bits.sink, UInt<1>(0h0)
connect _WIRE_66.valid, UInt<1>(0h0)
connect _WIRE_66.ready, UInt<1>(0h0)
wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_67.bits, _WIRE_66.bits
connect _WIRE_67.valid, _WIRE_66.valid
connect _WIRE_67.ready, _WIRE_66.ready
invalidate _WIRE_67.bits.sink
invalidate _WIRE_67.valid
invalidate _WIRE_67.ready
wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_68.bits.sink, UInt<1>(0h0)
connect _WIRE_68.valid, UInt<1>(0h0)
connect _WIRE_68.ready, UInt<1>(0h0)
wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_69.bits, _WIRE_68.bits
connect _WIRE_69.valid, _WIRE_68.valid
connect _WIRE_69.ready, _WIRE_68.ready
connect _WIRE_69.ready, UInt<1>(0h1)
wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_70.bits.sink, UInt<1>(0h0)
connect _WIRE_70.valid, UInt<1>(0h0)
connect _WIRE_70.ready, UInt<1>(0h0)
wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_71.bits, _WIRE_70.bits
connect _WIRE_71.valid, _WIRE_70.valid
connect _WIRE_71.ready, _WIRE_70.ready
connect _WIRE_71.valid, UInt<1>(0h0)
invalidate out[2].a.bits.user.amba_prot.fetch
invalidate out[2].a.bits.user.amba_prot.secure
invalidate out[2].a.bits.user.amba_prot.privileged
invalidate out[2].a.bits.user.amba_prot.writealloc
invalidate out[2].a.bits.user.amba_prot.readalloc
invalidate out[2].a.bits.user.amba_prot.modifiable
invalidate out[2].a.bits.user.amba_prot.bufferable
connect x1_anonOut_1.a.bits.corrupt, out[2].a.bits.corrupt
connect x1_anonOut_1.a.bits.data, out[2].a.bits.data
connect x1_anonOut_1.a.bits.mask, out[2].a.bits.mask
connect x1_anonOut_1.a.bits.user.amba_prot.fetch, out[2].a.bits.user.amba_prot.fetch
connect x1_anonOut_1.a.bits.user.amba_prot.secure, out[2].a.bits.user.amba_prot.secure
connect x1_anonOut_1.a.bits.user.amba_prot.privileged, out[2].a.bits.user.amba_prot.privileged
connect x1_anonOut_1.a.bits.user.amba_prot.writealloc, out[2].a.bits.user.amba_prot.writealloc
connect x1_anonOut_1.a.bits.user.amba_prot.readalloc, out[2].a.bits.user.amba_prot.readalloc
connect x1_anonOut_1.a.bits.user.amba_prot.modifiable, out[2].a.bits.user.amba_prot.modifiable
connect x1_anonOut_1.a.bits.user.amba_prot.bufferable, out[2].a.bits.user.amba_prot.bufferable
connect x1_anonOut_1.a.bits.address, out[2].a.bits.address
connect x1_anonOut_1.a.bits.source, out[2].a.bits.source
connect x1_anonOut_1.a.bits.size, out[2].a.bits.size
connect x1_anonOut_1.a.bits.param, out[2].a.bits.param
connect x1_anonOut_1.a.bits.opcode, out[2].a.bits.opcode
connect x1_anonOut_1.a.valid, out[2].a.valid
connect out[2].a.ready, x1_anonOut_1.a.ready
wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_72.bits.corrupt, UInt<1>(0h0)
connect _WIRE_72.bits.data, UInt<64>(0h0)
connect _WIRE_72.bits.mask, UInt<8>(0h0)
connect _WIRE_72.bits.address, UInt<29>(0h0)
connect _WIRE_72.bits.source, UInt<7>(0h0)
connect _WIRE_72.bits.size, UInt<3>(0h0)
connect _WIRE_72.bits.param, UInt<2>(0h0)
connect _WIRE_72.bits.opcode, UInt<3>(0h0)
connect _WIRE_72.valid, UInt<1>(0h0)
connect _WIRE_72.ready, UInt<1>(0h0)
wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_73.bits, _WIRE_72.bits
connect _WIRE_73.valid, _WIRE_72.valid
connect _WIRE_73.ready, _WIRE_72.ready
invalidate _WIRE_73.bits.corrupt
invalidate _WIRE_73.bits.data
invalidate _WIRE_73.bits.mask
invalidate _WIRE_73.bits.address
invalidate _WIRE_73.bits.source
invalidate _WIRE_73.bits.size
invalidate _WIRE_73.bits.param
invalidate _WIRE_73.bits.opcode
invalidate _WIRE_73.valid
invalidate _WIRE_73.ready
wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<15>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_74.bits.corrupt, UInt<1>(0h0)
connect _WIRE_74.bits.data, UInt<64>(0h0)
connect _WIRE_74.bits.mask, UInt<8>(0h0)
connect _WIRE_74.bits.address, UInt<15>(0h0)
connect _WIRE_74.bits.source, UInt<7>(0h0)
connect _WIRE_74.bits.size, UInt<3>(0h0)
connect _WIRE_74.bits.param, UInt<2>(0h0)
connect _WIRE_74.bits.opcode, UInt<3>(0h0)
connect _WIRE_74.valid, UInt<1>(0h0)
connect _WIRE_74.ready, UInt<1>(0h0)
wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<15>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_75.bits, _WIRE_74.bits
connect _WIRE_75.valid, _WIRE_74.valid
connect _WIRE_75.ready, _WIRE_74.ready
invalidate _WIRE_75.bits.corrupt
invalidate _WIRE_75.bits.data
invalidate _WIRE_75.bits.mask
invalidate _WIRE_75.bits.address
invalidate _WIRE_75.bits.source
invalidate _WIRE_75.bits.size
invalidate _WIRE_75.bits.param
invalidate _WIRE_75.bits.opcode
invalidate _WIRE_75.valid
invalidate _WIRE_75.ready
wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_76.bits.corrupt, UInt<1>(0h0)
connect _WIRE_76.bits.data, UInt<64>(0h0)
connect _WIRE_76.bits.mask, UInt<8>(0h0)
connect _WIRE_76.bits.address, UInt<29>(0h0)
connect _WIRE_76.bits.source, UInt<7>(0h0)
connect _WIRE_76.bits.size, UInt<3>(0h0)
connect _WIRE_76.bits.param, UInt<2>(0h0)
connect _WIRE_76.bits.opcode, UInt<3>(0h0)
connect _WIRE_76.valid, UInt<1>(0h0)
connect _WIRE_76.ready, UInt<1>(0h0)
wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_77.bits, _WIRE_76.bits
connect _WIRE_77.valid, _WIRE_76.valid
connect _WIRE_77.ready, _WIRE_76.ready
connect _WIRE_77.valid, UInt<1>(0h0)
wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<15>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_78.bits.corrupt, UInt<1>(0h0)
connect _WIRE_78.bits.data, UInt<64>(0h0)
connect _WIRE_78.bits.mask, UInt<8>(0h0)
connect _WIRE_78.bits.address, UInt<15>(0h0)
connect _WIRE_78.bits.source, UInt<7>(0h0)
connect _WIRE_78.bits.size, UInt<3>(0h0)
connect _WIRE_78.bits.param, UInt<2>(0h0)
connect _WIRE_78.bits.opcode, UInt<3>(0h0)
connect _WIRE_78.valid, UInt<1>(0h0)
connect _WIRE_78.ready, UInt<1>(0h0)
wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<15>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_79.bits, _WIRE_78.bits
connect _WIRE_79.valid, _WIRE_78.valid
connect _WIRE_79.ready, _WIRE_78.ready
connect _WIRE_79.ready, UInt<1>(0h1)
wire _WIRE_80 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_80.bits.corrupt, UInt<1>(0h0)
connect _WIRE_80.bits.data, UInt<64>(0h0)
connect _WIRE_80.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_80.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_80.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_80.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_80.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_80.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_80.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_80.bits.address, UInt<29>(0h0)
connect _WIRE_80.bits.source, UInt<7>(0h0)
connect _WIRE_80.bits.size, UInt<3>(0h0)
connect _WIRE_80.bits.param, UInt<3>(0h0)
connect _WIRE_80.bits.opcode, UInt<3>(0h0)
connect _WIRE_80.valid, UInt<1>(0h0)
connect _WIRE_80.ready, UInt<1>(0h0)
wire _WIRE_81 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_81.bits, _WIRE_80.bits
connect _WIRE_81.valid, _WIRE_80.valid
connect _WIRE_81.ready, _WIRE_80.ready
invalidate _WIRE_81.bits.corrupt
invalidate _WIRE_81.bits.data
invalidate _WIRE_81.bits.user.amba_prot.fetch
invalidate _WIRE_81.bits.user.amba_prot.secure
invalidate _WIRE_81.bits.user.amba_prot.privileged
invalidate _WIRE_81.bits.user.amba_prot.writealloc
invalidate _WIRE_81.bits.user.amba_prot.readalloc
invalidate _WIRE_81.bits.user.amba_prot.modifiable
invalidate _WIRE_81.bits.user.amba_prot.bufferable
invalidate _WIRE_81.bits.address
invalidate _WIRE_81.bits.source
invalidate _WIRE_81.bits.size
invalidate _WIRE_81.bits.param
invalidate _WIRE_81.bits.opcode
invalidate _WIRE_81.valid
invalidate _WIRE_81.ready
wire _WIRE_82 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_82.bits.corrupt, UInt<1>(0h0)
connect _WIRE_82.bits.data, UInt<64>(0h0)
connect _WIRE_82.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_82.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_82.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_82.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_82.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_82.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_82.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_82.bits.address, UInt<15>(0h0)
connect _WIRE_82.bits.source, UInt<7>(0h0)
connect _WIRE_82.bits.size, UInt<3>(0h0)
connect _WIRE_82.bits.param, UInt<3>(0h0)
connect _WIRE_82.bits.opcode, UInt<3>(0h0)
connect _WIRE_82.valid, UInt<1>(0h0)
connect _WIRE_82.ready, UInt<1>(0h0)
wire _WIRE_83 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_83.bits, _WIRE_82.bits
connect _WIRE_83.valid, _WIRE_82.valid
connect _WIRE_83.ready, _WIRE_82.ready
invalidate _WIRE_83.bits.corrupt
invalidate _WIRE_83.bits.data
invalidate _WIRE_83.bits.user.amba_prot.fetch
invalidate _WIRE_83.bits.user.amba_prot.secure
invalidate _WIRE_83.bits.user.amba_prot.privileged
invalidate _WIRE_83.bits.user.amba_prot.writealloc
invalidate _WIRE_83.bits.user.amba_prot.readalloc
invalidate _WIRE_83.bits.user.amba_prot.modifiable
invalidate _WIRE_83.bits.user.amba_prot.bufferable
invalidate _WIRE_83.bits.address
invalidate _WIRE_83.bits.source
invalidate _WIRE_83.bits.size
invalidate _WIRE_83.bits.param
invalidate _WIRE_83.bits.opcode
invalidate _WIRE_83.valid
invalidate _WIRE_83.ready
wire _WIRE_84 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_84.bits.corrupt, UInt<1>(0h0)
connect _WIRE_84.bits.data, UInt<64>(0h0)
connect _WIRE_84.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_84.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_84.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_84.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_84.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_84.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_84.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_84.bits.address, UInt<29>(0h0)
connect _WIRE_84.bits.source, UInt<7>(0h0)
connect _WIRE_84.bits.size, UInt<3>(0h0)
connect _WIRE_84.bits.param, UInt<3>(0h0)
connect _WIRE_84.bits.opcode, UInt<3>(0h0)
connect _WIRE_84.valid, UInt<1>(0h0)
connect _WIRE_84.ready, UInt<1>(0h0)
wire _WIRE_85 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_85.bits, _WIRE_84.bits
connect _WIRE_85.valid, _WIRE_84.valid
connect _WIRE_85.ready, _WIRE_84.ready
connect _WIRE_85.ready, UInt<1>(0h1)
wire _WIRE_86 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_86.bits.corrupt, UInt<1>(0h0)
connect _WIRE_86.bits.data, UInt<64>(0h0)
connect _WIRE_86.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_86.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_86.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_86.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_86.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_86.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_86.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_86.bits.address, UInt<15>(0h0)
connect _WIRE_86.bits.source, UInt<7>(0h0)
connect _WIRE_86.bits.size, UInt<3>(0h0)
connect _WIRE_86.bits.param, UInt<3>(0h0)
connect _WIRE_86.bits.opcode, UInt<3>(0h0)
connect _WIRE_86.valid, UInt<1>(0h0)
connect _WIRE_86.ready, UInt<1>(0h0)
wire _WIRE_87 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_87.bits, _WIRE_86.bits
connect _WIRE_87.valid, _WIRE_86.valid
connect _WIRE_87.ready, _WIRE_86.ready
connect _WIRE_87.valid, UInt<1>(0h0)
connect out[2].d.bits.corrupt, x1_anonOut_1.d.bits.corrupt
connect out[2].d.bits.data, x1_anonOut_1.d.bits.data
connect out[2].d.bits.denied, x1_anonOut_1.d.bits.denied
connect out[2].d.bits.sink, x1_anonOut_1.d.bits.sink
connect out[2].d.bits.source, x1_anonOut_1.d.bits.source
connect out[2].d.bits.size, x1_anonOut_1.d.bits.size
connect out[2].d.bits.param, x1_anonOut_1.d.bits.param
connect out[2].d.bits.opcode, x1_anonOut_1.d.bits.opcode
connect out[2].d.valid, x1_anonOut_1.d.valid
connect x1_anonOut_1.d.ready, out[2].d.ready
node _out_2_d_bits_sink_T = or(x1_anonOut_1.d.bits.sink, UInt<1>(0h0))
connect out[2].d.bits.sink, _out_2_d_bits_sink_T
wire _WIRE_88 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_88.bits.sink, UInt<1>(0h0)
connect _WIRE_88.valid, UInt<1>(0h0)
connect _WIRE_88.ready, UInt<1>(0h0)
wire _WIRE_89 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_89.bits, _WIRE_88.bits
connect _WIRE_89.valid, _WIRE_88.valid
connect _WIRE_89.ready, _WIRE_88.ready
invalidate _WIRE_89.bits.sink
invalidate _WIRE_89.valid
invalidate _WIRE_89.ready
wire _WIRE_90 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_90.bits.sink, UInt<1>(0h0)
connect _WIRE_90.valid, UInt<1>(0h0)
connect _WIRE_90.ready, UInt<1>(0h0)
wire _WIRE_91 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_91.bits, _WIRE_90.bits
connect _WIRE_91.valid, _WIRE_90.valid
connect _WIRE_91.ready, _WIRE_90.ready
invalidate _WIRE_91.bits.sink
invalidate _WIRE_91.valid
invalidate _WIRE_91.ready
wire _WIRE_92 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_92.bits.sink, UInt<1>(0h0)
connect _WIRE_92.valid, UInt<1>(0h0)
connect _WIRE_92.ready, UInt<1>(0h0)
wire _WIRE_93 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_93.bits, _WIRE_92.bits
connect _WIRE_93.valid, _WIRE_92.valid
connect _WIRE_93.ready, _WIRE_92.ready
connect _WIRE_93.ready, UInt<1>(0h1)
wire _WIRE_94 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_94.bits.sink, UInt<1>(0h0)
connect _WIRE_94.valid, UInt<1>(0h0)
connect _WIRE_94.ready, UInt<1>(0h0)
wire _WIRE_95 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_95.bits, _WIRE_94.bits
connect _WIRE_95.valid, _WIRE_94.valid
connect _WIRE_95.ready, _WIRE_94.ready
connect _WIRE_95.valid, UInt<1>(0h0)
wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0)
connect _addressC_WIRE.bits.data, UInt<64>(0h0)
connect _addressC_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _addressC_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _addressC_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _addressC_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _addressC_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _addressC_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _addressC_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _addressC_WIRE.bits.address, UInt<29>(0h0)
connect _addressC_WIRE.bits.source, UInt<7>(0h0)
connect _addressC_WIRE.bits.size, UInt<3>(0h0)
connect _addressC_WIRE.bits.param, UInt<3>(0h0)
connect _addressC_WIRE.bits.opcode, UInt<3>(0h0)
connect _addressC_WIRE.valid, UInt<1>(0h0)
connect _addressC_WIRE.ready, UInt<1>(0h0)
wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE_1.bits, _addressC_WIRE.bits
connect _addressC_WIRE_1.valid, _addressC_WIRE.valid
connect _addressC_WIRE_1.ready, _addressC_WIRE.ready
node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_1 = cvt(_requestAIO_T)
node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<30>(0h10004000)))
node _requestAIO_T_3 = asSInt(_requestAIO_T_2)
node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0)))
node requestAIO_0_0 = or(UInt<1>(0h0), _requestAIO_T_4)
node _requestAIO_T_5 = xor(in[0].a.bits.address, UInt<29>(0h10000000))
node _requestAIO_T_6 = cvt(_requestAIO_T_5)
node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<30>(0h10004000)))
node _requestAIO_T_8 = asSInt(_requestAIO_T_7)
node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0)))
node requestAIO_0_1 = or(UInt<1>(0h0), _requestAIO_T_9)
node _requestAIO_T_10 = xor(in[0].a.bits.address, UInt<15>(0h4000))
node _requestAIO_T_11 = cvt(_requestAIO_T_10)
node _requestAIO_T_12 = and(_requestAIO_T_11, asSInt(UInt<30>(0h10004000)))
node _requestAIO_T_13 = asSInt(_requestAIO_T_12)
node _requestAIO_T_14 = eq(_requestAIO_T_13, asSInt(UInt<1>(0h0)))
node requestAIO_0_2 = or(UInt<1>(0h0), _requestAIO_T_14)
node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0))
node _requestCIO_T_1 = cvt(_requestCIO_T)
node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0)))
node _requestCIO_T_3 = asSInt(_requestCIO_T_2)
node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0)))
node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4)
node _requestCIO_T_5 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0))
node _requestCIO_T_6 = cvt(_requestCIO_T_5)
node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0)))
node _requestCIO_T_8 = asSInt(_requestCIO_T_7)
node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0)))
node requestCIO_0_1 = or(UInt<1>(0h1), _requestCIO_T_9)
node _requestCIO_T_10 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0))
node _requestCIO_T_11 = cvt(_requestCIO_T_10)
node _requestCIO_T_12 = and(_requestCIO_T_11, asSInt(UInt<1>(0h0)))
node _requestCIO_T_13 = asSInt(_requestCIO_T_12)
node _requestCIO_T_14 = eq(_requestCIO_T_13, asSInt(UInt<1>(0h0)))
node requestCIO_0_2 = or(UInt<1>(0h1), _requestCIO_T_14)
wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE.bits.data, UInt<64>(0h0)
connect _requestBOI_WIRE.bits.mask, UInt<8>(0h0)
connect _requestBOI_WIRE.bits.address, UInt<29>(0h0)
connect _requestBOI_WIRE.bits.source, UInt<7>(0h0)
connect _requestBOI_WIRE.bits.size, UInt<3>(0h0)
connect _requestBOI_WIRE.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE.valid, UInt<1>(0h0)
connect _requestBOI_WIRE.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits
connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid
connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready
node _requestBOI_uncommonBits_T = or(_requestBOI_WIRE_1.bits.source, UInt<7>(0h0))
node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 6, 0)
node _requestBOI_T = shr(_requestBOI_WIRE_1.bits.source, 7)
node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0))
node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits)
node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2)
node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<7>(0h7f))
node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4)
wire _requestBOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE_2.bits.data, UInt<64>(0h0)
connect _requestBOI_WIRE_2.bits.mask, UInt<8>(0h0)
connect _requestBOI_WIRE_2.bits.address, UInt<29>(0h0)
connect _requestBOI_WIRE_2.bits.source, UInt<7>(0h0)
connect _requestBOI_WIRE_2.bits.size, UInt<3>(0h0)
connect _requestBOI_WIRE_2.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE_2.valid, UInt<1>(0h0)
connect _requestBOI_WIRE_2.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_3.bits, _requestBOI_WIRE_2.bits
connect _requestBOI_WIRE_3.valid, _requestBOI_WIRE_2.valid
connect _requestBOI_WIRE_3.ready, _requestBOI_WIRE_2.ready
node _requestBOI_uncommonBits_T_1 = or(_requestBOI_WIRE_3.bits.source, UInt<7>(0h0))
node requestBOI_uncommonBits_1 = bits(_requestBOI_uncommonBits_T_1, 6, 0)
node _requestBOI_T_5 = shr(_requestBOI_WIRE_3.bits.source, 7)
node _requestBOI_T_6 = eq(_requestBOI_T_5, UInt<1>(0h0))
node _requestBOI_T_7 = leq(UInt<1>(0h0), requestBOI_uncommonBits_1)
node _requestBOI_T_8 = and(_requestBOI_T_6, _requestBOI_T_7)
node _requestBOI_T_9 = leq(requestBOI_uncommonBits_1, UInt<7>(0h7f))
node requestBOI_1_0 = and(_requestBOI_T_8, _requestBOI_T_9)
wire _requestBOI_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE_4.bits.data, UInt<64>(0h0)
connect _requestBOI_WIRE_4.bits.mask, UInt<8>(0h0)
connect _requestBOI_WIRE_4.bits.address, UInt<29>(0h0)
connect _requestBOI_WIRE_4.bits.source, UInt<7>(0h0)
connect _requestBOI_WIRE_4.bits.size, UInt<3>(0h0)
connect _requestBOI_WIRE_4.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE_4.valid, UInt<1>(0h0)
connect _requestBOI_WIRE_4.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_5.bits, _requestBOI_WIRE_4.bits
connect _requestBOI_WIRE_5.valid, _requestBOI_WIRE_4.valid
connect _requestBOI_WIRE_5.ready, _requestBOI_WIRE_4.ready
node _requestBOI_uncommonBits_T_2 = or(_requestBOI_WIRE_5.bits.source, UInt<7>(0h0))
node requestBOI_uncommonBits_2 = bits(_requestBOI_uncommonBits_T_2, 6, 0)
node _requestBOI_T_10 = shr(_requestBOI_WIRE_5.bits.source, 7)
node _requestBOI_T_11 = eq(_requestBOI_T_10, UInt<1>(0h0))
node _requestBOI_T_12 = leq(UInt<1>(0h0), requestBOI_uncommonBits_2)
node _requestBOI_T_13 = and(_requestBOI_T_11, _requestBOI_T_12)
node _requestBOI_T_14 = leq(requestBOI_uncommonBits_2, UInt<7>(0h7f))
node requestBOI_2_0 = and(_requestBOI_T_13, _requestBOI_T_14)
node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<7>(0h0))
node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 6, 0)
node _requestDOI_T = shr(out[0].d.bits.source, 7)
node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0))
node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits)
node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2)
node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<7>(0h7f))
node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4)
node _requestDOI_uncommonBits_T_1 = or(out[1].d.bits.source, UInt<7>(0h0))
node requestDOI_uncommonBits_1 = bits(_requestDOI_uncommonBits_T_1, 6, 0)
node _requestDOI_T_5 = shr(out[1].d.bits.source, 7)
node _requestDOI_T_6 = eq(_requestDOI_T_5, UInt<1>(0h0))
node _requestDOI_T_7 = leq(UInt<1>(0h0), requestDOI_uncommonBits_1)
node _requestDOI_T_8 = and(_requestDOI_T_6, _requestDOI_T_7)
node _requestDOI_T_9 = leq(requestDOI_uncommonBits_1, UInt<7>(0h7f))
node requestDOI_1_0 = and(_requestDOI_T_8, _requestDOI_T_9)
node _requestDOI_uncommonBits_T_2 = or(out[2].d.bits.source, UInt<7>(0h0))
node requestDOI_uncommonBits_2 = bits(_requestDOI_uncommonBits_T_2, 6, 0)
node _requestDOI_T_10 = shr(out[2].d.bits.source, 7)
node _requestDOI_T_11 = eq(_requestDOI_T_10, UInt<1>(0h0))
node _requestDOI_T_12 = leq(UInt<1>(0h0), requestDOI_uncommonBits_2)
node _requestDOI_T_13 = and(_requestDOI_T_11, _requestDOI_T_12)
node _requestDOI_T_14 = leq(requestDOI_uncommonBits_2, UInt<7>(0h7f))
node requestDOI_2_0 = and(_requestDOI_T_13, _requestDOI_T_14)
wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE.valid, UInt<1>(0h0)
connect _requestEIO_WIRE.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits
connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid
connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready
wire _requestEIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_2.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE_2.valid, UInt<1>(0h0)
connect _requestEIO_WIRE_2.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_3.bits, _requestEIO_WIRE_2.bits
connect _requestEIO_WIRE_3.valid, _requestEIO_WIRE_2.valid
connect _requestEIO_WIRE_3.ready, _requestEIO_WIRE_2.ready
wire _requestEIO_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_4.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE_4.valid, UInt<1>(0h0)
connect _requestEIO_WIRE_4.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_5.bits, _requestEIO_WIRE_4.bits
connect _requestEIO_WIRE_5.valid, _requestEIO_WIRE_4.valid
connect _requestEIO_WIRE_5.ready, _requestEIO_WIRE_4.ready
node _beatsAI_decode_T = dshl(UInt<6>(0h3f), in[0].a.bits.size)
node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 5, 0)
node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1)
node beatsAI_decode = shr(_beatsAI_decode_T_2, 3)
node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2)
node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0))
node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0))
wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0)
connect _beatsBO_WIRE.bits.data, UInt<64>(0h0)
connect _beatsBO_WIRE.bits.mask, UInt<8>(0h0)
connect _beatsBO_WIRE.bits.address, UInt<29>(0h0)
connect _beatsBO_WIRE.bits.source, UInt<7>(0h0)
connect _beatsBO_WIRE.bits.size, UInt<3>(0h0)
connect _beatsBO_WIRE.bits.param, UInt<2>(0h0)
connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0)
connect _beatsBO_WIRE.valid, UInt<1>(0h0)
connect _beatsBO_WIRE.ready, UInt<1>(0h0)
wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits
connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid
connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready
node _beatsBO_decode_T = dshl(UInt<6>(0h3f), _beatsBO_WIRE_1.bits.size)
node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 5, 0)
node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1)
node beatsBO_decode = shr(_beatsBO_decode_T_2, 3)
node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2)
node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0))
node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0))
wire _beatsBO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _beatsBO_WIRE_2.bits.data, UInt<64>(0h0)
connect _beatsBO_WIRE_2.bits.mask, UInt<8>(0h0)
connect _beatsBO_WIRE_2.bits.address, UInt<29>(0h0)
connect _beatsBO_WIRE_2.bits.source, UInt<7>(0h0)
connect _beatsBO_WIRE_2.bits.size, UInt<3>(0h0)
connect _beatsBO_WIRE_2.bits.param, UInt<2>(0h0)
connect _beatsBO_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _beatsBO_WIRE_2.valid, UInt<1>(0h0)
connect _beatsBO_WIRE_2.ready, UInt<1>(0h0)
wire _beatsBO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_3.bits, _beatsBO_WIRE_2.bits
connect _beatsBO_WIRE_3.valid, _beatsBO_WIRE_2.valid
connect _beatsBO_WIRE_3.ready, _beatsBO_WIRE_2.ready
node _beatsBO_decode_T_3 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_3.bits.size)
node _beatsBO_decode_T_4 = bits(_beatsBO_decode_T_3, 5, 0)
node _beatsBO_decode_T_5 = not(_beatsBO_decode_T_4)
node beatsBO_decode_1 = shr(_beatsBO_decode_T_5, 3)
node _beatsBO_opdata_T_1 = bits(_beatsBO_WIRE_3.bits.opcode, 2, 2)
node beatsBO_opdata_1 = eq(_beatsBO_opdata_T_1, UInt<1>(0h0))
node beatsBO_1 = mux(UInt<1>(0h0), beatsBO_decode_1, UInt<1>(0h0))
wire _beatsBO_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _beatsBO_WIRE_4.bits.data, UInt<64>(0h0)
connect _beatsBO_WIRE_4.bits.mask, UInt<8>(0h0)
connect _beatsBO_WIRE_4.bits.address, UInt<29>(0h0)
connect _beatsBO_WIRE_4.bits.source, UInt<7>(0h0)
connect _beatsBO_WIRE_4.bits.size, UInt<3>(0h0)
connect _beatsBO_WIRE_4.bits.param, UInt<2>(0h0)
connect _beatsBO_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _beatsBO_WIRE_4.valid, UInt<1>(0h0)
connect _beatsBO_WIRE_4.ready, UInt<1>(0h0)
wire _beatsBO_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_5.bits, _beatsBO_WIRE_4.bits
connect _beatsBO_WIRE_5.valid, _beatsBO_WIRE_4.valid
connect _beatsBO_WIRE_5.ready, _beatsBO_WIRE_4.ready
node _beatsBO_decode_T_6 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_5.bits.size)
node _beatsBO_decode_T_7 = bits(_beatsBO_decode_T_6, 5, 0)
node _beatsBO_decode_T_8 = not(_beatsBO_decode_T_7)
node beatsBO_decode_2 = shr(_beatsBO_decode_T_8, 3)
node _beatsBO_opdata_T_2 = bits(_beatsBO_WIRE_5.bits.opcode, 2, 2)
node beatsBO_opdata_2 = eq(_beatsBO_opdata_T_2, UInt<1>(0h0))
node beatsBO_2 = mux(UInt<1>(0h0), beatsBO_decode_2, UInt<1>(0h0))
wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.data, UInt<64>(0h0)
connect _beatsCI_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.address, UInt<29>(0h0)
connect _beatsCI_WIRE.bits.source, UInt<7>(0h0)
connect _beatsCI_WIRE.bits.size, UInt<3>(0h0)
connect _beatsCI_WIRE.bits.param, UInt<3>(0h0)
connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0)
connect _beatsCI_WIRE.valid, UInt<1>(0h0)
connect _beatsCI_WIRE.ready, UInt<1>(0h0)
wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits
connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid
connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready
node _beatsCI_decode_T = dshl(UInt<6>(0h3f), _beatsCI_WIRE_1.bits.size)
node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 5, 0)
node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1)
node beatsCI_decode = shr(_beatsCI_decode_T_2, 3)
node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0)
node beatsCI_0 = mux(beatsCI_opdata, beatsCI_decode, UInt<1>(0h0))
node _beatsDO_decode_T = dshl(UInt<6>(0h3f), out[0].d.bits.size)
node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 5, 0)
node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1)
node beatsDO_decode = shr(_beatsDO_decode_T_2, 3)
node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0)
node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0))
node _beatsDO_decode_T_3 = dshl(UInt<6>(0h3f), out[1].d.bits.size)
node _beatsDO_decode_T_4 = bits(_beatsDO_decode_T_3, 5, 0)
node _beatsDO_decode_T_5 = not(_beatsDO_decode_T_4)
node beatsDO_decode_1 = shr(_beatsDO_decode_T_5, 3)
node beatsDO_opdata_1 = bits(out[1].d.bits.opcode, 0, 0)
node beatsDO_1 = mux(beatsDO_opdata_1, beatsDO_decode_1, UInt<1>(0h0))
node _beatsDO_decode_T_6 = dshl(UInt<6>(0h3f), out[2].d.bits.size)
node _beatsDO_decode_T_7 = bits(_beatsDO_decode_T_6, 5, 0)
node _beatsDO_decode_T_8 = not(_beatsDO_decode_T_7)
node beatsDO_decode_2 = shr(_beatsDO_decode_T_8, 3)
node beatsDO_opdata_2 = bits(out[2].d.bits.opcode, 0, 0)
node beatsDO_2 = mux(beatsDO_opdata_2, beatsDO_decode_2, UInt<1>(0h0))
wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE.bits.sink, UInt<1>(0h0)
connect _beatsEI_WIRE.valid, UInt<1>(0h0)
connect _beatsEI_WIRE.ready, UInt<1>(0h0)
wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits
connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid
connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready
wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[3]
connect portsAOI_filtered[0].bits, in[0].a.bits
node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h0))
node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T)
connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1
connect portsAOI_filtered[1].bits, in[0].a.bits
node _portsAOI_filtered_1_valid_T = or(requestAIO_0_1, UInt<1>(0h0))
node _portsAOI_filtered_1_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_1_valid_T)
connect portsAOI_filtered[1].valid, _portsAOI_filtered_1_valid_T_1
connect portsAOI_filtered[2].bits, in[0].a.bits
node _portsAOI_filtered_2_valid_T = or(requestAIO_0_2, UInt<1>(0h0))
node _portsAOI_filtered_2_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_2_valid_T)
connect portsAOI_filtered[2].valid, _portsAOI_filtered_2_valid_T_1
node _portsAOI_in_0_a_ready_T = mux(requestAIO_0_0, portsAOI_filtered[0].ready, UInt<1>(0h0))
node _portsAOI_in_0_a_ready_T_1 = mux(requestAIO_0_1, portsAOI_filtered[1].ready, UInt<1>(0h0))
node _portsAOI_in_0_a_ready_T_2 = mux(requestAIO_0_2, portsAOI_filtered[2].ready, UInt<1>(0h0))
node _portsAOI_in_0_a_ready_T_3 = or(_portsAOI_in_0_a_ready_T, _portsAOI_in_0_a_ready_T_1)
node _portsAOI_in_0_a_ready_T_4 = or(_portsAOI_in_0_a_ready_T_3, _portsAOI_in_0_a_ready_T_2)
wire _portsAOI_in_0_a_ready_WIRE : UInt<1>
connect _portsAOI_in_0_a_ready_WIRE, _portsAOI_in_0_a_ready_T_4
connect in[0].a.ready, _portsAOI_in_0_a_ready_WIRE
wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0)
connect _portsBIO_WIRE.bits.data, UInt<64>(0h0)
connect _portsBIO_WIRE.bits.mask, UInt<8>(0h0)
connect _portsBIO_WIRE.bits.address, UInt<29>(0h0)
connect _portsBIO_WIRE.bits.source, UInt<7>(0h0)
connect _portsBIO_WIRE.bits.size, UInt<3>(0h0)
connect _portsBIO_WIRE.bits.param, UInt<2>(0h0)
connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0)
connect _portsBIO_WIRE.valid, UInt<1>(0h0)
connect _portsBIO_WIRE.ready, UInt<1>(0h0)
wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits
connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid
connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready
wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits
node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h1))
node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T)
connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1
connect _portsBIO_WIRE_1.ready, portsBIO_filtered[0].ready
wire _portsBIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _portsBIO_WIRE_2.bits.data, UInt<64>(0h0)
connect _portsBIO_WIRE_2.bits.mask, UInt<8>(0h0)
connect _portsBIO_WIRE_2.bits.address, UInt<29>(0h0)
connect _portsBIO_WIRE_2.bits.source, UInt<7>(0h0)
connect _portsBIO_WIRE_2.bits.size, UInt<3>(0h0)
connect _portsBIO_WIRE_2.bits.param, UInt<2>(0h0)
connect _portsBIO_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _portsBIO_WIRE_2.valid, UInt<1>(0h0)
connect _portsBIO_WIRE_2.ready, UInt<1>(0h0)
wire _portsBIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_3.bits, _portsBIO_WIRE_2.bits
connect _portsBIO_WIRE_3.valid, _portsBIO_WIRE_2.valid
connect _portsBIO_WIRE_3.ready, _portsBIO_WIRE_2.ready
wire portsBIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsBIO_filtered_1[0].bits, _portsBIO_WIRE_3.bits
node _portsBIO_filtered_0_valid_T_2 = or(requestBOI_1_0, UInt<1>(0h1))
node _portsBIO_filtered_0_valid_T_3 = and(_portsBIO_WIRE_3.valid, _portsBIO_filtered_0_valid_T_2)
connect portsBIO_filtered_1[0].valid, _portsBIO_filtered_0_valid_T_3
connect _portsBIO_WIRE_3.ready, portsBIO_filtered_1[0].ready
wire _portsBIO_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _portsBIO_WIRE_4.bits.data, UInt<64>(0h0)
connect _portsBIO_WIRE_4.bits.mask, UInt<8>(0h0)
connect _portsBIO_WIRE_4.bits.address, UInt<29>(0h0)
connect _portsBIO_WIRE_4.bits.source, UInt<7>(0h0)
connect _portsBIO_WIRE_4.bits.size, UInt<3>(0h0)
connect _portsBIO_WIRE_4.bits.param, UInt<2>(0h0)
connect _portsBIO_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _portsBIO_WIRE_4.valid, UInt<1>(0h0)
connect _portsBIO_WIRE_4.ready, UInt<1>(0h0)
wire _portsBIO_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_5.bits, _portsBIO_WIRE_4.bits
connect _portsBIO_WIRE_5.valid, _portsBIO_WIRE_4.valid
connect _portsBIO_WIRE_5.ready, _portsBIO_WIRE_4.ready
wire portsBIO_filtered_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsBIO_filtered_2[0].bits, _portsBIO_WIRE_5.bits
node _portsBIO_filtered_0_valid_T_4 = or(requestBOI_2_0, UInt<1>(0h1))
node _portsBIO_filtered_0_valid_T_5 = and(_portsBIO_WIRE_5.valid, _portsBIO_filtered_0_valid_T_4)
connect portsBIO_filtered_2[0].valid, _portsBIO_filtered_0_valid_T_5
connect _portsBIO_WIRE_5.ready, portsBIO_filtered_2[0].ready
wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.data, UInt<64>(0h0)
connect _portsCOI_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.address, UInt<29>(0h0)
connect _portsCOI_WIRE.bits.source, UInt<7>(0h0)
connect _portsCOI_WIRE.bits.size, UInt<3>(0h0)
connect _portsCOI_WIRE.bits.param, UInt<3>(0h0)
connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0)
connect _portsCOI_WIRE.valid, UInt<1>(0h0)
connect _portsCOI_WIRE.ready, UInt<1>(0h0)
wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits
connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid
connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready
wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[3]
connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits
node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h0))
node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T)
connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1
connect portsCOI_filtered[1].bits, _portsCOI_WIRE_1.bits
node _portsCOI_filtered_1_valid_T = or(requestCIO_0_1, UInt<1>(0h0))
node _portsCOI_filtered_1_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_1_valid_T)
connect portsCOI_filtered[1].valid, _portsCOI_filtered_1_valid_T_1
connect portsCOI_filtered[2].bits, _portsCOI_WIRE_1.bits
node _portsCOI_filtered_2_valid_T = or(requestCIO_0_2, UInt<1>(0h0))
node _portsCOI_filtered_2_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_2_valid_T)
connect portsCOI_filtered[2].valid, _portsCOI_filtered_2_valid_T_1
node _portsCOI_T = mux(requestCIO_0_0, portsCOI_filtered[0].ready, UInt<1>(0h0))
node _portsCOI_T_1 = mux(requestCIO_0_1, portsCOI_filtered[1].ready, UInt<1>(0h0))
node _portsCOI_T_2 = mux(requestCIO_0_2, portsCOI_filtered[2].ready, UInt<1>(0h0))
node _portsCOI_T_3 = or(_portsCOI_T, _portsCOI_T_1)
node _portsCOI_T_4 = or(_portsCOI_T_3, _portsCOI_T_2)
wire _portsCOI_WIRE_2 : UInt<1>
connect _portsCOI_WIRE_2, _portsCOI_T_4
connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE_2
wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[0].bits.data, out[0].d.bits.data
connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[0].bits.source, out[0].d.bits.source
connect portsDIO_filtered[0].bits.size, out[0].d.bits.size
connect portsDIO_filtered[0].bits.param, out[0].d.bits.param
connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h1))
node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T)
connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1
connect out[0].d.ready, portsDIO_filtered[0].ready
wire portsDIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsDIO_filtered_1[0].bits.corrupt, out[1].d.bits.corrupt
connect portsDIO_filtered_1[0].bits.data, out[1].d.bits.data
connect portsDIO_filtered_1[0].bits.denied, out[1].d.bits.denied
connect portsDIO_filtered_1[0].bits.sink, out[1].d.bits.sink
connect portsDIO_filtered_1[0].bits.source, out[1].d.bits.source
connect portsDIO_filtered_1[0].bits.size, out[1].d.bits.size
connect portsDIO_filtered_1[0].bits.param, out[1].d.bits.param
connect portsDIO_filtered_1[0].bits.opcode, out[1].d.bits.opcode
node _portsDIO_filtered_0_valid_T_2 = or(requestDOI_1_0, UInt<1>(0h1))
node _portsDIO_filtered_0_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_0_valid_T_2)
connect portsDIO_filtered_1[0].valid, _portsDIO_filtered_0_valid_T_3
connect out[1].d.ready, portsDIO_filtered_1[0].ready
wire portsDIO_filtered_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsDIO_filtered_2[0].bits.corrupt, out[2].d.bits.corrupt
connect portsDIO_filtered_2[0].bits.data, out[2].d.bits.data
connect portsDIO_filtered_2[0].bits.denied, out[2].d.bits.denied
connect portsDIO_filtered_2[0].bits.sink, out[2].d.bits.sink
connect portsDIO_filtered_2[0].bits.source, out[2].d.bits.source
connect portsDIO_filtered_2[0].bits.size, out[2].d.bits.size
connect portsDIO_filtered_2[0].bits.param, out[2].d.bits.param
connect portsDIO_filtered_2[0].bits.opcode, out[2].d.bits.opcode
node _portsDIO_filtered_0_valid_T_4 = or(requestDOI_2_0, UInt<1>(0h1))
node _portsDIO_filtered_0_valid_T_5 = and(out[2].d.valid, _portsDIO_filtered_0_valid_T_4)
connect portsDIO_filtered_2[0].valid, _portsDIO_filtered_0_valid_T_5
connect out[2].d.ready, portsDIO_filtered_2[0].ready
wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE.bits.sink, UInt<1>(0h0)
connect _portsEOI_WIRE.valid, UInt<1>(0h0)
connect _portsEOI_WIRE.ready, UInt<1>(0h0)
wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits
connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid
connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready
wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[3]
connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits
node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T)
connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1
connect portsEOI_filtered[1].bits, _portsEOI_WIRE_1.bits
node _portsEOI_filtered_1_valid_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_1_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_1_valid_T)
connect portsEOI_filtered[1].valid, _portsEOI_filtered_1_valid_T_1
connect portsEOI_filtered[2].bits, _portsEOI_WIRE_1.bits
node _portsEOI_filtered_2_valid_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_2_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_2_valid_T)
connect portsEOI_filtered[2].valid, _portsEOI_filtered_2_valid_T_1
node _portsEOI_T = mux(UInt<1>(0h0), portsEOI_filtered[0].ready, UInt<1>(0h0))
node _portsEOI_T_1 = mux(UInt<1>(0h0), portsEOI_filtered[1].ready, UInt<1>(0h0))
node _portsEOI_T_2 = mux(UInt<1>(0h0), portsEOI_filtered[2].ready, UInt<1>(0h0))
node _portsEOI_T_3 = or(_portsEOI_T, _portsEOI_T_1)
node _portsEOI_T_4 = or(_portsEOI_T_3, _portsEOI_T_2)
wire _portsEOI_WIRE_2 : UInt<1>
connect _portsEOI_WIRE_2, _portsEOI_T_4
connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE_2
connect out[0].a, portsAOI_filtered[0]
wire _WIRE_96 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_96.bits.corrupt, UInt<1>(0h0)
connect _WIRE_96.bits.data, UInt<64>(0h0)
connect _WIRE_96.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_96.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_96.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_96.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_96.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_96.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_96.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_96.bits.address, UInt<29>(0h0)
connect _WIRE_96.bits.source, UInt<7>(0h0)
connect _WIRE_96.bits.size, UInt<3>(0h0)
connect _WIRE_96.bits.param, UInt<3>(0h0)
connect _WIRE_96.bits.opcode, UInt<3>(0h0)
connect _WIRE_96.valid, UInt<1>(0h0)
connect _WIRE_96.ready, UInt<1>(0h0)
wire _WIRE_97 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_97.bits, _WIRE_96.bits
connect _WIRE_97.valid, _WIRE_96.valid
connect _WIRE_97.ready, _WIRE_96.ready
invalidate _WIRE_97.bits.corrupt
invalidate _WIRE_97.bits.data
invalidate _WIRE_97.bits.user.amba_prot.fetch
invalidate _WIRE_97.bits.user.amba_prot.secure
invalidate _WIRE_97.bits.user.amba_prot.privileged
invalidate _WIRE_97.bits.user.amba_prot.writealloc
invalidate _WIRE_97.bits.user.amba_prot.readalloc
invalidate _WIRE_97.bits.user.amba_prot.modifiable
invalidate _WIRE_97.bits.user.amba_prot.bufferable
invalidate _WIRE_97.bits.address
invalidate _WIRE_97.bits.source
invalidate _WIRE_97.bits.size
invalidate _WIRE_97.bits.param
invalidate _WIRE_97.bits.opcode
wire _WIRE_98 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_98.bits.sink, UInt<1>(0h0)
connect _WIRE_98.valid, UInt<1>(0h0)
connect _WIRE_98.ready, UInt<1>(0h0)
wire _WIRE_99 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_99.bits, _WIRE_98.bits
connect _WIRE_99.valid, _WIRE_98.valid
connect _WIRE_99.ready, _WIRE_98.ready
invalidate _WIRE_99.bits.sink
connect portsCOI_filtered[0].ready, UInt<1>(0h0)
connect portsEOI_filtered[0].ready, UInt<1>(0h0)
connect out[1].a, portsAOI_filtered[1]
wire _WIRE_100 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_100.bits.corrupt, UInt<1>(0h0)
connect _WIRE_100.bits.data, UInt<64>(0h0)
connect _WIRE_100.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_100.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_100.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_100.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_100.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_100.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_100.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_100.bits.address, UInt<29>(0h0)
connect _WIRE_100.bits.source, UInt<7>(0h0)
connect _WIRE_100.bits.size, UInt<3>(0h0)
connect _WIRE_100.bits.param, UInt<3>(0h0)
connect _WIRE_100.bits.opcode, UInt<3>(0h0)
connect _WIRE_100.valid, UInt<1>(0h0)
connect _WIRE_100.ready, UInt<1>(0h0)
wire _WIRE_101 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_101.bits, _WIRE_100.bits
connect _WIRE_101.valid, _WIRE_100.valid
connect _WIRE_101.ready, _WIRE_100.ready
invalidate _WIRE_101.bits.corrupt
invalidate _WIRE_101.bits.data
invalidate _WIRE_101.bits.user.amba_prot.fetch
invalidate _WIRE_101.bits.user.amba_prot.secure
invalidate _WIRE_101.bits.user.amba_prot.privileged
invalidate _WIRE_101.bits.user.amba_prot.writealloc
invalidate _WIRE_101.bits.user.amba_prot.readalloc
invalidate _WIRE_101.bits.user.amba_prot.modifiable
invalidate _WIRE_101.bits.user.amba_prot.bufferable
invalidate _WIRE_101.bits.address
invalidate _WIRE_101.bits.source
invalidate _WIRE_101.bits.size
invalidate _WIRE_101.bits.param
invalidate _WIRE_101.bits.opcode
wire _WIRE_102 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_102.bits.sink, UInt<1>(0h0)
connect _WIRE_102.valid, UInt<1>(0h0)
connect _WIRE_102.ready, UInt<1>(0h0)
wire _WIRE_103 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_103.bits, _WIRE_102.bits
connect _WIRE_103.valid, _WIRE_102.valid
connect _WIRE_103.ready, _WIRE_102.ready
invalidate _WIRE_103.bits.sink
connect portsCOI_filtered[1].ready, UInt<1>(0h0)
connect portsEOI_filtered[1].ready, UInt<1>(0h0)
connect out[2].a, portsAOI_filtered[2]
wire _WIRE_104 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_104.bits.corrupt, UInt<1>(0h0)
connect _WIRE_104.bits.data, UInt<64>(0h0)
connect _WIRE_104.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_104.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_104.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_104.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_104.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_104.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_104.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_104.bits.address, UInt<29>(0h0)
connect _WIRE_104.bits.source, UInt<7>(0h0)
connect _WIRE_104.bits.size, UInt<3>(0h0)
connect _WIRE_104.bits.param, UInt<3>(0h0)
connect _WIRE_104.bits.opcode, UInt<3>(0h0)
connect _WIRE_104.valid, UInt<1>(0h0)
connect _WIRE_104.ready, UInt<1>(0h0)
wire _WIRE_105 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_105.bits, _WIRE_104.bits
connect _WIRE_105.valid, _WIRE_104.valid
connect _WIRE_105.ready, _WIRE_104.ready
invalidate _WIRE_105.bits.corrupt
invalidate _WIRE_105.bits.data
invalidate _WIRE_105.bits.user.amba_prot.fetch
invalidate _WIRE_105.bits.user.amba_prot.secure
invalidate _WIRE_105.bits.user.amba_prot.privileged
invalidate _WIRE_105.bits.user.amba_prot.writealloc
invalidate _WIRE_105.bits.user.amba_prot.readalloc
invalidate _WIRE_105.bits.user.amba_prot.modifiable
invalidate _WIRE_105.bits.user.amba_prot.bufferable
invalidate _WIRE_105.bits.address
invalidate _WIRE_105.bits.source
invalidate _WIRE_105.bits.size
invalidate _WIRE_105.bits.param
invalidate _WIRE_105.bits.opcode
wire _WIRE_106 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_106.bits.sink, UInt<1>(0h0)
connect _WIRE_106.valid, UInt<1>(0h0)
connect _WIRE_106.ready, UInt<1>(0h0)
wire _WIRE_107 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_107.bits, _WIRE_106.bits
connect _WIRE_107.valid, _WIRE_106.valid
connect _WIRE_107.ready, _WIRE_106.ready
invalidate _WIRE_107.bits.sink
connect portsCOI_filtered[2].ready, UInt<1>(0h0)
connect portsEOI_filtered[2].ready, UInt<1>(0h0)
wire _WIRE_108 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_108.bits.corrupt, UInt<1>(0h0)
connect _WIRE_108.bits.data, UInt<64>(0h0)
connect _WIRE_108.bits.mask, UInt<8>(0h0)
connect _WIRE_108.bits.address, UInt<29>(0h0)
connect _WIRE_108.bits.source, UInt<7>(0h0)
connect _WIRE_108.bits.size, UInt<3>(0h0)
connect _WIRE_108.bits.param, UInt<2>(0h0)
connect _WIRE_108.bits.opcode, UInt<3>(0h0)
connect _WIRE_108.valid, UInt<1>(0h0)
connect _WIRE_108.ready, UInt<1>(0h0)
wire _WIRE_109 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_109.bits, _WIRE_108.bits
connect _WIRE_109.valid, _WIRE_108.valid
connect _WIRE_109.ready, _WIRE_108.ready
invalidate _WIRE_109.bits.corrupt
invalidate _WIRE_109.bits.data
invalidate _WIRE_109.bits.mask
invalidate _WIRE_109.bits.address
invalidate _WIRE_109.bits.source
invalidate _WIRE_109.bits.size
invalidate _WIRE_109.bits.param
invalidate _WIRE_109.bits.opcode
regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0)
node idle = eq(beatsLeft, UInt<1>(0h0))
node latch = and(idle, in[0].d.ready)
node readys_hi = cat(portsDIO_filtered_2[0].valid, portsDIO_filtered_1[0].valid)
node _readys_T = cat(readys_hi, portsDIO_filtered[0].valid)
node readys_valid = bits(_readys_T, 2, 0)
node _readys_T_1 = eq(readys_valid, _readys_T)
node _readys_T_2 = asUInt(reset)
node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0))
when _readys_T_3 :
node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0))
when _readys_T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf
assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert
regreset readys_mask : UInt<3>, clock, reset, UInt<3>(0h7)
node _readys_filter_T = not(readys_mask)
node _readys_filter_T_1 = and(readys_valid, _readys_filter_T)
node readys_filter = cat(_readys_filter_T_1, readys_valid)
node _readys_unready_T = shr(readys_filter, 1)
node _readys_unready_T_1 = or(readys_filter, _readys_unready_T)
node _readys_unready_T_2 = shr(_readys_unready_T_1, 2)
node _readys_unready_T_3 = or(_readys_unready_T_1, _readys_unready_T_2)
node _readys_unready_T_4 = bits(_readys_unready_T_3, 5, 0)
node _readys_unready_T_5 = shr(_readys_unready_T_4, 1)
node _readys_unready_T_6 = shl(readys_mask, 3)
node readys_unready = or(_readys_unready_T_5, _readys_unready_T_6)
node _readys_readys_T = shr(readys_unready, 3)
node _readys_readys_T_1 = bits(readys_unready, 2, 0)
node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1)
node readys_readys = not(_readys_readys_T_2)
node _readys_T_5 = orr(readys_valid)
node _readys_T_6 = and(latch, _readys_T_5)
when _readys_T_6 :
node _readys_mask_T = and(readys_readys, readys_valid)
node _readys_mask_T_1 = shl(_readys_mask_T, 1)
node _readys_mask_T_2 = bits(_readys_mask_T_1, 2, 0)
node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2)
node _readys_mask_T_4 = shl(_readys_mask_T_3, 2)
node _readys_mask_T_5 = bits(_readys_mask_T_4, 2, 0)
node _readys_mask_T_6 = or(_readys_mask_T_3, _readys_mask_T_5)
node _readys_mask_T_7 = bits(_readys_mask_T_6, 2, 0)
connect readys_mask, _readys_mask_T_7
node _readys_T_7 = bits(readys_readys, 2, 0)
node _readys_T_8 = bits(_readys_T_7, 0, 0)
node _readys_T_9 = bits(_readys_T_7, 1, 1)
node _readys_T_10 = bits(_readys_T_7, 2, 2)
wire readys : UInt<1>[3]
connect readys[0], _readys_T_8
connect readys[1], _readys_T_9
connect readys[2], _readys_T_10
node _winner_T = and(readys[0], portsDIO_filtered[0].valid)
node _winner_T_1 = and(readys[1], portsDIO_filtered_1[0].valid)
node _winner_T_2 = and(readys[2], portsDIO_filtered_2[0].valid)
wire winner : UInt<1>[3]
connect winner[0], _winner_T
connect winner[1], _winner_T_1
connect winner[2], _winner_T_2
node prefixOR_1 = or(UInt<1>(0h0), winner[0])
node prefixOR_2 = or(prefixOR_1, winner[1])
node _prefixOR_T = or(prefixOR_2, winner[2])
node _T = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_1 = eq(winner[0], UInt<1>(0h0))
node _T_2 = or(_T, _T_1)
node _T_3 = eq(prefixOR_1, UInt<1>(0h0))
node _T_4 = eq(winner[1], UInt<1>(0h0))
node _T_5 = or(_T_3, _T_4)
node _T_6 = eq(prefixOR_2, UInt<1>(0h0))
node _T_7 = eq(winner[2], UInt<1>(0h0))
node _T_8 = or(_T_6, _T_7)
node _T_9 = and(_T_2, _T_5)
node _T_10 = and(_T_9, _T_8)
node _T_11 = asUInt(reset)
node _T_12 = eq(_T_11, UInt<1>(0h0))
when _T_12 :
node _T_13 = eq(_T_10, UInt<1>(0h0))
when _T_13 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf
assert(clock, _T_10, UInt<1>(0h1), "") : assert
node _T_14 = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid)
node _T_15 = or(_T_14, portsDIO_filtered_2[0].valid)
node _T_16 = eq(_T_15, UInt<1>(0h0))
node _T_17 = or(winner[0], winner[1])
node _T_18 = or(_T_17, winner[2])
node _T_19 = or(_T_16, _T_18)
node _T_20 = asUInt(reset)
node _T_21 = eq(_T_20, UInt<1>(0h0))
when _T_21 :
node _T_22 = eq(_T_19, UInt<1>(0h0))
when _T_22 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1
assert(clock, _T_19, UInt<1>(0h1), "") : assert_1
node maskedBeats_0 = mux(winner[0], beatsDO_0, UInt<1>(0h0))
node maskedBeats_1 = mux(winner[1], beatsDO_1, UInt<1>(0h0))
node maskedBeats_2 = mux(winner[2], beatsDO_2, UInt<1>(0h0))
node _initBeats_T = or(maskedBeats_0, maskedBeats_1)
node initBeats = or(_initBeats_T, maskedBeats_2)
node _beatsLeft_T = and(in[0].d.ready, in[0].d.valid)
node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T)
node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1)
node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2)
connect beatsLeft, _beatsLeft_T_3
wire _state_WIRE : UInt<1>[3]
connect _state_WIRE[0], UInt<1>(0h0)
connect _state_WIRE[1], UInt<1>(0h0)
connect _state_WIRE[2], UInt<1>(0h0)
regreset state : UInt<1>[3], clock, reset, _state_WIRE
node muxState = mux(idle, winner, state)
connect state, muxState
node allowed = mux(idle, readys, state)
node _filtered_0_ready_T = and(in[0].d.ready, allowed[0])
connect portsDIO_filtered[0].ready, _filtered_0_ready_T
node _filtered_0_ready_T_1 = and(in[0].d.ready, allowed[1])
connect portsDIO_filtered_1[0].ready, _filtered_0_ready_T_1
node _filtered_0_ready_T_2 = and(in[0].d.ready, allowed[2])
connect portsDIO_filtered_2[0].ready, _filtered_0_ready_T_2
node _in_0_d_valid_T = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid)
node _in_0_d_valid_T_1 = or(_in_0_d_valid_T, portsDIO_filtered_2[0].valid)
node _in_0_d_valid_T_2 = mux(state[0], portsDIO_filtered[0].valid, UInt<1>(0h0))
node _in_0_d_valid_T_3 = mux(state[1], portsDIO_filtered_1[0].valid, UInt<1>(0h0))
node _in_0_d_valid_T_4 = mux(state[2], portsDIO_filtered_2[0].valid, UInt<1>(0h0))
node _in_0_d_valid_T_5 = or(_in_0_d_valid_T_2, _in_0_d_valid_T_3)
node _in_0_d_valid_T_6 = or(_in_0_d_valid_T_5, _in_0_d_valid_T_4)
wire _in_0_d_valid_WIRE : UInt<1>
connect _in_0_d_valid_WIRE, _in_0_d_valid_T_6
node _in_0_d_valid_T_7 = mux(idle, _in_0_d_valid_T_1, _in_0_d_valid_WIRE)
connect in[0].d.valid, _in_0_d_valid_T_7
wire _in_0_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_0_d_bits_T = mux(muxState[0], portsDIO_filtered[0].bits.corrupt, UInt<1>(0h0))
node _in_0_d_bits_T_1 = mux(muxState[1], portsDIO_filtered_1[0].bits.corrupt, UInt<1>(0h0))
node _in_0_d_bits_T_2 = mux(muxState[2], portsDIO_filtered_2[0].bits.corrupt, UInt<1>(0h0))
node _in_0_d_bits_T_3 = or(_in_0_d_bits_T, _in_0_d_bits_T_1)
node _in_0_d_bits_T_4 = or(_in_0_d_bits_T_3, _in_0_d_bits_T_2)
wire _in_0_d_bits_WIRE_1 : UInt<1>
connect _in_0_d_bits_WIRE_1, _in_0_d_bits_T_4
connect _in_0_d_bits_WIRE.corrupt, _in_0_d_bits_WIRE_1
node _in_0_d_bits_T_5 = mux(muxState[0], portsDIO_filtered[0].bits.data, UInt<1>(0h0))
node _in_0_d_bits_T_6 = mux(muxState[1], portsDIO_filtered_1[0].bits.data, UInt<1>(0h0))
node _in_0_d_bits_T_7 = mux(muxState[2], portsDIO_filtered_2[0].bits.data, UInt<1>(0h0))
node _in_0_d_bits_T_8 = or(_in_0_d_bits_T_5, _in_0_d_bits_T_6)
node _in_0_d_bits_T_9 = or(_in_0_d_bits_T_8, _in_0_d_bits_T_7)
wire _in_0_d_bits_WIRE_2 : UInt<64>
connect _in_0_d_bits_WIRE_2, _in_0_d_bits_T_9
connect _in_0_d_bits_WIRE.data, _in_0_d_bits_WIRE_2
wire _in_0_d_bits_WIRE_3 : { }
connect _in_0_d_bits_WIRE.echo, _in_0_d_bits_WIRE_3
wire _in_0_d_bits_WIRE_4 : { }
connect _in_0_d_bits_WIRE.user, _in_0_d_bits_WIRE_4
node _in_0_d_bits_T_10 = mux(muxState[0], portsDIO_filtered[0].bits.denied, UInt<1>(0h0))
node _in_0_d_bits_T_11 = mux(muxState[1], portsDIO_filtered_1[0].bits.denied, UInt<1>(0h0))
node _in_0_d_bits_T_12 = mux(muxState[2], portsDIO_filtered_2[0].bits.denied, UInt<1>(0h0))
node _in_0_d_bits_T_13 = or(_in_0_d_bits_T_10, _in_0_d_bits_T_11)
node _in_0_d_bits_T_14 = or(_in_0_d_bits_T_13, _in_0_d_bits_T_12)
wire _in_0_d_bits_WIRE_5 : UInt<1>
connect _in_0_d_bits_WIRE_5, _in_0_d_bits_T_14
connect _in_0_d_bits_WIRE.denied, _in_0_d_bits_WIRE_5
node _in_0_d_bits_T_15 = mux(muxState[0], portsDIO_filtered[0].bits.sink, UInt<1>(0h0))
node _in_0_d_bits_T_16 = mux(muxState[1], portsDIO_filtered_1[0].bits.sink, UInt<1>(0h0))
node _in_0_d_bits_T_17 = mux(muxState[2], portsDIO_filtered_2[0].bits.sink, UInt<1>(0h0))
node _in_0_d_bits_T_18 = or(_in_0_d_bits_T_15, _in_0_d_bits_T_16)
node _in_0_d_bits_T_19 = or(_in_0_d_bits_T_18, _in_0_d_bits_T_17)
wire _in_0_d_bits_WIRE_6 : UInt<1>
connect _in_0_d_bits_WIRE_6, _in_0_d_bits_T_19
connect _in_0_d_bits_WIRE.sink, _in_0_d_bits_WIRE_6
node _in_0_d_bits_T_20 = mux(muxState[0], portsDIO_filtered[0].bits.source, UInt<1>(0h0))
node _in_0_d_bits_T_21 = mux(muxState[1], portsDIO_filtered_1[0].bits.source, UInt<1>(0h0))
node _in_0_d_bits_T_22 = mux(muxState[2], portsDIO_filtered_2[0].bits.source, UInt<1>(0h0))
node _in_0_d_bits_T_23 = or(_in_0_d_bits_T_20, _in_0_d_bits_T_21)
node _in_0_d_bits_T_24 = or(_in_0_d_bits_T_23, _in_0_d_bits_T_22)
wire _in_0_d_bits_WIRE_7 : UInt<7>
connect _in_0_d_bits_WIRE_7, _in_0_d_bits_T_24
connect _in_0_d_bits_WIRE.source, _in_0_d_bits_WIRE_7
node _in_0_d_bits_T_25 = mux(muxState[0], portsDIO_filtered[0].bits.size, UInt<1>(0h0))
node _in_0_d_bits_T_26 = mux(muxState[1], portsDIO_filtered_1[0].bits.size, UInt<1>(0h0))
node _in_0_d_bits_T_27 = mux(muxState[2], portsDIO_filtered_2[0].bits.size, UInt<1>(0h0))
node _in_0_d_bits_T_28 = or(_in_0_d_bits_T_25, _in_0_d_bits_T_26)
node _in_0_d_bits_T_29 = or(_in_0_d_bits_T_28, _in_0_d_bits_T_27)
wire _in_0_d_bits_WIRE_8 : UInt<3>
connect _in_0_d_bits_WIRE_8, _in_0_d_bits_T_29
connect _in_0_d_bits_WIRE.size, _in_0_d_bits_WIRE_8
node _in_0_d_bits_T_30 = mux(muxState[0], portsDIO_filtered[0].bits.param, UInt<1>(0h0))
node _in_0_d_bits_T_31 = mux(muxState[1], portsDIO_filtered_1[0].bits.param, UInt<1>(0h0))
node _in_0_d_bits_T_32 = mux(muxState[2], portsDIO_filtered_2[0].bits.param, UInt<1>(0h0))
node _in_0_d_bits_T_33 = or(_in_0_d_bits_T_30, _in_0_d_bits_T_31)
node _in_0_d_bits_T_34 = or(_in_0_d_bits_T_33, _in_0_d_bits_T_32)
wire _in_0_d_bits_WIRE_9 : UInt<2>
connect _in_0_d_bits_WIRE_9, _in_0_d_bits_T_34
connect _in_0_d_bits_WIRE.param, _in_0_d_bits_WIRE_9
node _in_0_d_bits_T_35 = mux(muxState[0], portsDIO_filtered[0].bits.opcode, UInt<1>(0h0))
node _in_0_d_bits_T_36 = mux(muxState[1], portsDIO_filtered_1[0].bits.opcode, UInt<1>(0h0))
node _in_0_d_bits_T_37 = mux(muxState[2], portsDIO_filtered_2[0].bits.opcode, UInt<1>(0h0))
node _in_0_d_bits_T_38 = or(_in_0_d_bits_T_35, _in_0_d_bits_T_36)
node _in_0_d_bits_T_39 = or(_in_0_d_bits_T_38, _in_0_d_bits_T_37)
wire _in_0_d_bits_WIRE_10 : UInt<3>
connect _in_0_d_bits_WIRE_10, _in_0_d_bits_T_39
connect _in_0_d_bits_WIRE.opcode, _in_0_d_bits_WIRE_10
connect in[0].d.bits.corrupt, _in_0_d_bits_WIRE.corrupt
connect in[0].d.bits.data, _in_0_d_bits_WIRE.data
connect in[0].d.bits.denied, _in_0_d_bits_WIRE.denied
connect in[0].d.bits.sink, _in_0_d_bits_WIRE.sink
connect in[0].d.bits.source, _in_0_d_bits_WIRE.source
connect in[0].d.bits.size, _in_0_d_bits_WIRE.size
connect in[0].d.bits.param, _in_0_d_bits_WIRE.param
connect in[0].d.bits.opcode, _in_0_d_bits_WIRE.opcode
connect portsBIO_filtered[0].ready, UInt<1>(0h0)
connect portsBIO_filtered_1[0].ready, UInt<1>(0h0)
connect portsBIO_filtered_2[0].ready, UInt<1>(0h0)
extmodule plusarg_reader_6 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_7 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLXbar_pbus_out_i1_o3_a29d64s7k1z3u( // @[Xbar.scala:74:9]
input clock, // @[Xbar.scala:74:9]
input reset, // @[Xbar.scala:74:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_2_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_2_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_2_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_out_2_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [14:0] auto_anon_out_2_a_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_2_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_2_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_2_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_2_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_out_2_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_2_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_2_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [12:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_0_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire requestAIO_0_0 = {auto_anon_in_a_bits_address[28], auto_anon_in_a_bits_address[14]} == 2'h0; // @[Parameters.scala:137:{41,46,59}]
wire requestAIO_0_1 = {~(auto_anon_in_a_bits_address[28]), auto_anon_in_a_bits_address[14]} == 2'h0; // @[Parameters.scala:137:{31,41,46,59}]
wire requestAIO_0_2 = {auto_anon_in_a_bits_address[28], ~(auto_anon_in_a_bits_address[14])} == 2'h0; // @[Parameters.scala:137:{31,41,46,59}]
wire _portsAOI_in_0_a_ready_T_4 = requestAIO_0_0 & auto_anon_out_0_a_ready | requestAIO_0_1 & auto_anon_out_1_a_ready | requestAIO_0_2 & auto_anon_out_2_a_ready; // @[Mux.scala:30:73]
reg [2:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 3'h0; // @[Arbiter.scala:60:30, :61:28]
wire [2:0] readys_valid = {auto_anon_out_2_d_valid, auto_anon_out_1_d_valid, auto_anon_out_0_d_valid}; // @[Arbiter.scala:68:51]
reg [2:0] readys_mask; // @[Arbiter.scala:23:23]
wire [2:0] _readys_filter_T_1 = readys_valid & ~readys_mask; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51]
wire [3:0] _GEN = {_readys_filter_T_1[1:0], auto_anon_out_2_d_valid, auto_anon_out_1_d_valid} | {_readys_filter_T_1, auto_anon_out_2_d_valid}; // @[package.scala:262:{43,48}]
wire [2:0] readys_readys = ~({readys_mask[2], _readys_filter_T_1[2] | readys_mask[1], _GEN[3] | readys_mask[0]} & (_GEN[2:0] | {_readys_filter_T_1[2], _GEN[3:2]})); // @[package.scala:262:{43,48}]
wire winner_0 = readys_readys[0] & auto_anon_out_0_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69]
wire winner_1 = readys_readys[1] & auto_anon_out_1_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69]
wire winner_2 = readys_readys[2] & auto_anon_out_2_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69]
wire _in_0_d_valid_T = auto_anon_out_0_d_valid | auto_anon_out_1_d_valid; // @[Arbiter.scala:79:31] |
Generate the Verilog code corresponding to this FIRRTL code module MSHR_6 :
input clock : Clock
input reset : Reset
output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<13>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<3>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<2>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<13>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<3>}}, flip nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}}
regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock
regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}, clock
when meta_valid :
node _T = eq(meta.state, UInt<2>(0h0))
when _T :
node _T_1 = orr(meta.clients)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _T_6 = eq(meta.dirty, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = eq(meta.state, UInt<2>(0h1))
when _T_10 :
node _T_11 = eq(meta.dirty, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2
assert(clock, _T_11, UInt<1>(0h1), "") : assert_2
node _T_15 = eq(meta.state, UInt<2>(0h2))
when _T_15 :
node _T_16 = orr(meta.clients)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3
assert(clock, _T_16, UInt<1>(0h1), "") : assert_3
node _T_20 = sub(meta.clients, UInt<1>(0h1))
node _T_21 = tail(_T_20, 1)
node _T_22 = and(meta.clients, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4
assert(clock, _T_23, UInt<1>(0h1), "") : assert_4
node _T_27 = eq(meta.state, UInt<2>(0h3))
when _T_27 :
skip
regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1)
reg sink : UInt<3>, clock
reg gotT : UInt<1>, clock
reg bad_grant : UInt<1>, clock
reg probes_done : UInt<2>, clock
reg probes_toN : UInt<2>, clock
reg probes_noT : UInt<1>, clock
node _T_28 = neq(meta.state, UInt<2>(0h0))
node _T_29 = and(meta_valid, _T_28)
node _T_30 = eq(io.nestedwb.set, request.set)
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.nestedwb.tag, meta.tag)
node _T_33 = and(_T_31, _T_32)
when _T_33 :
when io.nestedwb.b_clr_dirty :
connect meta.dirty, UInt<1>(0h0)
when io.nestedwb.c_set_dirty :
connect meta.dirty, UInt<1>(0h1)
when io.nestedwb.b_toB :
connect meta.state, UInt<2>(0h1)
when io.nestedwb.b_toN :
connect meta.hit, UInt<1>(0h0)
connect io.status.valid, request_valid
connect io.status.bits.set, request.set
connect io.status.bits.tag, request.tag
connect io.status.bits.way, meta.way
node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0))
node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0))
node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2)
node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4)
node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6)
node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7)
connect io.status.bits.blockB, _io_status_bits_blockB_T_8
node _io_status_bits_nestB_T = and(meta_valid, w_releaseack)
node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast)
node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast)
node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3)
connect io.status.bits.nestB, _io_status_bits_nestB_T_4
node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0))
connect io.status.bits.blockC, _io_status_bits_blockC_T
node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1)
node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3)
node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4)
connect io.status.bits.nestC, _io_status_bits_nestC_T_5
node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0))
node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0))
node _T_36 = or(_T_34, _T_35)
node _T_37 = asUInt(reset)
node _T_38 = eq(_T_37, UInt<1>(0h0))
when _T_38 :
node _T_39 = eq(_T_36, UInt<1>(0h0))
when _T_39 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5
assert(clock, _T_36, UInt<1>(0h1), "") : assert_5
node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0))
node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0))
node _T_42 = or(_T_40, _T_41)
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6
assert(clock, _T_42, UInt<1>(0h1), "") : assert_6
node _no_wait_T = and(w_rprobeacklast, w_releaseack)
node _no_wait_T_1 = and(_no_wait_T, w_grantlast)
node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast)
node no_wait = and(_no_wait_T_2, w_grantack)
node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0))
node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release)
node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe)
connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2
node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1)
connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2
node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst)
node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst)
node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3)
connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4
node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0))
node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack)
node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant)
connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2
node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0))
node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst)
connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1
node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0))
node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack)
connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1
node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst)
node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait)
node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3)
connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4
connect io.schedule.bits.reload, no_wait
node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid)
node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid)
node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid)
node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid)
node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid)
node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid)
connect io.schedule.valid, _io_schedule_valid_T_5
when io.schedule.ready :
connect s_rprobe, UInt<1>(0h1)
when w_rprobeackfirst :
connect s_release, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
node _T_46 = and(s_release, s_pprobe)
when _T_46 :
connect s_acquire, UInt<1>(0h1)
when w_releaseack :
connect s_flush, UInt<1>(0h1)
when w_pprobeackfirst :
connect s_probeack, UInt<1>(0h1)
when w_grantfirst :
connect s_grantack, UInt<1>(0h1)
node _T_47 = and(w_pprobeack, w_grant)
when _T_47 :
connect s_execute, UInt<1>(0h1)
when no_wait :
connect s_writeback, UInt<1>(0h1)
when no_wait :
connect request_valid, UInt<1>(0h0)
connect meta_valid, UInt<1>(0h0)
wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}
connect final_meta_writeback, meta
node _req_clientBit_T = eq(request.source, UInt<6>(0h24))
node _req_clientBit_T_1 = eq(request.source, UInt<6>(0h20))
node req_clientBit = cat(_req_clientBit_T_1, _req_clientBit_T)
node _req_needT_T = bits(request.opcode, 2, 2)
node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0))
node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5))
node _req_needT_T_3 = eq(request.param, UInt<1>(0h1))
node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3)
node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4)
node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6))
node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7))
node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7)
node _req_needT_T_9 = neq(request.param, UInt<2>(0h0))
node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9)
node req_needT = or(_req_needT_T_5, _req_needT_T_10)
node _req_acquire_T = eq(request.opcode, UInt<3>(0h6))
node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7))
node req_acquire = or(_req_acquire_T, _req_acquire_T_1)
node _meta_no_clients_T = orr(meta.clients)
node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0))
node _req_promoteT_T = eq(meta.state, UInt<2>(0h3))
node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T)
node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT)
node req_promoteT = and(req_acquire, _req_promoteT_T_2)
node _T_48 = and(request.prio[2], UInt<1>(0h1))
when _T_48 :
node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0)
node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1
node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3))
node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2))
node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1)
node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state)
connect final_meta_writeback.state, _final_meta_writeback_state_T_3
node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1))
node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2))
node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1)
node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5))
node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3)
node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5)
node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7
connect final_meta_writeback.hit, UInt<1>(0h1)
else :
node _T_49 = and(request.control, UInt<1>(0h1))
when _T_49 :
when meta.hit :
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
node _final_meta_writeback_clients_T_8 = not(probes_toN)
node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9
connect final_meta_writeback.hit, UInt<1>(0h0)
else :
node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty)
node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2)
node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0))
node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5
node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0))
node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1))
node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire)
node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state)
node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1))
node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state)
node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11)
node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state)
node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13)
node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15)
node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16)
connect final_meta_writeback.state, _final_meta_writeback_state_T_17
node _final_meta_writeback_clients_T_10 = not(probes_toN)
node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10)
node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0))
node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14
connect final_meta_writeback.tag, request.tag
connect final_meta_writeback.hit, UInt<1>(0h1)
when bad_grant :
when meta.hit :
node _T_50 = eq(meta_valid, UInt<1>(0h0))
node _T_51 = eq(meta.state, UInt<2>(0h1))
node _T_52 = or(_T_50, _T_51)
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(_T_52, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7
assert(clock, _T_52, UInt<1>(0h1), "") : assert_7
connect final_meta_writeback.hit, UInt<1>(0h1)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h1)
node _final_meta_writeback_clients_T_15 = not(probes_toN)
node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16
else :
connect final_meta_writeback.hit, UInt<1>(0h0)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
connect final_meta_writeback.clients, UInt<1>(0h0)
wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>}
connect invalid.dirty, UInt<1>(0h0)
connect invalid.state, UInt<2>(0h0)
connect invalid.clients, UInt<1>(0h0)
connect invalid.tag, UInt<1>(0h0)
node _honour_BtoT_T = and(meta.clients, req_clientBit)
node _honour_BtoT_T_1 = orr(_honour_BtoT_T)
node honour_BtoT = and(meta.hit, _honour_BtoT_T_1)
node _excluded_client_T = and(meta.hit, request.prio[0])
node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6))
node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7))
node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2)
node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4))
node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4)
node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5))
node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0))
node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7)
node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8)
node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0))
connect io.schedule.bits.a.bits.tag, request.tag
connect io.schedule.bits.a.bits.set, request.set
node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0))
connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1
node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6))
node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7))
node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2)
node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4)
connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5
connect io.schedule.bits.a.bits.source, UInt<1>(0h0)
node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1)
node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2)
connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3
node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag)
connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1
connect io.schedule.bits.b.bits.set, request.set
node _io_schedule_bits_b_bits_clients_T = not(excluded_client)
node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T)
connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1
node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6))
connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T
node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1))
node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1))
connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1
connect io.schedule.bits.c.bits.source, UInt<1>(0h0)
connect io.schedule.bits.c.bits.tag, meta.tag
connect io.schedule.bits.c.bits.set, request.set
connect io.schedule.bits.c.bits.way, meta.way
connect io.schedule.bits.c.bits.dirty, meta.dirty
connect io.schedule.bits.d.bits.set, request.set
connect io.schedule.bits.d.bits.put, request.put
connect io.schedule.bits.d.bits.offset, request.offset
connect io.schedule.bits.d.bits.tag, request.tag
connect io.schedule.bits.d.bits.source, request.source
connect io.schedule.bits.d.bits.size, request.size
connect io.schedule.bits.d.bits.param, request.param
connect io.schedule.bits.d.bits.opcode, request.opcode
connect io.schedule.bits.d.bits.control, request.control
connect io.schedule.bits.d.bits.prio, request.prio
node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0))
node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0))
node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param)
node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param)
node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param)
node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4)
node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param)
node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6)
node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8)
connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9
connect io.schedule.bits.d.bits.sink, UInt<1>(0h0)
connect io.schedule.bits.d.bits.way, meta.way
connect io.schedule.bits.d.bits.bad, bad_grant
connect io.schedule.bits.e.bits.sink, sink
connect io.schedule.bits.x.bits.fail, UInt<1>(0h0)
connect io.schedule.bits.dir.bits.set, request.set
connect io.schedule.bits.dir.bits.way, meta.way
node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0))
wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>}
connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag
connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients
connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state
connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty
node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE)
connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1
node _evict_T = eq(meta.hit, UInt<1>(0h0))
wire evict : UInt
connect evict, UInt<1>(0h0)
node evict_c = orr(meta.clients)
node _evict_T_1 = eq(UInt<2>(0h1), meta.state)
when _evict_T_1 :
node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1))
connect evict, _evict_out_T
else :
node _evict_T_2 = eq(UInt<2>(0h2), meta.state)
when _evict_T_2 :
node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect evict, _evict_out_T_1
else :
node _evict_T_3 = eq(UInt<2>(0h3), meta.state)
when _evict_T_3 :
node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3)
connect evict, _evict_out_T_4
else :
node _evict_T_4 = eq(UInt<2>(0h0), meta.state)
when _evict_T_4 :
connect evict, UInt<4>(0h8)
node _evict_T_5 = eq(_evict_T, UInt<1>(0h0))
when _evict_T_5 :
connect evict, UInt<4>(0h8)
wire before : UInt
connect before, UInt<1>(0h0)
node before_c = orr(meta.clients)
node _before_T = eq(UInt<2>(0h1), meta.state)
when _before_T :
node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1))
connect before, _before_out_T
else :
node _before_T_1 = eq(UInt<2>(0h2), meta.state)
when _before_T_1 :
node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect before, _before_out_T_1
else :
node _before_T_2 = eq(UInt<2>(0h3), meta.state)
when _before_T_2 :
node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3)
connect before, _before_out_T_4
else :
node _before_T_3 = eq(UInt<2>(0h0), meta.state)
when _before_T_3 :
connect before, UInt<4>(0h8)
node _before_T_4 = eq(meta.hit, UInt<1>(0h0))
when _before_T_4 :
connect before, UInt<4>(0h8)
wire after : UInt
connect after, UInt<1>(0h0)
node after_c = orr(final_meta_writeback.clients)
node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _after_T :
node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1))
connect after, _after_out_T
else :
node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _after_T_1 :
node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect after, _after_out_T_1
else :
node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _after_T_2 :
node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3)
connect after, _after_out_T_4
else :
node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _after_T_3 :
connect after, UInt<4>(0h8)
node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _after_T_4 :
connect after, UInt<4>(0h8)
node _T_56 = eq(s_release, UInt<1>(0h0))
node _T_57 = and(_T_56, w_rprobeackfirst)
node _T_58 = and(_T_57, io.schedule.ready)
when _T_58 :
node _T_59 = eq(evict, UInt<1>(0h1))
node _T_60 = eq(_T_59, UInt<1>(0h0))
node _T_61 = asUInt(reset)
node _T_62 = eq(_T_61, UInt<1>(0h0))
when _T_62 :
node _T_63 = eq(_T_60, UInt<1>(0h0))
when _T_63 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8
assert(clock, _T_60, UInt<1>(0h1), "") : assert_8
node _T_64 = eq(before, UInt<1>(0h1))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9
assert(clock, _T_65, UInt<1>(0h1), "") : assert_9
node _T_69 = eq(evict, UInt<1>(0h0))
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_T_70, UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10
assert(clock, _T_70, UInt<1>(0h1), "") : assert_10
node _T_74 = eq(before, UInt<1>(0h0))
node _T_75 = eq(_T_74, UInt<1>(0h0))
node _T_76 = asUInt(reset)
node _T_77 = eq(_T_76, UInt<1>(0h0))
when _T_77 :
node _T_78 = eq(_T_75, UInt<1>(0h0))
when _T_78 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11
assert(clock, _T_75, UInt<1>(0h1), "") : assert_11
node _T_79 = eq(evict, UInt<3>(0h7))
node _T_80 = eq(before, UInt<3>(0h7))
node _T_81 = eq(evict, UInt<3>(0h5))
node _T_82 = eq(before, UInt<3>(0h5))
node _T_83 = eq(evict, UInt<3>(0h4))
node _T_84 = eq(before, UInt<3>(0h4))
node _T_85 = eq(evict, UInt<3>(0h6))
node _T_86 = eq(before, UInt<3>(0h6))
node _T_87 = eq(evict, UInt<2>(0h3))
node _T_88 = eq(before, UInt<2>(0h3))
node _T_89 = eq(evict, UInt<2>(0h2))
node _T_90 = eq(before, UInt<2>(0h2))
node _T_91 = eq(s_writeback, UInt<1>(0h0))
node _T_92 = and(_T_91, no_wait)
node _T_93 = and(_T_92, io.schedule.ready)
when _T_93 :
node _T_94 = eq(before, UInt<4>(0h8))
node _T_95 = eq(after, UInt<1>(0h1))
node _T_96 = and(_T_94, _T_95)
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = asUInt(reset)
node _T_99 = eq(_T_98, UInt<1>(0h0))
when _T_99 :
node _T_100 = eq(_T_97, UInt<1>(0h0))
when _T_100 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12
assert(clock, _T_97, UInt<1>(0h1), "") : assert_12
node _T_101 = eq(before, UInt<4>(0h8))
node _T_102 = eq(after, UInt<1>(0h0))
node _T_103 = and(_T_101, _T_102)
node _T_104 = eq(_T_103, UInt<1>(0h0))
node _T_105 = asUInt(reset)
node _T_106 = eq(_T_105, UInt<1>(0h0))
when _T_106 :
node _T_107 = eq(_T_104, UInt<1>(0h0))
when _T_107 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13
assert(clock, _T_104, UInt<1>(0h1), "") : assert_13
node _T_108 = eq(before, UInt<4>(0h8))
node _T_109 = eq(after, UInt<3>(0h7))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(before, UInt<4>(0h8))
node _T_112 = eq(after, UInt<3>(0h5))
node _T_113 = and(_T_111, _T_112)
node _T_114 = eq(_T_113, UInt<1>(0h0))
node _T_115 = asUInt(reset)
node _T_116 = eq(_T_115, UInt<1>(0h0))
when _T_116 :
node _T_117 = eq(_T_114, UInt<1>(0h0))
when _T_117 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14
assert(clock, _T_114, UInt<1>(0h1), "") : assert_14
node _T_118 = eq(before, UInt<4>(0h8))
node _T_119 = eq(after, UInt<3>(0h4))
node _T_120 = and(_T_118, _T_119)
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15
assert(clock, _T_121, UInt<1>(0h1), "") : assert_15
node _T_125 = eq(before, UInt<4>(0h8))
node _T_126 = eq(after, UInt<3>(0h6))
node _T_127 = and(_T_125, _T_126)
node _T_128 = eq(before, UInt<4>(0h8))
node _T_129 = eq(after, UInt<2>(0h3))
node _T_130 = and(_T_128, _T_129)
node _T_131 = eq(before, UInt<4>(0h8))
node _T_132 = eq(after, UInt<2>(0h2))
node _T_133 = and(_T_131, _T_132)
node _T_134 = eq(_T_133, UInt<1>(0h0))
node _T_135 = asUInt(reset)
node _T_136 = eq(_T_135, UInt<1>(0h0))
when _T_136 :
node _T_137 = eq(_T_134, UInt<1>(0h0))
when _T_137 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16
assert(clock, _T_134, UInt<1>(0h1), "") : assert_16
node _T_138 = eq(before, UInt<1>(0h1))
node _T_139 = eq(after, UInt<4>(0h8))
node _T_140 = and(_T_138, _T_139)
node _T_141 = eq(_T_140, UInt<1>(0h0))
node _T_142 = asUInt(reset)
node _T_143 = eq(_T_142, UInt<1>(0h0))
when _T_143 :
node _T_144 = eq(_T_141, UInt<1>(0h0))
when _T_144 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17
assert(clock, _T_141, UInt<1>(0h1), "") : assert_17
node _T_145 = eq(before, UInt<1>(0h1))
node _T_146 = eq(after, UInt<1>(0h0))
node _T_147 = and(_T_145, _T_146)
node _T_148 = eq(_T_147, UInt<1>(0h0))
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_T_148, UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18
assert(clock, _T_148, UInt<1>(0h1), "") : assert_18
node _T_152 = eq(before, UInt<1>(0h1))
node _T_153 = eq(after, UInt<3>(0h7))
node _T_154 = and(_T_152, _T_153)
node _T_155 = eq(_T_154, UInt<1>(0h0))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19
assert(clock, _T_155, UInt<1>(0h1), "") : assert_19
node _T_159 = eq(before, UInt<1>(0h1))
node _T_160 = eq(after, UInt<3>(0h5))
node _T_161 = and(_T_159, _T_160)
node _T_162 = eq(_T_161, UInt<1>(0h0))
node _T_163 = asUInt(reset)
node _T_164 = eq(_T_163, UInt<1>(0h0))
when _T_164 :
node _T_165 = eq(_T_162, UInt<1>(0h0))
when _T_165 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20
assert(clock, _T_162, UInt<1>(0h1), "") : assert_20
node _T_166 = eq(before, UInt<1>(0h1))
node _T_167 = eq(after, UInt<3>(0h4))
node _T_168 = and(_T_166, _T_167)
node _T_169 = eq(_T_168, UInt<1>(0h0))
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_T_169, UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21
assert(clock, _T_169, UInt<1>(0h1), "") : assert_21
node _T_173 = eq(before, UInt<1>(0h1))
node _T_174 = eq(after, UInt<3>(0h6))
node _T_175 = and(_T_173, _T_174)
node _T_176 = eq(_T_175, UInt<1>(0h0))
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_T_176, UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22
assert(clock, _T_176, UInt<1>(0h1), "") : assert_22
node _T_180 = eq(before, UInt<1>(0h1))
node _T_181 = eq(after, UInt<2>(0h3))
node _T_182 = and(_T_180, _T_181)
node _T_183 = eq(_T_182, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(before, UInt<1>(0h1))
node _T_188 = eq(after, UInt<2>(0h2))
node _T_189 = and(_T_187, _T_188)
node _T_190 = eq(_T_189, UInt<1>(0h0))
node _T_191 = asUInt(reset)
node _T_192 = eq(_T_191, UInt<1>(0h0))
when _T_192 :
node _T_193 = eq(_T_190, UInt<1>(0h0))
when _T_193 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24
assert(clock, _T_190, UInt<1>(0h1), "") : assert_24
node _T_194 = eq(before, UInt<1>(0h0))
node _T_195 = eq(after, UInt<4>(0h8))
node _T_196 = and(_T_194, _T_195)
node _T_197 = eq(_T_196, UInt<1>(0h0))
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(_T_197, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25
assert(clock, _T_197, UInt<1>(0h1), "") : assert_25
node _T_201 = eq(before, UInt<1>(0h0))
node _T_202 = eq(after, UInt<1>(0h1))
node _T_203 = and(_T_201, _T_202)
node _T_204 = eq(_T_203, UInt<1>(0h0))
node _T_205 = asUInt(reset)
node _T_206 = eq(_T_205, UInt<1>(0h0))
when _T_206 :
node _T_207 = eq(_T_204, UInt<1>(0h0))
when _T_207 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26
assert(clock, _T_204, UInt<1>(0h1), "") : assert_26
node _T_208 = eq(before, UInt<1>(0h0))
node _T_209 = eq(after, UInt<3>(0h7))
node _T_210 = and(_T_208, _T_209)
node _T_211 = eq(_T_210, UInt<1>(0h0))
node _T_212 = asUInt(reset)
node _T_213 = eq(_T_212, UInt<1>(0h0))
when _T_213 :
node _T_214 = eq(_T_211, UInt<1>(0h0))
when _T_214 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27
assert(clock, _T_211, UInt<1>(0h1), "") : assert_27
node _T_215 = eq(before, UInt<1>(0h0))
node _T_216 = eq(after, UInt<3>(0h5))
node _T_217 = and(_T_215, _T_216)
node _T_218 = eq(_T_217, UInt<1>(0h0))
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28
assert(clock, _T_218, UInt<1>(0h1), "") : assert_28
node _T_222 = eq(before, UInt<1>(0h0))
node _T_223 = eq(after, UInt<3>(0h6))
node _T_224 = and(_T_222, _T_223)
node _T_225 = eq(_T_224, UInt<1>(0h0))
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_T_225, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29
assert(clock, _T_225, UInt<1>(0h1), "") : assert_29
node _T_229 = eq(before, UInt<1>(0h0))
node _T_230 = eq(after, UInt<3>(0h4))
node _T_231 = and(_T_229, _T_230)
node _T_232 = eq(_T_231, UInt<1>(0h0))
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(before, UInt<1>(0h0))
node _T_237 = eq(after, UInt<2>(0h3))
node _T_238 = and(_T_236, _T_237)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31
assert(clock, _T_239, UInt<1>(0h1), "") : assert_31
node _T_243 = eq(before, UInt<1>(0h0))
node _T_244 = eq(after, UInt<2>(0h2))
node _T_245 = and(_T_243, _T_244)
node _T_246 = eq(_T_245, UInt<1>(0h0))
node _T_247 = asUInt(reset)
node _T_248 = eq(_T_247, UInt<1>(0h0))
when _T_248 :
node _T_249 = eq(_T_246, UInt<1>(0h0))
when _T_249 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32
assert(clock, _T_246, UInt<1>(0h1), "") : assert_32
node _T_250 = eq(before, UInt<3>(0h7))
node _T_251 = eq(after, UInt<4>(0h8))
node _T_252 = and(_T_250, _T_251)
node _T_253 = eq(_T_252, UInt<1>(0h0))
node _T_254 = asUInt(reset)
node _T_255 = eq(_T_254, UInt<1>(0h0))
when _T_255 :
node _T_256 = eq(_T_253, UInt<1>(0h0))
when _T_256 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33
assert(clock, _T_253, UInt<1>(0h1), "") : assert_33
node _T_257 = eq(before, UInt<3>(0h7))
node _T_258 = eq(after, UInt<1>(0h1))
node _T_259 = and(_T_257, _T_258)
node _T_260 = eq(_T_259, UInt<1>(0h0))
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(_T_260, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34
assert(clock, _T_260, UInt<1>(0h1), "") : assert_34
node _T_264 = eq(before, UInt<3>(0h7))
node _T_265 = eq(after, UInt<1>(0h0))
node _T_266 = and(_T_264, _T_265)
node _T_267 = eq(_T_266, UInt<1>(0h0))
node _T_268 = asUInt(reset)
node _T_269 = eq(_T_268, UInt<1>(0h0))
when _T_269 :
node _T_270 = eq(_T_267, UInt<1>(0h0))
when _T_270 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35
assert(clock, _T_267, UInt<1>(0h1), "") : assert_35
node _T_271 = eq(before, UInt<3>(0h7))
node _T_272 = eq(after, UInt<3>(0h5))
node _T_273 = and(_T_271, _T_272)
node _T_274 = eq(_T_273, UInt<1>(0h0))
node _T_275 = asUInt(reset)
node _T_276 = eq(_T_275, UInt<1>(0h0))
when _T_276 :
node _T_277 = eq(_T_274, UInt<1>(0h0))
when _T_277 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36
assert(clock, _T_274, UInt<1>(0h1), "") : assert_36
node _T_278 = eq(before, UInt<3>(0h7))
node _T_279 = eq(after, UInt<3>(0h6))
node _T_280 = and(_T_278, _T_279)
node _T_281 = eq(before, UInt<3>(0h7))
node _T_282 = eq(after, UInt<3>(0h4))
node _T_283 = and(_T_281, _T_282)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(_T_284, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37
assert(clock, _T_284, UInt<1>(0h1), "") : assert_37
node _T_288 = eq(before, UInt<3>(0h7))
node _T_289 = eq(after, UInt<2>(0h3))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(before, UInt<3>(0h7))
node _T_292 = eq(after, UInt<2>(0h2))
node _T_293 = and(_T_291, _T_292)
node _T_294 = eq(_T_293, UInt<1>(0h0))
node _T_295 = asUInt(reset)
node _T_296 = eq(_T_295, UInt<1>(0h0))
when _T_296 :
node _T_297 = eq(_T_294, UInt<1>(0h0))
when _T_297 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38
assert(clock, _T_294, UInt<1>(0h1), "") : assert_38
node _T_298 = eq(before, UInt<3>(0h5))
node _T_299 = eq(after, UInt<4>(0h8))
node _T_300 = and(_T_298, _T_299)
node _T_301 = eq(_T_300, UInt<1>(0h0))
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39
assert(clock, _T_301, UInt<1>(0h1), "") : assert_39
node _T_305 = eq(before, UInt<3>(0h5))
node _T_306 = eq(after, UInt<1>(0h1))
node _T_307 = and(_T_305, _T_306)
node _T_308 = eq(_T_307, UInt<1>(0h0))
node _T_309 = asUInt(reset)
node _T_310 = eq(_T_309, UInt<1>(0h0))
when _T_310 :
node _T_311 = eq(_T_308, UInt<1>(0h0))
when _T_311 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40
assert(clock, _T_308, UInt<1>(0h1), "") : assert_40
node _T_312 = eq(before, UInt<3>(0h5))
node _T_313 = eq(after, UInt<1>(0h0))
node _T_314 = and(_T_312, _T_313)
node _T_315 = eq(_T_314, UInt<1>(0h0))
node _T_316 = asUInt(reset)
node _T_317 = eq(_T_316, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(_T_315, UInt<1>(0h0))
when _T_318 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41
assert(clock, _T_315, UInt<1>(0h1), "") : assert_41
node _T_319 = eq(before, UInt<3>(0h5))
node _T_320 = eq(after, UInt<3>(0h7))
node _T_321 = and(_T_319, _T_320)
node _T_322 = eq(before, UInt<3>(0h5))
node _T_323 = eq(after, UInt<3>(0h6))
node _T_324 = and(_T_322, _T_323)
node _T_325 = eq(before, UInt<3>(0h5))
node _T_326 = eq(after, UInt<3>(0h4))
node _T_327 = and(_T_325, _T_326)
node _T_328 = eq(_T_327, UInt<1>(0h0))
node _T_329 = asUInt(reset)
node _T_330 = eq(_T_329, UInt<1>(0h0))
when _T_330 :
node _T_331 = eq(_T_328, UInt<1>(0h0))
when _T_331 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42
assert(clock, _T_328, UInt<1>(0h1), "") : assert_42
node _T_332 = eq(before, UInt<3>(0h5))
node _T_333 = eq(after, UInt<2>(0h3))
node _T_334 = and(_T_332, _T_333)
node _T_335 = eq(before, UInt<3>(0h5))
node _T_336 = eq(after, UInt<2>(0h2))
node _T_337 = and(_T_335, _T_336)
node _T_338 = eq(_T_337, UInt<1>(0h0))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43
assert(clock, _T_338, UInt<1>(0h1), "") : assert_43
node _T_342 = eq(before, UInt<3>(0h6))
node _T_343 = eq(after, UInt<4>(0h8))
node _T_344 = and(_T_342, _T_343)
node _T_345 = eq(_T_344, UInt<1>(0h0))
node _T_346 = asUInt(reset)
node _T_347 = eq(_T_346, UInt<1>(0h0))
when _T_347 :
node _T_348 = eq(_T_345, UInt<1>(0h0))
when _T_348 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44
assert(clock, _T_345, UInt<1>(0h1), "") : assert_44
node _T_349 = eq(before, UInt<3>(0h6))
node _T_350 = eq(after, UInt<1>(0h1))
node _T_351 = and(_T_349, _T_350)
node _T_352 = eq(_T_351, UInt<1>(0h0))
node _T_353 = asUInt(reset)
node _T_354 = eq(_T_353, UInt<1>(0h0))
when _T_354 :
node _T_355 = eq(_T_352, UInt<1>(0h0))
when _T_355 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45
assert(clock, _T_352, UInt<1>(0h1), "") : assert_45
node _T_356 = eq(before, UInt<3>(0h6))
node _T_357 = eq(after, UInt<1>(0h0))
node _T_358 = and(_T_356, _T_357)
node _T_359 = eq(_T_358, UInt<1>(0h0))
node _T_360 = asUInt(reset)
node _T_361 = eq(_T_360, UInt<1>(0h0))
when _T_361 :
node _T_362 = eq(_T_359, UInt<1>(0h0))
when _T_362 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46
assert(clock, _T_359, UInt<1>(0h1), "") : assert_46
node _T_363 = eq(before, UInt<3>(0h6))
node _T_364 = eq(after, UInt<3>(0h7))
node _T_365 = and(_T_363, _T_364)
node _T_366 = eq(_T_365, UInt<1>(0h0))
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_T_366, UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47
assert(clock, _T_366, UInt<1>(0h1), "") : assert_47
node _T_370 = eq(before, UInt<3>(0h6))
node _T_371 = eq(after, UInt<3>(0h5))
node _T_372 = and(_T_370, _T_371)
node _T_373 = eq(_T_372, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48
assert(clock, _T_373, UInt<1>(0h1), "") : assert_48
node _T_377 = eq(before, UInt<3>(0h6))
node _T_378 = eq(after, UInt<3>(0h4))
node _T_379 = and(_T_377, _T_378)
node _T_380 = eq(_T_379, UInt<1>(0h0))
node _T_381 = asUInt(reset)
node _T_382 = eq(_T_381, UInt<1>(0h0))
when _T_382 :
node _T_383 = eq(_T_380, UInt<1>(0h0))
when _T_383 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49
assert(clock, _T_380, UInt<1>(0h1), "") : assert_49
node _T_384 = eq(before, UInt<3>(0h6))
node _T_385 = eq(after, UInt<2>(0h3))
node _T_386 = and(_T_384, _T_385)
node _T_387 = eq(_T_386, UInt<1>(0h0))
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(_T_387, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50
assert(clock, _T_387, UInt<1>(0h1), "") : assert_50
node _T_391 = eq(before, UInt<3>(0h6))
node _T_392 = eq(after, UInt<2>(0h2))
node _T_393 = and(_T_391, _T_392)
node _T_394 = eq(before, UInt<3>(0h4))
node _T_395 = eq(after, UInt<4>(0h8))
node _T_396 = and(_T_394, _T_395)
node _T_397 = eq(_T_396, UInt<1>(0h0))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51
assert(clock, _T_397, UInt<1>(0h1), "") : assert_51
node _T_401 = eq(before, UInt<3>(0h4))
node _T_402 = eq(after, UInt<1>(0h1))
node _T_403 = and(_T_401, _T_402)
node _T_404 = eq(_T_403, UInt<1>(0h0))
node _T_405 = asUInt(reset)
node _T_406 = eq(_T_405, UInt<1>(0h0))
when _T_406 :
node _T_407 = eq(_T_404, UInt<1>(0h0))
when _T_407 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52
assert(clock, _T_404, UInt<1>(0h1), "") : assert_52
node _T_408 = eq(before, UInt<3>(0h4))
node _T_409 = eq(after, UInt<1>(0h0))
node _T_410 = and(_T_408, _T_409)
node _T_411 = eq(_T_410, UInt<1>(0h0))
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53
assert(clock, _T_411, UInt<1>(0h1), "") : assert_53
node _T_415 = eq(before, UInt<3>(0h4))
node _T_416 = eq(after, UInt<3>(0h7))
node _T_417 = and(_T_415, _T_416)
node _T_418 = eq(_T_417, UInt<1>(0h0))
node _T_419 = asUInt(reset)
node _T_420 = eq(_T_419, UInt<1>(0h0))
when _T_420 :
node _T_421 = eq(_T_418, UInt<1>(0h0))
when _T_421 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54
assert(clock, _T_418, UInt<1>(0h1), "") : assert_54
node _T_422 = eq(before, UInt<3>(0h4))
node _T_423 = eq(after, UInt<3>(0h5))
node _T_424 = and(_T_422, _T_423)
node _T_425 = eq(_T_424, UInt<1>(0h0))
node _T_426 = asUInt(reset)
node _T_427 = eq(_T_426, UInt<1>(0h0))
when _T_427 :
node _T_428 = eq(_T_425, UInt<1>(0h0))
when _T_428 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55
assert(clock, _T_425, UInt<1>(0h1), "") : assert_55
node _T_429 = eq(before, UInt<3>(0h4))
node _T_430 = eq(after, UInt<3>(0h6))
node _T_431 = and(_T_429, _T_430)
node _T_432 = eq(before, UInt<3>(0h4))
node _T_433 = eq(after, UInt<2>(0h3))
node _T_434 = and(_T_432, _T_433)
node _T_435 = eq(_T_434, UInt<1>(0h0))
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56
assert(clock, _T_435, UInt<1>(0h1), "") : assert_56
node _T_439 = eq(before, UInt<3>(0h4))
node _T_440 = eq(after, UInt<2>(0h2))
node _T_441 = and(_T_439, _T_440)
node _T_442 = eq(before, UInt<2>(0h3))
node _T_443 = eq(after, UInt<4>(0h8))
node _T_444 = and(_T_442, _T_443)
node _T_445 = eq(_T_444, UInt<1>(0h0))
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57
assert(clock, _T_445, UInt<1>(0h1), "") : assert_57
node _T_449 = eq(before, UInt<2>(0h3))
node _T_450 = eq(after, UInt<1>(0h1))
node _T_451 = and(_T_449, _T_450)
node _T_452 = eq(_T_451, UInt<1>(0h0))
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(_T_452, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58
assert(clock, _T_452, UInt<1>(0h1), "") : assert_58
node _T_456 = eq(before, UInt<2>(0h3))
node _T_457 = eq(after, UInt<1>(0h0))
node _T_458 = and(_T_456, _T_457)
node _T_459 = eq(_T_458, UInt<1>(0h0))
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59
assert(clock, _T_459, UInt<1>(0h1), "") : assert_59
node _T_463 = eq(before, UInt<2>(0h3))
node _T_464 = eq(after, UInt<3>(0h7))
node _T_465 = and(_T_463, _T_464)
node _T_466 = eq(before, UInt<2>(0h3))
node _T_467 = eq(after, UInt<3>(0h5))
node _T_468 = and(_T_466, _T_467)
node _T_469 = eq(before, UInt<2>(0h3))
node _T_470 = eq(after, UInt<3>(0h6))
node _T_471 = and(_T_469, _T_470)
node _T_472 = eq(before, UInt<2>(0h3))
node _T_473 = eq(after, UInt<3>(0h4))
node _T_474 = and(_T_472, _T_473)
node _T_475 = eq(before, UInt<2>(0h3))
node _T_476 = eq(after, UInt<2>(0h2))
node _T_477 = and(_T_475, _T_476)
node _T_478 = eq(before, UInt<2>(0h2))
node _T_479 = eq(after, UInt<4>(0h8))
node _T_480 = and(_T_478, _T_479)
node _T_481 = eq(_T_480, UInt<1>(0h0))
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_T_481, UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60
assert(clock, _T_481, UInt<1>(0h1), "") : assert_60
node _T_485 = eq(before, UInt<2>(0h2))
node _T_486 = eq(after, UInt<1>(0h1))
node _T_487 = and(_T_485, _T_486)
node _T_488 = eq(_T_487, UInt<1>(0h0))
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61
assert(clock, _T_488, UInt<1>(0h1), "") : assert_61
node _T_492 = eq(before, UInt<2>(0h2))
node _T_493 = eq(after, UInt<1>(0h0))
node _T_494 = and(_T_492, _T_493)
node _T_495 = eq(_T_494, UInt<1>(0h0))
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_T_495, UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62
assert(clock, _T_495, UInt<1>(0h1), "") : assert_62
node _T_499 = eq(before, UInt<2>(0h2))
node _T_500 = eq(after, UInt<3>(0h7))
node _T_501 = and(_T_499, _T_500)
node _T_502 = eq(_T_501, UInt<1>(0h0))
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63
assert(clock, _T_502, UInt<1>(0h1), "") : assert_63
node _T_506 = eq(before, UInt<2>(0h2))
node _T_507 = eq(after, UInt<3>(0h5))
node _T_508 = and(_T_506, _T_507)
node _T_509 = eq(_T_508, UInt<1>(0h0))
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64
assert(clock, _T_509, UInt<1>(0h1), "") : assert_64
node _T_513 = eq(before, UInt<2>(0h2))
node _T_514 = eq(after, UInt<3>(0h6))
node _T_515 = and(_T_513, _T_514)
node _T_516 = eq(before, UInt<2>(0h2))
node _T_517 = eq(after, UInt<3>(0h4))
node _T_518 = and(_T_516, _T_517)
node _T_519 = eq(before, UInt<2>(0h2))
node _T_520 = eq(after, UInt<2>(0h3))
node _T_521 = and(_T_519, _T_520)
node _T_522 = eq(_T_521, UInt<1>(0h0))
node _T_523 = asUInt(reset)
node _T_524 = eq(_T_523, UInt<1>(0h0))
when _T_524 :
node _T_525 = eq(_T_522, UInt<1>(0h0))
when _T_525 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65
assert(clock, _T_522, UInt<1>(0h1), "") : assert_65
node _probe_bit_T = eq(io.sinkc.bits.source, UInt<6>(0h24))
node _probe_bit_T_1 = eq(io.sinkc.bits.source, UInt<6>(0h20))
node probe_bit = cat(_probe_bit_T_1, _probe_bit_T)
node _last_probe_T = or(probes_done, probe_bit)
node _last_probe_T_1 = not(excluded_client)
node _last_probe_T_2 = and(meta.clients, _last_probe_T_1)
node last_probe = eq(_last_probe_T, _last_probe_T_2)
node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1))
node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2))
node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1)
node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5))
node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3)
when io.sinkc.valid :
node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_527 = and(probe_toN, _T_526)
node _T_528 = eq(probe_toN, UInt<1>(0h0))
node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_530 = and(_T_528, _T_529)
node _probes_done_T = or(probes_done, probe_bit)
connect probes_done, _probes_done_T
node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0))
node _probes_toN_T_1 = or(probes_toN, _probes_toN_T)
connect probes_toN, _probes_toN_T_1
node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3))
node _probes_noT_T_1 = or(probes_noT, _probes_noT_T)
connect probes_noT, _probes_noT_T_1
node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe)
connect w_rprobeackfirst, _w_rprobeackfirst_T
node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T)
connect w_rprobeacklast, _w_rprobeacklast_T_1
node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe)
connect w_pprobeackfirst, _w_pprobeackfirst_T
node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T)
connect w_pprobeacklast, _w_pprobeacklast_T_1
node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0))
node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T)
node set_pprobeack = and(last_probe, _set_pprobeack_T_1)
node _w_pprobeack_T = or(w_pprobeack, set_pprobeack)
connect w_pprobeack, _w_pprobeack_T
node _T_531 = eq(set_pprobeack, UInt<1>(0h0))
node _T_532 = and(_T_531, w_rprobeackfirst)
node _T_533 = and(set_pprobeack, w_rprobeackfirst)
node _T_534 = neq(meta.state, UInt<2>(0h0))
node _T_535 = eq(io.sinkc.bits.tag, meta.tag)
node _T_536 = and(_T_534, _T_535)
node _T_537 = and(_T_536, io.sinkc.bits.data)
when _T_537 :
connect meta.dirty, UInt<1>(0h1)
when io.sinkd.valid :
node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4))
node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_540 = or(_T_538, _T_539)
when _T_540 :
connect sink, io.sinkd.bits.sink
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, io.sinkd.bits.last
connect bad_grant, io.sinkd.bits.denied
node _w_grant_T = eq(request.offset, UInt<1>(0h0))
node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last)
connect w_grant, _w_grant_T_1
node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_542 = eq(request.offset, UInt<1>(0h0))
node _T_543 = and(_T_541, _T_542)
node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_545 = neq(request.offset, UInt<1>(0h0))
node _T_546 = and(_T_544, _T_545)
node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0))
connect gotT, _gotT_T
else :
node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6))
when _T_547 :
connect w_releaseack, UInt<1>(0h1)
when io.sinke.valid :
connect w_grantack, UInt<1>(0h1)
wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}
connect allocate_as_full.set, io.allocate.bits.set
connect allocate_as_full.put, io.allocate.bits.put
connect allocate_as_full.offset, io.allocate.bits.offset
connect allocate_as_full.tag, io.allocate.bits.tag
connect allocate_as_full.source, io.allocate.bits.source
connect allocate_as_full.size, io.allocate.bits.size
connect allocate_as_full.param, io.allocate.bits.param
connect allocate_as_full.opcode, io.allocate.bits.opcode
connect allocate_as_full.control, io.allocate.bits.control
connect allocate_as_full.prio, io.allocate.bits.prio
node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat)
node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits)
node new_request = mux(io.allocate.valid, allocate_as_full, request)
node _new_needT_T = bits(new_request.opcode, 2, 2)
node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0))
node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5))
node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1))
node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3)
node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4)
node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6))
node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7))
node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7)
node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0))
node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9)
node new_needT = or(_new_needT_T_5, _new_needT_T_10)
node _new_clientBit_T = eq(new_request.source, UInt<6>(0h24))
node _new_clientBit_T_1 = eq(new_request.source, UInt<6>(0h20))
node new_clientBit = cat(_new_clientBit_T_1, _new_clientBit_T)
node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6))
node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7))
node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1)
node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4))
node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3)
node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5))
node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0))
node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6)
node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0))
wire prior : UInt
connect prior, UInt<1>(0h0)
node prior_c = orr(final_meta_writeback.clients)
node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _prior_T :
node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1))
connect prior, _prior_out_T
else :
node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _prior_T_1 :
node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect prior, _prior_out_T_1
else :
node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _prior_T_2 :
node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3)
connect prior, _prior_out_T_4
else :
node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _prior_T_3 :
connect prior, UInt<4>(0h8)
node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _prior_T_4 :
connect prior, UInt<4>(0h8)
node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat)
when _T_548 :
node _T_549 = eq(prior, UInt<4>(0h8))
node _T_550 = eq(prior, UInt<1>(0h1))
node _T_551 = eq(_T_550, UInt<1>(0h0))
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66
assert(clock, _T_551, UInt<1>(0h1), "") : assert_66
node _T_555 = eq(prior, UInt<1>(0h0))
node _T_556 = eq(_T_555, UInt<1>(0h0))
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67
assert(clock, _T_556, UInt<1>(0h1), "") : assert_67
node _T_560 = eq(prior, UInt<3>(0h7))
node _T_561 = eq(prior, UInt<3>(0h5))
node _T_562 = eq(prior, UInt<3>(0h4))
node _T_563 = eq(prior, UInt<3>(0h6))
node _T_564 = eq(prior, UInt<2>(0h3))
node _T_565 = eq(prior, UInt<2>(0h2))
when io.allocate.valid :
node _T_566 = eq(request_valid, UInt<1>(0h0))
node _T_567 = and(io.schedule.ready, io.schedule.valid)
node _T_568 = and(no_wait, _T_567)
node _T_569 = or(_T_566, _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68
assert(clock, _T_569, UInt<1>(0h1), "") : assert_68
connect request_valid, UInt<1>(0h1)
connect request.set, io.allocate.bits.set
connect request.put, io.allocate.bits.put
connect request.offset, io.allocate.bits.offset
connect request.tag, io.allocate.bits.tag
connect request.source, io.allocate.bits.source
connect request.size, io.allocate.bits.size
connect request.param, io.allocate.bits.param
connect request.opcode, io.allocate.bits.opcode
connect request.control, io.allocate.bits.control
connect request.prio, io.allocate.bits.prio
node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat)
node _T_574 = or(io.directory.valid, _T_573)
when _T_574 :
connect meta_valid, UInt<1>(0h1)
connect meta, new_meta
connect probes_done, UInt<1>(0h0)
connect probes_toN, UInt<1>(0h0)
connect probes_noT, UInt<1>(0h0)
connect gotT, UInt<1>(0h0)
connect bad_grant, UInt<1>(0h0)
connect s_rprobe, UInt<1>(0h1)
connect w_rprobeackfirst, UInt<1>(0h1)
connect w_rprobeacklast, UInt<1>(0h1)
connect s_release, UInt<1>(0h1)
connect w_releaseack, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
connect s_acquire, UInt<1>(0h1)
connect s_flush, UInt<1>(0h1)
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, UInt<1>(0h1)
connect w_grant, UInt<1>(0h1)
connect w_pprobeackfirst, UInt<1>(0h1)
connect w_pprobeacklast, UInt<1>(0h1)
connect w_pprobeack, UInt<1>(0h1)
connect s_probeack, UInt<1>(0h1)
connect s_grantack, UInt<1>(0h1)
connect s_execute, UInt<1>(0h1)
connect w_grantack, UInt<1>(0h1)
connect s_writeback, UInt<1>(0h1)
node _T_575 = and(new_request.prio[2], UInt<1>(0h1))
when _T_575 :
connect s_execute, UInt<1>(0h0)
node _T_576 = bits(new_request.opcode, 0, 0)
node _T_577 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_578 = and(_T_576, _T_577)
when _T_578 :
connect s_writeback, UInt<1>(0h0)
node _T_579 = eq(new_request.param, UInt<3>(0h0))
node _T_580 = eq(new_request.param, UInt<3>(0h4))
node _T_581 = or(_T_579, _T_580)
node _T_582 = eq(new_meta.state, UInt<2>(0h2))
node _T_583 = and(_T_581, _T_582)
when _T_583 :
connect s_writeback, UInt<1>(0h0)
node _T_584 = eq(new_request.param, UInt<3>(0h1))
node _T_585 = eq(new_request.param, UInt<3>(0h2))
node _T_586 = or(_T_584, _T_585)
node _T_587 = eq(new_request.param, UInt<3>(0h5))
node _T_588 = or(_T_586, _T_587)
node _T_589 = and(new_meta.clients, new_clientBit)
node _T_590 = neq(_T_589, UInt<1>(0h0))
node _T_591 = and(_T_588, _T_590)
when _T_591 :
connect s_writeback, UInt<1>(0h0)
node _T_592 = asUInt(reset)
node _T_593 = eq(_T_592, UInt<1>(0h0))
when _T_593 :
node _T_594 = eq(new_meta.hit, UInt<1>(0h0))
when _T_594 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69
assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69
else :
node _T_595 = and(new_request.control, UInt<1>(0h1))
when _T_595 :
connect s_flush, UInt<1>(0h0)
when new_meta.hit :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_596 = neq(new_meta.clients, UInt<1>(0h0))
node _T_597 = and(UInt<1>(0h1), _T_596)
when _T_597 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
else :
connect s_execute, UInt<1>(0h0)
node _T_598 = eq(new_meta.hit, UInt<1>(0h0))
node _T_599 = neq(new_meta.state, UInt<2>(0h0))
node _T_600 = and(_T_598, _T_599)
when _T_600 :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_601 = neq(new_meta.clients, UInt<1>(0h0))
node _T_602 = and(UInt<1>(0h1), _T_601)
when _T_602 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
node _T_603 = eq(new_meta.hit, UInt<1>(0h0))
node _T_604 = eq(new_meta.state, UInt<2>(0h1))
node _T_605 = and(_T_604, new_needT)
node _T_606 = or(_T_603, _T_605)
when _T_606 :
connect s_acquire, UInt<1>(0h0)
connect w_grantfirst, UInt<1>(0h0)
connect w_grantlast, UInt<1>(0h0)
connect w_grant, UInt<1>(0h0)
connect s_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_607 = eq(new_meta.state, UInt<2>(0h2))
node _T_608 = or(new_needT, _T_607)
node _T_609 = and(new_meta.hit, _T_608)
node _T_610 = not(new_skipProbe)
node _T_611 = and(new_meta.clients, _T_610)
node _T_612 = neq(_T_611, UInt<1>(0h0))
node _T_613 = and(_T_609, _T_612)
node _T_614 = and(UInt<1>(0h1), _T_613)
when _T_614 :
connect s_pprobe, UInt<1>(0h0)
connect w_pprobeackfirst, UInt<1>(0h0)
connect w_pprobeacklast, UInt<1>(0h0)
connect w_pprobeack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_615 = eq(new_request.opcode, UInt<3>(0h6))
node _T_616 = eq(new_request.opcode, UInt<3>(0h7))
node _T_617 = or(_T_615, _T_616)
when _T_617 :
connect w_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_618 = bits(new_request.opcode, 2, 2)
node _T_619 = eq(_T_618, UInt<1>(0h0))
node _T_620 = and(_T_619, new_meta.hit)
node _T_621 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_622 = and(_T_620, _T_621)
when _T_622 :
connect s_writeback, UInt<1>(0h0) | module MSHR_6( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_clients, // @[MSHR.scala:86:14]
input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [9:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [2:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output io_schedule_bits_b_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkc_valid, // @[MSHR.scala:86:14]
input io_sinkc_bits_last, // @[MSHR.scala:86:14]
input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14]
input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14]
input io_sinkc_bits_data, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input io_sinke_valid, // @[MSHR.scala:86:14]
input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14]
input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7]
wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7]
wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7]
wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7]
wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1 = 1'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1 = 1'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire _excluded_client_T = 1'h0; // @[MSHR.scala:279:38]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire _excluded_client_T_9 = 1'h0; // @[MSHR.scala:279:57]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire allocate_as_full_prio_0 = 1'h0; // @[MSHR.scala:504:34]
wire allocate_as_full_prio_1 = 1'h0; // @[MSHR.scala:504:34]
wire new_request_prio_0 = 1'h0; // @[MSHR.scala:506:24]
wire new_request_prio_1 = 1'h0; // @[MSHR.scala:506:24]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire [1:0] _io_schedule_bits_b_bits_clients_T = 2'h3; // @[MSHR.scala:289:53]
wire [1:0] _last_probe_T_1 = 2'h3; // @[MSHR.scala:459:66]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_clients = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] excluded_client = 2'h0; // @[MSHR.scala:279:28]
wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7]
wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire [1:0] _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
reg [12:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [9:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg [1:0] meta_clients; // @[MSHR.scala:100:17]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients; // @[MSHR.scala:100:17, :289:51]
wire [1:0] _last_probe_T_2 = meta_clients; // @[MSHR.scala:100:17, :459:64]
reg [12:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [2:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_rprobe; // @[MSHR.scala:121:33]
reg w_rprobeackfirst; // @[MSHR.scala:122:33]
reg w_rprobeacklast; // @[MSHR.scala:123:33]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
reg s_pprobe; // @[MSHR.scala:126:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg w_pprobeackfirst; // @[MSHR.scala:132:33]
reg w_pprobeacklast; // @[MSHR.scala:133:33]
reg w_pprobeack; // @[MSHR.scala:134:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
reg [1:0] probes_done; // @[MSHR.scala:150:24]
reg [1:0] probes_toN; // @[MSHR.scala:151:23]
reg probes_noT; // @[MSHR.scala:152:23]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}]
wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43]
wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64]
wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31]
wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44]
assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}]
assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire _req_clientBit_T = request_source == 6'h24; // @[Parameters.scala:46:9]
wire _req_clientBit_T_1 = request_source == 6'h20; // @[Parameters.scala:46:9]
wire [1:0] req_clientBit = {_req_clientBit_T_1, _req_clientBit_T}; // @[Parameters.scala:46:9]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire _meta_no_clients_T = |meta_clients; // @[MSHR.scala:100:17, :220:39]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire [1:0] _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 ? req_clientBit : 2'h0; // @[Parameters.scala:201:10, :282:66]
wire [1:0] _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}]
wire [1:0] _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}]
wire [1:0] _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54]
wire [1:0] _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire [1:0] _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66]
wire [1:0] _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}]
wire [1:0] _final_meta_writeback_clients_T_12 = meta_hit ? _final_meta_writeback_clients_T_11 : 2'h0; // @[MSHR.scala:100:17, :245:{40,64}]
wire [1:0] _final_meta_writeback_clients_T_13 = req_acquire ? req_clientBit : 2'h0; // @[Parameters.scala:201:10]
wire [1:0] _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40]
assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]
wire [1:0] _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54]
wire [1:0] _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}]
assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? (meta_hit ? _final_meta_writeback_clients_T_16 : 2'h0) : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire [1:0] _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:201:10]
wire _honour_BtoT_T_1 = |_honour_BtoT_T; // @[MSHR.scala:276:{47,64}]
wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42]
assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire evict_c = |meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire before_c = |meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire after_c = |final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _probe_bit_T = io_sinkc_bits_source_0 == 6'h24; // @[Parameters.scala:46:9]
wire _probe_bit_T_1 = io_sinkc_bits_source_0 == 6'h20; // @[Parameters.scala:46:9]
wire [1:0] probe_bit = {_probe_bit_T_1, _probe_bit_T}; // @[Parameters.scala:46:9]
wire [1:0] _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:201:10]
wire [1:0] _last_probe_T; // @[MSHR.scala:459:33]
assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33]
wire [1:0] _probes_done_T; // @[MSHR.scala:467:32]
assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32]
wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}]
wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75]
wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}]
wire [1:0] _probes_toN_T = probe_toN ? probe_bit : 2'h0; // @[Parameters.scala:201:10, :282:66]
wire [1:0] _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}]
wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53]
wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}]
wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42]
wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55]
wire _w_rprobeacklast_T; // @[MSHR.scala:471:55]
assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55]
wire _w_pprobeacklast_T; // @[MSHR.scala:473:55]
assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55]
wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}]
wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42]
wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}]
wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77]
wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}]
wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}]
wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32]
wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _new_clientBit_T = new_request_source == 6'h24; // @[Parameters.scala:46:9]
wire _new_clientBit_T_1 = new_request_source == 6'h20; // @[Parameters.scala:46:9]
wire [1:0] new_clientBit = {_new_clientBit_T_1, _new_clientBit_T}; // @[Parameters.scala:46:9]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire [1:0] new_skipProbe = _new_skipProbe_T_7 ? new_clientBit : 2'h0; // @[Parameters.scala:201:10, :279:106]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire prior_c = |final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28] |
Generate the Verilog code corresponding to this FIRRTL code module NullIntSource :
output auto : { int_out : UInt<1>[2]}
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
wire intnodeOut : UInt<1>[2]
invalidate intnodeOut[0]
invalidate intnodeOut[1]
connect auto.int_out, intnodeOut
connect intnodeOut[0], UInt<1>(0h0)
connect intnodeOut[1], UInt<1>(0h0) | module NullIntSource(); // @[NullIntSource.scala:16:9]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire intnodeOut_0 = 1'h0; // @[MixedNode.scala:542:17]
wire intnodeOut_1 = 1'h0; // @[MixedNode.scala:542:17]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module SourceC :
input clock : Clock
input reset : Reset
output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, bs_adr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<3>, mask : UInt<1>}}, flip bs_dat : { data : UInt<64>}, evict_req : { set : UInt<10>, way : UInt<3>}, flip evict_safe : UInt<1>}
inst queue of Queue12_TLBundleC_a32d64s3k3z3c
connect queue.clock, clock
connect queue.reset, reset
regreset fill : UInt<4>, clock, reset, UInt<4>(0h0)
regreset room : UInt<1>, clock, reset, UInt<1>(0h1)
node _T = and(queue.io.enq.ready, queue.io.enq.valid)
node _T_1 = and(queue.io.deq.ready, queue.io.deq.valid)
node _T_2 = neq(_T, _T_1)
when _T_2 :
node _fill_T = and(queue.io.enq.ready, queue.io.enq.valid)
node _fill_T_1 = not(UInt<4>(0h0))
node _fill_T_2 = mux(_fill_T, UInt<1>(0h1), _fill_T_1)
node _fill_T_3 = add(fill, _fill_T_2)
node _fill_T_4 = tail(_fill_T_3, 1)
connect fill, _fill_T_4
node _room_T = eq(fill, UInt<1>(0h0))
node _room_T_1 = eq(fill, UInt<1>(0h1))
node _room_T_2 = eq(fill, UInt<2>(0h2))
node _room_T_3 = or(_room_T_1, _room_T_2)
node _room_T_4 = and(queue.io.enq.ready, queue.io.enq.valid)
node _room_T_5 = eq(_room_T_4, UInt<1>(0h0))
node _room_T_6 = and(_room_T_3, _room_T_5)
node _room_T_7 = or(_room_T, _room_T_6)
connect room, _room_T_7
node _T_3 = leq(queue.io.count, UInt<1>(0h1))
node _T_4 = eq(room, _T_3)
node _T_5 = asUInt(reset)
node _T_6 = eq(_T_5, UInt<1>(0h0))
when _T_6 :
node _T_7 = eq(_T_4, UInt<1>(0h0))
when _T_7 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceC.scala:64 assert (room === queue.io.count <= 1.U)\n") : printf
assert(clock, _T_4, UInt<1>(0h1), "") : assert
regreset busy : UInt<1>, clock, reset, UInt<1>(0h0)
regreset beat : UInt<3>, clock, reset, UInt<3>(0h0)
node _last_T = not(UInt<3>(0h0))
node last = eq(beat, _last_T)
node _req_T = eq(busy, UInt<1>(0h0))
node _req_T_1 = eq(busy, UInt<1>(0h0))
node _req_T_2 = and(_req_T_1, io.req.valid)
reg req_r : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}, clock
when _req_T_2 :
connect req_r, io.req.bits
node req = mux(_req_T, io.req.bits, req_r)
node _want_data_T = and(io.req.valid, room)
node _want_data_T_1 = and(_want_data_T, io.req.bits.dirty)
node want_data = or(busy, _want_data_T_1)
node _io_req_ready_T = eq(busy, UInt<1>(0h0))
node _io_req_ready_T_1 = and(_io_req_ready_T, room)
connect io.req.ready, _io_req_ready_T_1
connect io.evict_req.set, req.set
connect io.evict_req.way, req.way
node _io_bs_adr_valid_T = orr(beat)
node _io_bs_adr_valid_T_1 = or(_io_bs_adr_valid_T, io.evict_safe)
node _io_bs_adr_valid_T_2 = and(_io_bs_adr_valid_T_1, want_data)
connect io.bs_adr.valid, _io_bs_adr_valid_T_2
connect io.bs_adr.bits.noop, UInt<1>(0h0)
connect io.bs_adr.bits.way, req.way
connect io.bs_adr.bits.set, req.set
connect io.bs_adr.bits.beat, beat
node _io_bs_adr_bits_mask_T = not(UInt<1>(0h0))
connect io.bs_adr.bits.mask, _io_bs_adr_bits_mask_T
node _T_8 = and(io.req.valid, io.req.bits.dirty)
node _T_9 = and(_T_8, room)
node _T_10 = eq(io.evict_safe, UInt<1>(0h0))
node _T_11 = and(_T_9, _T_10)
node _T_12 = eq(io.bs_adr.ready, UInt<1>(0h0))
node _T_13 = and(io.bs_adr.valid, _T_12)
node _T_14 = and(io.req.valid, room)
node _T_15 = and(_T_14, io.req.bits.dirty)
when _T_15 :
connect busy, UInt<1>(0h1)
node _T_16 = and(io.bs_adr.ready, io.bs_adr.valid)
when _T_16 :
node _beat_T = add(beat, UInt<1>(0h1))
node _beat_T_1 = tail(_beat_T, 1)
connect beat, _beat_T_1
when last :
connect busy, UInt<1>(0h0)
connect beat, UInt<1>(0h0)
node _s2_latch_T = and(io.bs_adr.ready, io.bs_adr.valid)
node _s2_latch_T_1 = and(io.req.ready, io.req.valid)
node s2_latch = mux(want_data, _s2_latch_T, _s2_latch_T_1)
reg s2_valid : UInt<1>, clock
connect s2_valid, s2_latch
reg s2_req : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}, clock
when s2_latch :
connect s2_req, req
reg s2_beat : UInt<3>, clock
when s2_latch :
connect s2_beat, beat
reg s2_last : UInt<1>, clock
when s2_latch :
connect s2_last, last
reg s3_valid : UInt<1>, clock
connect s3_valid, s2_valid
reg s3_req : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}, clock
when s2_valid :
connect s3_req, s2_req
reg s3_beat : UInt<3>, clock
when s2_valid :
connect s3_beat, s2_beat
reg s3_last : UInt<1>, clock
when s2_valid :
connect s3_last, s2_last
wire c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect c.valid, s3_valid
connect c.bits.opcode, s3_req.opcode
connect c.bits.param, s3_req.param
connect c.bits.size, UInt<3>(0h6)
connect c.bits.source, s3_req.source
node c_bits_address_base_y = or(s3_req.tag, UInt<13>(0h0))
node _c_bits_address_base_T = shr(c_bits_address_base_y, 13)
node _c_bits_address_base_T_1 = eq(_c_bits_address_base_T, UInt<1>(0h0))
node _c_bits_address_base_T_2 = asUInt(reset)
node _c_bits_address_base_T_3 = eq(_c_bits_address_base_T_2, UInt<1>(0h0))
when _c_bits_address_base_T_3 :
node _c_bits_address_base_T_4 = eq(_c_bits_address_base_T_1, UInt<1>(0h0))
when _c_bits_address_base_T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : c_bits_address_base_printf
assert(clock, _c_bits_address_base_T_1, UInt<1>(0h1), "") : c_bits_address_base_assert
node _c_bits_address_base_T_5 = bits(c_bits_address_base_y, 12, 0)
node c_bits_address_base_y_1 = or(s3_req.set, UInt<10>(0h0))
node _c_bits_address_base_T_6 = shr(c_bits_address_base_y_1, 10)
node _c_bits_address_base_T_7 = eq(_c_bits_address_base_T_6, UInt<1>(0h0))
node _c_bits_address_base_T_8 = asUInt(reset)
node _c_bits_address_base_T_9 = eq(_c_bits_address_base_T_8, UInt<1>(0h0))
when _c_bits_address_base_T_9 :
node _c_bits_address_base_T_10 = eq(_c_bits_address_base_T_7, UInt<1>(0h0))
when _c_bits_address_base_T_10 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : c_bits_address_base_printf_1
assert(clock, _c_bits_address_base_T_7, UInt<1>(0h1), "") : c_bits_address_base_assert_1
node _c_bits_address_base_T_11 = bits(c_bits_address_base_y_1, 9, 0)
node c_bits_address_base_y_2 = or(UInt<1>(0h0), UInt<6>(0h0))
node _c_bits_address_base_T_12 = shr(c_bits_address_base_y_2, 6)
node _c_bits_address_base_T_13 = eq(_c_bits_address_base_T_12, UInt<1>(0h0))
node _c_bits_address_base_T_14 = asUInt(reset)
node _c_bits_address_base_T_15 = eq(_c_bits_address_base_T_14, UInt<1>(0h0))
when _c_bits_address_base_T_15 :
node _c_bits_address_base_T_16 = eq(_c_bits_address_base_T_13, UInt<1>(0h0))
when _c_bits_address_base_T_16 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : c_bits_address_base_printf_2
assert(clock, _c_bits_address_base_T_13, UInt<1>(0h1), "") : c_bits_address_base_assert_2
node _c_bits_address_base_T_17 = bits(c_bits_address_base_y_2, 5, 0)
node c_bits_address_base_hi = cat(_c_bits_address_base_T_5, _c_bits_address_base_T_11)
node c_bits_address_base = cat(c_bits_address_base_hi, _c_bits_address_base_T_17)
node _c_bits_address_T = bits(c_bits_address_base, 0, 0)
node _c_bits_address_T_1 = bits(c_bits_address_base, 1, 1)
node _c_bits_address_T_2 = bits(c_bits_address_base, 2, 2)
node _c_bits_address_T_3 = bits(c_bits_address_base, 3, 3)
node _c_bits_address_T_4 = bits(c_bits_address_base, 4, 4)
node _c_bits_address_T_5 = bits(c_bits_address_base, 5, 5)
node _c_bits_address_T_6 = bits(c_bits_address_base, 6, 6)
node _c_bits_address_T_7 = bits(c_bits_address_base, 7, 7)
node _c_bits_address_T_8 = bits(c_bits_address_base, 8, 8)
node _c_bits_address_T_9 = bits(c_bits_address_base, 9, 9)
node _c_bits_address_T_10 = bits(c_bits_address_base, 10, 10)
node _c_bits_address_T_11 = bits(c_bits_address_base, 11, 11)
node _c_bits_address_T_12 = bits(c_bits_address_base, 12, 12)
node _c_bits_address_T_13 = bits(c_bits_address_base, 13, 13)
node _c_bits_address_T_14 = bits(c_bits_address_base, 14, 14)
node _c_bits_address_T_15 = bits(c_bits_address_base, 15, 15)
node _c_bits_address_T_16 = bits(c_bits_address_base, 16, 16)
node _c_bits_address_T_17 = bits(c_bits_address_base, 17, 17)
node _c_bits_address_T_18 = bits(c_bits_address_base, 18, 18)
node _c_bits_address_T_19 = bits(c_bits_address_base, 19, 19)
node _c_bits_address_T_20 = bits(c_bits_address_base, 20, 20)
node _c_bits_address_T_21 = bits(c_bits_address_base, 21, 21)
node _c_bits_address_T_22 = bits(c_bits_address_base, 22, 22)
node _c_bits_address_T_23 = bits(c_bits_address_base, 23, 23)
node _c_bits_address_T_24 = bits(c_bits_address_base, 24, 24)
node _c_bits_address_T_25 = bits(c_bits_address_base, 25, 25)
node _c_bits_address_T_26 = bits(c_bits_address_base, 26, 26)
node _c_bits_address_T_27 = bits(c_bits_address_base, 27, 27)
node _c_bits_address_T_28 = bits(c_bits_address_base, 28, 28)
node c_bits_address_lo_lo_lo_lo = cat(_c_bits_address_T_1, _c_bits_address_T)
node c_bits_address_lo_lo_lo_hi = cat(_c_bits_address_T_3, _c_bits_address_T_2)
node c_bits_address_lo_lo_lo = cat(c_bits_address_lo_lo_lo_hi, c_bits_address_lo_lo_lo_lo)
node c_bits_address_lo_lo_hi_lo = cat(_c_bits_address_T_5, _c_bits_address_T_4)
node c_bits_address_lo_lo_hi_hi = cat(_c_bits_address_T_7, _c_bits_address_T_6)
node c_bits_address_lo_lo_hi = cat(c_bits_address_lo_lo_hi_hi, c_bits_address_lo_lo_hi_lo)
node c_bits_address_lo_lo = cat(c_bits_address_lo_lo_hi, c_bits_address_lo_lo_lo)
node c_bits_address_lo_hi_lo_lo = cat(_c_bits_address_T_9, _c_bits_address_T_8)
node c_bits_address_lo_hi_lo_hi = cat(_c_bits_address_T_11, _c_bits_address_T_10)
node c_bits_address_lo_hi_lo = cat(c_bits_address_lo_hi_lo_hi, c_bits_address_lo_hi_lo_lo)
node c_bits_address_lo_hi_hi_lo = cat(_c_bits_address_T_13, _c_bits_address_T_12)
node c_bits_address_lo_hi_hi_hi = cat(_c_bits_address_T_15, _c_bits_address_T_14)
node c_bits_address_lo_hi_hi = cat(c_bits_address_lo_hi_hi_hi, c_bits_address_lo_hi_hi_lo)
node c_bits_address_lo_hi = cat(c_bits_address_lo_hi_hi, c_bits_address_lo_hi_lo)
node c_bits_address_lo = cat(c_bits_address_lo_hi, c_bits_address_lo_lo)
node c_bits_address_hi_lo_lo_lo = cat(_c_bits_address_T_17, _c_bits_address_T_16)
node c_bits_address_hi_lo_lo_hi = cat(_c_bits_address_T_19, _c_bits_address_T_18)
node c_bits_address_hi_lo_lo = cat(c_bits_address_hi_lo_lo_hi, c_bits_address_hi_lo_lo_lo)
node c_bits_address_hi_lo_hi_lo = cat(_c_bits_address_T_21, _c_bits_address_T_20)
node c_bits_address_hi_lo_hi_hi = cat(_c_bits_address_T_23, _c_bits_address_T_22)
node c_bits_address_hi_lo_hi = cat(c_bits_address_hi_lo_hi_hi, c_bits_address_hi_lo_hi_lo)
node c_bits_address_hi_lo = cat(c_bits_address_hi_lo_hi, c_bits_address_hi_lo_lo)
node c_bits_address_hi_hi_lo_lo = cat(_c_bits_address_T_25, _c_bits_address_T_24)
node c_bits_address_hi_hi_lo_hi = cat(_c_bits_address_T_27, _c_bits_address_T_26)
node c_bits_address_hi_hi_lo = cat(c_bits_address_hi_hi_lo_hi, c_bits_address_hi_hi_lo_lo)
node c_bits_address_hi_hi_hi_lo = cat(UInt<1>(0h0), UInt<1>(0h0))
node c_bits_address_hi_hi_hi_hi = cat(_c_bits_address_T_28, UInt<1>(0h0))
node c_bits_address_hi_hi_hi = cat(c_bits_address_hi_hi_hi_hi, c_bits_address_hi_hi_hi_lo)
node c_bits_address_hi_hi = cat(c_bits_address_hi_hi_hi, c_bits_address_hi_hi_lo)
node c_bits_address_hi = cat(c_bits_address_hi_hi, c_bits_address_hi_lo)
node _c_bits_address_T_29 = cat(c_bits_address_hi, c_bits_address_lo)
connect c.bits.address, _c_bits_address_T_29
connect c.bits.data, io.bs_dat.data
connect c.bits.corrupt, UInt<1>(0h0)
node _T_17 = eq(c.valid, UInt<1>(0h0))
node _T_18 = or(_T_17, c.ready)
node _T_19 = asUInt(reset)
node _T_20 = eq(_T_19, UInt<1>(0h0))
when _T_20 :
node _T_21 = eq(_T_18, UInt<1>(0h0))
when _T_21 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceC.scala:119 assert(!c.valid || c.ready)\n") : printf_1
assert(clock, _T_18, UInt<1>(0h1), "") : assert_1
node _T_22 = eq(c.ready, UInt<1>(0h0))
connect queue.io.enq, c
connect io.c.bits, queue.io.deq.bits
connect io.c.valid, queue.io.deq.valid
connect queue.io.deq.ready, io.c.ready | module SourceC( // @[SourceC.scala:35:7]
input clock, // @[SourceC.scala:35:7]
input reset, // @[SourceC.scala:35:7]
output io_req_ready, // @[SourceC.scala:37:14]
input io_req_valid, // @[SourceC.scala:37:14]
input [2:0] io_req_bits_opcode, // @[SourceC.scala:37:14]
input [2:0] io_req_bits_param, // @[SourceC.scala:37:14]
input [2:0] io_req_bits_source, // @[SourceC.scala:37:14]
input [12:0] io_req_bits_tag, // @[SourceC.scala:37:14]
input [9:0] io_req_bits_set, // @[SourceC.scala:37:14]
input [2:0] io_req_bits_way, // @[SourceC.scala:37:14]
input io_req_bits_dirty, // @[SourceC.scala:37:14]
input io_c_ready, // @[SourceC.scala:37:14]
output io_c_valid, // @[SourceC.scala:37:14]
output [2:0] io_c_bits_opcode, // @[SourceC.scala:37:14]
output [2:0] io_c_bits_param, // @[SourceC.scala:37:14]
output [2:0] io_c_bits_size, // @[SourceC.scala:37:14]
output [2:0] io_c_bits_source, // @[SourceC.scala:37:14]
output [31:0] io_c_bits_address, // @[SourceC.scala:37:14]
output [63:0] io_c_bits_data, // @[SourceC.scala:37:14]
output io_c_bits_corrupt, // @[SourceC.scala:37:14]
input io_bs_adr_ready, // @[SourceC.scala:37:14]
output io_bs_adr_valid, // @[SourceC.scala:37:14]
output [2:0] io_bs_adr_bits_way, // @[SourceC.scala:37:14]
output [9:0] io_bs_adr_bits_set, // @[SourceC.scala:37:14]
output [2:0] io_bs_adr_bits_beat, // @[SourceC.scala:37:14]
input [63:0] io_bs_dat_data, // @[SourceC.scala:37:14]
output [9:0] io_evict_req_set, // @[SourceC.scala:37:14]
output [2:0] io_evict_req_way, // @[SourceC.scala:37:14]
input io_evict_safe // @[SourceC.scala:37:14]
);
wire _queue_io_enq_ready; // @[SourceC.scala:54:21]
wire _queue_io_deq_valid; // @[SourceC.scala:54:21]
wire [3:0] _queue_io_count; // @[SourceC.scala:54:21]
reg [3:0] fill; // @[SourceC.scala:58:21]
reg room; // @[SourceC.scala:59:21]
reg busy; // @[SourceC.scala:66:21]
reg [2:0] beat; // @[SourceC.scala:67:21]
reg [2:0] req_r_opcode; // @[SourceC.scala:69:47]
reg [2:0] req_r_param; // @[SourceC.scala:69:47]
reg [2:0] req_r_source; // @[SourceC.scala:69:47]
reg [12:0] req_r_tag; // @[SourceC.scala:69:47]
reg [9:0] req_r_set; // @[SourceC.scala:69:47]
reg [2:0] req_r_way; // @[SourceC.scala:69:47]
wire [9:0] req_set = busy ? req_r_set : io_req_bits_set; // @[SourceC.scala:66:21, :69:{17,47}]
wire [2:0] req_way = busy ? req_r_way : io_req_bits_way; // @[SourceC.scala:66:21, :69:{17,47}]
wire _want_data_T = io_req_valid & room; // @[SourceC.scala:59:21, :70:41]
wire want_data = busy | _want_data_T & io_req_bits_dirty; // @[SourceC.scala:66:21, :70:{24,41,49}]
wire io_req_ready_0 = ~busy & room; // @[SourceC.scala:59:21, :66:21, :69:18, :72:25]
wire io_bs_adr_valid_0 = ((|beat) | io_evict_safe) & want_data; // @[SourceC.scala:67:21, :70:24, :77:{28,32,50}]
reg s2_valid; // @[SourceC.scala:97:25]
reg [2:0] s2_req_opcode; // @[SourceC.scala:98:25]
reg [2:0] s2_req_param; // @[SourceC.scala:98:25]
reg [2:0] s2_req_source; // @[SourceC.scala:98:25]
reg [12:0] s2_req_tag; // @[SourceC.scala:98:25]
reg [9:0] s2_req_set; // @[SourceC.scala:98:25]
reg s3_valid; // @[SourceC.scala:103:25]
reg [2:0] s3_req_opcode; // @[SourceC.scala:104:25]
reg [2:0] s3_req_param; // @[SourceC.scala:104:25]
reg [2:0] s3_req_source; // @[SourceC.scala:104:25]
reg [12:0] s3_req_tag; // @[SourceC.scala:104:25]
reg [9:0] s3_req_set; // @[SourceC.scala:104:25] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_141 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_156
connect io_out_sink_valid_1.clock, clock
connect io_out_sink_valid_1.reset, reset
connect io_out_sink_valid_1.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_valid_1.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_141( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_156 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetRegVec_w1_i0_38 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>}
node _reg_T = asAsyncReset(reset)
regreset reg : UInt<1>, clock, _reg_T, UInt<1>(0h0)
when io.en :
connect reg, io.d
connect io.q, reg | module AsyncResetRegVec_w1_i0_38( // @[AsyncResetReg.scala:56:7]
input clock, // @[AsyncResetReg.scala:56:7]
input reset, // @[AsyncResetReg.scala:56:7]
input io_d, // @[AsyncResetReg.scala:59:14]
output io_q // @[AsyncResetReg.scala:59:14]
);
wire io_d_0 = io_d; // @[AsyncResetReg.scala:56:7]
wire _reg_T = reset; // @[AsyncResetReg.scala:61:29]
wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14]
wire io_q_0; // @[AsyncResetReg.scala:56:7]
reg reg_0; // @[AsyncResetReg.scala:61:50]
assign io_q_0 = reg_0; // @[AsyncResetReg.scala:56:7, :61:50]
always @(posedge clock or posedge _reg_T) begin // @[AsyncResetReg.scala:56:7, :61:29]
if (_reg_T) // @[AsyncResetReg.scala:56:7, :61:29]
reg_0 <= 1'h0; // @[AsyncResetReg.scala:61:50]
else // @[AsyncResetReg.scala:56:7]
reg_0 <= io_d_0; // @[AsyncResetReg.scala:56:7, :61:50]
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_147 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_147( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLCFromBeat_SerialRAM_a64d64s8k8z8c :
input clock : Clock
input reset : Reset
output io : { protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<8>, source : UInt<8>, address : UInt<64>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip beat : { flip ready : UInt<1>, valid : UInt<1>, bits : { payload : UInt<86>, head : UInt<1>, tail : UInt<1>}}}
wire protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<8>, source : UInt<8>, address : UInt<64>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect io.protocol, protocol
regreset is_const : UInt<1>, clock, reset, UInt<1>(0h1)
reg const_reg : UInt<86>, clock
node const = mux(io.beat.bits.head, io.beat.bits.payload, const_reg)
node _io_beat_ready_T = eq(io.beat.bits.tail, UInt<1>(0h0))
node _io_beat_ready_T_1 = and(is_const, _io_beat_ready_T)
node _io_beat_ready_T_2 = or(_io_beat_ready_T_1, protocol.ready)
connect io.beat.ready, _io_beat_ready_T_2
node _protocol_valid_T = eq(is_const, UInt<1>(0h0))
node _protocol_valid_T_1 = or(_protocol_valid_T, io.beat.bits.tail)
node _protocol_valid_T_2 = and(_protocol_valid_T_1, io.beat.valid)
connect protocol.valid, _protocol_valid_T_2
wire _protocol_bits_echo_WIRE : { }
wire _protocol_bits_echo_WIRE_1 : UInt<0>
connect _protocol_bits_echo_WIRE_1, const
connect protocol.bits.echo, _protocol_bits_echo_WIRE
node _T = shr(const, 0)
wire _protocol_bits_user_WIRE : { }
wire _protocol_bits_user_WIRE_1 : UInt<0>
connect _protocol_bits_user_WIRE_1, _T
connect protocol.bits.user, _protocol_bits_user_WIRE
node _T_1 = shr(_T, 0)
wire _protocol_bits_address_WIRE : UInt<64>
connect _protocol_bits_address_WIRE, _T_1
connect protocol.bits.address, _protocol_bits_address_WIRE
node _T_2 = shr(_T_1, 64)
wire _protocol_bits_source_WIRE : UInt<8>
connect _protocol_bits_source_WIRE, _T_2
connect protocol.bits.source, _protocol_bits_source_WIRE
node _T_3 = shr(_T_2, 8)
wire _protocol_bits_size_WIRE : UInt<8>
connect _protocol_bits_size_WIRE, _T_3
connect protocol.bits.size, _protocol_bits_size_WIRE
node _T_4 = shr(_T_3, 8)
wire _protocol_bits_param_WIRE : UInt<3>
connect _protocol_bits_param_WIRE, _T_4
connect protocol.bits.param, _protocol_bits_param_WIRE
node _T_5 = shr(_T_4, 3)
wire _protocol_bits_opcode_WIRE : UInt<3>
connect _protocol_bits_opcode_WIRE, _T_5
connect protocol.bits.opcode, _protocol_bits_opcode_WIRE
node _T_6 = shr(_T_5, 3)
wire _protocol_bits_corrupt_WIRE : UInt<1>
connect _protocol_bits_corrupt_WIRE, io.beat.bits.payload
connect protocol.bits.corrupt, _protocol_bits_corrupt_WIRE
node _T_7 = shr(io.beat.bits.payload, 1)
wire _protocol_bits_data_WIRE : UInt<64>
connect _protocol_bits_data_WIRE, _T_7
connect protocol.bits.data, _protocol_bits_data_WIRE
node _T_8 = shr(_T_7, 64)
node _T_9 = and(io.beat.ready, io.beat.valid)
node _T_10 = and(_T_9, io.beat.bits.head)
when _T_10 :
connect is_const, UInt<1>(0h0)
connect const_reg, io.beat.bits.payload
node _T_11 = and(io.beat.ready, io.beat.valid)
node _T_12 = and(_T_11, io.beat.bits.tail)
when _T_12 :
connect is_const, UInt<1>(0h1) | module TLCFromBeat_SerialRAM_a64d64s8k8z8c( // @[TLChannelCompactor.scala:128:7]
input clock, // @[TLChannelCompactor.scala:128:7]
input reset, // @[TLChannelCompactor.scala:128:7]
output io_beat_ready, // @[TLChannelCompactor.scala:75:14]
input io_beat_valid, // @[TLChannelCompactor.scala:75:14]
input io_beat_bits_head, // @[TLChannelCompactor.scala:75:14]
input io_beat_bits_tail // @[TLChannelCompactor.scala:75:14]
);
reg is_const; // @[TLChannelCompactor.scala:88:25]
wire io_beat_ready_0 = is_const & ~io_beat_bits_tail; // @[TLChannelCompactor.scala:88:25, :91:{30,33}]
wire _GEN = io_beat_ready_0 & io_beat_valid; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[TLChannelCompactor.scala:128:7]
if (reset) // @[TLChannelCompactor.scala:128:7]
is_const <= 1'h1; // @[TLChannelCompactor.scala:88:25, :128:7]
else // @[TLChannelCompactor.scala:128:7]
is_const <= _GEN & io_beat_bits_tail | ~(_GEN & io_beat_bits_head) & is_const; // @[Decoupled.scala:51:35]
always @(posedge) |
Generate the Verilog code corresponding to this FIRRTL code module Tile_252 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_508
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_252( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0 // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
PE_508 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_117 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_127
connect io_out_sink_valid_1.clock, clock
connect io_out_sink_valid_1.reset, reset
connect io_out_sink_valid_1.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_valid_1.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_117( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_127 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ALU_4 :
input clock : Clock
input reset : Reset
output io : { flip dw : UInt<1>, flip fn : UInt<5>, flip in2 : UInt<64>, flip in1 : UInt<64>, out : UInt<64>, adder_out : UInt<64>, cmp_out : UInt<1>}
node _in2_inv_T = bits(io.fn, 3, 3)
node _in2_inv_T_1 = not(io.in2)
node in2_inv = mux(_in2_inv_T, _in2_inv_T_1, io.in2)
node in1_xor_in2 = xor(io.in1, in2_inv)
node in1_and_in2 = and(io.in1, in2_inv)
node _io_adder_out_T = add(io.in1, in2_inv)
node _io_adder_out_T_1 = tail(_io_adder_out_T, 1)
node _io_adder_out_T_2 = bits(io.fn, 3, 3)
node _io_adder_out_T_3 = add(_io_adder_out_T_1, _io_adder_out_T_2)
node _io_adder_out_T_4 = tail(_io_adder_out_T_3, 1)
connect io.adder_out, _io_adder_out_T_4
node _slt_T = bits(io.in1, 63, 63)
node _slt_T_1 = bits(io.in2, 63, 63)
node _slt_T_2 = eq(_slt_T, _slt_T_1)
node _slt_T_3 = bits(io.adder_out, 63, 63)
node _slt_T_4 = bits(io.fn, 1, 1)
node _slt_T_5 = bits(io.in2, 63, 63)
node _slt_T_6 = bits(io.in1, 63, 63)
node _slt_T_7 = mux(_slt_T_4, _slt_T_5, _slt_T_6)
node slt = mux(_slt_T_2, _slt_T_3, _slt_T_7)
node _io_cmp_out_T = bits(io.fn, 0, 0)
node _io_cmp_out_T_1 = bits(io.fn, 3, 3)
node _io_cmp_out_T_2 = eq(_io_cmp_out_T_1, UInt<1>(0h0))
node _io_cmp_out_T_3 = eq(in1_xor_in2, UInt<1>(0h0))
node _io_cmp_out_T_4 = mux(_io_cmp_out_T_2, _io_cmp_out_T_3, slt)
node _io_cmp_out_T_5 = xor(_io_cmp_out_T, _io_cmp_out_T_4)
connect io.cmp_out, _io_cmp_out_T_5
node _shin_hi_32_T = bits(io.fn, 3, 3)
node _shin_hi_32_T_1 = bits(io.in1, 31, 31)
node _shin_hi_32_T_2 = and(_shin_hi_32_T, _shin_hi_32_T_1)
node shin_hi_32 = mux(_shin_hi_32_T_2, UInt<32>(0hffffffff), UInt<32>(0h0))
node _shin_hi_T = eq(io.dw, UInt<1>(0h1))
node _shin_hi_T_1 = bits(io.in1, 63, 32)
node shin_hi = mux(_shin_hi_T, _shin_hi_T_1, shin_hi_32)
node _shamt_T = bits(io.in2, 5, 5)
node _shamt_T_1 = eq(io.dw, UInt<1>(0h1))
node _shamt_T_2 = and(_shamt_T, _shamt_T_1)
node _shamt_T_3 = bits(io.in2, 4, 0)
node shamt = cat(_shamt_T_2, _shamt_T_3)
node _T = bits(io.in1, 31, 0)
node shin_r = cat(shin_hi, _T)
node _shin_T = eq(io.fn, UInt<3>(0h5))
node _shin_T_1 = eq(io.fn, UInt<4>(0hb))
node _shin_T_2 = eq(io.fn, UInt<5>(0h12))
node _shin_T_3 = eq(io.fn, UInt<5>(0h13))
node _shin_T_4 = or(_shin_T, _shin_T_1)
node _shin_T_5 = or(_shin_T_4, _shin_T_2)
node _shin_T_6 = or(_shin_T_5, _shin_T_3)
node _shin_T_7 = eq(_shin_T_6, UInt<1>(0h0))
node _shin_T_8 = shl(UInt<32>(0hffffffff), 32)
node _shin_T_9 = xor(UInt<64>(0hffffffffffffffff), _shin_T_8)
node _shin_T_10 = shr(shin_r, 32)
node _shin_T_11 = and(_shin_T_10, _shin_T_9)
node _shin_T_12 = bits(shin_r, 31, 0)
node _shin_T_13 = shl(_shin_T_12, 32)
node _shin_T_14 = not(_shin_T_9)
node _shin_T_15 = and(_shin_T_13, _shin_T_14)
node _shin_T_16 = or(_shin_T_11, _shin_T_15)
node _shin_T_17 = bits(_shin_T_9, 47, 0)
node _shin_T_18 = shl(_shin_T_17, 16)
node _shin_T_19 = xor(_shin_T_9, _shin_T_18)
node _shin_T_20 = shr(_shin_T_16, 16)
node _shin_T_21 = and(_shin_T_20, _shin_T_19)
node _shin_T_22 = bits(_shin_T_16, 47, 0)
node _shin_T_23 = shl(_shin_T_22, 16)
node _shin_T_24 = not(_shin_T_19)
node _shin_T_25 = and(_shin_T_23, _shin_T_24)
node _shin_T_26 = or(_shin_T_21, _shin_T_25)
node _shin_T_27 = bits(_shin_T_19, 55, 0)
node _shin_T_28 = shl(_shin_T_27, 8)
node _shin_T_29 = xor(_shin_T_19, _shin_T_28)
node _shin_T_30 = shr(_shin_T_26, 8)
node _shin_T_31 = and(_shin_T_30, _shin_T_29)
node _shin_T_32 = bits(_shin_T_26, 55, 0)
node _shin_T_33 = shl(_shin_T_32, 8)
node _shin_T_34 = not(_shin_T_29)
node _shin_T_35 = and(_shin_T_33, _shin_T_34)
node _shin_T_36 = or(_shin_T_31, _shin_T_35)
node _shin_T_37 = bits(_shin_T_29, 59, 0)
node _shin_T_38 = shl(_shin_T_37, 4)
node _shin_T_39 = xor(_shin_T_29, _shin_T_38)
node _shin_T_40 = shr(_shin_T_36, 4)
node _shin_T_41 = and(_shin_T_40, _shin_T_39)
node _shin_T_42 = bits(_shin_T_36, 59, 0)
node _shin_T_43 = shl(_shin_T_42, 4)
node _shin_T_44 = not(_shin_T_39)
node _shin_T_45 = and(_shin_T_43, _shin_T_44)
node _shin_T_46 = or(_shin_T_41, _shin_T_45)
node _shin_T_47 = bits(_shin_T_39, 61, 0)
node _shin_T_48 = shl(_shin_T_47, 2)
node _shin_T_49 = xor(_shin_T_39, _shin_T_48)
node _shin_T_50 = shr(_shin_T_46, 2)
node _shin_T_51 = and(_shin_T_50, _shin_T_49)
node _shin_T_52 = bits(_shin_T_46, 61, 0)
node _shin_T_53 = shl(_shin_T_52, 2)
node _shin_T_54 = not(_shin_T_49)
node _shin_T_55 = and(_shin_T_53, _shin_T_54)
node _shin_T_56 = or(_shin_T_51, _shin_T_55)
node _shin_T_57 = bits(_shin_T_49, 62, 0)
node _shin_T_58 = shl(_shin_T_57, 1)
node _shin_T_59 = xor(_shin_T_49, _shin_T_58)
node _shin_T_60 = shr(_shin_T_56, 1)
node _shin_T_61 = and(_shin_T_60, _shin_T_59)
node _shin_T_62 = bits(_shin_T_56, 62, 0)
node _shin_T_63 = shl(_shin_T_62, 1)
node _shin_T_64 = not(_shin_T_59)
node _shin_T_65 = and(_shin_T_63, _shin_T_64)
node _shin_T_66 = or(_shin_T_61, _shin_T_65)
node shin = mux(_shin_T_7, _shin_T_66, shin_r)
node _shout_r_T = bits(io.fn, 3, 3)
node _shout_r_T_1 = bits(shin, 63, 63)
node _shout_r_T_2 = and(_shout_r_T, _shout_r_T_1)
node _shout_r_T_3 = cat(_shout_r_T_2, shin)
node _shout_r_T_4 = asSInt(_shout_r_T_3)
node _shout_r_T_5 = dshr(_shout_r_T_4, shamt)
node shout_r = bits(_shout_r_T_5, 63, 0)
node _shout_l_T = shl(UInt<32>(0hffffffff), 32)
node _shout_l_T_1 = xor(UInt<64>(0hffffffffffffffff), _shout_l_T)
node _shout_l_T_2 = shr(shout_r, 32)
node _shout_l_T_3 = and(_shout_l_T_2, _shout_l_T_1)
node _shout_l_T_4 = bits(shout_r, 31, 0)
node _shout_l_T_5 = shl(_shout_l_T_4, 32)
node _shout_l_T_6 = not(_shout_l_T_1)
node _shout_l_T_7 = and(_shout_l_T_5, _shout_l_T_6)
node _shout_l_T_8 = or(_shout_l_T_3, _shout_l_T_7)
node _shout_l_T_9 = bits(_shout_l_T_1, 47, 0)
node _shout_l_T_10 = shl(_shout_l_T_9, 16)
node _shout_l_T_11 = xor(_shout_l_T_1, _shout_l_T_10)
node _shout_l_T_12 = shr(_shout_l_T_8, 16)
node _shout_l_T_13 = and(_shout_l_T_12, _shout_l_T_11)
node _shout_l_T_14 = bits(_shout_l_T_8, 47, 0)
node _shout_l_T_15 = shl(_shout_l_T_14, 16)
node _shout_l_T_16 = not(_shout_l_T_11)
node _shout_l_T_17 = and(_shout_l_T_15, _shout_l_T_16)
node _shout_l_T_18 = or(_shout_l_T_13, _shout_l_T_17)
node _shout_l_T_19 = bits(_shout_l_T_11, 55, 0)
node _shout_l_T_20 = shl(_shout_l_T_19, 8)
node _shout_l_T_21 = xor(_shout_l_T_11, _shout_l_T_20)
node _shout_l_T_22 = shr(_shout_l_T_18, 8)
node _shout_l_T_23 = and(_shout_l_T_22, _shout_l_T_21)
node _shout_l_T_24 = bits(_shout_l_T_18, 55, 0)
node _shout_l_T_25 = shl(_shout_l_T_24, 8)
node _shout_l_T_26 = not(_shout_l_T_21)
node _shout_l_T_27 = and(_shout_l_T_25, _shout_l_T_26)
node _shout_l_T_28 = or(_shout_l_T_23, _shout_l_T_27)
node _shout_l_T_29 = bits(_shout_l_T_21, 59, 0)
node _shout_l_T_30 = shl(_shout_l_T_29, 4)
node _shout_l_T_31 = xor(_shout_l_T_21, _shout_l_T_30)
node _shout_l_T_32 = shr(_shout_l_T_28, 4)
node _shout_l_T_33 = and(_shout_l_T_32, _shout_l_T_31)
node _shout_l_T_34 = bits(_shout_l_T_28, 59, 0)
node _shout_l_T_35 = shl(_shout_l_T_34, 4)
node _shout_l_T_36 = not(_shout_l_T_31)
node _shout_l_T_37 = and(_shout_l_T_35, _shout_l_T_36)
node _shout_l_T_38 = or(_shout_l_T_33, _shout_l_T_37)
node _shout_l_T_39 = bits(_shout_l_T_31, 61, 0)
node _shout_l_T_40 = shl(_shout_l_T_39, 2)
node _shout_l_T_41 = xor(_shout_l_T_31, _shout_l_T_40)
node _shout_l_T_42 = shr(_shout_l_T_38, 2)
node _shout_l_T_43 = and(_shout_l_T_42, _shout_l_T_41)
node _shout_l_T_44 = bits(_shout_l_T_38, 61, 0)
node _shout_l_T_45 = shl(_shout_l_T_44, 2)
node _shout_l_T_46 = not(_shout_l_T_41)
node _shout_l_T_47 = and(_shout_l_T_45, _shout_l_T_46)
node _shout_l_T_48 = or(_shout_l_T_43, _shout_l_T_47)
node _shout_l_T_49 = bits(_shout_l_T_41, 62, 0)
node _shout_l_T_50 = shl(_shout_l_T_49, 1)
node _shout_l_T_51 = xor(_shout_l_T_41, _shout_l_T_50)
node _shout_l_T_52 = shr(_shout_l_T_48, 1)
node _shout_l_T_53 = and(_shout_l_T_52, _shout_l_T_51)
node _shout_l_T_54 = bits(_shout_l_T_48, 62, 0)
node _shout_l_T_55 = shl(_shout_l_T_54, 1)
node _shout_l_T_56 = not(_shout_l_T_51)
node _shout_l_T_57 = and(_shout_l_T_55, _shout_l_T_56)
node shout_l = or(_shout_l_T_53, _shout_l_T_57)
node _shout_T = eq(io.fn, UInt<3>(0h5))
node _shout_T_1 = eq(io.fn, UInt<4>(0hb))
node _shout_T_2 = or(_shout_T, _shout_T_1)
node _shout_T_3 = eq(io.fn, UInt<5>(0h13))
node _shout_T_4 = or(_shout_T_2, _shout_T_3)
node _shout_T_5 = mux(_shout_T_4, shout_r, UInt<1>(0h0))
node _shout_T_6 = eq(io.fn, UInt<1>(0h1))
node _shout_T_7 = mux(_shout_T_6, shout_l, UInt<1>(0h0))
node shout = or(_shout_T_5, _shout_T_7)
node in2_not_zero = orr(io.in2)
node _logic_T = eq(io.fn, UInt<3>(0h4))
node _logic_T_1 = eq(io.fn, UInt<3>(0h6))
node _logic_T_2 = or(_logic_T, _logic_T_1)
node _logic_T_3 = eq(io.fn, UInt<5>(0h19))
node _logic_T_4 = or(_logic_T_2, _logic_T_3)
node _logic_T_5 = eq(io.fn, UInt<5>(0h1a))
node _logic_T_6 = or(_logic_T_4, _logic_T_5)
node _logic_T_7 = mux(_logic_T_6, in1_xor_in2, UInt<1>(0h0))
node _logic_T_8 = eq(io.fn, UInt<3>(0h6))
node _logic_T_9 = eq(io.fn, UInt<3>(0h7))
node _logic_T_10 = or(_logic_T_8, _logic_T_9)
node _logic_T_11 = eq(io.fn, UInt<5>(0h19))
node _logic_T_12 = or(_logic_T_10, _logic_T_11)
node _logic_T_13 = eq(io.fn, UInt<5>(0h18))
node _logic_T_14 = or(_logic_T_12, _logic_T_13)
node _logic_T_15 = mux(_logic_T_14, in1_and_in2, UInt<1>(0h0))
node logic = or(_logic_T_7, _logic_T_15)
node _bext_mask_T = eq(io.fn, UInt<5>(0h13))
node _bext_mask_T_1 = and(UInt<1>(0h0), _bext_mask_T)
node _bext_mask_T_2 = not(UInt<64>(0h0))
node bext_mask = mux(_bext_mask_T_1, UInt<1>(0h1), _bext_mask_T_2)
node _shift_logic_T = geq(io.fn, UInt<4>(0hc))
node _shift_logic_T_1 = leq(io.fn, UInt<4>(0hf))
node _shift_logic_T_2 = and(_shift_logic_T, _shift_logic_T_1)
node _shift_logic_T_3 = and(_shift_logic_T_2, slt)
node _shift_logic_T_4 = or(_shift_logic_T_3, logic)
node _shift_logic_T_5 = and(shout, bext_mask)
node shift_logic = or(_shift_logic_T_4, _shift_logic_T_5)
node _tz_in_T = eq(io.dw, UInt<1>(0h0))
node _tz_in_T_1 = bits(io.in2, 0, 0)
node _tz_in_T_2 = eq(_tz_in_T_1, UInt<1>(0h0))
node _tz_in_T_3 = cat(_tz_in_T, _tz_in_T_2)
node _tz_in_T_4 = shl(UInt<32>(0hffffffff), 32)
node _tz_in_T_5 = xor(UInt<64>(0hffffffffffffffff), _tz_in_T_4)
node _tz_in_T_6 = shr(io.in1, 32)
node _tz_in_T_7 = and(_tz_in_T_6, _tz_in_T_5)
node _tz_in_T_8 = bits(io.in1, 31, 0)
node _tz_in_T_9 = shl(_tz_in_T_8, 32)
node _tz_in_T_10 = not(_tz_in_T_5)
node _tz_in_T_11 = and(_tz_in_T_9, _tz_in_T_10)
node _tz_in_T_12 = or(_tz_in_T_7, _tz_in_T_11)
node _tz_in_T_13 = bits(_tz_in_T_5, 47, 0)
node _tz_in_T_14 = shl(_tz_in_T_13, 16)
node _tz_in_T_15 = xor(_tz_in_T_5, _tz_in_T_14)
node _tz_in_T_16 = shr(_tz_in_T_12, 16)
node _tz_in_T_17 = and(_tz_in_T_16, _tz_in_T_15)
node _tz_in_T_18 = bits(_tz_in_T_12, 47, 0)
node _tz_in_T_19 = shl(_tz_in_T_18, 16)
node _tz_in_T_20 = not(_tz_in_T_15)
node _tz_in_T_21 = and(_tz_in_T_19, _tz_in_T_20)
node _tz_in_T_22 = or(_tz_in_T_17, _tz_in_T_21)
node _tz_in_T_23 = bits(_tz_in_T_15, 55, 0)
node _tz_in_T_24 = shl(_tz_in_T_23, 8)
node _tz_in_T_25 = xor(_tz_in_T_15, _tz_in_T_24)
node _tz_in_T_26 = shr(_tz_in_T_22, 8)
node _tz_in_T_27 = and(_tz_in_T_26, _tz_in_T_25)
node _tz_in_T_28 = bits(_tz_in_T_22, 55, 0)
node _tz_in_T_29 = shl(_tz_in_T_28, 8)
node _tz_in_T_30 = not(_tz_in_T_25)
node _tz_in_T_31 = and(_tz_in_T_29, _tz_in_T_30)
node _tz_in_T_32 = or(_tz_in_T_27, _tz_in_T_31)
node _tz_in_T_33 = bits(_tz_in_T_25, 59, 0)
node _tz_in_T_34 = shl(_tz_in_T_33, 4)
node _tz_in_T_35 = xor(_tz_in_T_25, _tz_in_T_34)
node _tz_in_T_36 = shr(_tz_in_T_32, 4)
node _tz_in_T_37 = and(_tz_in_T_36, _tz_in_T_35)
node _tz_in_T_38 = bits(_tz_in_T_32, 59, 0)
node _tz_in_T_39 = shl(_tz_in_T_38, 4)
node _tz_in_T_40 = not(_tz_in_T_35)
node _tz_in_T_41 = and(_tz_in_T_39, _tz_in_T_40)
node _tz_in_T_42 = or(_tz_in_T_37, _tz_in_T_41)
node _tz_in_T_43 = bits(_tz_in_T_35, 61, 0)
node _tz_in_T_44 = shl(_tz_in_T_43, 2)
node _tz_in_T_45 = xor(_tz_in_T_35, _tz_in_T_44)
node _tz_in_T_46 = shr(_tz_in_T_42, 2)
node _tz_in_T_47 = and(_tz_in_T_46, _tz_in_T_45)
node _tz_in_T_48 = bits(_tz_in_T_42, 61, 0)
node _tz_in_T_49 = shl(_tz_in_T_48, 2)
node _tz_in_T_50 = not(_tz_in_T_45)
node _tz_in_T_51 = and(_tz_in_T_49, _tz_in_T_50)
node _tz_in_T_52 = or(_tz_in_T_47, _tz_in_T_51)
node _tz_in_T_53 = bits(_tz_in_T_45, 62, 0)
node _tz_in_T_54 = shl(_tz_in_T_53, 1)
node _tz_in_T_55 = xor(_tz_in_T_45, _tz_in_T_54)
node _tz_in_T_56 = shr(_tz_in_T_52, 1)
node _tz_in_T_57 = and(_tz_in_T_56, _tz_in_T_55)
node _tz_in_T_58 = bits(_tz_in_T_52, 62, 0)
node _tz_in_T_59 = shl(_tz_in_T_58, 1)
node _tz_in_T_60 = not(_tz_in_T_55)
node _tz_in_T_61 = and(_tz_in_T_59, _tz_in_T_60)
node _tz_in_T_62 = or(_tz_in_T_57, _tz_in_T_61)
node _tz_in_T_63 = bits(io.in1, 31, 0)
node _tz_in_T_64 = cat(UInt<1>(0h1), _tz_in_T_63)
node _tz_in_T_65 = bits(io.in1, 31, 0)
node _tz_in_T_66 = shl(UInt<16>(0hffff), 16)
node _tz_in_T_67 = xor(UInt<32>(0hffffffff), _tz_in_T_66)
node _tz_in_T_68 = shr(_tz_in_T_65, 16)
node _tz_in_T_69 = and(_tz_in_T_68, _tz_in_T_67)
node _tz_in_T_70 = bits(_tz_in_T_65, 15, 0)
node _tz_in_T_71 = shl(_tz_in_T_70, 16)
node _tz_in_T_72 = not(_tz_in_T_67)
node _tz_in_T_73 = and(_tz_in_T_71, _tz_in_T_72)
node _tz_in_T_74 = or(_tz_in_T_69, _tz_in_T_73)
node _tz_in_T_75 = bits(_tz_in_T_67, 23, 0)
node _tz_in_T_76 = shl(_tz_in_T_75, 8)
node _tz_in_T_77 = xor(_tz_in_T_67, _tz_in_T_76)
node _tz_in_T_78 = shr(_tz_in_T_74, 8)
node _tz_in_T_79 = and(_tz_in_T_78, _tz_in_T_77)
node _tz_in_T_80 = bits(_tz_in_T_74, 23, 0)
node _tz_in_T_81 = shl(_tz_in_T_80, 8)
node _tz_in_T_82 = not(_tz_in_T_77)
node _tz_in_T_83 = and(_tz_in_T_81, _tz_in_T_82)
node _tz_in_T_84 = or(_tz_in_T_79, _tz_in_T_83)
node _tz_in_T_85 = bits(_tz_in_T_77, 27, 0)
node _tz_in_T_86 = shl(_tz_in_T_85, 4)
node _tz_in_T_87 = xor(_tz_in_T_77, _tz_in_T_86)
node _tz_in_T_88 = shr(_tz_in_T_84, 4)
node _tz_in_T_89 = and(_tz_in_T_88, _tz_in_T_87)
node _tz_in_T_90 = bits(_tz_in_T_84, 27, 0)
node _tz_in_T_91 = shl(_tz_in_T_90, 4)
node _tz_in_T_92 = not(_tz_in_T_87)
node _tz_in_T_93 = and(_tz_in_T_91, _tz_in_T_92)
node _tz_in_T_94 = or(_tz_in_T_89, _tz_in_T_93)
node _tz_in_T_95 = bits(_tz_in_T_87, 29, 0)
node _tz_in_T_96 = shl(_tz_in_T_95, 2)
node _tz_in_T_97 = xor(_tz_in_T_87, _tz_in_T_96)
node _tz_in_T_98 = shr(_tz_in_T_94, 2)
node _tz_in_T_99 = and(_tz_in_T_98, _tz_in_T_97)
node _tz_in_T_100 = bits(_tz_in_T_94, 29, 0)
node _tz_in_T_101 = shl(_tz_in_T_100, 2)
node _tz_in_T_102 = not(_tz_in_T_97)
node _tz_in_T_103 = and(_tz_in_T_101, _tz_in_T_102)
node _tz_in_T_104 = or(_tz_in_T_99, _tz_in_T_103)
node _tz_in_T_105 = bits(_tz_in_T_97, 30, 0)
node _tz_in_T_106 = shl(_tz_in_T_105, 1)
node _tz_in_T_107 = xor(_tz_in_T_97, _tz_in_T_106)
node _tz_in_T_108 = shr(_tz_in_T_104, 1)
node _tz_in_T_109 = and(_tz_in_T_108, _tz_in_T_107)
node _tz_in_T_110 = bits(_tz_in_T_104, 30, 0)
node _tz_in_T_111 = shl(_tz_in_T_110, 1)
node _tz_in_T_112 = not(_tz_in_T_107)
node _tz_in_T_113 = and(_tz_in_T_111, _tz_in_T_112)
node _tz_in_T_114 = or(_tz_in_T_109, _tz_in_T_113)
node _tz_in_T_115 = cat(UInt<1>(0h1), _tz_in_T_114)
node _tz_in_T_116 = eq(UInt<1>(0h1), _tz_in_T_3)
node _tz_in_T_117 = mux(_tz_in_T_116, _tz_in_T_62, io.in1)
node _tz_in_T_118 = eq(UInt<2>(0h2), _tz_in_T_3)
node _tz_in_T_119 = mux(_tz_in_T_118, _tz_in_T_64, _tz_in_T_117)
node _tz_in_T_120 = eq(UInt<2>(0h3), _tz_in_T_3)
node tz_in = mux(_tz_in_T_120, _tz_in_T_115, _tz_in_T_119)
node _popc_in_T = bits(io.in2, 1, 1)
node _popc_in_T_1 = eq(io.dw, UInt<1>(0h0))
node _popc_in_T_2 = bits(io.in1, 31, 0)
node _popc_in_T_3 = mux(_popc_in_T_1, _popc_in_T_2, io.in1)
node _popc_in_T_4 = cat(UInt<1>(0h1), tz_in)
node _popc_in_T_5 = bits(_popc_in_T_4, 0, 0)
node _popc_in_T_6 = bits(_popc_in_T_4, 1, 1)
node _popc_in_T_7 = bits(_popc_in_T_4, 2, 2)
node _popc_in_T_8 = bits(_popc_in_T_4, 3, 3)
node _popc_in_T_9 = bits(_popc_in_T_4, 4, 4)
node _popc_in_T_10 = bits(_popc_in_T_4, 5, 5)
node _popc_in_T_11 = bits(_popc_in_T_4, 6, 6)
node _popc_in_T_12 = bits(_popc_in_T_4, 7, 7)
node _popc_in_T_13 = bits(_popc_in_T_4, 8, 8)
node _popc_in_T_14 = bits(_popc_in_T_4, 9, 9)
node _popc_in_T_15 = bits(_popc_in_T_4, 10, 10)
node _popc_in_T_16 = bits(_popc_in_T_4, 11, 11)
node _popc_in_T_17 = bits(_popc_in_T_4, 12, 12)
node _popc_in_T_18 = bits(_popc_in_T_4, 13, 13)
node _popc_in_T_19 = bits(_popc_in_T_4, 14, 14)
node _popc_in_T_20 = bits(_popc_in_T_4, 15, 15)
node _popc_in_T_21 = bits(_popc_in_T_4, 16, 16)
node _popc_in_T_22 = bits(_popc_in_T_4, 17, 17)
node _popc_in_T_23 = bits(_popc_in_T_4, 18, 18)
node _popc_in_T_24 = bits(_popc_in_T_4, 19, 19)
node _popc_in_T_25 = bits(_popc_in_T_4, 20, 20)
node _popc_in_T_26 = bits(_popc_in_T_4, 21, 21)
node _popc_in_T_27 = bits(_popc_in_T_4, 22, 22)
node _popc_in_T_28 = bits(_popc_in_T_4, 23, 23)
node _popc_in_T_29 = bits(_popc_in_T_4, 24, 24)
node _popc_in_T_30 = bits(_popc_in_T_4, 25, 25)
node _popc_in_T_31 = bits(_popc_in_T_4, 26, 26)
node _popc_in_T_32 = bits(_popc_in_T_4, 27, 27)
node _popc_in_T_33 = bits(_popc_in_T_4, 28, 28)
node _popc_in_T_34 = bits(_popc_in_T_4, 29, 29)
node _popc_in_T_35 = bits(_popc_in_T_4, 30, 30)
node _popc_in_T_36 = bits(_popc_in_T_4, 31, 31)
node _popc_in_T_37 = bits(_popc_in_T_4, 32, 32)
node _popc_in_T_38 = bits(_popc_in_T_4, 33, 33)
node _popc_in_T_39 = bits(_popc_in_T_4, 34, 34)
node _popc_in_T_40 = bits(_popc_in_T_4, 35, 35)
node _popc_in_T_41 = bits(_popc_in_T_4, 36, 36)
node _popc_in_T_42 = bits(_popc_in_T_4, 37, 37)
node _popc_in_T_43 = bits(_popc_in_T_4, 38, 38)
node _popc_in_T_44 = bits(_popc_in_T_4, 39, 39)
node _popc_in_T_45 = bits(_popc_in_T_4, 40, 40)
node _popc_in_T_46 = bits(_popc_in_T_4, 41, 41)
node _popc_in_T_47 = bits(_popc_in_T_4, 42, 42)
node _popc_in_T_48 = bits(_popc_in_T_4, 43, 43)
node _popc_in_T_49 = bits(_popc_in_T_4, 44, 44)
node _popc_in_T_50 = bits(_popc_in_T_4, 45, 45)
node _popc_in_T_51 = bits(_popc_in_T_4, 46, 46)
node _popc_in_T_52 = bits(_popc_in_T_4, 47, 47)
node _popc_in_T_53 = bits(_popc_in_T_4, 48, 48)
node _popc_in_T_54 = bits(_popc_in_T_4, 49, 49)
node _popc_in_T_55 = bits(_popc_in_T_4, 50, 50)
node _popc_in_T_56 = bits(_popc_in_T_4, 51, 51)
node _popc_in_T_57 = bits(_popc_in_T_4, 52, 52)
node _popc_in_T_58 = bits(_popc_in_T_4, 53, 53)
node _popc_in_T_59 = bits(_popc_in_T_4, 54, 54)
node _popc_in_T_60 = bits(_popc_in_T_4, 55, 55)
node _popc_in_T_61 = bits(_popc_in_T_4, 56, 56)
node _popc_in_T_62 = bits(_popc_in_T_4, 57, 57)
node _popc_in_T_63 = bits(_popc_in_T_4, 58, 58)
node _popc_in_T_64 = bits(_popc_in_T_4, 59, 59)
node _popc_in_T_65 = bits(_popc_in_T_4, 60, 60)
node _popc_in_T_66 = bits(_popc_in_T_4, 61, 61)
node _popc_in_T_67 = bits(_popc_in_T_4, 62, 62)
node _popc_in_T_68 = bits(_popc_in_T_4, 63, 63)
node _popc_in_T_69 = bits(_popc_in_T_4, 64, 64)
node _popc_in_T_70 = mux(_popc_in_T_69, UInt<65>(0h10000000000000000), UInt<65>(0h0))
node _popc_in_T_71 = mux(_popc_in_T_68, UInt<65>(0h8000000000000000), _popc_in_T_70)
node _popc_in_T_72 = mux(_popc_in_T_67, UInt<65>(0h4000000000000000), _popc_in_T_71)
node _popc_in_T_73 = mux(_popc_in_T_66, UInt<65>(0h2000000000000000), _popc_in_T_72)
node _popc_in_T_74 = mux(_popc_in_T_65, UInt<65>(0h1000000000000000), _popc_in_T_73)
node _popc_in_T_75 = mux(_popc_in_T_64, UInt<65>(0h800000000000000), _popc_in_T_74)
node _popc_in_T_76 = mux(_popc_in_T_63, UInt<65>(0h400000000000000), _popc_in_T_75)
node _popc_in_T_77 = mux(_popc_in_T_62, UInt<65>(0h200000000000000), _popc_in_T_76)
node _popc_in_T_78 = mux(_popc_in_T_61, UInt<65>(0h100000000000000), _popc_in_T_77)
node _popc_in_T_79 = mux(_popc_in_T_60, UInt<65>(0h80000000000000), _popc_in_T_78)
node _popc_in_T_80 = mux(_popc_in_T_59, UInt<65>(0h40000000000000), _popc_in_T_79)
node _popc_in_T_81 = mux(_popc_in_T_58, UInt<65>(0h20000000000000), _popc_in_T_80)
node _popc_in_T_82 = mux(_popc_in_T_57, UInt<65>(0h10000000000000), _popc_in_T_81)
node _popc_in_T_83 = mux(_popc_in_T_56, UInt<65>(0h8000000000000), _popc_in_T_82)
node _popc_in_T_84 = mux(_popc_in_T_55, UInt<65>(0h4000000000000), _popc_in_T_83)
node _popc_in_T_85 = mux(_popc_in_T_54, UInt<65>(0h2000000000000), _popc_in_T_84)
node _popc_in_T_86 = mux(_popc_in_T_53, UInt<65>(0h1000000000000), _popc_in_T_85)
node _popc_in_T_87 = mux(_popc_in_T_52, UInt<65>(0h800000000000), _popc_in_T_86)
node _popc_in_T_88 = mux(_popc_in_T_51, UInt<65>(0h400000000000), _popc_in_T_87)
node _popc_in_T_89 = mux(_popc_in_T_50, UInt<65>(0h200000000000), _popc_in_T_88)
node _popc_in_T_90 = mux(_popc_in_T_49, UInt<65>(0h100000000000), _popc_in_T_89)
node _popc_in_T_91 = mux(_popc_in_T_48, UInt<65>(0h80000000000), _popc_in_T_90)
node _popc_in_T_92 = mux(_popc_in_T_47, UInt<65>(0h40000000000), _popc_in_T_91)
node _popc_in_T_93 = mux(_popc_in_T_46, UInt<65>(0h20000000000), _popc_in_T_92)
node _popc_in_T_94 = mux(_popc_in_T_45, UInt<65>(0h10000000000), _popc_in_T_93)
node _popc_in_T_95 = mux(_popc_in_T_44, UInt<65>(0h8000000000), _popc_in_T_94)
node _popc_in_T_96 = mux(_popc_in_T_43, UInt<65>(0h4000000000), _popc_in_T_95)
node _popc_in_T_97 = mux(_popc_in_T_42, UInt<65>(0h2000000000), _popc_in_T_96)
node _popc_in_T_98 = mux(_popc_in_T_41, UInt<65>(0h1000000000), _popc_in_T_97)
node _popc_in_T_99 = mux(_popc_in_T_40, UInt<65>(0h800000000), _popc_in_T_98)
node _popc_in_T_100 = mux(_popc_in_T_39, UInt<65>(0h400000000), _popc_in_T_99)
node _popc_in_T_101 = mux(_popc_in_T_38, UInt<65>(0h200000000), _popc_in_T_100)
node _popc_in_T_102 = mux(_popc_in_T_37, UInt<65>(0h100000000), _popc_in_T_101)
node _popc_in_T_103 = mux(_popc_in_T_36, UInt<65>(0h80000000), _popc_in_T_102)
node _popc_in_T_104 = mux(_popc_in_T_35, UInt<65>(0h40000000), _popc_in_T_103)
node _popc_in_T_105 = mux(_popc_in_T_34, UInt<65>(0h20000000), _popc_in_T_104)
node _popc_in_T_106 = mux(_popc_in_T_33, UInt<65>(0h10000000), _popc_in_T_105)
node _popc_in_T_107 = mux(_popc_in_T_32, UInt<65>(0h8000000), _popc_in_T_106)
node _popc_in_T_108 = mux(_popc_in_T_31, UInt<65>(0h4000000), _popc_in_T_107)
node _popc_in_T_109 = mux(_popc_in_T_30, UInt<65>(0h2000000), _popc_in_T_108)
node _popc_in_T_110 = mux(_popc_in_T_29, UInt<65>(0h1000000), _popc_in_T_109)
node _popc_in_T_111 = mux(_popc_in_T_28, UInt<65>(0h800000), _popc_in_T_110)
node _popc_in_T_112 = mux(_popc_in_T_27, UInt<65>(0h400000), _popc_in_T_111)
node _popc_in_T_113 = mux(_popc_in_T_26, UInt<65>(0h200000), _popc_in_T_112)
node _popc_in_T_114 = mux(_popc_in_T_25, UInt<65>(0h100000), _popc_in_T_113)
node _popc_in_T_115 = mux(_popc_in_T_24, UInt<65>(0h80000), _popc_in_T_114)
node _popc_in_T_116 = mux(_popc_in_T_23, UInt<65>(0h40000), _popc_in_T_115)
node _popc_in_T_117 = mux(_popc_in_T_22, UInt<65>(0h20000), _popc_in_T_116)
node _popc_in_T_118 = mux(_popc_in_T_21, UInt<65>(0h10000), _popc_in_T_117)
node _popc_in_T_119 = mux(_popc_in_T_20, UInt<65>(0h8000), _popc_in_T_118)
node _popc_in_T_120 = mux(_popc_in_T_19, UInt<65>(0h4000), _popc_in_T_119)
node _popc_in_T_121 = mux(_popc_in_T_18, UInt<65>(0h2000), _popc_in_T_120)
node _popc_in_T_122 = mux(_popc_in_T_17, UInt<65>(0h1000), _popc_in_T_121)
node _popc_in_T_123 = mux(_popc_in_T_16, UInt<65>(0h800), _popc_in_T_122)
node _popc_in_T_124 = mux(_popc_in_T_15, UInt<65>(0h400), _popc_in_T_123)
node _popc_in_T_125 = mux(_popc_in_T_14, UInt<65>(0h200), _popc_in_T_124)
node _popc_in_T_126 = mux(_popc_in_T_13, UInt<65>(0h100), _popc_in_T_125)
node _popc_in_T_127 = mux(_popc_in_T_12, UInt<65>(0h80), _popc_in_T_126)
node _popc_in_T_128 = mux(_popc_in_T_11, UInt<65>(0h40), _popc_in_T_127)
node _popc_in_T_129 = mux(_popc_in_T_10, UInt<65>(0h20), _popc_in_T_128)
node _popc_in_T_130 = mux(_popc_in_T_9, UInt<65>(0h10), _popc_in_T_129)
node _popc_in_T_131 = mux(_popc_in_T_8, UInt<65>(0h8), _popc_in_T_130)
node _popc_in_T_132 = mux(_popc_in_T_7, UInt<65>(0h4), _popc_in_T_131)
node _popc_in_T_133 = mux(_popc_in_T_6, UInt<65>(0h2), _popc_in_T_132)
node _popc_in_T_134 = mux(_popc_in_T_5, UInt<65>(0h1), _popc_in_T_133)
node _popc_in_T_135 = sub(_popc_in_T_134, UInt<1>(0h1))
node _popc_in_T_136 = tail(_popc_in_T_135, 1)
node _popc_in_T_137 = mux(_popc_in_T, _popc_in_T_3, _popc_in_T_136)
node popc_in = bits(_popc_in_T_137, 63, 0)
node _count_T = bits(popc_in, 0, 0)
node _count_T_1 = bits(popc_in, 1, 1)
node _count_T_2 = bits(popc_in, 2, 2)
node _count_T_3 = bits(popc_in, 3, 3)
node _count_T_4 = bits(popc_in, 4, 4)
node _count_T_5 = bits(popc_in, 5, 5)
node _count_T_6 = bits(popc_in, 6, 6)
node _count_T_7 = bits(popc_in, 7, 7)
node _count_T_8 = bits(popc_in, 8, 8)
node _count_T_9 = bits(popc_in, 9, 9)
node _count_T_10 = bits(popc_in, 10, 10)
node _count_T_11 = bits(popc_in, 11, 11)
node _count_T_12 = bits(popc_in, 12, 12)
node _count_T_13 = bits(popc_in, 13, 13)
node _count_T_14 = bits(popc_in, 14, 14)
node _count_T_15 = bits(popc_in, 15, 15)
node _count_T_16 = bits(popc_in, 16, 16)
node _count_T_17 = bits(popc_in, 17, 17)
node _count_T_18 = bits(popc_in, 18, 18)
node _count_T_19 = bits(popc_in, 19, 19)
node _count_T_20 = bits(popc_in, 20, 20)
node _count_T_21 = bits(popc_in, 21, 21)
node _count_T_22 = bits(popc_in, 22, 22)
node _count_T_23 = bits(popc_in, 23, 23)
node _count_T_24 = bits(popc_in, 24, 24)
node _count_T_25 = bits(popc_in, 25, 25)
node _count_T_26 = bits(popc_in, 26, 26)
node _count_T_27 = bits(popc_in, 27, 27)
node _count_T_28 = bits(popc_in, 28, 28)
node _count_T_29 = bits(popc_in, 29, 29)
node _count_T_30 = bits(popc_in, 30, 30)
node _count_T_31 = bits(popc_in, 31, 31)
node _count_T_32 = bits(popc_in, 32, 32)
node _count_T_33 = bits(popc_in, 33, 33)
node _count_T_34 = bits(popc_in, 34, 34)
node _count_T_35 = bits(popc_in, 35, 35)
node _count_T_36 = bits(popc_in, 36, 36)
node _count_T_37 = bits(popc_in, 37, 37)
node _count_T_38 = bits(popc_in, 38, 38)
node _count_T_39 = bits(popc_in, 39, 39)
node _count_T_40 = bits(popc_in, 40, 40)
node _count_T_41 = bits(popc_in, 41, 41)
node _count_T_42 = bits(popc_in, 42, 42)
node _count_T_43 = bits(popc_in, 43, 43)
node _count_T_44 = bits(popc_in, 44, 44)
node _count_T_45 = bits(popc_in, 45, 45)
node _count_T_46 = bits(popc_in, 46, 46)
node _count_T_47 = bits(popc_in, 47, 47)
node _count_T_48 = bits(popc_in, 48, 48)
node _count_T_49 = bits(popc_in, 49, 49)
node _count_T_50 = bits(popc_in, 50, 50)
node _count_T_51 = bits(popc_in, 51, 51)
node _count_T_52 = bits(popc_in, 52, 52)
node _count_T_53 = bits(popc_in, 53, 53)
node _count_T_54 = bits(popc_in, 54, 54)
node _count_T_55 = bits(popc_in, 55, 55)
node _count_T_56 = bits(popc_in, 56, 56)
node _count_T_57 = bits(popc_in, 57, 57)
node _count_T_58 = bits(popc_in, 58, 58)
node _count_T_59 = bits(popc_in, 59, 59)
node _count_T_60 = bits(popc_in, 60, 60)
node _count_T_61 = bits(popc_in, 61, 61)
node _count_T_62 = bits(popc_in, 62, 62)
node _count_T_63 = bits(popc_in, 63, 63)
node _count_T_64 = add(_count_T, _count_T_1)
node _count_T_65 = bits(_count_T_64, 1, 0)
node _count_T_66 = add(_count_T_2, _count_T_3)
node _count_T_67 = bits(_count_T_66, 1, 0)
node _count_T_68 = add(_count_T_65, _count_T_67)
node _count_T_69 = bits(_count_T_68, 2, 0)
node _count_T_70 = add(_count_T_4, _count_T_5)
node _count_T_71 = bits(_count_T_70, 1, 0)
node _count_T_72 = add(_count_T_6, _count_T_7)
node _count_T_73 = bits(_count_T_72, 1, 0)
node _count_T_74 = add(_count_T_71, _count_T_73)
node _count_T_75 = bits(_count_T_74, 2, 0)
node _count_T_76 = add(_count_T_69, _count_T_75)
node _count_T_77 = bits(_count_T_76, 3, 0)
node _count_T_78 = add(_count_T_8, _count_T_9)
node _count_T_79 = bits(_count_T_78, 1, 0)
node _count_T_80 = add(_count_T_10, _count_T_11)
node _count_T_81 = bits(_count_T_80, 1, 0)
node _count_T_82 = add(_count_T_79, _count_T_81)
node _count_T_83 = bits(_count_T_82, 2, 0)
node _count_T_84 = add(_count_T_12, _count_T_13)
node _count_T_85 = bits(_count_T_84, 1, 0)
node _count_T_86 = add(_count_T_14, _count_T_15)
node _count_T_87 = bits(_count_T_86, 1, 0)
node _count_T_88 = add(_count_T_85, _count_T_87)
node _count_T_89 = bits(_count_T_88, 2, 0)
node _count_T_90 = add(_count_T_83, _count_T_89)
node _count_T_91 = bits(_count_T_90, 3, 0)
node _count_T_92 = add(_count_T_77, _count_T_91)
node _count_T_93 = bits(_count_T_92, 4, 0)
node _count_T_94 = add(_count_T_16, _count_T_17)
node _count_T_95 = bits(_count_T_94, 1, 0)
node _count_T_96 = add(_count_T_18, _count_T_19)
node _count_T_97 = bits(_count_T_96, 1, 0)
node _count_T_98 = add(_count_T_95, _count_T_97)
node _count_T_99 = bits(_count_T_98, 2, 0)
node _count_T_100 = add(_count_T_20, _count_T_21)
node _count_T_101 = bits(_count_T_100, 1, 0)
node _count_T_102 = add(_count_T_22, _count_T_23)
node _count_T_103 = bits(_count_T_102, 1, 0)
node _count_T_104 = add(_count_T_101, _count_T_103)
node _count_T_105 = bits(_count_T_104, 2, 0)
node _count_T_106 = add(_count_T_99, _count_T_105)
node _count_T_107 = bits(_count_T_106, 3, 0)
node _count_T_108 = add(_count_T_24, _count_T_25)
node _count_T_109 = bits(_count_T_108, 1, 0)
node _count_T_110 = add(_count_T_26, _count_T_27)
node _count_T_111 = bits(_count_T_110, 1, 0)
node _count_T_112 = add(_count_T_109, _count_T_111)
node _count_T_113 = bits(_count_T_112, 2, 0)
node _count_T_114 = add(_count_T_28, _count_T_29)
node _count_T_115 = bits(_count_T_114, 1, 0)
node _count_T_116 = add(_count_T_30, _count_T_31)
node _count_T_117 = bits(_count_T_116, 1, 0)
node _count_T_118 = add(_count_T_115, _count_T_117)
node _count_T_119 = bits(_count_T_118, 2, 0)
node _count_T_120 = add(_count_T_113, _count_T_119)
node _count_T_121 = bits(_count_T_120, 3, 0)
node _count_T_122 = add(_count_T_107, _count_T_121)
node _count_T_123 = bits(_count_T_122, 4, 0)
node _count_T_124 = add(_count_T_93, _count_T_123)
node _count_T_125 = bits(_count_T_124, 5, 0)
node _count_T_126 = add(_count_T_32, _count_T_33)
node _count_T_127 = bits(_count_T_126, 1, 0)
node _count_T_128 = add(_count_T_34, _count_T_35)
node _count_T_129 = bits(_count_T_128, 1, 0)
node _count_T_130 = add(_count_T_127, _count_T_129)
node _count_T_131 = bits(_count_T_130, 2, 0)
node _count_T_132 = add(_count_T_36, _count_T_37)
node _count_T_133 = bits(_count_T_132, 1, 0)
node _count_T_134 = add(_count_T_38, _count_T_39)
node _count_T_135 = bits(_count_T_134, 1, 0)
node _count_T_136 = add(_count_T_133, _count_T_135)
node _count_T_137 = bits(_count_T_136, 2, 0)
node _count_T_138 = add(_count_T_131, _count_T_137)
node _count_T_139 = bits(_count_T_138, 3, 0)
node _count_T_140 = add(_count_T_40, _count_T_41)
node _count_T_141 = bits(_count_T_140, 1, 0)
node _count_T_142 = add(_count_T_42, _count_T_43)
node _count_T_143 = bits(_count_T_142, 1, 0)
node _count_T_144 = add(_count_T_141, _count_T_143)
node _count_T_145 = bits(_count_T_144, 2, 0)
node _count_T_146 = add(_count_T_44, _count_T_45)
node _count_T_147 = bits(_count_T_146, 1, 0)
node _count_T_148 = add(_count_T_46, _count_T_47)
node _count_T_149 = bits(_count_T_148, 1, 0)
node _count_T_150 = add(_count_T_147, _count_T_149)
node _count_T_151 = bits(_count_T_150, 2, 0)
node _count_T_152 = add(_count_T_145, _count_T_151)
node _count_T_153 = bits(_count_T_152, 3, 0)
node _count_T_154 = add(_count_T_139, _count_T_153)
node _count_T_155 = bits(_count_T_154, 4, 0)
node _count_T_156 = add(_count_T_48, _count_T_49)
node _count_T_157 = bits(_count_T_156, 1, 0)
node _count_T_158 = add(_count_T_50, _count_T_51)
node _count_T_159 = bits(_count_T_158, 1, 0)
node _count_T_160 = add(_count_T_157, _count_T_159)
node _count_T_161 = bits(_count_T_160, 2, 0)
node _count_T_162 = add(_count_T_52, _count_T_53)
node _count_T_163 = bits(_count_T_162, 1, 0)
node _count_T_164 = add(_count_T_54, _count_T_55)
node _count_T_165 = bits(_count_T_164, 1, 0)
node _count_T_166 = add(_count_T_163, _count_T_165)
node _count_T_167 = bits(_count_T_166, 2, 0)
node _count_T_168 = add(_count_T_161, _count_T_167)
node _count_T_169 = bits(_count_T_168, 3, 0)
node _count_T_170 = add(_count_T_56, _count_T_57)
node _count_T_171 = bits(_count_T_170, 1, 0)
node _count_T_172 = add(_count_T_58, _count_T_59)
node _count_T_173 = bits(_count_T_172, 1, 0)
node _count_T_174 = add(_count_T_171, _count_T_173)
node _count_T_175 = bits(_count_T_174, 2, 0)
node _count_T_176 = add(_count_T_60, _count_T_61)
node _count_T_177 = bits(_count_T_176, 1, 0)
node _count_T_178 = add(_count_T_62, _count_T_63)
node _count_T_179 = bits(_count_T_178, 1, 0)
node _count_T_180 = add(_count_T_177, _count_T_179)
node _count_T_181 = bits(_count_T_180, 2, 0)
node _count_T_182 = add(_count_T_175, _count_T_181)
node _count_T_183 = bits(_count_T_182, 3, 0)
node _count_T_184 = add(_count_T_169, _count_T_183)
node _count_T_185 = bits(_count_T_184, 4, 0)
node _count_T_186 = add(_count_T_155, _count_T_185)
node _count_T_187 = bits(_count_T_186, 5, 0)
node _count_T_188 = add(_count_T_125, _count_T_187)
node count = bits(_count_T_188, 6, 0)
wire in1_bytes : UInt<8>[8]
wire _in1_bytes_WIRE : UInt<64>
connect _in1_bytes_WIRE, io.in1
node _in1_bytes_T = bits(_in1_bytes_WIRE, 7, 0)
connect in1_bytes[0], _in1_bytes_T
node _in1_bytes_T_1 = bits(_in1_bytes_WIRE, 15, 8)
connect in1_bytes[1], _in1_bytes_T_1
node _in1_bytes_T_2 = bits(_in1_bytes_WIRE, 23, 16)
connect in1_bytes[2], _in1_bytes_T_2
node _in1_bytes_T_3 = bits(_in1_bytes_WIRE, 31, 24)
connect in1_bytes[3], _in1_bytes_T_3
node _in1_bytes_T_4 = bits(_in1_bytes_WIRE, 39, 32)
connect in1_bytes[4], _in1_bytes_T_4
node _in1_bytes_T_5 = bits(_in1_bytes_WIRE, 47, 40)
connect in1_bytes[5], _in1_bytes_T_5
node _in1_bytes_T_6 = bits(_in1_bytes_WIRE, 55, 48)
connect in1_bytes[6], _in1_bytes_T_6
node _in1_bytes_T_7 = bits(_in1_bytes_WIRE, 63, 56)
connect in1_bytes[7], _in1_bytes_T_7
node _orcb_T = neq(in1_bytes[0], UInt<1>(0h0))
node _orcb_T_1 = mux(_orcb_T, UInt<8>(0hff), UInt<8>(0h0))
node _orcb_T_2 = neq(in1_bytes[1], UInt<1>(0h0))
node _orcb_T_3 = mux(_orcb_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _orcb_T_4 = neq(in1_bytes[2], UInt<1>(0h0))
node _orcb_T_5 = mux(_orcb_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _orcb_T_6 = neq(in1_bytes[3], UInt<1>(0h0))
node _orcb_T_7 = mux(_orcb_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _orcb_T_8 = neq(in1_bytes[4], UInt<1>(0h0))
node _orcb_T_9 = mux(_orcb_T_8, UInt<8>(0hff), UInt<8>(0h0))
node _orcb_T_10 = neq(in1_bytes[5], UInt<1>(0h0))
node _orcb_T_11 = mux(_orcb_T_10, UInt<8>(0hff), UInt<8>(0h0))
node _orcb_T_12 = neq(in1_bytes[6], UInt<1>(0h0))
node _orcb_T_13 = mux(_orcb_T_12, UInt<8>(0hff), UInt<8>(0h0))
node _orcb_T_14 = neq(in1_bytes[7], UInt<1>(0h0))
node _orcb_T_15 = mux(_orcb_T_14, UInt<8>(0hff), UInt<8>(0h0))
wire _orcb_WIRE : UInt<8>[8]
connect _orcb_WIRE[0], _orcb_T_1
connect _orcb_WIRE[1], _orcb_T_3
connect _orcb_WIRE[2], _orcb_T_5
connect _orcb_WIRE[3], _orcb_T_7
connect _orcb_WIRE[4], _orcb_T_9
connect _orcb_WIRE[5], _orcb_T_11
connect _orcb_WIRE[6], _orcb_T_13
connect _orcb_WIRE[7], _orcb_T_15
node orcb_lo_lo = cat(_orcb_WIRE[1], _orcb_WIRE[0])
node orcb_lo_hi = cat(_orcb_WIRE[3], _orcb_WIRE[2])
node orcb_lo = cat(orcb_lo_hi, orcb_lo_lo)
node orcb_hi_lo = cat(_orcb_WIRE[5], _orcb_WIRE[4])
node orcb_hi_hi = cat(_orcb_WIRE[7], _orcb_WIRE[6])
node orcb_hi = cat(orcb_hi_hi, orcb_hi_lo)
node orcb = cat(orcb_hi, orcb_lo)
wire _rev8_WIRE : UInt<8>[8]
connect _rev8_WIRE[0], in1_bytes[7]
connect _rev8_WIRE[1], in1_bytes[6]
connect _rev8_WIRE[2], in1_bytes[5]
connect _rev8_WIRE[3], in1_bytes[4]
connect _rev8_WIRE[4], in1_bytes[3]
connect _rev8_WIRE[5], in1_bytes[2]
connect _rev8_WIRE[6], in1_bytes[1]
connect _rev8_WIRE[7], in1_bytes[0]
node rev8_lo_lo = cat(_rev8_WIRE[1], _rev8_WIRE[0])
node rev8_lo_hi = cat(_rev8_WIRE[3], _rev8_WIRE[2])
node rev8_lo = cat(rev8_lo_hi, rev8_lo_lo)
node rev8_hi_lo = cat(_rev8_WIRE[5], _rev8_WIRE[4])
node rev8_hi_hi = cat(_rev8_WIRE[7], _rev8_WIRE[6])
node rev8_hi = cat(rev8_hi_hi, rev8_hi_lo)
node rev8 = cat(rev8_hi, rev8_lo)
node _unary_T = bits(io.in2, 11, 0)
node _unary_T_1 = bits(io.in1, 15, 0)
node _unary_T_2 = bits(io.in1, 7, 7)
node _unary_T_3 = mux(_unary_T_2, UInt<56>(0hffffffffffffff), UInt<56>(0h0))
node _unary_T_4 = bits(io.in1, 7, 0)
node _unary_T_5 = cat(_unary_T_3, _unary_T_4)
node _unary_T_6 = bits(io.in1, 15, 15)
node _unary_T_7 = mux(_unary_T_6, UInt<48>(0hffffffffffff), UInt<48>(0h0))
node _unary_T_8 = bits(io.in1, 15, 0)
node _unary_T_9 = cat(_unary_T_7, _unary_T_8)
node _unary_T_10 = eq(UInt<10>(0h287), _unary_T)
node _unary_T_11 = mux(_unary_T_10, orcb, count)
node _unary_T_12 = eq(UInt<11>(0h6b8), _unary_T)
node _unary_T_13 = mux(_unary_T_12, rev8, _unary_T_11)
node _unary_T_14 = eq(UInt<8>(0h80), _unary_T)
node _unary_T_15 = mux(_unary_T_14, _unary_T_1, _unary_T_13)
node _unary_T_16 = eq(UInt<11>(0h604), _unary_T)
node _unary_T_17 = mux(_unary_T_16, _unary_T_5, _unary_T_15)
node _unary_T_18 = eq(UInt<11>(0h605), _unary_T)
node unary = mux(_unary_T_18, _unary_T_9, _unary_T_17)
node maxmin_out = mux(io.cmp_out, io.in2, io.in1)
node _rot_shamt_T = eq(io.dw, UInt<1>(0h0))
node _rot_shamt_T_1 = mux(_rot_shamt_T, UInt<6>(0h20), UInt<7>(0h40))
node _rot_shamt_T_2 = sub(_rot_shamt_T_1, shamt)
node rot_shamt = tail(_rot_shamt_T_2, 1)
node _rotin_T = bits(io.fn, 0, 0)
node _rotin_T_1 = shl(UInt<32>(0hffffffff), 32)
node _rotin_T_2 = xor(UInt<64>(0hffffffffffffffff), _rotin_T_1)
node _rotin_T_3 = shr(shin_r, 32)
node _rotin_T_4 = and(_rotin_T_3, _rotin_T_2)
node _rotin_T_5 = bits(shin_r, 31, 0)
node _rotin_T_6 = shl(_rotin_T_5, 32)
node _rotin_T_7 = not(_rotin_T_2)
node _rotin_T_8 = and(_rotin_T_6, _rotin_T_7)
node _rotin_T_9 = or(_rotin_T_4, _rotin_T_8)
node _rotin_T_10 = bits(_rotin_T_2, 47, 0)
node _rotin_T_11 = shl(_rotin_T_10, 16)
node _rotin_T_12 = xor(_rotin_T_2, _rotin_T_11)
node _rotin_T_13 = shr(_rotin_T_9, 16)
node _rotin_T_14 = and(_rotin_T_13, _rotin_T_12)
node _rotin_T_15 = bits(_rotin_T_9, 47, 0)
node _rotin_T_16 = shl(_rotin_T_15, 16)
node _rotin_T_17 = not(_rotin_T_12)
node _rotin_T_18 = and(_rotin_T_16, _rotin_T_17)
node _rotin_T_19 = or(_rotin_T_14, _rotin_T_18)
node _rotin_T_20 = bits(_rotin_T_12, 55, 0)
node _rotin_T_21 = shl(_rotin_T_20, 8)
node _rotin_T_22 = xor(_rotin_T_12, _rotin_T_21)
node _rotin_T_23 = shr(_rotin_T_19, 8)
node _rotin_T_24 = and(_rotin_T_23, _rotin_T_22)
node _rotin_T_25 = bits(_rotin_T_19, 55, 0)
node _rotin_T_26 = shl(_rotin_T_25, 8)
node _rotin_T_27 = not(_rotin_T_22)
node _rotin_T_28 = and(_rotin_T_26, _rotin_T_27)
node _rotin_T_29 = or(_rotin_T_24, _rotin_T_28)
node _rotin_T_30 = bits(_rotin_T_22, 59, 0)
node _rotin_T_31 = shl(_rotin_T_30, 4)
node _rotin_T_32 = xor(_rotin_T_22, _rotin_T_31)
node _rotin_T_33 = shr(_rotin_T_29, 4)
node _rotin_T_34 = and(_rotin_T_33, _rotin_T_32)
node _rotin_T_35 = bits(_rotin_T_29, 59, 0)
node _rotin_T_36 = shl(_rotin_T_35, 4)
node _rotin_T_37 = not(_rotin_T_32)
node _rotin_T_38 = and(_rotin_T_36, _rotin_T_37)
node _rotin_T_39 = or(_rotin_T_34, _rotin_T_38)
node _rotin_T_40 = bits(_rotin_T_32, 61, 0)
node _rotin_T_41 = shl(_rotin_T_40, 2)
node _rotin_T_42 = xor(_rotin_T_32, _rotin_T_41)
node _rotin_T_43 = shr(_rotin_T_39, 2)
node _rotin_T_44 = and(_rotin_T_43, _rotin_T_42)
node _rotin_T_45 = bits(_rotin_T_39, 61, 0)
node _rotin_T_46 = shl(_rotin_T_45, 2)
node _rotin_T_47 = not(_rotin_T_42)
node _rotin_T_48 = and(_rotin_T_46, _rotin_T_47)
node _rotin_T_49 = or(_rotin_T_44, _rotin_T_48)
node _rotin_T_50 = bits(_rotin_T_42, 62, 0)
node _rotin_T_51 = shl(_rotin_T_50, 1)
node _rotin_T_52 = xor(_rotin_T_42, _rotin_T_51)
node _rotin_T_53 = shr(_rotin_T_49, 1)
node _rotin_T_54 = and(_rotin_T_53, _rotin_T_52)
node _rotin_T_55 = bits(_rotin_T_49, 62, 0)
node _rotin_T_56 = shl(_rotin_T_55, 1)
node _rotin_T_57 = not(_rotin_T_52)
node _rotin_T_58 = and(_rotin_T_56, _rotin_T_57)
node _rotin_T_59 = or(_rotin_T_54, _rotin_T_58)
node rotin = mux(_rotin_T, shin_r, _rotin_T_59)
node _rotout_r_T = dshr(rotin, rot_shamt)
node rotout_r = bits(_rotout_r_T, 63, 0)
node _rotout_l_T = shl(UInt<32>(0hffffffff), 32)
node _rotout_l_T_1 = xor(UInt<64>(0hffffffffffffffff), _rotout_l_T)
node _rotout_l_T_2 = shr(rotout_r, 32)
node _rotout_l_T_3 = and(_rotout_l_T_2, _rotout_l_T_1)
node _rotout_l_T_4 = bits(rotout_r, 31, 0)
node _rotout_l_T_5 = shl(_rotout_l_T_4, 32)
node _rotout_l_T_6 = not(_rotout_l_T_1)
node _rotout_l_T_7 = and(_rotout_l_T_5, _rotout_l_T_6)
node _rotout_l_T_8 = or(_rotout_l_T_3, _rotout_l_T_7)
node _rotout_l_T_9 = bits(_rotout_l_T_1, 47, 0)
node _rotout_l_T_10 = shl(_rotout_l_T_9, 16)
node _rotout_l_T_11 = xor(_rotout_l_T_1, _rotout_l_T_10)
node _rotout_l_T_12 = shr(_rotout_l_T_8, 16)
node _rotout_l_T_13 = and(_rotout_l_T_12, _rotout_l_T_11)
node _rotout_l_T_14 = bits(_rotout_l_T_8, 47, 0)
node _rotout_l_T_15 = shl(_rotout_l_T_14, 16)
node _rotout_l_T_16 = not(_rotout_l_T_11)
node _rotout_l_T_17 = and(_rotout_l_T_15, _rotout_l_T_16)
node _rotout_l_T_18 = or(_rotout_l_T_13, _rotout_l_T_17)
node _rotout_l_T_19 = bits(_rotout_l_T_11, 55, 0)
node _rotout_l_T_20 = shl(_rotout_l_T_19, 8)
node _rotout_l_T_21 = xor(_rotout_l_T_11, _rotout_l_T_20)
node _rotout_l_T_22 = shr(_rotout_l_T_18, 8)
node _rotout_l_T_23 = and(_rotout_l_T_22, _rotout_l_T_21)
node _rotout_l_T_24 = bits(_rotout_l_T_18, 55, 0)
node _rotout_l_T_25 = shl(_rotout_l_T_24, 8)
node _rotout_l_T_26 = not(_rotout_l_T_21)
node _rotout_l_T_27 = and(_rotout_l_T_25, _rotout_l_T_26)
node _rotout_l_T_28 = or(_rotout_l_T_23, _rotout_l_T_27)
node _rotout_l_T_29 = bits(_rotout_l_T_21, 59, 0)
node _rotout_l_T_30 = shl(_rotout_l_T_29, 4)
node _rotout_l_T_31 = xor(_rotout_l_T_21, _rotout_l_T_30)
node _rotout_l_T_32 = shr(_rotout_l_T_28, 4)
node _rotout_l_T_33 = and(_rotout_l_T_32, _rotout_l_T_31)
node _rotout_l_T_34 = bits(_rotout_l_T_28, 59, 0)
node _rotout_l_T_35 = shl(_rotout_l_T_34, 4)
node _rotout_l_T_36 = not(_rotout_l_T_31)
node _rotout_l_T_37 = and(_rotout_l_T_35, _rotout_l_T_36)
node _rotout_l_T_38 = or(_rotout_l_T_33, _rotout_l_T_37)
node _rotout_l_T_39 = bits(_rotout_l_T_31, 61, 0)
node _rotout_l_T_40 = shl(_rotout_l_T_39, 2)
node _rotout_l_T_41 = xor(_rotout_l_T_31, _rotout_l_T_40)
node _rotout_l_T_42 = shr(_rotout_l_T_38, 2)
node _rotout_l_T_43 = and(_rotout_l_T_42, _rotout_l_T_41)
node _rotout_l_T_44 = bits(_rotout_l_T_38, 61, 0)
node _rotout_l_T_45 = shl(_rotout_l_T_44, 2)
node _rotout_l_T_46 = not(_rotout_l_T_41)
node _rotout_l_T_47 = and(_rotout_l_T_45, _rotout_l_T_46)
node _rotout_l_T_48 = or(_rotout_l_T_43, _rotout_l_T_47)
node _rotout_l_T_49 = bits(_rotout_l_T_41, 62, 0)
node _rotout_l_T_50 = shl(_rotout_l_T_49, 1)
node _rotout_l_T_51 = xor(_rotout_l_T_41, _rotout_l_T_50)
node _rotout_l_T_52 = shr(_rotout_l_T_48, 1)
node _rotout_l_T_53 = and(_rotout_l_T_52, _rotout_l_T_51)
node _rotout_l_T_54 = bits(_rotout_l_T_48, 62, 0)
node _rotout_l_T_55 = shl(_rotout_l_T_54, 1)
node _rotout_l_T_56 = not(_rotout_l_T_51)
node _rotout_l_T_57 = and(_rotout_l_T_55, _rotout_l_T_56)
node rotout_l = or(_rotout_l_T_53, _rotout_l_T_57)
node _rotout_T = bits(io.fn, 0, 0)
node _rotout_T_1 = mux(_rotout_T, rotout_r, rotout_l)
node _rotout_T_2 = bits(io.fn, 0, 0)
node _rotout_T_3 = mux(_rotout_T_2, shout_l, shout_r)
node rotout = or(_rotout_T_1, _rotout_T_3)
node _out_T = eq(UInt<1>(0h0), io.fn)
node _out_T_1 = mux(_out_T, io.adder_out, shift_logic)
node _out_T_2 = eq(UInt<4>(0ha), io.fn)
node out = mux(_out_T_2, io.adder_out, _out_T_1)
connect io.out, out
node _T_1 = eq(io.dw, UInt<1>(0h0))
when _T_1 :
node _io_out_T = bits(out, 31, 31)
node _io_out_T_1 = mux(_io_out_T, UInt<32>(0hffffffff), UInt<32>(0h0))
node _io_out_T_2 = bits(out, 31, 0)
node _io_out_T_3 = cat(_io_out_T_1, _io_out_T_2)
connect io.out, _io_out_T_3 | module ALU_4( // @[ALU.scala:83:7]
input clock, // @[ALU.scala:83:7]
input reset, // @[ALU.scala:83:7]
input io_dw, // @[ALU.scala:72:14]
input [4:0] io_fn, // @[ALU.scala:72:14]
input [63:0] io_in2, // @[ALU.scala:72:14]
input [63:0] io_in1, // @[ALU.scala:72:14]
output [63:0] io_out // @[ALU.scala:72:14]
);
wire [7:0] in1_bytes_6; // @[ALU.scala:140:34]
wire [7:0] in1_bytes_5; // @[ALU.scala:140:34]
wire [7:0] in1_bytes_4; // @[ALU.scala:140:34]
wire [7:0] in1_bytes_3; // @[ALU.scala:140:34]
wire [7:0] in1_bytes_2; // @[ALU.scala:140:34]
wire [7:0] in1_bytes_1; // @[ALU.scala:140:34]
wire [7:0] in1_bytes_0; // @[ALU.scala:140:34]
wire io_dw_0 = io_dw; // @[ALU.scala:83:7]
wire [4:0] io_fn_0 = io_fn; // @[ALU.scala:83:7]
wire [63:0] io_in2_0 = io_in2; // @[ALU.scala:83:7]
wire [63:0] io_in1_0 = io_in1; // @[ALU.scala:83:7]
wire _bext_mask_T_1 = 1'h0; // @[ALU.scala:122:43]
wire [63:0] _bext_mask_T_2 = 64'hFFFFFFFFFFFFFFFF; // @[ALU.scala:122:70]
wire [63:0] bext_mask = 64'hFFFFFFFFFFFFFFFF; // @[ALU.scala:122:22]
wire [31:0] _tz_in_T_67 = 32'hFFFF; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_66 = 32'hFFFF0000; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_72 = 32'hFFFF0000; // @[ALU.scala:134:26]
wire [23:0] _tz_in_T_75 = 24'hFFFF; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_76 = 32'hFFFF00; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_77 = 32'hFF00FF; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_82 = 32'hFF00FF00; // @[ALU.scala:134:26]
wire [27:0] _tz_in_T_85 = 28'hFF00FF; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_86 = 32'hFF00FF0; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_87 = 32'hF0F0F0F; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_92 = 32'hF0F0F0F0; // @[ALU.scala:134:26]
wire [29:0] _tz_in_T_95 = 30'hF0F0F0F; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_96 = 32'h3C3C3C3C; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_97 = 32'h33333333; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_102 = 32'hCCCCCCCC; // @[ALU.scala:134:26]
wire [30:0] _tz_in_T_105 = 31'h33333333; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_106 = 32'h66666666; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_107 = 32'h55555555; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_112 = 32'hAAAAAAAA; // @[ALU.scala:134:26]
wire [63:0] _shin_T_9 = 64'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_1 = 64'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_5 = 64'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_2 = 64'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_1 = 64'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_8 = 64'hFFFFFFFF00000000; // @[ALU.scala:106:46]
wire [63:0] _shin_T_14 = 64'hFFFFFFFF00000000; // @[ALU.scala:106:46]
wire [63:0] _shout_l_T = 64'hFFFFFFFF00000000; // @[ALU.scala:108:24]
wire [63:0] _shout_l_T_6 = 64'hFFFFFFFF00000000; // @[ALU.scala:108:24]
wire [63:0] _tz_in_T_4 = 64'hFFFFFFFF00000000; // @[ALU.scala:132:19]
wire [63:0] _tz_in_T_10 = 64'hFFFFFFFF00000000; // @[ALU.scala:132:19]
wire [63:0] _rotin_T_1 = 64'hFFFFFFFF00000000; // @[ALU.scala:156:44]
wire [63:0] _rotin_T_7 = 64'hFFFFFFFF00000000; // @[ALU.scala:156:44]
wire [63:0] _rotout_l_T = 64'hFFFFFFFF00000000; // @[ALU.scala:158:25]
wire [63:0] _rotout_l_T_6 = 64'hFFFFFFFF00000000; // @[ALU.scala:158:25]
wire [47:0] _shin_T_17 = 48'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [47:0] _shout_l_T_9 = 48'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [47:0] _tz_in_T_13 = 48'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [47:0] _rotin_T_10 = 48'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [47:0] _rotout_l_T_9 = 48'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_18 = 64'hFFFFFFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_10 = 64'hFFFFFFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_14 = 64'hFFFFFFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_11 = 64'hFFFFFFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_10 = 64'hFFFFFFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_19 = 64'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_11 = 64'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_15 = 64'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_12 = 64'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_11 = 64'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_24 = 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_16 = 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_20 = 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_17 = 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_16 = 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [55:0] _shin_T_27 = 56'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [55:0] _shout_l_T_19 = 56'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [55:0] _tz_in_T_23 = 56'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [55:0] _rotin_T_20 = 56'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [55:0] _rotout_l_T_19 = 56'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_28 = 64'hFFFF0000FFFF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_20 = 64'hFFFF0000FFFF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_24 = 64'hFFFF0000FFFF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_21 = 64'hFFFF0000FFFF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_20 = 64'hFFFF0000FFFF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_29 = 64'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_21 = 64'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_25 = 64'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_22 = 64'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_21 = 64'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_34 = 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_26 = 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_30 = 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_27 = 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_26 = 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [59:0] _shin_T_37 = 60'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [59:0] _shout_l_T_29 = 60'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [59:0] _tz_in_T_33 = 60'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [59:0] _rotin_T_30 = 60'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [59:0] _rotout_l_T_29 = 60'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_38 = 64'hFF00FF00FF00FF0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_30 = 64'hFF00FF00FF00FF0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_34 = 64'hFF00FF00FF00FF0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_31 = 64'hFF00FF00FF00FF0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_30 = 64'hFF00FF00FF00FF0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_39 = 64'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_31 = 64'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_35 = 64'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_32 = 64'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_31 = 64'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_44 = 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_36 = 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_40 = 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_37 = 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_36 = 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [61:0] _shin_T_47 = 62'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [61:0] _shout_l_T_39 = 62'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [61:0] _tz_in_T_43 = 62'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [61:0] _rotin_T_40 = 62'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [61:0] _rotout_l_T_39 = 62'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_48 = 64'h3C3C3C3C3C3C3C3C; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_40 = 64'h3C3C3C3C3C3C3C3C; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_44 = 64'h3C3C3C3C3C3C3C3C; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_41 = 64'h3C3C3C3C3C3C3C3C; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_40 = 64'h3C3C3C3C3C3C3C3C; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_49 = 64'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_41 = 64'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_45 = 64'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_42 = 64'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_41 = 64'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_54 = 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_46 = 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_50 = 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_47 = 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_46 = 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [62:0] _shin_T_57 = 63'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [62:0] _shout_l_T_49 = 63'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [62:0] _tz_in_T_53 = 63'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [62:0] _rotin_T_50 = 63'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [62:0] _rotout_l_T_49 = 63'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_58 = 64'h6666666666666666; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_50 = 64'h6666666666666666; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_54 = 64'h6666666666666666; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_51 = 64'h6666666666666666; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_50 = 64'h6666666666666666; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_59 = 64'h5555555555555555; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_51 = 64'h5555555555555555; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_55 = 64'h5555555555555555; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_52 = 64'h5555555555555555; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_51 = 64'h5555555555555555; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_64 = 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_56 = 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_60 = 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_57 = 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_56 = 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire _shin_hi_T = io_dw_0; // @[ALU.scala:83:7, :102:31]
wire _shamt_T_1 = io_dw_0; // @[ALU.scala:83:7, :103:42]
wire [63:0] _in1_bytes_WIRE = io_in1_0; // @[ALU.scala:83:7, :140:34]
wire [63:0] _io_adder_out_T_4; // @[ALU.scala:88:36]
wire _io_cmp_out_T_5; // @[ALU.scala:94:36]
wire [63:0] io_out_0; // @[ALU.scala:83:7]
wire [63:0] io_adder_out; // @[ALU.scala:83:7]
wire io_cmp_out; // @[ALU.scala:83:7]
wire _in2_inv_T = io_fn_0[3]; // @[ALU.scala:58:29, :83:7]
wire _io_adder_out_T_2 = io_fn_0[3]; // @[ALU.scala:58:29, :83:7]
wire _io_cmp_out_T_1 = io_fn_0[3]; // @[ALU.scala:58:29, :63:30, :83:7]
wire _shin_hi_32_T = io_fn_0[3]; // @[ALU.scala:58:29, :83:7]
wire _shout_r_T = io_fn_0[3]; // @[ALU.scala:58:29, :83:7]
wire [63:0] _in2_inv_T_1 = ~io_in2_0; // @[ALU.scala:83:7, :85:35]
wire [63:0] in2_inv = _in2_inv_T ? _in2_inv_T_1 : io_in2_0; // @[ALU.scala:58:29, :83:7, :85:{20,35}]
wire [63:0] in1_xor_in2 = io_in1_0 ^ in2_inv; // @[ALU.scala:83:7, :85:20, :86:28]
wire [63:0] in1_and_in2 = io_in1_0 & in2_inv; // @[ALU.scala:83:7, :85:20, :87:28]
wire [64:0] _io_adder_out_T = {1'h0, io_in1_0} + {1'h0, in2_inv}; // @[ALU.scala:83:7, :85:20, :88:26]
wire [63:0] _io_adder_out_T_1 = _io_adder_out_T[63:0]; // @[ALU.scala:88:26]
wire [64:0] _io_adder_out_T_3 = {1'h0, _io_adder_out_T_1} + {64'h0, _io_adder_out_T_2}; // @[ALU.scala:58:29, :88:{26,36}]
assign _io_adder_out_T_4 = _io_adder_out_T_3[63:0]; // @[ALU.scala:88:36]
assign io_adder_out = _io_adder_out_T_4; // @[ALU.scala:83:7, :88:36]
wire _slt_T = io_in1_0[63]; // @[ALU.scala:83:7, :92:15]
wire _slt_T_6 = io_in1_0[63]; // @[ALU.scala:83:7, :92:15, :93:51]
wire _slt_T_1 = io_in2_0[63]; // @[ALU.scala:83:7, :92:34]
wire _slt_T_5 = io_in2_0[63]; // @[ALU.scala:83:7, :92:34, :93:35]
wire _slt_T_2 = _slt_T == _slt_T_1; // @[ALU.scala:92:{15,24,34}]
wire _slt_T_3 = io_adder_out[63]; // @[ALU.scala:83:7, :92:56]
wire _slt_T_4 = io_fn_0[1]; // @[ALU.scala:61:35, :83:7]
wire _slt_T_7 = _slt_T_4 ? _slt_T_5 : _slt_T_6; // @[ALU.scala:61:35, :93:{8,35,51}]
wire slt = _slt_T_2 ? _slt_T_3 : _slt_T_7; // @[ALU.scala:92:{8,24,56}, :93:8]
wire _io_cmp_out_T = io_fn_0[0]; // @[ALU.scala:62:35, :83:7]
wire _rotin_T = io_fn_0[0]; // @[ALU.scala:62:35, :83:7, :156:24]
wire _rotout_T = io_fn_0[0]; // @[ALU.scala:62:35, :83:7, :159:25]
wire _rotout_T_2 = io_fn_0[0]; // @[ALU.scala:62:35, :83:7, :159:61]
wire _io_cmp_out_T_2 = ~_io_cmp_out_T_1; // @[ALU.scala:63:{26,30}]
wire _io_cmp_out_T_3 = in1_xor_in2 == 64'h0; // @[ALU.scala:86:28, :94:68]
wire _io_cmp_out_T_4 = _io_cmp_out_T_2 ? _io_cmp_out_T_3 : slt; // @[ALU.scala:63:26, :92:8, :94:{41,68}]
assign _io_cmp_out_T_5 = _io_cmp_out_T ^ _io_cmp_out_T_4; // @[ALU.scala:62:35, :94:{36,41}]
assign io_cmp_out = _io_cmp_out_T_5; // @[ALU.scala:83:7, :94:36]
wire _shin_hi_32_T_1 = io_in1_0[31]; // @[ALU.scala:83:7, :101:55]
wire _shin_hi_32_T_2 = _shin_hi_32_T & _shin_hi_32_T_1; // @[ALU.scala:58:29, :101:{46,55}]
wire [31:0] shin_hi_32 = {32{_shin_hi_32_T_2}}; // @[ALU.scala:101:{28,46}]
wire [31:0] _shin_hi_T_1 = io_in1_0[63:32]; // @[ALU.scala:83:7, :102:48]
wire [31:0] _tz_in_T_6 = io_in1_0[63:32]; // @[ALU.scala:83:7, :102:48, :132:19]
wire [31:0] shin_hi = _shin_hi_T ? _shin_hi_T_1 : shin_hi_32; // @[ALU.scala:101:28, :102:{24,31,48}]
wire _shamt_T = io_in2_0[5]; // @[ALU.scala:83:7, :103:29]
wire _shamt_T_2 = _shamt_T & _shamt_T_1; // @[ALU.scala:103:{29,33,42}]
wire [4:0] _shamt_T_3 = io_in2_0[4:0]; // @[ALU.scala:83:7, :103:60]
wire [5:0] shamt = {_shamt_T_2, _shamt_T_3}; // @[ALU.scala:103:{22,33,60}]
wire [31:0] _tz_in_T_8 = io_in1_0[31:0]; // @[ALU.scala:83:7, :104:34, :132:19]
wire [31:0] _tz_in_T_63 = io_in1_0[31:0]; // @[ALU.scala:83:7, :104:34, :133:25]
wire [31:0] _tz_in_T_65 = io_in1_0[31:0]; // @[ALU.scala:83:7, :104:34, :134:33]
wire [31:0] _popc_in_T_2 = io_in1_0[31:0]; // @[ALU.scala:83:7, :104:34, :137:32]
wire [63:0] shin_r = {shin_hi, io_in1_0[31:0]}; // @[ALU.scala:83:7, :102:24, :104:{18,34}]
wire _GEN = io_fn_0 == 5'h5; // @[package.scala:16:47]
wire _shin_T; // @[package.scala:16:47]
assign _shin_T = _GEN; // @[package.scala:16:47]
wire _shout_T; // @[ALU.scala:109:25]
assign _shout_T = _GEN; // @[package.scala:16:47]
wire _GEN_0 = io_fn_0 == 5'hB; // @[package.scala:16:47]
wire _shin_T_1; // @[package.scala:16:47]
assign _shin_T_1 = _GEN_0; // @[package.scala:16:47]
wire _shout_T_1; // @[ALU.scala:109:44]
assign _shout_T_1 = _GEN_0; // @[package.scala:16:47]
wire _shin_T_2 = io_fn_0 == 5'h12; // @[package.scala:16:47]
wire _GEN_1 = io_fn_0 == 5'h13; // @[package.scala:16:47]
wire _shin_T_3; // @[package.scala:16:47]
assign _shin_T_3 = _GEN_1; // @[package.scala:16:47]
wire _shout_T_3; // @[ALU.scala:109:64]
assign _shout_T_3 = _GEN_1; // @[package.scala:16:47]
wire _bext_mask_T; // @[ALU.scala:122:52]
assign _bext_mask_T = _GEN_1; // @[package.scala:16:47]
wire _shin_T_4 = _shin_T | _shin_T_1; // @[package.scala:16:47, :81:59]
wire _shin_T_5 = _shin_T_4 | _shin_T_2; // @[package.scala:16:47, :81:59]
wire _shin_T_6 = _shin_T_5 | _shin_T_3; // @[package.scala:16:47, :81:59]
wire _shin_T_7 = ~_shin_T_6; // @[package.scala:81:59]
wire [31:0] _shin_T_10 = shin_r[63:32]; // @[ALU.scala:104:18, :106:46]
wire [31:0] _rotin_T_3 = shin_r[63:32]; // @[ALU.scala:104:18, :106:46, :156:44]
wire [63:0] _shin_T_11 = {32'h0, _shin_T_10}; // @[ALU.scala:106:46]
wire [31:0] _shin_T_12 = shin_r[31:0]; // @[ALU.scala:104:18, :106:46]
wire [31:0] _rotin_T_5 = shin_r[31:0]; // @[ALU.scala:104:18, :106:46, :156:44]
wire [63:0] _shin_T_13 = {_shin_T_12, 32'h0}; // @[ALU.scala:106:46]
wire [63:0] _shin_T_15 = _shin_T_13 & 64'hFFFFFFFF00000000; // @[ALU.scala:106:46]
wire [63:0] _shin_T_16 = _shin_T_11 | _shin_T_15; // @[ALU.scala:106:46]
wire [47:0] _shin_T_20 = _shin_T_16[63:16]; // @[ALU.scala:106:46]
wire [63:0] _shin_T_21 = {16'h0, _shin_T_20 & 48'hFFFF0000FFFF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [47:0] _shin_T_22 = _shin_T_16[47:0]; // @[ALU.scala:106:46]
wire [63:0] _shin_T_23 = {_shin_T_22, 16'h0}; // @[ALU.scala:106:46]
wire [63:0] _shin_T_25 = _shin_T_23 & 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_26 = _shin_T_21 | _shin_T_25; // @[ALU.scala:106:46]
wire [55:0] _shin_T_30 = _shin_T_26[63:8]; // @[ALU.scala:106:46]
wire [63:0] _shin_T_31 = {8'h0, _shin_T_30 & 56'hFF00FF00FF00FF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [55:0] _shin_T_32 = _shin_T_26[55:0]; // @[ALU.scala:106:46]
wire [63:0] _shin_T_33 = {_shin_T_32, 8'h0}; // @[ALU.scala:106:46]
wire [63:0] _shin_T_35 = _shin_T_33 & 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_36 = _shin_T_31 | _shin_T_35; // @[ALU.scala:106:46]
wire [59:0] _shin_T_40 = _shin_T_36[63:4]; // @[ALU.scala:106:46]
wire [63:0] _shin_T_41 = {4'h0, _shin_T_40 & 60'hF0F0F0F0F0F0F0F}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [59:0] _shin_T_42 = _shin_T_36[59:0]; // @[ALU.scala:106:46]
wire [63:0] _shin_T_43 = {_shin_T_42, 4'h0}; // @[ALU.scala:106:46]
wire [63:0] _shin_T_45 = _shin_T_43 & 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_46 = _shin_T_41 | _shin_T_45; // @[ALU.scala:106:46]
wire [61:0] _shin_T_50 = _shin_T_46[63:2]; // @[ALU.scala:106:46]
wire [63:0] _shin_T_51 = {2'h0, _shin_T_50 & 62'h3333333333333333}; // @[package.scala:16:47]
wire [61:0] _shin_T_52 = _shin_T_46[61:0]; // @[ALU.scala:106:46]
wire [63:0] _shin_T_53 = {_shin_T_52, 2'h0}; // @[package.scala:16:47]
wire [63:0] _shin_T_55 = _shin_T_53 & 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_56 = _shin_T_51 | _shin_T_55; // @[ALU.scala:106:46]
wire [62:0] _shin_T_60 = _shin_T_56[63:1]; // @[ALU.scala:106:46]
wire [63:0] _shin_T_61 = {1'h0, _shin_T_60 & 63'h5555555555555555}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [62:0] _shin_T_62 = _shin_T_56[62:0]; // @[ALU.scala:106:46]
wire [63:0] _shin_T_63 = {_shin_T_62, 1'h0}; // @[ALU.scala:106:46]
wire [63:0] _shin_T_65 = _shin_T_63 & 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_66 = _shin_T_61 | _shin_T_65; // @[ALU.scala:106:46]
wire [63:0] shin = _shin_T_7 ? _shin_T_66 : shin_r; // @[ALU.scala:64:33, :104:18, :106:{17,46}]
wire _shout_r_T_1 = shin[63]; // @[ALU.scala:106:17, :107:41]
wire _shout_r_T_2 = _shout_r_T & _shout_r_T_1; // @[ALU.scala:58:29, :107:{35,41}]
wire [64:0] _shout_r_T_3 = {_shout_r_T_2, shin}; // @[ALU.scala:106:17, :107:{21,35}]
wire [64:0] _shout_r_T_4 = _shout_r_T_3; // @[ALU.scala:107:{21,57}]
wire [64:0] _shout_r_T_5 = $signed($signed(_shout_r_T_4) >>> shamt); // @[ALU.scala:103:22, :107:{57,64}]
wire [63:0] shout_r = _shout_r_T_5[63:0]; // @[ALU.scala:107:{64,73}]
wire [31:0] _shout_l_T_2 = shout_r[63:32]; // @[ALU.scala:107:73, :108:24]
wire [63:0] _shout_l_T_3 = {32'h0, _shout_l_T_2}; // @[ALU.scala:108:24]
wire [31:0] _shout_l_T_4 = shout_r[31:0]; // @[ALU.scala:107:73, :108:24]
wire [63:0] _shout_l_T_5 = {_shout_l_T_4, 32'h0}; // @[ALU.scala:108:24]
wire [63:0] _shout_l_T_7 = _shout_l_T_5 & 64'hFFFFFFFF00000000; // @[ALU.scala:108:24]
wire [63:0] _shout_l_T_8 = _shout_l_T_3 | _shout_l_T_7; // @[ALU.scala:108:24]
wire [47:0] _shout_l_T_12 = _shout_l_T_8[63:16]; // @[ALU.scala:108:24]
wire [63:0] _shout_l_T_13 = {16'h0, _shout_l_T_12 & 48'hFFFF0000FFFF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [47:0] _shout_l_T_14 = _shout_l_T_8[47:0]; // @[ALU.scala:108:24]
wire [63:0] _shout_l_T_15 = {_shout_l_T_14, 16'h0}; // @[ALU.scala:106:46, :108:24]
wire [63:0] _shout_l_T_17 = _shout_l_T_15 & 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_18 = _shout_l_T_13 | _shout_l_T_17; // @[ALU.scala:108:24]
wire [55:0] _shout_l_T_22 = _shout_l_T_18[63:8]; // @[ALU.scala:108:24]
wire [63:0] _shout_l_T_23 = {8'h0, _shout_l_T_22 & 56'hFF00FF00FF00FF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [55:0] _shout_l_T_24 = _shout_l_T_18[55:0]; // @[ALU.scala:108:24]
wire [63:0] _shout_l_T_25 = {_shout_l_T_24, 8'h0}; // @[ALU.scala:108:24]
wire [63:0] _shout_l_T_27 = _shout_l_T_25 & 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_28 = _shout_l_T_23 | _shout_l_T_27; // @[ALU.scala:108:24]
wire [59:0] _shout_l_T_32 = _shout_l_T_28[63:4]; // @[ALU.scala:108:24]
wire [63:0] _shout_l_T_33 = {4'h0, _shout_l_T_32 & 60'hF0F0F0F0F0F0F0F}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [59:0] _shout_l_T_34 = _shout_l_T_28[59:0]; // @[ALU.scala:108:24]
wire [63:0] _shout_l_T_35 = {_shout_l_T_34, 4'h0}; // @[ALU.scala:106:46, :108:24]
wire [63:0] _shout_l_T_37 = _shout_l_T_35 & 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_38 = _shout_l_T_33 | _shout_l_T_37; // @[ALU.scala:108:24]
wire [61:0] _shout_l_T_42 = _shout_l_T_38[63:2]; // @[ALU.scala:108:24]
wire [63:0] _shout_l_T_43 = {2'h0, _shout_l_T_42 & 62'h3333333333333333}; // @[package.scala:16:47]
wire [61:0] _shout_l_T_44 = _shout_l_T_38[61:0]; // @[ALU.scala:108:24]
wire [63:0] _shout_l_T_45 = {_shout_l_T_44, 2'h0}; // @[package.scala:16:47]
wire [63:0] _shout_l_T_47 = _shout_l_T_45 & 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_48 = _shout_l_T_43 | _shout_l_T_47; // @[ALU.scala:108:24]
wire [62:0] _shout_l_T_52 = _shout_l_T_48[63:1]; // @[ALU.scala:108:24]
wire [63:0] _shout_l_T_53 = {1'h0, _shout_l_T_52 & 63'h5555555555555555}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [62:0] _shout_l_T_54 = _shout_l_T_48[62:0]; // @[ALU.scala:108:24]
wire [63:0] _shout_l_T_55 = {_shout_l_T_54, 1'h0}; // @[ALU.scala:108:24]
wire [63:0] _shout_l_T_57 = _shout_l_T_55 & 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] shout_l = _shout_l_T_53 | _shout_l_T_57; // @[ALU.scala:108:24]
wire _shout_T_2 = _shout_T | _shout_T_1; // @[ALU.scala:109:{25,35,44}]
wire _shout_T_4 = _shout_T_2 | _shout_T_3; // @[ALU.scala:109:{35,55,64}]
wire [63:0] _shout_T_5 = _shout_T_4 ? shout_r : 64'h0; // @[ALU.scala:107:73, :109:{18,55}]
wire _shout_T_6 = io_fn_0 == 5'h1; // @[ALU.scala:83:7, :110:25]
wire [63:0] _shout_T_7 = _shout_T_6 ? shout_l : 64'h0; // @[ALU.scala:108:24, :110:{18,25}]
wire [63:0] shout = _shout_T_5 | _shout_T_7; // @[ALU.scala:109:{18,91}, :110:18]
wire [63:0] _shift_logic_T_5 = shout; // @[ALU.scala:109:91, :123:61]
wire in2_not_zero = |io_in2_0; // @[ALU.scala:83:7, :113:29]
wire _logic_T = io_fn_0 == 5'h4; // @[ALU.scala:83:7, :119:25]
wire _GEN_2 = io_fn_0 == 5'h6; // @[ALU.scala:83:7, :119:45]
wire _logic_T_1; // @[ALU.scala:119:45]
assign _logic_T_1 = _GEN_2; // @[ALU.scala:119:45]
wire _logic_T_8; // @[ALU.scala:120:25]
assign _logic_T_8 = _GEN_2; // @[ALU.scala:119:45, :120:25]
wire _logic_T_2 = _logic_T | _logic_T_1; // @[ALU.scala:119:{25,36,45}]
wire _GEN_3 = io_fn_0 == 5'h19; // @[ALU.scala:83:7, :119:64]
wire _logic_T_3; // @[ALU.scala:119:64]
assign _logic_T_3 = _GEN_3; // @[ALU.scala:119:64]
wire _logic_T_11; // @[ALU.scala:120:64]
assign _logic_T_11 = _GEN_3; // @[ALU.scala:119:64, :120:64]
wire _logic_T_4 = _logic_T_2 | _logic_T_3; // @[ALU.scala:119:{36,55,64}]
wire _logic_T_5 = io_fn_0 == 5'h1A; // @[ALU.scala:83:7, :119:84]
wire _logic_T_6 = _logic_T_4 | _logic_T_5; // @[ALU.scala:119:{55,75,84}]
wire [63:0] _logic_T_7 = _logic_T_6 ? in1_xor_in2 : 64'h0; // @[ALU.scala:86:28, :119:{18,75}]
wire _logic_T_9 = io_fn_0 == 5'h7; // @[ALU.scala:83:7, :120:44]
wire _logic_T_10 = _logic_T_8 | _logic_T_9; // @[ALU.scala:120:{25,35,44}]
wire _logic_T_12 = _logic_T_10 | _logic_T_11; // @[ALU.scala:120:{35,55,64}]
wire _logic_T_13 = io_fn_0 == 5'h18; // @[ALU.scala:83:7, :120:84]
wire _logic_T_14 = _logic_T_12 | _logic_T_13; // @[ALU.scala:120:{55,75,84}]
wire [63:0] _logic_T_15 = _logic_T_14 ? in1_and_in2 : 64'h0; // @[ALU.scala:87:28, :120:{18,75}]
wire [63:0] logic_0 = _logic_T_7 | _logic_T_15; // @[ALU.scala:119:{18,115}, :120:18]
wire _shift_logic_T = io_fn_0 > 5'hB; // @[ALU.scala:59:31, :83:7]
wire _shift_logic_T_1 = ~(io_fn_0[4]); // @[ALU.scala:59:48, :83:7]
wire _shift_logic_T_2 = _shift_logic_T & _shift_logic_T_1; // @[ALU.scala:59:{31,41,48}]
wire _shift_logic_T_3 = _shift_logic_T_2 & slt; // @[ALU.scala:59:41, :92:8, :123:36]
wire [63:0] _shift_logic_T_4 = {63'h0, _shift_logic_T_3} | logic_0; // @[ALU.scala:119:115, :123:{36,44}]
wire [63:0] shift_logic = _shift_logic_T_4 | _shift_logic_T_5; // @[ALU.scala:123:{44,52,61}]
wire _tz_in_T = ~io_dw_0; // @[ALU.scala:83:7, :130:32]
wire _tz_in_T_1 = io_in2_0[0]; // @[ALU.scala:83:7, :130:53]
wire _tz_in_T_2 = ~_tz_in_T_1; // @[ALU.scala:130:{46,53}]
wire [1:0] _tz_in_T_3 = {_tz_in_T, _tz_in_T_2}; // @[ALU.scala:130:{32,43,46}]
wire [63:0] _tz_in_T_7 = {32'h0, _tz_in_T_6}; // @[ALU.scala:132:19]
wire [63:0] _tz_in_T_9 = {_tz_in_T_8, 32'h0}; // @[ALU.scala:132:19]
wire [63:0] _tz_in_T_11 = _tz_in_T_9 & 64'hFFFFFFFF00000000; // @[ALU.scala:132:19]
wire [63:0] _tz_in_T_12 = _tz_in_T_7 | _tz_in_T_11; // @[ALU.scala:132:19]
wire [47:0] _tz_in_T_16 = _tz_in_T_12[63:16]; // @[ALU.scala:132:19]
wire [63:0] _tz_in_T_17 = {16'h0, _tz_in_T_16 & 48'hFFFF0000FFFF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [47:0] _tz_in_T_18 = _tz_in_T_12[47:0]; // @[ALU.scala:132:19]
wire [63:0] _tz_in_T_19 = {_tz_in_T_18, 16'h0}; // @[ALU.scala:106:46, :132:19]
wire [63:0] _tz_in_T_21 = _tz_in_T_19 & 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_22 = _tz_in_T_17 | _tz_in_T_21; // @[ALU.scala:132:19]
wire [55:0] _tz_in_T_26 = _tz_in_T_22[63:8]; // @[ALU.scala:132:19]
wire [63:0] _tz_in_T_27 = {8'h0, _tz_in_T_26 & 56'hFF00FF00FF00FF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [55:0] _tz_in_T_28 = _tz_in_T_22[55:0]; // @[ALU.scala:132:19]
wire [63:0] _tz_in_T_29 = {_tz_in_T_28, 8'h0}; // @[ALU.scala:132:19]
wire [63:0] _tz_in_T_31 = _tz_in_T_29 & 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_32 = _tz_in_T_27 | _tz_in_T_31; // @[ALU.scala:132:19]
wire [59:0] _tz_in_T_36 = _tz_in_T_32[63:4]; // @[ALU.scala:132:19]
wire [63:0] _tz_in_T_37 = {4'h0, _tz_in_T_36 & 60'hF0F0F0F0F0F0F0F}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [59:0] _tz_in_T_38 = _tz_in_T_32[59:0]; // @[ALU.scala:132:19]
wire [63:0] _tz_in_T_39 = {_tz_in_T_38, 4'h0}; // @[ALU.scala:106:46, :132:19]
wire [63:0] _tz_in_T_41 = _tz_in_T_39 & 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_42 = _tz_in_T_37 | _tz_in_T_41; // @[ALU.scala:132:19]
wire [61:0] _tz_in_T_46 = _tz_in_T_42[63:2]; // @[ALU.scala:132:19]
wire [63:0] _tz_in_T_47 = {2'h0, _tz_in_T_46 & 62'h3333333333333333}; // @[package.scala:16:47]
wire [61:0] _tz_in_T_48 = _tz_in_T_42[61:0]; // @[ALU.scala:132:19]
wire [63:0] _tz_in_T_49 = {_tz_in_T_48, 2'h0}; // @[package.scala:16:47]
wire [63:0] _tz_in_T_51 = _tz_in_T_49 & 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_52 = _tz_in_T_47 | _tz_in_T_51; // @[ALU.scala:132:19]
wire [62:0] _tz_in_T_56 = _tz_in_T_52[63:1]; // @[ALU.scala:132:19]
wire [63:0] _tz_in_T_57 = {1'h0, _tz_in_T_56 & 63'h5555555555555555}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [62:0] _tz_in_T_58 = _tz_in_T_52[62:0]; // @[ALU.scala:132:19]
wire [63:0] _tz_in_T_59 = {_tz_in_T_58, 1'h0}; // @[ALU.scala:132:19]
wire [63:0] _tz_in_T_61 = _tz_in_T_59 & 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_62 = _tz_in_T_57 | _tz_in_T_61; // @[ALU.scala:132:19]
wire [32:0] _tz_in_T_64 = {1'h1, _tz_in_T_63}; // @[ALU.scala:133:{16,25}]
wire [15:0] _tz_in_T_68 = _tz_in_T_65[31:16]; // @[ALU.scala:134:{26,33}]
wire [31:0] _tz_in_T_69 = {16'h0, _tz_in_T_68}; // @[ALU.scala:106:46, :134:26]
wire [15:0] _tz_in_T_70 = _tz_in_T_65[15:0]; // @[ALU.scala:134:{26,33}]
wire [31:0] _tz_in_T_71 = {_tz_in_T_70, 16'h0}; // @[ALU.scala:106:46, :134:26]
wire [31:0] _tz_in_T_73 = _tz_in_T_71 & 32'hFFFF0000; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_74 = _tz_in_T_69 | _tz_in_T_73; // @[ALU.scala:134:26]
wire [23:0] _tz_in_T_78 = _tz_in_T_74[31:8]; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_79 = {8'h0, _tz_in_T_78 & 24'hFF00FF}; // @[ALU.scala:134:26]
wire [23:0] _tz_in_T_80 = _tz_in_T_74[23:0]; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_81 = {_tz_in_T_80, 8'h0}; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_83 = _tz_in_T_81 & 32'hFF00FF00; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_84 = _tz_in_T_79 | _tz_in_T_83; // @[ALU.scala:134:26]
wire [27:0] _tz_in_T_88 = _tz_in_T_84[31:4]; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_89 = {4'h0, _tz_in_T_88 & 28'hF0F0F0F}; // @[ALU.scala:106:46, :134:26]
wire [27:0] _tz_in_T_90 = _tz_in_T_84[27:0]; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_91 = {_tz_in_T_90, 4'h0}; // @[ALU.scala:106:46, :134:26]
wire [31:0] _tz_in_T_93 = _tz_in_T_91 & 32'hF0F0F0F0; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_94 = _tz_in_T_89 | _tz_in_T_93; // @[ALU.scala:134:26]
wire [29:0] _tz_in_T_98 = _tz_in_T_94[31:2]; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_99 = {2'h0, _tz_in_T_98 & 30'h33333333}; // @[package.scala:16:47]
wire [29:0] _tz_in_T_100 = _tz_in_T_94[29:0]; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_101 = {_tz_in_T_100, 2'h0}; // @[package.scala:16:47]
wire [31:0] _tz_in_T_103 = _tz_in_T_101 & 32'hCCCCCCCC; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_104 = _tz_in_T_99 | _tz_in_T_103; // @[ALU.scala:134:26]
wire [30:0] _tz_in_T_108 = _tz_in_T_104[31:1]; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_109 = {1'h0, _tz_in_T_108 & 31'h55555555}; // @[ALU.scala:134:26]
wire [30:0] _tz_in_T_110 = _tz_in_T_104[30:0]; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_111 = {_tz_in_T_110, 1'h0}; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_113 = _tz_in_T_111 & 32'hAAAAAAAA; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_114 = _tz_in_T_109 | _tz_in_T_113; // @[ALU.scala:134:26]
wire [32:0] _tz_in_T_115 = {1'h1, _tz_in_T_114}; // @[ALU.scala:134:{16,26}]
wire _tz_in_T_116 = _tz_in_T_3 == 2'h1; // @[ALU.scala:130:{43,62}]
wire [63:0] _tz_in_T_117 = _tz_in_T_116 ? _tz_in_T_62 : io_in1_0; // @[ALU.scala:83:7, :130:62, :132:19]
wire _tz_in_T_118 = _tz_in_T_3 == 2'h2; // @[ALU.scala:130:{43,62}]
wire [63:0] _tz_in_T_119 = _tz_in_T_118 ? {31'h0, _tz_in_T_64} : _tz_in_T_117; // @[ALU.scala:130:62, :133:16]
wire _tz_in_T_120 = &_tz_in_T_3; // @[ALU.scala:130:{43,62}]
wire [63:0] tz_in = _tz_in_T_120 ? {31'h0, _tz_in_T_115} : _tz_in_T_119; // @[ALU.scala:130:62, :134:16]
wire _popc_in_T = io_in2_0[1]; // @[ALU.scala:83:7, :136:27]
wire _popc_in_T_1 = ~io_dw_0; // @[ALU.scala:83:7, :130:32, :137:15]
wire [63:0] _popc_in_T_3 = _popc_in_T_1 ? {32'h0, _popc_in_T_2} : io_in1_0; // @[ALU.scala:83:7, :137:{8,15,32}]
wire [64:0] _popc_in_T_4 = {1'h1, tz_in}; // @[ALU.scala:130:62, :138:27]
wire _popc_in_T_5 = _popc_in_T_4[0]; // @[OneHot.scala:85:71]
wire _popc_in_T_6 = _popc_in_T_4[1]; // @[OneHot.scala:85:71]
wire _popc_in_T_7 = _popc_in_T_4[2]; // @[OneHot.scala:85:71]
wire _popc_in_T_8 = _popc_in_T_4[3]; // @[OneHot.scala:85:71]
wire _popc_in_T_9 = _popc_in_T_4[4]; // @[OneHot.scala:85:71]
wire _popc_in_T_10 = _popc_in_T_4[5]; // @[OneHot.scala:85:71]
wire _popc_in_T_11 = _popc_in_T_4[6]; // @[OneHot.scala:85:71]
wire _popc_in_T_12 = _popc_in_T_4[7]; // @[OneHot.scala:85:71]
wire _popc_in_T_13 = _popc_in_T_4[8]; // @[OneHot.scala:85:71]
wire _popc_in_T_14 = _popc_in_T_4[9]; // @[OneHot.scala:85:71]
wire _popc_in_T_15 = _popc_in_T_4[10]; // @[OneHot.scala:85:71]
wire _popc_in_T_16 = _popc_in_T_4[11]; // @[OneHot.scala:85:71]
wire _popc_in_T_17 = _popc_in_T_4[12]; // @[OneHot.scala:85:71]
wire _popc_in_T_18 = _popc_in_T_4[13]; // @[OneHot.scala:85:71]
wire _popc_in_T_19 = _popc_in_T_4[14]; // @[OneHot.scala:85:71]
wire _popc_in_T_20 = _popc_in_T_4[15]; // @[OneHot.scala:85:71]
wire _popc_in_T_21 = _popc_in_T_4[16]; // @[OneHot.scala:85:71]
wire _popc_in_T_22 = _popc_in_T_4[17]; // @[OneHot.scala:85:71]
wire _popc_in_T_23 = _popc_in_T_4[18]; // @[OneHot.scala:85:71]
wire _popc_in_T_24 = _popc_in_T_4[19]; // @[OneHot.scala:85:71]
wire _popc_in_T_25 = _popc_in_T_4[20]; // @[OneHot.scala:85:71]
wire _popc_in_T_26 = _popc_in_T_4[21]; // @[OneHot.scala:85:71]
wire _popc_in_T_27 = _popc_in_T_4[22]; // @[OneHot.scala:85:71]
wire _popc_in_T_28 = _popc_in_T_4[23]; // @[OneHot.scala:85:71]
wire _popc_in_T_29 = _popc_in_T_4[24]; // @[OneHot.scala:85:71]
wire _popc_in_T_30 = _popc_in_T_4[25]; // @[OneHot.scala:85:71]
wire _popc_in_T_31 = _popc_in_T_4[26]; // @[OneHot.scala:85:71]
wire _popc_in_T_32 = _popc_in_T_4[27]; // @[OneHot.scala:85:71]
wire _popc_in_T_33 = _popc_in_T_4[28]; // @[OneHot.scala:85:71]
wire _popc_in_T_34 = _popc_in_T_4[29]; // @[OneHot.scala:85:71]
wire _popc_in_T_35 = _popc_in_T_4[30]; // @[OneHot.scala:85:71]
wire _popc_in_T_36 = _popc_in_T_4[31]; // @[OneHot.scala:85:71]
wire _popc_in_T_37 = _popc_in_T_4[32]; // @[OneHot.scala:85:71]
wire _popc_in_T_38 = _popc_in_T_4[33]; // @[OneHot.scala:85:71]
wire _popc_in_T_39 = _popc_in_T_4[34]; // @[OneHot.scala:85:71]
wire _popc_in_T_40 = _popc_in_T_4[35]; // @[OneHot.scala:85:71]
wire _popc_in_T_41 = _popc_in_T_4[36]; // @[OneHot.scala:85:71]
wire _popc_in_T_42 = _popc_in_T_4[37]; // @[OneHot.scala:85:71]
wire _popc_in_T_43 = _popc_in_T_4[38]; // @[OneHot.scala:85:71]
wire _popc_in_T_44 = _popc_in_T_4[39]; // @[OneHot.scala:85:71]
wire _popc_in_T_45 = _popc_in_T_4[40]; // @[OneHot.scala:85:71]
wire _popc_in_T_46 = _popc_in_T_4[41]; // @[OneHot.scala:85:71]
wire _popc_in_T_47 = _popc_in_T_4[42]; // @[OneHot.scala:85:71]
wire _popc_in_T_48 = _popc_in_T_4[43]; // @[OneHot.scala:85:71]
wire _popc_in_T_49 = _popc_in_T_4[44]; // @[OneHot.scala:85:71]
wire _popc_in_T_50 = _popc_in_T_4[45]; // @[OneHot.scala:85:71]
wire _popc_in_T_51 = _popc_in_T_4[46]; // @[OneHot.scala:85:71]
wire _popc_in_T_52 = _popc_in_T_4[47]; // @[OneHot.scala:85:71]
wire _popc_in_T_53 = _popc_in_T_4[48]; // @[OneHot.scala:85:71]
wire _popc_in_T_54 = _popc_in_T_4[49]; // @[OneHot.scala:85:71]
wire _popc_in_T_55 = _popc_in_T_4[50]; // @[OneHot.scala:85:71]
wire _popc_in_T_56 = _popc_in_T_4[51]; // @[OneHot.scala:85:71]
wire _popc_in_T_57 = _popc_in_T_4[52]; // @[OneHot.scala:85:71]
wire _popc_in_T_58 = _popc_in_T_4[53]; // @[OneHot.scala:85:71]
wire _popc_in_T_59 = _popc_in_T_4[54]; // @[OneHot.scala:85:71]
wire _popc_in_T_60 = _popc_in_T_4[55]; // @[OneHot.scala:85:71]
wire _popc_in_T_61 = _popc_in_T_4[56]; // @[OneHot.scala:85:71]
wire _popc_in_T_62 = _popc_in_T_4[57]; // @[OneHot.scala:85:71]
wire _popc_in_T_63 = _popc_in_T_4[58]; // @[OneHot.scala:85:71]
wire _popc_in_T_64 = _popc_in_T_4[59]; // @[OneHot.scala:85:71]
wire _popc_in_T_65 = _popc_in_T_4[60]; // @[OneHot.scala:85:71]
wire _popc_in_T_66 = _popc_in_T_4[61]; // @[OneHot.scala:85:71]
wire _popc_in_T_67 = _popc_in_T_4[62]; // @[OneHot.scala:85:71]
wire _popc_in_T_68 = _popc_in_T_4[63]; // @[OneHot.scala:85:71]
wire _popc_in_T_69 = _popc_in_T_4[64]; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_70 = {_popc_in_T_69, 64'h0}; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_71 = _popc_in_T_68 ? 65'h8000000000000000 : _popc_in_T_70; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_72 = _popc_in_T_67 ? 65'h4000000000000000 : _popc_in_T_71; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_73 = _popc_in_T_66 ? 65'h2000000000000000 : _popc_in_T_72; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_74 = _popc_in_T_65 ? 65'h1000000000000000 : _popc_in_T_73; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_75 = _popc_in_T_64 ? 65'h800000000000000 : _popc_in_T_74; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_76 = _popc_in_T_63 ? 65'h400000000000000 : _popc_in_T_75; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_77 = _popc_in_T_62 ? 65'h200000000000000 : _popc_in_T_76; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_78 = _popc_in_T_61 ? 65'h100000000000000 : _popc_in_T_77; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_79 = _popc_in_T_60 ? 65'h80000000000000 : _popc_in_T_78; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_80 = _popc_in_T_59 ? 65'h40000000000000 : _popc_in_T_79; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_81 = _popc_in_T_58 ? 65'h20000000000000 : _popc_in_T_80; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_82 = _popc_in_T_57 ? 65'h10000000000000 : _popc_in_T_81; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_83 = _popc_in_T_56 ? 65'h8000000000000 : _popc_in_T_82; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_84 = _popc_in_T_55 ? 65'h4000000000000 : _popc_in_T_83; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_85 = _popc_in_T_54 ? 65'h2000000000000 : _popc_in_T_84; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_86 = _popc_in_T_53 ? 65'h1000000000000 : _popc_in_T_85; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_87 = _popc_in_T_52 ? 65'h800000000000 : _popc_in_T_86; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_88 = _popc_in_T_51 ? 65'h400000000000 : _popc_in_T_87; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_89 = _popc_in_T_50 ? 65'h200000000000 : _popc_in_T_88; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_90 = _popc_in_T_49 ? 65'h100000000000 : _popc_in_T_89; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_91 = _popc_in_T_48 ? 65'h80000000000 : _popc_in_T_90; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_92 = _popc_in_T_47 ? 65'h40000000000 : _popc_in_T_91; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_93 = _popc_in_T_46 ? 65'h20000000000 : _popc_in_T_92; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_94 = _popc_in_T_45 ? 65'h10000000000 : _popc_in_T_93; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_95 = _popc_in_T_44 ? 65'h8000000000 : _popc_in_T_94; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_96 = _popc_in_T_43 ? 65'h4000000000 : _popc_in_T_95; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_97 = _popc_in_T_42 ? 65'h2000000000 : _popc_in_T_96; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_98 = _popc_in_T_41 ? 65'h1000000000 : _popc_in_T_97; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_99 = _popc_in_T_40 ? 65'h800000000 : _popc_in_T_98; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_100 = _popc_in_T_39 ? 65'h400000000 : _popc_in_T_99; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_101 = _popc_in_T_38 ? 65'h200000000 : _popc_in_T_100; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_102 = _popc_in_T_37 ? 65'h100000000 : _popc_in_T_101; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_103 = _popc_in_T_36 ? 65'h80000000 : _popc_in_T_102; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_104 = _popc_in_T_35 ? 65'h40000000 : _popc_in_T_103; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_105 = _popc_in_T_34 ? 65'h20000000 : _popc_in_T_104; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_106 = _popc_in_T_33 ? 65'h10000000 : _popc_in_T_105; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_107 = _popc_in_T_32 ? 65'h8000000 : _popc_in_T_106; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_108 = _popc_in_T_31 ? 65'h4000000 : _popc_in_T_107; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_109 = _popc_in_T_30 ? 65'h2000000 : _popc_in_T_108; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_110 = _popc_in_T_29 ? 65'h1000000 : _popc_in_T_109; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_111 = _popc_in_T_28 ? 65'h800000 : _popc_in_T_110; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_112 = _popc_in_T_27 ? 65'h400000 : _popc_in_T_111; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_113 = _popc_in_T_26 ? 65'h200000 : _popc_in_T_112; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_114 = _popc_in_T_25 ? 65'h100000 : _popc_in_T_113; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_115 = _popc_in_T_24 ? 65'h80000 : _popc_in_T_114; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_116 = _popc_in_T_23 ? 65'h40000 : _popc_in_T_115; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_117 = _popc_in_T_22 ? 65'h20000 : _popc_in_T_116; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_118 = _popc_in_T_21 ? 65'h10000 : _popc_in_T_117; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_119 = _popc_in_T_20 ? 65'h8000 : _popc_in_T_118; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_120 = _popc_in_T_19 ? 65'h4000 : _popc_in_T_119; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_121 = _popc_in_T_18 ? 65'h2000 : _popc_in_T_120; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_122 = _popc_in_T_17 ? 65'h1000 : _popc_in_T_121; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_123 = _popc_in_T_16 ? 65'h800 : _popc_in_T_122; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_124 = _popc_in_T_15 ? 65'h400 : _popc_in_T_123; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_125 = _popc_in_T_14 ? 65'h200 : _popc_in_T_124; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_126 = _popc_in_T_13 ? 65'h100 : _popc_in_T_125; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_127 = _popc_in_T_12 ? 65'h80 : _popc_in_T_126; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_128 = _popc_in_T_11 ? 65'h40 : _popc_in_T_127; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_129 = _popc_in_T_10 ? 65'h20 : _popc_in_T_128; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_130 = _popc_in_T_9 ? 65'h10 : _popc_in_T_129; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_131 = _popc_in_T_8 ? 65'h8 : _popc_in_T_130; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_132 = _popc_in_T_7 ? 65'h4 : _popc_in_T_131; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_133 = _popc_in_T_6 ? 65'h2 : _popc_in_T_132; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_134 = _popc_in_T_5 ? 65'h1 : _popc_in_T_133; // @[OneHot.scala:85:71]
wire [65:0] _popc_in_T_135 = {1'h0, _popc_in_T_134} - 66'h1; // @[Mux.scala:50:70]
wire [64:0] _popc_in_T_136 = _popc_in_T_135[64:0]; // @[ALU.scala:138:37]
wire [64:0] _popc_in_T_137 = _popc_in_T ? {1'h0, _popc_in_T_3} : _popc_in_T_136; // @[ALU.scala:136:{20,27}, :137:8, :138:37]
wire [63:0] popc_in = _popc_in_T_137[63:0]; // @[ALU.scala:136:20, :138:43]
wire _count_T = popc_in[0]; // @[ALU.scala:138:43, :139:23]
wire _count_T_1 = popc_in[1]; // @[ALU.scala:138:43, :139:23]
wire _count_T_2 = popc_in[2]; // @[ALU.scala:138:43, :139:23]
wire _count_T_3 = popc_in[3]; // @[ALU.scala:138:43, :139:23]
wire _count_T_4 = popc_in[4]; // @[ALU.scala:138:43, :139:23]
wire _count_T_5 = popc_in[5]; // @[ALU.scala:138:43, :139:23]
wire _count_T_6 = popc_in[6]; // @[ALU.scala:138:43, :139:23]
wire _count_T_7 = popc_in[7]; // @[ALU.scala:138:43, :139:23]
wire _count_T_8 = popc_in[8]; // @[ALU.scala:138:43, :139:23]
wire _count_T_9 = popc_in[9]; // @[ALU.scala:138:43, :139:23]
wire _count_T_10 = popc_in[10]; // @[ALU.scala:138:43, :139:23]
wire _count_T_11 = popc_in[11]; // @[ALU.scala:138:43, :139:23]
wire _count_T_12 = popc_in[12]; // @[ALU.scala:138:43, :139:23]
wire _count_T_13 = popc_in[13]; // @[ALU.scala:138:43, :139:23]
wire _count_T_14 = popc_in[14]; // @[ALU.scala:138:43, :139:23]
wire _count_T_15 = popc_in[15]; // @[ALU.scala:138:43, :139:23]
wire _count_T_16 = popc_in[16]; // @[ALU.scala:138:43, :139:23]
wire _count_T_17 = popc_in[17]; // @[ALU.scala:138:43, :139:23]
wire _count_T_18 = popc_in[18]; // @[ALU.scala:138:43, :139:23]
wire _count_T_19 = popc_in[19]; // @[ALU.scala:138:43, :139:23]
wire _count_T_20 = popc_in[20]; // @[ALU.scala:138:43, :139:23]
wire _count_T_21 = popc_in[21]; // @[ALU.scala:138:43, :139:23]
wire _count_T_22 = popc_in[22]; // @[ALU.scala:138:43, :139:23]
wire _count_T_23 = popc_in[23]; // @[ALU.scala:138:43, :139:23]
wire _count_T_24 = popc_in[24]; // @[ALU.scala:138:43, :139:23]
wire _count_T_25 = popc_in[25]; // @[ALU.scala:138:43, :139:23]
wire _count_T_26 = popc_in[26]; // @[ALU.scala:138:43, :139:23]
wire _count_T_27 = popc_in[27]; // @[ALU.scala:138:43, :139:23]
wire _count_T_28 = popc_in[28]; // @[ALU.scala:138:43, :139:23]
wire _count_T_29 = popc_in[29]; // @[ALU.scala:138:43, :139:23]
wire _count_T_30 = popc_in[30]; // @[ALU.scala:138:43, :139:23]
wire _count_T_31 = popc_in[31]; // @[ALU.scala:138:43, :139:23]
wire _count_T_32 = popc_in[32]; // @[ALU.scala:138:43, :139:23]
wire _count_T_33 = popc_in[33]; // @[ALU.scala:138:43, :139:23]
wire _count_T_34 = popc_in[34]; // @[ALU.scala:138:43, :139:23]
wire _count_T_35 = popc_in[35]; // @[ALU.scala:138:43, :139:23]
wire _count_T_36 = popc_in[36]; // @[ALU.scala:138:43, :139:23]
wire _count_T_37 = popc_in[37]; // @[ALU.scala:138:43, :139:23]
wire _count_T_38 = popc_in[38]; // @[ALU.scala:138:43, :139:23]
wire _count_T_39 = popc_in[39]; // @[ALU.scala:138:43, :139:23]
wire _count_T_40 = popc_in[40]; // @[ALU.scala:138:43, :139:23]
wire _count_T_41 = popc_in[41]; // @[ALU.scala:138:43, :139:23]
wire _count_T_42 = popc_in[42]; // @[ALU.scala:138:43, :139:23]
wire _count_T_43 = popc_in[43]; // @[ALU.scala:138:43, :139:23]
wire _count_T_44 = popc_in[44]; // @[ALU.scala:138:43, :139:23]
wire _count_T_45 = popc_in[45]; // @[ALU.scala:138:43, :139:23]
wire _count_T_46 = popc_in[46]; // @[ALU.scala:138:43, :139:23]
wire _count_T_47 = popc_in[47]; // @[ALU.scala:138:43, :139:23]
wire _count_T_48 = popc_in[48]; // @[ALU.scala:138:43, :139:23]
wire _count_T_49 = popc_in[49]; // @[ALU.scala:138:43, :139:23]
wire _count_T_50 = popc_in[50]; // @[ALU.scala:138:43, :139:23]
wire _count_T_51 = popc_in[51]; // @[ALU.scala:138:43, :139:23]
wire _count_T_52 = popc_in[52]; // @[ALU.scala:138:43, :139:23]
wire _count_T_53 = popc_in[53]; // @[ALU.scala:138:43, :139:23]
wire _count_T_54 = popc_in[54]; // @[ALU.scala:138:43, :139:23]
wire _count_T_55 = popc_in[55]; // @[ALU.scala:138:43, :139:23]
wire _count_T_56 = popc_in[56]; // @[ALU.scala:138:43, :139:23]
wire _count_T_57 = popc_in[57]; // @[ALU.scala:138:43, :139:23]
wire _count_T_58 = popc_in[58]; // @[ALU.scala:138:43, :139:23]
wire _count_T_59 = popc_in[59]; // @[ALU.scala:138:43, :139:23]
wire _count_T_60 = popc_in[60]; // @[ALU.scala:138:43, :139:23]
wire _count_T_61 = popc_in[61]; // @[ALU.scala:138:43, :139:23]
wire _count_T_62 = popc_in[62]; // @[ALU.scala:138:43, :139:23]
wire _count_T_63 = popc_in[63]; // @[ALU.scala:138:43, :139:23]
wire [1:0] _count_T_64 = {1'h0, _count_T} + {1'h0, _count_T_1}; // @[ALU.scala:139:23]
wire [1:0] _count_T_65 = _count_T_64; // @[ALU.scala:139:23]
wire [1:0] _count_T_66 = {1'h0, _count_T_2} + {1'h0, _count_T_3}; // @[ALU.scala:139:23]
wire [1:0] _count_T_67 = _count_T_66; // @[ALU.scala:139:23]
wire [2:0] _count_T_68 = {1'h0, _count_T_65} + {1'h0, _count_T_67}; // @[ALU.scala:139:23]
wire [2:0] _count_T_69 = _count_T_68; // @[ALU.scala:139:23]
wire [1:0] _count_T_70 = {1'h0, _count_T_4} + {1'h0, _count_T_5}; // @[ALU.scala:139:23]
wire [1:0] _count_T_71 = _count_T_70; // @[ALU.scala:139:23]
wire [1:0] _count_T_72 = {1'h0, _count_T_6} + {1'h0, _count_T_7}; // @[ALU.scala:139:23]
wire [1:0] _count_T_73 = _count_T_72; // @[ALU.scala:139:23]
wire [2:0] _count_T_74 = {1'h0, _count_T_71} + {1'h0, _count_T_73}; // @[ALU.scala:139:23]
wire [2:0] _count_T_75 = _count_T_74; // @[ALU.scala:139:23]
wire [3:0] _count_T_76 = {1'h0, _count_T_69} + {1'h0, _count_T_75}; // @[ALU.scala:139:23]
wire [3:0] _count_T_77 = _count_T_76; // @[ALU.scala:139:23]
wire [1:0] _count_T_78 = {1'h0, _count_T_8} + {1'h0, _count_T_9}; // @[ALU.scala:139:23]
wire [1:0] _count_T_79 = _count_T_78; // @[ALU.scala:139:23]
wire [1:0] _count_T_80 = {1'h0, _count_T_10} + {1'h0, _count_T_11}; // @[ALU.scala:139:23]
wire [1:0] _count_T_81 = _count_T_80; // @[ALU.scala:139:23]
wire [2:0] _count_T_82 = {1'h0, _count_T_79} + {1'h0, _count_T_81}; // @[ALU.scala:139:23]
wire [2:0] _count_T_83 = _count_T_82; // @[ALU.scala:139:23]
wire [1:0] _count_T_84 = {1'h0, _count_T_12} + {1'h0, _count_T_13}; // @[ALU.scala:139:23]
wire [1:0] _count_T_85 = _count_T_84; // @[ALU.scala:139:23]
wire [1:0] _count_T_86 = {1'h0, _count_T_14} + {1'h0, _count_T_15}; // @[ALU.scala:139:23]
wire [1:0] _count_T_87 = _count_T_86; // @[ALU.scala:139:23]
wire [2:0] _count_T_88 = {1'h0, _count_T_85} + {1'h0, _count_T_87}; // @[ALU.scala:139:23]
wire [2:0] _count_T_89 = _count_T_88; // @[ALU.scala:139:23]
wire [3:0] _count_T_90 = {1'h0, _count_T_83} + {1'h0, _count_T_89}; // @[ALU.scala:139:23]
wire [3:0] _count_T_91 = _count_T_90; // @[ALU.scala:139:23]
wire [4:0] _count_T_92 = {1'h0, _count_T_77} + {1'h0, _count_T_91}; // @[ALU.scala:139:23]
wire [4:0] _count_T_93 = _count_T_92; // @[ALU.scala:139:23]
wire [1:0] _count_T_94 = {1'h0, _count_T_16} + {1'h0, _count_T_17}; // @[ALU.scala:139:23]
wire [1:0] _count_T_95 = _count_T_94; // @[ALU.scala:139:23]
wire [1:0] _count_T_96 = {1'h0, _count_T_18} + {1'h0, _count_T_19}; // @[ALU.scala:139:23]
wire [1:0] _count_T_97 = _count_T_96; // @[ALU.scala:139:23]
wire [2:0] _count_T_98 = {1'h0, _count_T_95} + {1'h0, _count_T_97}; // @[ALU.scala:139:23]
wire [2:0] _count_T_99 = _count_T_98; // @[ALU.scala:139:23]
wire [1:0] _count_T_100 = {1'h0, _count_T_20} + {1'h0, _count_T_21}; // @[ALU.scala:139:23]
wire [1:0] _count_T_101 = _count_T_100; // @[ALU.scala:139:23]
wire [1:0] _count_T_102 = {1'h0, _count_T_22} + {1'h0, _count_T_23}; // @[ALU.scala:139:23]
wire [1:0] _count_T_103 = _count_T_102; // @[ALU.scala:139:23]
wire [2:0] _count_T_104 = {1'h0, _count_T_101} + {1'h0, _count_T_103}; // @[ALU.scala:139:23]
wire [2:0] _count_T_105 = _count_T_104; // @[ALU.scala:139:23]
wire [3:0] _count_T_106 = {1'h0, _count_T_99} + {1'h0, _count_T_105}; // @[ALU.scala:139:23]
wire [3:0] _count_T_107 = _count_T_106; // @[ALU.scala:139:23]
wire [1:0] _count_T_108 = {1'h0, _count_T_24} + {1'h0, _count_T_25}; // @[ALU.scala:139:23]
wire [1:0] _count_T_109 = _count_T_108; // @[ALU.scala:139:23]
wire [1:0] _count_T_110 = {1'h0, _count_T_26} + {1'h0, _count_T_27}; // @[ALU.scala:139:23]
wire [1:0] _count_T_111 = _count_T_110; // @[ALU.scala:139:23]
wire [2:0] _count_T_112 = {1'h0, _count_T_109} + {1'h0, _count_T_111}; // @[ALU.scala:139:23]
wire [2:0] _count_T_113 = _count_T_112; // @[ALU.scala:139:23]
wire [1:0] _count_T_114 = {1'h0, _count_T_28} + {1'h0, _count_T_29}; // @[ALU.scala:139:23]
wire [1:0] _count_T_115 = _count_T_114; // @[ALU.scala:139:23]
wire [1:0] _count_T_116 = {1'h0, _count_T_30} + {1'h0, _count_T_31}; // @[ALU.scala:139:23]
wire [1:0] _count_T_117 = _count_T_116; // @[ALU.scala:139:23]
wire [2:0] _count_T_118 = {1'h0, _count_T_115} + {1'h0, _count_T_117}; // @[ALU.scala:139:23]
wire [2:0] _count_T_119 = _count_T_118; // @[ALU.scala:139:23]
wire [3:0] _count_T_120 = {1'h0, _count_T_113} + {1'h0, _count_T_119}; // @[ALU.scala:139:23]
wire [3:0] _count_T_121 = _count_T_120; // @[ALU.scala:139:23]
wire [4:0] _count_T_122 = {1'h0, _count_T_107} + {1'h0, _count_T_121}; // @[ALU.scala:139:23]
wire [4:0] _count_T_123 = _count_T_122; // @[ALU.scala:139:23]
wire [5:0] _count_T_124 = {1'h0, _count_T_93} + {1'h0, _count_T_123}; // @[ALU.scala:139:23]
wire [5:0] _count_T_125 = _count_T_124; // @[ALU.scala:139:23]
wire [1:0] _count_T_126 = {1'h0, _count_T_32} + {1'h0, _count_T_33}; // @[ALU.scala:139:23]
wire [1:0] _count_T_127 = _count_T_126; // @[ALU.scala:139:23]
wire [1:0] _count_T_128 = {1'h0, _count_T_34} + {1'h0, _count_T_35}; // @[ALU.scala:139:23]
wire [1:0] _count_T_129 = _count_T_128; // @[ALU.scala:139:23]
wire [2:0] _count_T_130 = {1'h0, _count_T_127} + {1'h0, _count_T_129}; // @[ALU.scala:139:23]
wire [2:0] _count_T_131 = _count_T_130; // @[ALU.scala:139:23]
wire [1:0] _count_T_132 = {1'h0, _count_T_36} + {1'h0, _count_T_37}; // @[ALU.scala:139:23]
wire [1:0] _count_T_133 = _count_T_132; // @[ALU.scala:139:23]
wire [1:0] _count_T_134 = {1'h0, _count_T_38} + {1'h0, _count_T_39}; // @[ALU.scala:139:23]
wire [1:0] _count_T_135 = _count_T_134; // @[ALU.scala:139:23]
wire [2:0] _count_T_136 = {1'h0, _count_T_133} + {1'h0, _count_T_135}; // @[ALU.scala:139:23]
wire [2:0] _count_T_137 = _count_T_136; // @[ALU.scala:139:23]
wire [3:0] _count_T_138 = {1'h0, _count_T_131} + {1'h0, _count_T_137}; // @[ALU.scala:139:23]
wire [3:0] _count_T_139 = _count_T_138; // @[ALU.scala:139:23]
wire [1:0] _count_T_140 = {1'h0, _count_T_40} + {1'h0, _count_T_41}; // @[ALU.scala:139:23]
wire [1:0] _count_T_141 = _count_T_140; // @[ALU.scala:139:23]
wire [1:0] _count_T_142 = {1'h0, _count_T_42} + {1'h0, _count_T_43}; // @[ALU.scala:139:23]
wire [1:0] _count_T_143 = _count_T_142; // @[ALU.scala:139:23]
wire [2:0] _count_T_144 = {1'h0, _count_T_141} + {1'h0, _count_T_143}; // @[ALU.scala:139:23]
wire [2:0] _count_T_145 = _count_T_144; // @[ALU.scala:139:23]
wire [1:0] _count_T_146 = {1'h0, _count_T_44} + {1'h0, _count_T_45}; // @[ALU.scala:139:23]
wire [1:0] _count_T_147 = _count_T_146; // @[ALU.scala:139:23]
wire [1:0] _count_T_148 = {1'h0, _count_T_46} + {1'h0, _count_T_47}; // @[ALU.scala:139:23]
wire [1:0] _count_T_149 = _count_T_148; // @[ALU.scala:139:23]
wire [2:0] _count_T_150 = {1'h0, _count_T_147} + {1'h0, _count_T_149}; // @[ALU.scala:139:23]
wire [2:0] _count_T_151 = _count_T_150; // @[ALU.scala:139:23]
wire [3:0] _count_T_152 = {1'h0, _count_T_145} + {1'h0, _count_T_151}; // @[ALU.scala:139:23]
wire [3:0] _count_T_153 = _count_T_152; // @[ALU.scala:139:23]
wire [4:0] _count_T_154 = {1'h0, _count_T_139} + {1'h0, _count_T_153}; // @[ALU.scala:139:23]
wire [4:0] _count_T_155 = _count_T_154; // @[ALU.scala:139:23]
wire [1:0] _count_T_156 = {1'h0, _count_T_48} + {1'h0, _count_T_49}; // @[ALU.scala:139:23]
wire [1:0] _count_T_157 = _count_T_156; // @[ALU.scala:139:23]
wire [1:0] _count_T_158 = {1'h0, _count_T_50} + {1'h0, _count_T_51}; // @[ALU.scala:139:23]
wire [1:0] _count_T_159 = _count_T_158; // @[ALU.scala:139:23]
wire [2:0] _count_T_160 = {1'h0, _count_T_157} + {1'h0, _count_T_159}; // @[ALU.scala:139:23]
wire [2:0] _count_T_161 = _count_T_160; // @[ALU.scala:139:23]
wire [1:0] _count_T_162 = {1'h0, _count_T_52} + {1'h0, _count_T_53}; // @[ALU.scala:139:23]
wire [1:0] _count_T_163 = _count_T_162; // @[ALU.scala:139:23]
wire [1:0] _count_T_164 = {1'h0, _count_T_54} + {1'h0, _count_T_55}; // @[ALU.scala:139:23]
wire [1:0] _count_T_165 = _count_T_164; // @[ALU.scala:139:23]
wire [2:0] _count_T_166 = {1'h0, _count_T_163} + {1'h0, _count_T_165}; // @[ALU.scala:139:23]
wire [2:0] _count_T_167 = _count_T_166; // @[ALU.scala:139:23]
wire [3:0] _count_T_168 = {1'h0, _count_T_161} + {1'h0, _count_T_167}; // @[ALU.scala:139:23]
wire [3:0] _count_T_169 = _count_T_168; // @[ALU.scala:139:23]
wire [1:0] _count_T_170 = {1'h0, _count_T_56} + {1'h0, _count_T_57}; // @[ALU.scala:139:23]
wire [1:0] _count_T_171 = _count_T_170; // @[ALU.scala:139:23]
wire [1:0] _count_T_172 = {1'h0, _count_T_58} + {1'h0, _count_T_59}; // @[ALU.scala:139:23]
wire [1:0] _count_T_173 = _count_T_172; // @[ALU.scala:139:23]
wire [2:0] _count_T_174 = {1'h0, _count_T_171} + {1'h0, _count_T_173}; // @[ALU.scala:139:23]
wire [2:0] _count_T_175 = _count_T_174; // @[ALU.scala:139:23]
wire [1:0] _count_T_176 = {1'h0, _count_T_60} + {1'h0, _count_T_61}; // @[ALU.scala:139:23]
wire [1:0] _count_T_177 = _count_T_176; // @[ALU.scala:139:23]
wire [1:0] _count_T_178 = {1'h0, _count_T_62} + {1'h0, _count_T_63}; // @[ALU.scala:139:23]
wire [1:0] _count_T_179 = _count_T_178; // @[ALU.scala:139:23]
wire [2:0] _count_T_180 = {1'h0, _count_T_177} + {1'h0, _count_T_179}; // @[ALU.scala:139:23]
wire [2:0] _count_T_181 = _count_T_180; // @[ALU.scala:139:23]
wire [3:0] _count_T_182 = {1'h0, _count_T_175} + {1'h0, _count_T_181}; // @[ALU.scala:139:23]
wire [3:0] _count_T_183 = _count_T_182; // @[ALU.scala:139:23]
wire [4:0] _count_T_184 = {1'h0, _count_T_169} + {1'h0, _count_T_183}; // @[ALU.scala:139:23]
wire [4:0] _count_T_185 = _count_T_184; // @[ALU.scala:139:23]
wire [5:0] _count_T_186 = {1'h0, _count_T_155} + {1'h0, _count_T_185}; // @[ALU.scala:139:23]
wire [5:0] _count_T_187 = _count_T_186; // @[ALU.scala:139:23]
wire [6:0] _count_T_188 = {1'h0, _count_T_125} + {1'h0, _count_T_187}; // @[ALU.scala:139:23]
wire [6:0] count = _count_T_188; // @[ALU.scala:139:23]
wire [7:0] _in1_bytes_T; // @[ALU.scala:140:34]
wire [7:0] _in1_bytes_T_1; // @[ALU.scala:140:34]
wire [7:0] _rev8_WIRE_7 = in1_bytes_0; // @[ALU.scala:140:34, :142:21]
wire [7:0] _in1_bytes_T_2; // @[ALU.scala:140:34]
wire [7:0] _rev8_WIRE_6 = in1_bytes_1; // @[ALU.scala:140:34, :142:21]
wire [7:0] _in1_bytes_T_3; // @[ALU.scala:140:34]
wire [7:0] _rev8_WIRE_5 = in1_bytes_2; // @[ALU.scala:140:34, :142:21]
wire [7:0] _in1_bytes_T_4; // @[ALU.scala:140:34]
wire [7:0] _rev8_WIRE_4 = in1_bytes_3; // @[ALU.scala:140:34, :142:21]
wire [7:0] _in1_bytes_T_5; // @[ALU.scala:140:34]
wire [7:0] _rev8_WIRE_3 = in1_bytes_4; // @[ALU.scala:140:34, :142:21]
wire [7:0] _in1_bytes_T_6; // @[ALU.scala:140:34]
wire [7:0] _rev8_WIRE_2 = in1_bytes_5; // @[ALU.scala:140:34, :142:21]
wire [7:0] _in1_bytes_T_7; // @[ALU.scala:140:34]
wire [7:0] _rev8_WIRE_1 = in1_bytes_6; // @[ALU.scala:140:34, :142:21]
wire [7:0] in1_bytes_7; // @[ALU.scala:140:34]
wire [7:0] _rev8_WIRE_0 = in1_bytes_7; // @[ALU.scala:140:34, :142:21]
assign _in1_bytes_T = _in1_bytes_WIRE[7:0]; // @[ALU.scala:140:34]
assign in1_bytes_0 = _in1_bytes_T; // @[ALU.scala:140:34]
assign _in1_bytes_T_1 = _in1_bytes_WIRE[15:8]; // @[ALU.scala:140:34]
assign in1_bytes_1 = _in1_bytes_T_1; // @[ALU.scala:140:34]
assign _in1_bytes_T_2 = _in1_bytes_WIRE[23:16]; // @[ALU.scala:140:34]
assign in1_bytes_2 = _in1_bytes_T_2; // @[ALU.scala:140:34]
assign _in1_bytes_T_3 = _in1_bytes_WIRE[31:24]; // @[ALU.scala:140:34]
assign in1_bytes_3 = _in1_bytes_T_3; // @[ALU.scala:140:34]
assign _in1_bytes_T_4 = _in1_bytes_WIRE[39:32]; // @[ALU.scala:140:34]
assign in1_bytes_4 = _in1_bytes_T_4; // @[ALU.scala:140:34]
assign _in1_bytes_T_5 = _in1_bytes_WIRE[47:40]; // @[ALU.scala:140:34]
assign in1_bytes_5 = _in1_bytes_T_5; // @[ALU.scala:140:34]
assign _in1_bytes_T_6 = _in1_bytes_WIRE[55:48]; // @[ALU.scala:140:34]
assign in1_bytes_6 = _in1_bytes_T_6; // @[ALU.scala:140:34]
assign _in1_bytes_T_7 = _in1_bytes_WIRE[63:56]; // @[ALU.scala:140:34]
assign in1_bytes_7 = _in1_bytes_T_7; // @[ALU.scala:140:34]
wire _orcb_T = |in1_bytes_0; // @[ALU.scala:140:34, :141:51]
wire [7:0] _orcb_T_1 = {8{_orcb_T}}; // @[ALU.scala:141:{45,51}]
wire [7:0] _orcb_WIRE_0 = _orcb_T_1; // @[ALU.scala:141:{21,45}]
wire _orcb_T_2 = |in1_bytes_1; // @[ALU.scala:140:34, :141:51]
wire [7:0] _orcb_T_3 = {8{_orcb_T_2}}; // @[ALU.scala:141:{45,51}]
wire [7:0] _orcb_WIRE_1 = _orcb_T_3; // @[ALU.scala:141:{21,45}]
wire _orcb_T_4 = |in1_bytes_2; // @[ALU.scala:140:34, :141:51]
wire [7:0] _orcb_T_5 = {8{_orcb_T_4}}; // @[ALU.scala:141:{45,51}]
wire [7:0] _orcb_WIRE_2 = _orcb_T_5; // @[ALU.scala:141:{21,45}]
wire _orcb_T_6 = |in1_bytes_3; // @[ALU.scala:140:34, :141:51]
wire [7:0] _orcb_T_7 = {8{_orcb_T_6}}; // @[ALU.scala:141:{45,51}]
wire [7:0] _orcb_WIRE_3 = _orcb_T_7; // @[ALU.scala:141:{21,45}]
wire _orcb_T_8 = |in1_bytes_4; // @[ALU.scala:140:34, :141:51]
wire [7:0] _orcb_T_9 = {8{_orcb_T_8}}; // @[ALU.scala:141:{45,51}]
wire [7:0] _orcb_WIRE_4 = _orcb_T_9; // @[ALU.scala:141:{21,45}]
wire _orcb_T_10 = |in1_bytes_5; // @[ALU.scala:140:34, :141:51]
wire [7:0] _orcb_T_11 = {8{_orcb_T_10}}; // @[ALU.scala:141:{45,51}]
wire [7:0] _orcb_WIRE_5 = _orcb_T_11; // @[ALU.scala:141:{21,45}]
wire _orcb_T_12 = |in1_bytes_6; // @[ALU.scala:140:34, :141:51]
wire [7:0] _orcb_T_13 = {8{_orcb_T_12}}; // @[ALU.scala:141:{45,51}]
wire [7:0] _orcb_WIRE_6 = _orcb_T_13; // @[ALU.scala:141:{21,45}]
wire _orcb_T_14 = |in1_bytes_7; // @[ALU.scala:140:34, :141:51]
wire [7:0] _orcb_T_15 = {8{_orcb_T_14}}; // @[ALU.scala:141:{45,51}]
wire [7:0] _orcb_WIRE_7 = _orcb_T_15; // @[ALU.scala:141:{21,45}]
wire [15:0] orcb_lo_lo = {_orcb_WIRE_1, _orcb_WIRE_0}; // @[ALU.scala:141:{21,62}]
wire [15:0] orcb_lo_hi = {_orcb_WIRE_3, _orcb_WIRE_2}; // @[ALU.scala:141:{21,62}]
wire [31:0] orcb_lo = {orcb_lo_hi, orcb_lo_lo}; // @[ALU.scala:141:62]
wire [15:0] orcb_hi_lo = {_orcb_WIRE_5, _orcb_WIRE_4}; // @[ALU.scala:141:{21,62}]
wire [15:0] orcb_hi_hi = {_orcb_WIRE_7, _orcb_WIRE_6}; // @[ALU.scala:141:{21,62}]
wire [31:0] orcb_hi = {orcb_hi_hi, orcb_hi_lo}; // @[ALU.scala:141:62]
wire [63:0] orcb = {orcb_hi, orcb_lo}; // @[ALU.scala:141:62]
wire [15:0] rev8_lo_lo = {_rev8_WIRE_1, _rev8_WIRE_0}; // @[ALU.scala:142:{21,41}]
wire [15:0] rev8_lo_hi = {_rev8_WIRE_3, _rev8_WIRE_2}; // @[ALU.scala:142:{21,41}]
wire [31:0] rev8_lo = {rev8_lo_hi, rev8_lo_lo}; // @[ALU.scala:142:41]
wire [15:0] rev8_hi_lo = {_rev8_WIRE_5, _rev8_WIRE_4}; // @[ALU.scala:142:{21,41}]
wire [15:0] rev8_hi_hi = {_rev8_WIRE_7, _rev8_WIRE_6}; // @[ALU.scala:142:{21,41}]
wire [31:0] rev8_hi = {rev8_hi_hi, rev8_hi_lo}; // @[ALU.scala:142:41]
wire [63:0] rev8 = {rev8_hi, rev8_lo}; // @[ALU.scala:142:41]
wire [11:0] _unary_T = io_in2_0[11:0]; // @[ALU.scala:83:7, :143:31]
wire [15:0] _unary_T_1 = io_in1_0[15:0]; // @[ALU.scala:83:7, :146:22]
wire [15:0] _unary_T_8 = io_in1_0[15:0]; // @[ALU.scala:83:7, :146:22, :148:51]
wire _unary_T_2 = io_in1_0[7]; // @[ALU.scala:83:7, :147:35]
wire [55:0] _unary_T_3 = {56{_unary_T_2}}; // @[ALU.scala:147:{20,35}]
wire [7:0] _unary_T_4 = io_in1_0[7:0]; // @[ALU.scala:83:7, :147:49]
wire [63:0] _unary_T_5 = {_unary_T_3, _unary_T_4}; // @[ALU.scala:147:{20,40,49}]
wire _unary_T_6 = io_in1_0[15]; // @[ALU.scala:83:7, :148:36]
wire [47:0] _unary_T_7 = {48{_unary_T_6}}; // @[ALU.scala:148:{20,36}]
wire [63:0] _unary_T_9 = {_unary_T_7, _unary_T_8}; // @[ALU.scala:148:{20,42,51}]
wire _unary_T_10 = _unary_T == 12'h287; // @[ALU.scala:143:{31,45}]
wire [63:0] _unary_T_11 = _unary_T_10 ? orcb : {57'h0, count}; // @[ALU.scala:139:23, :141:62, :143:45]
wire _unary_T_12 = _unary_T == 12'h6B8; // @[ALU.scala:143:{31,45}]
wire [63:0] _unary_T_13 = _unary_T_12 ? rev8 : _unary_T_11; // @[ALU.scala:142:41, :143:45]
wire _unary_T_14 = _unary_T == 12'h80; // @[ALU.scala:143:{31,45}]
wire [63:0] _unary_T_15 = _unary_T_14 ? {48'h0, _unary_T_1} : _unary_T_13; // @[ALU.scala:143:45, :146:22]
wire _unary_T_16 = _unary_T == 12'h604; // @[ALU.scala:143:{31,45}]
wire [63:0] _unary_T_17 = _unary_T_16 ? _unary_T_5 : _unary_T_15; // @[ALU.scala:143:45, :147:40]
wire _unary_T_18 = _unary_T == 12'h605; // @[ALU.scala:143:{31,45}]
wire [63:0] unary = _unary_T_18 ? _unary_T_9 : _unary_T_17; // @[ALU.scala:143:45, :148:42]
wire [63:0] maxmin_out = io_cmp_out ? io_in2_0 : io_in1_0; // @[ALU.scala:83:7, :152:23]
wire _rot_shamt_T = ~io_dw_0; // @[ALU.scala:83:7, :130:32, :155:29]
wire [6:0] _rot_shamt_T_1 = _rot_shamt_T ? 7'h20 : 7'h40; // @[ALU.scala:155:{22,29}]
wire [7:0] _rot_shamt_T_2 = {1'h0, _rot_shamt_T_1} - {2'h0, shamt}; // @[package.scala:16:47]
wire [6:0] rot_shamt = _rot_shamt_T_2[6:0]; // @[ALU.scala:155:54]
wire [63:0] _rotin_T_4 = {32'h0, _rotin_T_3}; // @[ALU.scala:156:44]
wire [63:0] _rotin_T_6 = {_rotin_T_5, 32'h0}; // @[ALU.scala:156:44]
wire [63:0] _rotin_T_8 = _rotin_T_6 & 64'hFFFFFFFF00000000; // @[ALU.scala:156:44]
wire [63:0] _rotin_T_9 = _rotin_T_4 | _rotin_T_8; // @[ALU.scala:156:44]
wire [47:0] _rotin_T_13 = _rotin_T_9[63:16]; // @[ALU.scala:156:44]
wire [63:0] _rotin_T_14 = {16'h0, _rotin_T_13 & 48'hFFFF0000FFFF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [47:0] _rotin_T_15 = _rotin_T_9[47:0]; // @[ALU.scala:156:44]
wire [63:0] _rotin_T_16 = {_rotin_T_15, 16'h0}; // @[ALU.scala:106:46, :156:44]
wire [63:0] _rotin_T_18 = _rotin_T_16 & 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_19 = _rotin_T_14 | _rotin_T_18; // @[ALU.scala:156:44]
wire [55:0] _rotin_T_23 = _rotin_T_19[63:8]; // @[ALU.scala:156:44]
wire [63:0] _rotin_T_24 = {8'h0, _rotin_T_23 & 56'hFF00FF00FF00FF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [55:0] _rotin_T_25 = _rotin_T_19[55:0]; // @[ALU.scala:156:44]
wire [63:0] _rotin_T_26 = {_rotin_T_25, 8'h0}; // @[ALU.scala:156:44]
wire [63:0] _rotin_T_28 = _rotin_T_26 & 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_29 = _rotin_T_24 | _rotin_T_28; // @[ALU.scala:156:44]
wire [59:0] _rotin_T_33 = _rotin_T_29[63:4]; // @[ALU.scala:156:44]
wire [63:0] _rotin_T_34 = {4'h0, _rotin_T_33 & 60'hF0F0F0F0F0F0F0F}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [59:0] _rotin_T_35 = _rotin_T_29[59:0]; // @[ALU.scala:156:44]
wire [63:0] _rotin_T_36 = {_rotin_T_35, 4'h0}; // @[ALU.scala:106:46, :156:44]
wire [63:0] _rotin_T_38 = _rotin_T_36 & 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_39 = _rotin_T_34 | _rotin_T_38; // @[ALU.scala:156:44]
wire [61:0] _rotin_T_43 = _rotin_T_39[63:2]; // @[ALU.scala:156:44]
wire [63:0] _rotin_T_44 = {2'h0, _rotin_T_43 & 62'h3333333333333333}; // @[package.scala:16:47]
wire [61:0] _rotin_T_45 = _rotin_T_39[61:0]; // @[ALU.scala:156:44]
wire [63:0] _rotin_T_46 = {_rotin_T_45, 2'h0}; // @[package.scala:16:47]
wire [63:0] _rotin_T_48 = _rotin_T_46 & 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_49 = _rotin_T_44 | _rotin_T_48; // @[ALU.scala:156:44]
wire [62:0] _rotin_T_53 = _rotin_T_49[63:1]; // @[ALU.scala:156:44]
wire [63:0] _rotin_T_54 = {1'h0, _rotin_T_53 & 63'h5555555555555555}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [62:0] _rotin_T_55 = _rotin_T_49[62:0]; // @[ALU.scala:156:44]
wire [63:0] _rotin_T_56 = {_rotin_T_55, 1'h0}; // @[ALU.scala:156:44]
wire [63:0] _rotin_T_58 = _rotin_T_56 & 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_59 = _rotin_T_54 | _rotin_T_58; // @[ALU.scala:156:44]
wire [63:0] rotin = _rotin_T ? shin_r : _rotin_T_59; // @[ALU.scala:104:18, :156:{18,24,44}]
wire [63:0] _rotout_r_T = rotin >> rot_shamt; // @[ALU.scala:155:54, :156:18, :157:25]
wire [63:0] rotout_r = _rotout_r_T; // @[ALU.scala:157:{25,38}]
wire [31:0] _rotout_l_T_2 = rotout_r[63:32]; // @[ALU.scala:157:38, :158:25]
wire [63:0] _rotout_l_T_3 = {32'h0, _rotout_l_T_2}; // @[ALU.scala:158:25]
wire [31:0] _rotout_l_T_4 = rotout_r[31:0]; // @[ALU.scala:157:38, :158:25]
wire [63:0] _rotout_l_T_5 = {_rotout_l_T_4, 32'h0}; // @[ALU.scala:158:25]
wire [63:0] _rotout_l_T_7 = _rotout_l_T_5 & 64'hFFFFFFFF00000000; // @[ALU.scala:158:25]
wire [63:0] _rotout_l_T_8 = _rotout_l_T_3 | _rotout_l_T_7; // @[ALU.scala:158:25]
wire [47:0] _rotout_l_T_12 = _rotout_l_T_8[63:16]; // @[ALU.scala:158:25]
wire [63:0] _rotout_l_T_13 = {16'h0, _rotout_l_T_12 & 48'hFFFF0000FFFF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [47:0] _rotout_l_T_14 = _rotout_l_T_8[47:0]; // @[ALU.scala:158:25]
wire [63:0] _rotout_l_T_15 = {_rotout_l_T_14, 16'h0}; // @[ALU.scala:106:46, :158:25]
wire [63:0] _rotout_l_T_17 = _rotout_l_T_15 & 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_18 = _rotout_l_T_13 | _rotout_l_T_17; // @[ALU.scala:158:25]
wire [55:0] _rotout_l_T_22 = _rotout_l_T_18[63:8]; // @[ALU.scala:158:25]
wire [63:0] _rotout_l_T_23 = {8'h0, _rotout_l_T_22 & 56'hFF00FF00FF00FF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [55:0] _rotout_l_T_24 = _rotout_l_T_18[55:0]; // @[ALU.scala:158:25]
wire [63:0] _rotout_l_T_25 = {_rotout_l_T_24, 8'h0}; // @[ALU.scala:158:25]
wire [63:0] _rotout_l_T_27 = _rotout_l_T_25 & 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_28 = _rotout_l_T_23 | _rotout_l_T_27; // @[ALU.scala:158:25]
wire [59:0] _rotout_l_T_32 = _rotout_l_T_28[63:4]; // @[ALU.scala:158:25]
wire [63:0] _rotout_l_T_33 = {4'h0, _rotout_l_T_32 & 60'hF0F0F0F0F0F0F0F}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [59:0] _rotout_l_T_34 = _rotout_l_T_28[59:0]; // @[ALU.scala:158:25]
wire [63:0] _rotout_l_T_35 = {_rotout_l_T_34, 4'h0}; // @[ALU.scala:106:46, :158:25]
wire [63:0] _rotout_l_T_37 = _rotout_l_T_35 & 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_38 = _rotout_l_T_33 | _rotout_l_T_37; // @[ALU.scala:158:25]
wire [61:0] _rotout_l_T_42 = _rotout_l_T_38[63:2]; // @[ALU.scala:158:25]
wire [63:0] _rotout_l_T_43 = {2'h0, _rotout_l_T_42 & 62'h3333333333333333}; // @[package.scala:16:47]
wire [61:0] _rotout_l_T_44 = _rotout_l_T_38[61:0]; // @[ALU.scala:158:25]
wire [63:0] _rotout_l_T_45 = {_rotout_l_T_44, 2'h0}; // @[package.scala:16:47]
wire [63:0] _rotout_l_T_47 = _rotout_l_T_45 & 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_48 = _rotout_l_T_43 | _rotout_l_T_47; // @[ALU.scala:158:25]
wire [62:0] _rotout_l_T_52 = _rotout_l_T_48[63:1]; // @[ALU.scala:158:25]
wire [63:0] _rotout_l_T_53 = {1'h0, _rotout_l_T_52 & 63'h5555555555555555}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [62:0] _rotout_l_T_54 = _rotout_l_T_48[62:0]; // @[ALU.scala:158:25]
wire [63:0] _rotout_l_T_55 = {_rotout_l_T_54, 1'h0}; // @[ALU.scala:158:25]
wire [63:0] _rotout_l_T_57 = _rotout_l_T_55 & 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] rotout_l = _rotout_l_T_53 | _rotout_l_T_57; // @[ALU.scala:158:25]
wire [63:0] _rotout_T_1 = _rotout_T ? rotout_r : rotout_l; // @[ALU.scala:157:38, :158:25, :159:{19,25}]
wire [63:0] _rotout_T_3 = _rotout_T_2 ? shout_l : shout_r; // @[ALU.scala:107:73, :108:24, :159:{55,61}]
wire [63:0] rotout = _rotout_T_1 | _rotout_T_3; // @[ALU.scala:159:{19,50,55}]
wire _out_T = io_fn_0 == 5'h0; // @[ALU.scala:83:7, :161:47]
wire [63:0] _out_T_1 = _out_T ? io_adder_out : shift_logic; // @[ALU.scala:83:7, :123:52, :161:47]
wire _out_T_2 = io_fn_0 == 5'hA; // @[ALU.scala:83:7, :161:47]
wire [63:0] out = _out_T_2 ? io_adder_out : _out_T_1; // @[ALU.scala:83:7, :161:47]
wire _io_out_T = out[31]; // @[ALU.scala:161:47, :178:56]
wire [31:0] _io_out_T_1 = {32{_io_out_T}}; // @[ALU.scala:178:{48,56}]
wire [31:0] _io_out_T_2 = out[31:0]; // @[ALU.scala:161:47, :178:66]
wire [63:0] _io_out_T_3 = {_io_out_T_1, _io_out_T_2}; // @[ALU.scala:178:{43,48,66}]
assign io_out_0 = io_dw_0 ? out : _io_out_T_3; // @[ALU.scala:83:7, :161:47, :175:10, :178:{28,37,43}]
assign io_out = io_out_0; // @[ALU.scala:83:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLSplitACDxBENoC_be_router_10ClockSinkDomain :
output auto : { egress_width_widget_out : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<74>, ingress_id : UInt}}}, flip ingress_width_widget_in : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<74>, egress_id : UInt}}}, routers_debug_out : { va_stall : UInt[2], sa_stall : UInt[2]}, routers_source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<4>, flip vc_free : UInt<4>}, flip routers_dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<4>, flip vc_free : UInt<4>}, flip clock_in : { clock : Clock, reset : Reset}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst routers of Router_23
connect routers.clock, childClock
connect routers.reset, childReset
inst ingress_width_widget of IngressWidthWidget_11
connect ingress_width_widget.clock, childClock
connect ingress_width_widget.reset, childReset
inst egress_width_widget of EgressWidthWidget_11
connect egress_width_widget.clock, childClock
connect egress_width_widget.reset, childReset
wire clockNodeIn : { clock : Clock, reset : Reset}
invalidate clockNodeIn.reset
invalidate clockNodeIn.clock
connect egress_width_widget.auto.in, routers.auto.egress_nodes_out
connect routers.auto.ingress_nodes_in, ingress_width_widget.auto.out
connect clockNodeIn, auto.clock_in
connect routers.auto.dest_nodes_in, auto.routers_dest_nodes_in
connect routers.auto.source_nodes_out.vc_free, auto.routers_source_nodes_out.vc_free
connect routers.auto.source_nodes_out.credit_return, auto.routers_source_nodes_out.credit_return
connect auto.routers_source_nodes_out.flit, routers.auto.source_nodes_out.flit
connect auto.routers_debug_out, routers.auto.debug_out
connect ingress_width_widget.auto.in, auto.ingress_width_widget_in
connect auto.egress_width_widget_out.flit.bits, egress_width_widget.auto.out.flit.bits
connect auto.egress_width_widget_out.flit.valid, egress_width_widget.auto.out.flit.valid
connect egress_width_widget.auto.out.flit.ready, auto.egress_width_widget_out.flit.ready
connect childClock, clockNodeIn.clock
connect childReset, clockNodeIn.reset
connect clock, clockNodeIn.clock
connect reset, clockNodeIn.reset | module TLSplitACDxBENoC_be_router_10ClockSinkDomain( // @[ClockDomain.scala:14:9]
output auto_egress_width_widget_out_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_width_widget_out_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_width_widget_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [73:0] auto_egress_width_widget_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_ingress_width_widget_in_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_ingress_width_widget_in_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_ingress_width_widget_in_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_ingress_width_widget_in_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [73:0] auto_ingress_width_widget_in_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_ingress_width_widget_in_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [36:0] auto_routers_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [36:0] auto_routers_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_dest_nodes_in_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
wire _egress_width_widget_auto_in_flit_ready; // @[WidthWidget.scala:111:43]
wire _ingress_width_widget_auto_out_flit_valid; // @[WidthWidget.scala:88:44]
wire _ingress_width_widget_auto_out_flit_bits_head; // @[WidthWidget.scala:88:44]
wire _ingress_width_widget_auto_out_flit_bits_tail; // @[WidthWidget.scala:88:44]
wire [36:0] _ingress_width_widget_auto_out_flit_bits_payload; // @[WidthWidget.scala:88:44]
wire [3:0] _ingress_width_widget_auto_out_flit_bits_egress_id; // @[WidthWidget.scala:88:44]
wire _routers_auto_egress_nodes_out_flit_valid; // @[NoC.scala:67:22]
wire _routers_auto_egress_nodes_out_flit_bits_head; // @[NoC.scala:67:22]
wire _routers_auto_egress_nodes_out_flit_bits_tail; // @[NoC.scala:67:22]
wire [36:0] _routers_auto_egress_nodes_out_flit_bits_payload; // @[NoC.scala:67:22]
wire _routers_auto_ingress_nodes_in_flit_ready; // @[NoC.scala:67:22]
Router_23 routers ( // @[NoC.scala:67:22]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0),
.auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1),
.auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0),
.auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1),
.auto_egress_nodes_out_flit_ready (_egress_width_widget_auto_in_flit_ready), // @[WidthWidget.scala:111:43]
.auto_egress_nodes_out_flit_valid (_routers_auto_egress_nodes_out_flit_valid),
.auto_egress_nodes_out_flit_bits_head (_routers_auto_egress_nodes_out_flit_bits_head),
.auto_egress_nodes_out_flit_bits_tail (_routers_auto_egress_nodes_out_flit_bits_tail),
.auto_egress_nodes_out_flit_bits_payload (_routers_auto_egress_nodes_out_flit_bits_payload),
.auto_ingress_nodes_in_flit_ready (_routers_auto_ingress_nodes_in_flit_ready),
.auto_ingress_nodes_in_flit_valid (_ingress_width_widget_auto_out_flit_valid), // @[WidthWidget.scala:88:44]
.auto_ingress_nodes_in_flit_bits_head (_ingress_width_widget_auto_out_flit_bits_head), // @[WidthWidget.scala:88:44]
.auto_ingress_nodes_in_flit_bits_tail (_ingress_width_widget_auto_out_flit_bits_tail), // @[WidthWidget.scala:88:44]
.auto_ingress_nodes_in_flit_bits_payload (_ingress_width_widget_auto_out_flit_bits_payload), // @[WidthWidget.scala:88:44]
.auto_ingress_nodes_in_flit_bits_egress_id (_ingress_width_widget_auto_out_flit_bits_egress_id), // @[WidthWidget.scala:88:44]
.auto_source_nodes_out_flit_0_valid (auto_routers_source_nodes_out_flit_0_valid),
.auto_source_nodes_out_flit_0_bits_head (auto_routers_source_nodes_out_flit_0_bits_head),
.auto_source_nodes_out_flit_0_bits_tail (auto_routers_source_nodes_out_flit_0_bits_tail),
.auto_source_nodes_out_flit_0_bits_payload (auto_routers_source_nodes_out_flit_0_bits_payload),
.auto_source_nodes_out_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_credit_return (auto_routers_source_nodes_out_credit_return),
.auto_source_nodes_out_vc_free (auto_routers_source_nodes_out_vc_free),
.auto_dest_nodes_in_flit_0_valid (auto_routers_dest_nodes_in_flit_0_valid),
.auto_dest_nodes_in_flit_0_bits_head (auto_routers_dest_nodes_in_flit_0_bits_head),
.auto_dest_nodes_in_flit_0_bits_tail (auto_routers_dest_nodes_in_flit_0_bits_tail),
.auto_dest_nodes_in_flit_0_bits_payload (auto_routers_dest_nodes_in_flit_0_bits_payload),
.auto_dest_nodes_in_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_credit_return (auto_routers_dest_nodes_in_credit_return),
.auto_dest_nodes_in_vc_free (auto_routers_dest_nodes_in_vc_free)
); // @[NoC.scala:67:22]
IngressWidthWidget ingress_width_widget ( // @[WidthWidget.scala:88:44]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_flit_ready (auto_ingress_width_widget_in_flit_ready),
.auto_in_flit_valid (auto_ingress_width_widget_in_flit_valid),
.auto_in_flit_bits_head (auto_ingress_width_widget_in_flit_bits_head),
.auto_in_flit_bits_tail (auto_ingress_width_widget_in_flit_bits_tail),
.auto_in_flit_bits_payload (auto_ingress_width_widget_in_flit_bits_payload),
.auto_in_flit_bits_egress_id (auto_ingress_width_widget_in_flit_bits_egress_id),
.auto_out_flit_ready (_routers_auto_ingress_nodes_in_flit_ready), // @[NoC.scala:67:22]
.auto_out_flit_valid (_ingress_width_widget_auto_out_flit_valid),
.auto_out_flit_bits_head (_ingress_width_widget_auto_out_flit_bits_head),
.auto_out_flit_bits_tail (_ingress_width_widget_auto_out_flit_bits_tail),
.auto_out_flit_bits_payload (_ingress_width_widget_auto_out_flit_bits_payload),
.auto_out_flit_bits_egress_id (_ingress_width_widget_auto_out_flit_bits_egress_id)
); // @[WidthWidget.scala:88:44]
EgressWidthWidget egress_width_widget ( // @[WidthWidget.scala:111:43]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_flit_ready (_egress_width_widget_auto_in_flit_ready),
.auto_in_flit_valid (_routers_auto_egress_nodes_out_flit_valid), // @[NoC.scala:67:22]
.auto_in_flit_bits_head (_routers_auto_egress_nodes_out_flit_bits_head), // @[NoC.scala:67:22]
.auto_in_flit_bits_tail (_routers_auto_egress_nodes_out_flit_bits_tail), // @[NoC.scala:67:22]
.auto_in_flit_bits_payload (_routers_auto_egress_nodes_out_flit_bits_payload), // @[NoC.scala:67:22]
.auto_out_flit_ready (1'h1), // @[LazyModuleImp.scala:107:25]
.auto_out_flit_valid (auto_egress_width_widget_out_flit_valid),
.auto_out_flit_bits_head (auto_egress_width_widget_out_flit_bits_head),
.auto_out_flit_bits_tail (auto_egress_width_widget_out_flit_bits_tail),
.auto_out_flit_bits_payload (auto_egress_width_widget_out_flit_bits_payload)
); // @[WidthWidget.scala:111:43]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module InputBuffer_116 :
input clock : Clock
input reset : Reset
output io : { flip enq : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>}}[10]}
cmem mem : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>} [4]
wire _heads_WIRE : UInt<2>[10]
connect _heads_WIRE[0], UInt<2>(0h0)
connect _heads_WIRE[1], UInt<2>(0h0)
connect _heads_WIRE[2], UInt<2>(0h0)
connect _heads_WIRE[3], UInt<2>(0h0)
connect _heads_WIRE[4], UInt<2>(0h0)
connect _heads_WIRE[5], UInt<2>(0h0)
connect _heads_WIRE[6], UInt<2>(0h0)
connect _heads_WIRE[7], UInt<2>(0h0)
connect _heads_WIRE[8], UInt<2>(0h0)
connect _heads_WIRE[9], UInt<2>(0h0)
regreset heads : UInt<2>[10], clock, reset, _heads_WIRE
wire _tails_WIRE : UInt<2>[10]
connect _tails_WIRE[0], UInt<2>(0h0)
connect _tails_WIRE[1], UInt<2>(0h0)
connect _tails_WIRE[2], UInt<2>(0h0)
connect _tails_WIRE[3], UInt<2>(0h0)
connect _tails_WIRE[4], UInt<2>(0h0)
connect _tails_WIRE[5], UInt<2>(0h0)
connect _tails_WIRE[6], UInt<2>(0h0)
connect _tails_WIRE[7], UInt<2>(0h0)
connect _tails_WIRE[8], UInt<2>(0h0)
connect _tails_WIRE[9], UInt<2>(0h0)
regreset tails : UInt<2>[10], clock, reset, _tails_WIRE
node empty_0 = eq(heads[0], tails[0])
node empty_1 = eq(heads[1], tails[1])
node empty_2 = eq(heads[2], tails[2])
node empty_3 = eq(heads[3], tails[3])
node empty_4 = eq(heads[4], tails[4])
node empty_5 = eq(heads[5], tails[5])
node empty_6 = eq(heads[6], tails[6])
node empty_7 = eq(heads[7], tails[7])
node empty_8 = eq(heads[8], tails[8])
node empty_9 = eq(heads[9], tails[9])
inst qs_0 of Queue1_BaseFlit_846
connect qs_0.clock, clock
connect qs_0.reset, reset
inst qs_1 of Queue1_BaseFlit_847
connect qs_1.clock, clock
connect qs_1.reset, reset
inst qs_2 of Queue1_BaseFlit_848
connect qs_2.clock, clock
connect qs_2.reset, reset
inst qs_3 of Queue1_BaseFlit_849
connect qs_3.clock, clock
connect qs_3.reset, reset
inst qs_4 of Queue1_BaseFlit_850
connect qs_4.clock, clock
connect qs_4.reset, reset
inst qs_5 of Queue1_BaseFlit_851
connect qs_5.clock, clock
connect qs_5.reset, reset
inst qs_6 of Queue1_BaseFlit_852
connect qs_6.clock, clock
connect qs_6.reset, reset
inst qs_7 of Queue1_BaseFlit_853
connect qs_7.clock, clock
connect qs_7.reset, reset
inst qs_8 of Queue1_BaseFlit_854
connect qs_8.clock, clock
connect qs_8.reset, reset
inst qs_9 of Queue1_BaseFlit_855
connect qs_9.clock, clock
connect qs_9.reset, reset
connect qs_0.io.enq.valid, UInt<1>(0h0)
connect qs_1.io.enq.valid, UInt<1>(0h0)
connect qs_2.io.enq.valid, UInt<1>(0h0)
connect qs_3.io.enq.valid, UInt<1>(0h0)
connect qs_4.io.enq.valid, UInt<1>(0h0)
connect qs_5.io.enq.valid, UInt<1>(0h0)
connect qs_6.io.enq.valid, UInt<1>(0h0)
connect qs_7.io.enq.valid, UInt<1>(0h0)
connect qs_8.io.enq.valid, UInt<1>(0h0)
connect qs_9.io.enq.valid, UInt<1>(0h0)
invalidate qs_0.io.enq.bits.payload
invalidate qs_0.io.enq.bits.tail
invalidate qs_0.io.enq.bits.head
invalidate qs_1.io.enq.bits.payload
invalidate qs_1.io.enq.bits.tail
invalidate qs_1.io.enq.bits.head
invalidate qs_2.io.enq.bits.payload
invalidate qs_2.io.enq.bits.tail
invalidate qs_2.io.enq.bits.head
invalidate qs_3.io.enq.bits.payload
invalidate qs_3.io.enq.bits.tail
invalidate qs_3.io.enq.bits.head
invalidate qs_4.io.enq.bits.payload
invalidate qs_4.io.enq.bits.tail
invalidate qs_4.io.enq.bits.head
invalidate qs_5.io.enq.bits.payload
invalidate qs_5.io.enq.bits.tail
invalidate qs_5.io.enq.bits.head
invalidate qs_6.io.enq.bits.payload
invalidate qs_6.io.enq.bits.tail
invalidate qs_6.io.enq.bits.head
invalidate qs_7.io.enq.bits.payload
invalidate qs_7.io.enq.bits.tail
invalidate qs_7.io.enq.bits.head
invalidate qs_8.io.enq.bits.payload
invalidate qs_8.io.enq.bits.tail
invalidate qs_8.io.enq.bits.head
invalidate qs_9.io.enq.bits.payload
invalidate qs_9.io.enq.bits.tail
invalidate qs_9.io.enq.bits.head
node vc_sel = dshl(UInt<1>(0h1), io.enq[0].bits.virt_channel_id)
wire flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>}
node _direct_to_q_T = bits(vc_sel, 0, 0)
node _direct_to_q_T_1 = bits(vc_sel, 1, 1)
node _direct_to_q_T_2 = bits(vc_sel, 2, 2)
node _direct_to_q_T_3 = bits(vc_sel, 3, 3)
node _direct_to_q_T_4 = bits(vc_sel, 4, 4)
node _direct_to_q_T_5 = bits(vc_sel, 5, 5)
node _direct_to_q_T_6 = bits(vc_sel, 6, 6)
node _direct_to_q_T_7 = bits(vc_sel, 7, 7)
node _direct_to_q_T_8 = bits(vc_sel, 8, 8)
node _direct_to_q_T_9 = bits(vc_sel, 9, 9)
node _direct_to_q_T_10 = mux(_direct_to_q_T, qs_0.io.enq.ready, UInt<1>(0h0))
node _direct_to_q_T_11 = mux(_direct_to_q_T_1, qs_1.io.enq.ready, UInt<1>(0h0))
node _direct_to_q_T_12 = mux(_direct_to_q_T_2, qs_2.io.enq.ready, UInt<1>(0h0))
node _direct_to_q_T_13 = mux(_direct_to_q_T_3, qs_3.io.enq.ready, UInt<1>(0h0))
node _direct_to_q_T_14 = mux(_direct_to_q_T_4, qs_4.io.enq.ready, UInt<1>(0h0))
node _direct_to_q_T_15 = mux(_direct_to_q_T_5, qs_5.io.enq.ready, UInt<1>(0h0))
node _direct_to_q_T_16 = mux(_direct_to_q_T_6, qs_6.io.enq.ready, UInt<1>(0h0))
node _direct_to_q_T_17 = mux(_direct_to_q_T_7, qs_7.io.enq.ready, UInt<1>(0h0))
node _direct_to_q_T_18 = mux(_direct_to_q_T_8, qs_8.io.enq.ready, UInt<1>(0h0))
node _direct_to_q_T_19 = mux(_direct_to_q_T_9, qs_9.io.enq.ready, UInt<1>(0h0))
node _direct_to_q_T_20 = or(_direct_to_q_T_10, _direct_to_q_T_11)
node _direct_to_q_T_21 = or(_direct_to_q_T_20, _direct_to_q_T_12)
node _direct_to_q_T_22 = or(_direct_to_q_T_21, _direct_to_q_T_13)
node _direct_to_q_T_23 = or(_direct_to_q_T_22, _direct_to_q_T_14)
node _direct_to_q_T_24 = or(_direct_to_q_T_23, _direct_to_q_T_15)
node _direct_to_q_T_25 = or(_direct_to_q_T_24, _direct_to_q_T_16)
node _direct_to_q_T_26 = or(_direct_to_q_T_25, _direct_to_q_T_17)
node _direct_to_q_T_27 = or(_direct_to_q_T_26, _direct_to_q_T_18)
node _direct_to_q_T_28 = or(_direct_to_q_T_27, _direct_to_q_T_19)
wire _direct_to_q_WIRE : UInt<1>
connect _direct_to_q_WIRE, _direct_to_q_T_28
node _direct_to_q_T_29 = bits(vc_sel, 0, 0)
node _direct_to_q_T_30 = bits(vc_sel, 1, 1)
node _direct_to_q_T_31 = bits(vc_sel, 2, 2)
node _direct_to_q_T_32 = bits(vc_sel, 3, 3)
node _direct_to_q_T_33 = bits(vc_sel, 4, 4)
node _direct_to_q_T_34 = bits(vc_sel, 5, 5)
node _direct_to_q_T_35 = bits(vc_sel, 6, 6)
node _direct_to_q_T_36 = bits(vc_sel, 7, 7)
node _direct_to_q_T_37 = bits(vc_sel, 8, 8)
node _direct_to_q_T_38 = bits(vc_sel, 9, 9)
node _direct_to_q_T_39 = mux(_direct_to_q_T_29, empty_0, UInt<1>(0h0))
node _direct_to_q_T_40 = mux(_direct_to_q_T_30, empty_1, UInt<1>(0h0))
node _direct_to_q_T_41 = mux(_direct_to_q_T_31, empty_2, UInt<1>(0h0))
node _direct_to_q_T_42 = mux(_direct_to_q_T_32, empty_3, UInt<1>(0h0))
node _direct_to_q_T_43 = mux(_direct_to_q_T_33, empty_4, UInt<1>(0h0))
node _direct_to_q_T_44 = mux(_direct_to_q_T_34, empty_5, UInt<1>(0h0))
node _direct_to_q_T_45 = mux(_direct_to_q_T_35, empty_6, UInt<1>(0h0))
node _direct_to_q_T_46 = mux(_direct_to_q_T_36, empty_7, UInt<1>(0h0))
node _direct_to_q_T_47 = mux(_direct_to_q_T_37, empty_8, UInt<1>(0h0))
node _direct_to_q_T_48 = mux(_direct_to_q_T_38, empty_9, UInt<1>(0h0))
node _direct_to_q_T_49 = or(_direct_to_q_T_39, _direct_to_q_T_40)
node _direct_to_q_T_50 = or(_direct_to_q_T_49, _direct_to_q_T_41)
node _direct_to_q_T_51 = or(_direct_to_q_T_50, _direct_to_q_T_42)
node _direct_to_q_T_52 = or(_direct_to_q_T_51, _direct_to_q_T_43)
node _direct_to_q_T_53 = or(_direct_to_q_T_52, _direct_to_q_T_44)
node _direct_to_q_T_54 = or(_direct_to_q_T_53, _direct_to_q_T_45)
node _direct_to_q_T_55 = or(_direct_to_q_T_54, _direct_to_q_T_46)
node _direct_to_q_T_56 = or(_direct_to_q_T_55, _direct_to_q_T_47)
node _direct_to_q_T_57 = or(_direct_to_q_T_56, _direct_to_q_T_48)
wire _direct_to_q_WIRE_1 : UInt<1>
connect _direct_to_q_WIRE_1, _direct_to_q_T_57
node _direct_to_q_T_58 = and(_direct_to_q_WIRE, _direct_to_q_WIRE_1)
node direct_to_q = and(_direct_to_q_T_58, UInt<1>(0h1))
connect flit.head, io.enq[0].bits.head
connect flit.tail, io.enq[0].bits.tail
connect flit.payload, io.enq[0].bits.payload
node _T = eq(direct_to_q, UInt<1>(0h0))
node _T_1 = and(io.enq[0].valid, _T)
when _T_1 :
write mport MPORT = mem[tails[io.enq[0].bits.virt_channel_id]], clock
connect MPORT, flit
node _tails_T = bits(vc_sel, 0, 0)
node _tails_T_1 = bits(vc_sel, 1, 1)
node _tails_T_2 = bits(vc_sel, 2, 2)
node _tails_T_3 = bits(vc_sel, 3, 3)
node _tails_T_4 = bits(vc_sel, 4, 4)
node _tails_T_5 = bits(vc_sel, 5, 5)
node _tails_T_6 = bits(vc_sel, 6, 6)
node _tails_T_7 = bits(vc_sel, 7, 7)
node _tails_T_8 = bits(vc_sel, 8, 8)
node _tails_T_9 = bits(vc_sel, 9, 9)
node _tails_T_10 = mux(_tails_T, UInt<1>(0h0), UInt<1>(0h0))
node _tails_T_11 = mux(_tails_T_1, UInt<1>(0h0), UInt<1>(0h0))
node _tails_T_12 = mux(_tails_T_2, UInt<1>(0h0), UInt<1>(0h0))
node _tails_T_13 = mux(_tails_T_3, UInt<1>(0h0), UInt<1>(0h0))
node _tails_T_14 = mux(_tails_T_4, UInt<1>(0h0), UInt<1>(0h0))
node _tails_T_15 = mux(_tails_T_5, UInt<1>(0h0), UInt<1>(0h0))
node _tails_T_16 = mux(_tails_T_6, UInt<1>(0h0), UInt<1>(0h0))
node _tails_T_17 = mux(_tails_T_7, UInt<1>(0h0), UInt<1>(0h0))
node _tails_T_18 = mux(_tails_T_8, UInt<2>(0h3), UInt<1>(0h0))
node _tails_T_19 = mux(_tails_T_9, UInt<1>(0h0), UInt<1>(0h0))
node _tails_T_20 = or(_tails_T_10, _tails_T_11)
node _tails_T_21 = or(_tails_T_20, _tails_T_12)
node _tails_T_22 = or(_tails_T_21, _tails_T_13)
node _tails_T_23 = or(_tails_T_22, _tails_T_14)
node _tails_T_24 = or(_tails_T_23, _tails_T_15)
node _tails_T_25 = or(_tails_T_24, _tails_T_16)
node _tails_T_26 = or(_tails_T_25, _tails_T_17)
node _tails_T_27 = or(_tails_T_26, _tails_T_18)
node _tails_T_28 = or(_tails_T_27, _tails_T_19)
wire _tails_WIRE_1 : UInt<2>
connect _tails_WIRE_1, _tails_T_28
node _tails_T_29 = eq(tails[io.enq[0].bits.virt_channel_id], _tails_WIRE_1)
node _tails_T_30 = bits(vc_sel, 0, 0)
node _tails_T_31 = bits(vc_sel, 1, 1)
node _tails_T_32 = bits(vc_sel, 2, 2)
node _tails_T_33 = bits(vc_sel, 3, 3)
node _tails_T_34 = bits(vc_sel, 4, 4)
node _tails_T_35 = bits(vc_sel, 5, 5)
node _tails_T_36 = bits(vc_sel, 6, 6)
node _tails_T_37 = bits(vc_sel, 7, 7)
node _tails_T_38 = bits(vc_sel, 8, 8)
node _tails_T_39 = bits(vc_sel, 9, 9)
node _tails_T_40 = mux(_tails_T_30, UInt<1>(0h0), UInt<1>(0h0))
node _tails_T_41 = mux(_tails_T_31, UInt<1>(0h0), UInt<1>(0h0))
node _tails_T_42 = mux(_tails_T_32, UInt<1>(0h0), UInt<1>(0h0))
node _tails_T_43 = mux(_tails_T_33, UInt<1>(0h0), UInt<1>(0h0))
node _tails_T_44 = mux(_tails_T_34, UInt<1>(0h0), UInt<1>(0h0))
node _tails_T_45 = mux(_tails_T_35, UInt<1>(0h0), UInt<1>(0h0))
node _tails_T_46 = mux(_tails_T_36, UInt<1>(0h0), UInt<1>(0h0))
node _tails_T_47 = mux(_tails_T_37, UInt<1>(0h0), UInt<1>(0h0))
node _tails_T_48 = mux(_tails_T_38, UInt<1>(0h0), UInt<1>(0h0))
node _tails_T_49 = mux(_tails_T_39, UInt<1>(0h0), UInt<1>(0h0))
node _tails_T_50 = or(_tails_T_40, _tails_T_41)
node _tails_T_51 = or(_tails_T_50, _tails_T_42)
node _tails_T_52 = or(_tails_T_51, _tails_T_43)
node _tails_T_53 = or(_tails_T_52, _tails_T_44)
node _tails_T_54 = or(_tails_T_53, _tails_T_45)
node _tails_T_55 = or(_tails_T_54, _tails_T_46)
node _tails_T_56 = or(_tails_T_55, _tails_T_47)
node _tails_T_57 = or(_tails_T_56, _tails_T_48)
node _tails_T_58 = or(_tails_T_57, _tails_T_49)
wire _tails_WIRE_2 : UInt<1>
connect _tails_WIRE_2, _tails_T_58
node _tails_T_59 = add(tails[io.enq[0].bits.virt_channel_id], UInt<1>(0h1))
node _tails_T_60 = tail(_tails_T_59, 1)
node _tails_T_61 = mux(_tails_T_29, _tails_WIRE_2, _tails_T_60)
connect tails[io.enq[0].bits.virt_channel_id], _tails_T_61
else :
node _T_2 = and(io.enq[0].valid, direct_to_q)
when _T_2 :
node _T_3 = eq(io.enq[0].bits.virt_channel_id, UInt<1>(0h0))
when _T_3 :
connect qs_0.io.enq.valid, UInt<1>(0h1)
connect qs_0.io.enq.bits.payload, flit.payload
connect qs_0.io.enq.bits.tail, flit.tail
connect qs_0.io.enq.bits.head, flit.head
node _T_4 = eq(io.enq[0].bits.virt_channel_id, UInt<1>(0h1))
when _T_4 :
connect qs_1.io.enq.valid, UInt<1>(0h1)
connect qs_1.io.enq.bits.payload, flit.payload
connect qs_1.io.enq.bits.tail, flit.tail
connect qs_1.io.enq.bits.head, flit.head
node _T_5 = eq(io.enq[0].bits.virt_channel_id, UInt<2>(0h2))
when _T_5 :
connect qs_2.io.enq.valid, UInt<1>(0h1)
connect qs_2.io.enq.bits.payload, flit.payload
connect qs_2.io.enq.bits.tail, flit.tail
connect qs_2.io.enq.bits.head, flit.head
node _T_6 = eq(io.enq[0].bits.virt_channel_id, UInt<2>(0h3))
when _T_6 :
connect qs_3.io.enq.valid, UInt<1>(0h1)
connect qs_3.io.enq.bits.payload, flit.payload
connect qs_3.io.enq.bits.tail, flit.tail
connect qs_3.io.enq.bits.head, flit.head
node _T_7 = eq(io.enq[0].bits.virt_channel_id, UInt<3>(0h4))
when _T_7 :
connect qs_4.io.enq.valid, UInt<1>(0h1)
connect qs_4.io.enq.bits.payload, flit.payload
connect qs_4.io.enq.bits.tail, flit.tail
connect qs_4.io.enq.bits.head, flit.head
node _T_8 = eq(io.enq[0].bits.virt_channel_id, UInt<3>(0h5))
when _T_8 :
connect qs_5.io.enq.valid, UInt<1>(0h1)
connect qs_5.io.enq.bits.payload, flit.payload
connect qs_5.io.enq.bits.tail, flit.tail
connect qs_5.io.enq.bits.head, flit.head
node _T_9 = eq(io.enq[0].bits.virt_channel_id, UInt<3>(0h6))
when _T_9 :
connect qs_6.io.enq.valid, UInt<1>(0h1)
connect qs_6.io.enq.bits.payload, flit.payload
connect qs_6.io.enq.bits.tail, flit.tail
connect qs_6.io.enq.bits.head, flit.head
node _T_10 = eq(io.enq[0].bits.virt_channel_id, UInt<3>(0h7))
when _T_10 :
connect qs_7.io.enq.valid, UInt<1>(0h1)
connect qs_7.io.enq.bits.payload, flit.payload
connect qs_7.io.enq.bits.tail, flit.tail
connect qs_7.io.enq.bits.head, flit.head
node _T_11 = eq(io.enq[0].bits.virt_channel_id, UInt<4>(0h8))
when _T_11 :
connect qs_8.io.enq.valid, UInt<1>(0h1)
connect qs_8.io.enq.bits.payload, flit.payload
connect qs_8.io.enq.bits.tail, flit.tail
connect qs_8.io.enq.bits.head, flit.head
node _T_12 = eq(io.enq[0].bits.virt_channel_id, UInt<4>(0h9))
when _T_12 :
connect qs_9.io.enq.valid, UInt<1>(0h1)
connect qs_9.io.enq.bits.payload, flit.payload
connect qs_9.io.enq.bits.tail, flit.tail
connect qs_9.io.enq.bits.head, flit.head
node _can_to_q_T = eq(empty_0, UInt<1>(0h0))
node can_to_q_0 = and(_can_to_q_T, qs_0.io.enq.ready)
node _can_to_q_T_1 = eq(empty_1, UInt<1>(0h0))
node can_to_q_1 = and(_can_to_q_T_1, qs_1.io.enq.ready)
node _can_to_q_T_2 = eq(empty_2, UInt<1>(0h0))
node can_to_q_2 = and(_can_to_q_T_2, qs_2.io.enq.ready)
node _can_to_q_T_3 = eq(empty_3, UInt<1>(0h0))
node can_to_q_3 = and(_can_to_q_T_3, qs_3.io.enq.ready)
node _can_to_q_T_4 = eq(empty_4, UInt<1>(0h0))
node can_to_q_4 = and(_can_to_q_T_4, qs_4.io.enq.ready)
node _can_to_q_T_5 = eq(empty_5, UInt<1>(0h0))
node can_to_q_5 = and(_can_to_q_T_5, qs_5.io.enq.ready)
node _can_to_q_T_6 = eq(empty_6, UInt<1>(0h0))
node can_to_q_6 = and(_can_to_q_T_6, qs_6.io.enq.ready)
node _can_to_q_T_7 = eq(empty_7, UInt<1>(0h0))
node can_to_q_7 = and(_can_to_q_T_7, qs_7.io.enq.ready)
node _can_to_q_T_8 = eq(empty_8, UInt<1>(0h0))
node can_to_q_8 = and(_can_to_q_T_8, qs_8.io.enq.ready)
node _can_to_q_T_9 = eq(empty_9, UInt<1>(0h0))
node can_to_q_9 = and(_can_to_q_T_9, qs_9.io.enq.ready)
node _to_q_oh_enc_T = mux(can_to_q_9, UInt<10>(0h200), UInt<10>(0h0))
node _to_q_oh_enc_T_1 = mux(can_to_q_8, UInt<10>(0h100), _to_q_oh_enc_T)
node _to_q_oh_enc_T_2 = mux(can_to_q_7, UInt<10>(0h80), _to_q_oh_enc_T_1)
node _to_q_oh_enc_T_3 = mux(can_to_q_6, UInt<10>(0h40), _to_q_oh_enc_T_2)
node _to_q_oh_enc_T_4 = mux(can_to_q_5, UInt<10>(0h20), _to_q_oh_enc_T_3)
node _to_q_oh_enc_T_5 = mux(can_to_q_4, UInt<10>(0h10), _to_q_oh_enc_T_4)
node _to_q_oh_enc_T_6 = mux(can_to_q_3, UInt<10>(0h8), _to_q_oh_enc_T_5)
node _to_q_oh_enc_T_7 = mux(can_to_q_2, UInt<10>(0h4), _to_q_oh_enc_T_6)
node _to_q_oh_enc_T_8 = mux(can_to_q_1, UInt<10>(0h2), _to_q_oh_enc_T_7)
node to_q_oh_enc = mux(can_to_q_0, UInt<10>(0h1), _to_q_oh_enc_T_8)
node to_q_oh_0 = bits(to_q_oh_enc, 0, 0)
node to_q_oh_1 = bits(to_q_oh_enc, 1, 1)
node to_q_oh_2 = bits(to_q_oh_enc, 2, 2)
node to_q_oh_3 = bits(to_q_oh_enc, 3, 3)
node to_q_oh_4 = bits(to_q_oh_enc, 4, 4)
node to_q_oh_5 = bits(to_q_oh_enc, 5, 5)
node to_q_oh_6 = bits(to_q_oh_enc, 6, 6)
node to_q_oh_7 = bits(to_q_oh_enc, 7, 7)
node to_q_oh_8 = bits(to_q_oh_enc, 8, 8)
node to_q_oh_9 = bits(to_q_oh_enc, 9, 9)
node to_q_lo_lo = cat(to_q_oh_1, to_q_oh_0)
node to_q_lo_hi_hi = cat(to_q_oh_4, to_q_oh_3)
node to_q_lo_hi = cat(to_q_lo_hi_hi, to_q_oh_2)
node to_q_lo = cat(to_q_lo_hi, to_q_lo_lo)
node to_q_hi_lo = cat(to_q_oh_6, to_q_oh_5)
node to_q_hi_hi_hi = cat(to_q_oh_9, to_q_oh_8)
node to_q_hi_hi = cat(to_q_hi_hi_hi, to_q_oh_7)
node to_q_hi = cat(to_q_hi_hi, to_q_hi_lo)
node _to_q_T = cat(to_q_hi, to_q_lo)
node to_q_hi_1 = bits(_to_q_T, 9, 8)
node to_q_lo_1 = bits(_to_q_T, 7, 0)
node _to_q_T_1 = orr(to_q_hi_1)
node _to_q_T_2 = or(to_q_hi_1, to_q_lo_1)
node to_q_hi_2 = bits(_to_q_T_2, 7, 4)
node to_q_lo_2 = bits(_to_q_T_2, 3, 0)
node _to_q_T_3 = orr(to_q_hi_2)
node _to_q_T_4 = or(to_q_hi_2, to_q_lo_2)
node to_q_hi_3 = bits(_to_q_T_4, 3, 2)
node to_q_lo_3 = bits(_to_q_T_4, 1, 0)
node _to_q_T_5 = orr(to_q_hi_3)
node _to_q_T_6 = or(to_q_hi_3, to_q_lo_3)
node _to_q_T_7 = bits(_to_q_T_6, 1, 1)
node _to_q_T_8 = cat(_to_q_T_5, _to_q_T_7)
node _to_q_T_9 = cat(_to_q_T_3, _to_q_T_8)
node to_q = cat(_to_q_T_1, _to_q_T_9)
node _T_13 = or(can_to_q_0, can_to_q_1)
node _T_14 = or(_T_13, can_to_q_2)
node _T_15 = or(_T_14, can_to_q_3)
node _T_16 = or(_T_15, can_to_q_4)
node _T_17 = or(_T_16, can_to_q_5)
node _T_18 = or(_T_17, can_to_q_6)
node _T_19 = or(_T_18, can_to_q_7)
node _T_20 = or(_T_19, can_to_q_8)
node _T_21 = or(_T_20, can_to_q_9)
when _T_21 :
node _head_T = mux(to_q_oh_0, heads[0], UInt<1>(0h0))
node _head_T_1 = mux(to_q_oh_1, heads[1], UInt<1>(0h0))
node _head_T_2 = mux(to_q_oh_2, heads[2], UInt<1>(0h0))
node _head_T_3 = mux(to_q_oh_3, heads[3], UInt<1>(0h0))
node _head_T_4 = mux(to_q_oh_4, heads[4], UInt<1>(0h0))
node _head_T_5 = mux(to_q_oh_5, heads[5], UInt<1>(0h0))
node _head_T_6 = mux(to_q_oh_6, heads[6], UInt<1>(0h0))
node _head_T_7 = mux(to_q_oh_7, heads[7], UInt<1>(0h0))
node _head_T_8 = mux(to_q_oh_8, heads[8], UInt<1>(0h0))
node _head_T_9 = mux(to_q_oh_9, heads[9], UInt<1>(0h0))
node _head_T_10 = or(_head_T, _head_T_1)
node _head_T_11 = or(_head_T_10, _head_T_2)
node _head_T_12 = or(_head_T_11, _head_T_3)
node _head_T_13 = or(_head_T_12, _head_T_4)
node _head_T_14 = or(_head_T_13, _head_T_5)
node _head_T_15 = or(_head_T_14, _head_T_6)
node _head_T_16 = or(_head_T_15, _head_T_7)
node _head_T_17 = or(_head_T_16, _head_T_8)
node _head_T_18 = or(_head_T_17, _head_T_9)
wire head : UInt<2>
connect head, _head_T_18
node _heads_T = mux(to_q_oh_0, UInt<1>(0h0), UInt<1>(0h0))
node _heads_T_1 = mux(to_q_oh_1, UInt<1>(0h0), UInt<1>(0h0))
node _heads_T_2 = mux(to_q_oh_2, UInt<1>(0h0), UInt<1>(0h0))
node _heads_T_3 = mux(to_q_oh_3, UInt<1>(0h0), UInt<1>(0h0))
node _heads_T_4 = mux(to_q_oh_4, UInt<1>(0h0), UInt<1>(0h0))
node _heads_T_5 = mux(to_q_oh_5, UInt<1>(0h0), UInt<1>(0h0))
node _heads_T_6 = mux(to_q_oh_6, UInt<1>(0h0), UInt<1>(0h0))
node _heads_T_7 = mux(to_q_oh_7, UInt<1>(0h0), UInt<1>(0h0))
node _heads_T_8 = mux(to_q_oh_8, UInt<2>(0h3), UInt<1>(0h0))
node _heads_T_9 = mux(to_q_oh_9, UInt<1>(0h0), UInt<1>(0h0))
node _heads_T_10 = or(_heads_T, _heads_T_1)
node _heads_T_11 = or(_heads_T_10, _heads_T_2)
node _heads_T_12 = or(_heads_T_11, _heads_T_3)
node _heads_T_13 = or(_heads_T_12, _heads_T_4)
node _heads_T_14 = or(_heads_T_13, _heads_T_5)
node _heads_T_15 = or(_heads_T_14, _heads_T_6)
node _heads_T_16 = or(_heads_T_15, _heads_T_7)
node _heads_T_17 = or(_heads_T_16, _heads_T_8)
node _heads_T_18 = or(_heads_T_17, _heads_T_9)
wire _heads_WIRE_1 : UInt<2>
connect _heads_WIRE_1, _heads_T_18
node _heads_T_19 = eq(head, _heads_WIRE_1)
node _heads_T_20 = mux(to_q_oh_0, UInt<1>(0h0), UInt<1>(0h0))
node _heads_T_21 = mux(to_q_oh_1, UInt<1>(0h0), UInt<1>(0h0))
node _heads_T_22 = mux(to_q_oh_2, UInt<1>(0h0), UInt<1>(0h0))
node _heads_T_23 = mux(to_q_oh_3, UInt<1>(0h0), UInt<1>(0h0))
node _heads_T_24 = mux(to_q_oh_4, UInt<1>(0h0), UInt<1>(0h0))
node _heads_T_25 = mux(to_q_oh_5, UInt<1>(0h0), UInt<1>(0h0))
node _heads_T_26 = mux(to_q_oh_6, UInt<1>(0h0), UInt<1>(0h0))
node _heads_T_27 = mux(to_q_oh_7, UInt<1>(0h0), UInt<1>(0h0))
node _heads_T_28 = mux(to_q_oh_8, UInt<1>(0h0), UInt<1>(0h0))
node _heads_T_29 = mux(to_q_oh_9, UInt<1>(0h0), UInt<1>(0h0))
node _heads_T_30 = or(_heads_T_20, _heads_T_21)
node _heads_T_31 = or(_heads_T_30, _heads_T_22)
node _heads_T_32 = or(_heads_T_31, _heads_T_23)
node _heads_T_33 = or(_heads_T_32, _heads_T_24)
node _heads_T_34 = or(_heads_T_33, _heads_T_25)
node _heads_T_35 = or(_heads_T_34, _heads_T_26)
node _heads_T_36 = or(_heads_T_35, _heads_T_27)
node _heads_T_37 = or(_heads_T_36, _heads_T_28)
node _heads_T_38 = or(_heads_T_37, _heads_T_29)
wire _heads_WIRE_2 : UInt<1>
connect _heads_WIRE_2, _heads_T_38
node _heads_T_39 = add(head, UInt<1>(0h1))
node _heads_T_40 = tail(_heads_T_39, 1)
node _heads_T_41 = mux(_heads_T_19, _heads_WIRE_2, _heads_T_40)
connect heads[to_q], _heads_T_41
when to_q_oh_0 :
connect qs_0.io.enq.valid, UInt<1>(0h1)
read mport qs_0_io_enq_bits_MPORT = mem[head], clock
connect qs_0.io.enq.bits.payload, qs_0_io_enq_bits_MPORT.payload
connect qs_0.io.enq.bits.tail, qs_0_io_enq_bits_MPORT.tail
connect qs_0.io.enq.bits.head, qs_0_io_enq_bits_MPORT.head
when to_q_oh_1 :
connect qs_1.io.enq.valid, UInt<1>(0h1)
read mport qs_1_io_enq_bits_MPORT = mem[head], clock
connect qs_1.io.enq.bits.payload, qs_1_io_enq_bits_MPORT.payload
connect qs_1.io.enq.bits.tail, qs_1_io_enq_bits_MPORT.tail
connect qs_1.io.enq.bits.head, qs_1_io_enq_bits_MPORT.head
when to_q_oh_2 :
connect qs_2.io.enq.valid, UInt<1>(0h1)
read mport qs_2_io_enq_bits_MPORT = mem[head], clock
connect qs_2.io.enq.bits.payload, qs_2_io_enq_bits_MPORT.payload
connect qs_2.io.enq.bits.tail, qs_2_io_enq_bits_MPORT.tail
connect qs_2.io.enq.bits.head, qs_2_io_enq_bits_MPORT.head
when to_q_oh_3 :
connect qs_3.io.enq.valid, UInt<1>(0h1)
read mport qs_3_io_enq_bits_MPORT = mem[head], clock
connect qs_3.io.enq.bits.payload, qs_3_io_enq_bits_MPORT.payload
connect qs_3.io.enq.bits.tail, qs_3_io_enq_bits_MPORT.tail
connect qs_3.io.enq.bits.head, qs_3_io_enq_bits_MPORT.head
when to_q_oh_4 :
connect qs_4.io.enq.valid, UInt<1>(0h1)
read mport qs_4_io_enq_bits_MPORT = mem[head], clock
connect qs_4.io.enq.bits.payload, qs_4_io_enq_bits_MPORT.payload
connect qs_4.io.enq.bits.tail, qs_4_io_enq_bits_MPORT.tail
connect qs_4.io.enq.bits.head, qs_4_io_enq_bits_MPORT.head
when to_q_oh_5 :
connect qs_5.io.enq.valid, UInt<1>(0h1)
read mport qs_5_io_enq_bits_MPORT = mem[head], clock
connect qs_5.io.enq.bits.payload, qs_5_io_enq_bits_MPORT.payload
connect qs_5.io.enq.bits.tail, qs_5_io_enq_bits_MPORT.tail
connect qs_5.io.enq.bits.head, qs_5_io_enq_bits_MPORT.head
when to_q_oh_6 :
connect qs_6.io.enq.valid, UInt<1>(0h1)
read mport qs_6_io_enq_bits_MPORT = mem[head], clock
connect qs_6.io.enq.bits.payload, qs_6_io_enq_bits_MPORT.payload
connect qs_6.io.enq.bits.tail, qs_6_io_enq_bits_MPORT.tail
connect qs_6.io.enq.bits.head, qs_6_io_enq_bits_MPORT.head
when to_q_oh_7 :
connect qs_7.io.enq.valid, UInt<1>(0h1)
read mport qs_7_io_enq_bits_MPORT = mem[head], clock
connect qs_7.io.enq.bits.payload, qs_7_io_enq_bits_MPORT.payload
connect qs_7.io.enq.bits.tail, qs_7_io_enq_bits_MPORT.tail
connect qs_7.io.enq.bits.head, qs_7_io_enq_bits_MPORT.head
when to_q_oh_8 :
connect qs_8.io.enq.valid, UInt<1>(0h1)
read mport qs_8_io_enq_bits_MPORT = mem[head], clock
connect qs_8.io.enq.bits.payload, qs_8_io_enq_bits_MPORT.payload
connect qs_8.io.enq.bits.tail, qs_8_io_enq_bits_MPORT.tail
connect qs_8.io.enq.bits.head, qs_8_io_enq_bits_MPORT.head
when to_q_oh_9 :
connect qs_9.io.enq.valid, UInt<1>(0h1)
read mport qs_9_io_enq_bits_MPORT = mem[head], clock
connect qs_9.io.enq.bits.payload, qs_9_io_enq_bits_MPORT.payload
connect qs_9.io.enq.bits.tail, qs_9_io_enq_bits_MPORT.tail
connect qs_9.io.enq.bits.head, qs_9_io_enq_bits_MPORT.head
connect io.deq[0].bits, qs_0.io.deq.bits
connect io.deq[0].valid, qs_0.io.deq.valid
connect qs_0.io.deq.ready, io.deq[0].ready
connect io.deq[1].bits, qs_1.io.deq.bits
connect io.deq[1].valid, qs_1.io.deq.valid
connect qs_1.io.deq.ready, io.deq[1].ready
connect io.deq[2].bits, qs_2.io.deq.bits
connect io.deq[2].valid, qs_2.io.deq.valid
connect qs_2.io.deq.ready, io.deq[2].ready
connect io.deq[3].bits, qs_3.io.deq.bits
connect io.deq[3].valid, qs_3.io.deq.valid
connect qs_3.io.deq.ready, io.deq[3].ready
connect io.deq[4].bits, qs_4.io.deq.bits
connect io.deq[4].valid, qs_4.io.deq.valid
connect qs_4.io.deq.ready, io.deq[4].ready
connect io.deq[5].bits, qs_5.io.deq.bits
connect io.deq[5].valid, qs_5.io.deq.valid
connect qs_5.io.deq.ready, io.deq[5].ready
connect io.deq[6].bits, qs_6.io.deq.bits
connect io.deq[6].valid, qs_6.io.deq.valid
connect qs_6.io.deq.ready, io.deq[6].ready
connect io.deq[7].bits, qs_7.io.deq.bits
connect io.deq[7].valid, qs_7.io.deq.valid
connect qs_7.io.deq.ready, io.deq[7].ready
connect io.deq[8].bits, qs_8.io.deq.bits
connect io.deq[8].valid, qs_8.io.deq.valid
connect qs_8.io.deq.ready, io.deq[8].ready
connect io.deq[9].bits, qs_9.io.deq.bits
connect io.deq[9].valid, qs_9.io.deq.valid
connect qs_9.io.deq.ready, io.deq[9].ready | module InputBuffer_116( // @[InputUnit.scala:49:7]
input clock, // @[InputUnit.scala:49:7]
input reset, // @[InputUnit.scala:49:7]
input io_enq_0_valid, // @[InputUnit.scala:51:14]
input io_enq_0_bits_head, // @[InputUnit.scala:51:14]
input io_enq_0_bits_tail, // @[InputUnit.scala:51:14]
input [72:0] io_enq_0_bits_payload, // @[InputUnit.scala:51:14]
input [3:0] io_enq_0_bits_virt_channel_id, // @[InputUnit.scala:51:14]
output io_deq_0_bits_head, // @[InputUnit.scala:51:14]
output io_deq_0_bits_tail, // @[InputUnit.scala:51:14]
output [72:0] io_deq_0_bits_payload, // @[InputUnit.scala:51:14]
output io_deq_1_bits_head, // @[InputUnit.scala:51:14]
output io_deq_1_bits_tail, // @[InputUnit.scala:51:14]
output [72:0] io_deq_1_bits_payload, // @[InputUnit.scala:51:14]
output io_deq_2_bits_head, // @[InputUnit.scala:51:14]
output io_deq_2_bits_tail, // @[InputUnit.scala:51:14]
output [72:0] io_deq_2_bits_payload, // @[InputUnit.scala:51:14]
output io_deq_3_bits_head, // @[InputUnit.scala:51:14]
output io_deq_3_bits_tail, // @[InputUnit.scala:51:14]
output [72:0] io_deq_3_bits_payload, // @[InputUnit.scala:51:14]
output io_deq_4_bits_head, // @[InputUnit.scala:51:14]
output io_deq_4_bits_tail, // @[InputUnit.scala:51:14]
output [72:0] io_deq_4_bits_payload, // @[InputUnit.scala:51:14]
output io_deq_5_bits_head, // @[InputUnit.scala:51:14]
output io_deq_5_bits_tail, // @[InputUnit.scala:51:14]
output [72:0] io_deq_5_bits_payload, // @[InputUnit.scala:51:14]
output io_deq_6_bits_head, // @[InputUnit.scala:51:14]
output io_deq_6_bits_tail, // @[InputUnit.scala:51:14]
output [72:0] io_deq_6_bits_payload, // @[InputUnit.scala:51:14]
output io_deq_7_bits_head, // @[InputUnit.scala:51:14]
output io_deq_7_bits_tail, // @[InputUnit.scala:51:14]
output [72:0] io_deq_7_bits_payload, // @[InputUnit.scala:51:14]
input io_deq_8_ready, // @[InputUnit.scala:51:14]
output io_deq_8_valid, // @[InputUnit.scala:51:14]
output io_deq_8_bits_head, // @[InputUnit.scala:51:14]
output io_deq_8_bits_tail, // @[InputUnit.scala:51:14]
output [72:0] io_deq_8_bits_payload, // @[InputUnit.scala:51:14]
output io_deq_9_bits_head, // @[InputUnit.scala:51:14]
output io_deq_9_bits_tail, // @[InputUnit.scala:51:14]
output [72:0] io_deq_9_bits_payload // @[InputUnit.scala:51:14]
);
wire _qs_9_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_8_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_7_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_6_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_5_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_4_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_3_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_2_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_1_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_0_io_enq_ready; // @[InputUnit.scala:90:49]
wire [74:0] _mem_ext_R0_data; // @[InputUnit.scala:85:18]
wire [74:0] _mem_ext_R1_data; // @[InputUnit.scala:85:18]
wire [74:0] _mem_ext_R2_data; // @[InputUnit.scala:85:18]
wire [74:0] _mem_ext_R3_data; // @[InputUnit.scala:85:18]
wire [74:0] _mem_ext_R4_data; // @[InputUnit.scala:85:18]
wire [74:0] _mem_ext_R5_data; // @[InputUnit.scala:85:18]
wire [74:0] _mem_ext_R6_data; // @[InputUnit.scala:85:18]
wire [74:0] _mem_ext_R7_data; // @[InputUnit.scala:85:18]
wire [74:0] _mem_ext_R8_data; // @[InputUnit.scala:85:18]
wire [74:0] _mem_ext_R9_data; // @[InputUnit.scala:85:18]
reg [1:0] heads_0; // @[InputUnit.scala:86:24]
reg [1:0] heads_1; // @[InputUnit.scala:86:24]
reg [1:0] heads_2; // @[InputUnit.scala:86:24]
reg [1:0] heads_3; // @[InputUnit.scala:86:24]
reg [1:0] heads_4; // @[InputUnit.scala:86:24]
reg [1:0] heads_5; // @[InputUnit.scala:86:24]
reg [1:0] heads_6; // @[InputUnit.scala:86:24]
reg [1:0] heads_7; // @[InputUnit.scala:86:24]
reg [1:0] heads_8; // @[InputUnit.scala:86:24]
reg [1:0] heads_9; // @[InputUnit.scala:86:24]
reg [1:0] tails_0; // @[InputUnit.scala:87:24]
reg [1:0] tails_1; // @[InputUnit.scala:87:24]
reg [1:0] tails_2; // @[InputUnit.scala:87:24]
reg [1:0] tails_3; // @[InputUnit.scala:87:24]
reg [1:0] tails_4; // @[InputUnit.scala:87:24]
reg [1:0] tails_5; // @[InputUnit.scala:87:24]
reg [1:0] tails_6; // @[InputUnit.scala:87:24]
reg [1:0] tails_7; // @[InputUnit.scala:87:24]
reg [1:0] tails_8; // @[InputUnit.scala:87:24]
reg [1:0] tails_9; // @[InputUnit.scala:87:24]
wire _tails_T_30 = io_enq_0_bits_virt_channel_id == 4'h0; // @[Mux.scala:32:36]
wire _tails_T_31 = io_enq_0_bits_virt_channel_id == 4'h1; // @[Mux.scala:32:36]
wire _tails_T_32 = io_enq_0_bits_virt_channel_id == 4'h2; // @[Mux.scala:32:36]
wire _tails_T_33 = io_enq_0_bits_virt_channel_id == 4'h3; // @[Mux.scala:32:36]
wire _tails_T_34 = io_enq_0_bits_virt_channel_id == 4'h4; // @[Mux.scala:32:36]
wire _tails_T_35 = io_enq_0_bits_virt_channel_id == 4'h5; // @[Mux.scala:32:36]
wire _tails_T_36 = io_enq_0_bits_virt_channel_id == 4'h6; // @[Mux.scala:32:36]
wire _tails_T_37 = io_enq_0_bits_virt_channel_id == 4'h7; // @[Mux.scala:32:36]
wire _tails_T_38 = io_enq_0_bits_virt_channel_id == 4'h8; // @[Mux.scala:32:36]
wire _tails_T_39 = io_enq_0_bits_virt_channel_id == 4'h9; // @[Mux.scala:32:36]
wire direct_to_q = (_tails_T_30 & _qs_0_io_enq_ready | _tails_T_31 & _qs_1_io_enq_ready | _tails_T_32 & _qs_2_io_enq_ready | _tails_T_33 & _qs_3_io_enq_ready | _tails_T_34 & _qs_4_io_enq_ready | _tails_T_35 & _qs_5_io_enq_ready | _tails_T_36 & _qs_6_io_enq_ready | _tails_T_37 & _qs_7_io_enq_ready | _tails_T_38 & _qs_8_io_enq_ready | _tails_T_39 & _qs_9_io_enq_ready) & (_tails_T_30 & heads_0 == tails_0 | _tails_T_31 & heads_1 == tails_1 | _tails_T_32 & heads_2 == tails_2 | _tails_T_33 & heads_3 == tails_3 | _tails_T_34 & heads_4 == tails_4 | _tails_T_35 & heads_5 == tails_5 | _tails_T_36 & heads_6 == tails_6 | _tails_T_37 & heads_7 == tails_7 | _tails_T_38 & heads_8 == tails_8 | _tails_T_39 & heads_9 == tails_9); // @[Mux.scala:30:73, :32:36]
wire mem_MPORT_en = io_enq_0_valid & ~direct_to_q; // @[InputUnit.scala:96:62, :100:{27,30}]
wire [15:0][1:0] _GEN = {{tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_9}, {tails_8}, {tails_7}, {tails_6}, {tails_5}, {tails_4}, {tails_3}, {tails_2}, {tails_1}, {tails_0}}; // @[InputUnit.scala:87:24, :102:16]
wire _GEN_0 = io_enq_0_bits_virt_channel_id == 4'h0; // @[InputUnit.scala:103:45]
wire _GEN_1 = io_enq_0_bits_virt_channel_id == 4'h1; // @[InputUnit.scala:103:45]
wire _GEN_2 = io_enq_0_bits_virt_channel_id == 4'h2; // @[InputUnit.scala:103:45]
wire _GEN_3 = io_enq_0_bits_virt_channel_id == 4'h3; // @[InputUnit.scala:103:45]
wire _GEN_4 = io_enq_0_bits_virt_channel_id == 4'h4; // @[InputUnit.scala:103:45]
wire _GEN_5 = io_enq_0_bits_virt_channel_id == 4'h5; // @[InputUnit.scala:103:45]
wire _GEN_6 = io_enq_0_bits_virt_channel_id == 4'h6; // @[InputUnit.scala:103:45]
wire _GEN_7 = io_enq_0_bits_virt_channel_id == 4'h7; // @[InputUnit.scala:103:45]
wire _GEN_8 = io_enq_0_bits_virt_channel_id == 4'h8; // @[InputUnit.scala:103:45]
wire _GEN_9 = io_enq_0_bits_virt_channel_id == 4'h9; // @[InputUnit.scala:103:45]
wire _GEN_10 = io_enq_0_valid & direct_to_q; // @[InputUnit.scala:96:62, :107:34]
wire can_to_q_0 = heads_0 != tails_0 & _qs_0_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_1 = heads_1 != tails_1 & _qs_1_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_2 = heads_2 != tails_2 & _qs_2_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_3 = heads_3 != tails_3 & _qs_3_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_4 = heads_4 != tails_4 & _qs_4_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_5 = heads_5 != tails_5 & _qs_5_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_6 = heads_6 != tails_6 & _qs_6_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_7 = heads_7 != tails_7 & _qs_7_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_8 = heads_8 != tails_8 & _qs_8_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_9 = heads_9 != tails_9 & _qs_9_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire [9:0] to_q_oh_enc = can_to_q_0 ? 10'h1 : can_to_q_1 ? 10'h2 : can_to_q_2 ? 10'h4 : can_to_q_3 ? 10'h8 : can_to_q_4 ? 10'h10 : can_to_q_5 ? 10'h20 : can_to_q_6 ? 10'h40 : can_to_q_7 ? 10'h80 : can_to_q_8 ? 10'h100 : {can_to_q_9, 9'h0}; // @[Mux.scala:50:70]
wire _GEN_11 = can_to_q_0 | can_to_q_1 | can_to_q_2 | can_to_q_3 | can_to_q_4 | can_to_q_5 | can_to_q_6 | can_to_q_7 | can_to_q_8 | can_to_q_9; // @[package.scala:81:59]
wire [1:0] head = (to_q_oh_enc[0] ? heads_0 : 2'h0) | (to_q_oh_enc[1] ? heads_1 : 2'h0) | (to_q_oh_enc[2] ? heads_2 : 2'h0) | (to_q_oh_enc[3] ? heads_3 : 2'h0) | (to_q_oh_enc[4] ? heads_4 : 2'h0) | (to_q_oh_enc[5] ? heads_5 : 2'h0) | (to_q_oh_enc[6] ? heads_6 : 2'h0) | (to_q_oh_enc[7] ? heads_7 : 2'h0) | (to_q_oh_enc[8] ? heads_8 : 2'h0) | (to_q_oh_enc[9] ? heads_9 : 2'h0); // @[OneHot.scala:83:30]
wire _GEN_12 = _GEN_11 & to_q_oh_enc[0]; // @[OneHot.scala:83:30]
wire _GEN_13 = _GEN_11 & to_q_oh_enc[1]; // @[OneHot.scala:83:30]
wire _GEN_14 = _GEN_11 & to_q_oh_enc[2]; // @[OneHot.scala:83:30]
wire _GEN_15 = _GEN_11 & to_q_oh_enc[3]; // @[OneHot.scala:83:30]
wire _GEN_16 = _GEN_11 & to_q_oh_enc[4]; // @[OneHot.scala:83:30]
wire _GEN_17 = _GEN_11 & to_q_oh_enc[5]; // @[OneHot.scala:83:30]
wire _GEN_18 = _GEN_11 & to_q_oh_enc[6]; // @[OneHot.scala:83:30]
wire _GEN_19 = _GEN_11 & to_q_oh_enc[7]; // @[OneHot.scala:83:30]
wire _GEN_20 = _GEN_11 & to_q_oh_enc[8]; // @[OneHot.scala:83:30]
wire _GEN_21 = _GEN_11 & to_q_oh_enc[9]; // @[OneHot.scala:83:30]
wire [1:0] _tails_T_61 = _GEN[io_enq_0_bits_virt_channel_id] == {2{_tails_T_38}} ? 2'h0 : _GEN[io_enq_0_bits_virt_channel_id] + 2'h1; // @[Mux.scala:30:73, :32:36]
wire [6:0] _to_q_T_2 = {6'h0, to_q_oh_enc[9]} | to_q_oh_enc[7:1]; // @[OneHot.scala:31:18, :32:28]
wire [2:0] _to_q_T_4 = _to_q_T_2[6:4] | _to_q_T_2[2:0]; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _to_q_T_6 = _to_q_T_4[2] | _to_q_T_4[0]; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] to_q = {|(to_q_oh_enc[9:8]), |(_to_q_T_2[6:3]), |(_to_q_T_4[2:1]), _to_q_T_6}; // @[OneHot.scala:30:18, :32:{10,14,28}]
wire [1:0] _heads_T_41 = head == {2{to_q_oh_enc[8]}} ? 2'h0 : head + 2'h1; // @[OneHot.scala:83:30]
always @(posedge clock) begin // @[InputUnit.scala:49:7]
if (reset) begin // @[InputUnit.scala:49:7]
heads_0 <= 2'h0; // @[InputUnit.scala:49:7, :86:24]
heads_1 <= 2'h0; // @[InputUnit.scala:49:7, :86:24]
heads_2 <= 2'h0; // @[InputUnit.scala:49:7, :86:24]
heads_3 <= 2'h0; // @[InputUnit.scala:49:7, :86:24]
heads_4 <= 2'h0; // @[InputUnit.scala:49:7, :86:24]
heads_5 <= 2'h0; // @[InputUnit.scala:49:7, :86:24]
heads_6 <= 2'h0; // @[InputUnit.scala:49:7, :86:24]
heads_7 <= 2'h0; // @[InputUnit.scala:49:7, :86:24]
heads_8 <= 2'h0; // @[InputUnit.scala:49:7, :86:24]
heads_9 <= 2'h0; // @[InputUnit.scala:49:7, :86:24]
tails_0 <= 2'h0; // @[InputUnit.scala:49:7, :87:24]
tails_1 <= 2'h0; // @[InputUnit.scala:49:7, :87:24]
tails_2 <= 2'h0; // @[InputUnit.scala:49:7, :87:24]
tails_3 <= 2'h0; // @[InputUnit.scala:49:7, :87:24]
tails_4 <= 2'h0; // @[InputUnit.scala:49:7, :87:24]
tails_5 <= 2'h0; // @[InputUnit.scala:49:7, :87:24]
tails_6 <= 2'h0; // @[InputUnit.scala:49:7, :87:24]
tails_7 <= 2'h0; // @[InputUnit.scala:49:7, :87:24]
tails_8 <= 2'h0; // @[InputUnit.scala:49:7, :87:24]
tails_9 <= 2'h0; // @[InputUnit.scala:49:7, :87:24]
end
else begin // @[InputUnit.scala:49:7]
if (_GEN_11 & {to_q_oh_enc[9:8], |(_to_q_T_2[6:3]), |(_to_q_T_4[2:1]), _to_q_T_6} == 5'h0) // @[OneHot.scala:30:18, :32:{10,14,28}]
heads_0 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_11 & to_q == 4'h1) // @[OneHot.scala:32:10]
heads_1 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_11 & to_q == 4'h2) // @[OneHot.scala:32:10]
heads_2 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_11 & to_q == 4'h3) // @[OneHot.scala:32:10]
heads_3 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_11 & to_q == 4'h4) // @[OneHot.scala:32:10]
heads_4 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_11 & to_q == 4'h5) // @[OneHot.scala:32:10]
heads_5 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_11 & to_q == 4'h6) // @[OneHot.scala:32:10]
heads_6 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_11 & to_q == 4'h7) // @[OneHot.scala:32:10]
heads_7 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_11 & to_q == 4'h8) // @[OneHot.scala:32:10]
heads_8 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_11 & to_q == 4'h9) // @[OneHot.scala:32:10]
heads_9 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27]
if (mem_MPORT_en & _GEN_0) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_0 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & _GEN_1) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_1 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & _GEN_2) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_2 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & _GEN_3) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_3 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & _GEN_4) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_4 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & _GEN_5) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_5 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & _GEN_6) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_6 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & _GEN_7) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_7 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & _GEN_8) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_8 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & _GEN_9) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_9 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51]
end
always @(posedge) |
Generate the Verilog code corresponding to this FIRRTL code module TLAtomicAutomata_cbus :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_21
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
wire initval : { state : UInt<2>}
connect initval.state, UInt<1>(0h0)
wire _cam_s_WIRE : { state : UInt<2>}[1]
connect _cam_s_WIRE[0], initval
regreset cam_s : { state : UInt<2>}[1], clock, reset, _cam_s_WIRE
reg cam_a : { bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, fifoId : UInt<1>, lut : UInt<4>}[1], clock
reg cam_d : { data : UInt<64>, denied : UInt<1>, corrupt : UInt<1>}[1], clock
node cam_free_0 = eq(cam_s[0].state, UInt<1>(0h0))
node cam_amo_0 = eq(cam_s[0].state, UInt<2>(0h2))
node _cam_abusy_T = eq(cam_s[0].state, UInt<2>(0h3))
node _cam_abusy_T_1 = eq(cam_s[0].state, UInt<2>(0h2))
node cam_abusy_0 = or(_cam_abusy_T, _cam_abusy_T_1)
node cam_dmatch_0 = neq(cam_s[0].state, UInt<1>(0h0))
node _a_canLogical_T = leq(UInt<1>(0h0), nodeIn.a.bits.size)
node _a_canLogical_T_1 = leq(nodeIn.a.bits.size, UInt<2>(0h3))
node _a_canLogical_T_2 = and(_a_canLogical_T, _a_canLogical_T_1)
node _a_canLogical_T_3 = or(UInt<1>(0h0), _a_canLogical_T_2)
node _a_canLogical_T_4 = xor(nodeIn.a.bits.address, UInt<13>(0h1000))
node _a_canLogical_T_5 = cvt(_a_canLogical_T_4)
node _a_canLogical_T_6 = and(_a_canLogical_T_5, asSInt(UInt<30>(0h1a011000)))
node _a_canLogical_T_7 = asSInt(_a_canLogical_T_6)
node _a_canLogical_T_8 = eq(_a_canLogical_T_7, asSInt(UInt<1>(0h0)))
node _a_canLogical_T_9 = xor(nodeIn.a.bits.address, UInt<29>(0h10000000))
node _a_canLogical_T_10 = cvt(_a_canLogical_T_9)
node _a_canLogical_T_11 = and(_a_canLogical_T_10, asSInt(UInt<30>(0h1a011000)))
node _a_canLogical_T_12 = asSInt(_a_canLogical_T_11)
node _a_canLogical_T_13 = eq(_a_canLogical_T_12, asSInt(UInt<1>(0h0)))
node _a_canLogical_T_14 = or(_a_canLogical_T_8, _a_canLogical_T_13)
node _a_canLogical_T_15 = and(_a_canLogical_T_3, _a_canLogical_T_14)
node _a_canLogical_T_16 = or(UInt<1>(0h0), UInt<1>(0h0))
node _a_canLogical_T_17 = xor(nodeIn.a.bits.address, UInt<1>(0h0))
node _a_canLogical_T_18 = cvt(_a_canLogical_T_17)
node _a_canLogical_T_19 = and(_a_canLogical_T_18, asSInt(UInt<30>(0h1a001000)))
node _a_canLogical_T_20 = asSInt(_a_canLogical_T_19)
node _a_canLogical_T_21 = eq(_a_canLogical_T_20, asSInt(UInt<1>(0h0)))
node _a_canLogical_T_22 = xor(nodeIn.a.bits.address, UInt<17>(0h10000))
node _a_canLogical_T_23 = cvt(_a_canLogical_T_22)
node _a_canLogical_T_24 = and(_a_canLogical_T_23, asSInt(UInt<30>(0h1a010000)))
node _a_canLogical_T_25 = asSInt(_a_canLogical_T_24)
node _a_canLogical_T_26 = eq(_a_canLogical_T_25, asSInt(UInt<1>(0h0)))
node _a_canLogical_T_27 = xor(nodeIn.a.bits.address, UInt<26>(0h2000000))
node _a_canLogical_T_28 = cvt(_a_canLogical_T_27)
node _a_canLogical_T_29 = and(_a_canLogical_T_28, asSInt(UInt<30>(0h1a010000)))
node _a_canLogical_T_30 = asSInt(_a_canLogical_T_29)
node _a_canLogical_T_31 = eq(_a_canLogical_T_30, asSInt(UInt<1>(0h0)))
node _a_canLogical_T_32 = xor(nodeIn.a.bits.address, UInt<26>(0h2010000))
node _a_canLogical_T_33 = cvt(_a_canLogical_T_32)
node _a_canLogical_T_34 = and(_a_canLogical_T_33, asSInt(UInt<30>(0h1a011000)))
node _a_canLogical_T_35 = asSInt(_a_canLogical_T_34)
node _a_canLogical_T_36 = eq(_a_canLogical_T_35, asSInt(UInt<1>(0h0)))
node _a_canLogical_T_37 = xor(nodeIn.a.bits.address, UInt<28>(0h8000000))
node _a_canLogical_T_38 = cvt(_a_canLogical_T_37)
node _a_canLogical_T_39 = and(_a_canLogical_T_38, asSInt(UInt<30>(0h18000000)))
node _a_canLogical_T_40 = asSInt(_a_canLogical_T_39)
node _a_canLogical_T_41 = eq(_a_canLogical_T_40, asSInt(UInt<1>(0h0)))
node _a_canLogical_T_42 = or(_a_canLogical_T_21, _a_canLogical_T_26)
node _a_canLogical_T_43 = or(_a_canLogical_T_42, _a_canLogical_T_31)
node _a_canLogical_T_44 = or(_a_canLogical_T_43, _a_canLogical_T_36)
node _a_canLogical_T_45 = or(_a_canLogical_T_44, _a_canLogical_T_41)
node _a_canLogical_T_46 = and(_a_canLogical_T_16, _a_canLogical_T_45)
node _a_canLogical_T_47 = or(UInt<1>(0h0), _a_canLogical_T_15)
node _a_canLogical_T_48 = or(_a_canLogical_T_47, _a_canLogical_T_46)
node a_canLogical = and(UInt<1>(0h1), _a_canLogical_T_48)
node _a_canArithmetic_T = leq(UInt<1>(0h0), nodeIn.a.bits.size)
node _a_canArithmetic_T_1 = leq(nodeIn.a.bits.size, UInt<2>(0h3))
node _a_canArithmetic_T_2 = and(_a_canArithmetic_T, _a_canArithmetic_T_1)
node _a_canArithmetic_T_3 = or(UInt<1>(0h0), _a_canArithmetic_T_2)
node _a_canArithmetic_T_4 = xor(nodeIn.a.bits.address, UInt<13>(0h1000))
node _a_canArithmetic_T_5 = cvt(_a_canArithmetic_T_4)
node _a_canArithmetic_T_6 = and(_a_canArithmetic_T_5, asSInt(UInt<30>(0h1a011000)))
node _a_canArithmetic_T_7 = asSInt(_a_canArithmetic_T_6)
node _a_canArithmetic_T_8 = eq(_a_canArithmetic_T_7, asSInt(UInt<1>(0h0)))
node _a_canArithmetic_T_9 = xor(nodeIn.a.bits.address, UInt<29>(0h10000000))
node _a_canArithmetic_T_10 = cvt(_a_canArithmetic_T_9)
node _a_canArithmetic_T_11 = and(_a_canArithmetic_T_10, asSInt(UInt<30>(0h1a011000)))
node _a_canArithmetic_T_12 = asSInt(_a_canArithmetic_T_11)
node _a_canArithmetic_T_13 = eq(_a_canArithmetic_T_12, asSInt(UInt<1>(0h0)))
node _a_canArithmetic_T_14 = or(_a_canArithmetic_T_8, _a_canArithmetic_T_13)
node _a_canArithmetic_T_15 = and(_a_canArithmetic_T_3, _a_canArithmetic_T_14)
node _a_canArithmetic_T_16 = or(UInt<1>(0h0), UInt<1>(0h0))
node _a_canArithmetic_T_17 = xor(nodeIn.a.bits.address, UInt<1>(0h0))
node _a_canArithmetic_T_18 = cvt(_a_canArithmetic_T_17)
node _a_canArithmetic_T_19 = and(_a_canArithmetic_T_18, asSInt(UInt<30>(0h1a001000)))
node _a_canArithmetic_T_20 = asSInt(_a_canArithmetic_T_19)
node _a_canArithmetic_T_21 = eq(_a_canArithmetic_T_20, asSInt(UInt<1>(0h0)))
node _a_canArithmetic_T_22 = xor(nodeIn.a.bits.address, UInt<17>(0h10000))
node _a_canArithmetic_T_23 = cvt(_a_canArithmetic_T_22)
node _a_canArithmetic_T_24 = and(_a_canArithmetic_T_23, asSInt(UInt<30>(0h1a010000)))
node _a_canArithmetic_T_25 = asSInt(_a_canArithmetic_T_24)
node _a_canArithmetic_T_26 = eq(_a_canArithmetic_T_25, asSInt(UInt<1>(0h0)))
node _a_canArithmetic_T_27 = xor(nodeIn.a.bits.address, UInt<26>(0h2000000))
node _a_canArithmetic_T_28 = cvt(_a_canArithmetic_T_27)
node _a_canArithmetic_T_29 = and(_a_canArithmetic_T_28, asSInt(UInt<30>(0h1a010000)))
node _a_canArithmetic_T_30 = asSInt(_a_canArithmetic_T_29)
node _a_canArithmetic_T_31 = eq(_a_canArithmetic_T_30, asSInt(UInt<1>(0h0)))
node _a_canArithmetic_T_32 = xor(nodeIn.a.bits.address, UInt<26>(0h2010000))
node _a_canArithmetic_T_33 = cvt(_a_canArithmetic_T_32)
node _a_canArithmetic_T_34 = and(_a_canArithmetic_T_33, asSInt(UInt<30>(0h1a011000)))
node _a_canArithmetic_T_35 = asSInt(_a_canArithmetic_T_34)
node _a_canArithmetic_T_36 = eq(_a_canArithmetic_T_35, asSInt(UInt<1>(0h0)))
node _a_canArithmetic_T_37 = xor(nodeIn.a.bits.address, UInt<28>(0h8000000))
node _a_canArithmetic_T_38 = cvt(_a_canArithmetic_T_37)
node _a_canArithmetic_T_39 = and(_a_canArithmetic_T_38, asSInt(UInt<30>(0h18000000)))
node _a_canArithmetic_T_40 = asSInt(_a_canArithmetic_T_39)
node _a_canArithmetic_T_41 = eq(_a_canArithmetic_T_40, asSInt(UInt<1>(0h0)))
node _a_canArithmetic_T_42 = or(_a_canArithmetic_T_21, _a_canArithmetic_T_26)
node _a_canArithmetic_T_43 = or(_a_canArithmetic_T_42, _a_canArithmetic_T_31)
node _a_canArithmetic_T_44 = or(_a_canArithmetic_T_43, _a_canArithmetic_T_36)
node _a_canArithmetic_T_45 = or(_a_canArithmetic_T_44, _a_canArithmetic_T_41)
node _a_canArithmetic_T_46 = and(_a_canArithmetic_T_16, _a_canArithmetic_T_45)
node _a_canArithmetic_T_47 = or(UInt<1>(0h0), _a_canArithmetic_T_15)
node _a_canArithmetic_T_48 = or(_a_canArithmetic_T_47, _a_canArithmetic_T_46)
node a_canArithmetic = and(UInt<1>(0h1), _a_canArithmetic_T_48)
node a_isLogical = eq(nodeIn.a.bits.opcode, UInt<2>(0h3))
node a_isArithmetic = eq(nodeIn.a.bits.opcode, UInt<2>(0h2))
node _a_isSupported_T = mux(a_isArithmetic, a_canArithmetic, UInt<1>(0h1))
node a_isSupported = mux(a_isLogical, a_canLogical, _a_isSupported_T)
node _a_cam_por_put_T = or(UInt<1>(0h0), cam_amo_0)
node _a_cam_sel_put_T = eq(UInt<1>(0h0), UInt<1>(0h0))
node a_cam_sel_put_0 = and(cam_amo_0, _a_cam_sel_put_T)
node _a_fifoId_T = xor(nodeIn.a.bits.address, UInt<1>(0h0))
node _a_fifoId_T_1 = cvt(_a_fifoId_T)
node _a_fifoId_T_2 = and(_a_fifoId_T_1, asSInt(UInt<1>(0h0)))
node _a_fifoId_T_3 = asSInt(_a_fifoId_T_2)
node _a_fifoId_T_4 = eq(_a_fifoId_T_3, asSInt(UInt<1>(0h0)))
node _a_cam_busy_T = eq(cam_a[0].fifoId, UInt<1>(0h0))
node a_cam_busy = and(cam_abusy_0, _a_cam_busy_T)
node _a_cam_por_free_T = or(UInt<1>(0h0), cam_free_0)
node _a_cam_sel_free_T = eq(UInt<1>(0h0), UInt<1>(0h0))
node a_cam_sel_free_0 = and(cam_free_0, _a_cam_sel_free_T)
node _indexes_T = bits(cam_a[0].bits.data, 0, 0)
node _indexes_T_1 = bits(cam_d[0].data, 0, 0)
node indexes_0 = cat(_indexes_T, _indexes_T_1)
node _indexes_T_2 = bits(cam_a[0].bits.data, 1, 1)
node _indexes_T_3 = bits(cam_d[0].data, 1, 1)
node indexes_1 = cat(_indexes_T_2, _indexes_T_3)
node _indexes_T_4 = bits(cam_a[0].bits.data, 2, 2)
node _indexes_T_5 = bits(cam_d[0].data, 2, 2)
node indexes_2 = cat(_indexes_T_4, _indexes_T_5)
node _indexes_T_6 = bits(cam_a[0].bits.data, 3, 3)
node _indexes_T_7 = bits(cam_d[0].data, 3, 3)
node indexes_3 = cat(_indexes_T_6, _indexes_T_7)
node _indexes_T_8 = bits(cam_a[0].bits.data, 4, 4)
node _indexes_T_9 = bits(cam_d[0].data, 4, 4)
node indexes_4 = cat(_indexes_T_8, _indexes_T_9)
node _indexes_T_10 = bits(cam_a[0].bits.data, 5, 5)
node _indexes_T_11 = bits(cam_d[0].data, 5, 5)
node indexes_5 = cat(_indexes_T_10, _indexes_T_11)
node _indexes_T_12 = bits(cam_a[0].bits.data, 6, 6)
node _indexes_T_13 = bits(cam_d[0].data, 6, 6)
node indexes_6 = cat(_indexes_T_12, _indexes_T_13)
node _indexes_T_14 = bits(cam_a[0].bits.data, 7, 7)
node _indexes_T_15 = bits(cam_d[0].data, 7, 7)
node indexes_7 = cat(_indexes_T_14, _indexes_T_15)
node _indexes_T_16 = bits(cam_a[0].bits.data, 8, 8)
node _indexes_T_17 = bits(cam_d[0].data, 8, 8)
node indexes_8 = cat(_indexes_T_16, _indexes_T_17)
node _indexes_T_18 = bits(cam_a[0].bits.data, 9, 9)
node _indexes_T_19 = bits(cam_d[0].data, 9, 9)
node indexes_9 = cat(_indexes_T_18, _indexes_T_19)
node _indexes_T_20 = bits(cam_a[0].bits.data, 10, 10)
node _indexes_T_21 = bits(cam_d[0].data, 10, 10)
node indexes_10 = cat(_indexes_T_20, _indexes_T_21)
node _indexes_T_22 = bits(cam_a[0].bits.data, 11, 11)
node _indexes_T_23 = bits(cam_d[0].data, 11, 11)
node indexes_11 = cat(_indexes_T_22, _indexes_T_23)
node _indexes_T_24 = bits(cam_a[0].bits.data, 12, 12)
node _indexes_T_25 = bits(cam_d[0].data, 12, 12)
node indexes_12 = cat(_indexes_T_24, _indexes_T_25)
node _indexes_T_26 = bits(cam_a[0].bits.data, 13, 13)
node _indexes_T_27 = bits(cam_d[0].data, 13, 13)
node indexes_13 = cat(_indexes_T_26, _indexes_T_27)
node _indexes_T_28 = bits(cam_a[0].bits.data, 14, 14)
node _indexes_T_29 = bits(cam_d[0].data, 14, 14)
node indexes_14 = cat(_indexes_T_28, _indexes_T_29)
node _indexes_T_30 = bits(cam_a[0].bits.data, 15, 15)
node _indexes_T_31 = bits(cam_d[0].data, 15, 15)
node indexes_15 = cat(_indexes_T_30, _indexes_T_31)
node _indexes_T_32 = bits(cam_a[0].bits.data, 16, 16)
node _indexes_T_33 = bits(cam_d[0].data, 16, 16)
node indexes_16 = cat(_indexes_T_32, _indexes_T_33)
node _indexes_T_34 = bits(cam_a[0].bits.data, 17, 17)
node _indexes_T_35 = bits(cam_d[0].data, 17, 17)
node indexes_17 = cat(_indexes_T_34, _indexes_T_35)
node _indexes_T_36 = bits(cam_a[0].bits.data, 18, 18)
node _indexes_T_37 = bits(cam_d[0].data, 18, 18)
node indexes_18 = cat(_indexes_T_36, _indexes_T_37)
node _indexes_T_38 = bits(cam_a[0].bits.data, 19, 19)
node _indexes_T_39 = bits(cam_d[0].data, 19, 19)
node indexes_19 = cat(_indexes_T_38, _indexes_T_39)
node _indexes_T_40 = bits(cam_a[0].bits.data, 20, 20)
node _indexes_T_41 = bits(cam_d[0].data, 20, 20)
node indexes_20 = cat(_indexes_T_40, _indexes_T_41)
node _indexes_T_42 = bits(cam_a[0].bits.data, 21, 21)
node _indexes_T_43 = bits(cam_d[0].data, 21, 21)
node indexes_21 = cat(_indexes_T_42, _indexes_T_43)
node _indexes_T_44 = bits(cam_a[0].bits.data, 22, 22)
node _indexes_T_45 = bits(cam_d[0].data, 22, 22)
node indexes_22 = cat(_indexes_T_44, _indexes_T_45)
node _indexes_T_46 = bits(cam_a[0].bits.data, 23, 23)
node _indexes_T_47 = bits(cam_d[0].data, 23, 23)
node indexes_23 = cat(_indexes_T_46, _indexes_T_47)
node _indexes_T_48 = bits(cam_a[0].bits.data, 24, 24)
node _indexes_T_49 = bits(cam_d[0].data, 24, 24)
node indexes_24 = cat(_indexes_T_48, _indexes_T_49)
node _indexes_T_50 = bits(cam_a[0].bits.data, 25, 25)
node _indexes_T_51 = bits(cam_d[0].data, 25, 25)
node indexes_25 = cat(_indexes_T_50, _indexes_T_51)
node _indexes_T_52 = bits(cam_a[0].bits.data, 26, 26)
node _indexes_T_53 = bits(cam_d[0].data, 26, 26)
node indexes_26 = cat(_indexes_T_52, _indexes_T_53)
node _indexes_T_54 = bits(cam_a[0].bits.data, 27, 27)
node _indexes_T_55 = bits(cam_d[0].data, 27, 27)
node indexes_27 = cat(_indexes_T_54, _indexes_T_55)
node _indexes_T_56 = bits(cam_a[0].bits.data, 28, 28)
node _indexes_T_57 = bits(cam_d[0].data, 28, 28)
node indexes_28 = cat(_indexes_T_56, _indexes_T_57)
node _indexes_T_58 = bits(cam_a[0].bits.data, 29, 29)
node _indexes_T_59 = bits(cam_d[0].data, 29, 29)
node indexes_29 = cat(_indexes_T_58, _indexes_T_59)
node _indexes_T_60 = bits(cam_a[0].bits.data, 30, 30)
node _indexes_T_61 = bits(cam_d[0].data, 30, 30)
node indexes_30 = cat(_indexes_T_60, _indexes_T_61)
node _indexes_T_62 = bits(cam_a[0].bits.data, 31, 31)
node _indexes_T_63 = bits(cam_d[0].data, 31, 31)
node indexes_31 = cat(_indexes_T_62, _indexes_T_63)
node _indexes_T_64 = bits(cam_a[0].bits.data, 32, 32)
node _indexes_T_65 = bits(cam_d[0].data, 32, 32)
node indexes_32 = cat(_indexes_T_64, _indexes_T_65)
node _indexes_T_66 = bits(cam_a[0].bits.data, 33, 33)
node _indexes_T_67 = bits(cam_d[0].data, 33, 33)
node indexes_33 = cat(_indexes_T_66, _indexes_T_67)
node _indexes_T_68 = bits(cam_a[0].bits.data, 34, 34)
node _indexes_T_69 = bits(cam_d[0].data, 34, 34)
node indexes_34 = cat(_indexes_T_68, _indexes_T_69)
node _indexes_T_70 = bits(cam_a[0].bits.data, 35, 35)
node _indexes_T_71 = bits(cam_d[0].data, 35, 35)
node indexes_35 = cat(_indexes_T_70, _indexes_T_71)
node _indexes_T_72 = bits(cam_a[0].bits.data, 36, 36)
node _indexes_T_73 = bits(cam_d[0].data, 36, 36)
node indexes_36 = cat(_indexes_T_72, _indexes_T_73)
node _indexes_T_74 = bits(cam_a[0].bits.data, 37, 37)
node _indexes_T_75 = bits(cam_d[0].data, 37, 37)
node indexes_37 = cat(_indexes_T_74, _indexes_T_75)
node _indexes_T_76 = bits(cam_a[0].bits.data, 38, 38)
node _indexes_T_77 = bits(cam_d[0].data, 38, 38)
node indexes_38 = cat(_indexes_T_76, _indexes_T_77)
node _indexes_T_78 = bits(cam_a[0].bits.data, 39, 39)
node _indexes_T_79 = bits(cam_d[0].data, 39, 39)
node indexes_39 = cat(_indexes_T_78, _indexes_T_79)
node _indexes_T_80 = bits(cam_a[0].bits.data, 40, 40)
node _indexes_T_81 = bits(cam_d[0].data, 40, 40)
node indexes_40 = cat(_indexes_T_80, _indexes_T_81)
node _indexes_T_82 = bits(cam_a[0].bits.data, 41, 41)
node _indexes_T_83 = bits(cam_d[0].data, 41, 41)
node indexes_41 = cat(_indexes_T_82, _indexes_T_83)
node _indexes_T_84 = bits(cam_a[0].bits.data, 42, 42)
node _indexes_T_85 = bits(cam_d[0].data, 42, 42)
node indexes_42 = cat(_indexes_T_84, _indexes_T_85)
node _indexes_T_86 = bits(cam_a[0].bits.data, 43, 43)
node _indexes_T_87 = bits(cam_d[0].data, 43, 43)
node indexes_43 = cat(_indexes_T_86, _indexes_T_87)
node _indexes_T_88 = bits(cam_a[0].bits.data, 44, 44)
node _indexes_T_89 = bits(cam_d[0].data, 44, 44)
node indexes_44 = cat(_indexes_T_88, _indexes_T_89)
node _indexes_T_90 = bits(cam_a[0].bits.data, 45, 45)
node _indexes_T_91 = bits(cam_d[0].data, 45, 45)
node indexes_45 = cat(_indexes_T_90, _indexes_T_91)
node _indexes_T_92 = bits(cam_a[0].bits.data, 46, 46)
node _indexes_T_93 = bits(cam_d[0].data, 46, 46)
node indexes_46 = cat(_indexes_T_92, _indexes_T_93)
node _indexes_T_94 = bits(cam_a[0].bits.data, 47, 47)
node _indexes_T_95 = bits(cam_d[0].data, 47, 47)
node indexes_47 = cat(_indexes_T_94, _indexes_T_95)
node _indexes_T_96 = bits(cam_a[0].bits.data, 48, 48)
node _indexes_T_97 = bits(cam_d[0].data, 48, 48)
node indexes_48 = cat(_indexes_T_96, _indexes_T_97)
node _indexes_T_98 = bits(cam_a[0].bits.data, 49, 49)
node _indexes_T_99 = bits(cam_d[0].data, 49, 49)
node indexes_49 = cat(_indexes_T_98, _indexes_T_99)
node _indexes_T_100 = bits(cam_a[0].bits.data, 50, 50)
node _indexes_T_101 = bits(cam_d[0].data, 50, 50)
node indexes_50 = cat(_indexes_T_100, _indexes_T_101)
node _indexes_T_102 = bits(cam_a[0].bits.data, 51, 51)
node _indexes_T_103 = bits(cam_d[0].data, 51, 51)
node indexes_51 = cat(_indexes_T_102, _indexes_T_103)
node _indexes_T_104 = bits(cam_a[0].bits.data, 52, 52)
node _indexes_T_105 = bits(cam_d[0].data, 52, 52)
node indexes_52 = cat(_indexes_T_104, _indexes_T_105)
node _indexes_T_106 = bits(cam_a[0].bits.data, 53, 53)
node _indexes_T_107 = bits(cam_d[0].data, 53, 53)
node indexes_53 = cat(_indexes_T_106, _indexes_T_107)
node _indexes_T_108 = bits(cam_a[0].bits.data, 54, 54)
node _indexes_T_109 = bits(cam_d[0].data, 54, 54)
node indexes_54 = cat(_indexes_T_108, _indexes_T_109)
node _indexes_T_110 = bits(cam_a[0].bits.data, 55, 55)
node _indexes_T_111 = bits(cam_d[0].data, 55, 55)
node indexes_55 = cat(_indexes_T_110, _indexes_T_111)
node _indexes_T_112 = bits(cam_a[0].bits.data, 56, 56)
node _indexes_T_113 = bits(cam_d[0].data, 56, 56)
node indexes_56 = cat(_indexes_T_112, _indexes_T_113)
node _indexes_T_114 = bits(cam_a[0].bits.data, 57, 57)
node _indexes_T_115 = bits(cam_d[0].data, 57, 57)
node indexes_57 = cat(_indexes_T_114, _indexes_T_115)
node _indexes_T_116 = bits(cam_a[0].bits.data, 58, 58)
node _indexes_T_117 = bits(cam_d[0].data, 58, 58)
node indexes_58 = cat(_indexes_T_116, _indexes_T_117)
node _indexes_T_118 = bits(cam_a[0].bits.data, 59, 59)
node _indexes_T_119 = bits(cam_d[0].data, 59, 59)
node indexes_59 = cat(_indexes_T_118, _indexes_T_119)
node _indexes_T_120 = bits(cam_a[0].bits.data, 60, 60)
node _indexes_T_121 = bits(cam_d[0].data, 60, 60)
node indexes_60 = cat(_indexes_T_120, _indexes_T_121)
node _indexes_T_122 = bits(cam_a[0].bits.data, 61, 61)
node _indexes_T_123 = bits(cam_d[0].data, 61, 61)
node indexes_61 = cat(_indexes_T_122, _indexes_T_123)
node _indexes_T_124 = bits(cam_a[0].bits.data, 62, 62)
node _indexes_T_125 = bits(cam_d[0].data, 62, 62)
node indexes_62 = cat(_indexes_T_124, _indexes_T_125)
node _indexes_T_126 = bits(cam_a[0].bits.data, 63, 63)
node _indexes_T_127 = bits(cam_d[0].data, 63, 63)
node indexes_63 = cat(_indexes_T_126, _indexes_T_127)
node _logic_out_T = dshr(cam_a[0].lut, indexes_0)
node _logic_out_T_1 = bits(_logic_out_T, 0, 0)
node _logic_out_T_2 = dshr(cam_a[0].lut, indexes_1)
node _logic_out_T_3 = bits(_logic_out_T_2, 0, 0)
node _logic_out_T_4 = dshr(cam_a[0].lut, indexes_2)
node _logic_out_T_5 = bits(_logic_out_T_4, 0, 0)
node _logic_out_T_6 = dshr(cam_a[0].lut, indexes_3)
node _logic_out_T_7 = bits(_logic_out_T_6, 0, 0)
node _logic_out_T_8 = dshr(cam_a[0].lut, indexes_4)
node _logic_out_T_9 = bits(_logic_out_T_8, 0, 0)
node _logic_out_T_10 = dshr(cam_a[0].lut, indexes_5)
node _logic_out_T_11 = bits(_logic_out_T_10, 0, 0)
node _logic_out_T_12 = dshr(cam_a[0].lut, indexes_6)
node _logic_out_T_13 = bits(_logic_out_T_12, 0, 0)
node _logic_out_T_14 = dshr(cam_a[0].lut, indexes_7)
node _logic_out_T_15 = bits(_logic_out_T_14, 0, 0)
node _logic_out_T_16 = dshr(cam_a[0].lut, indexes_8)
node _logic_out_T_17 = bits(_logic_out_T_16, 0, 0)
node _logic_out_T_18 = dshr(cam_a[0].lut, indexes_9)
node _logic_out_T_19 = bits(_logic_out_T_18, 0, 0)
node _logic_out_T_20 = dshr(cam_a[0].lut, indexes_10)
node _logic_out_T_21 = bits(_logic_out_T_20, 0, 0)
node _logic_out_T_22 = dshr(cam_a[0].lut, indexes_11)
node _logic_out_T_23 = bits(_logic_out_T_22, 0, 0)
node _logic_out_T_24 = dshr(cam_a[0].lut, indexes_12)
node _logic_out_T_25 = bits(_logic_out_T_24, 0, 0)
node _logic_out_T_26 = dshr(cam_a[0].lut, indexes_13)
node _logic_out_T_27 = bits(_logic_out_T_26, 0, 0)
node _logic_out_T_28 = dshr(cam_a[0].lut, indexes_14)
node _logic_out_T_29 = bits(_logic_out_T_28, 0, 0)
node _logic_out_T_30 = dshr(cam_a[0].lut, indexes_15)
node _logic_out_T_31 = bits(_logic_out_T_30, 0, 0)
node _logic_out_T_32 = dshr(cam_a[0].lut, indexes_16)
node _logic_out_T_33 = bits(_logic_out_T_32, 0, 0)
node _logic_out_T_34 = dshr(cam_a[0].lut, indexes_17)
node _logic_out_T_35 = bits(_logic_out_T_34, 0, 0)
node _logic_out_T_36 = dshr(cam_a[0].lut, indexes_18)
node _logic_out_T_37 = bits(_logic_out_T_36, 0, 0)
node _logic_out_T_38 = dshr(cam_a[0].lut, indexes_19)
node _logic_out_T_39 = bits(_logic_out_T_38, 0, 0)
node _logic_out_T_40 = dshr(cam_a[0].lut, indexes_20)
node _logic_out_T_41 = bits(_logic_out_T_40, 0, 0)
node _logic_out_T_42 = dshr(cam_a[0].lut, indexes_21)
node _logic_out_T_43 = bits(_logic_out_T_42, 0, 0)
node _logic_out_T_44 = dshr(cam_a[0].lut, indexes_22)
node _logic_out_T_45 = bits(_logic_out_T_44, 0, 0)
node _logic_out_T_46 = dshr(cam_a[0].lut, indexes_23)
node _logic_out_T_47 = bits(_logic_out_T_46, 0, 0)
node _logic_out_T_48 = dshr(cam_a[0].lut, indexes_24)
node _logic_out_T_49 = bits(_logic_out_T_48, 0, 0)
node _logic_out_T_50 = dshr(cam_a[0].lut, indexes_25)
node _logic_out_T_51 = bits(_logic_out_T_50, 0, 0)
node _logic_out_T_52 = dshr(cam_a[0].lut, indexes_26)
node _logic_out_T_53 = bits(_logic_out_T_52, 0, 0)
node _logic_out_T_54 = dshr(cam_a[0].lut, indexes_27)
node _logic_out_T_55 = bits(_logic_out_T_54, 0, 0)
node _logic_out_T_56 = dshr(cam_a[0].lut, indexes_28)
node _logic_out_T_57 = bits(_logic_out_T_56, 0, 0)
node _logic_out_T_58 = dshr(cam_a[0].lut, indexes_29)
node _logic_out_T_59 = bits(_logic_out_T_58, 0, 0)
node _logic_out_T_60 = dshr(cam_a[0].lut, indexes_30)
node _logic_out_T_61 = bits(_logic_out_T_60, 0, 0)
node _logic_out_T_62 = dshr(cam_a[0].lut, indexes_31)
node _logic_out_T_63 = bits(_logic_out_T_62, 0, 0)
node _logic_out_T_64 = dshr(cam_a[0].lut, indexes_32)
node _logic_out_T_65 = bits(_logic_out_T_64, 0, 0)
node _logic_out_T_66 = dshr(cam_a[0].lut, indexes_33)
node _logic_out_T_67 = bits(_logic_out_T_66, 0, 0)
node _logic_out_T_68 = dshr(cam_a[0].lut, indexes_34)
node _logic_out_T_69 = bits(_logic_out_T_68, 0, 0)
node _logic_out_T_70 = dshr(cam_a[0].lut, indexes_35)
node _logic_out_T_71 = bits(_logic_out_T_70, 0, 0)
node _logic_out_T_72 = dshr(cam_a[0].lut, indexes_36)
node _logic_out_T_73 = bits(_logic_out_T_72, 0, 0)
node _logic_out_T_74 = dshr(cam_a[0].lut, indexes_37)
node _logic_out_T_75 = bits(_logic_out_T_74, 0, 0)
node _logic_out_T_76 = dshr(cam_a[0].lut, indexes_38)
node _logic_out_T_77 = bits(_logic_out_T_76, 0, 0)
node _logic_out_T_78 = dshr(cam_a[0].lut, indexes_39)
node _logic_out_T_79 = bits(_logic_out_T_78, 0, 0)
node _logic_out_T_80 = dshr(cam_a[0].lut, indexes_40)
node _logic_out_T_81 = bits(_logic_out_T_80, 0, 0)
node _logic_out_T_82 = dshr(cam_a[0].lut, indexes_41)
node _logic_out_T_83 = bits(_logic_out_T_82, 0, 0)
node _logic_out_T_84 = dshr(cam_a[0].lut, indexes_42)
node _logic_out_T_85 = bits(_logic_out_T_84, 0, 0)
node _logic_out_T_86 = dshr(cam_a[0].lut, indexes_43)
node _logic_out_T_87 = bits(_logic_out_T_86, 0, 0)
node _logic_out_T_88 = dshr(cam_a[0].lut, indexes_44)
node _logic_out_T_89 = bits(_logic_out_T_88, 0, 0)
node _logic_out_T_90 = dshr(cam_a[0].lut, indexes_45)
node _logic_out_T_91 = bits(_logic_out_T_90, 0, 0)
node _logic_out_T_92 = dshr(cam_a[0].lut, indexes_46)
node _logic_out_T_93 = bits(_logic_out_T_92, 0, 0)
node _logic_out_T_94 = dshr(cam_a[0].lut, indexes_47)
node _logic_out_T_95 = bits(_logic_out_T_94, 0, 0)
node _logic_out_T_96 = dshr(cam_a[0].lut, indexes_48)
node _logic_out_T_97 = bits(_logic_out_T_96, 0, 0)
node _logic_out_T_98 = dshr(cam_a[0].lut, indexes_49)
node _logic_out_T_99 = bits(_logic_out_T_98, 0, 0)
node _logic_out_T_100 = dshr(cam_a[0].lut, indexes_50)
node _logic_out_T_101 = bits(_logic_out_T_100, 0, 0)
node _logic_out_T_102 = dshr(cam_a[0].lut, indexes_51)
node _logic_out_T_103 = bits(_logic_out_T_102, 0, 0)
node _logic_out_T_104 = dshr(cam_a[0].lut, indexes_52)
node _logic_out_T_105 = bits(_logic_out_T_104, 0, 0)
node _logic_out_T_106 = dshr(cam_a[0].lut, indexes_53)
node _logic_out_T_107 = bits(_logic_out_T_106, 0, 0)
node _logic_out_T_108 = dshr(cam_a[0].lut, indexes_54)
node _logic_out_T_109 = bits(_logic_out_T_108, 0, 0)
node _logic_out_T_110 = dshr(cam_a[0].lut, indexes_55)
node _logic_out_T_111 = bits(_logic_out_T_110, 0, 0)
node _logic_out_T_112 = dshr(cam_a[0].lut, indexes_56)
node _logic_out_T_113 = bits(_logic_out_T_112, 0, 0)
node _logic_out_T_114 = dshr(cam_a[0].lut, indexes_57)
node _logic_out_T_115 = bits(_logic_out_T_114, 0, 0)
node _logic_out_T_116 = dshr(cam_a[0].lut, indexes_58)
node _logic_out_T_117 = bits(_logic_out_T_116, 0, 0)
node _logic_out_T_118 = dshr(cam_a[0].lut, indexes_59)
node _logic_out_T_119 = bits(_logic_out_T_118, 0, 0)
node _logic_out_T_120 = dshr(cam_a[0].lut, indexes_60)
node _logic_out_T_121 = bits(_logic_out_T_120, 0, 0)
node _logic_out_T_122 = dshr(cam_a[0].lut, indexes_61)
node _logic_out_T_123 = bits(_logic_out_T_122, 0, 0)
node _logic_out_T_124 = dshr(cam_a[0].lut, indexes_62)
node _logic_out_T_125 = bits(_logic_out_T_124, 0, 0)
node _logic_out_T_126 = dshr(cam_a[0].lut, indexes_63)
node _logic_out_T_127 = bits(_logic_out_T_126, 0, 0)
node logic_out_lo_lo_lo_lo_lo = cat(_logic_out_T_3, _logic_out_T_1)
node logic_out_lo_lo_lo_lo_hi = cat(_logic_out_T_7, _logic_out_T_5)
node logic_out_lo_lo_lo_lo = cat(logic_out_lo_lo_lo_lo_hi, logic_out_lo_lo_lo_lo_lo)
node logic_out_lo_lo_lo_hi_lo = cat(_logic_out_T_11, _logic_out_T_9)
node logic_out_lo_lo_lo_hi_hi = cat(_logic_out_T_15, _logic_out_T_13)
node logic_out_lo_lo_lo_hi = cat(logic_out_lo_lo_lo_hi_hi, logic_out_lo_lo_lo_hi_lo)
node logic_out_lo_lo_lo = cat(logic_out_lo_lo_lo_hi, logic_out_lo_lo_lo_lo)
node logic_out_lo_lo_hi_lo_lo = cat(_logic_out_T_19, _logic_out_T_17)
node logic_out_lo_lo_hi_lo_hi = cat(_logic_out_T_23, _logic_out_T_21)
node logic_out_lo_lo_hi_lo = cat(logic_out_lo_lo_hi_lo_hi, logic_out_lo_lo_hi_lo_lo)
node logic_out_lo_lo_hi_hi_lo = cat(_logic_out_T_27, _logic_out_T_25)
node logic_out_lo_lo_hi_hi_hi = cat(_logic_out_T_31, _logic_out_T_29)
node logic_out_lo_lo_hi_hi = cat(logic_out_lo_lo_hi_hi_hi, logic_out_lo_lo_hi_hi_lo)
node logic_out_lo_lo_hi = cat(logic_out_lo_lo_hi_hi, logic_out_lo_lo_hi_lo)
node logic_out_lo_lo = cat(logic_out_lo_lo_hi, logic_out_lo_lo_lo)
node logic_out_lo_hi_lo_lo_lo = cat(_logic_out_T_35, _logic_out_T_33)
node logic_out_lo_hi_lo_lo_hi = cat(_logic_out_T_39, _logic_out_T_37)
node logic_out_lo_hi_lo_lo = cat(logic_out_lo_hi_lo_lo_hi, logic_out_lo_hi_lo_lo_lo)
node logic_out_lo_hi_lo_hi_lo = cat(_logic_out_T_43, _logic_out_T_41)
node logic_out_lo_hi_lo_hi_hi = cat(_logic_out_T_47, _logic_out_T_45)
node logic_out_lo_hi_lo_hi = cat(logic_out_lo_hi_lo_hi_hi, logic_out_lo_hi_lo_hi_lo)
node logic_out_lo_hi_lo = cat(logic_out_lo_hi_lo_hi, logic_out_lo_hi_lo_lo)
node logic_out_lo_hi_hi_lo_lo = cat(_logic_out_T_51, _logic_out_T_49)
node logic_out_lo_hi_hi_lo_hi = cat(_logic_out_T_55, _logic_out_T_53)
node logic_out_lo_hi_hi_lo = cat(logic_out_lo_hi_hi_lo_hi, logic_out_lo_hi_hi_lo_lo)
node logic_out_lo_hi_hi_hi_lo = cat(_logic_out_T_59, _logic_out_T_57)
node logic_out_lo_hi_hi_hi_hi = cat(_logic_out_T_63, _logic_out_T_61)
node logic_out_lo_hi_hi_hi = cat(logic_out_lo_hi_hi_hi_hi, logic_out_lo_hi_hi_hi_lo)
node logic_out_lo_hi_hi = cat(logic_out_lo_hi_hi_hi, logic_out_lo_hi_hi_lo)
node logic_out_lo_hi = cat(logic_out_lo_hi_hi, logic_out_lo_hi_lo)
node logic_out_lo = cat(logic_out_lo_hi, logic_out_lo_lo)
node logic_out_hi_lo_lo_lo_lo = cat(_logic_out_T_67, _logic_out_T_65)
node logic_out_hi_lo_lo_lo_hi = cat(_logic_out_T_71, _logic_out_T_69)
node logic_out_hi_lo_lo_lo = cat(logic_out_hi_lo_lo_lo_hi, logic_out_hi_lo_lo_lo_lo)
node logic_out_hi_lo_lo_hi_lo = cat(_logic_out_T_75, _logic_out_T_73)
node logic_out_hi_lo_lo_hi_hi = cat(_logic_out_T_79, _logic_out_T_77)
node logic_out_hi_lo_lo_hi = cat(logic_out_hi_lo_lo_hi_hi, logic_out_hi_lo_lo_hi_lo)
node logic_out_hi_lo_lo = cat(logic_out_hi_lo_lo_hi, logic_out_hi_lo_lo_lo)
node logic_out_hi_lo_hi_lo_lo = cat(_logic_out_T_83, _logic_out_T_81)
node logic_out_hi_lo_hi_lo_hi = cat(_logic_out_T_87, _logic_out_T_85)
node logic_out_hi_lo_hi_lo = cat(logic_out_hi_lo_hi_lo_hi, logic_out_hi_lo_hi_lo_lo)
node logic_out_hi_lo_hi_hi_lo = cat(_logic_out_T_91, _logic_out_T_89)
node logic_out_hi_lo_hi_hi_hi = cat(_logic_out_T_95, _logic_out_T_93)
node logic_out_hi_lo_hi_hi = cat(logic_out_hi_lo_hi_hi_hi, logic_out_hi_lo_hi_hi_lo)
node logic_out_hi_lo_hi = cat(logic_out_hi_lo_hi_hi, logic_out_hi_lo_hi_lo)
node logic_out_hi_lo = cat(logic_out_hi_lo_hi, logic_out_hi_lo_lo)
node logic_out_hi_hi_lo_lo_lo = cat(_logic_out_T_99, _logic_out_T_97)
node logic_out_hi_hi_lo_lo_hi = cat(_logic_out_T_103, _logic_out_T_101)
node logic_out_hi_hi_lo_lo = cat(logic_out_hi_hi_lo_lo_hi, logic_out_hi_hi_lo_lo_lo)
node logic_out_hi_hi_lo_hi_lo = cat(_logic_out_T_107, _logic_out_T_105)
node logic_out_hi_hi_lo_hi_hi = cat(_logic_out_T_111, _logic_out_T_109)
node logic_out_hi_hi_lo_hi = cat(logic_out_hi_hi_lo_hi_hi, logic_out_hi_hi_lo_hi_lo)
node logic_out_hi_hi_lo = cat(logic_out_hi_hi_lo_hi, logic_out_hi_hi_lo_lo)
node logic_out_hi_hi_hi_lo_lo = cat(_logic_out_T_115, _logic_out_T_113)
node logic_out_hi_hi_hi_lo_hi = cat(_logic_out_T_119, _logic_out_T_117)
node logic_out_hi_hi_hi_lo = cat(logic_out_hi_hi_hi_lo_hi, logic_out_hi_hi_hi_lo_lo)
node logic_out_hi_hi_hi_hi_lo = cat(_logic_out_T_123, _logic_out_T_121)
node logic_out_hi_hi_hi_hi_hi = cat(_logic_out_T_127, _logic_out_T_125)
node logic_out_hi_hi_hi_hi = cat(logic_out_hi_hi_hi_hi_hi, logic_out_hi_hi_hi_hi_lo)
node logic_out_hi_hi_hi = cat(logic_out_hi_hi_hi_hi, logic_out_hi_hi_hi_lo)
node logic_out_hi_hi = cat(logic_out_hi_hi_hi, logic_out_hi_hi_lo)
node logic_out_hi = cat(logic_out_hi_hi, logic_out_hi_lo)
node logic_out = cat(logic_out_hi, logic_out_lo)
node unsigned = bits(cam_a[0].bits.param, 1, 1)
node take_max = bits(cam_a[0].bits.param, 0, 0)
node adder = bits(cam_a[0].bits.param, 2, 2)
node _signSel_T = not(cam_a[0].bits.mask)
node _signSel_T_1 = shr(cam_a[0].bits.mask, 1)
node _signSel_T_2 = or(_signSel_T, _signSel_T_1)
node signSel = not(_signSel_T_2)
node _signbits_a_T = bits(cam_a[0].bits.data, 7, 7)
node _signbits_a_T_1 = bits(cam_a[0].bits.data, 15, 15)
node _signbits_a_T_2 = bits(cam_a[0].bits.data, 23, 23)
node _signbits_a_T_3 = bits(cam_a[0].bits.data, 31, 31)
node _signbits_a_T_4 = bits(cam_a[0].bits.data, 39, 39)
node _signbits_a_T_5 = bits(cam_a[0].bits.data, 47, 47)
node _signbits_a_T_6 = bits(cam_a[0].bits.data, 55, 55)
node _signbits_a_T_7 = bits(cam_a[0].bits.data, 63, 63)
node signbits_a_lo_lo = cat(_signbits_a_T_1, _signbits_a_T)
node signbits_a_lo_hi = cat(_signbits_a_T_3, _signbits_a_T_2)
node signbits_a_lo = cat(signbits_a_lo_hi, signbits_a_lo_lo)
node signbits_a_hi_lo = cat(_signbits_a_T_5, _signbits_a_T_4)
node signbits_a_hi_hi = cat(_signbits_a_T_7, _signbits_a_T_6)
node signbits_a_hi = cat(signbits_a_hi_hi, signbits_a_hi_lo)
node signbits_a = cat(signbits_a_hi, signbits_a_lo)
node _signbits_d_T = bits(cam_d[0].data, 7, 7)
node _signbits_d_T_1 = bits(cam_d[0].data, 15, 15)
node _signbits_d_T_2 = bits(cam_d[0].data, 23, 23)
node _signbits_d_T_3 = bits(cam_d[0].data, 31, 31)
node _signbits_d_T_4 = bits(cam_d[0].data, 39, 39)
node _signbits_d_T_5 = bits(cam_d[0].data, 47, 47)
node _signbits_d_T_6 = bits(cam_d[0].data, 55, 55)
node _signbits_d_T_7 = bits(cam_d[0].data, 63, 63)
node signbits_d_lo_lo = cat(_signbits_d_T_1, _signbits_d_T)
node signbits_d_lo_hi = cat(_signbits_d_T_3, _signbits_d_T_2)
node signbits_d_lo = cat(signbits_d_lo_hi, signbits_d_lo_lo)
node signbits_d_hi_lo = cat(_signbits_d_T_5, _signbits_d_T_4)
node signbits_d_hi_hi = cat(_signbits_d_T_7, _signbits_d_T_6)
node signbits_d_hi = cat(signbits_d_hi_hi, signbits_d_hi_lo)
node signbits_d = cat(signbits_d_hi, signbits_d_lo)
node _signbit_a_T = and(signbits_a, signSel)
node _signbit_a_T_1 = shl(_signbit_a_T, 1)
node signbit_a = bits(_signbit_a_T_1, 7, 0)
node _signbit_d_T = and(signbits_d, signSel)
node _signbit_d_T_1 = shl(_signbit_d_T, 1)
node signbit_d = bits(_signbit_d_T_1, 7, 0)
node _signext_a_T = shl(signbit_a, 1)
node _signext_a_T_1 = bits(_signext_a_T, 7, 0)
node _signext_a_T_2 = or(signbit_a, _signext_a_T_1)
node _signext_a_T_3 = shl(_signext_a_T_2, 2)
node _signext_a_T_4 = bits(_signext_a_T_3, 7, 0)
node _signext_a_T_5 = or(_signext_a_T_2, _signext_a_T_4)
node _signext_a_T_6 = shl(_signext_a_T_5, 4)
node _signext_a_T_7 = bits(_signext_a_T_6, 7, 0)
node _signext_a_T_8 = or(_signext_a_T_5, _signext_a_T_7)
node _signext_a_T_9 = bits(_signext_a_T_8, 7, 0)
node _signext_a_T_10 = bits(_signext_a_T_9, 0, 0)
node _signext_a_T_11 = bits(_signext_a_T_9, 1, 1)
node _signext_a_T_12 = bits(_signext_a_T_9, 2, 2)
node _signext_a_T_13 = bits(_signext_a_T_9, 3, 3)
node _signext_a_T_14 = bits(_signext_a_T_9, 4, 4)
node _signext_a_T_15 = bits(_signext_a_T_9, 5, 5)
node _signext_a_T_16 = bits(_signext_a_T_9, 6, 6)
node _signext_a_T_17 = bits(_signext_a_T_9, 7, 7)
node _signext_a_T_18 = mux(_signext_a_T_10, UInt<8>(0hff), UInt<8>(0h0))
node _signext_a_T_19 = mux(_signext_a_T_11, UInt<8>(0hff), UInt<8>(0h0))
node _signext_a_T_20 = mux(_signext_a_T_12, UInt<8>(0hff), UInt<8>(0h0))
node _signext_a_T_21 = mux(_signext_a_T_13, UInt<8>(0hff), UInt<8>(0h0))
node _signext_a_T_22 = mux(_signext_a_T_14, UInt<8>(0hff), UInt<8>(0h0))
node _signext_a_T_23 = mux(_signext_a_T_15, UInt<8>(0hff), UInt<8>(0h0))
node _signext_a_T_24 = mux(_signext_a_T_16, UInt<8>(0hff), UInt<8>(0h0))
node _signext_a_T_25 = mux(_signext_a_T_17, UInt<8>(0hff), UInt<8>(0h0))
node signext_a_lo_lo = cat(_signext_a_T_19, _signext_a_T_18)
node signext_a_lo_hi = cat(_signext_a_T_21, _signext_a_T_20)
node signext_a_lo = cat(signext_a_lo_hi, signext_a_lo_lo)
node signext_a_hi_lo = cat(_signext_a_T_23, _signext_a_T_22)
node signext_a_hi_hi = cat(_signext_a_T_25, _signext_a_T_24)
node signext_a_hi = cat(signext_a_hi_hi, signext_a_hi_lo)
node signext_a = cat(signext_a_hi, signext_a_lo)
node _signext_d_T = shl(signbit_d, 1)
node _signext_d_T_1 = bits(_signext_d_T, 7, 0)
node _signext_d_T_2 = or(signbit_d, _signext_d_T_1)
node _signext_d_T_3 = shl(_signext_d_T_2, 2)
node _signext_d_T_4 = bits(_signext_d_T_3, 7, 0)
node _signext_d_T_5 = or(_signext_d_T_2, _signext_d_T_4)
node _signext_d_T_6 = shl(_signext_d_T_5, 4)
node _signext_d_T_7 = bits(_signext_d_T_6, 7, 0)
node _signext_d_T_8 = or(_signext_d_T_5, _signext_d_T_7)
node _signext_d_T_9 = bits(_signext_d_T_8, 7, 0)
node _signext_d_T_10 = bits(_signext_d_T_9, 0, 0)
node _signext_d_T_11 = bits(_signext_d_T_9, 1, 1)
node _signext_d_T_12 = bits(_signext_d_T_9, 2, 2)
node _signext_d_T_13 = bits(_signext_d_T_9, 3, 3)
node _signext_d_T_14 = bits(_signext_d_T_9, 4, 4)
node _signext_d_T_15 = bits(_signext_d_T_9, 5, 5)
node _signext_d_T_16 = bits(_signext_d_T_9, 6, 6)
node _signext_d_T_17 = bits(_signext_d_T_9, 7, 7)
node _signext_d_T_18 = mux(_signext_d_T_10, UInt<8>(0hff), UInt<8>(0h0))
node _signext_d_T_19 = mux(_signext_d_T_11, UInt<8>(0hff), UInt<8>(0h0))
node _signext_d_T_20 = mux(_signext_d_T_12, UInt<8>(0hff), UInt<8>(0h0))
node _signext_d_T_21 = mux(_signext_d_T_13, UInt<8>(0hff), UInt<8>(0h0))
node _signext_d_T_22 = mux(_signext_d_T_14, UInt<8>(0hff), UInt<8>(0h0))
node _signext_d_T_23 = mux(_signext_d_T_15, UInt<8>(0hff), UInt<8>(0h0))
node _signext_d_T_24 = mux(_signext_d_T_16, UInt<8>(0hff), UInt<8>(0h0))
node _signext_d_T_25 = mux(_signext_d_T_17, UInt<8>(0hff), UInt<8>(0h0))
node signext_d_lo_lo = cat(_signext_d_T_19, _signext_d_T_18)
node signext_d_lo_hi = cat(_signext_d_T_21, _signext_d_T_20)
node signext_d_lo = cat(signext_d_lo_hi, signext_d_lo_lo)
node signext_d_hi_lo = cat(_signext_d_T_23, _signext_d_T_22)
node signext_d_hi_hi = cat(_signext_d_T_25, _signext_d_T_24)
node signext_d_hi = cat(signext_d_hi_hi, signext_d_hi_lo)
node signext_d = cat(signext_d_hi, signext_d_lo)
node _wide_mask_T = bits(cam_a[0].bits.mask, 0, 0)
node _wide_mask_T_1 = bits(cam_a[0].bits.mask, 1, 1)
node _wide_mask_T_2 = bits(cam_a[0].bits.mask, 2, 2)
node _wide_mask_T_3 = bits(cam_a[0].bits.mask, 3, 3)
node _wide_mask_T_4 = bits(cam_a[0].bits.mask, 4, 4)
node _wide_mask_T_5 = bits(cam_a[0].bits.mask, 5, 5)
node _wide_mask_T_6 = bits(cam_a[0].bits.mask, 6, 6)
node _wide_mask_T_7 = bits(cam_a[0].bits.mask, 7, 7)
node _wide_mask_T_8 = mux(_wide_mask_T, UInt<8>(0hff), UInt<8>(0h0))
node _wide_mask_T_9 = mux(_wide_mask_T_1, UInt<8>(0hff), UInt<8>(0h0))
node _wide_mask_T_10 = mux(_wide_mask_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _wide_mask_T_11 = mux(_wide_mask_T_3, UInt<8>(0hff), UInt<8>(0h0))
node _wide_mask_T_12 = mux(_wide_mask_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _wide_mask_T_13 = mux(_wide_mask_T_5, UInt<8>(0hff), UInt<8>(0h0))
node _wide_mask_T_14 = mux(_wide_mask_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _wide_mask_T_15 = mux(_wide_mask_T_7, UInt<8>(0hff), UInt<8>(0h0))
node wide_mask_lo_lo = cat(_wide_mask_T_9, _wide_mask_T_8)
node wide_mask_lo_hi = cat(_wide_mask_T_11, _wide_mask_T_10)
node wide_mask_lo = cat(wide_mask_lo_hi, wide_mask_lo_lo)
node wide_mask_hi_lo = cat(_wide_mask_T_13, _wide_mask_T_12)
node wide_mask_hi_hi = cat(_wide_mask_T_15, _wide_mask_T_14)
node wide_mask_hi = cat(wide_mask_hi_hi, wide_mask_hi_lo)
node wide_mask = cat(wide_mask_hi, wide_mask_lo)
node _a_a_ext_T = and(cam_a[0].bits.data, wide_mask)
node a_a_ext = or(_a_a_ext_T, signext_a)
node _a_d_ext_T = and(cam_d[0].data, wide_mask)
node a_d_ext = or(_a_d_ext_T, signext_d)
node _a_d_inv_T = not(a_d_ext)
node a_d_inv = mux(adder, a_d_ext, _a_d_inv_T)
node _adder_out_T = add(a_a_ext, a_d_inv)
node adder_out = tail(_adder_out_T, 1)
node _a_bigger_uneq_T = bits(a_a_ext, 63, 63)
node a_bigger_uneq = eq(unsigned, _a_bigger_uneq_T)
node _a_bigger_T = bits(a_a_ext, 63, 63)
node _a_bigger_T_1 = bits(a_d_ext, 63, 63)
node _a_bigger_T_2 = eq(_a_bigger_T, _a_bigger_T_1)
node _a_bigger_T_3 = bits(adder_out, 63, 63)
node _a_bigger_T_4 = eq(_a_bigger_T_3, UInt<1>(0h0))
node a_bigger = mux(_a_bigger_T_2, _a_bigger_T_4, a_bigger_uneq)
node pick_a = eq(take_max, a_bigger)
node _arith_out_T = mux(pick_a, cam_a[0].bits.data, cam_d[0].data)
node arith_out = mux(adder, adder_out, _arith_out_T)
node _amo_data_T = bits(cam_a[0].bits.opcode, 0, 0)
node amo_data = mux(_amo_data_T, logic_out, arith_out)
wire source_i : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
node _a_allow_T = eq(a_cam_busy, UInt<1>(0h0))
node _a_allow_T_1 = or(a_isSupported, cam_free_0)
node a_allow = and(_a_allow_T, _a_allow_T_1)
node _nodeIn_a_ready_T = and(source_i.ready, a_allow)
connect nodeIn.a.ready, _nodeIn_a_ready_T
node _source_i_valid_T = and(nodeIn.a.valid, a_allow)
connect source_i.valid, _source_i_valid_T
connect source_i.bits, nodeIn.a.bits
node _T = eq(a_isSupported, UInt<1>(0h0))
when _T :
connect source_i.bits.opcode, UInt<3>(0h4)
connect source_i.bits.param, UInt<1>(0h0)
wire source_c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect source_c.valid, cam_amo_0
node _source_c_bits_T = or(cam_a[0].bits.corrupt, cam_d[0].corrupt)
node _source_c_bits_legal_T = leq(UInt<1>(0h0), cam_a[0].bits.size)
node _source_c_bits_legal_T_1 = leq(cam_a[0].bits.size, UInt<4>(0hc))
node _source_c_bits_legal_T_2 = and(_source_c_bits_legal_T, _source_c_bits_legal_T_1)
node _source_c_bits_legal_T_3 = or(UInt<1>(0h0), _source_c_bits_legal_T_2)
node _source_c_bits_legal_T_4 = xor(cam_a[0].bits.address, UInt<14>(0h3000))
node _source_c_bits_legal_T_5 = cvt(_source_c_bits_legal_T_4)
node _source_c_bits_legal_T_6 = and(_source_c_bits_legal_T_5, asSInt(UInt<30>(0h1a113000)))
node _source_c_bits_legal_T_7 = asSInt(_source_c_bits_legal_T_6)
node _source_c_bits_legal_T_8 = eq(_source_c_bits_legal_T_7, asSInt(UInt<1>(0h0)))
node _source_c_bits_legal_T_9 = and(_source_c_bits_legal_T_3, _source_c_bits_legal_T_8)
node _source_c_bits_legal_T_10 = leq(UInt<1>(0h0), cam_a[0].bits.size)
node _source_c_bits_legal_T_11 = leq(cam_a[0].bits.size, UInt<3>(0h6))
node _source_c_bits_legal_T_12 = and(_source_c_bits_legal_T_10, _source_c_bits_legal_T_11)
node _source_c_bits_legal_T_13 = or(UInt<1>(0h0), _source_c_bits_legal_T_12)
node _source_c_bits_legal_T_14 = xor(cam_a[0].bits.address, UInt<1>(0h0))
node _source_c_bits_legal_T_15 = cvt(_source_c_bits_legal_T_14)
node _source_c_bits_legal_T_16 = and(_source_c_bits_legal_T_15, asSInt(UInt<30>(0h1a112000)))
node _source_c_bits_legal_T_17 = asSInt(_source_c_bits_legal_T_16)
node _source_c_bits_legal_T_18 = eq(_source_c_bits_legal_T_17, asSInt(UInt<1>(0h0)))
node _source_c_bits_legal_T_19 = xor(cam_a[0].bits.address, UInt<21>(0h100000))
node _source_c_bits_legal_T_20 = cvt(_source_c_bits_legal_T_19)
node _source_c_bits_legal_T_21 = and(_source_c_bits_legal_T_20, asSInt(UInt<30>(0h1a103000)))
node _source_c_bits_legal_T_22 = asSInt(_source_c_bits_legal_T_21)
node _source_c_bits_legal_T_23 = eq(_source_c_bits_legal_T_22, asSInt(UInt<1>(0h0)))
node _source_c_bits_legal_T_24 = xor(cam_a[0].bits.address, UInt<26>(0h2000000))
node _source_c_bits_legal_T_25 = cvt(_source_c_bits_legal_T_24)
node _source_c_bits_legal_T_26 = and(_source_c_bits_legal_T_25, asSInt(UInt<30>(0h1a110000)))
node _source_c_bits_legal_T_27 = asSInt(_source_c_bits_legal_T_26)
node _source_c_bits_legal_T_28 = eq(_source_c_bits_legal_T_27, asSInt(UInt<1>(0h0)))
node _source_c_bits_legal_T_29 = xor(cam_a[0].bits.address, UInt<26>(0h2010000))
node _source_c_bits_legal_T_30 = cvt(_source_c_bits_legal_T_29)
node _source_c_bits_legal_T_31 = and(_source_c_bits_legal_T_30, asSInt(UInt<30>(0h1a113000)))
node _source_c_bits_legal_T_32 = asSInt(_source_c_bits_legal_T_31)
node _source_c_bits_legal_T_33 = eq(_source_c_bits_legal_T_32, asSInt(UInt<1>(0h0)))
node _source_c_bits_legal_T_34 = xor(cam_a[0].bits.address, UInt<28>(0h8000000))
node _source_c_bits_legal_T_35 = cvt(_source_c_bits_legal_T_34)
node _source_c_bits_legal_T_36 = and(_source_c_bits_legal_T_35, asSInt(UInt<30>(0h18000000)))
node _source_c_bits_legal_T_37 = asSInt(_source_c_bits_legal_T_36)
node _source_c_bits_legal_T_38 = eq(_source_c_bits_legal_T_37, asSInt(UInt<1>(0h0)))
node _source_c_bits_legal_T_39 = xor(cam_a[0].bits.address, UInt<29>(0h10000000))
node _source_c_bits_legal_T_40 = cvt(_source_c_bits_legal_T_39)
node _source_c_bits_legal_T_41 = and(_source_c_bits_legal_T_40, asSInt(UInt<30>(0h1a113000)))
node _source_c_bits_legal_T_42 = asSInt(_source_c_bits_legal_T_41)
node _source_c_bits_legal_T_43 = eq(_source_c_bits_legal_T_42, asSInt(UInt<1>(0h0)))
node _source_c_bits_legal_T_44 = or(_source_c_bits_legal_T_18, _source_c_bits_legal_T_23)
node _source_c_bits_legal_T_45 = or(_source_c_bits_legal_T_44, _source_c_bits_legal_T_28)
node _source_c_bits_legal_T_46 = or(_source_c_bits_legal_T_45, _source_c_bits_legal_T_33)
node _source_c_bits_legal_T_47 = or(_source_c_bits_legal_T_46, _source_c_bits_legal_T_38)
node _source_c_bits_legal_T_48 = or(_source_c_bits_legal_T_47, _source_c_bits_legal_T_43)
node _source_c_bits_legal_T_49 = and(_source_c_bits_legal_T_13, _source_c_bits_legal_T_48)
node _source_c_bits_legal_T_50 = or(UInt<1>(0h0), UInt<1>(0h0))
node _source_c_bits_legal_T_51 = xor(cam_a[0].bits.address, UInt<17>(0h10000))
node _source_c_bits_legal_T_52 = cvt(_source_c_bits_legal_T_51)
node _source_c_bits_legal_T_53 = and(_source_c_bits_legal_T_52, asSInt(UInt<30>(0h1a110000)))
node _source_c_bits_legal_T_54 = asSInt(_source_c_bits_legal_T_53)
node _source_c_bits_legal_T_55 = eq(_source_c_bits_legal_T_54, asSInt(UInt<1>(0h0)))
node _source_c_bits_legal_T_56 = and(_source_c_bits_legal_T_50, _source_c_bits_legal_T_55)
node _source_c_bits_legal_T_57 = or(UInt<1>(0h0), _source_c_bits_legal_T_9)
node _source_c_bits_legal_T_58 = or(_source_c_bits_legal_T_57, _source_c_bits_legal_T_49)
node source_c_bits_legal = or(_source_c_bits_legal_T_58, _source_c_bits_legal_T_56)
wire source_c_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect source_c_bits_a.opcode, UInt<1>(0h0)
connect source_c_bits_a.param, UInt<1>(0h0)
connect source_c_bits_a.size, cam_a[0].bits.size
connect source_c_bits_a.source, cam_a[0].bits.source
connect source_c_bits_a.address, cam_a[0].bits.address
node _source_c_bits_a_mask_sizeOH_T = or(cam_a[0].bits.size, UInt<3>(0h0))
node source_c_bits_a_mask_sizeOH_shiftAmount = bits(_source_c_bits_a_mask_sizeOH_T, 1, 0)
node _source_c_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), source_c_bits_a_mask_sizeOH_shiftAmount)
node _source_c_bits_a_mask_sizeOH_T_2 = bits(_source_c_bits_a_mask_sizeOH_T_1, 2, 0)
node source_c_bits_a_mask_sizeOH = or(_source_c_bits_a_mask_sizeOH_T_2, UInt<1>(0h1))
node source_c_bits_a_mask_sub_sub_sub_0_1 = geq(cam_a[0].bits.size, UInt<2>(0h3))
node source_c_bits_a_mask_sub_sub_size = bits(source_c_bits_a_mask_sizeOH, 2, 2)
node source_c_bits_a_mask_sub_sub_bit = bits(cam_a[0].bits.address, 2, 2)
node source_c_bits_a_mask_sub_sub_nbit = eq(source_c_bits_a_mask_sub_sub_bit, UInt<1>(0h0))
node source_c_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), source_c_bits_a_mask_sub_sub_nbit)
node _source_c_bits_a_mask_sub_sub_acc_T = and(source_c_bits_a_mask_sub_sub_size, source_c_bits_a_mask_sub_sub_0_2)
node source_c_bits_a_mask_sub_sub_0_1 = or(source_c_bits_a_mask_sub_sub_sub_0_1, _source_c_bits_a_mask_sub_sub_acc_T)
node source_c_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), source_c_bits_a_mask_sub_sub_bit)
node _source_c_bits_a_mask_sub_sub_acc_T_1 = and(source_c_bits_a_mask_sub_sub_size, source_c_bits_a_mask_sub_sub_1_2)
node source_c_bits_a_mask_sub_sub_1_1 = or(source_c_bits_a_mask_sub_sub_sub_0_1, _source_c_bits_a_mask_sub_sub_acc_T_1)
node source_c_bits_a_mask_sub_size = bits(source_c_bits_a_mask_sizeOH, 1, 1)
node source_c_bits_a_mask_sub_bit = bits(cam_a[0].bits.address, 1, 1)
node source_c_bits_a_mask_sub_nbit = eq(source_c_bits_a_mask_sub_bit, UInt<1>(0h0))
node source_c_bits_a_mask_sub_0_2 = and(source_c_bits_a_mask_sub_sub_0_2, source_c_bits_a_mask_sub_nbit)
node _source_c_bits_a_mask_sub_acc_T = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_0_2)
node source_c_bits_a_mask_sub_0_1 = or(source_c_bits_a_mask_sub_sub_0_1, _source_c_bits_a_mask_sub_acc_T)
node source_c_bits_a_mask_sub_1_2 = and(source_c_bits_a_mask_sub_sub_0_2, source_c_bits_a_mask_sub_bit)
node _source_c_bits_a_mask_sub_acc_T_1 = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_1_2)
node source_c_bits_a_mask_sub_1_1 = or(source_c_bits_a_mask_sub_sub_0_1, _source_c_bits_a_mask_sub_acc_T_1)
node source_c_bits_a_mask_sub_2_2 = and(source_c_bits_a_mask_sub_sub_1_2, source_c_bits_a_mask_sub_nbit)
node _source_c_bits_a_mask_sub_acc_T_2 = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_2_2)
node source_c_bits_a_mask_sub_2_1 = or(source_c_bits_a_mask_sub_sub_1_1, _source_c_bits_a_mask_sub_acc_T_2)
node source_c_bits_a_mask_sub_3_2 = and(source_c_bits_a_mask_sub_sub_1_2, source_c_bits_a_mask_sub_bit)
node _source_c_bits_a_mask_sub_acc_T_3 = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_3_2)
node source_c_bits_a_mask_sub_3_1 = or(source_c_bits_a_mask_sub_sub_1_1, _source_c_bits_a_mask_sub_acc_T_3)
node source_c_bits_a_mask_size = bits(source_c_bits_a_mask_sizeOH, 0, 0)
node source_c_bits_a_mask_bit = bits(cam_a[0].bits.address, 0, 0)
node source_c_bits_a_mask_nbit = eq(source_c_bits_a_mask_bit, UInt<1>(0h0))
node source_c_bits_a_mask_eq = and(source_c_bits_a_mask_sub_0_2, source_c_bits_a_mask_nbit)
node _source_c_bits_a_mask_acc_T = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq)
node source_c_bits_a_mask_acc = or(source_c_bits_a_mask_sub_0_1, _source_c_bits_a_mask_acc_T)
node source_c_bits_a_mask_eq_1 = and(source_c_bits_a_mask_sub_0_2, source_c_bits_a_mask_bit)
node _source_c_bits_a_mask_acc_T_1 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_1)
node source_c_bits_a_mask_acc_1 = or(source_c_bits_a_mask_sub_0_1, _source_c_bits_a_mask_acc_T_1)
node source_c_bits_a_mask_eq_2 = and(source_c_bits_a_mask_sub_1_2, source_c_bits_a_mask_nbit)
node _source_c_bits_a_mask_acc_T_2 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_2)
node source_c_bits_a_mask_acc_2 = or(source_c_bits_a_mask_sub_1_1, _source_c_bits_a_mask_acc_T_2)
node source_c_bits_a_mask_eq_3 = and(source_c_bits_a_mask_sub_1_2, source_c_bits_a_mask_bit)
node _source_c_bits_a_mask_acc_T_3 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_3)
node source_c_bits_a_mask_acc_3 = or(source_c_bits_a_mask_sub_1_1, _source_c_bits_a_mask_acc_T_3)
node source_c_bits_a_mask_eq_4 = and(source_c_bits_a_mask_sub_2_2, source_c_bits_a_mask_nbit)
node _source_c_bits_a_mask_acc_T_4 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_4)
node source_c_bits_a_mask_acc_4 = or(source_c_bits_a_mask_sub_2_1, _source_c_bits_a_mask_acc_T_4)
node source_c_bits_a_mask_eq_5 = and(source_c_bits_a_mask_sub_2_2, source_c_bits_a_mask_bit)
node _source_c_bits_a_mask_acc_T_5 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_5)
node source_c_bits_a_mask_acc_5 = or(source_c_bits_a_mask_sub_2_1, _source_c_bits_a_mask_acc_T_5)
node source_c_bits_a_mask_eq_6 = and(source_c_bits_a_mask_sub_3_2, source_c_bits_a_mask_nbit)
node _source_c_bits_a_mask_acc_T_6 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_6)
node source_c_bits_a_mask_acc_6 = or(source_c_bits_a_mask_sub_3_1, _source_c_bits_a_mask_acc_T_6)
node source_c_bits_a_mask_eq_7 = and(source_c_bits_a_mask_sub_3_2, source_c_bits_a_mask_bit)
node _source_c_bits_a_mask_acc_T_7 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_7)
node source_c_bits_a_mask_acc_7 = or(source_c_bits_a_mask_sub_3_1, _source_c_bits_a_mask_acc_T_7)
node source_c_bits_a_mask_lo_lo = cat(source_c_bits_a_mask_acc_1, source_c_bits_a_mask_acc)
node source_c_bits_a_mask_lo_hi = cat(source_c_bits_a_mask_acc_3, source_c_bits_a_mask_acc_2)
node source_c_bits_a_mask_lo = cat(source_c_bits_a_mask_lo_hi, source_c_bits_a_mask_lo_lo)
node source_c_bits_a_mask_hi_lo = cat(source_c_bits_a_mask_acc_5, source_c_bits_a_mask_acc_4)
node source_c_bits_a_mask_hi_hi = cat(source_c_bits_a_mask_acc_7, source_c_bits_a_mask_acc_6)
node source_c_bits_a_mask_hi = cat(source_c_bits_a_mask_hi_hi, source_c_bits_a_mask_hi_lo)
node _source_c_bits_a_mask_T = cat(source_c_bits_a_mask_hi, source_c_bits_a_mask_lo)
connect source_c_bits_a.mask, _source_c_bits_a_mask_T
connect source_c_bits_a.data, amo_data
connect source_c_bits_a.corrupt, _source_c_bits_T
connect source_c.bits, source_c_bits_a
node _decode_T = dshl(UInt<12>(0hfff), nodeIn.a.bits.size)
node _decode_T_1 = bits(_decode_T, 11, 0)
node _decode_T_2 = not(_decode_T_1)
node decode = shr(_decode_T_2, 3)
node _opdata_T = bits(nodeIn.a.bits.opcode, 2, 2)
node opdata = eq(_opdata_T, UInt<1>(0h0))
node _T_1 = mux(opdata, decode, UInt<1>(0h0))
regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0)
node idle = eq(beatsLeft, UInt<1>(0h0))
node latch = and(idle, nodeOut.a.ready)
node _readys_T = cat(source_i.valid, source_c.valid)
node _readys_T_1 = shl(_readys_T, 1)
node _readys_T_2 = bits(_readys_T_1, 1, 0)
node _readys_T_3 = or(_readys_T, _readys_T_2)
node _readys_T_4 = bits(_readys_T_3, 1, 0)
node _readys_T_5 = shl(_readys_T_4, 1)
node _readys_T_6 = bits(_readys_T_5, 1, 0)
node _readys_T_7 = not(_readys_T_6)
node _readys_T_8 = bits(_readys_T_7, 0, 0)
node _readys_T_9 = bits(_readys_T_7, 1, 1)
wire readys : UInt<1>[2]
connect readys[0], _readys_T_8
connect readys[1], _readys_T_9
node _winner_T = and(readys[0], source_c.valid)
node _winner_T_1 = and(readys[1], source_i.valid)
wire winner : UInt<1>[2]
connect winner[0], _winner_T
connect winner[1], _winner_T_1
node prefixOR_1 = or(UInt<1>(0h0), winner[0])
node _prefixOR_T = or(prefixOR_1, winner[1])
node _T_2 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_3 = eq(winner[0], UInt<1>(0h0))
node _T_4 = or(_T_2, _T_3)
node _T_5 = eq(prefixOR_1, UInt<1>(0h0))
node _T_6 = eq(winner[1], UInt<1>(0h0))
node _T_7 = or(_T_5, _T_6)
node _T_8 = and(_T_4, _T_7)
node _T_9 = asUInt(reset)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
node _T_11 = eq(_T_8, UInt<1>(0h0))
when _T_11 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf
assert(clock, _T_8, UInt<1>(0h1), "") : assert
node _T_12 = or(source_c.valid, source_i.valid)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = or(winner[0], winner[1])
node _T_15 = or(_T_13, _T_14)
node _T_16 = asUInt(reset)
node _T_17 = eq(_T_16, UInt<1>(0h0))
when _T_17 :
node _T_18 = eq(_T_15, UInt<1>(0h0))
when _T_18 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1
assert(clock, _T_15, UInt<1>(0h1), "") : assert_1
node maskedBeats_0 = mux(winner[0], UInt<1>(0h0), UInt<1>(0h0))
node maskedBeats_1 = mux(winner[1], _T_1, UInt<1>(0h0))
node initBeats = or(maskedBeats_0, maskedBeats_1)
node _beatsLeft_T = and(nodeOut.a.ready, nodeOut.a.valid)
node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T)
node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1)
node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2)
connect beatsLeft, _beatsLeft_T_3
wire _state_WIRE : UInt<1>[2]
connect _state_WIRE[0], UInt<1>(0h0)
connect _state_WIRE[1], UInt<1>(0h0)
regreset state : UInt<1>[2], clock, reset, _state_WIRE
node muxState = mux(idle, winner, state)
connect state, muxState
node allowed = mux(idle, readys, state)
node _source_c_ready_T = and(nodeOut.a.ready, allowed[0])
connect source_c.ready, _source_c_ready_T
node _source_i_ready_T = and(nodeOut.a.ready, allowed[1])
connect source_i.ready, _source_i_ready_T
node _nodeOut_a_valid_T = or(source_c.valid, source_i.valid)
node _nodeOut_a_valid_T_1 = mux(state[0], source_c.valid, UInt<1>(0h0))
node _nodeOut_a_valid_T_2 = mux(state[1], source_i.valid, UInt<1>(0h0))
node _nodeOut_a_valid_T_3 = or(_nodeOut_a_valid_T_1, _nodeOut_a_valid_T_2)
wire _nodeOut_a_valid_WIRE : UInt<1>
connect _nodeOut_a_valid_WIRE, _nodeOut_a_valid_T_3
node _nodeOut_a_valid_T_4 = mux(idle, _nodeOut_a_valid_T, _nodeOut_a_valid_WIRE)
connect nodeOut.a.valid, _nodeOut_a_valid_T_4
wire _nodeOut_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
node _nodeOut_a_bits_T = mux(muxState[0], source_c.bits.corrupt, UInt<1>(0h0))
node _nodeOut_a_bits_T_1 = mux(muxState[1], source_i.bits.corrupt, UInt<1>(0h0))
node _nodeOut_a_bits_T_2 = or(_nodeOut_a_bits_T, _nodeOut_a_bits_T_1)
wire _nodeOut_a_bits_WIRE_1 : UInt<1>
connect _nodeOut_a_bits_WIRE_1, _nodeOut_a_bits_T_2
connect _nodeOut_a_bits_WIRE.corrupt, _nodeOut_a_bits_WIRE_1
node _nodeOut_a_bits_T_3 = mux(muxState[0], source_c.bits.data, UInt<1>(0h0))
node _nodeOut_a_bits_T_4 = mux(muxState[1], source_i.bits.data, UInt<1>(0h0))
node _nodeOut_a_bits_T_5 = or(_nodeOut_a_bits_T_3, _nodeOut_a_bits_T_4)
wire _nodeOut_a_bits_WIRE_2 : UInt<64>
connect _nodeOut_a_bits_WIRE_2, _nodeOut_a_bits_T_5
connect _nodeOut_a_bits_WIRE.data, _nodeOut_a_bits_WIRE_2
node _nodeOut_a_bits_T_6 = mux(muxState[0], source_c.bits.mask, UInt<1>(0h0))
node _nodeOut_a_bits_T_7 = mux(muxState[1], source_i.bits.mask, UInt<1>(0h0))
node _nodeOut_a_bits_T_8 = or(_nodeOut_a_bits_T_6, _nodeOut_a_bits_T_7)
wire _nodeOut_a_bits_WIRE_3 : UInt<8>
connect _nodeOut_a_bits_WIRE_3, _nodeOut_a_bits_T_8
connect _nodeOut_a_bits_WIRE.mask, _nodeOut_a_bits_WIRE_3
wire _nodeOut_a_bits_WIRE_4 : { }
connect _nodeOut_a_bits_WIRE.echo, _nodeOut_a_bits_WIRE_4
wire _nodeOut_a_bits_WIRE_5 : { }
connect _nodeOut_a_bits_WIRE.user, _nodeOut_a_bits_WIRE_5
node _nodeOut_a_bits_T_9 = mux(muxState[0], source_c.bits.address, UInt<1>(0h0))
node _nodeOut_a_bits_T_10 = mux(muxState[1], source_i.bits.address, UInt<1>(0h0))
node _nodeOut_a_bits_T_11 = or(_nodeOut_a_bits_T_9, _nodeOut_a_bits_T_10)
wire _nodeOut_a_bits_WIRE_6 : UInt<29>
connect _nodeOut_a_bits_WIRE_6, _nodeOut_a_bits_T_11
connect _nodeOut_a_bits_WIRE.address, _nodeOut_a_bits_WIRE_6
node _nodeOut_a_bits_T_12 = mux(muxState[0], source_c.bits.source, UInt<1>(0h0))
node _nodeOut_a_bits_T_13 = mux(muxState[1], source_i.bits.source, UInt<1>(0h0))
node _nodeOut_a_bits_T_14 = or(_nodeOut_a_bits_T_12, _nodeOut_a_bits_T_13)
wire _nodeOut_a_bits_WIRE_7 : UInt<9>
connect _nodeOut_a_bits_WIRE_7, _nodeOut_a_bits_T_14
connect _nodeOut_a_bits_WIRE.source, _nodeOut_a_bits_WIRE_7
node _nodeOut_a_bits_T_15 = mux(muxState[0], source_c.bits.size, UInt<1>(0h0))
node _nodeOut_a_bits_T_16 = mux(muxState[1], source_i.bits.size, UInt<1>(0h0))
node _nodeOut_a_bits_T_17 = or(_nodeOut_a_bits_T_15, _nodeOut_a_bits_T_16)
wire _nodeOut_a_bits_WIRE_8 : UInt<4>
connect _nodeOut_a_bits_WIRE_8, _nodeOut_a_bits_T_17
connect _nodeOut_a_bits_WIRE.size, _nodeOut_a_bits_WIRE_8
node _nodeOut_a_bits_T_18 = mux(muxState[0], source_c.bits.param, UInt<1>(0h0))
node _nodeOut_a_bits_T_19 = mux(muxState[1], source_i.bits.param, UInt<1>(0h0))
node _nodeOut_a_bits_T_20 = or(_nodeOut_a_bits_T_18, _nodeOut_a_bits_T_19)
wire _nodeOut_a_bits_WIRE_9 : UInt<3>
connect _nodeOut_a_bits_WIRE_9, _nodeOut_a_bits_T_20
connect _nodeOut_a_bits_WIRE.param, _nodeOut_a_bits_WIRE_9
node _nodeOut_a_bits_T_21 = mux(muxState[0], source_c.bits.opcode, UInt<1>(0h0))
node _nodeOut_a_bits_T_22 = mux(muxState[1], source_i.bits.opcode, UInt<1>(0h0))
node _nodeOut_a_bits_T_23 = or(_nodeOut_a_bits_T_21, _nodeOut_a_bits_T_22)
wire _nodeOut_a_bits_WIRE_10 : UInt<3>
connect _nodeOut_a_bits_WIRE_10, _nodeOut_a_bits_T_23
connect _nodeOut_a_bits_WIRE.opcode, _nodeOut_a_bits_WIRE_10
connect nodeOut.a.bits.corrupt, _nodeOut_a_bits_WIRE.corrupt
connect nodeOut.a.bits.data, _nodeOut_a_bits_WIRE.data
connect nodeOut.a.bits.mask, _nodeOut_a_bits_WIRE.mask
connect nodeOut.a.bits.address, _nodeOut_a_bits_WIRE.address
connect nodeOut.a.bits.source, _nodeOut_a_bits_WIRE.source
connect nodeOut.a.bits.size, _nodeOut_a_bits_WIRE.size
connect nodeOut.a.bits.param, _nodeOut_a_bits_WIRE.param
connect nodeOut.a.bits.opcode, _nodeOut_a_bits_WIRE.opcode
node _T_19 = and(source_i.ready, source_i.valid)
node _T_20 = eq(a_isSupported, UInt<1>(0h0))
node _T_21 = and(_T_19, _T_20)
when _T_21 :
when a_cam_sel_free_0 :
connect cam_a[0].fifoId, UInt<1>(0h0)
connect cam_a[0].bits, nodeIn.a.bits
node _cam_a_0_lut_T = bits(nodeIn.a.bits.param, 1, 0)
node _cam_a_0_lut_T_1 = eq(UInt<3>(0h1), _cam_a_0_lut_T)
node _cam_a_0_lut_T_2 = mux(_cam_a_0_lut_T_1, UInt<4>(0he), UInt<4>(0h8))
node _cam_a_0_lut_T_3 = eq(UInt<3>(0h0), _cam_a_0_lut_T)
node _cam_a_0_lut_T_4 = mux(_cam_a_0_lut_T_3, UInt<3>(0h6), _cam_a_0_lut_T_2)
node _cam_a_0_lut_T_5 = eq(UInt<3>(0h3), _cam_a_0_lut_T)
node _cam_a_0_lut_T_6 = mux(_cam_a_0_lut_T_5, UInt<4>(0hc), _cam_a_0_lut_T_4)
connect cam_a[0].lut, _cam_a_0_lut_T_6
when a_cam_sel_free_0 :
connect cam_s[0].state, UInt<2>(0h3)
node _T_22 = and(source_c.ready, source_c.valid)
when _T_22 :
when a_cam_sel_put_0 :
connect cam_s[0].state, UInt<1>(0h1)
node _d_first_T = and(nodeOut.d.ready, nodeOut.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), nodeOut.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(nodeOut.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
node d_cam_sel_raw_0 = eq(cam_a[0].bits.source, nodeIn.d.bits.source)
node d_cam_sel_match_0 = and(d_cam_sel_raw_0, cam_dmatch_0)
node d_cam_sel_0 = mux(UInt<1>(0h0), a_cam_sel_free_0, d_cam_sel_match_0)
node d_cam_sel_any = or(UInt<1>(0h0), d_cam_sel_match_0)
node d_ackd = eq(nodeOut.d.bits.opcode, UInt<1>(0h1))
node d_ack = eq(nodeOut.d.bits.opcode, UInt<1>(0h0))
node _T_23 = and(nodeOut.d.ready, nodeOut.d.valid)
node _T_24 = and(_T_23, d_first)
when _T_24 :
node _T_25 = and(d_cam_sel_0, d_ackd)
when _T_25 :
connect cam_d[0].data, nodeOut.d.bits.data
connect cam_d[0].denied, nodeOut.d.bits.denied
connect cam_d[0].corrupt, nodeOut.d.bits.corrupt
when d_cam_sel_0 :
node _cam_s_0_state_T = mux(d_ackd, UInt<2>(0h2), UInt<1>(0h0))
connect cam_s[0].state, _cam_s_0_state_T
node _d_drop_T = and(d_first, d_ackd)
node d_drop = and(_d_drop_T, d_cam_sel_any)
node _d_replace_T = and(d_first, d_ack)
node d_replace = and(_d_replace_T, d_cam_sel_match_0)
node _nodeIn_d_valid_T = eq(d_drop, UInt<1>(0h0))
node _nodeIn_d_valid_T_1 = and(nodeOut.d.valid, _nodeIn_d_valid_T)
connect nodeIn.d.valid, _nodeIn_d_valid_T_1
node _nodeOut_d_ready_T = or(nodeIn.d.ready, d_drop)
connect nodeOut.d.ready, _nodeOut_d_ready_T
connect nodeIn.d.bits.corrupt, nodeOut.d.bits.corrupt
connect nodeIn.d.bits.data, nodeOut.d.bits.data
connect nodeIn.d.bits.denied, nodeOut.d.bits.denied
connect nodeIn.d.bits.sink, nodeOut.d.bits.sink
connect nodeIn.d.bits.source, nodeOut.d.bits.source
connect nodeIn.d.bits.size, nodeOut.d.bits.size
connect nodeIn.d.bits.param, nodeOut.d.bits.param
connect nodeIn.d.bits.opcode, nodeOut.d.bits.opcode
when d_replace :
connect nodeIn.d.bits.opcode, UInt<1>(0h1)
connect nodeIn.d.bits.data, cam_d[0].data
node _nodeIn_d_bits_corrupt_T = or(cam_d[0].corrupt, nodeOut.d.bits.denied)
connect nodeIn.d.bits.corrupt, _nodeIn_d_bits_corrupt_T
node _nodeIn_d_bits_denied_T = or(cam_d[0].denied, nodeOut.d.bits.denied)
connect nodeIn.d.bits.denied, _nodeIn_d_bits_denied_T
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<29>(0h0)
connect _WIRE.bits.source, UInt<9>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<29>(0h0)
connect _WIRE_2.bits.source, UInt<9>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<9>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<29>(0h0)
connect _WIRE_8.bits.source, UInt<9>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_10.bits.sink, UInt<1>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0)
extmodule plusarg_reader_44 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_45 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLAtomicAutomata_cbus( // @[AtomicAutomata.scala:36:9]
input clock, // @[AtomicAutomata.scala:36:9]
input reset, // @[AtomicAutomata.scala:36:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [8:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [8:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [8:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [8:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[AtomicAutomata.scala:36:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[AtomicAutomata.scala:36:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[AtomicAutomata.scala:36:9]
wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[AtomicAutomata.scala:36:9]
wire [8:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[AtomicAutomata.scala:36:9]
wire [28:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[AtomicAutomata.scala:36:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[AtomicAutomata.scala:36:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[AtomicAutomata.scala:36:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[AtomicAutomata.scala:36:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[AtomicAutomata.scala:36:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[AtomicAutomata.scala:36:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[AtomicAutomata.scala:36:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[AtomicAutomata.scala:36:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[AtomicAutomata.scala:36:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[AtomicAutomata.scala:36:9]
wire [8:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[AtomicAutomata.scala:36:9]
wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[AtomicAutomata.scala:36:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[AtomicAutomata.scala:36:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[AtomicAutomata.scala:36:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[AtomicAutomata.scala:36:9]
wire _a_canLogical_T = 1'h1; // @[Parameters.scala:92:28]
wire _a_canArithmetic_T = 1'h1; // @[Parameters.scala:92:28]
wire _a_cam_sel_put_T = 1'h1; // @[AtomicAutomata.scala:103:83]
wire _a_fifoId_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire _a_cam_busy_T = 1'h1; // @[AtomicAutomata.scala:111:60]
wire _a_cam_sel_free_T = 1'h1; // @[AtomicAutomata.scala:116:85]
wire _source_c_bits_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _source_c_bits_legal_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire _a_canLogical_T_16 = 1'h0; // @[Parameters.scala:684:29]
wire _a_canLogical_T_46 = 1'h0; // @[Parameters.scala:684:54]
wire _a_canArithmetic_T_16 = 1'h0; // @[Parameters.scala:684:29]
wire _a_canArithmetic_T_46 = 1'h0; // @[Parameters.scala:684:54]
wire _source_c_bits_legal_T_50 = 1'h0; // @[Parameters.scala:684:29]
wire _source_c_bits_legal_T_56 = 1'h0; // @[Parameters.scala:684:54]
wire maskedBeats_0 = 1'h0; // @[Arbiter.scala:82:69]
wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34]
wire [2:0] source_c_bits_opcode = 3'h0; // @[AtomicAutomata.scala:165:28]
wire [2:0] source_c_bits_param = 3'h0; // @[AtomicAutomata.scala:165:28]
wire [2:0] source_c_bits_a_opcode = 3'h0; // @[Edges.scala:480:17]
wire [2:0] source_c_bits_a_param = 3'h0; // @[Edges.scala:480:17]
wire [2:0] _nodeOut_a_bits_T_18 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_21 = 3'h0; // @[Mux.scala:30:73]
wire [29:0] _a_fifoId_T_2 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] _a_fifoId_T_3 = 30'h0; // @[Parameters.scala:137:46]
wire [1:0] initval_state = 2'h0; // @[AtomicAutomata.scala:80:27]
wire [1:0] _cam_s_WIRE_0_state = 2'h0; // @[AtomicAutomata.scala:82:50]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[AtomicAutomata.scala:36:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[AtomicAutomata.scala:36:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[AtomicAutomata.scala:36:9]
wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[AtomicAutomata.scala:36:9]
wire [8:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[AtomicAutomata.scala:36:9]
wire [28:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[AtomicAutomata.scala:36:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[AtomicAutomata.scala:36:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[AtomicAutomata.scala:36:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[AtomicAutomata.scala:36:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[AtomicAutomata.scala:36:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [8:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[AtomicAutomata.scala:36:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [8:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [28:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[AtomicAutomata.scala:36:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[AtomicAutomata.scala:36:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[AtomicAutomata.scala:36:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[AtomicAutomata.scala:36:9]
wire [8:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[AtomicAutomata.scala:36:9]
wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[AtomicAutomata.scala:36:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[AtomicAutomata.scala:36:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[AtomicAutomata.scala:36:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[AtomicAutomata.scala:36:9]
wire auto_in_a_ready_0; // @[AtomicAutomata.scala:36:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[AtomicAutomata.scala:36:9]
wire [1:0] auto_in_d_bits_param_0; // @[AtomicAutomata.scala:36:9]
wire [3:0] auto_in_d_bits_size_0; // @[AtomicAutomata.scala:36:9]
wire [8:0] auto_in_d_bits_source_0; // @[AtomicAutomata.scala:36:9]
wire auto_in_d_bits_sink_0; // @[AtomicAutomata.scala:36:9]
wire auto_in_d_bits_denied_0; // @[AtomicAutomata.scala:36:9]
wire [63:0] auto_in_d_bits_data_0; // @[AtomicAutomata.scala:36:9]
wire auto_in_d_bits_corrupt_0; // @[AtomicAutomata.scala:36:9]
wire auto_in_d_valid_0; // @[AtomicAutomata.scala:36:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[AtomicAutomata.scala:36:9]
wire [2:0] auto_out_a_bits_param_0; // @[AtomicAutomata.scala:36:9]
wire [3:0] auto_out_a_bits_size_0; // @[AtomicAutomata.scala:36:9]
wire [8:0] auto_out_a_bits_source_0; // @[AtomicAutomata.scala:36:9]
wire [28:0] auto_out_a_bits_address_0; // @[AtomicAutomata.scala:36:9]
wire [7:0] auto_out_a_bits_mask_0; // @[AtomicAutomata.scala:36:9]
wire [63:0] auto_out_a_bits_data_0; // @[AtomicAutomata.scala:36:9]
wire auto_out_a_bits_corrupt_0; // @[AtomicAutomata.scala:36:9]
wire auto_out_a_valid_0; // @[AtomicAutomata.scala:36:9]
wire auto_out_d_ready_0; // @[AtomicAutomata.scala:36:9]
wire _nodeIn_a_ready_T; // @[AtomicAutomata.scala:156:38]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[AtomicAutomata.scala:36:9]
wire [3:0] source_i_bits_size = nodeIn_a_bits_size; // @[AtomicAutomata.scala:154:28]
wire [8:0] source_i_bits_source = nodeIn_a_bits_source; // @[AtomicAutomata.scala:154:28]
wire [28:0] _a_canLogical_T_17 = nodeIn_a_bits_address; // @[Parameters.scala:137:31]
wire [28:0] _a_canArithmetic_T_17 = nodeIn_a_bits_address; // @[Parameters.scala:137:31]
wire [28:0] _a_fifoId_T = nodeIn_a_bits_address; // @[Parameters.scala:137:31]
wire [28:0] source_i_bits_address = nodeIn_a_bits_address; // @[AtomicAutomata.scala:154:28]
wire [7:0] source_i_bits_mask = nodeIn_a_bits_mask; // @[AtomicAutomata.scala:154:28]
wire [63:0] source_i_bits_data = nodeIn_a_bits_data; // @[AtomicAutomata.scala:154:28]
wire source_i_bits_corrupt = nodeIn_a_bits_corrupt; // @[AtomicAutomata.scala:154:28]
wire _nodeIn_d_valid_T_1; // @[AtomicAutomata.scala:241:35]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[AtomicAutomata.scala:36:9]
wire _nodeOut_a_valid_T_4; // @[Arbiter.scala:96:24]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[AtomicAutomata.scala:36:9]
wire [2:0] _nodeOut_a_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[AtomicAutomata.scala:36:9]
wire [2:0] _nodeOut_a_bits_WIRE_param; // @[Mux.scala:30:73]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[AtomicAutomata.scala:36:9]
wire [3:0] _nodeOut_a_bits_WIRE_size; // @[Mux.scala:30:73]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[AtomicAutomata.scala:36:9]
wire [8:0] _nodeOut_a_bits_WIRE_source; // @[Mux.scala:30:73]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[AtomicAutomata.scala:36:9]
wire [28:0] _nodeOut_a_bits_WIRE_address; // @[Mux.scala:30:73]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[AtomicAutomata.scala:36:9]
wire [7:0] _nodeOut_a_bits_WIRE_mask; // @[Mux.scala:30:73]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[AtomicAutomata.scala:36:9]
wire [63:0] _nodeOut_a_bits_WIRE_data; // @[Mux.scala:30:73]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[AtomicAutomata.scala:36:9]
wire _nodeOut_a_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[AtomicAutomata.scala:36:9]
wire _nodeOut_d_ready_T; // @[AtomicAutomata.scala:242:35]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[AtomicAutomata.scala:36:9]
assign nodeIn_d_bits_param = nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_size = nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_source = nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_sink = nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
reg [1:0] cam_s_0_state; // @[AtomicAutomata.scala:82:28]
reg [2:0] cam_a_0_bits_opcode; // @[AtomicAutomata.scala:83:24]
reg [2:0] cam_a_0_bits_param; // @[AtomicAutomata.scala:83:24]
reg [3:0] cam_a_0_bits_size; // @[AtomicAutomata.scala:83:24]
wire [3:0] source_c_bits_a_size = cam_a_0_bits_size; // @[Edges.scala:480:17]
wire [3:0] _source_c_bits_a_mask_sizeOH_T = cam_a_0_bits_size; // @[Misc.scala:202:34]
reg [8:0] cam_a_0_bits_source; // @[AtomicAutomata.scala:83:24]
wire [8:0] source_c_bits_a_source = cam_a_0_bits_source; // @[Edges.scala:480:17]
reg [28:0] cam_a_0_bits_address; // @[AtomicAutomata.scala:83:24]
wire [28:0] _source_c_bits_legal_T_14 = cam_a_0_bits_address; // @[AtomicAutomata.scala:83:24]
wire [28:0] source_c_bits_a_address = cam_a_0_bits_address; // @[Edges.scala:480:17]
reg [7:0] cam_a_0_bits_mask; // @[AtomicAutomata.scala:83:24]
reg [63:0] cam_a_0_bits_data; // @[AtomicAutomata.scala:83:24]
reg cam_a_0_bits_corrupt; // @[AtomicAutomata.scala:83:24]
reg [3:0] cam_a_0_lut; // @[AtomicAutomata.scala:83:24]
reg [63:0] cam_d_0_data; // @[AtomicAutomata.scala:84:24]
reg cam_d_0_denied; // @[AtomicAutomata.scala:84:24]
reg cam_d_0_corrupt; // @[AtomicAutomata.scala:84:24]
wire cam_free_0 = ~(|cam_s_0_state); // @[AtomicAutomata.scala:82:28, :86:44]
wire _a_cam_por_free_T = cam_free_0; // @[AtomicAutomata.scala:86:44, :115:58]
wire a_cam_sel_free_0 = cam_free_0; // @[AtomicAutomata.scala:86:44, :116:82]
wire _GEN = cam_s_0_state == 2'h2; // @[AtomicAutomata.scala:82:28, :87:44]
wire cam_amo_0; // @[AtomicAutomata.scala:87:44]
assign cam_amo_0 = _GEN; // @[AtomicAutomata.scala:87:44]
wire _cam_abusy_T_1; // @[AtomicAutomata.scala:88:68]
assign _cam_abusy_T_1 = _GEN; // @[AtomicAutomata.scala:87:44, :88:68]
wire _a_cam_por_put_T = cam_amo_0; // @[AtomicAutomata.scala:87:44, :102:56]
wire a_cam_sel_put_0 = cam_amo_0; // @[AtomicAutomata.scala:87:44, :103:80]
wire source_c_valid = cam_amo_0; // @[AtomicAutomata.scala:87:44, :165:28]
wire _cam_abusy_T = &cam_s_0_state; // @[AtomicAutomata.scala:82:28, :88:49]
wire cam_abusy_0 = _cam_abusy_T | _cam_abusy_T_1; // @[AtomicAutomata.scala:88:{49,57,68}]
wire a_cam_busy = cam_abusy_0; // @[AtomicAutomata.scala:88:57, :111:96]
wire cam_dmatch_0 = |cam_s_0_state; // @[AtomicAutomata.scala:82:28, :86:44, :89:49]
wire _GEN_0 = nodeIn_a_bits_size < 4'h4; // @[Parameters.scala:92:38]
wire _a_canLogical_T_1; // @[Parameters.scala:92:38]
assign _a_canLogical_T_1 = _GEN_0; // @[Parameters.scala:92:38]
wire _a_canArithmetic_T_1; // @[Parameters.scala:92:38]
assign _a_canArithmetic_T_1 = _GEN_0; // @[Parameters.scala:92:38]
wire _a_canLogical_T_2 = _a_canLogical_T_1; // @[Parameters.scala:92:{33,38}]
wire _a_canLogical_T_3 = _a_canLogical_T_2; // @[Parameters.scala:684:29]
wire [28:0] _GEN_1 = {nodeIn_a_bits_address[28:13], nodeIn_a_bits_address[12:0] ^ 13'h1000}; // @[Parameters.scala:137:31]
wire [28:0] _a_canLogical_T_4; // @[Parameters.scala:137:31]
assign _a_canLogical_T_4 = _GEN_1; // @[Parameters.scala:137:31]
wire [28:0] _a_canArithmetic_T_4; // @[Parameters.scala:137:31]
assign _a_canArithmetic_T_4 = _GEN_1; // @[Parameters.scala:137:31]
wire [29:0] _a_canLogical_T_5 = {1'h0, _a_canLogical_T_4}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canLogical_T_6 = _a_canLogical_T_5 & 30'h1A011000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canLogical_T_7 = _a_canLogical_T_6; // @[Parameters.scala:137:46]
wire _a_canLogical_T_8 = _a_canLogical_T_7 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] _GEN_2 = nodeIn_a_bits_address ^ 29'h10000000; // @[Parameters.scala:137:31]
wire [28:0] _a_canLogical_T_9; // @[Parameters.scala:137:31]
assign _a_canLogical_T_9 = _GEN_2; // @[Parameters.scala:137:31]
wire [28:0] _a_canArithmetic_T_9; // @[Parameters.scala:137:31]
assign _a_canArithmetic_T_9 = _GEN_2; // @[Parameters.scala:137:31]
wire [29:0] _a_canLogical_T_10 = {1'h0, _a_canLogical_T_9}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canLogical_T_11 = _a_canLogical_T_10 & 30'h1A011000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canLogical_T_12 = _a_canLogical_T_11; // @[Parameters.scala:137:46]
wire _a_canLogical_T_13 = _a_canLogical_T_12 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire _a_canLogical_T_14 = _a_canLogical_T_8 | _a_canLogical_T_13; // @[Parameters.scala:685:42]
wire _a_canLogical_T_15 = _a_canLogical_T_3 & _a_canLogical_T_14; // @[Parameters.scala:684:{29,54}, :685:42]
wire _a_canLogical_T_47 = _a_canLogical_T_15; // @[Parameters.scala:684:54, :686:26]
wire [29:0] _a_canLogical_T_18 = {1'h0, _a_canLogical_T_17}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canLogical_T_19 = _a_canLogical_T_18 & 30'h1A001000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canLogical_T_20 = _a_canLogical_T_19; // @[Parameters.scala:137:46]
wire _a_canLogical_T_21 = _a_canLogical_T_20 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] _GEN_3 = {nodeIn_a_bits_address[28:17], nodeIn_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31]
wire [28:0] _a_canLogical_T_22; // @[Parameters.scala:137:31]
assign _a_canLogical_T_22 = _GEN_3; // @[Parameters.scala:137:31]
wire [28:0] _a_canArithmetic_T_22; // @[Parameters.scala:137:31]
assign _a_canArithmetic_T_22 = _GEN_3; // @[Parameters.scala:137:31]
wire [29:0] _a_canLogical_T_23 = {1'h0, _a_canLogical_T_22}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canLogical_T_24 = _a_canLogical_T_23 & 30'h1A010000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canLogical_T_25 = _a_canLogical_T_24; // @[Parameters.scala:137:46]
wire _a_canLogical_T_26 = _a_canLogical_T_25 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] _GEN_4 = {nodeIn_a_bits_address[28:26], nodeIn_a_bits_address[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31]
wire [28:0] _a_canLogical_T_27; // @[Parameters.scala:137:31]
assign _a_canLogical_T_27 = _GEN_4; // @[Parameters.scala:137:31]
wire [28:0] _a_canArithmetic_T_27; // @[Parameters.scala:137:31]
assign _a_canArithmetic_T_27 = _GEN_4; // @[Parameters.scala:137:31]
wire [29:0] _a_canLogical_T_28 = {1'h0, _a_canLogical_T_27}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canLogical_T_29 = _a_canLogical_T_28 & 30'h1A010000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canLogical_T_30 = _a_canLogical_T_29; // @[Parameters.scala:137:46]
wire _a_canLogical_T_31 = _a_canLogical_T_30 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] _GEN_5 = {nodeIn_a_bits_address[28:26], nodeIn_a_bits_address[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31]
wire [28:0] _a_canLogical_T_32; // @[Parameters.scala:137:31]
assign _a_canLogical_T_32 = _GEN_5; // @[Parameters.scala:137:31]
wire [28:0] _a_canArithmetic_T_32; // @[Parameters.scala:137:31]
assign _a_canArithmetic_T_32 = _GEN_5; // @[Parameters.scala:137:31]
wire [29:0] _a_canLogical_T_33 = {1'h0, _a_canLogical_T_32}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canLogical_T_34 = _a_canLogical_T_33 & 30'h1A011000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canLogical_T_35 = _a_canLogical_T_34; // @[Parameters.scala:137:46]
wire _a_canLogical_T_36 = _a_canLogical_T_35 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] _GEN_6 = {nodeIn_a_bits_address[28], nodeIn_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31]
wire [28:0] _a_canLogical_T_37; // @[Parameters.scala:137:31]
assign _a_canLogical_T_37 = _GEN_6; // @[Parameters.scala:137:31]
wire [28:0] _a_canArithmetic_T_37; // @[Parameters.scala:137:31]
assign _a_canArithmetic_T_37 = _GEN_6; // @[Parameters.scala:137:31]
wire [29:0] _a_canLogical_T_38 = {1'h0, _a_canLogical_T_37}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canLogical_T_39 = _a_canLogical_T_38 & 30'h18000000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canLogical_T_40 = _a_canLogical_T_39; // @[Parameters.scala:137:46]
wire _a_canLogical_T_41 = _a_canLogical_T_40 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire _a_canLogical_T_42 = _a_canLogical_T_21 | _a_canLogical_T_26; // @[Parameters.scala:685:42]
wire _a_canLogical_T_43 = _a_canLogical_T_42 | _a_canLogical_T_31; // @[Parameters.scala:685:42]
wire _a_canLogical_T_44 = _a_canLogical_T_43 | _a_canLogical_T_36; // @[Parameters.scala:685:42]
wire _a_canLogical_T_45 = _a_canLogical_T_44 | _a_canLogical_T_41; // @[Parameters.scala:685:42]
wire _a_canLogical_T_48 = _a_canLogical_T_47; // @[Parameters.scala:686:26]
wire a_canLogical = _a_canLogical_T_48; // @[Parameters.scala:686:26]
wire _a_canArithmetic_T_2 = _a_canArithmetic_T_1; // @[Parameters.scala:92:{33,38}]
wire _a_canArithmetic_T_3 = _a_canArithmetic_T_2; // @[Parameters.scala:684:29]
wire [29:0] _a_canArithmetic_T_5 = {1'h0, _a_canArithmetic_T_4}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canArithmetic_T_6 = _a_canArithmetic_T_5 & 30'h1A011000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canArithmetic_T_7 = _a_canArithmetic_T_6; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_8 = _a_canArithmetic_T_7 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [29:0] _a_canArithmetic_T_10 = {1'h0, _a_canArithmetic_T_9}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canArithmetic_T_11 = _a_canArithmetic_T_10 & 30'h1A011000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canArithmetic_T_12 = _a_canArithmetic_T_11; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_13 = _a_canArithmetic_T_12 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire _a_canArithmetic_T_14 = _a_canArithmetic_T_8 | _a_canArithmetic_T_13; // @[Parameters.scala:685:42]
wire _a_canArithmetic_T_15 = _a_canArithmetic_T_3 & _a_canArithmetic_T_14; // @[Parameters.scala:684:{29,54}, :685:42]
wire _a_canArithmetic_T_47 = _a_canArithmetic_T_15; // @[Parameters.scala:684:54, :686:26]
wire [29:0] _a_canArithmetic_T_18 = {1'h0, _a_canArithmetic_T_17}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canArithmetic_T_19 = _a_canArithmetic_T_18 & 30'h1A001000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canArithmetic_T_20 = _a_canArithmetic_T_19; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_21 = _a_canArithmetic_T_20 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [29:0] _a_canArithmetic_T_23 = {1'h0, _a_canArithmetic_T_22}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canArithmetic_T_24 = _a_canArithmetic_T_23 & 30'h1A010000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canArithmetic_T_25 = _a_canArithmetic_T_24; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_26 = _a_canArithmetic_T_25 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [29:0] _a_canArithmetic_T_28 = {1'h0, _a_canArithmetic_T_27}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canArithmetic_T_29 = _a_canArithmetic_T_28 & 30'h1A010000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canArithmetic_T_30 = _a_canArithmetic_T_29; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_31 = _a_canArithmetic_T_30 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [29:0] _a_canArithmetic_T_33 = {1'h0, _a_canArithmetic_T_32}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canArithmetic_T_34 = _a_canArithmetic_T_33 & 30'h1A011000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canArithmetic_T_35 = _a_canArithmetic_T_34; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_36 = _a_canArithmetic_T_35 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [29:0] _a_canArithmetic_T_38 = {1'h0, _a_canArithmetic_T_37}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canArithmetic_T_39 = _a_canArithmetic_T_38 & 30'h18000000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canArithmetic_T_40 = _a_canArithmetic_T_39; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_41 = _a_canArithmetic_T_40 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire _a_canArithmetic_T_42 = _a_canArithmetic_T_21 | _a_canArithmetic_T_26; // @[Parameters.scala:685:42]
wire _a_canArithmetic_T_43 = _a_canArithmetic_T_42 | _a_canArithmetic_T_31; // @[Parameters.scala:685:42]
wire _a_canArithmetic_T_44 = _a_canArithmetic_T_43 | _a_canArithmetic_T_36; // @[Parameters.scala:685:42]
wire _a_canArithmetic_T_45 = _a_canArithmetic_T_44 | _a_canArithmetic_T_41; // @[Parameters.scala:685:42]
wire _a_canArithmetic_T_48 = _a_canArithmetic_T_47; // @[Parameters.scala:686:26]
wire a_canArithmetic = _a_canArithmetic_T_48; // @[Parameters.scala:686:26]
wire a_isLogical = nodeIn_a_bits_opcode == 3'h3; // @[AtomicAutomata.scala:96:47]
wire a_isArithmetic = nodeIn_a_bits_opcode == 3'h2; // @[AtomicAutomata.scala:97:47]
wire _a_isSupported_T = ~a_isArithmetic | a_canArithmetic; // @[AtomicAutomata.scala:95:45, :97:47, :98:63]
wire a_isSupported = a_isLogical ? a_canLogical : _a_isSupported_T; // @[AtomicAutomata.scala:94:45, :96:47, :98:{32,63}]
wire [29:0] _a_fifoId_T_1 = {1'h0, _a_fifoId_T}; // @[Parameters.scala:137:{31,41}]
wire _indexes_T = cam_a_0_bits_data[0]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_1 = cam_d_0_data[0]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_0 = {_indexes_T, _indexes_T_1}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_2 = cam_a_0_bits_data[1]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_3 = cam_d_0_data[1]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_1 = {_indexes_T_2, _indexes_T_3}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_4 = cam_a_0_bits_data[2]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_5 = cam_d_0_data[2]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_2 = {_indexes_T_4, _indexes_T_5}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_6 = cam_a_0_bits_data[3]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_7 = cam_d_0_data[3]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_3 = {_indexes_T_6, _indexes_T_7}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_8 = cam_a_0_bits_data[4]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_9 = cam_d_0_data[4]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_4 = {_indexes_T_8, _indexes_T_9}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_10 = cam_a_0_bits_data[5]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_11 = cam_d_0_data[5]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_5 = {_indexes_T_10, _indexes_T_11}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_12 = cam_a_0_bits_data[6]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_13 = cam_d_0_data[6]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_6 = {_indexes_T_12, _indexes_T_13}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_14 = cam_a_0_bits_data[7]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T = cam_a_0_bits_data[7]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_15 = cam_d_0_data[7]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T = cam_d_0_data[7]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_7 = {_indexes_T_14, _indexes_T_15}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_16 = cam_a_0_bits_data[8]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_17 = cam_d_0_data[8]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_8 = {_indexes_T_16, _indexes_T_17}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_18 = cam_a_0_bits_data[9]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_19 = cam_d_0_data[9]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_9 = {_indexes_T_18, _indexes_T_19}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_20 = cam_a_0_bits_data[10]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_21 = cam_d_0_data[10]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_10 = {_indexes_T_20, _indexes_T_21}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_22 = cam_a_0_bits_data[11]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_23 = cam_d_0_data[11]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_11 = {_indexes_T_22, _indexes_T_23}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_24 = cam_a_0_bits_data[12]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_25 = cam_d_0_data[12]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_12 = {_indexes_T_24, _indexes_T_25}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_26 = cam_a_0_bits_data[13]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_27 = cam_d_0_data[13]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_13 = {_indexes_T_26, _indexes_T_27}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_28 = cam_a_0_bits_data[14]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_29 = cam_d_0_data[14]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_14 = {_indexes_T_28, _indexes_T_29}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_30 = cam_a_0_bits_data[15]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T_1 = cam_a_0_bits_data[15]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_31 = cam_d_0_data[15]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T_1 = cam_d_0_data[15]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_15 = {_indexes_T_30, _indexes_T_31}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_32 = cam_a_0_bits_data[16]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_33 = cam_d_0_data[16]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_16 = {_indexes_T_32, _indexes_T_33}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_34 = cam_a_0_bits_data[17]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_35 = cam_d_0_data[17]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_17 = {_indexes_T_34, _indexes_T_35}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_36 = cam_a_0_bits_data[18]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_37 = cam_d_0_data[18]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_18 = {_indexes_T_36, _indexes_T_37}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_38 = cam_a_0_bits_data[19]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_39 = cam_d_0_data[19]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_19 = {_indexes_T_38, _indexes_T_39}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_40 = cam_a_0_bits_data[20]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_41 = cam_d_0_data[20]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_20 = {_indexes_T_40, _indexes_T_41}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_42 = cam_a_0_bits_data[21]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_43 = cam_d_0_data[21]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_21 = {_indexes_T_42, _indexes_T_43}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_44 = cam_a_0_bits_data[22]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_45 = cam_d_0_data[22]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_22 = {_indexes_T_44, _indexes_T_45}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_46 = cam_a_0_bits_data[23]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T_2 = cam_a_0_bits_data[23]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_47 = cam_d_0_data[23]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T_2 = cam_d_0_data[23]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_23 = {_indexes_T_46, _indexes_T_47}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_48 = cam_a_0_bits_data[24]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_49 = cam_d_0_data[24]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_24 = {_indexes_T_48, _indexes_T_49}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_50 = cam_a_0_bits_data[25]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_51 = cam_d_0_data[25]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_25 = {_indexes_T_50, _indexes_T_51}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_52 = cam_a_0_bits_data[26]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_53 = cam_d_0_data[26]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_26 = {_indexes_T_52, _indexes_T_53}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_54 = cam_a_0_bits_data[27]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_55 = cam_d_0_data[27]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_27 = {_indexes_T_54, _indexes_T_55}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_56 = cam_a_0_bits_data[28]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_57 = cam_d_0_data[28]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_28 = {_indexes_T_56, _indexes_T_57}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_58 = cam_a_0_bits_data[29]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_59 = cam_d_0_data[29]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_29 = {_indexes_T_58, _indexes_T_59}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_60 = cam_a_0_bits_data[30]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_61 = cam_d_0_data[30]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_30 = {_indexes_T_60, _indexes_T_61}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_62 = cam_a_0_bits_data[31]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T_3 = cam_a_0_bits_data[31]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_63 = cam_d_0_data[31]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T_3 = cam_d_0_data[31]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_31 = {_indexes_T_62, _indexes_T_63}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_64 = cam_a_0_bits_data[32]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_65 = cam_d_0_data[32]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_32 = {_indexes_T_64, _indexes_T_65}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_66 = cam_a_0_bits_data[33]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_67 = cam_d_0_data[33]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_33 = {_indexes_T_66, _indexes_T_67}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_68 = cam_a_0_bits_data[34]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_69 = cam_d_0_data[34]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_34 = {_indexes_T_68, _indexes_T_69}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_70 = cam_a_0_bits_data[35]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_71 = cam_d_0_data[35]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_35 = {_indexes_T_70, _indexes_T_71}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_72 = cam_a_0_bits_data[36]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_73 = cam_d_0_data[36]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_36 = {_indexes_T_72, _indexes_T_73}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_74 = cam_a_0_bits_data[37]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_75 = cam_d_0_data[37]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_37 = {_indexes_T_74, _indexes_T_75}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_76 = cam_a_0_bits_data[38]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_77 = cam_d_0_data[38]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_38 = {_indexes_T_76, _indexes_T_77}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_78 = cam_a_0_bits_data[39]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T_4 = cam_a_0_bits_data[39]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_79 = cam_d_0_data[39]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T_4 = cam_d_0_data[39]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_39 = {_indexes_T_78, _indexes_T_79}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_80 = cam_a_0_bits_data[40]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_81 = cam_d_0_data[40]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_40 = {_indexes_T_80, _indexes_T_81}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_82 = cam_a_0_bits_data[41]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_83 = cam_d_0_data[41]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_41 = {_indexes_T_82, _indexes_T_83}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_84 = cam_a_0_bits_data[42]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_85 = cam_d_0_data[42]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_42 = {_indexes_T_84, _indexes_T_85}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_86 = cam_a_0_bits_data[43]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_87 = cam_d_0_data[43]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_43 = {_indexes_T_86, _indexes_T_87}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_88 = cam_a_0_bits_data[44]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_89 = cam_d_0_data[44]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_44 = {_indexes_T_88, _indexes_T_89}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_90 = cam_a_0_bits_data[45]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_91 = cam_d_0_data[45]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_45 = {_indexes_T_90, _indexes_T_91}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_92 = cam_a_0_bits_data[46]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_93 = cam_d_0_data[46]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_46 = {_indexes_T_92, _indexes_T_93}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_94 = cam_a_0_bits_data[47]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T_5 = cam_a_0_bits_data[47]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_95 = cam_d_0_data[47]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T_5 = cam_d_0_data[47]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_47 = {_indexes_T_94, _indexes_T_95}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_96 = cam_a_0_bits_data[48]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_97 = cam_d_0_data[48]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_48 = {_indexes_T_96, _indexes_T_97}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_98 = cam_a_0_bits_data[49]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_99 = cam_d_0_data[49]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_49 = {_indexes_T_98, _indexes_T_99}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_100 = cam_a_0_bits_data[50]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_101 = cam_d_0_data[50]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_50 = {_indexes_T_100, _indexes_T_101}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_102 = cam_a_0_bits_data[51]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_103 = cam_d_0_data[51]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_51 = {_indexes_T_102, _indexes_T_103}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_104 = cam_a_0_bits_data[52]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_105 = cam_d_0_data[52]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_52 = {_indexes_T_104, _indexes_T_105}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_106 = cam_a_0_bits_data[53]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_107 = cam_d_0_data[53]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_53 = {_indexes_T_106, _indexes_T_107}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_108 = cam_a_0_bits_data[54]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_109 = cam_d_0_data[54]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_54 = {_indexes_T_108, _indexes_T_109}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_110 = cam_a_0_bits_data[55]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T_6 = cam_a_0_bits_data[55]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_111 = cam_d_0_data[55]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T_6 = cam_d_0_data[55]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_55 = {_indexes_T_110, _indexes_T_111}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_112 = cam_a_0_bits_data[56]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_113 = cam_d_0_data[56]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_56 = {_indexes_T_112, _indexes_T_113}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_114 = cam_a_0_bits_data[57]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_115 = cam_d_0_data[57]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_57 = {_indexes_T_114, _indexes_T_115}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_116 = cam_a_0_bits_data[58]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_117 = cam_d_0_data[58]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_58 = {_indexes_T_116, _indexes_T_117}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_118 = cam_a_0_bits_data[59]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_119 = cam_d_0_data[59]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_59 = {_indexes_T_118, _indexes_T_119}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_120 = cam_a_0_bits_data[60]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_121 = cam_d_0_data[60]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_60 = {_indexes_T_120, _indexes_T_121}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_122 = cam_a_0_bits_data[61]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_123 = cam_d_0_data[61]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_61 = {_indexes_T_122, _indexes_T_123}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_124 = cam_a_0_bits_data[62]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_125 = cam_d_0_data[62]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_62 = {_indexes_T_124, _indexes_T_125}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_126 = cam_a_0_bits_data[63]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T_7 = cam_a_0_bits_data[63]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_127 = cam_d_0_data[63]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T_7 = cam_d_0_data[63]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_63 = {_indexes_T_126, _indexes_T_127}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire [3:0] _logic_out_T = cam_a_0_lut >> indexes_0; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_1 = _logic_out_T[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_2 = cam_a_0_lut >> indexes_1; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_3 = _logic_out_T_2[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_4 = cam_a_0_lut >> indexes_2; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_5 = _logic_out_T_4[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_6 = cam_a_0_lut >> indexes_3; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_7 = _logic_out_T_6[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_8 = cam_a_0_lut >> indexes_4; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_9 = _logic_out_T_8[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_10 = cam_a_0_lut >> indexes_5; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_11 = _logic_out_T_10[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_12 = cam_a_0_lut >> indexes_6; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_13 = _logic_out_T_12[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_14 = cam_a_0_lut >> indexes_7; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_15 = _logic_out_T_14[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_16 = cam_a_0_lut >> indexes_8; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_17 = _logic_out_T_16[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_18 = cam_a_0_lut >> indexes_9; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_19 = _logic_out_T_18[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_20 = cam_a_0_lut >> indexes_10; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_21 = _logic_out_T_20[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_22 = cam_a_0_lut >> indexes_11; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_23 = _logic_out_T_22[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_24 = cam_a_0_lut >> indexes_12; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_25 = _logic_out_T_24[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_26 = cam_a_0_lut >> indexes_13; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_27 = _logic_out_T_26[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_28 = cam_a_0_lut >> indexes_14; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_29 = _logic_out_T_28[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_30 = cam_a_0_lut >> indexes_15; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_31 = _logic_out_T_30[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_32 = cam_a_0_lut >> indexes_16; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_33 = _logic_out_T_32[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_34 = cam_a_0_lut >> indexes_17; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_35 = _logic_out_T_34[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_36 = cam_a_0_lut >> indexes_18; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_37 = _logic_out_T_36[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_38 = cam_a_0_lut >> indexes_19; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_39 = _logic_out_T_38[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_40 = cam_a_0_lut >> indexes_20; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_41 = _logic_out_T_40[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_42 = cam_a_0_lut >> indexes_21; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_43 = _logic_out_T_42[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_44 = cam_a_0_lut >> indexes_22; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_45 = _logic_out_T_44[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_46 = cam_a_0_lut >> indexes_23; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_47 = _logic_out_T_46[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_48 = cam_a_0_lut >> indexes_24; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_49 = _logic_out_T_48[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_50 = cam_a_0_lut >> indexes_25; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_51 = _logic_out_T_50[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_52 = cam_a_0_lut >> indexes_26; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_53 = _logic_out_T_52[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_54 = cam_a_0_lut >> indexes_27; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_55 = _logic_out_T_54[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_56 = cam_a_0_lut >> indexes_28; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_57 = _logic_out_T_56[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_58 = cam_a_0_lut >> indexes_29; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_59 = _logic_out_T_58[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_60 = cam_a_0_lut >> indexes_30; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_61 = _logic_out_T_60[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_62 = cam_a_0_lut >> indexes_31; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_63 = _logic_out_T_62[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_64 = cam_a_0_lut >> indexes_32; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_65 = _logic_out_T_64[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_66 = cam_a_0_lut >> indexes_33; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_67 = _logic_out_T_66[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_68 = cam_a_0_lut >> indexes_34; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_69 = _logic_out_T_68[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_70 = cam_a_0_lut >> indexes_35; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_71 = _logic_out_T_70[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_72 = cam_a_0_lut >> indexes_36; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_73 = _logic_out_T_72[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_74 = cam_a_0_lut >> indexes_37; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_75 = _logic_out_T_74[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_76 = cam_a_0_lut >> indexes_38; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_77 = _logic_out_T_76[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_78 = cam_a_0_lut >> indexes_39; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_79 = _logic_out_T_78[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_80 = cam_a_0_lut >> indexes_40; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_81 = _logic_out_T_80[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_82 = cam_a_0_lut >> indexes_41; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_83 = _logic_out_T_82[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_84 = cam_a_0_lut >> indexes_42; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_85 = _logic_out_T_84[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_86 = cam_a_0_lut >> indexes_43; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_87 = _logic_out_T_86[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_88 = cam_a_0_lut >> indexes_44; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_89 = _logic_out_T_88[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_90 = cam_a_0_lut >> indexes_45; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_91 = _logic_out_T_90[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_92 = cam_a_0_lut >> indexes_46; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_93 = _logic_out_T_92[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_94 = cam_a_0_lut >> indexes_47; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_95 = _logic_out_T_94[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_96 = cam_a_0_lut >> indexes_48; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_97 = _logic_out_T_96[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_98 = cam_a_0_lut >> indexes_49; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_99 = _logic_out_T_98[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_100 = cam_a_0_lut >> indexes_50; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_101 = _logic_out_T_100[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_102 = cam_a_0_lut >> indexes_51; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_103 = _logic_out_T_102[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_104 = cam_a_0_lut >> indexes_52; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_105 = _logic_out_T_104[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_106 = cam_a_0_lut >> indexes_53; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_107 = _logic_out_T_106[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_108 = cam_a_0_lut >> indexes_54; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_109 = _logic_out_T_108[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_110 = cam_a_0_lut >> indexes_55; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_111 = _logic_out_T_110[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_112 = cam_a_0_lut >> indexes_56; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_113 = _logic_out_T_112[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_114 = cam_a_0_lut >> indexes_57; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_115 = _logic_out_T_114[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_116 = cam_a_0_lut >> indexes_58; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_117 = _logic_out_T_116[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_118 = cam_a_0_lut >> indexes_59; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_119 = _logic_out_T_118[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_120 = cam_a_0_lut >> indexes_60; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_121 = _logic_out_T_120[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_122 = cam_a_0_lut >> indexes_61; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_123 = _logic_out_T_122[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_124 = cam_a_0_lut >> indexes_62; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_125 = _logic_out_T_124[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_126 = cam_a_0_lut >> indexes_63; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_127 = _logic_out_T_126[0]; // @[AtomicAutomata.scala:120:57]
wire [1:0] logic_out_lo_lo_lo_lo_lo = {_logic_out_T_3, _logic_out_T_1}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_lo_lo_lo_hi = {_logic_out_T_7, _logic_out_T_5}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_lo_lo_lo = {logic_out_lo_lo_lo_lo_hi, logic_out_lo_lo_lo_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_lo_lo_lo_hi_lo = {_logic_out_T_11, _logic_out_T_9}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_lo_lo_hi_hi = {_logic_out_T_15, _logic_out_T_13}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_lo_lo_hi = {logic_out_lo_lo_lo_hi_hi, logic_out_lo_lo_lo_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_lo_lo_lo = {logic_out_lo_lo_lo_hi, logic_out_lo_lo_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_lo_lo_hi_lo_lo = {_logic_out_T_19, _logic_out_T_17}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_lo_hi_lo_hi = {_logic_out_T_23, _logic_out_T_21}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_lo_hi_lo = {logic_out_lo_lo_hi_lo_hi, logic_out_lo_lo_hi_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_lo_lo_hi_hi_lo = {_logic_out_T_27, _logic_out_T_25}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_lo_hi_hi_hi = {_logic_out_T_31, _logic_out_T_29}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_lo_hi_hi = {logic_out_lo_lo_hi_hi_hi, logic_out_lo_lo_hi_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_lo_lo_hi = {logic_out_lo_lo_hi_hi, logic_out_lo_lo_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [15:0] logic_out_lo_lo = {logic_out_lo_lo_hi, logic_out_lo_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_lo_hi_lo_lo_lo = {_logic_out_T_35, _logic_out_T_33}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_hi_lo_lo_hi = {_logic_out_T_39, _logic_out_T_37}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_hi_lo_lo = {logic_out_lo_hi_lo_lo_hi, logic_out_lo_hi_lo_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_lo_hi_lo_hi_lo = {_logic_out_T_43, _logic_out_T_41}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_hi_lo_hi_hi = {_logic_out_T_47, _logic_out_T_45}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_hi_lo_hi = {logic_out_lo_hi_lo_hi_hi, logic_out_lo_hi_lo_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_lo_hi_lo = {logic_out_lo_hi_lo_hi, logic_out_lo_hi_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_lo_hi_hi_lo_lo = {_logic_out_T_51, _logic_out_T_49}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_hi_hi_lo_hi = {_logic_out_T_55, _logic_out_T_53}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_hi_hi_lo = {logic_out_lo_hi_hi_lo_hi, logic_out_lo_hi_hi_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_lo_hi_hi_hi_lo = {_logic_out_T_59, _logic_out_T_57}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_hi_hi_hi_hi = {_logic_out_T_63, _logic_out_T_61}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_hi_hi_hi = {logic_out_lo_hi_hi_hi_hi, logic_out_lo_hi_hi_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_lo_hi_hi = {logic_out_lo_hi_hi_hi, logic_out_lo_hi_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [15:0] logic_out_lo_hi = {logic_out_lo_hi_hi, logic_out_lo_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [31:0] logic_out_lo = {logic_out_lo_hi, logic_out_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_lo_lo_lo_lo = {_logic_out_T_67, _logic_out_T_65}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_lo_lo_lo_hi = {_logic_out_T_71, _logic_out_T_69}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_lo_lo_lo = {logic_out_hi_lo_lo_lo_hi, logic_out_hi_lo_lo_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_lo_lo_hi_lo = {_logic_out_T_75, _logic_out_T_73}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_lo_lo_hi_hi = {_logic_out_T_79, _logic_out_T_77}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_lo_lo_hi = {logic_out_hi_lo_lo_hi_hi, logic_out_hi_lo_lo_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_hi_lo_lo = {logic_out_hi_lo_lo_hi, logic_out_hi_lo_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_lo_hi_lo_lo = {_logic_out_T_83, _logic_out_T_81}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_lo_hi_lo_hi = {_logic_out_T_87, _logic_out_T_85}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_lo_hi_lo = {logic_out_hi_lo_hi_lo_hi, logic_out_hi_lo_hi_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_lo_hi_hi_lo = {_logic_out_T_91, _logic_out_T_89}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_lo_hi_hi_hi = {_logic_out_T_95, _logic_out_T_93}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_lo_hi_hi = {logic_out_hi_lo_hi_hi_hi, logic_out_hi_lo_hi_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_hi_lo_hi = {logic_out_hi_lo_hi_hi, logic_out_hi_lo_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [15:0] logic_out_hi_lo = {logic_out_hi_lo_hi, logic_out_hi_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_hi_lo_lo_lo = {_logic_out_T_99, _logic_out_T_97}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_hi_lo_lo_hi = {_logic_out_T_103, _logic_out_T_101}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_hi_lo_lo = {logic_out_hi_hi_lo_lo_hi, logic_out_hi_hi_lo_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_hi_lo_hi_lo = {_logic_out_T_107, _logic_out_T_105}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_hi_lo_hi_hi = {_logic_out_T_111, _logic_out_T_109}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_hi_lo_hi = {logic_out_hi_hi_lo_hi_hi, logic_out_hi_hi_lo_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_hi_hi_lo = {logic_out_hi_hi_lo_hi, logic_out_hi_hi_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_hi_hi_lo_lo = {_logic_out_T_115, _logic_out_T_113}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_hi_hi_lo_hi = {_logic_out_T_119, _logic_out_T_117}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_hi_hi_lo = {logic_out_hi_hi_hi_lo_hi, logic_out_hi_hi_hi_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_hi_hi_hi_lo = {_logic_out_T_123, _logic_out_T_121}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_hi_hi_hi_hi = {_logic_out_T_127, _logic_out_T_125}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_hi_hi_hi = {logic_out_hi_hi_hi_hi_hi, logic_out_hi_hi_hi_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_hi_hi_hi = {logic_out_hi_hi_hi_hi, logic_out_hi_hi_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [15:0] logic_out_hi_hi = {logic_out_hi_hi_hi, logic_out_hi_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [31:0] logic_out_hi = {logic_out_hi_hi, logic_out_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [63:0] logic_out = {logic_out_hi, logic_out_lo}; // @[AtomicAutomata.scala:120:28]
wire unsigned_0 = cam_a_0_bits_param[1]; // @[AtomicAutomata.scala:83:24, :123:42]
wire take_max = cam_a_0_bits_param[0]; // @[AtomicAutomata.scala:83:24, :124:42]
wire adder = cam_a_0_bits_param[2]; // @[AtomicAutomata.scala:83:24, :125:39]
wire [7:0] _signSel_T = ~cam_a_0_bits_mask; // @[AtomicAutomata.scala:83:24, :127:25]
wire [6:0] _signSel_T_1 = cam_a_0_bits_mask[7:1]; // @[AtomicAutomata.scala:83:24, :127:39]
wire [7:0] _signSel_T_2 = {_signSel_T[7], _signSel_T[6:0] | _signSel_T_1}; // @[AtomicAutomata.scala:127:{25,31,39}]
wire [7:0] signSel = ~_signSel_T_2; // @[AtomicAutomata.scala:127:{23,31}]
wire [1:0] signbits_a_lo_lo = {_signbits_a_T_1, _signbits_a_T}; // @[AtomicAutomata.scala:128:{29,64}]
wire [1:0] signbits_a_lo_hi = {_signbits_a_T_3, _signbits_a_T_2}; // @[AtomicAutomata.scala:128:{29,64}]
wire [3:0] signbits_a_lo = {signbits_a_lo_hi, signbits_a_lo_lo}; // @[AtomicAutomata.scala:128:29]
wire [1:0] signbits_a_hi_lo = {_signbits_a_T_5, _signbits_a_T_4}; // @[AtomicAutomata.scala:128:{29,64}]
wire [1:0] signbits_a_hi_hi = {_signbits_a_T_7, _signbits_a_T_6}; // @[AtomicAutomata.scala:128:{29,64}]
wire [3:0] signbits_a_hi = {signbits_a_hi_hi, signbits_a_hi_lo}; // @[AtomicAutomata.scala:128:29]
wire [7:0] signbits_a = {signbits_a_hi, signbits_a_lo}; // @[AtomicAutomata.scala:128:29]
wire [1:0] signbits_d_lo_lo = {_signbits_d_T_1, _signbits_d_T}; // @[AtomicAutomata.scala:129:{29,64}]
wire [1:0] signbits_d_lo_hi = {_signbits_d_T_3, _signbits_d_T_2}; // @[AtomicAutomata.scala:129:{29,64}]
wire [3:0] signbits_d_lo = {signbits_d_lo_hi, signbits_d_lo_lo}; // @[AtomicAutomata.scala:129:29]
wire [1:0] signbits_d_hi_lo = {_signbits_d_T_5, _signbits_d_T_4}; // @[AtomicAutomata.scala:129:{29,64}]
wire [1:0] signbits_d_hi_hi = {_signbits_d_T_7, _signbits_d_T_6}; // @[AtomicAutomata.scala:129:{29,64}]
wire [3:0] signbits_d_hi = {signbits_d_hi_hi, signbits_d_hi_lo}; // @[AtomicAutomata.scala:129:29]
wire [7:0] signbits_d = {signbits_d_hi, signbits_d_lo}; // @[AtomicAutomata.scala:129:29]
wire [7:0] _signbit_a_T = signbits_a & signSel; // @[AtomicAutomata.scala:127:23, :128:29, :131:38]
wire [8:0] _signbit_a_T_1 = {_signbit_a_T, 1'h0}; // @[AtomicAutomata.scala:131:{38,49}]
wire [7:0] signbit_a = _signbit_a_T_1[7:0]; // @[AtomicAutomata.scala:131:{49,54}]
wire [7:0] _signbit_d_T = signbits_d & signSel; // @[AtomicAutomata.scala:127:23, :129:29, :132:38]
wire [8:0] _signbit_d_T_1 = {_signbit_d_T, 1'h0}; // @[AtomicAutomata.scala:132:{38,49}]
wire [7:0] signbit_d = _signbit_d_T_1[7:0]; // @[AtomicAutomata.scala:132:{49,54}]
wire [8:0] _signext_a_T = {signbit_a, 1'h0}; // @[package.scala:253:48]
wire [7:0] _signext_a_T_1 = _signext_a_T[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _signext_a_T_2 = signbit_a | _signext_a_T_1; // @[package.scala:253:{43,53}]
wire [9:0] _signext_a_T_3 = {_signext_a_T_2, 2'h0}; // @[package.scala:253:{43,48}]
wire [7:0] _signext_a_T_4 = _signext_a_T_3[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _signext_a_T_5 = _signext_a_T_2 | _signext_a_T_4; // @[package.scala:253:{43,53}]
wire [11:0] _signext_a_T_6 = {_signext_a_T_5, 4'h0}; // @[package.scala:253:{43,48}]
wire [7:0] _signext_a_T_7 = _signext_a_T_6[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _signext_a_T_8 = _signext_a_T_5 | _signext_a_T_7; // @[package.scala:253:{43,53}]
wire [7:0] _signext_a_T_9 = _signext_a_T_8; // @[package.scala:253:43, :254:17]
wire _signext_a_T_10 = _signext_a_T_9[0]; // @[package.scala:254:17]
wire _signext_a_T_11 = _signext_a_T_9[1]; // @[package.scala:254:17]
wire _signext_a_T_12 = _signext_a_T_9[2]; // @[package.scala:254:17]
wire _signext_a_T_13 = _signext_a_T_9[3]; // @[package.scala:254:17]
wire _signext_a_T_14 = _signext_a_T_9[4]; // @[package.scala:254:17]
wire _signext_a_T_15 = _signext_a_T_9[5]; // @[package.scala:254:17]
wire _signext_a_T_16 = _signext_a_T_9[6]; // @[package.scala:254:17]
wire _signext_a_T_17 = _signext_a_T_9[7]; // @[package.scala:254:17]
wire [7:0] _signext_a_T_18 = {8{_signext_a_T_10}}; // @[AtomicAutomata.scala:133:40]
wire [7:0] _signext_a_T_19 = {8{_signext_a_T_11}}; // @[AtomicAutomata.scala:133:40]
wire [7:0] _signext_a_T_20 = {8{_signext_a_T_12}}; // @[AtomicAutomata.scala:133:40]
wire [7:0] _signext_a_T_21 = {8{_signext_a_T_13}}; // @[AtomicAutomata.scala:133:40]
wire [7:0] _signext_a_T_22 = {8{_signext_a_T_14}}; // @[AtomicAutomata.scala:133:40]
wire [7:0] _signext_a_T_23 = {8{_signext_a_T_15}}; // @[AtomicAutomata.scala:133:40]
wire [7:0] _signext_a_T_24 = {8{_signext_a_T_16}}; // @[AtomicAutomata.scala:133:40]
wire [7:0] _signext_a_T_25 = {8{_signext_a_T_17}}; // @[AtomicAutomata.scala:133:40]
wire [15:0] signext_a_lo_lo = {_signext_a_T_19, _signext_a_T_18}; // @[AtomicAutomata.scala:133:40]
wire [15:0] signext_a_lo_hi = {_signext_a_T_21, _signext_a_T_20}; // @[AtomicAutomata.scala:133:40]
wire [31:0] signext_a_lo = {signext_a_lo_hi, signext_a_lo_lo}; // @[AtomicAutomata.scala:133:40]
wire [15:0] signext_a_hi_lo = {_signext_a_T_23, _signext_a_T_22}; // @[AtomicAutomata.scala:133:40]
wire [15:0] signext_a_hi_hi = {_signext_a_T_25, _signext_a_T_24}; // @[AtomicAutomata.scala:133:40]
wire [31:0] signext_a_hi = {signext_a_hi_hi, signext_a_hi_lo}; // @[AtomicAutomata.scala:133:40]
wire [63:0] signext_a = {signext_a_hi, signext_a_lo}; // @[AtomicAutomata.scala:133:40]
wire [8:0] _signext_d_T = {signbit_d, 1'h0}; // @[package.scala:253:48]
wire [7:0] _signext_d_T_1 = _signext_d_T[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _signext_d_T_2 = signbit_d | _signext_d_T_1; // @[package.scala:253:{43,53}]
wire [9:0] _signext_d_T_3 = {_signext_d_T_2, 2'h0}; // @[package.scala:253:{43,48}]
wire [7:0] _signext_d_T_4 = _signext_d_T_3[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _signext_d_T_5 = _signext_d_T_2 | _signext_d_T_4; // @[package.scala:253:{43,53}]
wire [11:0] _signext_d_T_6 = {_signext_d_T_5, 4'h0}; // @[package.scala:253:{43,48}]
wire [7:0] _signext_d_T_7 = _signext_d_T_6[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _signext_d_T_8 = _signext_d_T_5 | _signext_d_T_7; // @[package.scala:253:{43,53}]
wire [7:0] _signext_d_T_9 = _signext_d_T_8; // @[package.scala:253:43, :254:17]
wire _signext_d_T_10 = _signext_d_T_9[0]; // @[package.scala:254:17]
wire _signext_d_T_11 = _signext_d_T_9[1]; // @[package.scala:254:17]
wire _signext_d_T_12 = _signext_d_T_9[2]; // @[package.scala:254:17]
wire _signext_d_T_13 = _signext_d_T_9[3]; // @[package.scala:254:17]
wire _signext_d_T_14 = _signext_d_T_9[4]; // @[package.scala:254:17]
wire _signext_d_T_15 = _signext_d_T_9[5]; // @[package.scala:254:17]
wire _signext_d_T_16 = _signext_d_T_9[6]; // @[package.scala:254:17]
wire _signext_d_T_17 = _signext_d_T_9[7]; // @[package.scala:254:17]
wire [7:0] _signext_d_T_18 = {8{_signext_d_T_10}}; // @[AtomicAutomata.scala:134:40]
wire [7:0] _signext_d_T_19 = {8{_signext_d_T_11}}; // @[AtomicAutomata.scala:134:40]
wire [7:0] _signext_d_T_20 = {8{_signext_d_T_12}}; // @[AtomicAutomata.scala:134:40]
wire [7:0] _signext_d_T_21 = {8{_signext_d_T_13}}; // @[AtomicAutomata.scala:134:40]
wire [7:0] _signext_d_T_22 = {8{_signext_d_T_14}}; // @[AtomicAutomata.scala:134:40]
wire [7:0] _signext_d_T_23 = {8{_signext_d_T_15}}; // @[AtomicAutomata.scala:134:40]
wire [7:0] _signext_d_T_24 = {8{_signext_d_T_16}}; // @[AtomicAutomata.scala:134:40]
wire [7:0] _signext_d_T_25 = {8{_signext_d_T_17}}; // @[AtomicAutomata.scala:134:40]
wire [15:0] signext_d_lo_lo = {_signext_d_T_19, _signext_d_T_18}; // @[AtomicAutomata.scala:134:40]
wire [15:0] signext_d_lo_hi = {_signext_d_T_21, _signext_d_T_20}; // @[AtomicAutomata.scala:134:40]
wire [31:0] signext_d_lo = {signext_d_lo_hi, signext_d_lo_lo}; // @[AtomicAutomata.scala:134:40]
wire [15:0] signext_d_hi_lo = {_signext_d_T_23, _signext_d_T_22}; // @[AtomicAutomata.scala:134:40]
wire [15:0] signext_d_hi_hi = {_signext_d_T_25, _signext_d_T_24}; // @[AtomicAutomata.scala:134:40]
wire [31:0] signext_d_hi = {signext_d_hi_hi, signext_d_hi_lo}; // @[AtomicAutomata.scala:134:40]
wire [63:0] signext_d = {signext_d_hi, signext_d_lo}; // @[AtomicAutomata.scala:134:40]
wire _wide_mask_T = cam_a_0_bits_mask[0]; // @[AtomicAutomata.scala:83:24, :136:40]
wire _wide_mask_T_1 = cam_a_0_bits_mask[1]; // @[AtomicAutomata.scala:83:24, :136:40]
wire _wide_mask_T_2 = cam_a_0_bits_mask[2]; // @[AtomicAutomata.scala:83:24, :136:40]
wire _wide_mask_T_3 = cam_a_0_bits_mask[3]; // @[AtomicAutomata.scala:83:24, :136:40]
wire _wide_mask_T_4 = cam_a_0_bits_mask[4]; // @[AtomicAutomata.scala:83:24, :136:40]
wire _wide_mask_T_5 = cam_a_0_bits_mask[5]; // @[AtomicAutomata.scala:83:24, :136:40]
wire _wide_mask_T_6 = cam_a_0_bits_mask[6]; // @[AtomicAutomata.scala:83:24, :136:40]
wire _wide_mask_T_7 = cam_a_0_bits_mask[7]; // @[AtomicAutomata.scala:83:24, :136:40]
wire [7:0] _wide_mask_T_8 = {8{_wide_mask_T}}; // @[AtomicAutomata.scala:136:40]
wire [7:0] _wide_mask_T_9 = {8{_wide_mask_T_1}}; // @[AtomicAutomata.scala:136:40]
wire [7:0] _wide_mask_T_10 = {8{_wide_mask_T_2}}; // @[AtomicAutomata.scala:136:40]
wire [7:0] _wide_mask_T_11 = {8{_wide_mask_T_3}}; // @[AtomicAutomata.scala:136:40]
wire [7:0] _wide_mask_T_12 = {8{_wide_mask_T_4}}; // @[AtomicAutomata.scala:136:40]
wire [7:0] _wide_mask_T_13 = {8{_wide_mask_T_5}}; // @[AtomicAutomata.scala:136:40]
wire [7:0] _wide_mask_T_14 = {8{_wide_mask_T_6}}; // @[AtomicAutomata.scala:136:40]
wire [7:0] _wide_mask_T_15 = {8{_wide_mask_T_7}}; // @[AtomicAutomata.scala:136:40]
wire [15:0] wide_mask_lo_lo = {_wide_mask_T_9, _wide_mask_T_8}; // @[AtomicAutomata.scala:136:40]
wire [15:0] wide_mask_lo_hi = {_wide_mask_T_11, _wide_mask_T_10}; // @[AtomicAutomata.scala:136:40]
wire [31:0] wide_mask_lo = {wide_mask_lo_hi, wide_mask_lo_lo}; // @[AtomicAutomata.scala:136:40]
wire [15:0] wide_mask_hi_lo = {_wide_mask_T_13, _wide_mask_T_12}; // @[AtomicAutomata.scala:136:40]
wire [15:0] wide_mask_hi_hi = {_wide_mask_T_15, _wide_mask_T_14}; // @[AtomicAutomata.scala:136:40]
wire [31:0] wide_mask_hi = {wide_mask_hi_hi, wide_mask_hi_lo}; // @[AtomicAutomata.scala:136:40]
wire [63:0] wide_mask = {wide_mask_hi, wide_mask_lo}; // @[AtomicAutomata.scala:136:40]
wire [63:0] _a_a_ext_T = cam_a_0_bits_data & wide_mask; // @[AtomicAutomata.scala:83:24, :136:40, :137:28]
wire [63:0] a_a_ext = _a_a_ext_T | signext_a; // @[AtomicAutomata.scala:133:40, :137:{28,41}]
wire [63:0] _a_d_ext_T = cam_d_0_data & wide_mask; // @[AtomicAutomata.scala:84:24, :136:40, :138:28]
wire [63:0] a_d_ext = _a_d_ext_T | signext_d; // @[AtomicAutomata.scala:134:40, :138:{28,41}]
wire [63:0] _a_d_inv_T = ~a_d_ext; // @[AtomicAutomata.scala:138:41, :139:43]
wire [63:0] a_d_inv = adder ? a_d_ext : _a_d_inv_T; // @[AtomicAutomata.scala:125:39, :138:41, :139:{26,43}]
wire [64:0] _adder_out_T = {1'h0, a_a_ext} + {1'h0, a_d_inv}; // @[AtomicAutomata.scala:137:41, :139:26, :140:33]
wire [63:0] adder_out = _adder_out_T[63:0]; // @[AtomicAutomata.scala:140:33]
wire _a_bigger_uneq_T = a_a_ext[63]; // @[AtomicAutomata.scala:137:41, :142:49]
wire _a_bigger_T = a_a_ext[63]; // @[AtomicAutomata.scala:137:41, :142:49, :143:35]
wire a_bigger_uneq = unsigned_0 == _a_bigger_uneq_T; // @[AtomicAutomata.scala:123:42, :142:{38,49}]
wire _a_bigger_T_1 = a_d_ext[63]; // @[AtomicAutomata.scala:138:41, :143:50]
wire _a_bigger_T_2 = _a_bigger_T == _a_bigger_T_1; // @[AtomicAutomata.scala:143:{35,39,50}]
wire _a_bigger_T_3 = adder_out[63]; // @[AtomicAutomata.scala:140:33, :143:65]
wire _a_bigger_T_4 = ~_a_bigger_T_3; // @[AtomicAutomata.scala:143:{55,65}]
wire a_bigger = _a_bigger_T_2 ? _a_bigger_T_4 : a_bigger_uneq; // @[AtomicAutomata.scala:142:38, :143:{27,39,55}]
wire pick_a = take_max == a_bigger; // @[AtomicAutomata.scala:124:42, :143:27, :144:31]
wire [63:0] _arith_out_T = pick_a ? cam_a_0_bits_data : cam_d_0_data; // @[AtomicAutomata.scala:83:24, :84:24, :144:31, :145:50]
wire [63:0] arith_out = adder ? adder_out : _arith_out_T; // @[AtomicAutomata.scala:125:39, :140:33, :145:{28,50}]
wire _amo_data_T = cam_a_0_bits_opcode[0]; // @[AtomicAutomata.scala:83:24, :151:34]
wire [63:0] amo_data = _amo_data_T ? logic_out : arith_out; // @[AtomicAutomata.scala:120:28, :145:28, :151:{14,34}]
wire [63:0] source_c_bits_a_data = amo_data; // @[Edges.scala:480:17]
wire _source_i_ready_T; // @[Arbiter.scala:94:31]
wire _source_i_valid_T; // @[AtomicAutomata.scala:157:38]
wire [2:0] source_i_bits_opcode; // @[AtomicAutomata.scala:154:28]
wire [2:0] source_i_bits_param; // @[AtomicAutomata.scala:154:28]
wire source_i_ready; // @[AtomicAutomata.scala:154:28]
wire source_i_valid; // @[AtomicAutomata.scala:154:28]
wire _a_allow_T = ~a_cam_busy; // @[AtomicAutomata.scala:111:96, :155:23]
wire _a_allow_T_1 = a_isSupported | cam_free_0; // @[AtomicAutomata.scala:86:44, :98:32, :155:53]
wire a_allow = _a_allow_T & _a_allow_T_1; // @[AtomicAutomata.scala:155:{23,35,53}]
assign _nodeIn_a_ready_T = source_i_ready & a_allow; // @[AtomicAutomata.scala:154:28, :155:35, :156:38]
assign nodeIn_a_ready = _nodeIn_a_ready_T; // @[AtomicAutomata.scala:156:38]
assign _source_i_valid_T = nodeIn_a_valid & a_allow; // @[AtomicAutomata.scala:155:35, :157:38]
assign source_i_valid = _source_i_valid_T; // @[AtomicAutomata.scala:154:28, :157:38]
assign source_i_bits_opcode = a_isSupported ? nodeIn_a_bits_opcode : 3'h4; // @[AtomicAutomata.scala:98:32, :154:28, :158:24, :159:31, :160:32]
assign source_i_bits_param = a_isSupported ? nodeIn_a_bits_param : 3'h0; // @[AtomicAutomata.scala:98:32, :154:28, :158:24, :159:31, :161:32]
wire _source_c_ready_T; // @[Arbiter.scala:94:31]
wire [7:0] source_c_bits_a_mask; // @[Edges.scala:480:17]
wire source_c_bits_a_corrupt; // @[Edges.scala:480:17]
wire [3:0] source_c_bits_size; // @[AtomicAutomata.scala:165:28]
wire [8:0] source_c_bits_source; // @[AtomicAutomata.scala:165:28]
wire [28:0] source_c_bits_address; // @[AtomicAutomata.scala:165:28]
wire [7:0] source_c_bits_mask; // @[AtomicAutomata.scala:165:28]
wire [63:0] source_c_bits_data; // @[AtomicAutomata.scala:165:28]
wire source_c_bits_corrupt; // @[AtomicAutomata.scala:165:28]
wire source_c_ready; // @[AtomicAutomata.scala:165:28]
wire _source_c_bits_T = cam_a_0_bits_corrupt | cam_d_0_corrupt; // @[AtomicAutomata.scala:83:24, :84:24, :172:45]
assign source_c_bits_a_corrupt = _source_c_bits_T; // @[Edges.scala:480:17]
wire _source_c_bits_legal_T_1 = cam_a_0_bits_size < 4'hD; // @[AtomicAutomata.scala:83:24]
wire _source_c_bits_legal_T_2 = _source_c_bits_legal_T_1; // @[Parameters.scala:92:{33,38}]
wire _source_c_bits_legal_T_3 = _source_c_bits_legal_T_2; // @[Parameters.scala:684:29]
wire [28:0] _source_c_bits_legal_T_4 = {cam_a_0_bits_address[28:14], cam_a_0_bits_address[13:0] ^ 14'h3000}; // @[AtomicAutomata.scala:83:24]
wire [29:0] _source_c_bits_legal_T_5 = {1'h0, _source_c_bits_legal_T_4}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _source_c_bits_legal_T_6 = _source_c_bits_legal_T_5 & 30'h1A113000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _source_c_bits_legal_T_7 = _source_c_bits_legal_T_6; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_8 = _source_c_bits_legal_T_7 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire _source_c_bits_legal_T_9 = _source_c_bits_legal_T_3 & _source_c_bits_legal_T_8; // @[Parameters.scala:684:{29,54}]
wire _source_c_bits_legal_T_57 = _source_c_bits_legal_T_9; // @[Parameters.scala:684:54, :686:26]
wire _source_c_bits_legal_T_11 = cam_a_0_bits_size < 4'h7; // @[AtomicAutomata.scala:83:24]
wire _source_c_bits_legal_T_12 = _source_c_bits_legal_T_11; // @[Parameters.scala:92:{33,38}]
wire _source_c_bits_legal_T_13 = _source_c_bits_legal_T_12; // @[Parameters.scala:684:29]
wire [29:0] _source_c_bits_legal_T_15 = {1'h0, _source_c_bits_legal_T_14}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _source_c_bits_legal_T_16 = _source_c_bits_legal_T_15 & 30'h1A112000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _source_c_bits_legal_T_17 = _source_c_bits_legal_T_16; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_18 = _source_c_bits_legal_T_17 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] _source_c_bits_legal_T_19 = {cam_a_0_bits_address[28:21], cam_a_0_bits_address[20:0] ^ 21'h100000}; // @[AtomicAutomata.scala:83:24]
wire [29:0] _source_c_bits_legal_T_20 = {1'h0, _source_c_bits_legal_T_19}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _source_c_bits_legal_T_21 = _source_c_bits_legal_T_20 & 30'h1A103000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _source_c_bits_legal_T_22 = _source_c_bits_legal_T_21; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_23 = _source_c_bits_legal_T_22 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] _source_c_bits_legal_T_24 = {cam_a_0_bits_address[28:26], cam_a_0_bits_address[25:0] ^ 26'h2000000}; // @[AtomicAutomata.scala:83:24]
wire [29:0] _source_c_bits_legal_T_25 = {1'h0, _source_c_bits_legal_T_24}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _source_c_bits_legal_T_26 = _source_c_bits_legal_T_25 & 30'h1A110000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _source_c_bits_legal_T_27 = _source_c_bits_legal_T_26; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_28 = _source_c_bits_legal_T_27 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] _source_c_bits_legal_T_29 = {cam_a_0_bits_address[28:26], cam_a_0_bits_address[25:0] ^ 26'h2010000}; // @[AtomicAutomata.scala:83:24]
wire [29:0] _source_c_bits_legal_T_30 = {1'h0, _source_c_bits_legal_T_29}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _source_c_bits_legal_T_31 = _source_c_bits_legal_T_30 & 30'h1A113000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _source_c_bits_legal_T_32 = _source_c_bits_legal_T_31; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_33 = _source_c_bits_legal_T_32 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] _source_c_bits_legal_T_34 = {cam_a_0_bits_address[28], cam_a_0_bits_address[27:0] ^ 28'h8000000}; // @[AtomicAutomata.scala:83:24]
wire [29:0] _source_c_bits_legal_T_35 = {1'h0, _source_c_bits_legal_T_34}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _source_c_bits_legal_T_36 = _source_c_bits_legal_T_35 & 30'h18000000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _source_c_bits_legal_T_37 = _source_c_bits_legal_T_36; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_38 = _source_c_bits_legal_T_37 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] _source_c_bits_legal_T_39 = cam_a_0_bits_address ^ 29'h10000000; // @[AtomicAutomata.scala:83:24]
wire [29:0] _source_c_bits_legal_T_40 = {1'h0, _source_c_bits_legal_T_39}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _source_c_bits_legal_T_41 = _source_c_bits_legal_T_40 & 30'h1A113000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _source_c_bits_legal_T_42 = _source_c_bits_legal_T_41; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_43 = _source_c_bits_legal_T_42 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire _source_c_bits_legal_T_44 = _source_c_bits_legal_T_18 | _source_c_bits_legal_T_23; // @[Parameters.scala:685:42]
wire _source_c_bits_legal_T_45 = _source_c_bits_legal_T_44 | _source_c_bits_legal_T_28; // @[Parameters.scala:685:42]
wire _source_c_bits_legal_T_46 = _source_c_bits_legal_T_45 | _source_c_bits_legal_T_33; // @[Parameters.scala:685:42]
wire _source_c_bits_legal_T_47 = _source_c_bits_legal_T_46 | _source_c_bits_legal_T_38; // @[Parameters.scala:685:42]
wire _source_c_bits_legal_T_48 = _source_c_bits_legal_T_47 | _source_c_bits_legal_T_43; // @[Parameters.scala:685:42]
wire _source_c_bits_legal_T_49 = _source_c_bits_legal_T_13 & _source_c_bits_legal_T_48; // @[Parameters.scala:684:{29,54}, :685:42]
wire [28:0] _source_c_bits_legal_T_51 = {cam_a_0_bits_address[28:17], cam_a_0_bits_address[16:0] ^ 17'h10000}; // @[AtomicAutomata.scala:83:24]
wire [29:0] _source_c_bits_legal_T_52 = {1'h0, _source_c_bits_legal_T_51}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _source_c_bits_legal_T_53 = _source_c_bits_legal_T_52 & 30'h1A110000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _source_c_bits_legal_T_54 = _source_c_bits_legal_T_53; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_55 = _source_c_bits_legal_T_54 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire _source_c_bits_legal_T_58 = _source_c_bits_legal_T_57 | _source_c_bits_legal_T_49; // @[Parameters.scala:684:54, :686:26]
wire source_c_bits_legal = _source_c_bits_legal_T_58; // @[Parameters.scala:686:26]
assign source_c_bits_size = source_c_bits_a_size; // @[Edges.scala:480:17]
assign source_c_bits_source = source_c_bits_a_source; // @[Edges.scala:480:17]
assign source_c_bits_address = source_c_bits_a_address; // @[Edges.scala:480:17]
wire [7:0] _source_c_bits_a_mask_T; // @[Misc.scala:222:10]
assign source_c_bits_mask = source_c_bits_a_mask; // @[Edges.scala:480:17]
assign source_c_bits_data = source_c_bits_a_data; // @[Edges.scala:480:17]
assign source_c_bits_corrupt = source_c_bits_a_corrupt; // @[Edges.scala:480:17]
wire [1:0] source_c_bits_a_mask_sizeOH_shiftAmount = _source_c_bits_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _source_c_bits_a_mask_sizeOH_T_1 = 4'h1 << source_c_bits_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _source_c_bits_a_mask_sizeOH_T_2 = _source_c_bits_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] source_c_bits_a_mask_sizeOH = {_source_c_bits_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire source_c_bits_a_mask_sub_sub_sub_0_1 = cam_a_0_bits_size > 4'h2; // @[Misc.scala:206:21]
wire source_c_bits_a_mask_sub_sub_size = source_c_bits_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire source_c_bits_a_mask_sub_sub_bit = cam_a_0_bits_address[2]; // @[Misc.scala:210:26]
wire source_c_bits_a_mask_sub_sub_1_2 = source_c_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire source_c_bits_a_mask_sub_sub_nbit = ~source_c_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire source_c_bits_a_mask_sub_sub_0_2 = source_c_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _source_c_bits_a_mask_sub_sub_acc_T = source_c_bits_a_mask_sub_sub_size & source_c_bits_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_sub_sub_0_1 = source_c_bits_a_mask_sub_sub_sub_0_1 | _source_c_bits_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _source_c_bits_a_mask_sub_sub_acc_T_1 = source_c_bits_a_mask_sub_sub_size & source_c_bits_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_sub_sub_1_1 = source_c_bits_a_mask_sub_sub_sub_0_1 | _source_c_bits_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire source_c_bits_a_mask_sub_size = source_c_bits_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire source_c_bits_a_mask_sub_bit = cam_a_0_bits_address[1]; // @[Misc.scala:210:26]
wire source_c_bits_a_mask_sub_nbit = ~source_c_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire source_c_bits_a_mask_sub_0_2 = source_c_bits_a_mask_sub_sub_0_2 & source_c_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _source_c_bits_a_mask_sub_acc_T = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_sub_0_1 = source_c_bits_a_mask_sub_sub_0_1 | _source_c_bits_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_sub_1_2 = source_c_bits_a_mask_sub_sub_0_2 & source_c_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _source_c_bits_a_mask_sub_acc_T_1 = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_sub_1_1 = source_c_bits_a_mask_sub_sub_0_1 | _source_c_bits_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_sub_2_2 = source_c_bits_a_mask_sub_sub_1_2 & source_c_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _source_c_bits_a_mask_sub_acc_T_2 = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_sub_2_1 = source_c_bits_a_mask_sub_sub_1_1 | _source_c_bits_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_sub_3_2 = source_c_bits_a_mask_sub_sub_1_2 & source_c_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _source_c_bits_a_mask_sub_acc_T_3 = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_sub_3_1 = source_c_bits_a_mask_sub_sub_1_1 | _source_c_bits_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_size = source_c_bits_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire source_c_bits_a_mask_bit = cam_a_0_bits_address[0]; // @[Misc.scala:210:26]
wire source_c_bits_a_mask_nbit = ~source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire source_c_bits_a_mask_eq = source_c_bits_a_mask_sub_0_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _source_c_bits_a_mask_acc_T = source_c_bits_a_mask_size & source_c_bits_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc = source_c_bits_a_mask_sub_0_1 | _source_c_bits_a_mask_acc_T; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_eq_1 = source_c_bits_a_mask_sub_0_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _source_c_bits_a_mask_acc_T_1 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc_1 = source_c_bits_a_mask_sub_0_1 | _source_c_bits_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_eq_2 = source_c_bits_a_mask_sub_1_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _source_c_bits_a_mask_acc_T_2 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc_2 = source_c_bits_a_mask_sub_1_1 | _source_c_bits_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_eq_3 = source_c_bits_a_mask_sub_1_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _source_c_bits_a_mask_acc_T_3 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc_3 = source_c_bits_a_mask_sub_1_1 | _source_c_bits_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_eq_4 = source_c_bits_a_mask_sub_2_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _source_c_bits_a_mask_acc_T_4 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc_4 = source_c_bits_a_mask_sub_2_1 | _source_c_bits_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_eq_5 = source_c_bits_a_mask_sub_2_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _source_c_bits_a_mask_acc_T_5 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc_5 = source_c_bits_a_mask_sub_2_1 | _source_c_bits_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_eq_6 = source_c_bits_a_mask_sub_3_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _source_c_bits_a_mask_acc_T_6 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc_6 = source_c_bits_a_mask_sub_3_1 | _source_c_bits_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_eq_7 = source_c_bits_a_mask_sub_3_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _source_c_bits_a_mask_acc_T_7 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc_7 = source_c_bits_a_mask_sub_3_1 | _source_c_bits_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] source_c_bits_a_mask_lo_lo = {source_c_bits_a_mask_acc_1, source_c_bits_a_mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] source_c_bits_a_mask_lo_hi = {source_c_bits_a_mask_acc_3, source_c_bits_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] source_c_bits_a_mask_lo = {source_c_bits_a_mask_lo_hi, source_c_bits_a_mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] source_c_bits_a_mask_hi_lo = {source_c_bits_a_mask_acc_5, source_c_bits_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] source_c_bits_a_mask_hi_hi = {source_c_bits_a_mask_acc_7, source_c_bits_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] source_c_bits_a_mask_hi = {source_c_bits_a_mask_hi_hi, source_c_bits_a_mask_hi_lo}; // @[Misc.scala:222:10]
assign _source_c_bits_a_mask_T = {source_c_bits_a_mask_hi, source_c_bits_a_mask_lo}; // @[Misc.scala:222:10]
assign source_c_bits_a_mask = _source_c_bits_a_mask_T; // @[Misc.scala:222:10]
wire [26:0] _decode_T = 27'hFFF << nodeIn_a_bits_size; // @[package.scala:243:71]
wire [11:0] _decode_T_1 = _decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _decode_T_2 = ~_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] decode = _decode_T_2[11:3]; // @[package.scala:243:46]
wire _opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire opdata = ~_opdata_T; // @[Edges.scala:92:{28,37}]
reg [8:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch = idle & nodeOut_a_ready; // @[Arbiter.scala:61:28, :62:24]
wire [1:0] _readys_T = {source_i_valid, source_c_valid}; // @[AtomicAutomata.scala:154:28, :165:28]
wire [2:0] _readys_T_1 = {_readys_T, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_T_2 = _readys_T_1[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_T_3 = _readys_T | _readys_T_2; // @[package.scala:253:{43,53}]
wire [1:0] _readys_T_4 = _readys_T_3; // @[package.scala:253:43, :254:17]
wire [2:0] _readys_T_5 = {_readys_T_4, 1'h0}; // @[package.scala:254:17]
wire [1:0] _readys_T_6 = _readys_T_5[1:0]; // @[Arbiter.scala:16:{78,83}]
wire [1:0] _readys_T_7 = ~_readys_T_6; // @[Arbiter.scala:16:{61,83}]
wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:16:61, :68:76]
wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:16:61, :68:76]
wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}]
wire _winner_T = readys_0 & source_c_valid; // @[AtomicAutomata.scala:165:28]
wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_1 = readys_1 & source_i_valid; // @[AtomicAutomata.scala:154:28]
wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48]
wire _nodeOut_a_valid_T = source_c_valid | source_i_valid; // @[AtomicAutomata.scala:154:28, :165:28] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_152 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_260
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_152( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_260 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_34 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0)
node _source_ok_T = shr(io.in.a.bits.source, 4)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits = bits(_uncommonBits_T, 3, 0)
node _T_4 = shr(io.in.a.bits.source, 4)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<4>(0h9))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<8>(0hc0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<9>(0hc0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0)
node _T_24 = shr(io.in.a.bits.source, 4)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<4>(0h9))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_39 = cvt(_T_38)
node _T_40 = and(_T_39, asSInt(UInt<29>(0h10000000)))
node _T_41 = asSInt(_T_40)
node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0)))
node _T_43 = or(_T_37, _T_42)
node _T_44 = and(_T_32, _T_43)
node _T_45 = or(UInt<1>(0h0), _T_44)
node _T_46 = and(_T_31, _T_45)
node _T_47 = asUInt(reset)
node _T_48 = eq(_T_47, UInt<1>(0h0))
when _T_48 :
node _T_49 = eq(_T_46, UInt<1>(0h0))
when _T_49 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_46, UInt<1>(0h1), "") : assert_2
node _T_50 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_51 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_52 = and(_T_50, _T_51)
node _T_53 = or(UInt<1>(0h0), _T_52)
node _T_54 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_55 = cvt(_T_54)
node _T_56 = and(_T_55, asSInt(UInt<17>(0h10000)))
node _T_57 = asSInt(_T_56)
node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0)))
node _T_59 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_60 = cvt(_T_59)
node _T_61 = and(_T_60, asSInt(UInt<29>(0h10000000)))
node _T_62 = asSInt(_T_61)
node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0)))
node _T_64 = or(_T_58, _T_63)
node _T_65 = and(_T_53, _T_64)
node _T_66 = or(UInt<1>(0h0), _T_65)
node _T_67 = and(UInt<1>(0h0), _T_66)
node _T_68 = asUInt(reset)
node _T_69 = eq(_T_68, UInt<1>(0h0))
when _T_69 :
node _T_70 = eq(_T_67, UInt<1>(0h0))
when _T_70 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_67, UInt<1>(0h1), "") : assert_3
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_74 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_74, UInt<1>(0h1), "") : assert_5
node _T_78 = asUInt(reset)
node _T_79 = eq(_T_78, UInt<1>(0h0))
when _T_79 :
node _T_80 = eq(is_aligned, UInt<1>(0h0))
when _T_80 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_81 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_82 = asUInt(reset)
node _T_83 = eq(_T_82, UInt<1>(0h0))
when _T_83 :
node _T_84 = eq(_T_81, UInt<1>(0h0))
when _T_84 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_81, UInt<1>(0h1), "") : assert_7
node _T_85 = not(io.in.a.bits.mask)
node _T_86 = eq(_T_85, UInt<1>(0h0))
node _T_87 = asUInt(reset)
node _T_88 = eq(_T_87, UInt<1>(0h0))
when _T_88 :
node _T_89 = eq(_T_86, UInt<1>(0h0))
when _T_89 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_86, UInt<1>(0h1), "") : assert_8
node _T_90 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_91 = asUInt(reset)
node _T_92 = eq(_T_91, UInt<1>(0h0))
when _T_92 :
node _T_93 = eq(_T_90, UInt<1>(0h0))
when _T_93 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_90, UInt<1>(0h1), "") : assert_9
node _T_94 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_94 :
node _T_95 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_96 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_97 = and(_T_95, _T_96)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0)
node _T_98 = shr(io.in.a.bits.source, 4)
node _T_99 = eq(_T_98, UInt<1>(0h0))
node _T_100 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_101 = and(_T_99, _T_100)
node _T_102 = leq(uncommonBits_2, UInt<4>(0h9))
node _T_103 = and(_T_101, _T_102)
node _T_104 = and(_T_97, _T_103)
node _T_105 = or(UInt<1>(0h0), _T_104)
node _T_106 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_107 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_108 = cvt(_T_107)
node _T_109 = and(_T_108, asSInt(UInt<17>(0h10000)))
node _T_110 = asSInt(_T_109)
node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0)))
node _T_112 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_113 = cvt(_T_112)
node _T_114 = and(_T_113, asSInt(UInt<29>(0h10000000)))
node _T_115 = asSInt(_T_114)
node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0)))
node _T_117 = or(_T_111, _T_116)
node _T_118 = and(_T_106, _T_117)
node _T_119 = or(UInt<1>(0h0), _T_118)
node _T_120 = and(_T_105, _T_119)
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_T_120, UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_120, UInt<1>(0h1), "") : assert_10
node _T_124 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_125 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_126 = and(_T_124, _T_125)
node _T_127 = or(UInt<1>(0h0), _T_126)
node _T_128 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_129 = cvt(_T_128)
node _T_130 = and(_T_129, asSInt(UInt<17>(0h10000)))
node _T_131 = asSInt(_T_130)
node _T_132 = eq(_T_131, asSInt(UInt<1>(0h0)))
node _T_133 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_134 = cvt(_T_133)
node _T_135 = and(_T_134, asSInt(UInt<29>(0h10000000)))
node _T_136 = asSInt(_T_135)
node _T_137 = eq(_T_136, asSInt(UInt<1>(0h0)))
node _T_138 = or(_T_132, _T_137)
node _T_139 = and(_T_127, _T_138)
node _T_140 = or(UInt<1>(0h0), _T_139)
node _T_141 = and(UInt<1>(0h0), _T_140)
node _T_142 = asUInt(reset)
node _T_143 = eq(_T_142, UInt<1>(0h0))
when _T_143 :
node _T_144 = eq(_T_141, UInt<1>(0h0))
when _T_144 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_141, UInt<1>(0h1), "") : assert_11
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_148 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_T_148, UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_148, UInt<1>(0h1), "") : assert_13
node _T_152 = asUInt(reset)
node _T_153 = eq(_T_152, UInt<1>(0h0))
when _T_153 :
node _T_154 = eq(is_aligned, UInt<1>(0h0))
when _T_154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_155 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_155, UInt<1>(0h1), "") : assert_15
node _T_159 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_159, UInt<1>(0h1), "") : assert_16
node _T_163 = not(io.in.a.bits.mask)
node _T_164 = eq(_T_163, UInt<1>(0h0))
node _T_165 = asUInt(reset)
node _T_166 = eq(_T_165, UInt<1>(0h0))
when _T_166 :
node _T_167 = eq(_T_164, UInt<1>(0h0))
when _T_167 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_164, UInt<1>(0h1), "") : assert_17
node _T_168 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_169 = asUInt(reset)
node _T_170 = eq(_T_169, UInt<1>(0h0))
when _T_170 :
node _T_171 = eq(_T_168, UInt<1>(0h0))
when _T_171 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_168, UInt<1>(0h1), "") : assert_18
node _T_172 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_172 :
node _T_173 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_174 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_175 = and(_T_173, _T_174)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0)
node _T_176 = shr(io.in.a.bits.source, 4)
node _T_177 = eq(_T_176, UInt<1>(0h0))
node _T_178 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_179 = and(_T_177, _T_178)
node _T_180 = leq(uncommonBits_3, UInt<4>(0h9))
node _T_181 = and(_T_179, _T_180)
node _T_182 = and(_T_175, _T_181)
node _T_183 = or(UInt<1>(0h0), _T_182)
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_183, UInt<1>(0h1), "") : assert_19
node _T_187 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_188 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_189 = and(_T_187, _T_188)
node _T_190 = or(UInt<1>(0h0), _T_189)
node _T_191 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_192 = cvt(_T_191)
node _T_193 = and(_T_192, asSInt(UInt<17>(0h10000)))
node _T_194 = asSInt(_T_193)
node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0)))
node _T_196 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_197 = cvt(_T_196)
node _T_198 = and(_T_197, asSInt(UInt<29>(0h10000000)))
node _T_199 = asSInt(_T_198)
node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0)))
node _T_201 = or(_T_195, _T_200)
node _T_202 = and(_T_190, _T_201)
node _T_203 = or(UInt<1>(0h0), _T_202)
node _T_204 = asUInt(reset)
node _T_205 = eq(_T_204, UInt<1>(0h0))
when _T_205 :
node _T_206 = eq(_T_203, UInt<1>(0h0))
when _T_206 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_203, UInt<1>(0h1), "") : assert_20
node _T_207 = asUInt(reset)
node _T_208 = eq(_T_207, UInt<1>(0h0))
when _T_208 :
node _T_209 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_209 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_210 = asUInt(reset)
node _T_211 = eq(_T_210, UInt<1>(0h0))
when _T_211 :
node _T_212 = eq(is_aligned, UInt<1>(0h0))
when _T_212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_213 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_214 = asUInt(reset)
node _T_215 = eq(_T_214, UInt<1>(0h0))
when _T_215 :
node _T_216 = eq(_T_213, UInt<1>(0h0))
when _T_216 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_213, UInt<1>(0h1), "") : assert_23
node _T_217 = eq(io.in.a.bits.mask, mask)
node _T_218 = asUInt(reset)
node _T_219 = eq(_T_218, UInt<1>(0h0))
when _T_219 :
node _T_220 = eq(_T_217, UInt<1>(0h0))
when _T_220 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_217, UInt<1>(0h1), "") : assert_24
node _T_221 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_T_221, UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_221, UInt<1>(0h1), "") : assert_25
node _T_225 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_225 :
node _T_226 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_227 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_228 = and(_T_226, _T_227)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0)
node _T_229 = shr(io.in.a.bits.source, 4)
node _T_230 = eq(_T_229, UInt<1>(0h0))
node _T_231 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_232 = and(_T_230, _T_231)
node _T_233 = leq(uncommonBits_4, UInt<4>(0h9))
node _T_234 = and(_T_232, _T_233)
node _T_235 = and(_T_228, _T_234)
node _T_236 = or(UInt<1>(0h0), _T_235)
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_239 = and(_T_237, _T_238)
node _T_240 = or(UInt<1>(0h0), _T_239)
node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_242 = cvt(_T_241)
node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000)))
node _T_244 = asSInt(_T_243)
node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0)))
node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_247 = cvt(_T_246)
node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000)))
node _T_249 = asSInt(_T_248)
node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0)))
node _T_251 = or(_T_245, _T_250)
node _T_252 = and(_T_240, _T_251)
node _T_253 = or(UInt<1>(0h0), _T_252)
node _T_254 = and(_T_236, _T_253)
node _T_255 = asUInt(reset)
node _T_256 = eq(_T_255, UInt<1>(0h0))
when _T_256 :
node _T_257 = eq(_T_254, UInt<1>(0h0))
when _T_257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_254, UInt<1>(0h1), "") : assert_26
node _T_258 = asUInt(reset)
node _T_259 = eq(_T_258, UInt<1>(0h0))
when _T_259 :
node _T_260 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_260 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(is_aligned, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_264 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_265 = asUInt(reset)
node _T_266 = eq(_T_265, UInt<1>(0h0))
when _T_266 :
node _T_267 = eq(_T_264, UInt<1>(0h0))
when _T_267 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_264, UInt<1>(0h1), "") : assert_29
node _T_268 = eq(io.in.a.bits.mask, mask)
node _T_269 = asUInt(reset)
node _T_270 = eq(_T_269, UInt<1>(0h0))
when _T_270 :
node _T_271 = eq(_T_268, UInt<1>(0h0))
when _T_271 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_268, UInt<1>(0h1), "") : assert_30
node _T_272 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_272 :
node _T_273 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_274 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_275 = and(_T_273, _T_274)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0)
node _T_276 = shr(io.in.a.bits.source, 4)
node _T_277 = eq(_T_276, UInt<1>(0h0))
node _T_278 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_279 = and(_T_277, _T_278)
node _T_280 = leq(uncommonBits_5, UInt<4>(0h9))
node _T_281 = and(_T_279, _T_280)
node _T_282 = and(_T_275, _T_281)
node _T_283 = or(UInt<1>(0h0), _T_282)
node _T_284 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_285 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_286 = and(_T_284, _T_285)
node _T_287 = or(UInt<1>(0h0), _T_286)
node _T_288 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_289 = cvt(_T_288)
node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000)))
node _T_291 = asSInt(_T_290)
node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0)))
node _T_293 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_294 = cvt(_T_293)
node _T_295 = and(_T_294, asSInt(UInt<29>(0h10000000)))
node _T_296 = asSInt(_T_295)
node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0)))
node _T_298 = or(_T_292, _T_297)
node _T_299 = and(_T_287, _T_298)
node _T_300 = or(UInt<1>(0h0), _T_299)
node _T_301 = and(_T_283, _T_300)
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_301, UInt<1>(0h1), "") : assert_31
node _T_305 = asUInt(reset)
node _T_306 = eq(_T_305, UInt<1>(0h0))
when _T_306 :
node _T_307 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_307 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_308 = asUInt(reset)
node _T_309 = eq(_T_308, UInt<1>(0h0))
when _T_309 :
node _T_310 = eq(is_aligned, UInt<1>(0h0))
when _T_310 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_311 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_312 = asUInt(reset)
node _T_313 = eq(_T_312, UInt<1>(0h0))
when _T_313 :
node _T_314 = eq(_T_311, UInt<1>(0h0))
when _T_314 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_311, UInt<1>(0h1), "") : assert_34
node _T_315 = not(mask)
node _T_316 = and(io.in.a.bits.mask, _T_315)
node _T_317 = eq(_T_316, UInt<1>(0h0))
node _T_318 = asUInt(reset)
node _T_319 = eq(_T_318, UInt<1>(0h0))
when _T_319 :
node _T_320 = eq(_T_317, UInt<1>(0h0))
when _T_320 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_317, UInt<1>(0h1), "") : assert_35
node _T_321 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_321 :
node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_323 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_324 = and(_T_322, _T_323)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0)
node _T_325 = shr(io.in.a.bits.source, 4)
node _T_326 = eq(_T_325, UInt<1>(0h0))
node _T_327 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_328 = and(_T_326, _T_327)
node _T_329 = leq(uncommonBits_6, UInt<4>(0h9))
node _T_330 = and(_T_328, _T_329)
node _T_331 = and(_T_324, _T_330)
node _T_332 = or(UInt<1>(0h0), _T_331)
node _T_333 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_334 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_335 = cvt(_T_334)
node _T_336 = and(_T_335, asSInt(UInt<17>(0h10000)))
node _T_337 = asSInt(_T_336)
node _T_338 = eq(_T_337, asSInt(UInt<1>(0h0)))
node _T_339 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_340 = cvt(_T_339)
node _T_341 = and(_T_340, asSInt(UInt<29>(0h10000000)))
node _T_342 = asSInt(_T_341)
node _T_343 = eq(_T_342, asSInt(UInt<1>(0h0)))
node _T_344 = or(_T_338, _T_343)
node _T_345 = and(_T_333, _T_344)
node _T_346 = or(UInt<1>(0h0), _T_345)
node _T_347 = and(_T_332, _T_346)
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_347, UInt<1>(0h1), "") : assert_36
node _T_351 = asUInt(reset)
node _T_352 = eq(_T_351, UInt<1>(0h0))
when _T_352 :
node _T_353 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_353 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_354 = asUInt(reset)
node _T_355 = eq(_T_354, UInt<1>(0h0))
when _T_355 :
node _T_356 = eq(is_aligned, UInt<1>(0h0))
when _T_356 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_357 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_358 = asUInt(reset)
node _T_359 = eq(_T_358, UInt<1>(0h0))
when _T_359 :
node _T_360 = eq(_T_357, UInt<1>(0h0))
when _T_360 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_357, UInt<1>(0h1), "") : assert_39
node _T_361 = eq(io.in.a.bits.mask, mask)
node _T_362 = asUInt(reset)
node _T_363 = eq(_T_362, UInt<1>(0h0))
when _T_363 :
node _T_364 = eq(_T_361, UInt<1>(0h0))
when _T_364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_361, UInt<1>(0h1), "") : assert_40
node _T_365 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_365 :
node _T_366 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_367 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_368 = and(_T_366, _T_367)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0)
node _T_369 = shr(io.in.a.bits.source, 4)
node _T_370 = eq(_T_369, UInt<1>(0h0))
node _T_371 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_372 = and(_T_370, _T_371)
node _T_373 = leq(uncommonBits_7, UInt<4>(0h9))
node _T_374 = and(_T_372, _T_373)
node _T_375 = and(_T_368, _T_374)
node _T_376 = or(UInt<1>(0h0), _T_375)
node _T_377 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_378 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_379 = cvt(_T_378)
node _T_380 = and(_T_379, asSInt(UInt<17>(0h10000)))
node _T_381 = asSInt(_T_380)
node _T_382 = eq(_T_381, asSInt(UInt<1>(0h0)))
node _T_383 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_384 = cvt(_T_383)
node _T_385 = and(_T_384, asSInt(UInt<29>(0h10000000)))
node _T_386 = asSInt(_T_385)
node _T_387 = eq(_T_386, asSInt(UInt<1>(0h0)))
node _T_388 = or(_T_382, _T_387)
node _T_389 = and(_T_377, _T_388)
node _T_390 = or(UInt<1>(0h0), _T_389)
node _T_391 = and(_T_376, _T_390)
node _T_392 = asUInt(reset)
node _T_393 = eq(_T_392, UInt<1>(0h0))
when _T_393 :
node _T_394 = eq(_T_391, UInt<1>(0h0))
when _T_394 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_391, UInt<1>(0h1), "") : assert_41
node _T_395 = asUInt(reset)
node _T_396 = eq(_T_395, UInt<1>(0h0))
when _T_396 :
node _T_397 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_397 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(is_aligned, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_401 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_T_401, UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_401, UInt<1>(0h1), "") : assert_44
node _T_405 = eq(io.in.a.bits.mask, mask)
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_405, UInt<1>(0h1), "") : assert_45
node _T_409 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_409 :
node _T_410 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_411 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_412 = and(_T_410, _T_411)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0)
node _T_413 = shr(io.in.a.bits.source, 4)
node _T_414 = eq(_T_413, UInt<1>(0h0))
node _T_415 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_416 = and(_T_414, _T_415)
node _T_417 = leq(uncommonBits_8, UInt<4>(0h9))
node _T_418 = and(_T_416, _T_417)
node _T_419 = and(_T_412, _T_418)
node _T_420 = or(UInt<1>(0h0), _T_419)
node _T_421 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_422 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_423 = cvt(_T_422)
node _T_424 = and(_T_423, asSInt(UInt<17>(0h10000)))
node _T_425 = asSInt(_T_424)
node _T_426 = eq(_T_425, asSInt(UInt<1>(0h0)))
node _T_427 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_428 = cvt(_T_427)
node _T_429 = and(_T_428, asSInt(UInt<29>(0h10000000)))
node _T_430 = asSInt(_T_429)
node _T_431 = eq(_T_430, asSInt(UInt<1>(0h0)))
node _T_432 = or(_T_426, _T_431)
node _T_433 = and(_T_421, _T_432)
node _T_434 = or(UInt<1>(0h0), _T_433)
node _T_435 = and(_T_420, _T_434)
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_435, UInt<1>(0h1), "") : assert_46
node _T_439 = asUInt(reset)
node _T_440 = eq(_T_439, UInt<1>(0h0))
when _T_440 :
node _T_441 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_441 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_442 = asUInt(reset)
node _T_443 = eq(_T_442, UInt<1>(0h0))
when _T_443 :
node _T_444 = eq(is_aligned, UInt<1>(0h0))
when _T_444 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_445 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_445, UInt<1>(0h1), "") : assert_49
node _T_449 = eq(io.in.a.bits.mask, mask)
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_T_449, UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_449, UInt<1>(0h1), "") : assert_50
node _T_453 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_454 = asUInt(reset)
node _T_455 = eq(_T_454, UInt<1>(0h0))
when _T_455 :
node _T_456 = eq(_T_453, UInt<1>(0h0))
when _T_456 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_453, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_457 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_458 = asUInt(reset)
node _T_459 = eq(_T_458, UInt<1>(0h0))
when _T_459 :
node _T_460 = eq(_T_457, UInt<1>(0h0))
when _T_460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_457, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 4)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_461 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_461 :
node _T_462 = asUInt(reset)
node _T_463 = eq(_T_462, UInt<1>(0h0))
when _T_463 :
node _T_464 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_464 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_465 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_466 = asUInt(reset)
node _T_467 = eq(_T_466, UInt<1>(0h0))
when _T_467 :
node _T_468 = eq(_T_465, UInt<1>(0h0))
when _T_468 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_465, UInt<1>(0h1), "") : assert_54
node _T_469 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_469, UInt<1>(0h1), "") : assert_55
node _T_473 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_474 = asUInt(reset)
node _T_475 = eq(_T_474, UInt<1>(0h0))
when _T_475 :
node _T_476 = eq(_T_473, UInt<1>(0h0))
when _T_476 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_473, UInt<1>(0h1), "") : assert_56
node _T_477 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_478 = asUInt(reset)
node _T_479 = eq(_T_478, UInt<1>(0h0))
when _T_479 :
node _T_480 = eq(_T_477, UInt<1>(0h0))
when _T_480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_477, UInt<1>(0h1), "") : assert_57
node _T_481 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_481 :
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_485 = asUInt(reset)
node _T_486 = eq(_T_485, UInt<1>(0h0))
when _T_486 :
node _T_487 = eq(sink_ok, UInt<1>(0h0))
when _T_487 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_488 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_488, UInt<1>(0h1), "") : assert_60
node _T_492 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_493 = asUInt(reset)
node _T_494 = eq(_T_493, UInt<1>(0h0))
when _T_494 :
node _T_495 = eq(_T_492, UInt<1>(0h0))
when _T_495 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_492, UInt<1>(0h1), "") : assert_61
node _T_496 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_497 = asUInt(reset)
node _T_498 = eq(_T_497, UInt<1>(0h0))
when _T_498 :
node _T_499 = eq(_T_496, UInt<1>(0h0))
when _T_499 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_496, UInt<1>(0h1), "") : assert_62
node _T_500 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_501 = asUInt(reset)
node _T_502 = eq(_T_501, UInt<1>(0h0))
when _T_502 :
node _T_503 = eq(_T_500, UInt<1>(0h0))
when _T_503 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_500, UInt<1>(0h1), "") : assert_63
node _T_504 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_505 = or(UInt<1>(0h1), _T_504)
node _T_506 = asUInt(reset)
node _T_507 = eq(_T_506, UInt<1>(0h0))
when _T_507 :
node _T_508 = eq(_T_505, UInt<1>(0h0))
when _T_508 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_505, UInt<1>(0h1), "") : assert_64
node _T_509 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_509 :
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_513 = asUInt(reset)
node _T_514 = eq(_T_513, UInt<1>(0h0))
when _T_514 :
node _T_515 = eq(sink_ok, UInt<1>(0h0))
when _T_515 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_516 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_517 = asUInt(reset)
node _T_518 = eq(_T_517, UInt<1>(0h0))
when _T_518 :
node _T_519 = eq(_T_516, UInt<1>(0h0))
when _T_519 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_516, UInt<1>(0h1), "") : assert_67
node _T_520 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_521 = asUInt(reset)
node _T_522 = eq(_T_521, UInt<1>(0h0))
when _T_522 :
node _T_523 = eq(_T_520, UInt<1>(0h0))
when _T_523 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_520, UInt<1>(0h1), "") : assert_68
node _T_524 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_525 = asUInt(reset)
node _T_526 = eq(_T_525, UInt<1>(0h0))
when _T_526 :
node _T_527 = eq(_T_524, UInt<1>(0h0))
when _T_527 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_524, UInt<1>(0h1), "") : assert_69
node _T_528 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_529 = or(_T_528, io.in.d.bits.corrupt)
node _T_530 = asUInt(reset)
node _T_531 = eq(_T_530, UInt<1>(0h0))
when _T_531 :
node _T_532 = eq(_T_529, UInt<1>(0h0))
when _T_532 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_529, UInt<1>(0h1), "") : assert_70
node _T_533 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_534 = or(UInt<1>(0h1), _T_533)
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_534, UInt<1>(0h1), "") : assert_71
node _T_538 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_538 :
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_542 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_543 = asUInt(reset)
node _T_544 = eq(_T_543, UInt<1>(0h0))
when _T_544 :
node _T_545 = eq(_T_542, UInt<1>(0h0))
when _T_545 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_542, UInt<1>(0h1), "") : assert_73
node _T_546 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_547 = asUInt(reset)
node _T_548 = eq(_T_547, UInt<1>(0h0))
when _T_548 :
node _T_549 = eq(_T_546, UInt<1>(0h0))
when _T_549 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_546, UInt<1>(0h1), "") : assert_74
node _T_550 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_551 = or(UInt<1>(0h1), _T_550)
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_551, UInt<1>(0h1), "") : assert_75
node _T_555 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_555 :
node _T_556 = asUInt(reset)
node _T_557 = eq(_T_556, UInt<1>(0h0))
when _T_557 :
node _T_558 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_558 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_559 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_560 = asUInt(reset)
node _T_561 = eq(_T_560, UInt<1>(0h0))
when _T_561 :
node _T_562 = eq(_T_559, UInt<1>(0h0))
when _T_562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_559, UInt<1>(0h1), "") : assert_77
node _T_563 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_564 = or(_T_563, io.in.d.bits.corrupt)
node _T_565 = asUInt(reset)
node _T_566 = eq(_T_565, UInt<1>(0h0))
when _T_566 :
node _T_567 = eq(_T_564, UInt<1>(0h0))
when _T_567 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_564, UInt<1>(0h1), "") : assert_78
node _T_568 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_569 = or(UInt<1>(0h1), _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_569, UInt<1>(0h1), "") : assert_79
node _T_573 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_573 :
node _T_574 = asUInt(reset)
node _T_575 = eq(_T_574, UInt<1>(0h0))
when _T_575 :
node _T_576 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_576 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_577 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_578 = asUInt(reset)
node _T_579 = eq(_T_578, UInt<1>(0h0))
when _T_579 :
node _T_580 = eq(_T_577, UInt<1>(0h0))
when _T_580 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_577, UInt<1>(0h1), "") : assert_81
node _T_581 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_582 = asUInt(reset)
node _T_583 = eq(_T_582, UInt<1>(0h0))
when _T_583 :
node _T_584 = eq(_T_581, UInt<1>(0h0))
when _T_584 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_581, UInt<1>(0h1), "") : assert_82
node _T_585 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_586 = or(UInt<1>(0h1), _T_585)
node _T_587 = asUInt(reset)
node _T_588 = eq(_T_587, UInt<1>(0h0))
when _T_588 :
node _T_589 = eq(_T_586, UInt<1>(0h0))
when _T_589 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_586, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<4>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_590 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_591 = asUInt(reset)
node _T_592 = eq(_T_591, UInt<1>(0h0))
when _T_592 :
node _T_593 = eq(_T_590, UInt<1>(0h0))
when _T_593 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_590, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<4>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_594 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_595 = asUInt(reset)
node _T_596 = eq(_T_595, UInt<1>(0h0))
when _T_596 :
node _T_597 = eq(_T_594, UInt<1>(0h0))
when _T_597 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_594, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_598 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_599 = asUInt(reset)
node _T_600 = eq(_T_599, UInt<1>(0h0))
when _T_600 :
node _T_601 = eq(_T_598, UInt<1>(0h0))
when _T_601 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_598, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_602 = eq(a_first, UInt<1>(0h0))
node _T_603 = and(io.in.a.valid, _T_602)
when _T_603 :
node _T_604 = eq(io.in.a.bits.opcode, opcode)
node _T_605 = asUInt(reset)
node _T_606 = eq(_T_605, UInt<1>(0h0))
when _T_606 :
node _T_607 = eq(_T_604, UInt<1>(0h0))
when _T_607 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_604, UInt<1>(0h1), "") : assert_87
node _T_608 = eq(io.in.a.bits.param, param)
node _T_609 = asUInt(reset)
node _T_610 = eq(_T_609, UInt<1>(0h0))
when _T_610 :
node _T_611 = eq(_T_608, UInt<1>(0h0))
when _T_611 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_608, UInt<1>(0h1), "") : assert_88
node _T_612 = eq(io.in.a.bits.size, size)
node _T_613 = asUInt(reset)
node _T_614 = eq(_T_613, UInt<1>(0h0))
when _T_614 :
node _T_615 = eq(_T_612, UInt<1>(0h0))
when _T_615 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_612, UInt<1>(0h1), "") : assert_89
node _T_616 = eq(io.in.a.bits.source, source)
node _T_617 = asUInt(reset)
node _T_618 = eq(_T_617, UInt<1>(0h0))
when _T_618 :
node _T_619 = eq(_T_616, UInt<1>(0h0))
when _T_619 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_616, UInt<1>(0h1), "") : assert_90
node _T_620 = eq(io.in.a.bits.address, address)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_620, UInt<1>(0h1), "") : assert_91
node _T_624 = and(io.in.a.ready, io.in.a.valid)
node _T_625 = and(_T_624, a_first)
when _T_625 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_626 = eq(d_first, UInt<1>(0h0))
node _T_627 = and(io.in.d.valid, _T_626)
when _T_627 :
node _T_628 = eq(io.in.d.bits.opcode, opcode_1)
node _T_629 = asUInt(reset)
node _T_630 = eq(_T_629, UInt<1>(0h0))
when _T_630 :
node _T_631 = eq(_T_628, UInt<1>(0h0))
when _T_631 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_628, UInt<1>(0h1), "") : assert_92
node _T_632 = eq(io.in.d.bits.param, param_1)
node _T_633 = asUInt(reset)
node _T_634 = eq(_T_633, UInt<1>(0h0))
when _T_634 :
node _T_635 = eq(_T_632, UInt<1>(0h0))
when _T_635 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_632, UInt<1>(0h1), "") : assert_93
node _T_636 = eq(io.in.d.bits.size, size_1)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_636, UInt<1>(0h1), "") : assert_94
node _T_640 = eq(io.in.d.bits.source, source_1)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_640, UInt<1>(0h1), "") : assert_95
node _T_644 = eq(io.in.d.bits.sink, sink)
node _T_645 = asUInt(reset)
node _T_646 = eq(_T_645, UInt<1>(0h0))
when _T_646 :
node _T_647 = eq(_T_644, UInt<1>(0h0))
when _T_647 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_644, UInt<1>(0h1), "") : assert_96
node _T_648 = eq(io.in.d.bits.denied, denied)
node _T_649 = asUInt(reset)
node _T_650 = eq(_T_649, UInt<1>(0h0))
when _T_650 :
node _T_651 = eq(_T_648, UInt<1>(0h0))
when _T_651 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_648, UInt<1>(0h1), "") : assert_97
node _T_652 = and(io.in.d.ready, io.in.d.valid)
node _T_653 = and(_T_652, d_first)
when _T_653 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0)
regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0)
regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<10>
connect a_set, UInt<10>(0h0)
wire a_set_wo_ready : UInt<10>
connect a_set_wo_ready, UInt<10>(0h0)
wire a_opcodes_set : UInt<40>
connect a_opcodes_set, UInt<40>(0h0)
wire a_sizes_set : UInt<40>
connect a_sizes_set, UInt<40>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_654 = and(io.in.a.valid, a_first_1)
node _T_655 = and(_T_654, UInt<1>(0h1))
when _T_655 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_656 = and(io.in.a.ready, io.in.a.valid)
node _T_657 = and(_T_656, a_first_1)
node _T_658 = and(_T_657, UInt<1>(0h1))
when _T_658 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_659 = dshr(inflight, io.in.a.bits.source)
node _T_660 = bits(_T_659, 0, 0)
node _T_661 = eq(_T_660, UInt<1>(0h0))
node _T_662 = asUInt(reset)
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(_T_661, UInt<1>(0h0))
when _T_664 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_661, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<10>
connect d_clr, UInt<10>(0h0)
wire d_clr_wo_ready : UInt<10>
connect d_clr_wo_ready, UInt<10>(0h0)
wire d_opcodes_clr : UInt<40>
connect d_opcodes_clr, UInt<40>(0h0)
wire d_sizes_clr : UInt<40>
connect d_sizes_clr, UInt<40>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_665 = and(io.in.d.valid, d_first_1)
node _T_666 = and(_T_665, UInt<1>(0h1))
node _T_667 = eq(d_release_ack, UInt<1>(0h0))
node _T_668 = and(_T_666, _T_667)
when _T_668 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_669 = and(io.in.d.ready, io.in.d.valid)
node _T_670 = and(_T_669, d_first_1)
node _T_671 = and(_T_670, UInt<1>(0h1))
node _T_672 = eq(d_release_ack, UInt<1>(0h0))
node _T_673 = and(_T_671, _T_672)
when _T_673 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_674 = and(io.in.d.valid, d_first_1)
node _T_675 = and(_T_674, UInt<1>(0h1))
node _T_676 = eq(d_release_ack, UInt<1>(0h0))
node _T_677 = and(_T_675, _T_676)
when _T_677 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_678 = dshr(inflight, io.in.d.bits.source)
node _T_679 = bits(_T_678, 0, 0)
node _T_680 = or(_T_679, same_cycle_resp)
node _T_681 = asUInt(reset)
node _T_682 = eq(_T_681, UInt<1>(0h0))
when _T_682 :
node _T_683 = eq(_T_680, UInt<1>(0h0))
when _T_683 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_680, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_684 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_685 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_686 = or(_T_684, _T_685)
node _T_687 = asUInt(reset)
node _T_688 = eq(_T_687, UInt<1>(0h0))
when _T_688 :
node _T_689 = eq(_T_686, UInt<1>(0h0))
when _T_689 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_686, UInt<1>(0h1), "") : assert_100
node _T_690 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_691 = asUInt(reset)
node _T_692 = eq(_T_691, UInt<1>(0h0))
when _T_692 :
node _T_693 = eq(_T_690, UInt<1>(0h0))
when _T_693 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_690, UInt<1>(0h1), "") : assert_101
else :
node _T_694 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_695 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_696 = or(_T_694, _T_695)
node _T_697 = asUInt(reset)
node _T_698 = eq(_T_697, UInt<1>(0h0))
when _T_698 :
node _T_699 = eq(_T_696, UInt<1>(0h0))
when _T_699 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_696, UInt<1>(0h1), "") : assert_102
node _T_700 = eq(io.in.d.bits.size, a_size_lookup)
node _T_701 = asUInt(reset)
node _T_702 = eq(_T_701, UInt<1>(0h0))
when _T_702 :
node _T_703 = eq(_T_700, UInt<1>(0h0))
when _T_703 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_700, UInt<1>(0h1), "") : assert_103
node _T_704 = and(io.in.d.valid, d_first_1)
node _T_705 = and(_T_704, a_first_1)
node _T_706 = and(_T_705, io.in.a.valid)
node _T_707 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_708 = and(_T_706, _T_707)
node _T_709 = eq(d_release_ack, UInt<1>(0h0))
node _T_710 = and(_T_708, _T_709)
when _T_710 :
node _T_711 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_712 = or(_T_711, io.in.a.ready)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_712, UInt<1>(0h1), "") : assert_104
node _T_716 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_717 = orr(a_set_wo_ready)
node _T_718 = eq(_T_717, UInt<1>(0h0))
node _T_719 = or(_T_716, _T_718)
node _T_720 = asUInt(reset)
node _T_721 = eq(_T_720, UInt<1>(0h0))
when _T_721 :
node _T_722 = eq(_T_719, UInt<1>(0h0))
when _T_722 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_719, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_77
node _T_723 = orr(inflight)
node _T_724 = eq(_T_723, UInt<1>(0h0))
node _T_725 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_726 = or(_T_724, _T_725)
node _T_727 = lt(watchdog, plusarg_reader.out)
node _T_728 = or(_T_726, _T_727)
node _T_729 = asUInt(reset)
node _T_730 = eq(_T_729, UInt<1>(0h0))
when _T_730 :
node _T_731 = eq(_T_728, UInt<1>(0h0))
when _T_731 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_728, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_732 = and(io.in.a.ready, io.in.a.valid)
node _T_733 = and(io.in.d.ready, io.in.d.valid)
node _T_734 = or(_T_732, _T_733)
when _T_734 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0)
regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0)
regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<4>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<10>
connect c_set, UInt<10>(0h0)
wire c_set_wo_ready : UInt<10>
connect c_set_wo_ready, UInt<10>(0h0)
wire c_opcodes_set : UInt<40>
connect c_opcodes_set, UInt<40>(0h0)
wire c_sizes_set : UInt<40>
connect c_sizes_set, UInt<40>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<4>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_735 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<4>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_736 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_737 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_738 = and(_T_736, _T_737)
node _T_739 = and(_T_735, _T_738)
when _T_739 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<4>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_740 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_741 = and(_T_740, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<4>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_742 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_743 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_744 = and(_T_742, _T_743)
node _T_745 = and(_T_741, _T_744)
when _T_745 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<4>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_746 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_747 = bits(_T_746, 0, 0)
node _T_748 = eq(_T_747, UInt<1>(0h0))
node _T_749 = asUInt(reset)
node _T_750 = eq(_T_749, UInt<1>(0h0))
when _T_750 :
node _T_751 = eq(_T_748, UInt<1>(0h0))
when _T_751 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_748, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<10>
connect d_clr_1, UInt<10>(0h0)
wire d_clr_wo_ready_1 : UInt<10>
connect d_clr_wo_ready_1, UInt<10>(0h0)
wire d_opcodes_clr_1 : UInt<40>
connect d_opcodes_clr_1, UInt<40>(0h0)
wire d_sizes_clr_1 : UInt<40>
connect d_sizes_clr_1, UInt<40>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_752 = and(io.in.d.valid, d_first_2)
node _T_753 = and(_T_752, UInt<1>(0h1))
node _T_754 = and(_T_753, d_release_ack_1)
when _T_754 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_755 = and(io.in.d.ready, io.in.d.valid)
node _T_756 = and(_T_755, d_first_2)
node _T_757 = and(_T_756, UInt<1>(0h1))
node _T_758 = and(_T_757, d_release_ack_1)
when _T_758 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_759 = and(io.in.d.valid, d_first_2)
node _T_760 = and(_T_759, UInt<1>(0h1))
node _T_761 = and(_T_760, d_release_ack_1)
when _T_761 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_762 = dshr(inflight_1, io.in.d.bits.source)
node _T_763 = bits(_T_762, 0, 0)
node _T_764 = or(_T_763, same_cycle_resp_1)
node _T_765 = asUInt(reset)
node _T_766 = eq(_T_765, UInt<1>(0h0))
when _T_766 :
node _T_767 = eq(_T_764, UInt<1>(0h0))
when _T_767 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_764, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<4>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_768 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_769 = asUInt(reset)
node _T_770 = eq(_T_769, UInt<1>(0h0))
when _T_770 :
node _T_771 = eq(_T_768, UInt<1>(0h0))
when _T_771 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_768, UInt<1>(0h1), "") : assert_109
else :
node _T_772 = eq(io.in.d.bits.size, c_size_lookup)
node _T_773 = asUInt(reset)
node _T_774 = eq(_T_773, UInt<1>(0h0))
when _T_774 :
node _T_775 = eq(_T_772, UInt<1>(0h0))
when _T_775 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_772, UInt<1>(0h1), "") : assert_110
node _T_776 = and(io.in.d.valid, d_first_2)
node _T_777 = and(_T_776, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<4>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_778 = and(_T_777, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<4>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_779 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_780 = and(_T_778, _T_779)
node _T_781 = and(_T_780, d_release_ack_1)
node _T_782 = eq(c_probe_ack, UInt<1>(0h0))
node _T_783 = and(_T_781, _T_782)
when _T_783 :
node _T_784 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<4>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_785 = or(_T_784, _WIRE_23.ready)
node _T_786 = asUInt(reset)
node _T_787 = eq(_T_786, UInt<1>(0h0))
when _T_787 :
node _T_788 = eq(_T_785, UInt<1>(0h0))
when _T_788 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_785, UInt<1>(0h1), "") : assert_111
node _T_789 = orr(c_set_wo_ready)
when _T_789 :
node _T_790 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_791 = asUInt(reset)
node _T_792 = eq(_T_791, UInt<1>(0h0))
when _T_792 :
node _T_793 = eq(_T_790, UInt<1>(0h0))
when _T_793 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_790, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_78
node _T_794 = orr(inflight_1)
node _T_795 = eq(_T_794, UInt<1>(0h0))
node _T_796 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_797 = or(_T_795, _T_796)
node _T_798 = lt(watchdog_1, plusarg_reader_1.out)
node _T_799 = or(_T_797, _T_798)
node _T_800 = asUInt(reset)
node _T_801 = eq(_T_800, UInt<1>(0h0))
when _T_801 :
node _T_802 = eq(_T_799, UInt<1>(0h0))
when _T_802 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_799, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<4>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_803 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_804 = and(io.in.d.ready, io.in.d.valid)
node _T_805 = or(_T_803, _T_804)
when _T_805 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_34( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [3:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [3:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [9:0] inflight; // @[Monitor.scala:614:27]
reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [39:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire [15:0] _GEN_0 = {12'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [15:0] _GEN_3 = {12'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [9:0] inflight_1; // @[Monitor.scala:726:35]
reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_46 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T
node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2))
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_lo = cat(mask_acc_1, mask_acc)
node mask_hi = cat(mask_acc_3, mask_acc_2)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_15 :
node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_17 = and(UInt<1>(0h0), _T_16)
node _T_18 = or(UInt<1>(0h0), _T_17)
node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_20 = xor(io.in.a.bits.address, UInt<7>(0h40))
node _T_21 = cvt(_T_20)
node _T_22 = and(_T_21, asSInt(UInt<5>(0h14)))
node _T_23 = asSInt(_T_22)
node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0)))
node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h50))
node _T_26 = cvt(_T_25)
node _T_27 = and(_T_26, asSInt(UInt<4>(0h8)))
node _T_28 = asSInt(_T_27)
node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0)))
node _T_30 = or(_T_24, _T_29)
node _T_31 = and(_T_19, _T_30)
node _T_32 = or(UInt<1>(0h0), _T_31)
node _T_33 = and(_T_18, _T_32)
node _T_34 = asUInt(reset)
node _T_35 = eq(_T_34, UInt<1>(0h0))
when _T_35 :
node _T_36 = eq(_T_33, UInt<1>(0h0))
when _T_36 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_33, UInt<1>(0h1), "") : assert_2
node _T_37 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_38 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_39 = and(_T_37, _T_38)
node _T_40 = or(UInt<1>(0h0), _T_39)
node _T_41 = xor(io.in.a.bits.address, UInt<7>(0h40))
node _T_42 = cvt(_T_41)
node _T_43 = and(_T_42, asSInt(UInt<5>(0h14)))
node _T_44 = asSInt(_T_43)
node _T_45 = eq(_T_44, asSInt(UInt<1>(0h0)))
node _T_46 = xor(io.in.a.bits.address, UInt<7>(0h50))
node _T_47 = cvt(_T_46)
node _T_48 = and(_T_47, asSInt(UInt<4>(0h8)))
node _T_49 = asSInt(_T_48)
node _T_50 = eq(_T_49, asSInt(UInt<1>(0h0)))
node _T_51 = or(_T_45, _T_50)
node _T_52 = and(_T_40, _T_51)
node _T_53 = or(UInt<1>(0h0), _T_52)
node _T_54 = and(UInt<1>(0h0), _T_53)
node _T_55 = asUInt(reset)
node _T_56 = eq(_T_55, UInt<1>(0h0))
when _T_56 :
node _T_57 = eq(_T_54, UInt<1>(0h0))
when _T_57 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_54, UInt<1>(0h1), "") : assert_3
node _T_58 = asUInt(reset)
node _T_59 = eq(_T_58, UInt<1>(0h0))
when _T_59 :
node _T_60 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_60 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_61 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_62 = asUInt(reset)
node _T_63 = eq(_T_62, UInt<1>(0h0))
when _T_63 :
node _T_64 = eq(_T_61, UInt<1>(0h0))
when _T_64 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_61, UInt<1>(0h1), "") : assert_5
node _T_65 = asUInt(reset)
node _T_66 = eq(_T_65, UInt<1>(0h0))
when _T_66 :
node _T_67 = eq(is_aligned, UInt<1>(0h0))
when _T_67 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_68 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_69 = asUInt(reset)
node _T_70 = eq(_T_69, UInt<1>(0h0))
when _T_70 :
node _T_71 = eq(_T_68, UInt<1>(0h0))
when _T_71 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_68, UInt<1>(0h1), "") : assert_7
node _T_72 = not(io.in.a.bits.mask)
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = asUInt(reset)
node _T_75 = eq(_T_74, UInt<1>(0h0))
when _T_75 :
node _T_76 = eq(_T_73, UInt<1>(0h0))
when _T_76 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_73, UInt<1>(0h1), "") : assert_8
node _T_77 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_78 = asUInt(reset)
node _T_79 = eq(_T_78, UInt<1>(0h0))
when _T_79 :
node _T_80 = eq(_T_77, UInt<1>(0h0))
when _T_80 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_77, UInt<1>(0h1), "") : assert_9
node _T_81 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_81 :
node _T_82 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_83 = and(UInt<1>(0h0), _T_82)
node _T_84 = or(UInt<1>(0h0), _T_83)
node _T_85 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_86 = xor(io.in.a.bits.address, UInt<7>(0h40))
node _T_87 = cvt(_T_86)
node _T_88 = and(_T_87, asSInt(UInt<5>(0h14)))
node _T_89 = asSInt(_T_88)
node _T_90 = eq(_T_89, asSInt(UInt<1>(0h0)))
node _T_91 = xor(io.in.a.bits.address, UInt<7>(0h50))
node _T_92 = cvt(_T_91)
node _T_93 = and(_T_92, asSInt(UInt<4>(0h8)))
node _T_94 = asSInt(_T_93)
node _T_95 = eq(_T_94, asSInt(UInt<1>(0h0)))
node _T_96 = or(_T_90, _T_95)
node _T_97 = and(_T_85, _T_96)
node _T_98 = or(UInt<1>(0h0), _T_97)
node _T_99 = and(_T_84, _T_98)
node _T_100 = asUInt(reset)
node _T_101 = eq(_T_100, UInt<1>(0h0))
when _T_101 :
node _T_102 = eq(_T_99, UInt<1>(0h0))
when _T_102 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_99, UInt<1>(0h1), "") : assert_10
node _T_103 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_104 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_105 = and(_T_103, _T_104)
node _T_106 = or(UInt<1>(0h0), _T_105)
node _T_107 = xor(io.in.a.bits.address, UInt<7>(0h40))
node _T_108 = cvt(_T_107)
node _T_109 = and(_T_108, asSInt(UInt<5>(0h14)))
node _T_110 = asSInt(_T_109)
node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0)))
node _T_112 = xor(io.in.a.bits.address, UInt<7>(0h50))
node _T_113 = cvt(_T_112)
node _T_114 = and(_T_113, asSInt(UInt<4>(0h8)))
node _T_115 = asSInt(_T_114)
node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0)))
node _T_117 = or(_T_111, _T_116)
node _T_118 = and(_T_106, _T_117)
node _T_119 = or(UInt<1>(0h0), _T_118)
node _T_120 = and(UInt<1>(0h0), _T_119)
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_T_120, UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_120, UInt<1>(0h1), "") : assert_11
node _T_124 = asUInt(reset)
node _T_125 = eq(_T_124, UInt<1>(0h0))
when _T_125 :
node _T_126 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_126 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_127 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(_T_127, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_127, UInt<1>(0h1), "") : assert_13
node _T_131 = asUInt(reset)
node _T_132 = eq(_T_131, UInt<1>(0h0))
when _T_132 :
node _T_133 = eq(is_aligned, UInt<1>(0h0))
when _T_133 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_134 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_135 = asUInt(reset)
node _T_136 = eq(_T_135, UInt<1>(0h0))
when _T_136 :
node _T_137 = eq(_T_134, UInt<1>(0h0))
when _T_137 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_134, UInt<1>(0h1), "") : assert_15
node _T_138 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_139 = asUInt(reset)
node _T_140 = eq(_T_139, UInt<1>(0h0))
when _T_140 :
node _T_141 = eq(_T_138, UInt<1>(0h0))
when _T_141 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_138, UInt<1>(0h1), "") : assert_16
node _T_142 = not(io.in.a.bits.mask)
node _T_143 = eq(_T_142, UInt<1>(0h0))
node _T_144 = asUInt(reset)
node _T_145 = eq(_T_144, UInt<1>(0h0))
when _T_145 :
node _T_146 = eq(_T_143, UInt<1>(0h0))
when _T_146 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_143, UInt<1>(0h1), "") : assert_17
node _T_147 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_148 = asUInt(reset)
node _T_149 = eq(_T_148, UInt<1>(0h0))
when _T_149 :
node _T_150 = eq(_T_147, UInt<1>(0h0))
when _T_150 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_147, UInt<1>(0h1), "") : assert_18
node _T_151 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_151 :
node _T_152 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_153 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_154 = and(_T_152, _T_153)
node _T_155 = or(UInt<1>(0h0), _T_154)
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_155, UInt<1>(0h1), "") : assert_19
node _T_159 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_160 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_161 = and(_T_159, _T_160)
node _T_162 = or(UInt<1>(0h0), _T_161)
node _T_163 = xor(io.in.a.bits.address, UInt<7>(0h40))
node _T_164 = cvt(_T_163)
node _T_165 = and(_T_164, asSInt(UInt<5>(0h14)))
node _T_166 = asSInt(_T_165)
node _T_167 = eq(_T_166, asSInt(UInt<1>(0h0)))
node _T_168 = xor(io.in.a.bits.address, UInt<7>(0h50))
node _T_169 = cvt(_T_168)
node _T_170 = and(_T_169, asSInt(UInt<4>(0h8)))
node _T_171 = asSInt(_T_170)
node _T_172 = eq(_T_171, asSInt(UInt<1>(0h0)))
node _T_173 = or(_T_167, _T_172)
node _T_174 = and(_T_162, _T_173)
node _T_175 = or(UInt<1>(0h0), _T_174)
node _T_176 = asUInt(reset)
node _T_177 = eq(_T_176, UInt<1>(0h0))
when _T_177 :
node _T_178 = eq(_T_175, UInt<1>(0h0))
when _T_178 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_175, UInt<1>(0h1), "") : assert_20
node _T_179 = asUInt(reset)
node _T_180 = eq(_T_179, UInt<1>(0h0))
when _T_180 :
node _T_181 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_181 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_182 = asUInt(reset)
node _T_183 = eq(_T_182, UInt<1>(0h0))
when _T_183 :
node _T_184 = eq(is_aligned, UInt<1>(0h0))
when _T_184 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_185 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_186 = asUInt(reset)
node _T_187 = eq(_T_186, UInt<1>(0h0))
when _T_187 :
node _T_188 = eq(_T_185, UInt<1>(0h0))
when _T_188 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_185, UInt<1>(0h1), "") : assert_23
node _T_189 = eq(io.in.a.bits.mask, mask)
node _T_190 = asUInt(reset)
node _T_191 = eq(_T_190, UInt<1>(0h0))
when _T_191 :
node _T_192 = eq(_T_189, UInt<1>(0h0))
when _T_192 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_189, UInt<1>(0h1), "") : assert_24
node _T_193 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_194 = asUInt(reset)
node _T_195 = eq(_T_194, UInt<1>(0h0))
when _T_195 :
node _T_196 = eq(_T_193, UInt<1>(0h0))
when _T_196 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_193, UInt<1>(0h1), "") : assert_25
node _T_197 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_197 :
node _T_198 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_199 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_200 = and(_T_198, _T_199)
node _T_201 = or(UInt<1>(0h0), _T_200)
node _T_202 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_203 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_204 = and(_T_202, _T_203)
node _T_205 = or(UInt<1>(0h0), _T_204)
node _T_206 = xor(io.in.a.bits.address, UInt<7>(0h40))
node _T_207 = cvt(_T_206)
node _T_208 = and(_T_207, asSInt(UInt<5>(0h14)))
node _T_209 = asSInt(_T_208)
node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0)))
node _T_211 = xor(io.in.a.bits.address, UInt<7>(0h50))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<4>(0h8)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = or(_T_210, _T_215)
node _T_217 = and(_T_205, _T_216)
node _T_218 = or(UInt<1>(0h0), _T_217)
node _T_219 = and(_T_201, _T_218)
node _T_220 = asUInt(reset)
node _T_221 = eq(_T_220, UInt<1>(0h0))
when _T_221 :
node _T_222 = eq(_T_219, UInt<1>(0h0))
when _T_222 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_219, UInt<1>(0h1), "") : assert_26
node _T_223 = asUInt(reset)
node _T_224 = eq(_T_223, UInt<1>(0h0))
when _T_224 :
node _T_225 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_225 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(is_aligned, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_229 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_230 = asUInt(reset)
node _T_231 = eq(_T_230, UInt<1>(0h0))
when _T_231 :
node _T_232 = eq(_T_229, UInt<1>(0h0))
when _T_232 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_229, UInt<1>(0h1), "") : assert_29
node _T_233 = eq(io.in.a.bits.mask, mask)
node _T_234 = asUInt(reset)
node _T_235 = eq(_T_234, UInt<1>(0h0))
when _T_235 :
node _T_236 = eq(_T_233, UInt<1>(0h0))
when _T_236 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_233, UInt<1>(0h1), "") : assert_30
node _T_237 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_237 :
node _T_238 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_239 = and(UInt<1>(0h0), _T_238)
node _T_240 = or(UInt<1>(0h0), _T_239)
node _T_241 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_242 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_243 = and(_T_241, _T_242)
node _T_244 = or(UInt<1>(0h0), _T_243)
node _T_245 = xor(io.in.a.bits.address, UInt<7>(0h40))
node _T_246 = cvt(_T_245)
node _T_247 = and(_T_246, asSInt(UInt<5>(0h14)))
node _T_248 = asSInt(_T_247)
node _T_249 = eq(_T_248, asSInt(UInt<1>(0h0)))
node _T_250 = xor(io.in.a.bits.address, UInt<7>(0h50))
node _T_251 = cvt(_T_250)
node _T_252 = and(_T_251, asSInt(UInt<4>(0h8)))
node _T_253 = asSInt(_T_252)
node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0)))
node _T_255 = or(_T_249, _T_254)
node _T_256 = and(_T_244, _T_255)
node _T_257 = or(UInt<1>(0h0), _T_256)
node _T_258 = and(_T_240, _T_257)
node _T_259 = asUInt(reset)
node _T_260 = eq(_T_259, UInt<1>(0h0))
when _T_260 :
node _T_261 = eq(_T_258, UInt<1>(0h0))
when _T_261 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_258, UInt<1>(0h1), "") : assert_31
node _T_262 = asUInt(reset)
node _T_263 = eq(_T_262, UInt<1>(0h0))
when _T_263 :
node _T_264 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_264 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_265 = asUInt(reset)
node _T_266 = eq(_T_265, UInt<1>(0h0))
when _T_266 :
node _T_267 = eq(is_aligned, UInt<1>(0h0))
when _T_267 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_268 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_269 = asUInt(reset)
node _T_270 = eq(_T_269, UInt<1>(0h0))
when _T_270 :
node _T_271 = eq(_T_268, UInt<1>(0h0))
when _T_271 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_268, UInt<1>(0h1), "") : assert_34
node _T_272 = not(mask)
node _T_273 = and(io.in.a.bits.mask, _T_272)
node _T_274 = eq(_T_273, UInt<1>(0h0))
node _T_275 = asUInt(reset)
node _T_276 = eq(_T_275, UInt<1>(0h0))
when _T_276 :
node _T_277 = eq(_T_274, UInt<1>(0h0))
when _T_277 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_274, UInt<1>(0h1), "") : assert_35
node _T_278 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_278 :
node _T_279 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_280 = and(UInt<1>(0h0), _T_279)
node _T_281 = or(UInt<1>(0h0), _T_280)
node _T_282 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_283 = xor(io.in.a.bits.address, UInt<7>(0h40))
node _T_284 = cvt(_T_283)
node _T_285 = and(_T_284, asSInt(UInt<5>(0h14)))
node _T_286 = asSInt(_T_285)
node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0)))
node _T_288 = xor(io.in.a.bits.address, UInt<7>(0h50))
node _T_289 = cvt(_T_288)
node _T_290 = and(_T_289, asSInt(UInt<4>(0h8)))
node _T_291 = asSInt(_T_290)
node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0)))
node _T_293 = or(_T_287, _T_292)
node _T_294 = and(_T_282, _T_293)
node _T_295 = or(UInt<1>(0h0), _T_294)
node _T_296 = and(_T_281, _T_295)
node _T_297 = asUInt(reset)
node _T_298 = eq(_T_297, UInt<1>(0h0))
when _T_298 :
node _T_299 = eq(_T_296, UInt<1>(0h0))
when _T_299 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_296, UInt<1>(0h1), "") : assert_36
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(is_aligned, UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_306 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_307 = asUInt(reset)
node _T_308 = eq(_T_307, UInt<1>(0h0))
when _T_308 :
node _T_309 = eq(_T_306, UInt<1>(0h0))
when _T_309 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_306, UInt<1>(0h1), "") : assert_39
node _T_310 = eq(io.in.a.bits.mask, mask)
node _T_311 = asUInt(reset)
node _T_312 = eq(_T_311, UInt<1>(0h0))
when _T_312 :
node _T_313 = eq(_T_310, UInt<1>(0h0))
when _T_313 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_310, UInt<1>(0h1), "") : assert_40
node _T_314 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_314 :
node _T_315 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_316 = and(UInt<1>(0h0), _T_315)
node _T_317 = or(UInt<1>(0h0), _T_316)
node _T_318 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_319 = xor(io.in.a.bits.address, UInt<7>(0h40))
node _T_320 = cvt(_T_319)
node _T_321 = and(_T_320, asSInt(UInt<5>(0h14)))
node _T_322 = asSInt(_T_321)
node _T_323 = eq(_T_322, asSInt(UInt<1>(0h0)))
node _T_324 = xor(io.in.a.bits.address, UInt<7>(0h50))
node _T_325 = cvt(_T_324)
node _T_326 = and(_T_325, asSInt(UInt<4>(0h8)))
node _T_327 = asSInt(_T_326)
node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0)))
node _T_329 = or(_T_323, _T_328)
node _T_330 = and(_T_318, _T_329)
node _T_331 = or(UInt<1>(0h0), _T_330)
node _T_332 = and(_T_317, _T_331)
node _T_333 = asUInt(reset)
node _T_334 = eq(_T_333, UInt<1>(0h0))
when _T_334 :
node _T_335 = eq(_T_332, UInt<1>(0h0))
when _T_335 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_332, UInt<1>(0h1), "") : assert_41
node _T_336 = asUInt(reset)
node _T_337 = eq(_T_336, UInt<1>(0h0))
when _T_337 :
node _T_338 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_338 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(is_aligned, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_342 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_343 = asUInt(reset)
node _T_344 = eq(_T_343, UInt<1>(0h0))
when _T_344 :
node _T_345 = eq(_T_342, UInt<1>(0h0))
when _T_345 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_342, UInt<1>(0h1), "") : assert_44
node _T_346 = eq(io.in.a.bits.mask, mask)
node _T_347 = asUInt(reset)
node _T_348 = eq(_T_347, UInt<1>(0h0))
when _T_348 :
node _T_349 = eq(_T_346, UInt<1>(0h0))
when _T_349 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_346, UInt<1>(0h1), "") : assert_45
node _T_350 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_350 :
node _T_351 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_352 = and(UInt<1>(0h0), _T_351)
node _T_353 = or(UInt<1>(0h0), _T_352)
node _T_354 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_355 = xor(io.in.a.bits.address, UInt<7>(0h40))
node _T_356 = cvt(_T_355)
node _T_357 = and(_T_356, asSInt(UInt<5>(0h14)))
node _T_358 = asSInt(_T_357)
node _T_359 = eq(_T_358, asSInt(UInt<1>(0h0)))
node _T_360 = xor(io.in.a.bits.address, UInt<7>(0h50))
node _T_361 = cvt(_T_360)
node _T_362 = and(_T_361, asSInt(UInt<4>(0h8)))
node _T_363 = asSInt(_T_362)
node _T_364 = eq(_T_363, asSInt(UInt<1>(0h0)))
node _T_365 = or(_T_359, _T_364)
node _T_366 = and(_T_354, _T_365)
node _T_367 = or(UInt<1>(0h0), _T_366)
node _T_368 = and(_T_353, _T_367)
node _T_369 = asUInt(reset)
node _T_370 = eq(_T_369, UInt<1>(0h0))
when _T_370 :
node _T_371 = eq(_T_368, UInt<1>(0h0))
when _T_371 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_368, UInt<1>(0h1), "") : assert_46
node _T_372 = asUInt(reset)
node _T_373 = eq(_T_372, UInt<1>(0h0))
when _T_373 :
node _T_374 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_374 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_375 = asUInt(reset)
node _T_376 = eq(_T_375, UInt<1>(0h0))
when _T_376 :
node _T_377 = eq(is_aligned, UInt<1>(0h0))
when _T_377 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_378 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_T_378, UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_378, UInt<1>(0h1), "") : assert_49
node _T_382 = eq(io.in.a.bits.mask, mask)
node _T_383 = asUInt(reset)
node _T_384 = eq(_T_383, UInt<1>(0h0))
when _T_384 :
node _T_385 = eq(_T_382, UInt<1>(0h0))
when _T_385 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_382, UInt<1>(0h1), "") : assert_50
node _T_386 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_387 = asUInt(reset)
node _T_388 = eq(_T_387, UInt<1>(0h0))
when _T_388 :
node _T_389 = eq(_T_386, UInt<1>(0h0))
when _T_389 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_386, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_390 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_391 = asUInt(reset)
node _T_392 = eq(_T_391, UInt<1>(0h0))
when _T_392 :
node _T_393 = eq(_T_390, UInt<1>(0h0))
when _T_393 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_390, UInt<1>(0h1), "") : assert_52
node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_1
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_394 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_394 :
node _T_395 = asUInt(reset)
node _T_396 = eq(_T_395, UInt<1>(0h0))
when _T_396 :
node _T_397 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_397 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_398 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_399 = asUInt(reset)
node _T_400 = eq(_T_399, UInt<1>(0h0))
when _T_400 :
node _T_401 = eq(_T_398, UInt<1>(0h0))
when _T_401 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_398, UInt<1>(0h1), "") : assert_54
node _T_402 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_403 = asUInt(reset)
node _T_404 = eq(_T_403, UInt<1>(0h0))
when _T_404 :
node _T_405 = eq(_T_402, UInt<1>(0h0))
when _T_405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_402, UInt<1>(0h1), "") : assert_55
node _T_406 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_407 = asUInt(reset)
node _T_408 = eq(_T_407, UInt<1>(0h0))
when _T_408 :
node _T_409 = eq(_T_406, UInt<1>(0h0))
when _T_409 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_406, UInt<1>(0h1), "") : assert_56
node _T_410 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_411 = asUInt(reset)
node _T_412 = eq(_T_411, UInt<1>(0h0))
when _T_412 :
node _T_413 = eq(_T_410, UInt<1>(0h0))
when _T_413 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_410, UInt<1>(0h1), "") : assert_57
node _T_414 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_414 :
node _T_415 = asUInt(reset)
node _T_416 = eq(_T_415, UInt<1>(0h0))
when _T_416 :
node _T_417 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_417 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(sink_ok, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_421 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_T_421, UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_421, UInt<1>(0h1), "") : assert_60
node _T_425 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_426 = asUInt(reset)
node _T_427 = eq(_T_426, UInt<1>(0h0))
when _T_427 :
node _T_428 = eq(_T_425, UInt<1>(0h0))
when _T_428 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_425, UInt<1>(0h1), "") : assert_61
node _T_429 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_430 = asUInt(reset)
node _T_431 = eq(_T_430, UInt<1>(0h0))
when _T_431 :
node _T_432 = eq(_T_429, UInt<1>(0h0))
when _T_432 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_429, UInt<1>(0h1), "") : assert_62
node _T_433 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_434 = asUInt(reset)
node _T_435 = eq(_T_434, UInt<1>(0h0))
when _T_435 :
node _T_436 = eq(_T_433, UInt<1>(0h0))
when _T_436 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_433, UInt<1>(0h1), "") : assert_63
node _T_437 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_438 = or(UInt<1>(0h0), _T_437)
node _T_439 = asUInt(reset)
node _T_440 = eq(_T_439, UInt<1>(0h0))
when _T_440 :
node _T_441 = eq(_T_438, UInt<1>(0h0))
when _T_441 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_438, UInt<1>(0h1), "") : assert_64
node _T_442 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_442 :
node _T_443 = asUInt(reset)
node _T_444 = eq(_T_443, UInt<1>(0h0))
when _T_444 :
node _T_445 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_445 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(sink_ok, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_449 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_T_449, UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_449, UInt<1>(0h1), "") : assert_67
node _T_453 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_454 = asUInt(reset)
node _T_455 = eq(_T_454, UInt<1>(0h0))
when _T_455 :
node _T_456 = eq(_T_453, UInt<1>(0h0))
when _T_456 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_453, UInt<1>(0h1), "") : assert_68
node _T_457 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_458 = asUInt(reset)
node _T_459 = eq(_T_458, UInt<1>(0h0))
when _T_459 :
node _T_460 = eq(_T_457, UInt<1>(0h0))
when _T_460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_457, UInt<1>(0h1), "") : assert_69
node _T_461 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_462 = or(_T_461, io.in.d.bits.corrupt)
node _T_463 = asUInt(reset)
node _T_464 = eq(_T_463, UInt<1>(0h0))
when _T_464 :
node _T_465 = eq(_T_462, UInt<1>(0h0))
when _T_465 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_462, UInt<1>(0h1), "") : assert_70
node _T_466 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_467 = or(UInt<1>(0h0), _T_466)
node _T_468 = asUInt(reset)
node _T_469 = eq(_T_468, UInt<1>(0h0))
when _T_469 :
node _T_470 = eq(_T_467, UInt<1>(0h0))
when _T_470 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_467, UInt<1>(0h1), "") : assert_71
node _T_471 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_471 :
node _T_472 = asUInt(reset)
node _T_473 = eq(_T_472, UInt<1>(0h0))
when _T_473 :
node _T_474 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_474 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_475 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_476 = asUInt(reset)
node _T_477 = eq(_T_476, UInt<1>(0h0))
when _T_477 :
node _T_478 = eq(_T_475, UInt<1>(0h0))
when _T_478 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_475, UInt<1>(0h1), "") : assert_73
node _T_479 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_480 = asUInt(reset)
node _T_481 = eq(_T_480, UInt<1>(0h0))
when _T_481 :
node _T_482 = eq(_T_479, UInt<1>(0h0))
when _T_482 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_479, UInt<1>(0h1), "") : assert_74
node _T_483 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_484 = or(UInt<1>(0h0), _T_483)
node _T_485 = asUInt(reset)
node _T_486 = eq(_T_485, UInt<1>(0h0))
when _T_486 :
node _T_487 = eq(_T_484, UInt<1>(0h0))
when _T_487 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_484, UInt<1>(0h1), "") : assert_75
node _T_488 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_488 :
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_492 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_493 = asUInt(reset)
node _T_494 = eq(_T_493, UInt<1>(0h0))
when _T_494 :
node _T_495 = eq(_T_492, UInt<1>(0h0))
when _T_495 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_492, UInt<1>(0h1), "") : assert_77
node _T_496 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_497 = or(_T_496, io.in.d.bits.corrupt)
node _T_498 = asUInt(reset)
node _T_499 = eq(_T_498, UInt<1>(0h0))
when _T_499 :
node _T_500 = eq(_T_497, UInt<1>(0h0))
when _T_500 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_497, UInt<1>(0h1), "") : assert_78
node _T_501 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_502 = or(UInt<1>(0h0), _T_501)
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_502, UInt<1>(0h1), "") : assert_79
node _T_506 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_506 :
node _T_507 = asUInt(reset)
node _T_508 = eq(_T_507, UInt<1>(0h0))
when _T_508 :
node _T_509 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_509 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_510 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_511 = asUInt(reset)
node _T_512 = eq(_T_511, UInt<1>(0h0))
when _T_512 :
node _T_513 = eq(_T_510, UInt<1>(0h0))
when _T_513 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_510, UInt<1>(0h1), "") : assert_81
node _T_514 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_515 = asUInt(reset)
node _T_516 = eq(_T_515, UInt<1>(0h0))
when _T_516 :
node _T_517 = eq(_T_514, UInt<1>(0h0))
when _T_517 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_514, UInt<1>(0h1), "") : assert_82
node _T_518 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_519 = or(UInt<1>(0h0), _T_518)
node _T_520 = asUInt(reset)
node _T_521 = eq(_T_520, UInt<1>(0h0))
when _T_521 :
node _T_522 = eq(_T_519, UInt<1>(0h0))
when _T_522 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_519, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<7>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<32>(0h0)
connect _WIRE.bits.mask, UInt<4>(0h0)
connect _WIRE.bits.address, UInt<7>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<7>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_523 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_524 = asUInt(reset)
node _T_525 = eq(_T_524, UInt<1>(0h0))
when _T_525 :
node _T_526 = eq(_T_523, UInt<1>(0h0))
when _T_526 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_523, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<32>(0h0)
connect _WIRE_2.bits.address, UInt<7>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_527 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_528 = asUInt(reset)
node _T_529 = eq(_T_528, UInt<1>(0h0))
when _T_529 :
node _T_530 = eq(_T_527, UInt<1>(0h0))
when _T_530 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_527, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_531 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_532 = asUInt(reset)
node _T_533 = eq(_T_532, UInt<1>(0h0))
when _T_533 :
node _T_534 = eq(_T_531, UInt<1>(0h0))
when _T_534 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_531, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_535 = eq(a_first, UInt<1>(0h0))
node _T_536 = and(io.in.a.valid, _T_535)
when _T_536 :
node _T_537 = eq(io.in.a.bits.opcode, opcode)
node _T_538 = asUInt(reset)
node _T_539 = eq(_T_538, UInt<1>(0h0))
when _T_539 :
node _T_540 = eq(_T_537, UInt<1>(0h0))
when _T_540 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_537, UInt<1>(0h1), "") : assert_87
node _T_541 = eq(io.in.a.bits.param, param)
node _T_542 = asUInt(reset)
node _T_543 = eq(_T_542, UInt<1>(0h0))
when _T_543 :
node _T_544 = eq(_T_541, UInt<1>(0h0))
when _T_544 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_541, UInt<1>(0h1), "") : assert_88
node _T_545 = eq(io.in.a.bits.size, size)
node _T_546 = asUInt(reset)
node _T_547 = eq(_T_546, UInt<1>(0h0))
when _T_547 :
node _T_548 = eq(_T_545, UInt<1>(0h0))
when _T_548 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_545, UInt<1>(0h1), "") : assert_89
node _T_549 = eq(io.in.a.bits.source, source)
node _T_550 = asUInt(reset)
node _T_551 = eq(_T_550, UInt<1>(0h0))
when _T_551 :
node _T_552 = eq(_T_549, UInt<1>(0h0))
when _T_552 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_549, UInt<1>(0h1), "") : assert_90
node _T_553 = eq(io.in.a.bits.address, address)
node _T_554 = asUInt(reset)
node _T_555 = eq(_T_554, UInt<1>(0h0))
when _T_555 :
node _T_556 = eq(_T_553, UInt<1>(0h0))
when _T_556 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_553, UInt<1>(0h1), "") : assert_91
node _T_557 = and(io.in.a.ready, io.in.a.valid)
node _T_558 = and(_T_557, a_first)
when _T_558 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_559 = eq(d_first, UInt<1>(0h0))
node _T_560 = and(io.in.d.valid, _T_559)
when _T_560 :
node _T_561 = eq(io.in.d.bits.opcode, opcode_1)
node _T_562 = asUInt(reset)
node _T_563 = eq(_T_562, UInt<1>(0h0))
when _T_563 :
node _T_564 = eq(_T_561, UInt<1>(0h0))
when _T_564 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_561, UInt<1>(0h1), "") : assert_92
node _T_565 = eq(io.in.d.bits.param, param_1)
node _T_566 = asUInt(reset)
node _T_567 = eq(_T_566, UInt<1>(0h0))
when _T_567 :
node _T_568 = eq(_T_565, UInt<1>(0h0))
when _T_568 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_565, UInt<1>(0h1), "") : assert_93
node _T_569 = eq(io.in.d.bits.size, size_1)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_569, UInt<1>(0h1), "") : assert_94
node _T_573 = eq(io.in.d.bits.source, source_1)
node _T_574 = asUInt(reset)
node _T_575 = eq(_T_574, UInt<1>(0h0))
when _T_575 :
node _T_576 = eq(_T_573, UInt<1>(0h0))
when _T_576 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_573, UInt<1>(0h1), "") : assert_95
node _T_577 = eq(io.in.d.bits.sink, sink)
node _T_578 = asUInt(reset)
node _T_579 = eq(_T_578, UInt<1>(0h0))
when _T_579 :
node _T_580 = eq(_T_577, UInt<1>(0h0))
when _T_580 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_577, UInt<1>(0h1), "") : assert_96
node _T_581 = eq(io.in.d.bits.denied, denied)
node _T_582 = asUInt(reset)
node _T_583 = eq(_T_582, UInt<1>(0h0))
when _T_583 :
node _T_584 = eq(_T_581, UInt<1>(0h0))
when _T_584 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_581, UInt<1>(0h1), "") : assert_97
node _T_585 = and(io.in.d.ready, io.in.d.valid)
node _T_586 = and(_T_585, d_first)
when _T_586 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1>
connect a_set, UInt<1>(0h0)
wire a_set_wo_ready : UInt<1>
connect a_set_wo_ready, UInt<1>(0h0)
wire a_opcodes_set : UInt<4>
connect a_opcodes_set, UInt<4>(0h0)
wire a_sizes_set : UInt<4>
connect a_sizes_set, UInt<4>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_587 = and(io.in.a.valid, a_first_1)
node _T_588 = and(_T_587, UInt<1>(0h1))
when _T_588 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_589 = and(io.in.a.ready, io.in.a.valid)
node _T_590 = and(_T_589, a_first_1)
node _T_591 = and(_T_590, UInt<1>(0h1))
when _T_591 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_592 = dshr(inflight, io.in.a.bits.source)
node _T_593 = bits(_T_592, 0, 0)
node _T_594 = eq(_T_593, UInt<1>(0h0))
node _T_595 = asUInt(reset)
node _T_596 = eq(_T_595, UInt<1>(0h0))
when _T_596 :
node _T_597 = eq(_T_594, UInt<1>(0h0))
when _T_597 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_594, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1>
connect d_clr, UInt<1>(0h0)
wire d_clr_wo_ready : UInt<1>
connect d_clr_wo_ready, UInt<1>(0h0)
wire d_opcodes_clr : UInt<4>
connect d_opcodes_clr, UInt<4>(0h0)
wire d_sizes_clr : UInt<4>
connect d_sizes_clr, UInt<4>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_598 = and(io.in.d.valid, d_first_1)
node _T_599 = and(_T_598, UInt<1>(0h1))
node _T_600 = eq(d_release_ack, UInt<1>(0h0))
node _T_601 = and(_T_599, _T_600)
when _T_601 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_602 = and(io.in.d.ready, io.in.d.valid)
node _T_603 = and(_T_602, d_first_1)
node _T_604 = and(_T_603, UInt<1>(0h1))
node _T_605 = eq(d_release_ack, UInt<1>(0h0))
node _T_606 = and(_T_604, _T_605)
when _T_606 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_607 = and(io.in.d.valid, d_first_1)
node _T_608 = and(_T_607, UInt<1>(0h1))
node _T_609 = eq(d_release_ack, UInt<1>(0h0))
node _T_610 = and(_T_608, _T_609)
when _T_610 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_611 = dshr(inflight, io.in.d.bits.source)
node _T_612 = bits(_T_611, 0, 0)
node _T_613 = or(_T_612, same_cycle_resp)
node _T_614 = asUInt(reset)
node _T_615 = eq(_T_614, UInt<1>(0h0))
when _T_615 :
node _T_616 = eq(_T_613, UInt<1>(0h0))
when _T_616 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_613, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_617 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_618 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_619 = or(_T_617, _T_618)
node _T_620 = asUInt(reset)
node _T_621 = eq(_T_620, UInt<1>(0h0))
when _T_621 :
node _T_622 = eq(_T_619, UInt<1>(0h0))
when _T_622 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_619, UInt<1>(0h1), "") : assert_100
node _T_623 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_624 = asUInt(reset)
node _T_625 = eq(_T_624, UInt<1>(0h0))
when _T_625 :
node _T_626 = eq(_T_623, UInt<1>(0h0))
when _T_626 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_623, UInt<1>(0h1), "") : assert_101
else :
node _T_627 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_628 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_629 = or(_T_627, _T_628)
node _T_630 = asUInt(reset)
node _T_631 = eq(_T_630, UInt<1>(0h0))
when _T_631 :
node _T_632 = eq(_T_629, UInt<1>(0h0))
when _T_632 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_629, UInt<1>(0h1), "") : assert_102
node _T_633 = eq(io.in.d.bits.size, a_size_lookup)
node _T_634 = asUInt(reset)
node _T_635 = eq(_T_634, UInt<1>(0h0))
when _T_635 :
node _T_636 = eq(_T_633, UInt<1>(0h0))
when _T_636 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_633, UInt<1>(0h1), "") : assert_103
node _T_637 = and(io.in.d.valid, d_first_1)
node _T_638 = and(_T_637, a_first_1)
node _T_639 = and(_T_638, io.in.a.valid)
node _T_640 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_641 = and(_T_639, _T_640)
node _T_642 = eq(d_release_ack, UInt<1>(0h0))
node _T_643 = and(_T_641, _T_642)
when _T_643 :
node _T_644 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_645 = or(_T_644, io.in.a.ready)
node _T_646 = asUInt(reset)
node _T_647 = eq(_T_646, UInt<1>(0h0))
when _T_647 :
node _T_648 = eq(_T_645, UInt<1>(0h0))
when _T_648 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_645, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_93
node _T_649 = orr(inflight)
node _T_650 = eq(_T_649, UInt<1>(0h0))
node _T_651 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_652 = or(_T_650, _T_651)
node _T_653 = lt(watchdog, plusarg_reader.out)
node _T_654 = or(_T_652, _T_653)
node _T_655 = asUInt(reset)
node _T_656 = eq(_T_655, UInt<1>(0h0))
when _T_656 :
node _T_657 = eq(_T_654, UInt<1>(0h0))
when _T_657 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_654, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_658 = and(io.in.a.ready, io.in.a.valid)
node _T_659 = and(io.in.d.ready, io.in.d.valid)
node _T_660 = or(_T_658, _T_659)
when _T_660 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<32>(0h0)
connect _c_first_WIRE.bits.address, UInt<7>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1>
connect c_set, UInt<1>(0h0)
wire c_set_wo_ready : UInt<1>
connect c_set_wo_ready, UInt<1>(0h0)
wire c_opcodes_set : UInt<4>
connect c_opcodes_set, UInt<4>(0h0)
wire c_sizes_set : UInt<4>
connect c_sizes_set, UInt<4>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<32>(0h0)
connect _WIRE_6.bits.address, UInt<7>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_661 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<32>(0h0)
connect _WIRE_8.bits.address, UInt<7>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_662 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_663 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_664 = and(_T_662, _T_663)
node _T_665 = and(_T_661, _T_664)
when _T_665 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<32>(0h0)
connect _WIRE_10.bits.address, UInt<7>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_666 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_667 = and(_T_666, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<32>(0h0)
connect _WIRE_12.bits.address, UInt<7>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_668 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_669 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_670 = and(_T_668, _T_669)
node _T_671 = and(_T_667, _T_670)
when _T_671 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_WIRE.bits.address, UInt<7>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<32>(0h0)
connect _WIRE_14.bits.address, UInt<7>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_672 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_673 = bits(_T_672, 0, 0)
node _T_674 = eq(_T_673, UInt<1>(0h0))
node _T_675 = asUInt(reset)
node _T_676 = eq(_T_675, UInt<1>(0h0))
when _T_676 :
node _T_677 = eq(_T_674, UInt<1>(0h0))
when _T_677 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_674, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1>
connect d_clr_1, UInt<1>(0h0)
wire d_clr_wo_ready_1 : UInt<1>
connect d_clr_wo_ready_1, UInt<1>(0h0)
wire d_opcodes_clr_1 : UInt<4>
connect d_opcodes_clr_1, UInt<4>(0h0)
wire d_sizes_clr_1 : UInt<4>
connect d_sizes_clr_1, UInt<4>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_678 = and(io.in.d.valid, d_first_2)
node _T_679 = and(_T_678, UInt<1>(0h1))
node _T_680 = and(_T_679, d_release_ack_1)
when _T_680 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_681 = and(io.in.d.ready, io.in.d.valid)
node _T_682 = and(_T_681, d_first_2)
node _T_683 = and(_T_682, UInt<1>(0h1))
node _T_684 = and(_T_683, d_release_ack_1)
when _T_684 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_685 = and(io.in.d.valid, d_first_2)
node _T_686 = and(_T_685, UInt<1>(0h1))
node _T_687 = and(_T_686, d_release_ack_1)
when _T_687 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_688 = dshr(inflight_1, io.in.d.bits.source)
node _T_689 = bits(_T_688, 0, 0)
node _T_690 = or(_T_689, same_cycle_resp_1)
node _T_691 = asUInt(reset)
node _T_692 = eq(_T_691, UInt<1>(0h0))
when _T_692 :
node _T_693 = eq(_T_690, UInt<1>(0h0))
when _T_693 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_690, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<32>(0h0)
connect _WIRE_16.bits.address, UInt<7>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_694 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_695 = asUInt(reset)
node _T_696 = eq(_T_695, UInt<1>(0h0))
when _T_696 :
node _T_697 = eq(_T_694, UInt<1>(0h0))
when _T_697 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_694, UInt<1>(0h1), "") : assert_108
else :
node _T_698 = eq(io.in.d.bits.size, c_size_lookup)
node _T_699 = asUInt(reset)
node _T_700 = eq(_T_699, UInt<1>(0h0))
when _T_700 :
node _T_701 = eq(_T_698, UInt<1>(0h0))
when _T_701 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_698, UInt<1>(0h1), "") : assert_109
node _T_702 = and(io.in.d.valid, d_first_2)
node _T_703 = and(_T_702, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<32>(0h0)
connect _WIRE_18.bits.address, UInt<7>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_704 = and(_T_703, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<32>(0h0)
connect _WIRE_20.bits.address, UInt<7>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_705 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_706 = and(_T_704, _T_705)
node _T_707 = and(_T_706, d_release_ack_1)
node _T_708 = eq(c_probe_ack, UInt<1>(0h0))
node _T_709 = and(_T_707, _T_708)
when _T_709 :
node _T_710 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<32>(0h0)
connect _WIRE_22.bits.address, UInt<7>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_711 = or(_T_710, _WIRE_23.ready)
node _T_712 = asUInt(reset)
node _T_713 = eq(_T_712, UInt<1>(0h0))
when _T_713 :
node _T_714 = eq(_T_711, UInt<1>(0h0))
when _T_714 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_711, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_94
node _T_715 = orr(inflight_1)
node _T_716 = eq(_T_715, UInt<1>(0h0))
node _T_717 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_718 = or(_T_716, _T_717)
node _T_719 = lt(watchdog_1, plusarg_reader_1.out)
node _T_720 = or(_T_718, _T_719)
node _T_721 = asUInt(reset)
node _T_722 = eq(_T_721, UInt<1>(0h0))
when _T_722 :
node _T_723 = eq(_T_720, UInt<1>(0h0))
when _T_723 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_720, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<32>(0h0)
connect _WIRE_24.bits.address, UInt<7>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_724 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_725 = and(io.in.d.ready, io.in.d.valid)
node _T_726 = or(_T_724, _T_725)
when _T_726 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_46( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [6:0] address; // @[Monitor.scala:391:22]
reg d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [3:0] inflight_sizes; // @[Monitor.scala:618:33]
reg a_first_counter_1; // @[Edges.scala:229:27]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire a_set = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg d_first_counter_2; // @[Edges.scala:229:27]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module ProbePicker :
input clock : Clock
input reset : Reset
output auto : { flip in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
wire nodeIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn_1.d.bits.corrupt
invalidate nodeIn_1.d.bits.data
invalidate nodeIn_1.d.bits.denied
invalidate nodeIn_1.d.bits.sink
invalidate nodeIn_1.d.bits.source
invalidate nodeIn_1.d.bits.size
invalidate nodeIn_1.d.bits.param
invalidate nodeIn_1.d.bits.opcode
invalidate nodeIn_1.d.valid
invalidate nodeIn_1.d.ready
invalidate nodeIn_1.a.bits.corrupt
invalidate nodeIn_1.a.bits.data
invalidate nodeIn_1.a.bits.mask
invalidate nodeIn_1.a.bits.address
invalidate nodeIn_1.a.bits.source
invalidate nodeIn_1.a.bits.size
invalidate nodeIn_1.a.bits.param
invalidate nodeIn_1.a.bits.opcode
invalidate nodeIn_1.a.valid
invalidate nodeIn_1.a.ready
inst monitor of TLMonitor_44
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
inst monitor_1 of TLMonitor_45
connect monitor_1.clock, clock
connect monitor_1.reset, reset
connect monitor_1.io.in.d.bits.corrupt, nodeIn_1.d.bits.corrupt
connect monitor_1.io.in.d.bits.data, nodeIn_1.d.bits.data
connect monitor_1.io.in.d.bits.denied, nodeIn_1.d.bits.denied
connect monitor_1.io.in.d.bits.sink, nodeIn_1.d.bits.sink
connect monitor_1.io.in.d.bits.source, nodeIn_1.d.bits.source
connect monitor_1.io.in.d.bits.size, nodeIn_1.d.bits.size
connect monitor_1.io.in.d.bits.param, nodeIn_1.d.bits.param
connect monitor_1.io.in.d.bits.opcode, nodeIn_1.d.bits.opcode
connect monitor_1.io.in.d.valid, nodeIn_1.d.valid
connect monitor_1.io.in.d.ready, nodeIn_1.d.ready
connect monitor_1.io.in.a.bits.corrupt, nodeIn_1.a.bits.corrupt
connect monitor_1.io.in.a.bits.data, nodeIn_1.a.bits.data
connect monitor_1.io.in.a.bits.mask, nodeIn_1.a.bits.mask
connect monitor_1.io.in.a.bits.address, nodeIn_1.a.bits.address
connect monitor_1.io.in.a.bits.source, nodeIn_1.a.bits.source
connect monitor_1.io.in.a.bits.size, nodeIn_1.a.bits.size
connect monitor_1.io.in.a.bits.param, nodeIn_1.a.bits.param
connect monitor_1.io.in.a.bits.opcode, nodeIn_1.a.bits.opcode
connect monitor_1.io.in.a.valid, nodeIn_1.a.valid
connect monitor_1.io.in.a.ready, nodeIn_1.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
wire x1_nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_nodeOut.d.bits.corrupt
invalidate x1_nodeOut.d.bits.data
invalidate x1_nodeOut.d.bits.denied
invalidate x1_nodeOut.d.bits.sink
invalidate x1_nodeOut.d.bits.source
invalidate x1_nodeOut.d.bits.size
invalidate x1_nodeOut.d.bits.param
invalidate x1_nodeOut.d.bits.opcode
invalidate x1_nodeOut.d.valid
invalidate x1_nodeOut.d.ready
invalidate x1_nodeOut.a.bits.corrupt
invalidate x1_nodeOut.a.bits.data
invalidate x1_nodeOut.a.bits.mask
invalidate x1_nodeOut.a.bits.address
invalidate x1_nodeOut.a.bits.source
invalidate x1_nodeOut.a.bits.size
invalidate x1_nodeOut.a.bits.param
invalidate x1_nodeOut.a.bits.opcode
invalidate x1_nodeOut.a.valid
invalidate x1_nodeOut.a.ready
connect auto.out_0, nodeOut
connect auto.out_1, x1_nodeOut
connect nodeIn, auto.in_0
connect nodeIn_1, auto.in_1
connect nodeOut, nodeIn
connect x1_nodeOut, nodeIn_1 | module ProbePicker( // @[ProbePicker.scala:42:9]
input clock, // @[ProbePicker.scala:42:9]
input reset, // @[ProbePicker.scala:42:9]
output auto_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [27:0] auto_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_1_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_0_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_0_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_0_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_0_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [27:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire auto_in_1_a_valid_0 = auto_in_1_a_valid; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_1_a_bits_opcode_0 = auto_in_1_a_bits_opcode; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_1_a_bits_param_0 = auto_in_1_a_bits_param; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_1_a_bits_size_0 = auto_in_1_a_bits_size; // @[ProbePicker.scala:42:9]
wire [3:0] auto_in_1_a_bits_source_0 = auto_in_1_a_bits_source; // @[ProbePicker.scala:42:9]
wire [27:0] auto_in_1_a_bits_address_0 = auto_in_1_a_bits_address; // @[ProbePicker.scala:42:9]
wire [7:0] auto_in_1_a_bits_mask_0 = auto_in_1_a_bits_mask; // @[ProbePicker.scala:42:9]
wire [63:0] auto_in_1_a_bits_data_0 = auto_in_1_a_bits_data; // @[ProbePicker.scala:42:9]
wire auto_in_1_a_bits_corrupt_0 = auto_in_1_a_bits_corrupt; // @[ProbePicker.scala:42:9]
wire auto_in_1_d_ready_0 = auto_in_1_d_ready; // @[ProbePicker.scala:42:9]
wire auto_in_0_a_valid_0 = auto_in_0_a_valid; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_0_a_bits_opcode_0 = auto_in_0_a_bits_opcode; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_0_a_bits_param_0 = auto_in_0_a_bits_param; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_0_a_bits_size_0 = auto_in_0_a_bits_size; // @[ProbePicker.scala:42:9]
wire [3:0] auto_in_0_a_bits_source_0 = auto_in_0_a_bits_source; // @[ProbePicker.scala:42:9]
wire [31:0] auto_in_0_a_bits_address_0 = auto_in_0_a_bits_address; // @[ProbePicker.scala:42:9]
wire [7:0] auto_in_0_a_bits_mask_0 = auto_in_0_a_bits_mask; // @[ProbePicker.scala:42:9]
wire [63:0] auto_in_0_a_bits_data_0 = auto_in_0_a_bits_data; // @[ProbePicker.scala:42:9]
wire auto_in_0_a_bits_corrupt_0 = auto_in_0_a_bits_corrupt; // @[ProbePicker.scala:42:9]
wire auto_in_0_d_ready_0 = auto_in_0_d_ready; // @[ProbePicker.scala:42:9]
wire auto_out_1_a_ready_0 = auto_out_1_a_ready; // @[ProbePicker.scala:42:9]
wire auto_out_1_d_valid_0 = auto_out_1_d_valid; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_1_d_bits_opcode_0 = auto_out_1_d_bits_opcode; // @[ProbePicker.scala:42:9]
wire [1:0] auto_out_1_d_bits_param_0 = auto_out_1_d_bits_param; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_1_d_bits_size_0 = auto_out_1_d_bits_size; // @[ProbePicker.scala:42:9]
wire [3:0] auto_out_1_d_bits_source_0 = auto_out_1_d_bits_source; // @[ProbePicker.scala:42:9]
wire auto_out_1_d_bits_sink_0 = auto_out_1_d_bits_sink; // @[ProbePicker.scala:42:9]
wire auto_out_1_d_bits_denied_0 = auto_out_1_d_bits_denied; // @[ProbePicker.scala:42:9]
wire [63:0] auto_out_1_d_bits_data_0 = auto_out_1_d_bits_data; // @[ProbePicker.scala:42:9]
wire auto_out_1_d_bits_corrupt_0 = auto_out_1_d_bits_corrupt; // @[ProbePicker.scala:42:9]
wire auto_out_0_a_ready_0 = auto_out_0_a_ready; // @[ProbePicker.scala:42:9]
wire auto_out_0_d_valid_0 = auto_out_0_d_valid; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_0_d_bits_opcode_0 = auto_out_0_d_bits_opcode; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_0_d_bits_size_0 = auto_out_0_d_bits_size; // @[ProbePicker.scala:42:9]
wire [3:0] auto_out_0_d_bits_source_0 = auto_out_0_d_bits_source; // @[ProbePicker.scala:42:9]
wire auto_out_0_d_bits_denied_0 = auto_out_0_d_bits_denied; // @[ProbePicker.scala:42:9]
wire [63:0] auto_out_0_d_bits_data_0 = auto_out_0_d_bits_data; // @[ProbePicker.scala:42:9]
wire auto_out_0_d_bits_corrupt_0 = auto_out_0_d_bits_corrupt; // @[ProbePicker.scala:42:9]
wire auto_in_0_d_bits_sink = 1'h0; // @[ProbePicker.scala:42:9]
wire auto_out_0_d_bits_sink = 1'h0; // @[ProbePicker.scala:42:9]
wire nodeIn_d_bits_sink = 1'h0; // @[ProbePicker.scala:42:9]
wire nodeOut_d_bits_sink = 1'h0; // @[ProbePicker.scala:42:9]
wire [1:0] auto_in_0_d_bits_param = 2'h0; // @[ProbePicker.scala:42:9]
wire [1:0] auto_out_0_d_bits_param = 2'h0; // @[ProbePicker.scala:42:9]
wire [1:0] nodeIn_d_bits_param = 2'h0; // @[ProbePicker.scala:42:9]
wire nodeIn_1_a_ready; // @[MixedNode.scala:551:17]
wire [1:0] nodeOut_d_bits_param = 2'h0; // @[ProbePicker.scala:42:9]
wire nodeIn_1_a_valid = auto_in_1_a_valid_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeIn_1_a_bits_opcode = auto_in_1_a_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeIn_1_a_bits_param = auto_in_1_a_bits_param_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeIn_1_a_bits_size = auto_in_1_a_bits_size_0; // @[ProbePicker.scala:42:9]
wire [3:0] nodeIn_1_a_bits_source = auto_in_1_a_bits_source_0; // @[ProbePicker.scala:42:9]
wire [27:0] nodeIn_1_a_bits_address = auto_in_1_a_bits_address_0; // @[ProbePicker.scala:42:9]
wire [7:0] nodeIn_1_a_bits_mask = auto_in_1_a_bits_mask_0; // @[ProbePicker.scala:42:9]
wire [63:0] nodeIn_1_a_bits_data = auto_in_1_a_bits_data_0; // @[ProbePicker.scala:42:9]
wire nodeIn_1_a_bits_corrupt = auto_in_1_a_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire nodeIn_1_d_ready = auto_in_1_d_ready_0; // @[ProbePicker.scala:42:9]
wire nodeIn_1_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_1_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_1_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_1_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_1_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_1_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_1_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_1_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_valid = auto_in_0_a_valid_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_0_a_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeIn_a_bits_param = auto_in_0_a_bits_param_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeIn_a_bits_size = auto_in_0_a_bits_size_0; // @[ProbePicker.scala:42:9]
wire [3:0] nodeIn_a_bits_source = auto_in_0_a_bits_source_0; // @[ProbePicker.scala:42:9]
wire [31:0] nodeIn_a_bits_address = auto_in_0_a_bits_address_0; // @[ProbePicker.scala:42:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_0_a_bits_mask_0; // @[ProbePicker.scala:42:9]
wire [63:0] nodeIn_a_bits_data = auto_in_0_a_bits_data_0; // @[ProbePicker.scala:42:9]
wire nodeIn_a_bits_corrupt = auto_in_0_a_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire nodeIn_d_ready = auto_in_0_d_ready_0; // @[ProbePicker.scala:42:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire x1_nodeOut_a_ready = auto_out_1_a_ready_0; // @[ProbePicker.scala:42:9]
wire x1_nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] x1_nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [27:0] x1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire x1_nodeOut_d_valid = auto_out_1_d_valid_0; // @[ProbePicker.scala:42:9]
wire [2:0] x1_nodeOut_d_bits_opcode = auto_out_1_d_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [1:0] x1_nodeOut_d_bits_param = auto_out_1_d_bits_param_0; // @[ProbePicker.scala:42:9]
wire [2:0] x1_nodeOut_d_bits_size = auto_out_1_d_bits_size_0; // @[ProbePicker.scala:42:9]
wire [3:0] x1_nodeOut_d_bits_source = auto_out_1_d_bits_source_0; // @[ProbePicker.scala:42:9]
wire x1_nodeOut_d_bits_sink = auto_out_1_d_bits_sink_0; // @[ProbePicker.scala:42:9]
wire x1_nodeOut_d_bits_denied = auto_out_1_d_bits_denied_0; // @[ProbePicker.scala:42:9]
wire [63:0] x1_nodeOut_d_bits_data = auto_out_1_d_bits_data_0; // @[ProbePicker.scala:42:9]
wire x1_nodeOut_d_bits_corrupt = auto_out_1_d_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire nodeOut_a_ready = auto_out_0_a_ready_0; // @[ProbePicker.scala:42:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_0_d_valid_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_0_d_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeOut_d_bits_size = auto_out_0_d_bits_size_0; // @[ProbePicker.scala:42:9]
wire [3:0] nodeOut_d_bits_source = auto_out_0_d_bits_source_0; // @[ProbePicker.scala:42:9]
wire nodeOut_d_bits_denied = auto_out_0_d_bits_denied_0; // @[ProbePicker.scala:42:9]
wire [63:0] nodeOut_d_bits_data = auto_out_0_d_bits_data_0; // @[ProbePicker.scala:42:9]
wire nodeOut_d_bits_corrupt = auto_out_0_d_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire auto_in_1_a_ready_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_1_d_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [1:0] auto_in_1_d_bits_param_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_1_d_bits_size_0; // @[ProbePicker.scala:42:9]
wire [3:0] auto_in_1_d_bits_source_0; // @[ProbePicker.scala:42:9]
wire auto_in_1_d_bits_sink_0; // @[ProbePicker.scala:42:9]
wire auto_in_1_d_bits_denied_0; // @[ProbePicker.scala:42:9]
wire [63:0] auto_in_1_d_bits_data_0; // @[ProbePicker.scala:42:9]
wire auto_in_1_d_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire auto_in_1_d_valid_0; // @[ProbePicker.scala:42:9]
wire auto_in_0_a_ready_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_0_d_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_0_d_bits_size_0; // @[ProbePicker.scala:42:9]
wire [3:0] auto_in_0_d_bits_source_0; // @[ProbePicker.scala:42:9]
wire auto_in_0_d_bits_denied_0; // @[ProbePicker.scala:42:9]
wire [63:0] auto_in_0_d_bits_data_0; // @[ProbePicker.scala:42:9]
wire auto_in_0_d_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire auto_in_0_d_valid_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_1_a_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_1_a_bits_param_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_1_a_bits_size_0; // @[ProbePicker.scala:42:9]
wire [3:0] auto_out_1_a_bits_source_0; // @[ProbePicker.scala:42:9]
wire [27:0] auto_out_1_a_bits_address_0; // @[ProbePicker.scala:42:9]
wire [7:0] auto_out_1_a_bits_mask_0; // @[ProbePicker.scala:42:9]
wire [63:0] auto_out_1_a_bits_data_0; // @[ProbePicker.scala:42:9]
wire auto_out_1_a_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire auto_out_1_a_valid_0; // @[ProbePicker.scala:42:9]
wire auto_out_1_d_ready_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_0_a_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_0_a_bits_param_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_0_a_bits_size_0; // @[ProbePicker.scala:42:9]
wire [3:0] auto_out_0_a_bits_source_0; // @[ProbePicker.scala:42:9]
wire [31:0] auto_out_0_a_bits_address_0; // @[ProbePicker.scala:42:9]
wire [7:0] auto_out_0_a_bits_mask_0; // @[ProbePicker.scala:42:9]
wire [63:0] auto_out_0_a_bits_data_0; // @[ProbePicker.scala:42:9]
wire auto_out_0_a_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire auto_out_0_a_valid_0; // @[ProbePicker.scala:42:9]
wire auto_out_0_d_ready_0; // @[ProbePicker.scala:42:9]
assign auto_in_0_a_ready_0 = nodeIn_a_ready; // @[ProbePicker.scala:42:9]
assign nodeOut_a_valid = nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_param = nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_size = nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_source = nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_address = nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_mask = nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_corrupt = nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_d_ready = nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_in_0_d_valid_0 = nodeIn_d_valid; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_size_0 = nodeIn_d_bits_size; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_source_0 = nodeIn_d_bits_source; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_denied_0 = nodeIn_d_bits_denied; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_data_0 = nodeIn_d_bits_data; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[ProbePicker.scala:42:9]
assign auto_in_1_a_ready_0 = nodeIn_1_a_ready; // @[ProbePicker.scala:42:9]
assign x1_nodeOut_a_valid = nodeIn_1_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_opcode = nodeIn_1_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_param = nodeIn_1_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_size = nodeIn_1_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_source = nodeIn_1_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_address = nodeIn_1_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_mask = nodeIn_1_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_data = nodeIn_1_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_corrupt = nodeIn_1_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_d_ready = nodeIn_1_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_in_1_d_valid_0 = nodeIn_1_d_valid; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_opcode_0 = nodeIn_1_d_bits_opcode; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_param_0 = nodeIn_1_d_bits_param; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_size_0 = nodeIn_1_d_bits_size; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_source_0 = nodeIn_1_d_bits_source; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_sink_0 = nodeIn_1_d_bits_sink; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_denied_0 = nodeIn_1_d_bits_denied; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_data_0 = nodeIn_1_d_bits_data; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_corrupt_0 = nodeIn_1_d_bits_corrupt; // @[ProbePicker.scala:42:9]
assign nodeIn_a_ready = nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_out_0_a_valid_0 = nodeOut_a_valid; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_param_0 = nodeOut_a_bits_param; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_size_0 = nodeOut_a_bits_size; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_source_0 = nodeOut_a_bits_source; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_address_0 = nodeOut_a_bits_address; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_mask_0 = nodeOut_a_bits_mask; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_data_0 = nodeOut_a_bits_data; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[ProbePicker.scala:42:9]
assign auto_out_0_d_ready_0 = nodeOut_d_ready; // @[ProbePicker.scala:42:9]
assign nodeIn_d_valid = nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_opcode = nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_size = nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_source = nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_denied = nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_data = nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_corrupt = nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_1_a_ready = x1_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_out_1_a_valid_0 = x1_nodeOut_a_valid; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_opcode_0 = x1_nodeOut_a_bits_opcode; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_param_0 = x1_nodeOut_a_bits_param; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_size_0 = x1_nodeOut_a_bits_size; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_source_0 = x1_nodeOut_a_bits_source; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_address_0 = x1_nodeOut_a_bits_address; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_mask_0 = x1_nodeOut_a_bits_mask; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_data_0 = x1_nodeOut_a_bits_data; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_corrupt_0 = x1_nodeOut_a_bits_corrupt; // @[ProbePicker.scala:42:9]
assign auto_out_1_d_ready_0 = x1_nodeOut_d_ready; // @[ProbePicker.scala:42:9]
assign nodeIn_1_d_valid = x1_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_1_d_bits_opcode = x1_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_1_d_bits_param = x1_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_1_d_bits_size = x1_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_1_d_bits_source = x1_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_1_d_bits_sink = x1_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_1_d_bits_denied = x1_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_1_d_bits_data = x1_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_1_d_bits_corrupt = x1_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
TLMonitor_44 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
TLMonitor_45 monitor_1 ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_1_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_1_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_1_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_1_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_1_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_1_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_1_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_1_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_1_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_1_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_1_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_1_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_1_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_1_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_1_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_1_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_1_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_1_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_1_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_1_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
assign auto_in_1_a_ready = auto_in_1_a_ready_0; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_valid = auto_in_1_d_valid_0; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_opcode = auto_in_1_d_bits_opcode_0; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_param = auto_in_1_d_bits_param_0; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_size = auto_in_1_d_bits_size_0; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_source = auto_in_1_d_bits_source_0; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_sink = auto_in_1_d_bits_sink_0; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_denied = auto_in_1_d_bits_denied_0; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_data = auto_in_1_d_bits_data_0; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_corrupt = auto_in_1_d_bits_corrupt_0; // @[ProbePicker.scala:42:9]
assign auto_in_0_a_ready = auto_in_0_a_ready_0; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_valid = auto_in_0_d_valid_0; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_opcode = auto_in_0_d_bits_opcode_0; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_size = auto_in_0_d_bits_size_0; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_source = auto_in_0_d_bits_source_0; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_denied = auto_in_0_d_bits_denied_0; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_data = auto_in_0_d_bits_data_0; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_corrupt = auto_in_0_d_bits_corrupt_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_valid = auto_out_1_a_valid_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_opcode = auto_out_1_a_bits_opcode_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_param = auto_out_1_a_bits_param_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_size = auto_out_1_a_bits_size_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_source = auto_out_1_a_bits_source_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_address = auto_out_1_a_bits_address_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_mask = auto_out_1_a_bits_mask_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_data = auto_out_1_a_bits_data_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_corrupt = auto_out_1_a_bits_corrupt_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_d_ready = auto_out_1_d_ready_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_valid = auto_out_0_a_valid_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_opcode = auto_out_0_a_bits_opcode_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_param = auto_out_0_a_bits_param_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_size = auto_out_0_a_bits_size_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_source = auto_out_0_a_bits_source_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_address = auto_out_0_a_bits_address_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_mask = auto_out_0_a_bits_mask_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_data = auto_out_0_a_bits_data_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_corrupt = auto_out_0_a_bits_corrupt_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_d_ready = auto_out_0_d_ready_0; // @[ProbePicker.scala:42:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_21 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0)
node _source_ok_T_25 = shr(io.in.a.bits.source, 3)
node _source_ok_T_26 = eq(_source_ok_T_25, UInt<3>(0h4))
node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27)
node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h7))
node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29)
node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE : UInt<1>[10]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_30
connect _source_ok_WIRE[6], _source_ok_T_31
connect _source_ok_WIRE[7], _source_ok_T_32
connect _source_ok_WIRE[8], _source_ok_T_33
connect _source_ok_WIRE[9], _source_ok_T_34
node _source_ok_T_35 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[2])
node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[3])
node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[4])
node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[5])
node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[6])
node _source_ok_T_41 = or(_source_ok_T_40, _source_ok_WIRE[7])
node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[8])
node source_ok = or(_source_ok_T_42, _source_ok_WIRE[9])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0)
node _T_64 = shr(io.in.a.bits.source, 3)
node _T_65 = eq(_T_64, UInt<3>(0h4))
node _T_66 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_67 = and(_T_65, _T_66)
node _T_68 = leq(uncommonBits_4, UInt<3>(0h7))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_72 = cvt(_T_71)
node _T_73 = and(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = asSInt(_T_73)
node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0)))
node _T_76 = or(_T_70, _T_75)
node _T_77 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_78 = eq(_T_77, UInt<1>(0h0))
node _T_79 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_80 = cvt(_T_79)
node _T_81 = and(_T_80, asSInt(UInt<1>(0h0)))
node _T_82 = asSInt(_T_81)
node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0)))
node _T_84 = or(_T_78, _T_83)
node _T_85 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_86 = eq(_T_85, UInt<1>(0h0))
node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_88 = cvt(_T_87)
node _T_89 = and(_T_88, asSInt(UInt<1>(0h0)))
node _T_90 = asSInt(_T_89)
node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0)))
node _T_92 = or(_T_86, _T_91)
node _T_93 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_94 = eq(_T_93, UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<1>(0h0)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = or(_T_94, _T_99)
node _T_101 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_102 = eq(_T_101, UInt<1>(0h0))
node _T_103 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_104 = cvt(_T_103)
node _T_105 = and(_T_104, asSInt(UInt<1>(0h0)))
node _T_106 = asSInt(_T_105)
node _T_107 = eq(_T_106, asSInt(UInt<1>(0h0)))
node _T_108 = or(_T_102, _T_107)
node _T_109 = and(_T_11, _T_24)
node _T_110 = and(_T_109, _T_37)
node _T_111 = and(_T_110, _T_50)
node _T_112 = and(_T_111, _T_63)
node _T_113 = and(_T_112, _T_76)
node _T_114 = and(_T_113, _T_84)
node _T_115 = and(_T_114, _T_92)
node _T_116 = and(_T_115, _T_100)
node _T_117 = and(_T_116, _T_108)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_117, UInt<1>(0h1), "") : assert_1
node _T_121 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_121 :
node _T_122 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_123 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_124 = and(_T_122, _T_123)
node _T_125 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_126 = shr(io.in.a.bits.source, 2)
node _T_127 = eq(_T_126, UInt<1>(0h0))
node _T_128 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_129 = and(_T_127, _T_128)
node _T_130 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_131 = and(_T_129, _T_130)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_132 = shr(io.in.a.bits.source, 2)
node _T_133 = eq(_T_132, UInt<1>(0h1))
node _T_134 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_135 = and(_T_133, _T_134)
node _T_136 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_137 = and(_T_135, _T_136)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_138 = shr(io.in.a.bits.source, 2)
node _T_139 = eq(_T_138, UInt<2>(0h2))
node _T_140 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_141 = and(_T_139, _T_140)
node _T_142 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_143 = and(_T_141, _T_142)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_144 = shr(io.in.a.bits.source, 2)
node _T_145 = eq(_T_144, UInt<2>(0h3))
node _T_146 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_147 = and(_T_145, _T_146)
node _T_148 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_149 = and(_T_147, _T_148)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 2, 0)
node _T_150 = shr(io.in.a.bits.source, 3)
node _T_151 = eq(_T_150, UInt<3>(0h4))
node _T_152 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_153 = and(_T_151, _T_152)
node _T_154 = leq(uncommonBits_9, UInt<3>(0h7))
node _T_155 = and(_T_153, _T_154)
node _T_156 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_157 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_158 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_159 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_160 = or(_T_125, _T_131)
node _T_161 = or(_T_160, _T_137)
node _T_162 = or(_T_161, _T_143)
node _T_163 = or(_T_162, _T_149)
node _T_164 = or(_T_163, _T_155)
node _T_165 = or(_T_164, _T_156)
node _T_166 = or(_T_165, _T_157)
node _T_167 = or(_T_166, _T_158)
node _T_168 = or(_T_167, _T_159)
node _T_169 = and(_T_124, _T_168)
node _T_170 = or(UInt<1>(0h0), _T_169)
node _T_171 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_172 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_173 = cvt(_T_172)
node _T_174 = and(_T_173, asSInt(UInt<14>(0h2000)))
node _T_175 = asSInt(_T_174)
node _T_176 = eq(_T_175, asSInt(UInt<1>(0h0)))
node _T_177 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_178 = cvt(_T_177)
node _T_179 = and(_T_178, asSInt(UInt<13>(0h1000)))
node _T_180 = asSInt(_T_179)
node _T_181 = eq(_T_180, asSInt(UInt<1>(0h0)))
node _T_182 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_183 = cvt(_T_182)
node _T_184 = and(_T_183, asSInt(UInt<17>(0h10000)))
node _T_185 = asSInt(_T_184)
node _T_186 = eq(_T_185, asSInt(UInt<1>(0h0)))
node _T_187 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_188 = cvt(_T_187)
node _T_189 = and(_T_188, asSInt(UInt<18>(0h2f000)))
node _T_190 = asSInt(_T_189)
node _T_191 = eq(_T_190, asSInt(UInt<1>(0h0)))
node _T_192 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_193 = cvt(_T_192)
node _T_194 = and(_T_193, asSInt(UInt<17>(0h10000)))
node _T_195 = asSInt(_T_194)
node _T_196 = eq(_T_195, asSInt(UInt<1>(0h0)))
node _T_197 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_198 = cvt(_T_197)
node _T_199 = and(_T_198, asSInt(UInt<13>(0h1000)))
node _T_200 = asSInt(_T_199)
node _T_201 = eq(_T_200, asSInt(UInt<1>(0h0)))
node _T_202 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_203 = cvt(_T_202)
node _T_204 = and(_T_203, asSInt(UInt<27>(0h4000000)))
node _T_205 = asSInt(_T_204)
node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0)))
node _T_207 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_208 = cvt(_T_207)
node _T_209 = and(_T_208, asSInt(UInt<13>(0h1000)))
node _T_210 = asSInt(_T_209)
node _T_211 = eq(_T_210, asSInt(UInt<1>(0h0)))
node _T_212 = or(_T_176, _T_181)
node _T_213 = or(_T_212, _T_186)
node _T_214 = or(_T_213, _T_191)
node _T_215 = or(_T_214, _T_196)
node _T_216 = or(_T_215, _T_201)
node _T_217 = or(_T_216, _T_206)
node _T_218 = or(_T_217, _T_211)
node _T_219 = and(_T_171, _T_218)
node _T_220 = or(UInt<1>(0h0), _T_219)
node _T_221 = and(_T_170, _T_220)
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_T_221, UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_221, UInt<1>(0h1), "") : assert_2
node _T_225 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_226 = shr(io.in.a.bits.source, 2)
node _T_227 = eq(_T_226, UInt<1>(0h0))
node _T_228 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_229 = and(_T_227, _T_228)
node _T_230 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_231 = and(_T_229, _T_230)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_232 = shr(io.in.a.bits.source, 2)
node _T_233 = eq(_T_232, UInt<1>(0h1))
node _T_234 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_235 = and(_T_233, _T_234)
node _T_236 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_237 = and(_T_235, _T_236)
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_238 = shr(io.in.a.bits.source, 2)
node _T_239 = eq(_T_238, UInt<2>(0h2))
node _T_240 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_241 = and(_T_239, _T_240)
node _T_242 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_243 = and(_T_241, _T_242)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_244 = shr(io.in.a.bits.source, 2)
node _T_245 = eq(_T_244, UInt<2>(0h3))
node _T_246 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_247 = and(_T_245, _T_246)
node _T_248 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_249 = and(_T_247, _T_248)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 2, 0)
node _T_250 = shr(io.in.a.bits.source, 3)
node _T_251 = eq(_T_250, UInt<3>(0h4))
node _T_252 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_253 = and(_T_251, _T_252)
node _T_254 = leq(uncommonBits_14, UInt<3>(0h7))
node _T_255 = and(_T_253, _T_254)
node _T_256 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_257 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_258 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_259 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE : UInt<1>[10]
connect _WIRE[0], _T_225
connect _WIRE[1], _T_231
connect _WIRE[2], _T_237
connect _WIRE[3], _T_243
connect _WIRE[4], _T_249
connect _WIRE[5], _T_255
connect _WIRE[6], _T_256
connect _WIRE[7], _T_257
connect _WIRE[8], _T_258
connect _WIRE[9], _T_259
node _T_260 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_261 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_262 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_263 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_264 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_265 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_266 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_267 = mux(_WIRE[6], _T_260, UInt<1>(0h0))
node _T_268 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_269 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_270 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_271 = or(_T_261, _T_262)
node _T_272 = or(_T_271, _T_263)
node _T_273 = or(_T_272, _T_264)
node _T_274 = or(_T_273, _T_265)
node _T_275 = or(_T_274, _T_266)
node _T_276 = or(_T_275, _T_267)
node _T_277 = or(_T_276, _T_268)
node _T_278 = or(_T_277, _T_269)
node _T_279 = or(_T_278, _T_270)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_279
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _T_283 = or(UInt<1>(0h0), _T_282)
node _T_284 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_285 = cvt(_T_284)
node _T_286 = and(_T_285, asSInt(UInt<14>(0h2000)))
node _T_287 = asSInt(_T_286)
node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0)))
node _T_289 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_290 = cvt(_T_289)
node _T_291 = and(_T_290, asSInt(UInt<13>(0h1000)))
node _T_292 = asSInt(_T_291)
node _T_293 = eq(_T_292, asSInt(UInt<1>(0h0)))
node _T_294 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_295 = cvt(_T_294)
node _T_296 = and(_T_295, asSInt(UInt<17>(0h10000)))
node _T_297 = asSInt(_T_296)
node _T_298 = eq(_T_297, asSInt(UInt<1>(0h0)))
node _T_299 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_300 = cvt(_T_299)
node _T_301 = and(_T_300, asSInt(UInt<18>(0h2f000)))
node _T_302 = asSInt(_T_301)
node _T_303 = eq(_T_302, asSInt(UInt<1>(0h0)))
node _T_304 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_305 = cvt(_T_304)
node _T_306 = and(_T_305, asSInt(UInt<17>(0h10000)))
node _T_307 = asSInt(_T_306)
node _T_308 = eq(_T_307, asSInt(UInt<1>(0h0)))
node _T_309 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_310 = cvt(_T_309)
node _T_311 = and(_T_310, asSInt(UInt<13>(0h1000)))
node _T_312 = asSInt(_T_311)
node _T_313 = eq(_T_312, asSInt(UInt<1>(0h0)))
node _T_314 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_315 = cvt(_T_314)
node _T_316 = and(_T_315, asSInt(UInt<27>(0h4000000)))
node _T_317 = asSInt(_T_316)
node _T_318 = eq(_T_317, asSInt(UInt<1>(0h0)))
node _T_319 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_320 = cvt(_T_319)
node _T_321 = and(_T_320, asSInt(UInt<13>(0h1000)))
node _T_322 = asSInt(_T_321)
node _T_323 = eq(_T_322, asSInt(UInt<1>(0h0)))
node _T_324 = or(_T_288, _T_293)
node _T_325 = or(_T_324, _T_298)
node _T_326 = or(_T_325, _T_303)
node _T_327 = or(_T_326, _T_308)
node _T_328 = or(_T_327, _T_313)
node _T_329 = or(_T_328, _T_318)
node _T_330 = or(_T_329, _T_323)
node _T_331 = and(_T_283, _T_330)
node _T_332 = or(UInt<1>(0h0), _T_331)
node _T_333 = and(_WIRE_1, _T_332)
node _T_334 = asUInt(reset)
node _T_335 = eq(_T_334, UInt<1>(0h0))
when _T_335 :
node _T_336 = eq(_T_333, UInt<1>(0h0))
when _T_336 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_333, UInt<1>(0h1), "") : assert_3
node _T_337 = asUInt(reset)
node _T_338 = eq(_T_337, UInt<1>(0h0))
when _T_338 :
node _T_339 = eq(source_ok, UInt<1>(0h0))
when _T_339 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_340 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_T_340, UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_340, UInt<1>(0h1), "") : assert_5
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_347 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_347, UInt<1>(0h1), "") : assert_7
node _T_351 = not(io.in.a.bits.mask)
node _T_352 = eq(_T_351, UInt<1>(0h0))
node _T_353 = asUInt(reset)
node _T_354 = eq(_T_353, UInt<1>(0h0))
when _T_354 :
node _T_355 = eq(_T_352, UInt<1>(0h0))
when _T_355 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_352, UInt<1>(0h1), "") : assert_8
node _T_356 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_357 = asUInt(reset)
node _T_358 = eq(_T_357, UInt<1>(0h0))
when _T_358 :
node _T_359 = eq(_T_356, UInt<1>(0h0))
when _T_359 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_356, UInt<1>(0h1), "") : assert_9
node _T_360 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_360 :
node _T_361 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_362 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_363 = and(_T_361, _T_362)
node _T_364 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_365 = shr(io.in.a.bits.source, 2)
node _T_366 = eq(_T_365, UInt<1>(0h0))
node _T_367 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_368 = and(_T_366, _T_367)
node _T_369 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_370 = and(_T_368, _T_369)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_371 = shr(io.in.a.bits.source, 2)
node _T_372 = eq(_T_371, UInt<1>(0h1))
node _T_373 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_374 = and(_T_372, _T_373)
node _T_375 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_376 = and(_T_374, _T_375)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_377 = shr(io.in.a.bits.source, 2)
node _T_378 = eq(_T_377, UInt<2>(0h2))
node _T_379 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_380 = and(_T_378, _T_379)
node _T_381 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_382 = and(_T_380, _T_381)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_383 = shr(io.in.a.bits.source, 2)
node _T_384 = eq(_T_383, UInt<2>(0h3))
node _T_385 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_386 = and(_T_384, _T_385)
node _T_387 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_388 = and(_T_386, _T_387)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0)
node _T_389 = shr(io.in.a.bits.source, 3)
node _T_390 = eq(_T_389, UInt<3>(0h4))
node _T_391 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_392 = and(_T_390, _T_391)
node _T_393 = leq(uncommonBits_19, UInt<3>(0h7))
node _T_394 = and(_T_392, _T_393)
node _T_395 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_396 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_397 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_398 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_399 = or(_T_364, _T_370)
node _T_400 = or(_T_399, _T_376)
node _T_401 = or(_T_400, _T_382)
node _T_402 = or(_T_401, _T_388)
node _T_403 = or(_T_402, _T_394)
node _T_404 = or(_T_403, _T_395)
node _T_405 = or(_T_404, _T_396)
node _T_406 = or(_T_405, _T_397)
node _T_407 = or(_T_406, _T_398)
node _T_408 = and(_T_363, _T_407)
node _T_409 = or(UInt<1>(0h0), _T_408)
node _T_410 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_411 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_412 = cvt(_T_411)
node _T_413 = and(_T_412, asSInt(UInt<14>(0h2000)))
node _T_414 = asSInt(_T_413)
node _T_415 = eq(_T_414, asSInt(UInt<1>(0h0)))
node _T_416 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_417 = cvt(_T_416)
node _T_418 = and(_T_417, asSInt(UInt<13>(0h1000)))
node _T_419 = asSInt(_T_418)
node _T_420 = eq(_T_419, asSInt(UInt<1>(0h0)))
node _T_421 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_422 = cvt(_T_421)
node _T_423 = and(_T_422, asSInt(UInt<17>(0h10000)))
node _T_424 = asSInt(_T_423)
node _T_425 = eq(_T_424, asSInt(UInt<1>(0h0)))
node _T_426 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_427 = cvt(_T_426)
node _T_428 = and(_T_427, asSInt(UInt<18>(0h2f000)))
node _T_429 = asSInt(_T_428)
node _T_430 = eq(_T_429, asSInt(UInt<1>(0h0)))
node _T_431 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_432 = cvt(_T_431)
node _T_433 = and(_T_432, asSInt(UInt<17>(0h10000)))
node _T_434 = asSInt(_T_433)
node _T_435 = eq(_T_434, asSInt(UInt<1>(0h0)))
node _T_436 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_437 = cvt(_T_436)
node _T_438 = and(_T_437, asSInt(UInt<13>(0h1000)))
node _T_439 = asSInt(_T_438)
node _T_440 = eq(_T_439, asSInt(UInt<1>(0h0)))
node _T_441 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_442 = cvt(_T_441)
node _T_443 = and(_T_442, asSInt(UInt<27>(0h4000000)))
node _T_444 = asSInt(_T_443)
node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0)))
node _T_446 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_447 = cvt(_T_446)
node _T_448 = and(_T_447, asSInt(UInt<13>(0h1000)))
node _T_449 = asSInt(_T_448)
node _T_450 = eq(_T_449, asSInt(UInt<1>(0h0)))
node _T_451 = or(_T_415, _T_420)
node _T_452 = or(_T_451, _T_425)
node _T_453 = or(_T_452, _T_430)
node _T_454 = or(_T_453, _T_435)
node _T_455 = or(_T_454, _T_440)
node _T_456 = or(_T_455, _T_445)
node _T_457 = or(_T_456, _T_450)
node _T_458 = and(_T_410, _T_457)
node _T_459 = or(UInt<1>(0h0), _T_458)
node _T_460 = and(_T_409, _T_459)
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_460, UInt<1>(0h1), "") : assert_10
node _T_464 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_465 = shr(io.in.a.bits.source, 2)
node _T_466 = eq(_T_465, UInt<1>(0h0))
node _T_467 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_468 = and(_T_466, _T_467)
node _T_469 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_470 = and(_T_468, _T_469)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_471 = shr(io.in.a.bits.source, 2)
node _T_472 = eq(_T_471, UInt<1>(0h1))
node _T_473 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_474 = and(_T_472, _T_473)
node _T_475 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_476 = and(_T_474, _T_475)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_477 = shr(io.in.a.bits.source, 2)
node _T_478 = eq(_T_477, UInt<2>(0h2))
node _T_479 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_480 = and(_T_478, _T_479)
node _T_481 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_482 = and(_T_480, _T_481)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_483 = shr(io.in.a.bits.source, 2)
node _T_484 = eq(_T_483, UInt<2>(0h3))
node _T_485 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_486 = and(_T_484, _T_485)
node _T_487 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_488 = and(_T_486, _T_487)
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 2, 0)
node _T_489 = shr(io.in.a.bits.source, 3)
node _T_490 = eq(_T_489, UInt<3>(0h4))
node _T_491 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_492 = and(_T_490, _T_491)
node _T_493 = leq(uncommonBits_24, UInt<3>(0h7))
node _T_494 = and(_T_492, _T_493)
node _T_495 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_496 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_497 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_498 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE_2 : UInt<1>[10]
connect _WIRE_2[0], _T_464
connect _WIRE_2[1], _T_470
connect _WIRE_2[2], _T_476
connect _WIRE_2[3], _T_482
connect _WIRE_2[4], _T_488
connect _WIRE_2[5], _T_494
connect _WIRE_2[6], _T_495
connect _WIRE_2[7], _T_496
connect _WIRE_2[8], _T_497
connect _WIRE_2[9], _T_498
node _T_499 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_500 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_501 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_502 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_503 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_504 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_505 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_506 = mux(_WIRE_2[6], _T_499, UInt<1>(0h0))
node _T_507 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_508 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_509 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_510 = or(_T_500, _T_501)
node _T_511 = or(_T_510, _T_502)
node _T_512 = or(_T_511, _T_503)
node _T_513 = or(_T_512, _T_504)
node _T_514 = or(_T_513, _T_505)
node _T_515 = or(_T_514, _T_506)
node _T_516 = or(_T_515, _T_507)
node _T_517 = or(_T_516, _T_508)
node _T_518 = or(_T_517, _T_509)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_518
node _T_519 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_520 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_521 = and(_T_519, _T_520)
node _T_522 = or(UInt<1>(0h0), _T_521)
node _T_523 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_524 = cvt(_T_523)
node _T_525 = and(_T_524, asSInt(UInt<14>(0h2000)))
node _T_526 = asSInt(_T_525)
node _T_527 = eq(_T_526, asSInt(UInt<1>(0h0)))
node _T_528 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_529 = cvt(_T_528)
node _T_530 = and(_T_529, asSInt(UInt<13>(0h1000)))
node _T_531 = asSInt(_T_530)
node _T_532 = eq(_T_531, asSInt(UInt<1>(0h0)))
node _T_533 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_534 = cvt(_T_533)
node _T_535 = and(_T_534, asSInt(UInt<17>(0h10000)))
node _T_536 = asSInt(_T_535)
node _T_537 = eq(_T_536, asSInt(UInt<1>(0h0)))
node _T_538 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_539 = cvt(_T_538)
node _T_540 = and(_T_539, asSInt(UInt<18>(0h2f000)))
node _T_541 = asSInt(_T_540)
node _T_542 = eq(_T_541, asSInt(UInt<1>(0h0)))
node _T_543 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_544 = cvt(_T_543)
node _T_545 = and(_T_544, asSInt(UInt<17>(0h10000)))
node _T_546 = asSInt(_T_545)
node _T_547 = eq(_T_546, asSInt(UInt<1>(0h0)))
node _T_548 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_549 = cvt(_T_548)
node _T_550 = and(_T_549, asSInt(UInt<13>(0h1000)))
node _T_551 = asSInt(_T_550)
node _T_552 = eq(_T_551, asSInt(UInt<1>(0h0)))
node _T_553 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_554 = cvt(_T_553)
node _T_555 = and(_T_554, asSInt(UInt<27>(0h4000000)))
node _T_556 = asSInt(_T_555)
node _T_557 = eq(_T_556, asSInt(UInt<1>(0h0)))
node _T_558 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_559 = cvt(_T_558)
node _T_560 = and(_T_559, asSInt(UInt<13>(0h1000)))
node _T_561 = asSInt(_T_560)
node _T_562 = eq(_T_561, asSInt(UInt<1>(0h0)))
node _T_563 = or(_T_527, _T_532)
node _T_564 = or(_T_563, _T_537)
node _T_565 = or(_T_564, _T_542)
node _T_566 = or(_T_565, _T_547)
node _T_567 = or(_T_566, _T_552)
node _T_568 = or(_T_567, _T_557)
node _T_569 = or(_T_568, _T_562)
node _T_570 = and(_T_522, _T_569)
node _T_571 = or(UInt<1>(0h0), _T_570)
node _T_572 = and(_WIRE_3, _T_571)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_572, UInt<1>(0h1), "") : assert_11
node _T_576 = asUInt(reset)
node _T_577 = eq(_T_576, UInt<1>(0h0))
when _T_577 :
node _T_578 = eq(source_ok, UInt<1>(0h0))
when _T_578 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_579 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_580 = asUInt(reset)
node _T_581 = eq(_T_580, UInt<1>(0h0))
when _T_581 :
node _T_582 = eq(_T_579, UInt<1>(0h0))
when _T_582 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_579, UInt<1>(0h1), "") : assert_13
node _T_583 = asUInt(reset)
node _T_584 = eq(_T_583, UInt<1>(0h0))
when _T_584 :
node _T_585 = eq(is_aligned, UInt<1>(0h0))
when _T_585 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_586 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_587 = asUInt(reset)
node _T_588 = eq(_T_587, UInt<1>(0h0))
when _T_588 :
node _T_589 = eq(_T_586, UInt<1>(0h0))
when _T_589 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_586, UInt<1>(0h1), "") : assert_15
node _T_590 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_591 = asUInt(reset)
node _T_592 = eq(_T_591, UInt<1>(0h0))
when _T_592 :
node _T_593 = eq(_T_590, UInt<1>(0h0))
when _T_593 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_590, UInt<1>(0h1), "") : assert_16
node _T_594 = not(io.in.a.bits.mask)
node _T_595 = eq(_T_594, UInt<1>(0h0))
node _T_596 = asUInt(reset)
node _T_597 = eq(_T_596, UInt<1>(0h0))
when _T_597 :
node _T_598 = eq(_T_595, UInt<1>(0h0))
when _T_598 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_595, UInt<1>(0h1), "") : assert_17
node _T_599 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_600 = asUInt(reset)
node _T_601 = eq(_T_600, UInt<1>(0h0))
when _T_601 :
node _T_602 = eq(_T_599, UInt<1>(0h0))
when _T_602 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_599, UInt<1>(0h1), "") : assert_18
node _T_603 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_603 :
node _T_604 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_605 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_606 = and(_T_604, _T_605)
node _T_607 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_608 = shr(io.in.a.bits.source, 2)
node _T_609 = eq(_T_608, UInt<1>(0h0))
node _T_610 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_611 = and(_T_609, _T_610)
node _T_612 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_613 = and(_T_611, _T_612)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_614 = shr(io.in.a.bits.source, 2)
node _T_615 = eq(_T_614, UInt<1>(0h1))
node _T_616 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_617 = and(_T_615, _T_616)
node _T_618 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_619 = and(_T_617, _T_618)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_620 = shr(io.in.a.bits.source, 2)
node _T_621 = eq(_T_620, UInt<2>(0h2))
node _T_622 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_623 = and(_T_621, _T_622)
node _T_624 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_625 = and(_T_623, _T_624)
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_626 = shr(io.in.a.bits.source, 2)
node _T_627 = eq(_T_626, UInt<2>(0h3))
node _T_628 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_629 = and(_T_627, _T_628)
node _T_630 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_631 = and(_T_629, _T_630)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 2, 0)
node _T_632 = shr(io.in.a.bits.source, 3)
node _T_633 = eq(_T_632, UInt<3>(0h4))
node _T_634 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_635 = and(_T_633, _T_634)
node _T_636 = leq(uncommonBits_29, UInt<3>(0h7))
node _T_637 = and(_T_635, _T_636)
node _T_638 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_639 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_640 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_641 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_642 = or(_T_607, _T_613)
node _T_643 = or(_T_642, _T_619)
node _T_644 = or(_T_643, _T_625)
node _T_645 = or(_T_644, _T_631)
node _T_646 = or(_T_645, _T_637)
node _T_647 = or(_T_646, _T_638)
node _T_648 = or(_T_647, _T_639)
node _T_649 = or(_T_648, _T_640)
node _T_650 = or(_T_649, _T_641)
node _T_651 = and(_T_606, _T_650)
node _T_652 = or(UInt<1>(0h0), _T_651)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_652, UInt<1>(0h1), "") : assert_19
node _T_656 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_657 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_658 = and(_T_656, _T_657)
node _T_659 = or(UInt<1>(0h0), _T_658)
node _T_660 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_661 = cvt(_T_660)
node _T_662 = and(_T_661, asSInt(UInt<13>(0h1000)))
node _T_663 = asSInt(_T_662)
node _T_664 = eq(_T_663, asSInt(UInt<1>(0h0)))
node _T_665 = and(_T_659, _T_664)
node _T_666 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_667 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_668 = and(_T_666, _T_667)
node _T_669 = or(UInt<1>(0h0), _T_668)
node _T_670 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_671 = cvt(_T_670)
node _T_672 = and(_T_671, asSInt(UInt<14>(0h2000)))
node _T_673 = asSInt(_T_672)
node _T_674 = eq(_T_673, asSInt(UInt<1>(0h0)))
node _T_675 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_676 = cvt(_T_675)
node _T_677 = and(_T_676, asSInt(UInt<17>(0h10000)))
node _T_678 = asSInt(_T_677)
node _T_679 = eq(_T_678, asSInt(UInt<1>(0h0)))
node _T_680 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_681 = cvt(_T_680)
node _T_682 = and(_T_681, asSInt(UInt<18>(0h2f000)))
node _T_683 = asSInt(_T_682)
node _T_684 = eq(_T_683, asSInt(UInt<1>(0h0)))
node _T_685 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_686 = cvt(_T_685)
node _T_687 = and(_T_686, asSInt(UInt<17>(0h10000)))
node _T_688 = asSInt(_T_687)
node _T_689 = eq(_T_688, asSInt(UInt<1>(0h0)))
node _T_690 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_691 = cvt(_T_690)
node _T_692 = and(_T_691, asSInt(UInt<13>(0h1000)))
node _T_693 = asSInt(_T_692)
node _T_694 = eq(_T_693, asSInt(UInt<1>(0h0)))
node _T_695 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_696 = cvt(_T_695)
node _T_697 = and(_T_696, asSInt(UInt<27>(0h4000000)))
node _T_698 = asSInt(_T_697)
node _T_699 = eq(_T_698, asSInt(UInt<1>(0h0)))
node _T_700 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_701 = cvt(_T_700)
node _T_702 = and(_T_701, asSInt(UInt<13>(0h1000)))
node _T_703 = asSInt(_T_702)
node _T_704 = eq(_T_703, asSInt(UInt<1>(0h0)))
node _T_705 = or(_T_674, _T_679)
node _T_706 = or(_T_705, _T_684)
node _T_707 = or(_T_706, _T_689)
node _T_708 = or(_T_707, _T_694)
node _T_709 = or(_T_708, _T_699)
node _T_710 = or(_T_709, _T_704)
node _T_711 = and(_T_669, _T_710)
node _T_712 = or(UInt<1>(0h0), _T_665)
node _T_713 = or(_T_712, _T_711)
node _T_714 = asUInt(reset)
node _T_715 = eq(_T_714, UInt<1>(0h0))
when _T_715 :
node _T_716 = eq(_T_713, UInt<1>(0h0))
when _T_716 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_713, UInt<1>(0h1), "") : assert_20
node _T_717 = asUInt(reset)
node _T_718 = eq(_T_717, UInt<1>(0h0))
when _T_718 :
node _T_719 = eq(source_ok, UInt<1>(0h0))
when _T_719 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_720 = asUInt(reset)
node _T_721 = eq(_T_720, UInt<1>(0h0))
when _T_721 :
node _T_722 = eq(is_aligned, UInt<1>(0h0))
when _T_722 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_723 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_724 = asUInt(reset)
node _T_725 = eq(_T_724, UInt<1>(0h0))
when _T_725 :
node _T_726 = eq(_T_723, UInt<1>(0h0))
when _T_726 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_723, UInt<1>(0h1), "") : assert_23
node _T_727 = eq(io.in.a.bits.mask, mask)
node _T_728 = asUInt(reset)
node _T_729 = eq(_T_728, UInt<1>(0h0))
when _T_729 :
node _T_730 = eq(_T_727, UInt<1>(0h0))
when _T_730 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_727, UInt<1>(0h1), "") : assert_24
node _T_731 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_732 = asUInt(reset)
node _T_733 = eq(_T_732, UInt<1>(0h0))
when _T_733 :
node _T_734 = eq(_T_731, UInt<1>(0h0))
when _T_734 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_731, UInt<1>(0h1), "") : assert_25
node _T_735 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_735 :
node _T_736 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_737 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_738 = and(_T_736, _T_737)
node _T_739 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_740 = shr(io.in.a.bits.source, 2)
node _T_741 = eq(_T_740, UInt<1>(0h0))
node _T_742 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_743 = and(_T_741, _T_742)
node _T_744 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_745 = and(_T_743, _T_744)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_746 = shr(io.in.a.bits.source, 2)
node _T_747 = eq(_T_746, UInt<1>(0h1))
node _T_748 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_749 = and(_T_747, _T_748)
node _T_750 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_751 = and(_T_749, _T_750)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_752 = shr(io.in.a.bits.source, 2)
node _T_753 = eq(_T_752, UInt<2>(0h2))
node _T_754 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_755 = and(_T_753, _T_754)
node _T_756 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_757 = and(_T_755, _T_756)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_758 = shr(io.in.a.bits.source, 2)
node _T_759 = eq(_T_758, UInt<2>(0h3))
node _T_760 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_761 = and(_T_759, _T_760)
node _T_762 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_763 = and(_T_761, _T_762)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0)
node _T_764 = shr(io.in.a.bits.source, 3)
node _T_765 = eq(_T_764, UInt<3>(0h4))
node _T_766 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_767 = and(_T_765, _T_766)
node _T_768 = leq(uncommonBits_34, UInt<3>(0h7))
node _T_769 = and(_T_767, _T_768)
node _T_770 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_771 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_772 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_773 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_774 = or(_T_739, _T_745)
node _T_775 = or(_T_774, _T_751)
node _T_776 = or(_T_775, _T_757)
node _T_777 = or(_T_776, _T_763)
node _T_778 = or(_T_777, _T_769)
node _T_779 = or(_T_778, _T_770)
node _T_780 = or(_T_779, _T_771)
node _T_781 = or(_T_780, _T_772)
node _T_782 = or(_T_781, _T_773)
node _T_783 = and(_T_738, _T_782)
node _T_784 = or(UInt<1>(0h0), _T_783)
node _T_785 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_786 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_787 = and(_T_785, _T_786)
node _T_788 = or(UInt<1>(0h0), _T_787)
node _T_789 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_790 = cvt(_T_789)
node _T_791 = and(_T_790, asSInt(UInt<13>(0h1000)))
node _T_792 = asSInt(_T_791)
node _T_793 = eq(_T_792, asSInt(UInt<1>(0h0)))
node _T_794 = and(_T_788, _T_793)
node _T_795 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_796 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_797 = and(_T_795, _T_796)
node _T_798 = or(UInt<1>(0h0), _T_797)
node _T_799 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_800 = cvt(_T_799)
node _T_801 = and(_T_800, asSInt(UInt<14>(0h2000)))
node _T_802 = asSInt(_T_801)
node _T_803 = eq(_T_802, asSInt(UInt<1>(0h0)))
node _T_804 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_805 = cvt(_T_804)
node _T_806 = and(_T_805, asSInt(UInt<18>(0h2f000)))
node _T_807 = asSInt(_T_806)
node _T_808 = eq(_T_807, asSInt(UInt<1>(0h0)))
node _T_809 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_810 = cvt(_T_809)
node _T_811 = and(_T_810, asSInt(UInt<17>(0h10000)))
node _T_812 = asSInt(_T_811)
node _T_813 = eq(_T_812, asSInt(UInt<1>(0h0)))
node _T_814 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_815 = cvt(_T_814)
node _T_816 = and(_T_815, asSInt(UInt<13>(0h1000)))
node _T_817 = asSInt(_T_816)
node _T_818 = eq(_T_817, asSInt(UInt<1>(0h0)))
node _T_819 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_820 = cvt(_T_819)
node _T_821 = and(_T_820, asSInt(UInt<27>(0h4000000)))
node _T_822 = asSInt(_T_821)
node _T_823 = eq(_T_822, asSInt(UInt<1>(0h0)))
node _T_824 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_825 = cvt(_T_824)
node _T_826 = and(_T_825, asSInt(UInt<13>(0h1000)))
node _T_827 = asSInt(_T_826)
node _T_828 = eq(_T_827, asSInt(UInt<1>(0h0)))
node _T_829 = or(_T_803, _T_808)
node _T_830 = or(_T_829, _T_813)
node _T_831 = or(_T_830, _T_818)
node _T_832 = or(_T_831, _T_823)
node _T_833 = or(_T_832, _T_828)
node _T_834 = and(_T_798, _T_833)
node _T_835 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_836 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_837 = cvt(_T_836)
node _T_838 = and(_T_837, asSInt(UInt<17>(0h10000)))
node _T_839 = asSInt(_T_838)
node _T_840 = eq(_T_839, asSInt(UInt<1>(0h0)))
node _T_841 = and(_T_835, _T_840)
node _T_842 = or(UInt<1>(0h0), _T_794)
node _T_843 = or(_T_842, _T_834)
node _T_844 = or(_T_843, _T_841)
node _T_845 = and(_T_784, _T_844)
node _T_846 = asUInt(reset)
node _T_847 = eq(_T_846, UInt<1>(0h0))
when _T_847 :
node _T_848 = eq(_T_845, UInt<1>(0h0))
when _T_848 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_845, UInt<1>(0h1), "") : assert_26
node _T_849 = asUInt(reset)
node _T_850 = eq(_T_849, UInt<1>(0h0))
when _T_850 :
node _T_851 = eq(source_ok, UInt<1>(0h0))
when _T_851 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_852 = asUInt(reset)
node _T_853 = eq(_T_852, UInt<1>(0h0))
when _T_853 :
node _T_854 = eq(is_aligned, UInt<1>(0h0))
when _T_854 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_855 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_856 = asUInt(reset)
node _T_857 = eq(_T_856, UInt<1>(0h0))
when _T_857 :
node _T_858 = eq(_T_855, UInt<1>(0h0))
when _T_858 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_855, UInt<1>(0h1), "") : assert_29
node _T_859 = eq(io.in.a.bits.mask, mask)
node _T_860 = asUInt(reset)
node _T_861 = eq(_T_860, UInt<1>(0h0))
when _T_861 :
node _T_862 = eq(_T_859, UInt<1>(0h0))
when _T_862 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_859, UInt<1>(0h1), "") : assert_30
node _T_863 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_863 :
node _T_864 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_865 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_866 = and(_T_864, _T_865)
node _T_867 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_868 = shr(io.in.a.bits.source, 2)
node _T_869 = eq(_T_868, UInt<1>(0h0))
node _T_870 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_871 = and(_T_869, _T_870)
node _T_872 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_873 = and(_T_871, _T_872)
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_874 = shr(io.in.a.bits.source, 2)
node _T_875 = eq(_T_874, UInt<1>(0h1))
node _T_876 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_877 = and(_T_875, _T_876)
node _T_878 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_879 = and(_T_877, _T_878)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_880 = shr(io.in.a.bits.source, 2)
node _T_881 = eq(_T_880, UInt<2>(0h2))
node _T_882 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_883 = and(_T_881, _T_882)
node _T_884 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_885 = and(_T_883, _T_884)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_886 = shr(io.in.a.bits.source, 2)
node _T_887 = eq(_T_886, UInt<2>(0h3))
node _T_888 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_889 = and(_T_887, _T_888)
node _T_890 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_891 = and(_T_889, _T_890)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0)
node _T_892 = shr(io.in.a.bits.source, 3)
node _T_893 = eq(_T_892, UInt<3>(0h4))
node _T_894 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_895 = and(_T_893, _T_894)
node _T_896 = leq(uncommonBits_39, UInt<3>(0h7))
node _T_897 = and(_T_895, _T_896)
node _T_898 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_899 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_900 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_901 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_902 = or(_T_867, _T_873)
node _T_903 = or(_T_902, _T_879)
node _T_904 = or(_T_903, _T_885)
node _T_905 = or(_T_904, _T_891)
node _T_906 = or(_T_905, _T_897)
node _T_907 = or(_T_906, _T_898)
node _T_908 = or(_T_907, _T_899)
node _T_909 = or(_T_908, _T_900)
node _T_910 = or(_T_909, _T_901)
node _T_911 = and(_T_866, _T_910)
node _T_912 = or(UInt<1>(0h0), _T_911)
node _T_913 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_914 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_915 = and(_T_913, _T_914)
node _T_916 = or(UInt<1>(0h0), _T_915)
node _T_917 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_918 = cvt(_T_917)
node _T_919 = and(_T_918, asSInt(UInt<13>(0h1000)))
node _T_920 = asSInt(_T_919)
node _T_921 = eq(_T_920, asSInt(UInt<1>(0h0)))
node _T_922 = and(_T_916, _T_921)
node _T_923 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_924 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_925 = and(_T_923, _T_924)
node _T_926 = or(UInt<1>(0h0), _T_925)
node _T_927 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_928 = cvt(_T_927)
node _T_929 = and(_T_928, asSInt(UInt<14>(0h2000)))
node _T_930 = asSInt(_T_929)
node _T_931 = eq(_T_930, asSInt(UInt<1>(0h0)))
node _T_932 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_933 = cvt(_T_932)
node _T_934 = and(_T_933, asSInt(UInt<18>(0h2f000)))
node _T_935 = asSInt(_T_934)
node _T_936 = eq(_T_935, asSInt(UInt<1>(0h0)))
node _T_937 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_938 = cvt(_T_937)
node _T_939 = and(_T_938, asSInt(UInt<17>(0h10000)))
node _T_940 = asSInt(_T_939)
node _T_941 = eq(_T_940, asSInt(UInt<1>(0h0)))
node _T_942 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_943 = cvt(_T_942)
node _T_944 = and(_T_943, asSInt(UInt<13>(0h1000)))
node _T_945 = asSInt(_T_944)
node _T_946 = eq(_T_945, asSInt(UInt<1>(0h0)))
node _T_947 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_948 = cvt(_T_947)
node _T_949 = and(_T_948, asSInt(UInt<27>(0h4000000)))
node _T_950 = asSInt(_T_949)
node _T_951 = eq(_T_950, asSInt(UInt<1>(0h0)))
node _T_952 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_953 = cvt(_T_952)
node _T_954 = and(_T_953, asSInt(UInt<13>(0h1000)))
node _T_955 = asSInt(_T_954)
node _T_956 = eq(_T_955, asSInt(UInt<1>(0h0)))
node _T_957 = or(_T_931, _T_936)
node _T_958 = or(_T_957, _T_941)
node _T_959 = or(_T_958, _T_946)
node _T_960 = or(_T_959, _T_951)
node _T_961 = or(_T_960, _T_956)
node _T_962 = and(_T_926, _T_961)
node _T_963 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_964 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_965 = cvt(_T_964)
node _T_966 = and(_T_965, asSInt(UInt<17>(0h10000)))
node _T_967 = asSInt(_T_966)
node _T_968 = eq(_T_967, asSInt(UInt<1>(0h0)))
node _T_969 = and(_T_963, _T_968)
node _T_970 = or(UInt<1>(0h0), _T_922)
node _T_971 = or(_T_970, _T_962)
node _T_972 = or(_T_971, _T_969)
node _T_973 = and(_T_912, _T_972)
node _T_974 = asUInt(reset)
node _T_975 = eq(_T_974, UInt<1>(0h0))
when _T_975 :
node _T_976 = eq(_T_973, UInt<1>(0h0))
when _T_976 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_973, UInt<1>(0h1), "") : assert_31
node _T_977 = asUInt(reset)
node _T_978 = eq(_T_977, UInt<1>(0h0))
when _T_978 :
node _T_979 = eq(source_ok, UInt<1>(0h0))
when _T_979 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_980 = asUInt(reset)
node _T_981 = eq(_T_980, UInt<1>(0h0))
when _T_981 :
node _T_982 = eq(is_aligned, UInt<1>(0h0))
when _T_982 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_983 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_984 = asUInt(reset)
node _T_985 = eq(_T_984, UInt<1>(0h0))
when _T_985 :
node _T_986 = eq(_T_983, UInt<1>(0h0))
when _T_986 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_983, UInt<1>(0h1), "") : assert_34
node _T_987 = not(mask)
node _T_988 = and(io.in.a.bits.mask, _T_987)
node _T_989 = eq(_T_988, UInt<1>(0h0))
node _T_990 = asUInt(reset)
node _T_991 = eq(_T_990, UInt<1>(0h0))
when _T_991 :
node _T_992 = eq(_T_989, UInt<1>(0h0))
when _T_992 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_989, UInt<1>(0h1), "") : assert_35
node _T_993 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_993 :
node _T_994 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_995 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_996 = and(_T_994, _T_995)
node _T_997 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_998 = shr(io.in.a.bits.source, 2)
node _T_999 = eq(_T_998, UInt<1>(0h0))
node _T_1000 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_1001 = and(_T_999, _T_1000)
node _T_1002 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_1003 = and(_T_1001, _T_1002)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_1004 = shr(io.in.a.bits.source, 2)
node _T_1005 = eq(_T_1004, UInt<1>(0h1))
node _T_1006 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_1007 = and(_T_1005, _T_1006)
node _T_1008 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_1009 = and(_T_1007, _T_1008)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_1010 = shr(io.in.a.bits.source, 2)
node _T_1011 = eq(_T_1010, UInt<2>(0h2))
node _T_1012 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_1013 = and(_T_1011, _T_1012)
node _T_1014 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_1015 = and(_T_1013, _T_1014)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_1016 = shr(io.in.a.bits.source, 2)
node _T_1017 = eq(_T_1016, UInt<2>(0h3))
node _T_1018 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_1019 = and(_T_1017, _T_1018)
node _T_1020 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_1021 = and(_T_1019, _T_1020)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 2, 0)
node _T_1022 = shr(io.in.a.bits.source, 3)
node _T_1023 = eq(_T_1022, UInt<3>(0h4))
node _T_1024 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_1025 = and(_T_1023, _T_1024)
node _T_1026 = leq(uncommonBits_44, UInt<3>(0h7))
node _T_1027 = and(_T_1025, _T_1026)
node _T_1028 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1029 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1030 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1031 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1032 = or(_T_997, _T_1003)
node _T_1033 = or(_T_1032, _T_1009)
node _T_1034 = or(_T_1033, _T_1015)
node _T_1035 = or(_T_1034, _T_1021)
node _T_1036 = or(_T_1035, _T_1027)
node _T_1037 = or(_T_1036, _T_1028)
node _T_1038 = or(_T_1037, _T_1029)
node _T_1039 = or(_T_1038, _T_1030)
node _T_1040 = or(_T_1039, _T_1031)
node _T_1041 = and(_T_996, _T_1040)
node _T_1042 = or(UInt<1>(0h0), _T_1041)
node _T_1043 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1044 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1045 = and(_T_1043, _T_1044)
node _T_1046 = or(UInt<1>(0h0), _T_1045)
node _T_1047 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1048 = cvt(_T_1047)
node _T_1049 = and(_T_1048, asSInt(UInt<14>(0h2000)))
node _T_1050 = asSInt(_T_1049)
node _T_1051 = eq(_T_1050, asSInt(UInt<1>(0h0)))
node _T_1052 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1053 = cvt(_T_1052)
node _T_1054 = and(_T_1053, asSInt(UInt<13>(0h1000)))
node _T_1055 = asSInt(_T_1054)
node _T_1056 = eq(_T_1055, asSInt(UInt<1>(0h0)))
node _T_1057 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1058 = cvt(_T_1057)
node _T_1059 = and(_T_1058, asSInt(UInt<18>(0h2f000)))
node _T_1060 = asSInt(_T_1059)
node _T_1061 = eq(_T_1060, asSInt(UInt<1>(0h0)))
node _T_1062 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1063 = cvt(_T_1062)
node _T_1064 = and(_T_1063, asSInt(UInt<17>(0h10000)))
node _T_1065 = asSInt(_T_1064)
node _T_1066 = eq(_T_1065, asSInt(UInt<1>(0h0)))
node _T_1067 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1068 = cvt(_T_1067)
node _T_1069 = and(_T_1068, asSInt(UInt<13>(0h1000)))
node _T_1070 = asSInt(_T_1069)
node _T_1071 = eq(_T_1070, asSInt(UInt<1>(0h0)))
node _T_1072 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1073 = cvt(_T_1072)
node _T_1074 = and(_T_1073, asSInt(UInt<27>(0h4000000)))
node _T_1075 = asSInt(_T_1074)
node _T_1076 = eq(_T_1075, asSInt(UInt<1>(0h0)))
node _T_1077 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1078 = cvt(_T_1077)
node _T_1079 = and(_T_1078, asSInt(UInt<13>(0h1000)))
node _T_1080 = asSInt(_T_1079)
node _T_1081 = eq(_T_1080, asSInt(UInt<1>(0h0)))
node _T_1082 = or(_T_1051, _T_1056)
node _T_1083 = or(_T_1082, _T_1061)
node _T_1084 = or(_T_1083, _T_1066)
node _T_1085 = or(_T_1084, _T_1071)
node _T_1086 = or(_T_1085, _T_1076)
node _T_1087 = or(_T_1086, _T_1081)
node _T_1088 = and(_T_1046, _T_1087)
node _T_1089 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1090 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1091 = cvt(_T_1090)
node _T_1092 = and(_T_1091, asSInt(UInt<17>(0h10000)))
node _T_1093 = asSInt(_T_1092)
node _T_1094 = eq(_T_1093, asSInt(UInt<1>(0h0)))
node _T_1095 = and(_T_1089, _T_1094)
node _T_1096 = or(UInt<1>(0h0), _T_1088)
node _T_1097 = or(_T_1096, _T_1095)
node _T_1098 = and(_T_1042, _T_1097)
node _T_1099 = asUInt(reset)
node _T_1100 = eq(_T_1099, UInt<1>(0h0))
when _T_1100 :
node _T_1101 = eq(_T_1098, UInt<1>(0h0))
when _T_1101 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_1098, UInt<1>(0h1), "") : assert_36
node _T_1102 = asUInt(reset)
node _T_1103 = eq(_T_1102, UInt<1>(0h0))
when _T_1103 :
node _T_1104 = eq(source_ok, UInt<1>(0h0))
when _T_1104 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_1105 = asUInt(reset)
node _T_1106 = eq(_T_1105, UInt<1>(0h0))
when _T_1106 :
node _T_1107 = eq(is_aligned, UInt<1>(0h0))
when _T_1107 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_1108 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_1109 = asUInt(reset)
node _T_1110 = eq(_T_1109, UInt<1>(0h0))
when _T_1110 :
node _T_1111 = eq(_T_1108, UInt<1>(0h0))
when _T_1111 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_1108, UInt<1>(0h1), "") : assert_39
node _T_1112 = eq(io.in.a.bits.mask, mask)
node _T_1113 = asUInt(reset)
node _T_1114 = eq(_T_1113, UInt<1>(0h0))
when _T_1114 :
node _T_1115 = eq(_T_1112, UInt<1>(0h0))
when _T_1115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_1112, UInt<1>(0h1), "") : assert_40
node _T_1116 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_1116 :
node _T_1117 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1118 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1119 = and(_T_1117, _T_1118)
node _T_1120 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_1121 = shr(io.in.a.bits.source, 2)
node _T_1122 = eq(_T_1121, UInt<1>(0h0))
node _T_1123 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_1124 = and(_T_1122, _T_1123)
node _T_1125 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_1126 = and(_T_1124, _T_1125)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0)
node _T_1127 = shr(io.in.a.bits.source, 2)
node _T_1128 = eq(_T_1127, UInt<1>(0h1))
node _T_1129 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_1130 = and(_T_1128, _T_1129)
node _T_1131 = leq(uncommonBits_46, UInt<2>(0h3))
node _T_1132 = and(_T_1130, _T_1131)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0)
node _T_1133 = shr(io.in.a.bits.source, 2)
node _T_1134 = eq(_T_1133, UInt<2>(0h2))
node _T_1135 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_1136 = and(_T_1134, _T_1135)
node _T_1137 = leq(uncommonBits_47, UInt<2>(0h3))
node _T_1138 = and(_T_1136, _T_1137)
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0)
node _T_1139 = shr(io.in.a.bits.source, 2)
node _T_1140 = eq(_T_1139, UInt<2>(0h3))
node _T_1141 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_1142 = and(_T_1140, _T_1141)
node _T_1143 = leq(uncommonBits_48, UInt<2>(0h3))
node _T_1144 = and(_T_1142, _T_1143)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 2, 0)
node _T_1145 = shr(io.in.a.bits.source, 3)
node _T_1146 = eq(_T_1145, UInt<3>(0h4))
node _T_1147 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_1148 = and(_T_1146, _T_1147)
node _T_1149 = leq(uncommonBits_49, UInt<3>(0h7))
node _T_1150 = and(_T_1148, _T_1149)
node _T_1151 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1152 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1153 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1154 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1155 = or(_T_1120, _T_1126)
node _T_1156 = or(_T_1155, _T_1132)
node _T_1157 = or(_T_1156, _T_1138)
node _T_1158 = or(_T_1157, _T_1144)
node _T_1159 = or(_T_1158, _T_1150)
node _T_1160 = or(_T_1159, _T_1151)
node _T_1161 = or(_T_1160, _T_1152)
node _T_1162 = or(_T_1161, _T_1153)
node _T_1163 = or(_T_1162, _T_1154)
node _T_1164 = and(_T_1119, _T_1163)
node _T_1165 = or(UInt<1>(0h0), _T_1164)
node _T_1166 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1167 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1168 = and(_T_1166, _T_1167)
node _T_1169 = or(UInt<1>(0h0), _T_1168)
node _T_1170 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1171 = cvt(_T_1170)
node _T_1172 = and(_T_1171, asSInt(UInt<14>(0h2000)))
node _T_1173 = asSInt(_T_1172)
node _T_1174 = eq(_T_1173, asSInt(UInt<1>(0h0)))
node _T_1175 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1176 = cvt(_T_1175)
node _T_1177 = and(_T_1176, asSInt(UInt<13>(0h1000)))
node _T_1178 = asSInt(_T_1177)
node _T_1179 = eq(_T_1178, asSInt(UInt<1>(0h0)))
node _T_1180 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1181 = cvt(_T_1180)
node _T_1182 = and(_T_1181, asSInt(UInt<18>(0h2f000)))
node _T_1183 = asSInt(_T_1182)
node _T_1184 = eq(_T_1183, asSInt(UInt<1>(0h0)))
node _T_1185 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1186 = cvt(_T_1185)
node _T_1187 = and(_T_1186, asSInt(UInt<17>(0h10000)))
node _T_1188 = asSInt(_T_1187)
node _T_1189 = eq(_T_1188, asSInt(UInt<1>(0h0)))
node _T_1190 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1191 = cvt(_T_1190)
node _T_1192 = and(_T_1191, asSInt(UInt<13>(0h1000)))
node _T_1193 = asSInt(_T_1192)
node _T_1194 = eq(_T_1193, asSInt(UInt<1>(0h0)))
node _T_1195 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1196 = cvt(_T_1195)
node _T_1197 = and(_T_1196, asSInt(UInt<27>(0h4000000)))
node _T_1198 = asSInt(_T_1197)
node _T_1199 = eq(_T_1198, asSInt(UInt<1>(0h0)))
node _T_1200 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1201 = cvt(_T_1200)
node _T_1202 = and(_T_1201, asSInt(UInt<13>(0h1000)))
node _T_1203 = asSInt(_T_1202)
node _T_1204 = eq(_T_1203, asSInt(UInt<1>(0h0)))
node _T_1205 = or(_T_1174, _T_1179)
node _T_1206 = or(_T_1205, _T_1184)
node _T_1207 = or(_T_1206, _T_1189)
node _T_1208 = or(_T_1207, _T_1194)
node _T_1209 = or(_T_1208, _T_1199)
node _T_1210 = or(_T_1209, _T_1204)
node _T_1211 = and(_T_1169, _T_1210)
node _T_1212 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1213 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1214 = cvt(_T_1213)
node _T_1215 = and(_T_1214, asSInt(UInt<17>(0h10000)))
node _T_1216 = asSInt(_T_1215)
node _T_1217 = eq(_T_1216, asSInt(UInt<1>(0h0)))
node _T_1218 = and(_T_1212, _T_1217)
node _T_1219 = or(UInt<1>(0h0), _T_1211)
node _T_1220 = or(_T_1219, _T_1218)
node _T_1221 = and(_T_1165, _T_1220)
node _T_1222 = asUInt(reset)
node _T_1223 = eq(_T_1222, UInt<1>(0h0))
when _T_1223 :
node _T_1224 = eq(_T_1221, UInt<1>(0h0))
when _T_1224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1221, UInt<1>(0h1), "") : assert_41
node _T_1225 = asUInt(reset)
node _T_1226 = eq(_T_1225, UInt<1>(0h0))
when _T_1226 :
node _T_1227 = eq(source_ok, UInt<1>(0h0))
when _T_1227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1228 = asUInt(reset)
node _T_1229 = eq(_T_1228, UInt<1>(0h0))
when _T_1229 :
node _T_1230 = eq(is_aligned, UInt<1>(0h0))
when _T_1230 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1231 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1232 = asUInt(reset)
node _T_1233 = eq(_T_1232, UInt<1>(0h0))
when _T_1233 :
node _T_1234 = eq(_T_1231, UInt<1>(0h0))
when _T_1234 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1231, UInt<1>(0h1), "") : assert_44
node _T_1235 = eq(io.in.a.bits.mask, mask)
node _T_1236 = asUInt(reset)
node _T_1237 = eq(_T_1236, UInt<1>(0h0))
when _T_1237 :
node _T_1238 = eq(_T_1235, UInt<1>(0h0))
when _T_1238 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1235, UInt<1>(0h1), "") : assert_45
node _T_1239 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1239 :
node _T_1240 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1241 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1242 = and(_T_1240, _T_1241)
node _T_1243 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_1244 = shr(io.in.a.bits.source, 2)
node _T_1245 = eq(_T_1244, UInt<1>(0h0))
node _T_1246 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_1247 = and(_T_1245, _T_1246)
node _T_1248 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_1249 = and(_T_1247, _T_1248)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_1250 = shr(io.in.a.bits.source, 2)
node _T_1251 = eq(_T_1250, UInt<1>(0h1))
node _T_1252 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_1253 = and(_T_1251, _T_1252)
node _T_1254 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_1255 = and(_T_1253, _T_1254)
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0)
node _T_1256 = shr(io.in.a.bits.source, 2)
node _T_1257 = eq(_T_1256, UInt<2>(0h2))
node _T_1258 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_1259 = and(_T_1257, _T_1258)
node _T_1260 = leq(uncommonBits_52, UInt<2>(0h3))
node _T_1261 = and(_T_1259, _T_1260)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0)
node _T_1262 = shr(io.in.a.bits.source, 2)
node _T_1263 = eq(_T_1262, UInt<2>(0h3))
node _T_1264 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_1265 = and(_T_1263, _T_1264)
node _T_1266 = leq(uncommonBits_53, UInt<2>(0h3))
node _T_1267 = and(_T_1265, _T_1266)
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0)
node _T_1268 = shr(io.in.a.bits.source, 3)
node _T_1269 = eq(_T_1268, UInt<3>(0h4))
node _T_1270 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_1271 = and(_T_1269, _T_1270)
node _T_1272 = leq(uncommonBits_54, UInt<3>(0h7))
node _T_1273 = and(_T_1271, _T_1272)
node _T_1274 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1275 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1276 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1277 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1278 = or(_T_1243, _T_1249)
node _T_1279 = or(_T_1278, _T_1255)
node _T_1280 = or(_T_1279, _T_1261)
node _T_1281 = or(_T_1280, _T_1267)
node _T_1282 = or(_T_1281, _T_1273)
node _T_1283 = or(_T_1282, _T_1274)
node _T_1284 = or(_T_1283, _T_1275)
node _T_1285 = or(_T_1284, _T_1276)
node _T_1286 = or(_T_1285, _T_1277)
node _T_1287 = and(_T_1242, _T_1286)
node _T_1288 = or(UInt<1>(0h0), _T_1287)
node _T_1289 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1290 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1291 = and(_T_1289, _T_1290)
node _T_1292 = or(UInt<1>(0h0), _T_1291)
node _T_1293 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1294 = cvt(_T_1293)
node _T_1295 = and(_T_1294, asSInt(UInt<13>(0h1000)))
node _T_1296 = asSInt(_T_1295)
node _T_1297 = eq(_T_1296, asSInt(UInt<1>(0h0)))
node _T_1298 = and(_T_1292, _T_1297)
node _T_1299 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1300 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1301 = cvt(_T_1300)
node _T_1302 = and(_T_1301, asSInt(UInt<14>(0h2000)))
node _T_1303 = asSInt(_T_1302)
node _T_1304 = eq(_T_1303, asSInt(UInt<1>(0h0)))
node _T_1305 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1306 = cvt(_T_1305)
node _T_1307 = and(_T_1306, asSInt(UInt<17>(0h10000)))
node _T_1308 = asSInt(_T_1307)
node _T_1309 = eq(_T_1308, asSInt(UInt<1>(0h0)))
node _T_1310 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1311 = cvt(_T_1310)
node _T_1312 = and(_T_1311, asSInt(UInt<18>(0h2f000)))
node _T_1313 = asSInt(_T_1312)
node _T_1314 = eq(_T_1313, asSInt(UInt<1>(0h0)))
node _T_1315 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1316 = cvt(_T_1315)
node _T_1317 = and(_T_1316, asSInt(UInt<17>(0h10000)))
node _T_1318 = asSInt(_T_1317)
node _T_1319 = eq(_T_1318, asSInt(UInt<1>(0h0)))
node _T_1320 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1321 = cvt(_T_1320)
node _T_1322 = and(_T_1321, asSInt(UInt<13>(0h1000)))
node _T_1323 = asSInt(_T_1322)
node _T_1324 = eq(_T_1323, asSInt(UInt<1>(0h0)))
node _T_1325 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1326 = cvt(_T_1325)
node _T_1327 = and(_T_1326, asSInt(UInt<27>(0h4000000)))
node _T_1328 = asSInt(_T_1327)
node _T_1329 = eq(_T_1328, asSInt(UInt<1>(0h0)))
node _T_1330 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1331 = cvt(_T_1330)
node _T_1332 = and(_T_1331, asSInt(UInt<13>(0h1000)))
node _T_1333 = asSInt(_T_1332)
node _T_1334 = eq(_T_1333, asSInt(UInt<1>(0h0)))
node _T_1335 = or(_T_1304, _T_1309)
node _T_1336 = or(_T_1335, _T_1314)
node _T_1337 = or(_T_1336, _T_1319)
node _T_1338 = or(_T_1337, _T_1324)
node _T_1339 = or(_T_1338, _T_1329)
node _T_1340 = or(_T_1339, _T_1334)
node _T_1341 = and(_T_1299, _T_1340)
node _T_1342 = or(UInt<1>(0h0), _T_1298)
node _T_1343 = or(_T_1342, _T_1341)
node _T_1344 = and(_T_1288, _T_1343)
node _T_1345 = asUInt(reset)
node _T_1346 = eq(_T_1345, UInt<1>(0h0))
when _T_1346 :
node _T_1347 = eq(_T_1344, UInt<1>(0h0))
when _T_1347 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1344, UInt<1>(0h1), "") : assert_46
node _T_1348 = asUInt(reset)
node _T_1349 = eq(_T_1348, UInt<1>(0h0))
when _T_1349 :
node _T_1350 = eq(source_ok, UInt<1>(0h0))
when _T_1350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1351 = asUInt(reset)
node _T_1352 = eq(_T_1351, UInt<1>(0h0))
when _T_1352 :
node _T_1353 = eq(is_aligned, UInt<1>(0h0))
when _T_1353 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1354 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1355 = asUInt(reset)
node _T_1356 = eq(_T_1355, UInt<1>(0h0))
when _T_1356 :
node _T_1357 = eq(_T_1354, UInt<1>(0h0))
when _T_1357 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1354, UInt<1>(0h1), "") : assert_49
node _T_1358 = eq(io.in.a.bits.mask, mask)
node _T_1359 = asUInt(reset)
node _T_1360 = eq(_T_1359, UInt<1>(0h0))
when _T_1360 :
node _T_1361 = eq(_T_1358, UInt<1>(0h0))
when _T_1361 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1358, UInt<1>(0h1), "") : assert_50
node _T_1362 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1363 = asUInt(reset)
node _T_1364 = eq(_T_1363, UInt<1>(0h0))
when _T_1364 :
node _T_1365 = eq(_T_1362, UInt<1>(0h0))
when _T_1365 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1362, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1366 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1367 = asUInt(reset)
node _T_1368 = eq(_T_1367, UInt<1>(0h0))
when _T_1368 :
node _T_1369 = eq(_T_1366, UInt<1>(0h0))
when _T_1369 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1366, UInt<1>(0h1), "") : assert_52
node _source_ok_T_43 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_44 = shr(io.in.d.bits.source, 2)
node _source_ok_T_45 = eq(_source_ok_T_44, UInt<1>(0h0))
node _source_ok_T_46 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46)
node _source_ok_T_48 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_50 = shr(io.in.d.bits.source, 2)
node _source_ok_T_51 = eq(_source_ok_T_50, UInt<1>(0h1))
node _source_ok_T_52 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_53 = and(_source_ok_T_51, _source_ok_T_52)
node _source_ok_T_54 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_55 = and(_source_ok_T_53, _source_ok_T_54)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_56 = shr(io.in.d.bits.source, 2)
node _source_ok_T_57 = eq(_source_ok_T_56, UInt<2>(0h2))
node _source_ok_T_58 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58)
node _source_ok_T_60 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_62 = shr(io.in.d.bits.source, 2)
node _source_ok_T_63 = eq(_source_ok_T_62, UInt<2>(0h3))
node _source_ok_T_64 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64)
node _source_ok_T_66 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 2, 0)
node _source_ok_T_68 = shr(io.in.d.bits.source, 3)
node _source_ok_T_69 = eq(_source_ok_T_68, UInt<3>(0h4))
node _source_ok_T_70 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70)
node _source_ok_T_72 = leq(source_ok_uncommonBits_9, UInt<3>(0h7))
node _source_ok_T_73 = and(_source_ok_T_71, _source_ok_T_72)
node _source_ok_T_74 = eq(io.in.d.bits.source, UInt<6>(0h28))
node _source_ok_T_75 = eq(io.in.d.bits.source, UInt<6>(0h29))
node _source_ok_T_76 = eq(io.in.d.bits.source, UInt<6>(0h2a))
node _source_ok_T_77 = eq(io.in.d.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE_1 : UInt<1>[10]
connect _source_ok_WIRE_1[0], _source_ok_T_43
connect _source_ok_WIRE_1[1], _source_ok_T_49
connect _source_ok_WIRE_1[2], _source_ok_T_55
connect _source_ok_WIRE_1[3], _source_ok_T_61
connect _source_ok_WIRE_1[4], _source_ok_T_67
connect _source_ok_WIRE_1[5], _source_ok_T_73
connect _source_ok_WIRE_1[6], _source_ok_T_74
connect _source_ok_WIRE_1[7], _source_ok_T_75
connect _source_ok_WIRE_1[8], _source_ok_T_76
connect _source_ok_WIRE_1[9], _source_ok_T_77
node _source_ok_T_78 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE_1[2])
node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE_1[3])
node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE_1[4])
node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE_1[5])
node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE_1[6])
node _source_ok_T_84 = or(_source_ok_T_83, _source_ok_WIRE_1[7])
node _source_ok_T_85 = or(_source_ok_T_84, _source_ok_WIRE_1[8])
node source_ok_1 = or(_source_ok_T_85, _source_ok_WIRE_1[9])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1370 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1370 :
node _T_1371 = asUInt(reset)
node _T_1372 = eq(_T_1371, UInt<1>(0h0))
when _T_1372 :
node _T_1373 = eq(source_ok_1, UInt<1>(0h0))
when _T_1373 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1374 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1375 = asUInt(reset)
node _T_1376 = eq(_T_1375, UInt<1>(0h0))
when _T_1376 :
node _T_1377 = eq(_T_1374, UInt<1>(0h0))
when _T_1377 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1374, UInt<1>(0h1), "") : assert_54
node _T_1378 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1379 = asUInt(reset)
node _T_1380 = eq(_T_1379, UInt<1>(0h0))
when _T_1380 :
node _T_1381 = eq(_T_1378, UInt<1>(0h0))
when _T_1381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1378, UInt<1>(0h1), "") : assert_55
node _T_1382 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1383 = asUInt(reset)
node _T_1384 = eq(_T_1383, UInt<1>(0h0))
when _T_1384 :
node _T_1385 = eq(_T_1382, UInt<1>(0h0))
when _T_1385 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1382, UInt<1>(0h1), "") : assert_56
node _T_1386 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1387 = asUInt(reset)
node _T_1388 = eq(_T_1387, UInt<1>(0h0))
when _T_1388 :
node _T_1389 = eq(_T_1386, UInt<1>(0h0))
when _T_1389 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1386, UInt<1>(0h1), "") : assert_57
node _T_1390 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1390 :
node _T_1391 = asUInt(reset)
node _T_1392 = eq(_T_1391, UInt<1>(0h0))
when _T_1392 :
node _T_1393 = eq(source_ok_1, UInt<1>(0h0))
when _T_1393 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1394 = asUInt(reset)
node _T_1395 = eq(_T_1394, UInt<1>(0h0))
when _T_1395 :
node _T_1396 = eq(sink_ok, UInt<1>(0h0))
when _T_1396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1397 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1398 = asUInt(reset)
node _T_1399 = eq(_T_1398, UInt<1>(0h0))
when _T_1399 :
node _T_1400 = eq(_T_1397, UInt<1>(0h0))
when _T_1400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1397, UInt<1>(0h1), "") : assert_60
node _T_1401 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1402 = asUInt(reset)
node _T_1403 = eq(_T_1402, UInt<1>(0h0))
when _T_1403 :
node _T_1404 = eq(_T_1401, UInt<1>(0h0))
when _T_1404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1401, UInt<1>(0h1), "") : assert_61
node _T_1405 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1406 = asUInt(reset)
node _T_1407 = eq(_T_1406, UInt<1>(0h0))
when _T_1407 :
node _T_1408 = eq(_T_1405, UInt<1>(0h0))
when _T_1408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1405, UInt<1>(0h1), "") : assert_62
node _T_1409 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1410 = asUInt(reset)
node _T_1411 = eq(_T_1410, UInt<1>(0h0))
when _T_1411 :
node _T_1412 = eq(_T_1409, UInt<1>(0h0))
when _T_1412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1409, UInt<1>(0h1), "") : assert_63
node _T_1413 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1414 = or(UInt<1>(0h1), _T_1413)
node _T_1415 = asUInt(reset)
node _T_1416 = eq(_T_1415, UInt<1>(0h0))
when _T_1416 :
node _T_1417 = eq(_T_1414, UInt<1>(0h0))
when _T_1417 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1414, UInt<1>(0h1), "") : assert_64
node _T_1418 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1418 :
node _T_1419 = asUInt(reset)
node _T_1420 = eq(_T_1419, UInt<1>(0h0))
when _T_1420 :
node _T_1421 = eq(source_ok_1, UInt<1>(0h0))
when _T_1421 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1422 = asUInt(reset)
node _T_1423 = eq(_T_1422, UInt<1>(0h0))
when _T_1423 :
node _T_1424 = eq(sink_ok, UInt<1>(0h0))
when _T_1424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1425 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1426 = asUInt(reset)
node _T_1427 = eq(_T_1426, UInt<1>(0h0))
when _T_1427 :
node _T_1428 = eq(_T_1425, UInt<1>(0h0))
when _T_1428 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1425, UInt<1>(0h1), "") : assert_67
node _T_1429 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1430 = asUInt(reset)
node _T_1431 = eq(_T_1430, UInt<1>(0h0))
when _T_1431 :
node _T_1432 = eq(_T_1429, UInt<1>(0h0))
when _T_1432 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1429, UInt<1>(0h1), "") : assert_68
node _T_1433 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1434 = asUInt(reset)
node _T_1435 = eq(_T_1434, UInt<1>(0h0))
when _T_1435 :
node _T_1436 = eq(_T_1433, UInt<1>(0h0))
when _T_1436 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1433, UInt<1>(0h1), "") : assert_69
node _T_1437 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1438 = or(_T_1437, io.in.d.bits.corrupt)
node _T_1439 = asUInt(reset)
node _T_1440 = eq(_T_1439, UInt<1>(0h0))
when _T_1440 :
node _T_1441 = eq(_T_1438, UInt<1>(0h0))
when _T_1441 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1438, UInt<1>(0h1), "") : assert_70
node _T_1442 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1443 = or(UInt<1>(0h1), _T_1442)
node _T_1444 = asUInt(reset)
node _T_1445 = eq(_T_1444, UInt<1>(0h0))
when _T_1445 :
node _T_1446 = eq(_T_1443, UInt<1>(0h0))
when _T_1446 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1443, UInt<1>(0h1), "") : assert_71
node _T_1447 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1447 :
node _T_1448 = asUInt(reset)
node _T_1449 = eq(_T_1448, UInt<1>(0h0))
when _T_1449 :
node _T_1450 = eq(source_ok_1, UInt<1>(0h0))
when _T_1450 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1451 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1452 = asUInt(reset)
node _T_1453 = eq(_T_1452, UInt<1>(0h0))
when _T_1453 :
node _T_1454 = eq(_T_1451, UInt<1>(0h0))
when _T_1454 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1451, UInt<1>(0h1), "") : assert_73
node _T_1455 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1456 = asUInt(reset)
node _T_1457 = eq(_T_1456, UInt<1>(0h0))
when _T_1457 :
node _T_1458 = eq(_T_1455, UInt<1>(0h0))
when _T_1458 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1455, UInt<1>(0h1), "") : assert_74
node _T_1459 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1460 = or(UInt<1>(0h1), _T_1459)
node _T_1461 = asUInt(reset)
node _T_1462 = eq(_T_1461, UInt<1>(0h0))
when _T_1462 :
node _T_1463 = eq(_T_1460, UInt<1>(0h0))
when _T_1463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1460, UInt<1>(0h1), "") : assert_75
node _T_1464 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1464 :
node _T_1465 = asUInt(reset)
node _T_1466 = eq(_T_1465, UInt<1>(0h0))
when _T_1466 :
node _T_1467 = eq(source_ok_1, UInt<1>(0h0))
when _T_1467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1468 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1469 = asUInt(reset)
node _T_1470 = eq(_T_1469, UInt<1>(0h0))
when _T_1470 :
node _T_1471 = eq(_T_1468, UInt<1>(0h0))
when _T_1471 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1468, UInt<1>(0h1), "") : assert_77
node _T_1472 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1473 = or(_T_1472, io.in.d.bits.corrupt)
node _T_1474 = asUInt(reset)
node _T_1475 = eq(_T_1474, UInt<1>(0h0))
when _T_1475 :
node _T_1476 = eq(_T_1473, UInt<1>(0h0))
when _T_1476 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1473, UInt<1>(0h1), "") : assert_78
node _T_1477 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1478 = or(UInt<1>(0h1), _T_1477)
node _T_1479 = asUInt(reset)
node _T_1480 = eq(_T_1479, UInt<1>(0h0))
when _T_1480 :
node _T_1481 = eq(_T_1478, UInt<1>(0h0))
when _T_1481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1478, UInt<1>(0h1), "") : assert_79
node _T_1482 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1482 :
node _T_1483 = asUInt(reset)
node _T_1484 = eq(_T_1483, UInt<1>(0h0))
when _T_1484 :
node _T_1485 = eq(source_ok_1, UInt<1>(0h0))
when _T_1485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1486 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1487 = asUInt(reset)
node _T_1488 = eq(_T_1487, UInt<1>(0h0))
when _T_1488 :
node _T_1489 = eq(_T_1486, UInt<1>(0h0))
when _T_1489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1486, UInt<1>(0h1), "") : assert_81
node _T_1490 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1491 = asUInt(reset)
node _T_1492 = eq(_T_1491, UInt<1>(0h0))
when _T_1492 :
node _T_1493 = eq(_T_1490, UInt<1>(0h0))
when _T_1493 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1490, UInt<1>(0h1), "") : assert_82
node _T_1494 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1495 = or(UInt<1>(0h1), _T_1494)
node _T_1496 = asUInt(reset)
node _T_1497 = eq(_T_1496, UInt<1>(0h0))
when _T_1497 :
node _T_1498 = eq(_T_1495, UInt<1>(0h0))
when _T_1498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1495, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<29>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<4>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1499 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1500 = asUInt(reset)
node _T_1501 = eq(_T_1500, UInt<1>(0h0))
when _T_1501 :
node _T_1502 = eq(_T_1499, UInt<1>(0h0))
when _T_1502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1499, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1503 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1504 = asUInt(reset)
node _T_1505 = eq(_T_1504, UInt<1>(0h0))
when _T_1505 :
node _T_1506 = eq(_T_1503, UInt<1>(0h0))
when _T_1506 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1503, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1507 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1508 = asUInt(reset)
node _T_1509 = eq(_T_1508, UInt<1>(0h0))
when _T_1509 :
node _T_1510 = eq(_T_1507, UInt<1>(0h0))
when _T_1510 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1507, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1511 = eq(a_first, UInt<1>(0h0))
node _T_1512 = and(io.in.a.valid, _T_1511)
when _T_1512 :
node _T_1513 = eq(io.in.a.bits.opcode, opcode)
node _T_1514 = asUInt(reset)
node _T_1515 = eq(_T_1514, UInt<1>(0h0))
when _T_1515 :
node _T_1516 = eq(_T_1513, UInt<1>(0h0))
when _T_1516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1513, UInt<1>(0h1), "") : assert_87
node _T_1517 = eq(io.in.a.bits.param, param)
node _T_1518 = asUInt(reset)
node _T_1519 = eq(_T_1518, UInt<1>(0h0))
when _T_1519 :
node _T_1520 = eq(_T_1517, UInt<1>(0h0))
when _T_1520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1517, UInt<1>(0h1), "") : assert_88
node _T_1521 = eq(io.in.a.bits.size, size)
node _T_1522 = asUInt(reset)
node _T_1523 = eq(_T_1522, UInt<1>(0h0))
when _T_1523 :
node _T_1524 = eq(_T_1521, UInt<1>(0h0))
when _T_1524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1521, UInt<1>(0h1), "") : assert_89
node _T_1525 = eq(io.in.a.bits.source, source)
node _T_1526 = asUInt(reset)
node _T_1527 = eq(_T_1526, UInt<1>(0h0))
when _T_1527 :
node _T_1528 = eq(_T_1525, UInt<1>(0h0))
when _T_1528 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1525, UInt<1>(0h1), "") : assert_90
node _T_1529 = eq(io.in.a.bits.address, address)
node _T_1530 = asUInt(reset)
node _T_1531 = eq(_T_1530, UInt<1>(0h0))
when _T_1531 :
node _T_1532 = eq(_T_1529, UInt<1>(0h0))
when _T_1532 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1529, UInt<1>(0h1), "") : assert_91
node _T_1533 = and(io.in.a.ready, io.in.a.valid)
node _T_1534 = and(_T_1533, a_first)
when _T_1534 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1535 = eq(d_first, UInt<1>(0h0))
node _T_1536 = and(io.in.d.valid, _T_1535)
when _T_1536 :
node _T_1537 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1538 = asUInt(reset)
node _T_1539 = eq(_T_1538, UInt<1>(0h0))
when _T_1539 :
node _T_1540 = eq(_T_1537, UInt<1>(0h0))
when _T_1540 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1537, UInt<1>(0h1), "") : assert_92
node _T_1541 = eq(io.in.d.bits.param, param_1)
node _T_1542 = asUInt(reset)
node _T_1543 = eq(_T_1542, UInt<1>(0h0))
when _T_1543 :
node _T_1544 = eq(_T_1541, UInt<1>(0h0))
when _T_1544 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1541, UInt<1>(0h1), "") : assert_93
node _T_1545 = eq(io.in.d.bits.size, size_1)
node _T_1546 = asUInt(reset)
node _T_1547 = eq(_T_1546, UInt<1>(0h0))
when _T_1547 :
node _T_1548 = eq(_T_1545, UInt<1>(0h0))
when _T_1548 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1545, UInt<1>(0h1), "") : assert_94
node _T_1549 = eq(io.in.d.bits.source, source_1)
node _T_1550 = asUInt(reset)
node _T_1551 = eq(_T_1550, UInt<1>(0h0))
when _T_1551 :
node _T_1552 = eq(_T_1549, UInt<1>(0h0))
when _T_1552 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1549, UInt<1>(0h1), "") : assert_95
node _T_1553 = eq(io.in.d.bits.sink, sink)
node _T_1554 = asUInt(reset)
node _T_1555 = eq(_T_1554, UInt<1>(0h0))
when _T_1555 :
node _T_1556 = eq(_T_1553, UInt<1>(0h0))
when _T_1556 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1553, UInt<1>(0h1), "") : assert_96
node _T_1557 = eq(io.in.d.bits.denied, denied)
node _T_1558 = asUInt(reset)
node _T_1559 = eq(_T_1558, UInt<1>(0h0))
when _T_1559 :
node _T_1560 = eq(_T_1557, UInt<1>(0h0))
when _T_1560 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1557, UInt<1>(0h1), "") : assert_97
node _T_1561 = and(io.in.d.ready, io.in.d.valid)
node _T_1562 = and(_T_1561, d_first)
when _T_1562 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes : UInt<520>, clock, reset, UInt<520>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<65>
connect a_set, UInt<65>(0h0)
wire a_set_wo_ready : UInt<65>
connect a_set_wo_ready, UInt<65>(0h0)
wire a_opcodes_set : UInt<260>
connect a_opcodes_set, UInt<260>(0h0)
wire a_sizes_set : UInt<520>
connect a_sizes_set, UInt<520>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1563 = and(io.in.a.valid, a_first_1)
node _T_1564 = and(_T_1563, UInt<1>(0h1))
when _T_1564 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1565 = and(io.in.a.ready, io.in.a.valid)
node _T_1566 = and(_T_1565, a_first_1)
node _T_1567 = and(_T_1566, UInt<1>(0h1))
when _T_1567 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1568 = dshr(inflight, io.in.a.bits.source)
node _T_1569 = bits(_T_1568, 0, 0)
node _T_1570 = eq(_T_1569, UInt<1>(0h0))
node _T_1571 = asUInt(reset)
node _T_1572 = eq(_T_1571, UInt<1>(0h0))
when _T_1572 :
node _T_1573 = eq(_T_1570, UInt<1>(0h0))
when _T_1573 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1570, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<65>
connect d_clr, UInt<65>(0h0)
wire d_clr_wo_ready : UInt<65>
connect d_clr_wo_ready, UInt<65>(0h0)
wire d_opcodes_clr : UInt<260>
connect d_opcodes_clr, UInt<260>(0h0)
wire d_sizes_clr : UInt<520>
connect d_sizes_clr, UInt<520>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1574 = and(io.in.d.valid, d_first_1)
node _T_1575 = and(_T_1574, UInt<1>(0h1))
node _T_1576 = eq(d_release_ack, UInt<1>(0h0))
node _T_1577 = and(_T_1575, _T_1576)
when _T_1577 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1578 = and(io.in.d.ready, io.in.d.valid)
node _T_1579 = and(_T_1578, d_first_1)
node _T_1580 = and(_T_1579, UInt<1>(0h1))
node _T_1581 = eq(d_release_ack, UInt<1>(0h0))
node _T_1582 = and(_T_1580, _T_1581)
when _T_1582 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1583 = and(io.in.d.valid, d_first_1)
node _T_1584 = and(_T_1583, UInt<1>(0h1))
node _T_1585 = eq(d_release_ack, UInt<1>(0h0))
node _T_1586 = and(_T_1584, _T_1585)
when _T_1586 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1587 = dshr(inflight, io.in.d.bits.source)
node _T_1588 = bits(_T_1587, 0, 0)
node _T_1589 = or(_T_1588, same_cycle_resp)
node _T_1590 = asUInt(reset)
node _T_1591 = eq(_T_1590, UInt<1>(0h0))
when _T_1591 :
node _T_1592 = eq(_T_1589, UInt<1>(0h0))
when _T_1592 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1589, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1593 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1594 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1595 = or(_T_1593, _T_1594)
node _T_1596 = asUInt(reset)
node _T_1597 = eq(_T_1596, UInt<1>(0h0))
when _T_1597 :
node _T_1598 = eq(_T_1595, UInt<1>(0h0))
when _T_1598 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1595, UInt<1>(0h1), "") : assert_100
node _T_1599 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1600 = asUInt(reset)
node _T_1601 = eq(_T_1600, UInt<1>(0h0))
when _T_1601 :
node _T_1602 = eq(_T_1599, UInt<1>(0h0))
when _T_1602 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1599, UInt<1>(0h1), "") : assert_101
else :
node _T_1603 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1604 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1605 = or(_T_1603, _T_1604)
node _T_1606 = asUInt(reset)
node _T_1607 = eq(_T_1606, UInt<1>(0h0))
when _T_1607 :
node _T_1608 = eq(_T_1605, UInt<1>(0h0))
when _T_1608 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1605, UInt<1>(0h1), "") : assert_102
node _T_1609 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1610 = asUInt(reset)
node _T_1611 = eq(_T_1610, UInt<1>(0h0))
when _T_1611 :
node _T_1612 = eq(_T_1609, UInt<1>(0h0))
when _T_1612 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1609, UInt<1>(0h1), "") : assert_103
node _T_1613 = and(io.in.d.valid, d_first_1)
node _T_1614 = and(_T_1613, a_first_1)
node _T_1615 = and(_T_1614, io.in.a.valid)
node _T_1616 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1617 = and(_T_1615, _T_1616)
node _T_1618 = eq(d_release_ack, UInt<1>(0h0))
node _T_1619 = and(_T_1617, _T_1618)
when _T_1619 :
node _T_1620 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1621 = or(_T_1620, io.in.a.ready)
node _T_1622 = asUInt(reset)
node _T_1623 = eq(_T_1622, UInt<1>(0h0))
when _T_1623 :
node _T_1624 = eq(_T_1621, UInt<1>(0h0))
when _T_1624 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1621, UInt<1>(0h1), "") : assert_104
node _T_1625 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1626 = orr(a_set_wo_ready)
node _T_1627 = eq(_T_1626, UInt<1>(0h0))
node _T_1628 = or(_T_1625, _T_1627)
node _T_1629 = asUInt(reset)
node _T_1630 = eq(_T_1629, UInt<1>(0h0))
when _T_1630 :
node _T_1631 = eq(_T_1628, UInt<1>(0h0))
when _T_1631 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1628, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_42
node _T_1632 = orr(inflight)
node _T_1633 = eq(_T_1632, UInt<1>(0h0))
node _T_1634 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1635 = or(_T_1633, _T_1634)
node _T_1636 = lt(watchdog, plusarg_reader.out)
node _T_1637 = or(_T_1635, _T_1636)
node _T_1638 = asUInt(reset)
node _T_1639 = eq(_T_1638, UInt<1>(0h0))
when _T_1639 :
node _T_1640 = eq(_T_1637, UInt<1>(0h0))
when _T_1640 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1637, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1641 = and(io.in.a.ready, io.in.a.valid)
node _T_1642 = and(io.in.d.ready, io.in.d.valid)
node _T_1643 = or(_T_1641, _T_1642)
when _T_1643 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes_1 : UInt<520>, clock, reset, UInt<520>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<29>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<65>
connect c_set, UInt<65>(0h0)
wire c_set_wo_ready : UInt<65>
connect c_set_wo_ready, UInt<65>(0h0)
wire c_opcodes_set : UInt<260>
connect c_opcodes_set, UInt<260>(0h0)
wire c_sizes_set : UInt<520>
connect c_sizes_set, UInt<520>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<29>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1644 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<29>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1645 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1646 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1647 = and(_T_1645, _T_1646)
node _T_1648 = and(_T_1644, _T_1647)
when _T_1648 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<29>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1649 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1650 = and(_T_1649, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<29>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1651 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1652 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1653 = and(_T_1651, _T_1652)
node _T_1654 = and(_T_1650, _T_1653)
when _T_1654 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<29>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1655 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1656 = bits(_T_1655, 0, 0)
node _T_1657 = eq(_T_1656, UInt<1>(0h0))
node _T_1658 = asUInt(reset)
node _T_1659 = eq(_T_1658, UInt<1>(0h0))
when _T_1659 :
node _T_1660 = eq(_T_1657, UInt<1>(0h0))
when _T_1660 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1657, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<65>
connect d_clr_1, UInt<65>(0h0)
wire d_clr_wo_ready_1 : UInt<65>
connect d_clr_wo_ready_1, UInt<65>(0h0)
wire d_opcodes_clr_1 : UInt<260>
connect d_opcodes_clr_1, UInt<260>(0h0)
wire d_sizes_clr_1 : UInt<520>
connect d_sizes_clr_1, UInt<520>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1661 = and(io.in.d.valid, d_first_2)
node _T_1662 = and(_T_1661, UInt<1>(0h1))
node _T_1663 = and(_T_1662, d_release_ack_1)
when _T_1663 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1664 = and(io.in.d.ready, io.in.d.valid)
node _T_1665 = and(_T_1664, d_first_2)
node _T_1666 = and(_T_1665, UInt<1>(0h1))
node _T_1667 = and(_T_1666, d_release_ack_1)
when _T_1667 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1668 = and(io.in.d.valid, d_first_2)
node _T_1669 = and(_T_1668, UInt<1>(0h1))
node _T_1670 = and(_T_1669, d_release_ack_1)
when _T_1670 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1671 = dshr(inflight_1, io.in.d.bits.source)
node _T_1672 = bits(_T_1671, 0, 0)
node _T_1673 = or(_T_1672, same_cycle_resp_1)
node _T_1674 = asUInt(reset)
node _T_1675 = eq(_T_1674, UInt<1>(0h0))
when _T_1675 :
node _T_1676 = eq(_T_1673, UInt<1>(0h0))
when _T_1676 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1673, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<29>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1677 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1678 = asUInt(reset)
node _T_1679 = eq(_T_1678, UInt<1>(0h0))
when _T_1679 :
node _T_1680 = eq(_T_1677, UInt<1>(0h0))
when _T_1680 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1677, UInt<1>(0h1), "") : assert_109
else :
node _T_1681 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1682 = asUInt(reset)
node _T_1683 = eq(_T_1682, UInt<1>(0h0))
when _T_1683 :
node _T_1684 = eq(_T_1681, UInt<1>(0h0))
when _T_1684 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1681, UInt<1>(0h1), "") : assert_110
node _T_1685 = and(io.in.d.valid, d_first_2)
node _T_1686 = and(_T_1685, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<29>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1687 = and(_T_1686, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<29>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1688 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1689 = and(_T_1687, _T_1688)
node _T_1690 = and(_T_1689, d_release_ack_1)
node _T_1691 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1692 = and(_T_1690, _T_1691)
when _T_1692 :
node _T_1693 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<29>(0h0)
connect _WIRE_26.bits.source, UInt<7>(0h0)
connect _WIRE_26.bits.size, UInt<4>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1694 = or(_T_1693, _WIRE_27.ready)
node _T_1695 = asUInt(reset)
node _T_1696 = eq(_T_1695, UInt<1>(0h0))
when _T_1696 :
node _T_1697 = eq(_T_1694, UInt<1>(0h0))
when _T_1697 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1694, UInt<1>(0h1), "") : assert_111
node _T_1698 = orr(c_set_wo_ready)
when _T_1698 :
node _T_1699 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1700 = asUInt(reset)
node _T_1701 = eq(_T_1700, UInt<1>(0h0))
when _T_1701 :
node _T_1702 = eq(_T_1699, UInt<1>(0h0))
when _T_1702 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1699, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_43
node _T_1703 = orr(inflight_1)
node _T_1704 = eq(_T_1703, UInt<1>(0h0))
node _T_1705 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1706 = or(_T_1704, _T_1705)
node _T_1707 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1708 = or(_T_1706, _T_1707)
node _T_1709 = asUInt(reset)
node _T_1710 = eq(_T_1709, UInt<1>(0h0))
when _T_1710 :
node _T_1711 = eq(_T_1708, UInt<1>(0h0))
when _T_1711 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1708, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<29>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<4>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1712 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1713 = and(io.in.d.ready, io.in.d.valid)
node _T_1714 = or(_T_1712, _T_1713)
when _T_1714 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_21( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_48 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_54 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_70 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_72 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [519:0] c_sizes_set = 520'h0; // @[Monitor.scala:741:34]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_25 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_26 = _source_ok_T_25 == 4'h4; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31]
wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h29; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31]
wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_33; // @[Parameters.scala:1138:31]
wire _source_ok_T_34 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_34; // @[Parameters.scala:1138:31]
wire _source_ok_T_35 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_39 = _source_ok_T_38 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_41 = _source_ok_T_40 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_42 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_9 = _uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_14 = _uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_24 = _uncommonBits_T_24[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_44 = _uncommonBits_T_44[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_49 = _uncommonBits_T_49[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_43 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_43; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_44 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_50 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_56 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_62 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_45 = _source_ok_T_44 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_49 = _source_ok_T_47; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_49; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_51 = _source_ok_T_50 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_55 = _source_ok_T_53; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_55; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_57 = _source_ok_T_56 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_61; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_63 = _source_ok_T_62 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_67; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_68 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_69 = _source_ok_T_68 == 4'h4; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_71 = _source_ok_T_69; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_73 = _source_ok_T_71; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_5 = _source_ok_T_73; // @[Parameters.scala:1138:31]
wire _source_ok_T_74 = io_in_d_bits_source_0 == 7'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_74; // @[Parameters.scala:1138:31]
wire _source_ok_T_75 = io_in_d_bits_source_0 == 7'h29; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_75; // @[Parameters.scala:1138:31]
wire _source_ok_T_76 = io_in_d_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_76; // @[Parameters.scala:1138:31]
wire _source_ok_T_77 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_77; // @[Parameters.scala:1138:31]
wire _source_ok_T_78 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_79 = _source_ok_T_78 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_80 = _source_ok_T_79 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_81 = _source_ok_T_80 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_82 = _source_ok_T_81 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_83 = _source_ok_T_82 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_84 = _source_ok_T_83 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_85 = _source_ok_T_84 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_85 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1641 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1641; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1641; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_1714 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1714; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1714; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1714; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [519:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [519:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [519:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [519:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [519:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[519:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1567 = _T_1641 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1567 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1567 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1567 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1567 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1567 ? _a_sizes_set_T_1[519:0] : 520'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [519:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1613 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1613 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1582 = _T_1714 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1582 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1582 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1582 ? _d_sizes_clr_T_5[519:0] : 520'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [519:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [519:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [519:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [519:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [519:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [519:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [519:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[519:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [519:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1685 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1685 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1667 = _T_1714 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1667 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1667 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1667 ? _d_sizes_clr_T_11[519:0] : 520'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [519:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [519:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module Frontend :
input clock : Clock
input reset : Reset
output auto : { icache_master_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<7>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}, flip reset_vector_sink_in : UInt<32>}
output io : { flip cpu : { might_request : UInt<1>, flip clock_enabled : UInt<1>, req : { valid : UInt<1>, bits : { pc : UInt<40>, speculative : UInt<1>}}, sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { btb : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, replay : UInt<1>}}, flip gpa : { valid : UInt<1>, bits : UInt<40>}, flip gpa_is_pte : UInt<1>, btb_update : { valid : UInt<1>, bits : { prediction : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isValid : UInt<1>, br_pc : UInt<39>, cfiType : UInt<2>}}, bht_update : { valid : UInt<1>, bits : { prediction : { history : UInt<8>, value : UInt<1>}, pc : UInt<39>, branch : UInt<1>, taken : UInt<1>, mispredict : UInt<1>}}, ras_update : { valid : UInt<1>, bits : { cfiType : UInt<2>, returnAddr : UInt<39>}}, flush_icache : UInt<1>, flip npc : UInt<40>, flip perf : { acquire : UInt<1>, tlbMiss : UInt<1>}, progress : UInt<1>}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, errors : { bus : { valid : UInt<1>, bits : UInt<32>}}}
inst icache of ICache
connect icache.clock, clock
connect icache.reset, reset
wire resetVectorSinkNodeIn : UInt<32>
invalidate resetVectorSinkNodeIn
connect resetVectorSinkNodeIn, auto.reset_vector_sink_in
connect icache.auto.master_out.d, auto.icache_master_out.d
connect auto.icache_master_out.a.bits, icache.auto.master_out.a.bits
connect auto.icache_master_out.a.valid, icache.auto.master_out.a.valid
connect icache.auto.master_out.a.ready, auto.icache_master_out.a.ready
node _T = asUInt(reset)
node _T_1 = or(_T, io.cpu.req.valid)
inst fq of ShiftQueue
connect fq.clock, clock
connect fq.reset, _T_1
reg clock_en_reg : UInt<1>, clock
node clock_en = or(clock_en_reg, io.cpu.might_request)
connect io.cpu.clock_enabled, clock_en
node _T_2 = or(io.cpu.req.valid, io.cpu.sfence.valid)
node _T_3 = or(_T_2, io.cpu.flush_icache)
node _T_4 = or(_T_3, io.cpu.bht_update.valid)
node _T_5 = or(_T_4, io.cpu.btb_update.valid)
node _T_6 = eq(_T_5, UInt<1>(0h0))
node _T_7 = or(_T_6, io.cpu.might_request)
node _T_8 = asUInt(reset)
node _T_9 = eq(_T_8, UInt<1>(0h0))
when _T_9 :
node _T_10 = eq(_T_7, UInt<1>(0h0))
when _T_10 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Frontend.scala:96 assert(!(io.cpu.req.valid || io.cpu.sfence.valid || io.cpu.flush_icache || io.cpu.bht_update.valid || io.cpu.btb_update.valid) || io.cpu.might_request)\n") : printf
assert(clock, _T_7, UInt<1>(0h1), "") : assert
connect icache.clock, clock
connect icache.io.clock_enabled, clock_en
inst tlb of ITLB
connect tlb.clock, clock
connect tlb.reset, reset
reg s1_valid : UInt<1>, clock
regreset s2_valid : UInt<1>, clock, reset, UInt<1>(0h0)
node _s0_fq_has_space_T = bits(fq.io.mask, 2, 2)
node _s0_fq_has_space_T_1 = eq(_s0_fq_has_space_T, UInt<1>(0h0))
node _s0_fq_has_space_T_2 = bits(fq.io.mask, 3, 3)
node _s0_fq_has_space_T_3 = eq(_s0_fq_has_space_T_2, UInt<1>(0h0))
node _s0_fq_has_space_T_4 = eq(s1_valid, UInt<1>(0h0))
node _s0_fq_has_space_T_5 = eq(s2_valid, UInt<1>(0h0))
node _s0_fq_has_space_T_6 = or(_s0_fq_has_space_T_4, _s0_fq_has_space_T_5)
node _s0_fq_has_space_T_7 = and(_s0_fq_has_space_T_3, _s0_fq_has_space_T_6)
node _s0_fq_has_space_T_8 = or(_s0_fq_has_space_T_1, _s0_fq_has_space_T_7)
node _s0_fq_has_space_T_9 = bits(fq.io.mask, 4, 4)
node _s0_fq_has_space_T_10 = eq(_s0_fq_has_space_T_9, UInt<1>(0h0))
node _s0_fq_has_space_T_11 = eq(s1_valid, UInt<1>(0h0))
node _s0_fq_has_space_T_12 = eq(s2_valid, UInt<1>(0h0))
node _s0_fq_has_space_T_13 = and(_s0_fq_has_space_T_11, _s0_fq_has_space_T_12)
node _s0_fq_has_space_T_14 = and(_s0_fq_has_space_T_10, _s0_fq_has_space_T_13)
node s0_fq_has_space = or(_s0_fq_has_space_T_8, _s0_fq_has_space_T_14)
node s0_valid = or(io.cpu.req.valid, s0_fq_has_space)
connect s1_valid, s0_valid
reg s1_pc : UInt<40>, clock
reg s1_speculative : UInt<1>, clock
node _s2_pc_T = not(resetVectorSinkNodeIn)
node _s2_pc_T_1 = or(_s2_pc_T, UInt<1>(0h1))
node _s2_pc_T_2 = not(_s2_pc_T_1)
regreset s2_pc : UInt<40>, clock, reset, _s2_pc_T_2
reg s2_btb_resp_valid : UInt<1>, clock
reg s2_btb_resp_bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, clock
node s2_btb_taken = and(s2_btb_resp_valid, s2_btb_resp_bits.taken)
reg s2_tlb_resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, clock
node _s2_xcpt_T = or(s2_tlb_resp.ae.inst, s2_tlb_resp.pf.inst)
node s2_xcpt = or(_s2_xcpt_T, s2_tlb_resp.gf.inst)
regreset s2_speculative : UInt<1>, clock, reset, UInt<1>(0h0)
regreset s2_partial_insn_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg s2_partial_insn : UInt<16>, clock
regreset wrong_path : UInt<1>, clock, reset, UInt<1>(0h0)
node _s1_base_pc_T = not(s1_pc)
node _s1_base_pc_T_1 = or(_s1_base_pc_T, UInt<2>(0h3))
node s1_base_pc = not(_s1_base_pc_T_1)
node _ntpc_T = add(s1_base_pc, UInt<3>(0h4))
node ntpc = tail(_ntpc_T, 1)
wire predicted_npc : UInt
connect predicted_npc, ntpc
wire predicted_taken : UInt<1>
connect predicted_taken, UInt<1>(0h0)
wire s2_replay : UInt<1>
node _s2_replay_T = and(fq.io.enq.ready, fq.io.enq.valid)
node _s2_replay_T_1 = eq(_s2_replay_T, UInt<1>(0h0))
node _s2_replay_T_2 = and(s2_valid, _s2_replay_T_1)
node _s2_replay_T_3 = eq(s0_valid, UInt<1>(0h0))
node _s2_replay_T_4 = and(s2_replay, _s2_replay_T_3)
regreset s2_replay_REG : UInt<1>, clock, reset, UInt<1>(0h1)
connect s2_replay_REG, _s2_replay_T_4
node _s2_replay_T_5 = or(_s2_replay_T_2, s2_replay_REG)
connect s2_replay, _s2_replay_T_5
node npc = mux(s2_replay, s2_pc, predicted_npc)
connect s1_pc, io.cpu.npc
node _s0_speculative_T = eq(s2_speculative, UInt<1>(0h0))
node _s0_speculative_T_1 = and(s2_valid, _s0_speculative_T)
node _s0_speculative_T_2 = or(s1_speculative, _s0_speculative_T_1)
node s0_speculative = or(_s0_speculative_T_2, predicted_taken)
node _s1_speculative_T = mux(s2_replay, s2_speculative, s0_speculative)
node _s1_speculative_T_1 = mux(io.cpu.req.valid, io.cpu.req.bits.speculative, _s1_speculative_T)
connect s1_speculative, _s1_speculative_T_1
wire s2_redirect : UInt<1>
connect s2_redirect, io.cpu.req.valid
connect s2_valid, UInt<1>(0h0)
node _T_11 = eq(s2_replay, UInt<1>(0h0))
when _T_11 :
node _s2_valid_T = eq(s2_redirect, UInt<1>(0h0))
connect s2_valid, _s2_valid_T
connect s2_pc, s1_pc
connect s2_speculative, s1_speculative
connect s2_tlb_resp, tlb.io.resp
regreset recent_progress_counter : UInt, clock, reset, UInt<2>(0h3)
node recent_progress = gt(recent_progress_counter, UInt<1>(0h0))
node _T_12 = and(io.ptw.req.ready, io.ptw.req.valid)
node _T_13 = and(_T_12, recent_progress)
when _T_13 :
node _recent_progress_counter_T = sub(recent_progress_counter, UInt<1>(0h1))
node _recent_progress_counter_T_1 = tail(_recent_progress_counter_T, 1)
connect recent_progress_counter, _recent_progress_counter_T_1
when io.cpu.progress :
connect recent_progress_counter, UInt<2>(0h3)
node _s2_kill_speculative_tlb_refill_T = eq(recent_progress, UInt<1>(0h0))
node s2_kill_speculative_tlb_refill = and(s2_speculative, _s2_kill_speculative_tlb_refill_T)
connect tlb.io.ptw.customCSRs, io.ptw.customCSRs
connect tlb.io.ptw.pmp[0], io.ptw.pmp[0]
connect tlb.io.ptw.pmp[1], io.ptw.pmp[1]
connect tlb.io.ptw.pmp[2], io.ptw.pmp[2]
connect tlb.io.ptw.pmp[3], io.ptw.pmp[3]
connect tlb.io.ptw.pmp[4], io.ptw.pmp[4]
connect tlb.io.ptw.pmp[5], io.ptw.pmp[5]
connect tlb.io.ptw.pmp[6], io.ptw.pmp[6]
connect tlb.io.ptw.pmp[7], io.ptw.pmp[7]
connect tlb.io.ptw.gstatus, io.ptw.gstatus
connect tlb.io.ptw.hstatus, io.ptw.hstatus
connect tlb.io.ptw.status, io.ptw.status
connect tlb.io.ptw.vsatp, io.ptw.vsatp
connect tlb.io.ptw.hgatp, io.ptw.hgatp
connect tlb.io.ptw.ptbr, io.ptw.ptbr
connect tlb.io.ptw.resp, io.ptw.resp
connect io.ptw.req.bits, tlb.io.ptw.req.bits
connect io.ptw.req.valid, tlb.io.ptw.req.valid
connect tlb.io.ptw.req.ready, io.ptw.req.ready
node _tlb_io_req_valid_T = eq(s2_replay, UInt<1>(0h0))
node _tlb_io_req_valid_T_1 = and(s1_valid, _tlb_io_req_valid_T)
connect tlb.io.req.valid, _tlb_io_req_valid_T_1
connect tlb.io.req.bits.cmd, UInt<1>(0h0)
connect tlb.io.req.bits.vaddr, s1_pc
connect tlb.io.req.bits.passthrough, UInt<1>(0h0)
connect tlb.io.req.bits.size, UInt<2>(0h2)
connect tlb.io.req.bits.prv, io.ptw.status.prv
connect tlb.io.req.bits.v, io.ptw.status.v
connect tlb.io.sfence.bits.hg, io.cpu.sfence.bits.hg
connect tlb.io.sfence.bits.hv, io.cpu.sfence.bits.hv
connect tlb.io.sfence.bits.asid, io.cpu.sfence.bits.asid
connect tlb.io.sfence.bits.addr, io.cpu.sfence.bits.addr
connect tlb.io.sfence.bits.rs2, io.cpu.sfence.bits.rs2
connect tlb.io.sfence.bits.rs1, io.cpu.sfence.bits.rs1
connect tlb.io.sfence.valid, io.cpu.sfence.valid
node _tlb_io_kill_T = eq(s2_valid, UInt<1>(0h0))
node _tlb_io_kill_T_1 = or(_tlb_io_kill_T, s2_kill_speculative_tlb_refill)
connect tlb.io.kill, _tlb_io_kill_T_1
connect icache.io.req.valid, s0_valid
connect icache.io.req.bits.addr, io.cpu.npc
connect icache.io.invalidate, io.cpu.flush_icache
connect icache.io.s1_paddr, tlb.io.resp.paddr
connect icache.io.s2_vaddr, s2_pc
node _icache_io_s1_kill_T = or(s2_redirect, tlb.io.resp.miss)
node _icache_io_s1_kill_T_1 = or(_icache_io_s1_kill_T, s2_replay)
connect icache.io.s1_kill, _icache_io_s1_kill_T_1
node _s2_can_speculatively_refill_T = bits(io.ptw.customCSRs.csrs[0].value, 3, 3)
node _s2_can_speculatively_refill_T_1 = eq(_s2_can_speculatively_refill_T, UInt<1>(0h0))
node s2_can_speculatively_refill = and(s2_tlb_resp.cacheable, _s2_can_speculatively_refill_T_1)
node _icache_io_s2_kill_T = eq(s2_can_speculatively_refill, UInt<1>(0h0))
node _icache_io_s2_kill_T_1 = and(s2_speculative, _icache_io_s2_kill_T)
node _icache_io_s2_kill_T_2 = or(_icache_io_s2_kill_T_1, s2_xcpt)
connect icache.io.s2_kill, _icache_io_s2_kill_T_2
connect icache.io.s2_cacheable, s2_tlb_resp.cacheable
node _icache_io_s2_prefetch_T = bits(io.ptw.customCSRs.csrs[0].value, 17, 17)
node _icache_io_s2_prefetch_T_1 = eq(_icache_io_s2_prefetch_T, UInt<1>(0h0))
node _icache_io_s2_prefetch_T_2 = and(s2_tlb_resp.prefetchable, _icache_io_s2_prefetch_T_1)
connect icache.io.s2_prefetch, _icache_io_s2_prefetch_T_2
reg fq_io_enq_valid_REG : UInt<1>, clock
connect fq_io_enq_valid_REG, s1_valid
node _fq_io_enq_valid_T = and(fq_io_enq_valid_REG, s2_valid)
node _fq_io_enq_valid_T_1 = and(s2_kill_speculative_tlb_refill, s2_tlb_resp.miss)
node _fq_io_enq_valid_T_2 = or(icache.io.resp.valid, _fq_io_enq_valid_T_1)
node _fq_io_enq_valid_T_3 = eq(s2_tlb_resp.miss, UInt<1>(0h0))
node _fq_io_enq_valid_T_4 = and(_fq_io_enq_valid_T_3, icache.io.s2_kill)
node _fq_io_enq_valid_T_5 = or(_fq_io_enq_valid_T_2, _fq_io_enq_valid_T_4)
node _fq_io_enq_valid_T_6 = and(_fq_io_enq_valid_T, _fq_io_enq_valid_T_5)
connect fq.io.enq.valid, _fq_io_enq_valid_T_6
connect fq.io.enq.bits.pc, s2_pc
node _io_cpu_npc_T = mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc)
node _io_cpu_npc_T_1 = not(_io_cpu_npc_T)
node _io_cpu_npc_T_2 = or(_io_cpu_npc_T_1, UInt<1>(0h1))
node _io_cpu_npc_T_3 = not(_io_cpu_npc_T_2)
connect io.cpu.npc, _io_cpu_npc_T_3
connect fq.io.enq.bits.data, icache.io.resp.bits.data
node _fq_io_enq_bits_mask_T = bits(s2_pc, 1, 1)
node _fq_io_enq_bits_mask_T_1 = dshl(UInt<2>(0h3), _fq_io_enq_bits_mask_T)
connect fq.io.enq.bits.mask, _fq_io_enq_bits_mask_T_1
node _fq_io_enq_bits_replay_T = eq(icache.io.resp.valid, UInt<1>(0h0))
node _fq_io_enq_bits_replay_T_1 = and(icache.io.s2_kill, _fq_io_enq_bits_replay_T)
node _fq_io_enq_bits_replay_T_2 = eq(s2_xcpt, UInt<1>(0h0))
node _fq_io_enq_bits_replay_T_3 = and(_fq_io_enq_bits_replay_T_1, _fq_io_enq_bits_replay_T_2)
node _fq_io_enq_bits_replay_T_4 = or(icache.io.resp.bits.replay, _fq_io_enq_bits_replay_T_3)
node _fq_io_enq_bits_replay_T_5 = and(s2_kill_speculative_tlb_refill, s2_tlb_resp.miss)
node _fq_io_enq_bits_replay_T_6 = or(_fq_io_enq_bits_replay_T_4, _fq_io_enq_bits_replay_T_5)
connect fq.io.enq.bits.replay, _fq_io_enq_bits_replay_T_6
connect fq.io.enq.bits.btb.bht.value, s2_btb_resp_bits.bht.value
connect fq.io.enq.bits.btb.bht.history, s2_btb_resp_bits.bht.history
connect fq.io.enq.bits.btb.entry, s2_btb_resp_bits.entry
connect fq.io.enq.bits.btb.target, s2_btb_resp_bits.target
connect fq.io.enq.bits.btb.bridx, s2_btb_resp_bits.bridx
connect fq.io.enq.bits.btb.mask, s2_btb_resp_bits.mask
connect fq.io.enq.bits.btb.taken, s2_btb_resp_bits.taken
connect fq.io.enq.bits.btb.cfiType, s2_btb_resp_bits.cfiType
connect fq.io.enq.bits.btb.taken, s2_btb_taken
connect fq.io.enq.bits.xcpt.ae.inst, s2_tlb_resp.ae.inst
connect fq.io.enq.bits.xcpt.gf.inst, s2_tlb_resp.gf.inst
connect fq.io.enq.bits.xcpt.pf.inst, s2_tlb_resp.pf.inst
node _T_14 = bits(io.ptw.customCSRs.csrs[0].value, 3, 3)
node _T_15 = and(s2_speculative, _T_14)
node _T_16 = eq(icache.io.s2_kill, UInt<1>(0h0))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = asUInt(reset)
node _T_20 = eq(_T_19, UInt<1>(0h0))
when _T_20 :
node _T_21 = eq(_T_18, UInt<1>(0h0))
when _T_21 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Frontend.scala:194 assert(!(s2_speculative && io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableSpeculativeICacheRefill && !icache.io.s2_kill))\n") : printf_1
assert(clock, _T_18, UInt<1>(0h1), "") : assert_1
node _T_22 = and(icache.io.resp.valid, icache.io.resp.bits.ae)
when _T_22 :
connect fq.io.enq.bits.xcpt.ae.inst, UInt<1>(0h1)
inst btb of BTB
connect btb.clock, clock
connect btb.reset, reset
connect btb.io.flush, UInt<1>(0h0)
connect btb.io.req.valid, UInt<1>(0h0)
connect btb.io.req.bits.addr, s1_pc
connect btb.io.btb_update.bits.cfiType, io.cpu.btb_update.bits.cfiType
connect btb.io.btb_update.bits.br_pc, io.cpu.btb_update.bits.br_pc
connect btb.io.btb_update.bits.isValid, io.cpu.btb_update.bits.isValid
connect btb.io.btb_update.bits.taken, io.cpu.btb_update.bits.taken
connect btb.io.btb_update.bits.target, io.cpu.btb_update.bits.target
connect btb.io.btb_update.bits.pc, io.cpu.btb_update.bits.pc
connect btb.io.btb_update.bits.prediction.bht.value, io.cpu.btb_update.bits.prediction.bht.value
connect btb.io.btb_update.bits.prediction.bht.history, io.cpu.btb_update.bits.prediction.bht.history
connect btb.io.btb_update.bits.prediction.entry, io.cpu.btb_update.bits.prediction.entry
connect btb.io.btb_update.bits.prediction.target, io.cpu.btb_update.bits.prediction.target
connect btb.io.btb_update.bits.prediction.bridx, io.cpu.btb_update.bits.prediction.bridx
connect btb.io.btb_update.bits.prediction.mask, io.cpu.btb_update.bits.prediction.mask
connect btb.io.btb_update.bits.prediction.taken, io.cpu.btb_update.bits.prediction.taken
connect btb.io.btb_update.bits.prediction.cfiType, io.cpu.btb_update.bits.prediction.cfiType
connect btb.io.btb_update.valid, io.cpu.btb_update.valid
connect btb.io.bht_update.bits.mispredict, io.cpu.bht_update.bits.mispredict
connect btb.io.bht_update.bits.taken, io.cpu.bht_update.bits.taken
connect btb.io.bht_update.bits.branch, io.cpu.bht_update.bits.branch
connect btb.io.bht_update.bits.pc, io.cpu.bht_update.bits.pc
connect btb.io.bht_update.bits.prediction.value, io.cpu.bht_update.bits.prediction.value
connect btb.io.bht_update.bits.prediction.history, io.cpu.bht_update.bits.prediction.history
connect btb.io.bht_update.valid, io.cpu.bht_update.valid
connect btb.io.ras_update.valid, UInt<1>(0h0)
invalidate btb.io.ras_update.bits.returnAddr
invalidate btb.io.ras_update.bits.cfiType
connect btb.io.bht_advance.valid, UInt<1>(0h0)
invalidate btb.io.bht_advance.bits.bht.value
invalidate btb.io.bht_advance.bits.bht.history
invalidate btb.io.bht_advance.bits.entry
invalidate btb.io.bht_advance.bits.target
invalidate btb.io.bht_advance.bits.bridx
invalidate btb.io.bht_advance.bits.mask
invalidate btb.io.bht_advance.bits.taken
invalidate btb.io.bht_advance.bits.cfiType
node _T_23 = eq(s2_replay, UInt<1>(0h0))
when _T_23 :
node _btb_io_req_valid_T = eq(s2_redirect, UInt<1>(0h0))
connect btb.io.req.valid, _btb_io_req_valid_T
connect s2_btb_resp_valid, btb.io.resp.valid
connect s2_btb_resp_bits, btb.io.resp.bits
node _T_24 = and(btb.io.resp.valid, btb.io.resp.bits.taken)
when _T_24 :
node _predicted_npc_T = bits(btb.io.resp.bits.target, 38, 38)
node _predicted_npc_T_1 = cat(_predicted_npc_T, btb.io.resp.bits.target)
connect predicted_npc, _predicted_npc_T_1
connect predicted_taken, UInt<1>(0h1)
when UInt<1>(0h0) :
connect btb.io.flush, UInt<1>(0h1)
when UInt<1>(0h0) :
connect btb.io.bht_update.valid, UInt<1>(0h0)
node _s2_base_pc_T = not(s2_pc)
node _s2_base_pc_T_1 = or(_s2_base_pc_T, UInt<2>(0h3))
node s2_base_pc = not(_s2_base_pc_T_1)
wire taken_idx : UInt
wire after_idx : UInt
wire useRAS : UInt<1>
connect useRAS, UInt<1>(0h0)
wire updateBTB : UInt<1>
connect updateBTB, UInt<1>(0h0)
invalidate taken_idx
invalidate after_idx
node _T_25 = eq(io.cpu.btb_update.valid, UInt<1>(0h0))
when _T_25 :
node _fetch_bubble_likely_T = bits(fq.io.mask, 1, 1)
node fetch_bubble_likely = eq(_fetch_bubble_likely_T, UInt<1>(0h0))
node _btb_io_btb_update_valid_T = and(fq.io.enq.ready, fq.io.enq.valid)
node _btb_io_btb_update_valid_T_1 = eq(wrong_path, UInt<1>(0h0))
node _btb_io_btb_update_valid_T_2 = and(_btb_io_btb_update_valid_T, _btb_io_btb_update_valid_T_1)
node _btb_io_btb_update_valid_T_3 = and(_btb_io_btb_update_valid_T_2, fetch_bubble_likely)
node _btb_io_btb_update_valid_T_4 = and(_btb_io_btb_update_valid_T_3, updateBTB)
connect btb.io.btb_update.valid, _btb_io_btb_update_valid_T_4
connect btb.io.btb_update.bits.prediction.entry, UInt<5>(0h1c)
connect btb.io.btb_update.bits.isValid, UInt<1>(0h1)
connect btb.io.btb_update.bits.cfiType, btb.io.ras_update.bits.cfiType
node _btb_io_btb_update_bits_br_pc_T = shl(taken_idx, 1)
node _btb_io_btb_update_bits_br_pc_T_1 = or(s2_base_pc, _btb_io_btb_update_bits_br_pc_T)
connect btb.io.btb_update.bits.br_pc, _btb_io_btb_update_bits_br_pc_T_1
connect btb.io.btb_update.bits.pc, s2_base_pc
node _btb_io_ras_update_bits_returnAddr_T = shl(after_idx, 1)
node _btb_io_ras_update_bits_returnAddr_T_1 = add(s2_base_pc, _btb_io_ras_update_bits_returnAddr_T)
node _btb_io_ras_update_bits_returnAddr_T_2 = tail(_btb_io_ras_update_bits_returnAddr_T_1, 1)
connect btb.io.ras_update.bits.returnAddr, _btb_io_ras_update_bits_returnAddr_T_2
node _taken_prevRVI_T = bits(s2_partial_insn, 1, 0)
node _taken_prevRVI_T_1 = neq(_taken_prevRVI_T, UInt<2>(0h3))
node _taken_prevRVI_T_2 = eq(_taken_prevRVI_T_1, UInt<1>(0h0))
node taken_prevRVI = and(s2_partial_insn_valid, _taken_prevRVI_T_2)
node _taken_valid_T = bits(fq.io.enq.bits.mask, 0, 0)
node _taken_valid_T_1 = eq(taken_prevRVI, UInt<1>(0h0))
node taken_valid = and(_taken_valid_T, _taken_valid_T_1)
node taken_bits = bits(fq.io.enq.bits.data, 15, 0)
node _taken_rvc_T = bits(taken_bits, 1, 0)
node taken_rvc = neq(_taken_rvc_T, UInt<2>(0h3))
node taken_rviBits = cat(taken_bits, s2_partial_insn)
node _taken_rviBranch_T = bits(taken_rviBits, 6, 0)
node taken_rviBranch = eq(_taken_rviBranch_T, UInt<7>(0h63))
node _taken_rviJump_T = bits(taken_rviBits, 6, 0)
node taken_rviJump = eq(_taken_rviJump_T, UInt<7>(0h6f))
node _taken_rviJALR_T = bits(taken_rviBits, 6, 0)
node taken_rviJALR = eq(_taken_rviJALR_T, UInt<7>(0h67))
node _taken_rviReturn_T = bits(taken_rviBits, 7, 7)
node _taken_rviReturn_T_1 = eq(_taken_rviReturn_T, UInt<1>(0h0))
node _taken_rviReturn_T_2 = and(taken_rviJALR, _taken_rviReturn_T_1)
node _taken_rviReturn_T_3 = bits(taken_rviBits, 19, 15)
node _taken_rviReturn_T_4 = and(_taken_rviReturn_T_3, UInt<5>(0h1b))
node _taken_rviReturn_T_5 = eq(UInt<1>(0h1), _taken_rviReturn_T_4)
node taken_rviReturn = and(_taken_rviReturn_T_2, _taken_rviReturn_T_5)
node _taken_rviCall_T = or(taken_rviJALR, taken_rviJump)
node _taken_rviCall_T_1 = bits(taken_rviBits, 7, 7)
node taken_rviCall = and(_taken_rviCall_T, _taken_rviCall_T_1)
node _taken_rvcBranch_T = and(taken_bits, UInt<16>(0he003))
node _taken_rvcBranch_T_1 = eq(UInt<16>(0hc001), _taken_rvcBranch_T)
node _taken_rvcBranch_T_2 = and(taken_bits, UInt<16>(0he003))
node _taken_rvcBranch_T_3 = eq(UInt<16>(0he001), _taken_rvcBranch_T_2)
node taken_rvcBranch = or(_taken_rvcBranch_T_1, _taken_rvcBranch_T_3)
node _taken_rvcJAL_T = and(taken_bits, UInt<16>(0he003))
node _taken_rvcJAL_T_1 = eq(UInt<14>(0h2001), _taken_rvcJAL_T)
node taken_rvcJAL = and(UInt<1>(0h0), _taken_rvcJAL_T_1)
node _taken_rvcJump_T = and(taken_bits, UInt<16>(0he003))
node _taken_rvcJump_T_1 = eq(UInt<16>(0ha001), _taken_rvcJump_T)
node taken_rvcJump = or(_taken_rvcJump_T_1, taken_rvcJAL)
node _taken_rvcImm_T = bits(taken_bits, 14, 14)
node _taken_rvcImm_T_1 = bits(taken_bits, 12, 12)
node _taken_rvcImm_T_2 = mux(_taken_rvcImm_T_1, UInt<5>(0h1f), UInt<5>(0h0))
node _taken_rvcImm_T_3 = bits(taken_bits, 6, 5)
node _taken_rvcImm_T_4 = bits(taken_bits, 2, 2)
node _taken_rvcImm_T_5 = bits(taken_bits, 11, 10)
node _taken_rvcImm_T_6 = bits(taken_bits, 4, 3)
node taken_rvcImm_lo_hi = cat(_taken_rvcImm_T_5, _taken_rvcImm_T_6)
node taken_rvcImm_lo = cat(taken_rvcImm_lo_hi, UInt<1>(0h0))
node taken_rvcImm_hi_hi = cat(_taken_rvcImm_T_2, _taken_rvcImm_T_3)
node taken_rvcImm_hi = cat(taken_rvcImm_hi_hi, _taken_rvcImm_T_4)
node _taken_rvcImm_T_7 = cat(taken_rvcImm_hi, taken_rvcImm_lo)
node _taken_rvcImm_T_8 = asSInt(_taken_rvcImm_T_7)
node _taken_rvcImm_T_9 = bits(taken_bits, 12, 12)
node _taken_rvcImm_T_10 = mux(_taken_rvcImm_T_9, UInt<10>(0h3ff), UInt<10>(0h0))
node _taken_rvcImm_T_11 = bits(taken_bits, 8, 8)
node _taken_rvcImm_T_12 = bits(taken_bits, 10, 9)
node _taken_rvcImm_T_13 = bits(taken_bits, 6, 6)
node _taken_rvcImm_T_14 = bits(taken_bits, 7, 7)
node _taken_rvcImm_T_15 = bits(taken_bits, 2, 2)
node _taken_rvcImm_T_16 = bits(taken_bits, 11, 11)
node _taken_rvcImm_T_17 = bits(taken_bits, 5, 3)
node taken_rvcImm_lo_lo = cat(_taken_rvcImm_T_17, UInt<1>(0h0))
node taken_rvcImm_lo_hi_1 = cat(_taken_rvcImm_T_15, _taken_rvcImm_T_16)
node taken_rvcImm_lo_1 = cat(taken_rvcImm_lo_hi_1, taken_rvcImm_lo_lo)
node taken_rvcImm_hi_lo = cat(_taken_rvcImm_T_13, _taken_rvcImm_T_14)
node taken_rvcImm_hi_hi_hi = cat(_taken_rvcImm_T_10, _taken_rvcImm_T_11)
node taken_rvcImm_hi_hi_1 = cat(taken_rvcImm_hi_hi_hi, _taken_rvcImm_T_12)
node taken_rvcImm_hi_1 = cat(taken_rvcImm_hi_hi_1, taken_rvcImm_hi_lo)
node _taken_rvcImm_T_18 = cat(taken_rvcImm_hi_1, taken_rvcImm_lo_1)
node _taken_rvcImm_T_19 = asSInt(_taken_rvcImm_T_18)
node taken_rvcImm = mux(_taken_rvcImm_T, _taken_rvcImm_T_8, _taken_rvcImm_T_19)
node _taken_rvcJR_T = and(taken_bits, UInt<16>(0hf003))
node _taken_rvcJR_T_1 = eq(UInt<16>(0h8002), _taken_rvcJR_T)
node _taken_rvcJR_T_2 = bits(taken_bits, 6, 2)
node _taken_rvcJR_T_3 = eq(_taken_rvcJR_T_2, UInt<1>(0h0))
node taken_rvcJR = and(_taken_rvcJR_T_1, _taken_rvcJR_T_3)
node _taken_rvcReturn_T = bits(taken_bits, 11, 7)
node _taken_rvcReturn_T_1 = and(_taken_rvcReturn_T, UInt<5>(0h1b))
node _taken_rvcReturn_T_2 = eq(UInt<1>(0h1), _taken_rvcReturn_T_1)
node taken_rvcReturn = and(taken_rvcJR, _taken_rvcReturn_T_2)
node _taken_rvcJALR_T = and(taken_bits, UInt<16>(0hf003))
node _taken_rvcJALR_T_1 = eq(UInt<16>(0h9002), _taken_rvcJALR_T)
node _taken_rvcJALR_T_2 = bits(taken_bits, 6, 2)
node _taken_rvcJALR_T_3 = eq(_taken_rvcJALR_T_2, UInt<1>(0h0))
node taken_rvcJALR = and(_taken_rvcJALR_T_1, _taken_rvcJALR_T_3)
node taken_rvcCall = or(taken_rvcJAL, taken_rvcJALR)
node _taken_rviImm_T = bits(taken_rviBits, 3, 3)
node _taken_rviImm_sign_T = eq(UInt<3>(0h3), UInt<3>(0h5))
node _taken_rviImm_sign_T_1 = bits(taken_rviBits, 31, 31)
node _taken_rviImm_sign_T_2 = asSInt(_taken_rviImm_sign_T_1)
node taken_rviImm_sign = mux(_taken_rviImm_sign_T, asSInt(UInt<1>(0h0)), _taken_rviImm_sign_T_2)
node _taken_rviImm_b30_20_T = eq(UInt<3>(0h3), UInt<3>(0h2))
node _taken_rviImm_b30_20_T_1 = bits(taken_rviBits, 30, 20)
node _taken_rviImm_b30_20_T_2 = asSInt(_taken_rviImm_b30_20_T_1)
node taken_rviImm_b30_20 = mux(_taken_rviImm_b30_20_T, _taken_rviImm_b30_20_T_2, taken_rviImm_sign)
node _taken_rviImm_b19_12_T = neq(UInt<3>(0h3), UInt<3>(0h2))
node _taken_rviImm_b19_12_T_1 = neq(UInt<3>(0h3), UInt<3>(0h3))
node _taken_rviImm_b19_12_T_2 = and(_taken_rviImm_b19_12_T, _taken_rviImm_b19_12_T_1)
node _taken_rviImm_b19_12_T_3 = bits(taken_rviBits, 19, 12)
node _taken_rviImm_b19_12_T_4 = asSInt(_taken_rviImm_b19_12_T_3)
node taken_rviImm_b19_12 = mux(_taken_rviImm_b19_12_T_2, taken_rviImm_sign, _taken_rviImm_b19_12_T_4)
node _taken_rviImm_b11_T = eq(UInt<3>(0h3), UInt<3>(0h2))
node _taken_rviImm_b11_T_1 = eq(UInt<3>(0h3), UInt<3>(0h5))
node _taken_rviImm_b11_T_2 = or(_taken_rviImm_b11_T, _taken_rviImm_b11_T_1)
node _taken_rviImm_b11_T_3 = eq(UInt<3>(0h3), UInt<3>(0h3))
node _taken_rviImm_b11_T_4 = bits(taken_rviBits, 20, 20)
node _taken_rviImm_b11_T_5 = asSInt(_taken_rviImm_b11_T_4)
node _taken_rviImm_b11_T_6 = eq(UInt<3>(0h3), UInt<3>(0h1))
node _taken_rviImm_b11_T_7 = bits(taken_rviBits, 7, 7)
node _taken_rviImm_b11_T_8 = asSInt(_taken_rviImm_b11_T_7)
node _taken_rviImm_b11_T_9 = mux(_taken_rviImm_b11_T_6, _taken_rviImm_b11_T_8, taken_rviImm_sign)
node _taken_rviImm_b11_T_10 = mux(_taken_rviImm_b11_T_3, _taken_rviImm_b11_T_5, _taken_rviImm_b11_T_9)
node taken_rviImm_b11 = mux(_taken_rviImm_b11_T_2, asSInt(UInt<1>(0h0)), _taken_rviImm_b11_T_10)
node _taken_rviImm_b10_5_T = eq(UInt<3>(0h3), UInt<3>(0h2))
node _taken_rviImm_b10_5_T_1 = eq(UInt<3>(0h3), UInt<3>(0h5))
node _taken_rviImm_b10_5_T_2 = or(_taken_rviImm_b10_5_T, _taken_rviImm_b10_5_T_1)
node _taken_rviImm_b10_5_T_3 = bits(taken_rviBits, 30, 25)
node taken_rviImm_b10_5 = mux(_taken_rviImm_b10_5_T_2, UInt<1>(0h0), _taken_rviImm_b10_5_T_3)
node _taken_rviImm_b4_1_T = eq(UInt<3>(0h3), UInt<3>(0h2))
node _taken_rviImm_b4_1_T_1 = eq(UInt<3>(0h3), UInt<3>(0h0))
node _taken_rviImm_b4_1_T_2 = eq(UInt<3>(0h3), UInt<3>(0h1))
node _taken_rviImm_b4_1_T_3 = or(_taken_rviImm_b4_1_T_1, _taken_rviImm_b4_1_T_2)
node _taken_rviImm_b4_1_T_4 = bits(taken_rviBits, 11, 8)
node _taken_rviImm_b4_1_T_5 = eq(UInt<3>(0h3), UInt<3>(0h5))
node _taken_rviImm_b4_1_T_6 = bits(taken_rviBits, 19, 16)
node _taken_rviImm_b4_1_T_7 = bits(taken_rviBits, 24, 21)
node _taken_rviImm_b4_1_T_8 = mux(_taken_rviImm_b4_1_T_5, _taken_rviImm_b4_1_T_6, _taken_rviImm_b4_1_T_7)
node _taken_rviImm_b4_1_T_9 = mux(_taken_rviImm_b4_1_T_3, _taken_rviImm_b4_1_T_4, _taken_rviImm_b4_1_T_8)
node taken_rviImm_b4_1 = mux(_taken_rviImm_b4_1_T, UInt<1>(0h0), _taken_rviImm_b4_1_T_9)
node _taken_rviImm_b0_T = eq(UInt<3>(0h3), UInt<3>(0h0))
node _taken_rviImm_b0_T_1 = bits(taken_rviBits, 7, 7)
node _taken_rviImm_b0_T_2 = eq(UInt<3>(0h3), UInt<3>(0h4))
node _taken_rviImm_b0_T_3 = bits(taken_rviBits, 20, 20)
node _taken_rviImm_b0_T_4 = eq(UInt<3>(0h3), UInt<3>(0h5))
node _taken_rviImm_b0_T_5 = bits(taken_rviBits, 15, 15)
node _taken_rviImm_b0_T_6 = mux(_taken_rviImm_b0_T_4, _taken_rviImm_b0_T_5, UInt<1>(0h0))
node _taken_rviImm_b0_T_7 = mux(_taken_rviImm_b0_T_2, _taken_rviImm_b0_T_3, _taken_rviImm_b0_T_6)
node taken_rviImm_b0 = mux(_taken_rviImm_b0_T, _taken_rviImm_b0_T_1, _taken_rviImm_b0_T_7)
node taken_rviImm_lo_hi = cat(taken_rviImm_b10_5, taken_rviImm_b4_1)
node taken_rviImm_lo = cat(taken_rviImm_lo_hi, taken_rviImm_b0)
node taken_rviImm_hi_lo_lo = asUInt(taken_rviImm_b11)
node taken_rviImm_hi_lo_hi = asUInt(taken_rviImm_b19_12)
node taken_rviImm_hi_lo = cat(taken_rviImm_hi_lo_hi, taken_rviImm_hi_lo_lo)
node taken_rviImm_hi_hi_lo = asUInt(taken_rviImm_b30_20)
node taken_rviImm_hi_hi_hi = asUInt(taken_rviImm_sign)
node taken_rviImm_hi_hi = cat(taken_rviImm_hi_hi_hi, taken_rviImm_hi_hi_lo)
node taken_rviImm_hi = cat(taken_rviImm_hi_hi, taken_rviImm_hi_lo)
node _taken_rviImm_T_1 = cat(taken_rviImm_hi, taken_rviImm_lo)
node _taken_rviImm_T_2 = asSInt(_taken_rviImm_T_1)
node _taken_rviImm_sign_T_3 = eq(UInt<3>(0h1), UInt<3>(0h5))
node _taken_rviImm_sign_T_4 = bits(taken_rviBits, 31, 31)
node _taken_rviImm_sign_T_5 = asSInt(_taken_rviImm_sign_T_4)
node taken_rviImm_sign_1 = mux(_taken_rviImm_sign_T_3, asSInt(UInt<1>(0h0)), _taken_rviImm_sign_T_5)
node _taken_rviImm_b30_20_T_3 = eq(UInt<3>(0h1), UInt<3>(0h2))
node _taken_rviImm_b30_20_T_4 = bits(taken_rviBits, 30, 20)
node _taken_rviImm_b30_20_T_5 = asSInt(_taken_rviImm_b30_20_T_4)
node taken_rviImm_b30_20_1 = mux(_taken_rviImm_b30_20_T_3, _taken_rviImm_b30_20_T_5, taken_rviImm_sign_1)
node _taken_rviImm_b19_12_T_5 = neq(UInt<3>(0h1), UInt<3>(0h2))
node _taken_rviImm_b19_12_T_6 = neq(UInt<3>(0h1), UInt<3>(0h3))
node _taken_rviImm_b19_12_T_7 = and(_taken_rviImm_b19_12_T_5, _taken_rviImm_b19_12_T_6)
node _taken_rviImm_b19_12_T_8 = bits(taken_rviBits, 19, 12)
node _taken_rviImm_b19_12_T_9 = asSInt(_taken_rviImm_b19_12_T_8)
node taken_rviImm_b19_12_1 = mux(_taken_rviImm_b19_12_T_7, taken_rviImm_sign_1, _taken_rviImm_b19_12_T_9)
node _taken_rviImm_b11_T_11 = eq(UInt<3>(0h1), UInt<3>(0h2))
node _taken_rviImm_b11_T_12 = eq(UInt<3>(0h1), UInt<3>(0h5))
node _taken_rviImm_b11_T_13 = or(_taken_rviImm_b11_T_11, _taken_rviImm_b11_T_12)
node _taken_rviImm_b11_T_14 = eq(UInt<3>(0h1), UInt<3>(0h3))
node _taken_rviImm_b11_T_15 = bits(taken_rviBits, 20, 20)
node _taken_rviImm_b11_T_16 = asSInt(_taken_rviImm_b11_T_15)
node _taken_rviImm_b11_T_17 = eq(UInt<3>(0h1), UInt<3>(0h1))
node _taken_rviImm_b11_T_18 = bits(taken_rviBits, 7, 7)
node _taken_rviImm_b11_T_19 = asSInt(_taken_rviImm_b11_T_18)
node _taken_rviImm_b11_T_20 = mux(_taken_rviImm_b11_T_17, _taken_rviImm_b11_T_19, taken_rviImm_sign_1)
node _taken_rviImm_b11_T_21 = mux(_taken_rviImm_b11_T_14, _taken_rviImm_b11_T_16, _taken_rviImm_b11_T_20)
node taken_rviImm_b11_1 = mux(_taken_rviImm_b11_T_13, asSInt(UInt<1>(0h0)), _taken_rviImm_b11_T_21)
node _taken_rviImm_b10_5_T_4 = eq(UInt<3>(0h1), UInt<3>(0h2))
node _taken_rviImm_b10_5_T_5 = eq(UInt<3>(0h1), UInt<3>(0h5))
node _taken_rviImm_b10_5_T_6 = or(_taken_rviImm_b10_5_T_4, _taken_rviImm_b10_5_T_5)
node _taken_rviImm_b10_5_T_7 = bits(taken_rviBits, 30, 25)
node taken_rviImm_b10_5_1 = mux(_taken_rviImm_b10_5_T_6, UInt<1>(0h0), _taken_rviImm_b10_5_T_7)
node _taken_rviImm_b4_1_T_10 = eq(UInt<3>(0h1), UInt<3>(0h2))
node _taken_rviImm_b4_1_T_11 = eq(UInt<3>(0h1), UInt<3>(0h0))
node _taken_rviImm_b4_1_T_12 = eq(UInt<3>(0h1), UInt<3>(0h1))
node _taken_rviImm_b4_1_T_13 = or(_taken_rviImm_b4_1_T_11, _taken_rviImm_b4_1_T_12)
node _taken_rviImm_b4_1_T_14 = bits(taken_rviBits, 11, 8)
node _taken_rviImm_b4_1_T_15 = eq(UInt<3>(0h1), UInt<3>(0h5))
node _taken_rviImm_b4_1_T_16 = bits(taken_rviBits, 19, 16)
node _taken_rviImm_b4_1_T_17 = bits(taken_rviBits, 24, 21)
node _taken_rviImm_b4_1_T_18 = mux(_taken_rviImm_b4_1_T_15, _taken_rviImm_b4_1_T_16, _taken_rviImm_b4_1_T_17)
node _taken_rviImm_b4_1_T_19 = mux(_taken_rviImm_b4_1_T_13, _taken_rviImm_b4_1_T_14, _taken_rviImm_b4_1_T_18)
node taken_rviImm_b4_1_1 = mux(_taken_rviImm_b4_1_T_10, UInt<1>(0h0), _taken_rviImm_b4_1_T_19)
node _taken_rviImm_b0_T_8 = eq(UInt<3>(0h1), UInt<3>(0h0))
node _taken_rviImm_b0_T_9 = bits(taken_rviBits, 7, 7)
node _taken_rviImm_b0_T_10 = eq(UInt<3>(0h1), UInt<3>(0h4))
node _taken_rviImm_b0_T_11 = bits(taken_rviBits, 20, 20)
node _taken_rviImm_b0_T_12 = eq(UInt<3>(0h1), UInt<3>(0h5))
node _taken_rviImm_b0_T_13 = bits(taken_rviBits, 15, 15)
node _taken_rviImm_b0_T_14 = mux(_taken_rviImm_b0_T_12, _taken_rviImm_b0_T_13, UInt<1>(0h0))
node _taken_rviImm_b0_T_15 = mux(_taken_rviImm_b0_T_10, _taken_rviImm_b0_T_11, _taken_rviImm_b0_T_14)
node taken_rviImm_b0_1 = mux(_taken_rviImm_b0_T_8, _taken_rviImm_b0_T_9, _taken_rviImm_b0_T_15)
node taken_rviImm_lo_hi_1 = cat(taken_rviImm_b10_5_1, taken_rviImm_b4_1_1)
node taken_rviImm_lo_1 = cat(taken_rviImm_lo_hi_1, taken_rviImm_b0_1)
node taken_rviImm_hi_lo_lo_1 = asUInt(taken_rviImm_b11_1)
node taken_rviImm_hi_lo_hi_1 = asUInt(taken_rviImm_b19_12_1)
node taken_rviImm_hi_lo_1 = cat(taken_rviImm_hi_lo_hi_1, taken_rviImm_hi_lo_lo_1)
node taken_rviImm_hi_hi_lo_1 = asUInt(taken_rviImm_b30_20_1)
node taken_rviImm_hi_hi_hi_1 = asUInt(taken_rviImm_sign_1)
node taken_rviImm_hi_hi_1 = cat(taken_rviImm_hi_hi_hi_1, taken_rviImm_hi_hi_lo_1)
node taken_rviImm_hi_1 = cat(taken_rviImm_hi_hi_1, taken_rviImm_hi_lo_1)
node _taken_rviImm_T_3 = cat(taken_rviImm_hi_1, taken_rviImm_lo_1)
node _taken_rviImm_T_4 = asSInt(_taken_rviImm_T_3)
node taken_rviImm = mux(_taken_rviImm_T, _taken_rviImm_T_2, _taken_rviImm_T_4)
node _taken_predict_taken_T = bits(s2_btb_resp_bits.bht.value, 0, 0)
node taken_predict_taken = or(_taken_predict_taken_T, UInt<1>(0h0))
node _taken_taken_T = or(taken_rviJump, taken_rviJALR)
node _taken_taken_T_1 = and(taken_rviBranch, taken_predict_taken)
node _taken_taken_T_2 = or(_taken_taken_T, _taken_taken_T_1)
node _taken_taken_T_3 = and(taken_prevRVI, _taken_taken_T_2)
node _taken_taken_T_4 = or(taken_rvcJump, taken_rvcJALR)
node _taken_taken_T_5 = or(_taken_taken_T_4, taken_rvcJR)
node _taken_taken_T_6 = and(taken_rvcBranch, taken_predict_taken)
node _taken_taken_T_7 = or(_taken_taken_T_5, _taken_taken_T_6)
node _taken_taken_T_8 = and(taken_valid, _taken_taken_T_7)
node taken_taken = or(_taken_taken_T_3, _taken_taken_T_8)
node _taken_predictReturn_T = and(taken_prevRVI, taken_rviReturn)
node _taken_predictReturn_T_1 = and(taken_valid, taken_rvcReturn)
node _taken_predictReturn_T_2 = or(_taken_predictReturn_T, _taken_predictReturn_T_1)
node taken_predictReturn = and(btb.io.ras_head.valid, _taken_predictReturn_T_2)
node _taken_predictJump_T = and(taken_prevRVI, taken_rviJump)
node _taken_predictJump_T_1 = and(taken_valid, taken_rvcJump)
node taken_predictJump = or(_taken_predictJump_T, _taken_predictJump_T_1)
node _taken_predictBranch_T = and(taken_prevRVI, taken_rviBranch)
node _taken_predictBranch_T_1 = and(taken_valid, taken_rvcBranch)
node _taken_predictBranch_T_2 = or(_taken_predictBranch_T, _taken_predictBranch_T_1)
node taken_predictBranch = and(taken_predict_taken, _taken_predictBranch_T_2)
node _taken_T = and(s2_valid, s2_btb_resp_valid)
node _taken_T_1 = eq(s2_btb_resp_bits.bridx, UInt<1>(0h0))
node _taken_T_2 = and(_taken_T, _taken_T_1)
node _taken_T_3 = and(_taken_T_2, taken_valid)
node _taken_T_4 = eq(taken_rvc, UInt<1>(0h0))
node _taken_T_5 = and(_taken_T_3, _taken_T_4)
when _taken_T_5 :
connect btb.io.flush, UInt<1>(0h1)
connect fq.io.enq.bits.replay, UInt<1>(0h1)
connect wrong_path, UInt<1>(0h1)
node _taken_T_6 = eq(UInt<1>(0h0), UInt<1>(0h0))
when _taken_T_6 :
connect taken_idx, UInt<1>(0h0)
connect after_idx, UInt<1>(0h1)
node _taken_btb_io_ras_update_valid_T = and(fq.io.enq.ready, fq.io.enq.valid)
node _taken_btb_io_ras_update_valid_T_1 = eq(wrong_path, UInt<1>(0h0))
node _taken_btb_io_ras_update_valid_T_2 = and(_taken_btb_io_ras_update_valid_T, _taken_btb_io_ras_update_valid_T_1)
node _taken_btb_io_ras_update_valid_T_3 = or(taken_rviCall, taken_rviReturn)
node _taken_btb_io_ras_update_valid_T_4 = and(taken_prevRVI, _taken_btb_io_ras_update_valid_T_3)
node _taken_btb_io_ras_update_valid_T_5 = or(taken_rvcCall, taken_rvcReturn)
node _taken_btb_io_ras_update_valid_T_6 = and(taken_valid, _taken_btb_io_ras_update_valid_T_5)
node _taken_btb_io_ras_update_valid_T_7 = or(_taken_btb_io_ras_update_valid_T_4, _taken_btb_io_ras_update_valid_T_6)
node _taken_btb_io_ras_update_valid_T_8 = and(_taken_btb_io_ras_update_valid_T_2, _taken_btb_io_ras_update_valid_T_7)
connect btb.io.ras_update.valid, _taken_btb_io_ras_update_valid_T_8
node _taken_btb_io_ras_update_bits_cfiType_T = mux(taken_prevRVI, taken_rviReturn, taken_rvcReturn)
node _taken_btb_io_ras_update_bits_cfiType_T_1 = mux(taken_prevRVI, taken_rviCall, taken_rvcCall)
node _taken_btb_io_ras_update_bits_cfiType_T_2 = mux(taken_prevRVI, taken_rviBranch, taken_rvcBranch)
node _taken_btb_io_ras_update_bits_cfiType_T_3 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _taken_btb_io_ras_update_bits_cfiType_T_4 = and(_taken_btb_io_ras_update_bits_cfiType_T_2, _taken_btb_io_ras_update_bits_cfiType_T_3)
node _taken_btb_io_ras_update_bits_cfiType_T_5 = mux(_taken_btb_io_ras_update_bits_cfiType_T_4, UInt<1>(0h0), UInt<1>(0h1))
node _taken_btb_io_ras_update_bits_cfiType_T_6 = mux(_taken_btb_io_ras_update_bits_cfiType_T_1, UInt<2>(0h2), _taken_btb_io_ras_update_bits_cfiType_T_5)
node _taken_btb_io_ras_update_bits_cfiType_T_7 = mux(_taken_btb_io_ras_update_bits_cfiType_T, UInt<2>(0h3), _taken_btb_io_ras_update_bits_cfiType_T_6)
connect btb.io.ras_update.bits.cfiType, _taken_btb_io_ras_update_bits_cfiType_T_7
node _taken_T_7 = eq(s2_btb_taken, UInt<1>(0h0))
when _taken_T_7 :
node _taken_T_8 = and(fq.io.enq.ready, fq.io.enq.valid)
node _taken_T_9 = and(_taken_T_8, taken_taken)
node _taken_T_10 = eq(taken_predictBranch, UInt<1>(0h0))
node _taken_T_11 = and(_taken_T_9, _taken_T_10)
node _taken_T_12 = eq(taken_predictJump, UInt<1>(0h0))
node _taken_T_13 = and(_taken_T_11, _taken_T_12)
node _taken_T_14 = eq(taken_predictReturn, UInt<1>(0h0))
node _taken_T_15 = and(_taken_T_13, _taken_T_14)
when _taken_T_15 :
connect wrong_path, UInt<1>(0h1)
node _taken_T_16 = and(s2_valid, taken_predictReturn)
when _taken_T_16 :
connect useRAS, UInt<1>(0h1)
node _taken_T_17 = or(taken_predictBranch, taken_predictJump)
node _taken_T_18 = and(s2_valid, _taken_T_17)
when _taken_T_18 :
node taken_pc = or(s2_base_pc, UInt<1>(0h0))
node _taken_npc_T = asSInt(taken_pc)
node _taken_npc_T_1 = sub(taken_rviImm, asSInt(UInt<3>(0h2)))
node _taken_npc_T_2 = mux(taken_prevRVI, _taken_npc_T_1, taken_rvcImm)
node _taken_npc_T_3 = add(_taken_npc_T, _taken_npc_T_2)
node _taken_npc_T_4 = tail(_taken_npc_T_3, 1)
node taken_npc = asSInt(_taken_npc_T_4)
node _taken_predicted_npc_T = asUInt(taken_npc)
connect predicted_npc, _taken_predicted_npc_T
node _taken_T_19 = and(taken_prevRVI, taken_rviBranch)
node _taken_T_20 = and(taken_valid, taken_rvcBranch)
node _taken_T_21 = or(_taken_T_19, _taken_T_20)
when _taken_T_21 :
node _taken_btb_io_bht_advance_valid_T = and(fq.io.enq.ready, fq.io.enq.valid)
node _taken_btb_io_bht_advance_valid_T_1 = eq(wrong_path, UInt<1>(0h0))
node _taken_btb_io_bht_advance_valid_T_2 = and(_taken_btb_io_bht_advance_valid_T, _taken_btb_io_bht_advance_valid_T_1)
connect btb.io.bht_advance.valid, _taken_btb_io_bht_advance_valid_T_2
connect btb.io.bht_advance.bits.bht.value, s2_btb_resp_bits.bht.value
connect btb.io.bht_advance.bits.bht.history, s2_btb_resp_bits.bht.history
connect btb.io.bht_advance.bits.entry, s2_btb_resp_bits.entry
connect btb.io.bht_advance.bits.target, s2_btb_resp_bits.target
connect btb.io.bht_advance.bits.bridx, s2_btb_resp_bits.bridx
connect btb.io.bht_advance.bits.mask, s2_btb_resp_bits.mask
connect btb.io.bht_advance.bits.taken, s2_btb_resp_bits.taken
connect btb.io.bht_advance.bits.cfiType, s2_btb_resp_bits.cfiType
node _taken_T_22 = eq(s2_btb_resp_valid, UInt<1>(0h0))
node _taken_T_23 = eq(s2_btb_resp_bits.bht.value, UInt<1>(0h1))
node _taken_T_24 = and(taken_predictBranch, _taken_T_23)
node _taken_T_25 = or(_taken_T_24, taken_predictJump)
node _taken_T_26 = or(_taken_T_25, taken_predictReturn)
node _taken_T_27 = and(_taken_T_22, _taken_T_26)
when _taken_T_27 :
connect updateBTB, UInt<1>(0h1)
node _taken_T_28 = or(UInt<1>(0h0), taken_taken)
node _taken_prevRVI_T_3 = bits(taken_bits, 1, 0)
node _taken_prevRVI_T_4 = neq(_taken_prevRVI_T_3, UInt<2>(0h3))
node _taken_prevRVI_T_5 = eq(_taken_prevRVI_T_4, UInt<1>(0h0))
node taken_prevRVI_1 = and(taken_valid, _taken_prevRVI_T_5)
node _taken_valid_T_2 = bits(fq.io.enq.bits.mask, 1, 1)
node _taken_valid_T_3 = eq(taken_prevRVI_1, UInt<1>(0h0))
node taken_valid_1 = and(_taken_valid_T_2, _taken_valid_T_3)
node taken_bits_1 = bits(fq.io.enq.bits.data, 31, 16)
node _taken_rvc_T_1 = bits(taken_bits_1, 1, 0)
node taken_rvc_1 = neq(_taken_rvc_T_1, UInt<2>(0h3))
node taken_rviBits_1 = cat(taken_bits_1, taken_bits)
node _taken_rviBranch_T_1 = bits(taken_rviBits_1, 6, 0)
node taken_rviBranch_1 = eq(_taken_rviBranch_T_1, UInt<7>(0h63))
node _taken_rviJump_T_1 = bits(taken_rviBits_1, 6, 0)
node taken_rviJump_1 = eq(_taken_rviJump_T_1, UInt<7>(0h6f))
node _taken_rviJALR_T_1 = bits(taken_rviBits_1, 6, 0)
node taken_rviJALR_1 = eq(_taken_rviJALR_T_1, UInt<7>(0h67))
node _taken_rviReturn_T_6 = bits(taken_rviBits_1, 7, 7)
node _taken_rviReturn_T_7 = eq(_taken_rviReturn_T_6, UInt<1>(0h0))
node _taken_rviReturn_T_8 = and(taken_rviJALR_1, _taken_rviReturn_T_7)
node _taken_rviReturn_T_9 = bits(taken_rviBits_1, 19, 15)
node _taken_rviReturn_T_10 = and(_taken_rviReturn_T_9, UInt<5>(0h1b))
node _taken_rviReturn_T_11 = eq(UInt<1>(0h1), _taken_rviReturn_T_10)
node taken_rviReturn_1 = and(_taken_rviReturn_T_8, _taken_rviReturn_T_11)
node _taken_rviCall_T_2 = or(taken_rviJALR_1, taken_rviJump_1)
node _taken_rviCall_T_3 = bits(taken_rviBits_1, 7, 7)
node taken_rviCall_1 = and(_taken_rviCall_T_2, _taken_rviCall_T_3)
node _taken_rvcBranch_T_4 = and(taken_bits_1, UInt<16>(0he003))
node _taken_rvcBranch_T_5 = eq(UInt<16>(0hc001), _taken_rvcBranch_T_4)
node _taken_rvcBranch_T_6 = and(taken_bits_1, UInt<16>(0he003))
node _taken_rvcBranch_T_7 = eq(UInt<16>(0he001), _taken_rvcBranch_T_6)
node taken_rvcBranch_1 = or(_taken_rvcBranch_T_5, _taken_rvcBranch_T_7)
node _taken_rvcJAL_T_2 = and(taken_bits_1, UInt<16>(0he003))
node _taken_rvcJAL_T_3 = eq(UInt<14>(0h2001), _taken_rvcJAL_T_2)
node taken_rvcJAL_1 = and(UInt<1>(0h0), _taken_rvcJAL_T_3)
node _taken_rvcJump_T_2 = and(taken_bits_1, UInt<16>(0he003))
node _taken_rvcJump_T_3 = eq(UInt<16>(0ha001), _taken_rvcJump_T_2)
node taken_rvcJump_1 = or(_taken_rvcJump_T_3, taken_rvcJAL_1)
node _taken_rvcImm_T_20 = bits(taken_bits_1, 14, 14)
node _taken_rvcImm_T_21 = bits(taken_bits_1, 12, 12)
node _taken_rvcImm_T_22 = mux(_taken_rvcImm_T_21, UInt<5>(0h1f), UInt<5>(0h0))
node _taken_rvcImm_T_23 = bits(taken_bits_1, 6, 5)
node _taken_rvcImm_T_24 = bits(taken_bits_1, 2, 2)
node _taken_rvcImm_T_25 = bits(taken_bits_1, 11, 10)
node _taken_rvcImm_T_26 = bits(taken_bits_1, 4, 3)
node taken_rvcImm_lo_hi_2 = cat(_taken_rvcImm_T_25, _taken_rvcImm_T_26)
node taken_rvcImm_lo_2 = cat(taken_rvcImm_lo_hi_2, UInt<1>(0h0))
node taken_rvcImm_hi_hi_2 = cat(_taken_rvcImm_T_22, _taken_rvcImm_T_23)
node taken_rvcImm_hi_2 = cat(taken_rvcImm_hi_hi_2, _taken_rvcImm_T_24)
node _taken_rvcImm_T_27 = cat(taken_rvcImm_hi_2, taken_rvcImm_lo_2)
node _taken_rvcImm_T_28 = asSInt(_taken_rvcImm_T_27)
node _taken_rvcImm_T_29 = bits(taken_bits_1, 12, 12)
node _taken_rvcImm_T_30 = mux(_taken_rvcImm_T_29, UInt<10>(0h3ff), UInt<10>(0h0))
node _taken_rvcImm_T_31 = bits(taken_bits_1, 8, 8)
node _taken_rvcImm_T_32 = bits(taken_bits_1, 10, 9)
node _taken_rvcImm_T_33 = bits(taken_bits_1, 6, 6)
node _taken_rvcImm_T_34 = bits(taken_bits_1, 7, 7)
node _taken_rvcImm_T_35 = bits(taken_bits_1, 2, 2)
node _taken_rvcImm_T_36 = bits(taken_bits_1, 11, 11)
node _taken_rvcImm_T_37 = bits(taken_bits_1, 5, 3)
node taken_rvcImm_lo_lo_1 = cat(_taken_rvcImm_T_37, UInt<1>(0h0))
node taken_rvcImm_lo_hi_3 = cat(_taken_rvcImm_T_35, _taken_rvcImm_T_36)
node taken_rvcImm_lo_3 = cat(taken_rvcImm_lo_hi_3, taken_rvcImm_lo_lo_1)
node taken_rvcImm_hi_lo_1 = cat(_taken_rvcImm_T_33, _taken_rvcImm_T_34)
node taken_rvcImm_hi_hi_hi_1 = cat(_taken_rvcImm_T_30, _taken_rvcImm_T_31)
node taken_rvcImm_hi_hi_3 = cat(taken_rvcImm_hi_hi_hi_1, _taken_rvcImm_T_32)
node taken_rvcImm_hi_3 = cat(taken_rvcImm_hi_hi_3, taken_rvcImm_hi_lo_1)
node _taken_rvcImm_T_38 = cat(taken_rvcImm_hi_3, taken_rvcImm_lo_3)
node _taken_rvcImm_T_39 = asSInt(_taken_rvcImm_T_38)
node taken_rvcImm_1 = mux(_taken_rvcImm_T_20, _taken_rvcImm_T_28, _taken_rvcImm_T_39)
node _taken_rvcJR_T_4 = and(taken_bits_1, UInt<16>(0hf003))
node _taken_rvcJR_T_5 = eq(UInt<16>(0h8002), _taken_rvcJR_T_4)
node _taken_rvcJR_T_6 = bits(taken_bits_1, 6, 2)
node _taken_rvcJR_T_7 = eq(_taken_rvcJR_T_6, UInt<1>(0h0))
node taken_rvcJR_1 = and(_taken_rvcJR_T_5, _taken_rvcJR_T_7)
node _taken_rvcReturn_T_3 = bits(taken_bits_1, 11, 7)
node _taken_rvcReturn_T_4 = and(_taken_rvcReturn_T_3, UInt<5>(0h1b))
node _taken_rvcReturn_T_5 = eq(UInt<1>(0h1), _taken_rvcReturn_T_4)
node taken_rvcReturn_1 = and(taken_rvcJR_1, _taken_rvcReturn_T_5)
node _taken_rvcJALR_T_4 = and(taken_bits_1, UInt<16>(0hf003))
node _taken_rvcJALR_T_5 = eq(UInt<16>(0h9002), _taken_rvcJALR_T_4)
node _taken_rvcJALR_T_6 = bits(taken_bits_1, 6, 2)
node _taken_rvcJALR_T_7 = eq(_taken_rvcJALR_T_6, UInt<1>(0h0))
node taken_rvcJALR_1 = and(_taken_rvcJALR_T_5, _taken_rvcJALR_T_7)
node taken_rvcCall_1 = or(taken_rvcJAL_1, taken_rvcJALR_1)
node _taken_rviImm_T_5 = bits(taken_rviBits_1, 3, 3)
node _taken_rviImm_sign_T_6 = eq(UInt<3>(0h3), UInt<3>(0h5))
node _taken_rviImm_sign_T_7 = bits(taken_rviBits_1, 31, 31)
node _taken_rviImm_sign_T_8 = asSInt(_taken_rviImm_sign_T_7)
node taken_rviImm_sign_2 = mux(_taken_rviImm_sign_T_6, asSInt(UInt<1>(0h0)), _taken_rviImm_sign_T_8)
node _taken_rviImm_b30_20_T_6 = eq(UInt<3>(0h3), UInt<3>(0h2))
node _taken_rviImm_b30_20_T_7 = bits(taken_rviBits_1, 30, 20)
node _taken_rviImm_b30_20_T_8 = asSInt(_taken_rviImm_b30_20_T_7)
node taken_rviImm_b30_20_2 = mux(_taken_rviImm_b30_20_T_6, _taken_rviImm_b30_20_T_8, taken_rviImm_sign_2)
node _taken_rviImm_b19_12_T_10 = neq(UInt<3>(0h3), UInt<3>(0h2))
node _taken_rviImm_b19_12_T_11 = neq(UInt<3>(0h3), UInt<3>(0h3))
node _taken_rviImm_b19_12_T_12 = and(_taken_rviImm_b19_12_T_10, _taken_rviImm_b19_12_T_11)
node _taken_rviImm_b19_12_T_13 = bits(taken_rviBits_1, 19, 12)
node _taken_rviImm_b19_12_T_14 = asSInt(_taken_rviImm_b19_12_T_13)
node taken_rviImm_b19_12_2 = mux(_taken_rviImm_b19_12_T_12, taken_rviImm_sign_2, _taken_rviImm_b19_12_T_14)
node _taken_rviImm_b11_T_22 = eq(UInt<3>(0h3), UInt<3>(0h2))
node _taken_rviImm_b11_T_23 = eq(UInt<3>(0h3), UInt<3>(0h5))
node _taken_rviImm_b11_T_24 = or(_taken_rviImm_b11_T_22, _taken_rviImm_b11_T_23)
node _taken_rviImm_b11_T_25 = eq(UInt<3>(0h3), UInt<3>(0h3))
node _taken_rviImm_b11_T_26 = bits(taken_rviBits_1, 20, 20)
node _taken_rviImm_b11_T_27 = asSInt(_taken_rviImm_b11_T_26)
node _taken_rviImm_b11_T_28 = eq(UInt<3>(0h3), UInt<3>(0h1))
node _taken_rviImm_b11_T_29 = bits(taken_rviBits_1, 7, 7)
node _taken_rviImm_b11_T_30 = asSInt(_taken_rviImm_b11_T_29)
node _taken_rviImm_b11_T_31 = mux(_taken_rviImm_b11_T_28, _taken_rviImm_b11_T_30, taken_rviImm_sign_2)
node _taken_rviImm_b11_T_32 = mux(_taken_rviImm_b11_T_25, _taken_rviImm_b11_T_27, _taken_rviImm_b11_T_31)
node taken_rviImm_b11_2 = mux(_taken_rviImm_b11_T_24, asSInt(UInt<1>(0h0)), _taken_rviImm_b11_T_32)
node _taken_rviImm_b10_5_T_8 = eq(UInt<3>(0h3), UInt<3>(0h2))
node _taken_rviImm_b10_5_T_9 = eq(UInt<3>(0h3), UInt<3>(0h5))
node _taken_rviImm_b10_5_T_10 = or(_taken_rviImm_b10_5_T_8, _taken_rviImm_b10_5_T_9)
node _taken_rviImm_b10_5_T_11 = bits(taken_rviBits_1, 30, 25)
node taken_rviImm_b10_5_2 = mux(_taken_rviImm_b10_5_T_10, UInt<1>(0h0), _taken_rviImm_b10_5_T_11)
node _taken_rviImm_b4_1_T_20 = eq(UInt<3>(0h3), UInt<3>(0h2))
node _taken_rviImm_b4_1_T_21 = eq(UInt<3>(0h3), UInt<3>(0h0))
node _taken_rviImm_b4_1_T_22 = eq(UInt<3>(0h3), UInt<3>(0h1))
node _taken_rviImm_b4_1_T_23 = or(_taken_rviImm_b4_1_T_21, _taken_rviImm_b4_1_T_22)
node _taken_rviImm_b4_1_T_24 = bits(taken_rviBits_1, 11, 8)
node _taken_rviImm_b4_1_T_25 = eq(UInt<3>(0h3), UInt<3>(0h5))
node _taken_rviImm_b4_1_T_26 = bits(taken_rviBits_1, 19, 16)
node _taken_rviImm_b4_1_T_27 = bits(taken_rviBits_1, 24, 21)
node _taken_rviImm_b4_1_T_28 = mux(_taken_rviImm_b4_1_T_25, _taken_rviImm_b4_1_T_26, _taken_rviImm_b4_1_T_27)
node _taken_rviImm_b4_1_T_29 = mux(_taken_rviImm_b4_1_T_23, _taken_rviImm_b4_1_T_24, _taken_rviImm_b4_1_T_28)
node taken_rviImm_b4_1_2 = mux(_taken_rviImm_b4_1_T_20, UInt<1>(0h0), _taken_rviImm_b4_1_T_29)
node _taken_rviImm_b0_T_16 = eq(UInt<3>(0h3), UInt<3>(0h0))
node _taken_rviImm_b0_T_17 = bits(taken_rviBits_1, 7, 7)
node _taken_rviImm_b0_T_18 = eq(UInt<3>(0h3), UInt<3>(0h4))
node _taken_rviImm_b0_T_19 = bits(taken_rviBits_1, 20, 20)
node _taken_rviImm_b0_T_20 = eq(UInt<3>(0h3), UInt<3>(0h5))
node _taken_rviImm_b0_T_21 = bits(taken_rviBits_1, 15, 15)
node _taken_rviImm_b0_T_22 = mux(_taken_rviImm_b0_T_20, _taken_rviImm_b0_T_21, UInt<1>(0h0))
node _taken_rviImm_b0_T_23 = mux(_taken_rviImm_b0_T_18, _taken_rviImm_b0_T_19, _taken_rviImm_b0_T_22)
node taken_rviImm_b0_2 = mux(_taken_rviImm_b0_T_16, _taken_rviImm_b0_T_17, _taken_rviImm_b0_T_23)
node taken_rviImm_lo_hi_2 = cat(taken_rviImm_b10_5_2, taken_rviImm_b4_1_2)
node taken_rviImm_lo_2 = cat(taken_rviImm_lo_hi_2, taken_rviImm_b0_2)
node taken_rviImm_hi_lo_lo_2 = asUInt(taken_rviImm_b11_2)
node taken_rviImm_hi_lo_hi_2 = asUInt(taken_rviImm_b19_12_2)
node taken_rviImm_hi_lo_2 = cat(taken_rviImm_hi_lo_hi_2, taken_rviImm_hi_lo_lo_2)
node taken_rviImm_hi_hi_lo_2 = asUInt(taken_rviImm_b30_20_2)
node taken_rviImm_hi_hi_hi_2 = asUInt(taken_rviImm_sign_2)
node taken_rviImm_hi_hi_2 = cat(taken_rviImm_hi_hi_hi_2, taken_rviImm_hi_hi_lo_2)
node taken_rviImm_hi_2 = cat(taken_rviImm_hi_hi_2, taken_rviImm_hi_lo_2)
node _taken_rviImm_T_6 = cat(taken_rviImm_hi_2, taken_rviImm_lo_2)
node _taken_rviImm_T_7 = asSInt(_taken_rviImm_T_6)
node _taken_rviImm_sign_T_9 = eq(UInt<3>(0h1), UInt<3>(0h5))
node _taken_rviImm_sign_T_10 = bits(taken_rviBits_1, 31, 31)
node _taken_rviImm_sign_T_11 = asSInt(_taken_rviImm_sign_T_10)
node taken_rviImm_sign_3 = mux(_taken_rviImm_sign_T_9, asSInt(UInt<1>(0h0)), _taken_rviImm_sign_T_11)
node _taken_rviImm_b30_20_T_9 = eq(UInt<3>(0h1), UInt<3>(0h2))
node _taken_rviImm_b30_20_T_10 = bits(taken_rviBits_1, 30, 20)
node _taken_rviImm_b30_20_T_11 = asSInt(_taken_rviImm_b30_20_T_10)
node taken_rviImm_b30_20_3 = mux(_taken_rviImm_b30_20_T_9, _taken_rviImm_b30_20_T_11, taken_rviImm_sign_3)
node _taken_rviImm_b19_12_T_15 = neq(UInt<3>(0h1), UInt<3>(0h2))
node _taken_rviImm_b19_12_T_16 = neq(UInt<3>(0h1), UInt<3>(0h3))
node _taken_rviImm_b19_12_T_17 = and(_taken_rviImm_b19_12_T_15, _taken_rviImm_b19_12_T_16)
node _taken_rviImm_b19_12_T_18 = bits(taken_rviBits_1, 19, 12)
node _taken_rviImm_b19_12_T_19 = asSInt(_taken_rviImm_b19_12_T_18)
node taken_rviImm_b19_12_3 = mux(_taken_rviImm_b19_12_T_17, taken_rviImm_sign_3, _taken_rviImm_b19_12_T_19)
node _taken_rviImm_b11_T_33 = eq(UInt<3>(0h1), UInt<3>(0h2))
node _taken_rviImm_b11_T_34 = eq(UInt<3>(0h1), UInt<3>(0h5))
node _taken_rviImm_b11_T_35 = or(_taken_rviImm_b11_T_33, _taken_rviImm_b11_T_34)
node _taken_rviImm_b11_T_36 = eq(UInt<3>(0h1), UInt<3>(0h3))
node _taken_rviImm_b11_T_37 = bits(taken_rviBits_1, 20, 20)
node _taken_rviImm_b11_T_38 = asSInt(_taken_rviImm_b11_T_37)
node _taken_rviImm_b11_T_39 = eq(UInt<3>(0h1), UInt<3>(0h1))
node _taken_rviImm_b11_T_40 = bits(taken_rviBits_1, 7, 7)
node _taken_rviImm_b11_T_41 = asSInt(_taken_rviImm_b11_T_40)
node _taken_rviImm_b11_T_42 = mux(_taken_rviImm_b11_T_39, _taken_rviImm_b11_T_41, taken_rviImm_sign_3)
node _taken_rviImm_b11_T_43 = mux(_taken_rviImm_b11_T_36, _taken_rviImm_b11_T_38, _taken_rviImm_b11_T_42)
node taken_rviImm_b11_3 = mux(_taken_rviImm_b11_T_35, asSInt(UInt<1>(0h0)), _taken_rviImm_b11_T_43)
node _taken_rviImm_b10_5_T_12 = eq(UInt<3>(0h1), UInt<3>(0h2))
node _taken_rviImm_b10_5_T_13 = eq(UInt<3>(0h1), UInt<3>(0h5))
node _taken_rviImm_b10_5_T_14 = or(_taken_rviImm_b10_5_T_12, _taken_rviImm_b10_5_T_13)
node _taken_rviImm_b10_5_T_15 = bits(taken_rviBits_1, 30, 25)
node taken_rviImm_b10_5_3 = mux(_taken_rviImm_b10_5_T_14, UInt<1>(0h0), _taken_rviImm_b10_5_T_15)
node _taken_rviImm_b4_1_T_30 = eq(UInt<3>(0h1), UInt<3>(0h2))
node _taken_rviImm_b4_1_T_31 = eq(UInt<3>(0h1), UInt<3>(0h0))
node _taken_rviImm_b4_1_T_32 = eq(UInt<3>(0h1), UInt<3>(0h1))
node _taken_rviImm_b4_1_T_33 = or(_taken_rviImm_b4_1_T_31, _taken_rviImm_b4_1_T_32)
node _taken_rviImm_b4_1_T_34 = bits(taken_rviBits_1, 11, 8)
node _taken_rviImm_b4_1_T_35 = eq(UInt<3>(0h1), UInt<3>(0h5))
node _taken_rviImm_b4_1_T_36 = bits(taken_rviBits_1, 19, 16)
node _taken_rviImm_b4_1_T_37 = bits(taken_rviBits_1, 24, 21)
node _taken_rviImm_b4_1_T_38 = mux(_taken_rviImm_b4_1_T_35, _taken_rviImm_b4_1_T_36, _taken_rviImm_b4_1_T_37)
node _taken_rviImm_b4_1_T_39 = mux(_taken_rviImm_b4_1_T_33, _taken_rviImm_b4_1_T_34, _taken_rviImm_b4_1_T_38)
node taken_rviImm_b4_1_3 = mux(_taken_rviImm_b4_1_T_30, UInt<1>(0h0), _taken_rviImm_b4_1_T_39)
node _taken_rviImm_b0_T_24 = eq(UInt<3>(0h1), UInt<3>(0h0))
node _taken_rviImm_b0_T_25 = bits(taken_rviBits_1, 7, 7)
node _taken_rviImm_b0_T_26 = eq(UInt<3>(0h1), UInt<3>(0h4))
node _taken_rviImm_b0_T_27 = bits(taken_rviBits_1, 20, 20)
node _taken_rviImm_b0_T_28 = eq(UInt<3>(0h1), UInt<3>(0h5))
node _taken_rviImm_b0_T_29 = bits(taken_rviBits_1, 15, 15)
node _taken_rviImm_b0_T_30 = mux(_taken_rviImm_b0_T_28, _taken_rviImm_b0_T_29, UInt<1>(0h0))
node _taken_rviImm_b0_T_31 = mux(_taken_rviImm_b0_T_26, _taken_rviImm_b0_T_27, _taken_rviImm_b0_T_30)
node taken_rviImm_b0_3 = mux(_taken_rviImm_b0_T_24, _taken_rviImm_b0_T_25, _taken_rviImm_b0_T_31)
node taken_rviImm_lo_hi_3 = cat(taken_rviImm_b10_5_3, taken_rviImm_b4_1_3)
node taken_rviImm_lo_3 = cat(taken_rviImm_lo_hi_3, taken_rviImm_b0_3)
node taken_rviImm_hi_lo_lo_3 = asUInt(taken_rviImm_b11_3)
node taken_rviImm_hi_lo_hi_3 = asUInt(taken_rviImm_b19_12_3)
node taken_rviImm_hi_lo_3 = cat(taken_rviImm_hi_lo_hi_3, taken_rviImm_hi_lo_lo_3)
node taken_rviImm_hi_hi_lo_3 = asUInt(taken_rviImm_b30_20_3)
node taken_rviImm_hi_hi_hi_3 = asUInt(taken_rviImm_sign_3)
node taken_rviImm_hi_hi_3 = cat(taken_rviImm_hi_hi_hi_3, taken_rviImm_hi_hi_lo_3)
node taken_rviImm_hi_3 = cat(taken_rviImm_hi_hi_3, taken_rviImm_hi_lo_3)
node _taken_rviImm_T_8 = cat(taken_rviImm_hi_3, taken_rviImm_lo_3)
node _taken_rviImm_T_9 = asSInt(_taken_rviImm_T_8)
node taken_rviImm_1 = mux(_taken_rviImm_T_5, _taken_rviImm_T_7, _taken_rviImm_T_9)
node _taken_predict_taken_T_1 = bits(s2_btb_resp_bits.bht.value, 0, 0)
node taken_predict_taken_1 = or(_taken_predict_taken_T_1, UInt<1>(0h0))
node _taken_taken_T_9 = or(taken_rviJump_1, taken_rviJALR_1)
node _taken_taken_T_10 = and(taken_rviBranch_1, taken_predict_taken_1)
node _taken_taken_T_11 = or(_taken_taken_T_9, _taken_taken_T_10)
node _taken_taken_T_12 = and(taken_prevRVI_1, _taken_taken_T_11)
node _taken_taken_T_13 = or(taken_rvcJump_1, taken_rvcJALR_1)
node _taken_taken_T_14 = or(_taken_taken_T_13, taken_rvcJR_1)
node _taken_taken_T_15 = and(taken_rvcBranch_1, taken_predict_taken_1)
node _taken_taken_T_16 = or(_taken_taken_T_14, _taken_taken_T_15)
node _taken_taken_T_17 = and(taken_valid_1, _taken_taken_T_16)
node taken_taken_1 = or(_taken_taken_T_12, _taken_taken_T_17)
node _taken_predictReturn_T_3 = and(taken_prevRVI_1, taken_rviReturn_1)
node _taken_predictReturn_T_4 = and(taken_valid_1, taken_rvcReturn_1)
node _taken_predictReturn_T_5 = or(_taken_predictReturn_T_3, _taken_predictReturn_T_4)
node taken_predictReturn_1 = and(btb.io.ras_head.valid, _taken_predictReturn_T_5)
node _taken_predictJump_T_2 = and(taken_prevRVI_1, taken_rviJump_1)
node _taken_predictJump_T_3 = and(taken_valid_1, taken_rvcJump_1)
node taken_predictJump_1 = or(_taken_predictJump_T_2, _taken_predictJump_T_3)
node _taken_predictBranch_T_3 = and(taken_prevRVI_1, taken_rviBranch_1)
node _taken_predictBranch_T_4 = and(taken_valid_1, taken_rvcBranch_1)
node _taken_predictBranch_T_5 = or(_taken_predictBranch_T_3, _taken_predictBranch_T_4)
node taken_predictBranch_1 = and(taken_predict_taken_1, _taken_predictBranch_T_5)
node _taken_T_29 = and(s2_valid, s2_btb_resp_valid)
node _taken_T_30 = eq(s2_btb_resp_bits.bridx, UInt<1>(0h1))
node _taken_T_31 = and(_taken_T_29, _taken_T_30)
node _taken_T_32 = and(_taken_T_31, taken_valid_1)
node _taken_T_33 = eq(taken_rvc_1, UInt<1>(0h0))
node _taken_T_34 = and(_taken_T_32, _taken_T_33)
when _taken_T_34 :
connect btb.io.flush, UInt<1>(0h1)
connect fq.io.enq.bits.replay, UInt<1>(0h1)
connect wrong_path, UInt<1>(0h1)
node _taken_T_35 = eq(_taken_T_28, UInt<1>(0h0))
when _taken_T_35 :
connect taken_idx, UInt<1>(0h1)
connect after_idx, UInt<2>(0h2)
node _taken_btb_io_ras_update_valid_T_9 = and(fq.io.enq.ready, fq.io.enq.valid)
node _taken_btb_io_ras_update_valid_T_10 = eq(wrong_path, UInt<1>(0h0))
node _taken_btb_io_ras_update_valid_T_11 = and(_taken_btb_io_ras_update_valid_T_9, _taken_btb_io_ras_update_valid_T_10)
node _taken_btb_io_ras_update_valid_T_12 = or(taken_rviCall_1, taken_rviReturn_1)
node _taken_btb_io_ras_update_valid_T_13 = and(taken_prevRVI_1, _taken_btb_io_ras_update_valid_T_12)
node _taken_btb_io_ras_update_valid_T_14 = or(taken_rvcCall_1, taken_rvcReturn_1)
node _taken_btb_io_ras_update_valid_T_15 = and(taken_valid_1, _taken_btb_io_ras_update_valid_T_14)
node _taken_btb_io_ras_update_valid_T_16 = or(_taken_btb_io_ras_update_valid_T_13, _taken_btb_io_ras_update_valid_T_15)
node _taken_btb_io_ras_update_valid_T_17 = and(_taken_btb_io_ras_update_valid_T_11, _taken_btb_io_ras_update_valid_T_16)
connect btb.io.ras_update.valid, _taken_btb_io_ras_update_valid_T_17
node _taken_btb_io_ras_update_bits_cfiType_T_8 = mux(taken_prevRVI_1, taken_rviReturn_1, taken_rvcReturn_1)
node _taken_btb_io_ras_update_bits_cfiType_T_9 = mux(taken_prevRVI_1, taken_rviCall_1, taken_rvcCall_1)
node _taken_btb_io_ras_update_bits_cfiType_T_10 = mux(taken_prevRVI_1, taken_rviBranch_1, taken_rvcBranch_1)
node _taken_btb_io_ras_update_bits_cfiType_T_11 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _taken_btb_io_ras_update_bits_cfiType_T_12 = and(_taken_btb_io_ras_update_bits_cfiType_T_10, _taken_btb_io_ras_update_bits_cfiType_T_11)
node _taken_btb_io_ras_update_bits_cfiType_T_13 = mux(_taken_btb_io_ras_update_bits_cfiType_T_12, UInt<1>(0h0), UInt<1>(0h1))
node _taken_btb_io_ras_update_bits_cfiType_T_14 = mux(_taken_btb_io_ras_update_bits_cfiType_T_9, UInt<2>(0h2), _taken_btb_io_ras_update_bits_cfiType_T_13)
node _taken_btb_io_ras_update_bits_cfiType_T_15 = mux(_taken_btb_io_ras_update_bits_cfiType_T_8, UInt<2>(0h3), _taken_btb_io_ras_update_bits_cfiType_T_14)
connect btb.io.ras_update.bits.cfiType, _taken_btb_io_ras_update_bits_cfiType_T_15
node _taken_T_36 = eq(s2_btb_taken, UInt<1>(0h0))
when _taken_T_36 :
node _taken_T_37 = and(fq.io.enq.ready, fq.io.enq.valid)
node _taken_T_38 = and(_taken_T_37, taken_taken_1)
node _taken_T_39 = eq(taken_predictBranch_1, UInt<1>(0h0))
node _taken_T_40 = and(_taken_T_38, _taken_T_39)
node _taken_T_41 = eq(taken_predictJump_1, UInt<1>(0h0))
node _taken_T_42 = and(_taken_T_40, _taken_T_41)
node _taken_T_43 = eq(taken_predictReturn_1, UInt<1>(0h0))
node _taken_T_44 = and(_taken_T_42, _taken_T_43)
when _taken_T_44 :
connect wrong_path, UInt<1>(0h1)
node _taken_T_45 = and(s2_valid, taken_predictReturn_1)
when _taken_T_45 :
connect useRAS, UInt<1>(0h1)
node _taken_T_46 = or(taken_predictBranch_1, taken_predictJump_1)
node _taken_T_47 = and(s2_valid, _taken_T_46)
when _taken_T_47 :
node taken_pc_1 = or(s2_base_pc, UInt<2>(0h2))
node _taken_npc_T_5 = sub(taken_pc_1, UInt<2>(0h2))
node _taken_npc_T_6 = tail(_taken_npc_T_5, 1)
node _taken_npc_T_7 = mux(taken_prevRVI_1, _taken_npc_T_6, taken_pc_1)
node _taken_npc_T_8 = asSInt(_taken_npc_T_7)
node _taken_npc_T_9 = mux(taken_prevRVI_1, taken_rviImm_1, taken_rvcImm_1)
node _taken_npc_T_10 = add(_taken_npc_T_8, _taken_npc_T_9)
node _taken_npc_T_11 = tail(_taken_npc_T_10, 1)
node taken_npc_1 = asSInt(_taken_npc_T_11)
node _taken_predicted_npc_T_1 = asUInt(taken_npc_1)
connect predicted_npc, _taken_predicted_npc_T_1
node _taken_T_48 = and(taken_prevRVI_1, taken_rviBranch_1)
node _taken_T_49 = and(taken_valid_1, taken_rvcBranch_1)
node _taken_T_50 = or(_taken_T_48, _taken_T_49)
when _taken_T_50 :
node _taken_btb_io_bht_advance_valid_T_3 = and(fq.io.enq.ready, fq.io.enq.valid)
node _taken_btb_io_bht_advance_valid_T_4 = eq(wrong_path, UInt<1>(0h0))
node _taken_btb_io_bht_advance_valid_T_5 = and(_taken_btb_io_bht_advance_valid_T_3, _taken_btb_io_bht_advance_valid_T_4)
connect btb.io.bht_advance.valid, _taken_btb_io_bht_advance_valid_T_5
connect btb.io.bht_advance.bits.bht.value, s2_btb_resp_bits.bht.value
connect btb.io.bht_advance.bits.bht.history, s2_btb_resp_bits.bht.history
connect btb.io.bht_advance.bits.entry, s2_btb_resp_bits.entry
connect btb.io.bht_advance.bits.target, s2_btb_resp_bits.target
connect btb.io.bht_advance.bits.bridx, s2_btb_resp_bits.bridx
connect btb.io.bht_advance.bits.mask, s2_btb_resp_bits.mask
connect btb.io.bht_advance.bits.taken, s2_btb_resp_bits.taken
connect btb.io.bht_advance.bits.cfiType, s2_btb_resp_bits.cfiType
node _taken_T_51 = eq(s2_btb_resp_valid, UInt<1>(0h0))
node _taken_T_52 = eq(s2_btb_resp_bits.bht.value, UInt<1>(0h1))
node _taken_T_53 = and(taken_predictBranch_1, _taken_T_52)
node _taken_T_54 = or(_taken_T_53, taken_predictJump_1)
node _taken_T_55 = or(_taken_T_54, taken_predictReturn_1)
node _taken_T_56 = and(_taken_T_51, _taken_T_55)
when _taken_T_56 :
connect updateBTB, UInt<1>(0h1)
node _taken_T_57 = and(fq.io.enq.ready, fq.io.enq.valid)
when _taken_T_57 :
connect s2_partial_insn_valid, UInt<1>(0h0)
node _taken_T_58 = eq(_taken_T_28, UInt<1>(0h0))
node _taken_T_59 = and(taken_valid_1, _taken_T_58)
node _taken_T_60 = eq(taken_rvc_1, UInt<1>(0h0))
node _taken_T_61 = and(_taken_T_59, _taken_T_60)
when _taken_T_61 :
connect s2_partial_insn_valid, UInt<1>(0h1)
node _taken_s2_partial_insn_T = or(taken_bits_1, UInt<2>(0h3))
connect s2_partial_insn, _taken_s2_partial_insn_T
node taken = or(_taken_T_28, taken_taken_1)
when useRAS :
connect predicted_npc, btb.io.ras_head.bits
node _T_26 = and(fq.io.enq.ready, fq.io.enq.valid)
node _T_27 = or(s2_btb_taken, taken)
node _T_28 = and(_T_26, _T_27)
when _T_28 :
connect s2_partial_insn_valid, UInt<1>(0h0)
node _T_29 = eq(s2_btb_taken, UInt<1>(0h0))
when _T_29 :
when taken :
connect fq.io.enq.bits.btb.bridx, taken_idx
connect fq.io.enq.bits.btb.taken, UInt<1>(0h1)
connect fq.io.enq.bits.btb.entry, UInt<5>(0h1c)
node _T_30 = and(fq.io.enq.ready, fq.io.enq.valid)
when _T_30 :
connect s2_redirect, UInt<1>(0h1)
node _T_31 = eq(s2_partial_insn_valid, UInt<1>(0h0))
node _T_32 = bits(fq.io.enq.bits.mask, 0, 0)
node _T_33 = or(_T_31, _T_32)
node _T_34 = asUInt(reset)
node _T_35 = eq(_T_34, UInt<1>(0h0))
when _T_35 :
node _T_36 = eq(_T_33, UInt<1>(0h0))
when _T_36 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Frontend.scala:345 assert(!s2_partial_insn_valid || fq.io.enq.bits.mask(0))\n") : printf_2
assert(clock, _T_33, UInt<1>(0h1), "") : assert_2
when s2_redirect :
connect s2_partial_insn_valid, UInt<1>(0h0)
when io.cpu.req.valid :
connect wrong_path, UInt<1>(0h0)
connect io.cpu.resp.bits, fq.io.deq.bits
connect io.cpu.resp.valid, fq.io.deq.valid
connect fq.io.deq.ready, io.cpu.resp.ready
reg gpa_valid : UInt<1>, clock
reg gpa : UInt<40>, clock
reg gpa_is_pte : UInt<1>, clock
node _T_37 = and(fq.io.enq.ready, fq.io.enq.valid)
node _T_38 = and(_T_37, s2_tlb_resp.gf.inst)
when _T_38 :
node _T_39 = eq(gpa_valid, UInt<1>(0h0))
when _T_39 :
connect gpa, s2_tlb_resp.gpa
connect gpa_is_pte, s2_tlb_resp.gpa_is_pte
connect gpa_valid, UInt<1>(0h1)
when io.cpu.req.valid :
connect gpa_valid, UInt<1>(0h0)
connect io.cpu.gpa.valid, gpa_valid
connect io.cpu.gpa.bits, gpa
connect io.cpu.gpa_is_pte, gpa_is_pte
connect io.cpu.perf.acquire, icache.io.perf.acquire
node _io_cpu_perf_tlbMiss_T = and(io.ptw.req.ready, io.ptw.req.valid)
connect io.cpu.perf.tlbMiss, _io_cpu_perf_tlbMiss_T
connect io.errors, icache.io.errors
node _clock_en_reg_T = eq(UInt<1>(0h0), UInt<1>(0h0))
node _clock_en_reg_T_1 = or(_clock_en_reg_T, io.cpu.might_request)
node _clock_en_reg_T_2 = or(_clock_en_reg_T_1, icache.io.keep_clock_enabled)
node _clock_en_reg_T_3 = or(_clock_en_reg_T_2, s1_valid)
node _clock_en_reg_T_4 = or(_clock_en_reg_T_3, s2_valid)
node _clock_en_reg_T_5 = eq(tlb.io.req.ready, UInt<1>(0h0))
node _clock_en_reg_T_6 = or(_clock_en_reg_T_4, _clock_en_reg_T_5)
node _clock_en_reg_T_7 = bits(fq.io.mask, 4, 4)
node _clock_en_reg_T_8 = eq(_clock_en_reg_T_7, UInt<1>(0h0))
node _clock_en_reg_T_9 = or(_clock_en_reg_T_6, _clock_en_reg_T_8)
connect clock_en_reg, _clock_en_reg_T_9 | module Frontend( // @[Frontend.scala:82:7]
input clock, // @[Frontend.scala:82:7]
input reset, // @[Frontend.scala:82:7]
input auto_icache_master_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_icache_master_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_icache_master_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_icache_master_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_icache_master_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_icache_master_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_icache_master_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_icache_master_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_icache_master_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_icache_master_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_icache_master_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input io_cpu_might_request, // @[Frontend.scala:85:14]
input io_cpu_req_valid, // @[Frontend.scala:85:14]
input [39:0] io_cpu_req_bits_pc, // @[Frontend.scala:85:14]
input io_cpu_req_bits_speculative, // @[Frontend.scala:85:14]
input io_cpu_sfence_valid, // @[Frontend.scala:85:14]
input io_cpu_sfence_bits_rs1, // @[Frontend.scala:85:14]
input io_cpu_sfence_bits_rs2, // @[Frontend.scala:85:14]
input [38:0] io_cpu_sfence_bits_addr, // @[Frontend.scala:85:14]
input io_cpu_sfence_bits_asid, // @[Frontend.scala:85:14]
input io_cpu_sfence_bits_hv, // @[Frontend.scala:85:14]
input io_cpu_sfence_bits_hg, // @[Frontend.scala:85:14]
input io_cpu_resp_ready, // @[Frontend.scala:85:14]
output io_cpu_resp_valid, // @[Frontend.scala:85:14]
output [1:0] io_cpu_resp_bits_btb_cfiType, // @[Frontend.scala:85:14]
output io_cpu_resp_bits_btb_taken, // @[Frontend.scala:85:14]
output [1:0] io_cpu_resp_bits_btb_mask, // @[Frontend.scala:85:14]
output io_cpu_resp_bits_btb_bridx, // @[Frontend.scala:85:14]
output [38:0] io_cpu_resp_bits_btb_target, // @[Frontend.scala:85:14]
output [4:0] io_cpu_resp_bits_btb_entry, // @[Frontend.scala:85:14]
output [7:0] io_cpu_resp_bits_btb_bht_history, // @[Frontend.scala:85:14]
output io_cpu_resp_bits_btb_bht_value, // @[Frontend.scala:85:14]
output [39:0] io_cpu_resp_bits_pc, // @[Frontend.scala:85:14]
output [31:0] io_cpu_resp_bits_data, // @[Frontend.scala:85:14]
output [1:0] io_cpu_resp_bits_mask, // @[Frontend.scala:85:14]
output io_cpu_resp_bits_xcpt_pf_inst, // @[Frontend.scala:85:14]
output io_cpu_resp_bits_xcpt_gf_inst, // @[Frontend.scala:85:14]
output io_cpu_resp_bits_xcpt_ae_inst, // @[Frontend.scala:85:14]
output io_cpu_resp_bits_replay, // @[Frontend.scala:85:14]
output io_cpu_gpa_valid, // @[Frontend.scala:85:14]
output [39:0] io_cpu_gpa_bits, // @[Frontend.scala:85:14]
output io_cpu_gpa_is_pte, // @[Frontend.scala:85:14]
input io_cpu_btb_update_valid, // @[Frontend.scala:85:14]
input [1:0] io_cpu_btb_update_bits_prediction_cfiType, // @[Frontend.scala:85:14]
input io_cpu_btb_update_bits_prediction_taken, // @[Frontend.scala:85:14]
input [1:0] io_cpu_btb_update_bits_prediction_mask, // @[Frontend.scala:85:14]
input io_cpu_btb_update_bits_prediction_bridx, // @[Frontend.scala:85:14]
input [38:0] io_cpu_btb_update_bits_prediction_target, // @[Frontend.scala:85:14]
input [4:0] io_cpu_btb_update_bits_prediction_entry, // @[Frontend.scala:85:14]
input [7:0] io_cpu_btb_update_bits_prediction_bht_history, // @[Frontend.scala:85:14]
input io_cpu_btb_update_bits_prediction_bht_value, // @[Frontend.scala:85:14]
input [38:0] io_cpu_btb_update_bits_pc, // @[Frontend.scala:85:14]
input [38:0] io_cpu_btb_update_bits_target, // @[Frontend.scala:85:14]
input io_cpu_btb_update_bits_isValid, // @[Frontend.scala:85:14]
input [38:0] io_cpu_btb_update_bits_br_pc, // @[Frontend.scala:85:14]
input [1:0] io_cpu_btb_update_bits_cfiType, // @[Frontend.scala:85:14]
input io_cpu_bht_update_valid, // @[Frontend.scala:85:14]
input [7:0] io_cpu_bht_update_bits_prediction_history, // @[Frontend.scala:85:14]
input io_cpu_bht_update_bits_prediction_value, // @[Frontend.scala:85:14]
input [38:0] io_cpu_bht_update_bits_pc, // @[Frontend.scala:85:14]
input io_cpu_bht_update_bits_branch, // @[Frontend.scala:85:14]
input io_cpu_bht_update_bits_taken, // @[Frontend.scala:85:14]
input io_cpu_bht_update_bits_mispredict, // @[Frontend.scala:85:14]
input io_cpu_flush_icache, // @[Frontend.scala:85:14]
output [39:0] io_cpu_npc, // @[Frontend.scala:85:14]
output io_cpu_perf_acquire, // @[Frontend.scala:85:14]
output io_cpu_perf_tlbMiss, // @[Frontend.scala:85:14]
input io_cpu_progress, // @[Frontend.scala:85:14]
input io_ptw_req_ready, // @[Frontend.scala:85:14]
output io_ptw_req_valid, // @[Frontend.scala:85:14]
output io_ptw_req_bits_valid, // @[Frontend.scala:85:14]
output [26:0] io_ptw_req_bits_bits_addr, // @[Frontend.scala:85:14]
output io_ptw_req_bits_bits_need_gpa, // @[Frontend.scala:85:14]
input io_ptw_resp_valid, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_ae_ptw, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_ae_final, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_pf, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_gf, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_hr, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_hw, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_hx, // @[Frontend.scala:85:14]
input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[Frontend.scala:85:14]
input [43:0] io_ptw_resp_bits_pte_ppn, // @[Frontend.scala:85:14]
input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_pte_d, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_pte_a, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_pte_g, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_pte_u, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_pte_x, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_pte_w, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_pte_r, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_pte_v, // @[Frontend.scala:85:14]
input [1:0] io_ptw_resp_bits_level, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_homogeneous, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_gpa_valid, // @[Frontend.scala:85:14]
input [38:0] io_ptw_resp_bits_gpa_bits, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_gpa_is_pte, // @[Frontend.scala:85:14]
input [3:0] io_ptw_ptbr_mode, // @[Frontend.scala:85:14]
input [43:0] io_ptw_ptbr_ppn, // @[Frontend.scala:85:14]
input io_ptw_status_debug, // @[Frontend.scala:85:14]
input io_ptw_status_cease, // @[Frontend.scala:85:14]
input io_ptw_status_wfi, // @[Frontend.scala:85:14]
input [31:0] io_ptw_status_isa, // @[Frontend.scala:85:14]
input [1:0] io_ptw_status_dprv, // @[Frontend.scala:85:14]
input io_ptw_status_dv, // @[Frontend.scala:85:14]
input [1:0] io_ptw_status_prv, // @[Frontend.scala:85:14]
input io_ptw_status_v, // @[Frontend.scala:85:14]
input io_ptw_status_mpv, // @[Frontend.scala:85:14]
input io_ptw_status_gva, // @[Frontend.scala:85:14]
input io_ptw_status_tsr, // @[Frontend.scala:85:14]
input io_ptw_status_tw, // @[Frontend.scala:85:14]
input io_ptw_status_tvm, // @[Frontend.scala:85:14]
input io_ptw_status_mxr, // @[Frontend.scala:85:14]
input io_ptw_status_sum, // @[Frontend.scala:85:14]
input io_ptw_status_mprv, // @[Frontend.scala:85:14]
input [1:0] io_ptw_status_fs, // @[Frontend.scala:85:14]
input [1:0] io_ptw_status_mpp, // @[Frontend.scala:85:14]
input io_ptw_status_spp, // @[Frontend.scala:85:14]
input io_ptw_status_mpie, // @[Frontend.scala:85:14]
input io_ptw_status_spie, // @[Frontend.scala:85:14]
input io_ptw_status_mie, // @[Frontend.scala:85:14]
input io_ptw_status_sie, // @[Frontend.scala:85:14]
input io_ptw_hstatus_spvp, // @[Frontend.scala:85:14]
input io_ptw_hstatus_spv, // @[Frontend.scala:85:14]
input io_ptw_hstatus_gva, // @[Frontend.scala:85:14]
input io_ptw_gstatus_debug, // @[Frontend.scala:85:14]
input io_ptw_gstatus_cease, // @[Frontend.scala:85:14]
input io_ptw_gstatus_wfi, // @[Frontend.scala:85:14]
input [31:0] io_ptw_gstatus_isa, // @[Frontend.scala:85:14]
input [1:0] io_ptw_gstatus_dprv, // @[Frontend.scala:85:14]
input io_ptw_gstatus_dv, // @[Frontend.scala:85:14]
input [1:0] io_ptw_gstatus_prv, // @[Frontend.scala:85:14]
input io_ptw_gstatus_v, // @[Frontend.scala:85:14]
input [22:0] io_ptw_gstatus_zero2, // @[Frontend.scala:85:14]
input io_ptw_gstatus_mpv, // @[Frontend.scala:85:14]
input io_ptw_gstatus_gva, // @[Frontend.scala:85:14]
input io_ptw_gstatus_mbe, // @[Frontend.scala:85:14]
input io_ptw_gstatus_sbe, // @[Frontend.scala:85:14]
input [1:0] io_ptw_gstatus_sxl, // @[Frontend.scala:85:14]
input [7:0] io_ptw_gstatus_zero1, // @[Frontend.scala:85:14]
input io_ptw_gstatus_tsr, // @[Frontend.scala:85:14]
input io_ptw_gstatus_tw, // @[Frontend.scala:85:14]
input io_ptw_gstatus_tvm, // @[Frontend.scala:85:14]
input io_ptw_gstatus_mxr, // @[Frontend.scala:85:14]
input io_ptw_gstatus_sum, // @[Frontend.scala:85:14]
input io_ptw_gstatus_mprv, // @[Frontend.scala:85:14]
input [1:0] io_ptw_gstatus_fs, // @[Frontend.scala:85:14]
input [1:0] io_ptw_gstatus_mpp, // @[Frontend.scala:85:14]
input [1:0] io_ptw_gstatus_vs, // @[Frontend.scala:85:14]
input io_ptw_gstatus_spp, // @[Frontend.scala:85:14]
input io_ptw_gstatus_mpie, // @[Frontend.scala:85:14]
input io_ptw_gstatus_ube, // @[Frontend.scala:85:14]
input io_ptw_gstatus_spie, // @[Frontend.scala:85:14]
input io_ptw_gstatus_upie, // @[Frontend.scala:85:14]
input io_ptw_gstatus_mie, // @[Frontend.scala:85:14]
input io_ptw_gstatus_hie, // @[Frontend.scala:85:14]
input io_ptw_gstatus_sie, // @[Frontend.scala:85:14]
input io_ptw_gstatus_uie, // @[Frontend.scala:85:14]
input io_ptw_pmp_0_cfg_l, // @[Frontend.scala:85:14]
input [1:0] io_ptw_pmp_0_cfg_a, // @[Frontend.scala:85:14]
input io_ptw_pmp_0_cfg_x, // @[Frontend.scala:85:14]
input io_ptw_pmp_0_cfg_w, // @[Frontend.scala:85:14]
input io_ptw_pmp_0_cfg_r, // @[Frontend.scala:85:14]
input [29:0] io_ptw_pmp_0_addr, // @[Frontend.scala:85:14]
input [31:0] io_ptw_pmp_0_mask, // @[Frontend.scala:85:14]
input io_ptw_pmp_1_cfg_l, // @[Frontend.scala:85:14]
input [1:0] io_ptw_pmp_1_cfg_a, // @[Frontend.scala:85:14]
input io_ptw_pmp_1_cfg_x, // @[Frontend.scala:85:14]
input io_ptw_pmp_1_cfg_w, // @[Frontend.scala:85:14]
input io_ptw_pmp_1_cfg_r, // @[Frontend.scala:85:14]
input [29:0] io_ptw_pmp_1_addr, // @[Frontend.scala:85:14]
input [31:0] io_ptw_pmp_1_mask, // @[Frontend.scala:85:14]
input io_ptw_pmp_2_cfg_l, // @[Frontend.scala:85:14]
input [1:0] io_ptw_pmp_2_cfg_a, // @[Frontend.scala:85:14]
input io_ptw_pmp_2_cfg_x, // @[Frontend.scala:85:14]
input io_ptw_pmp_2_cfg_w, // @[Frontend.scala:85:14]
input io_ptw_pmp_2_cfg_r, // @[Frontend.scala:85:14]
input [29:0] io_ptw_pmp_2_addr, // @[Frontend.scala:85:14]
input [31:0] io_ptw_pmp_2_mask, // @[Frontend.scala:85:14]
input io_ptw_pmp_3_cfg_l, // @[Frontend.scala:85:14]
input [1:0] io_ptw_pmp_3_cfg_a, // @[Frontend.scala:85:14]
input io_ptw_pmp_3_cfg_x, // @[Frontend.scala:85:14]
input io_ptw_pmp_3_cfg_w, // @[Frontend.scala:85:14]
input io_ptw_pmp_3_cfg_r, // @[Frontend.scala:85:14]
input [29:0] io_ptw_pmp_3_addr, // @[Frontend.scala:85:14]
input [31:0] io_ptw_pmp_3_mask, // @[Frontend.scala:85:14]
input io_ptw_pmp_4_cfg_l, // @[Frontend.scala:85:14]
input [1:0] io_ptw_pmp_4_cfg_a, // @[Frontend.scala:85:14]
input io_ptw_pmp_4_cfg_x, // @[Frontend.scala:85:14]
input io_ptw_pmp_4_cfg_w, // @[Frontend.scala:85:14]
input io_ptw_pmp_4_cfg_r, // @[Frontend.scala:85:14]
input [29:0] io_ptw_pmp_4_addr, // @[Frontend.scala:85:14]
input [31:0] io_ptw_pmp_4_mask, // @[Frontend.scala:85:14]
input io_ptw_pmp_5_cfg_l, // @[Frontend.scala:85:14]
input [1:0] io_ptw_pmp_5_cfg_a, // @[Frontend.scala:85:14]
input io_ptw_pmp_5_cfg_x, // @[Frontend.scala:85:14]
input io_ptw_pmp_5_cfg_w, // @[Frontend.scala:85:14]
input io_ptw_pmp_5_cfg_r, // @[Frontend.scala:85:14]
input [29:0] io_ptw_pmp_5_addr, // @[Frontend.scala:85:14]
input [31:0] io_ptw_pmp_5_mask, // @[Frontend.scala:85:14]
input io_ptw_pmp_6_cfg_l, // @[Frontend.scala:85:14]
input [1:0] io_ptw_pmp_6_cfg_a, // @[Frontend.scala:85:14]
input io_ptw_pmp_6_cfg_x, // @[Frontend.scala:85:14]
input io_ptw_pmp_6_cfg_w, // @[Frontend.scala:85:14]
input io_ptw_pmp_6_cfg_r, // @[Frontend.scala:85:14]
input [29:0] io_ptw_pmp_6_addr, // @[Frontend.scala:85:14]
input [31:0] io_ptw_pmp_6_mask, // @[Frontend.scala:85:14]
input io_ptw_pmp_7_cfg_l, // @[Frontend.scala:85:14]
input [1:0] io_ptw_pmp_7_cfg_a, // @[Frontend.scala:85:14]
input io_ptw_pmp_7_cfg_x, // @[Frontend.scala:85:14]
input io_ptw_pmp_7_cfg_w, // @[Frontend.scala:85:14]
input io_ptw_pmp_7_cfg_r, // @[Frontend.scala:85:14]
input [29:0] io_ptw_pmp_7_addr, // @[Frontend.scala:85:14]
input [31:0] io_ptw_pmp_7_mask, // @[Frontend.scala:85:14]
input io_ptw_customCSRs_csrs_0_ren, // @[Frontend.scala:85:14]
input io_ptw_customCSRs_csrs_0_wen, // @[Frontend.scala:85:14]
input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[Frontend.scala:85:14]
input [63:0] io_ptw_customCSRs_csrs_0_value, // @[Frontend.scala:85:14]
input io_ptw_customCSRs_csrs_1_ren, // @[Frontend.scala:85:14]
input io_ptw_customCSRs_csrs_1_wen, // @[Frontend.scala:85:14]
input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[Frontend.scala:85:14]
input [63:0] io_ptw_customCSRs_csrs_1_value, // @[Frontend.scala:85:14]
input io_ptw_customCSRs_csrs_2_ren, // @[Frontend.scala:85:14]
input io_ptw_customCSRs_csrs_2_wen, // @[Frontend.scala:85:14]
input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[Frontend.scala:85:14]
input [63:0] io_ptw_customCSRs_csrs_2_value, // @[Frontend.scala:85:14]
input io_ptw_customCSRs_csrs_3_ren, // @[Frontend.scala:85:14]
input io_ptw_customCSRs_csrs_3_wen, // @[Frontend.scala:85:14]
input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[Frontend.scala:85:14]
input [63:0] io_ptw_customCSRs_csrs_3_value // @[Frontend.scala:85:14]
);
wire [1:0] btb_io_ras_update_bits_cfiType; // @[Frontend.scala:270:25, :274:40]
wire _btb_io_resp_valid; // @[Frontend.scala:198:21]
wire [1:0] _btb_io_resp_bits_cfiType; // @[Frontend.scala:198:21]
wire _btb_io_resp_bits_taken; // @[Frontend.scala:198:21]
wire [1:0] _btb_io_resp_bits_mask; // @[Frontend.scala:198:21]
wire _btb_io_resp_bits_bridx; // @[Frontend.scala:198:21]
wire [38:0] _btb_io_resp_bits_target; // @[Frontend.scala:198:21]
wire [4:0] _btb_io_resp_bits_entry; // @[Frontend.scala:198:21]
wire [7:0] _btb_io_resp_bits_bht_history; // @[Frontend.scala:198:21]
wire _btb_io_resp_bits_bht_value; // @[Frontend.scala:198:21]
wire _btb_io_ras_head_valid; // @[Frontend.scala:198:21]
wire [38:0] _btb_io_ras_head_bits; // @[Frontend.scala:198:21]
wire _tlb_io_req_ready; // @[Frontend.scala:105:19]
wire _tlb_io_resp_miss; // @[Frontend.scala:105:19]
wire [31:0] _tlb_io_resp_paddr; // @[Frontend.scala:105:19]
wire [39:0] _tlb_io_resp_gpa; // @[Frontend.scala:105:19]
wire _tlb_io_resp_pf_ld; // @[Frontend.scala:105:19]
wire _tlb_io_resp_pf_inst; // @[Frontend.scala:105:19]
wire _tlb_io_resp_ae_ld; // @[Frontend.scala:105:19]
wire _tlb_io_resp_ae_inst; // @[Frontend.scala:105:19]
wire _tlb_io_resp_ma_ld; // @[Frontend.scala:105:19]
wire _tlb_io_resp_cacheable; // @[Frontend.scala:105:19]
wire _tlb_io_resp_prefetchable; // @[Frontend.scala:105:19]
wire _fq_io_enq_ready; // @[Frontend.scala:91:64]
wire [4:0] _fq_io_mask; // @[Frontend.scala:91:64]
wire _icache_io_resp_valid; // @[Frontend.scala:70:26]
wire [31:0] _icache_io_resp_bits_data; // @[Frontend.scala:70:26]
wire _icache_io_resp_bits_ae; // @[Frontend.scala:70:26]
wire auto_icache_master_out_a_ready_0 = auto_icache_master_out_a_ready; // @[Frontend.scala:82:7]
wire auto_icache_master_out_d_valid_0 = auto_icache_master_out_d_valid; // @[Frontend.scala:82:7]
wire [2:0] auto_icache_master_out_d_bits_opcode_0 = auto_icache_master_out_d_bits_opcode; // @[Frontend.scala:82:7]
wire [1:0] auto_icache_master_out_d_bits_param_0 = auto_icache_master_out_d_bits_param; // @[Frontend.scala:82:7]
wire [3:0] auto_icache_master_out_d_bits_size_0 = auto_icache_master_out_d_bits_size; // @[Frontend.scala:82:7]
wire [6:0] auto_icache_master_out_d_bits_sink_0 = auto_icache_master_out_d_bits_sink; // @[Frontend.scala:82:7]
wire auto_icache_master_out_d_bits_denied_0 = auto_icache_master_out_d_bits_denied; // @[Frontend.scala:82:7]
wire [127:0] auto_icache_master_out_d_bits_data_0 = auto_icache_master_out_d_bits_data; // @[Frontend.scala:82:7]
wire auto_icache_master_out_d_bits_corrupt_0 = auto_icache_master_out_d_bits_corrupt; // @[Frontend.scala:82:7]
wire io_cpu_might_request_0 = io_cpu_might_request; // @[Frontend.scala:82:7]
wire io_cpu_req_valid_0 = io_cpu_req_valid; // @[Frontend.scala:82:7]
wire [39:0] io_cpu_req_bits_pc_0 = io_cpu_req_bits_pc; // @[Frontend.scala:82:7]
wire io_cpu_req_bits_speculative_0 = io_cpu_req_bits_speculative; // @[Frontend.scala:82:7]
wire io_cpu_sfence_valid_0 = io_cpu_sfence_valid; // @[Frontend.scala:82:7]
wire io_cpu_sfence_bits_rs1_0 = io_cpu_sfence_bits_rs1; // @[Frontend.scala:82:7]
wire io_cpu_sfence_bits_rs2_0 = io_cpu_sfence_bits_rs2; // @[Frontend.scala:82:7]
wire [38:0] io_cpu_sfence_bits_addr_0 = io_cpu_sfence_bits_addr; // @[Frontend.scala:82:7]
wire io_cpu_sfence_bits_asid_0 = io_cpu_sfence_bits_asid; // @[Frontend.scala:82:7]
wire io_cpu_sfence_bits_hv_0 = io_cpu_sfence_bits_hv; // @[Frontend.scala:82:7]
wire io_cpu_sfence_bits_hg_0 = io_cpu_sfence_bits_hg; // @[Frontend.scala:82:7]
wire io_cpu_resp_ready_0 = io_cpu_resp_ready; // @[Frontend.scala:82:7]
wire io_cpu_btb_update_valid_0 = io_cpu_btb_update_valid; // @[Frontend.scala:82:7]
wire [1:0] io_cpu_btb_update_bits_prediction_cfiType_0 = io_cpu_btb_update_bits_prediction_cfiType; // @[Frontend.scala:82:7]
wire io_cpu_btb_update_bits_prediction_taken_0 = io_cpu_btb_update_bits_prediction_taken; // @[Frontend.scala:82:7]
wire [1:0] io_cpu_btb_update_bits_prediction_mask_0 = io_cpu_btb_update_bits_prediction_mask; // @[Frontend.scala:82:7]
wire io_cpu_btb_update_bits_prediction_bridx_0 = io_cpu_btb_update_bits_prediction_bridx; // @[Frontend.scala:82:7]
wire [38:0] io_cpu_btb_update_bits_prediction_target_0 = io_cpu_btb_update_bits_prediction_target; // @[Frontend.scala:82:7]
wire [4:0] io_cpu_btb_update_bits_prediction_entry_0 = io_cpu_btb_update_bits_prediction_entry; // @[Frontend.scala:82:7]
wire [7:0] io_cpu_btb_update_bits_prediction_bht_history_0 = io_cpu_btb_update_bits_prediction_bht_history; // @[Frontend.scala:82:7]
wire io_cpu_btb_update_bits_prediction_bht_value_0 = io_cpu_btb_update_bits_prediction_bht_value; // @[Frontend.scala:82:7]
wire [38:0] io_cpu_btb_update_bits_pc_0 = io_cpu_btb_update_bits_pc; // @[Frontend.scala:82:7]
wire [38:0] io_cpu_btb_update_bits_target_0 = io_cpu_btb_update_bits_target; // @[Frontend.scala:82:7]
wire io_cpu_btb_update_bits_isValid_0 = io_cpu_btb_update_bits_isValid; // @[Frontend.scala:82:7]
wire [38:0] io_cpu_btb_update_bits_br_pc_0 = io_cpu_btb_update_bits_br_pc; // @[Frontend.scala:82:7]
wire [1:0] io_cpu_btb_update_bits_cfiType_0 = io_cpu_btb_update_bits_cfiType; // @[Frontend.scala:82:7]
wire io_cpu_bht_update_valid_0 = io_cpu_bht_update_valid; // @[Frontend.scala:82:7]
wire [7:0] io_cpu_bht_update_bits_prediction_history_0 = io_cpu_bht_update_bits_prediction_history; // @[Frontend.scala:82:7]
wire io_cpu_bht_update_bits_prediction_value_0 = io_cpu_bht_update_bits_prediction_value; // @[Frontend.scala:82:7]
wire [38:0] io_cpu_bht_update_bits_pc_0 = io_cpu_bht_update_bits_pc; // @[Frontend.scala:82:7]
wire io_cpu_bht_update_bits_branch_0 = io_cpu_bht_update_bits_branch; // @[Frontend.scala:82:7]
wire io_cpu_bht_update_bits_taken_0 = io_cpu_bht_update_bits_taken; // @[Frontend.scala:82:7]
wire io_cpu_bht_update_bits_mispredict_0 = io_cpu_bht_update_bits_mispredict; // @[Frontend.scala:82:7]
wire io_cpu_flush_icache_0 = io_cpu_flush_icache; // @[Frontend.scala:82:7]
wire io_cpu_progress_0 = io_cpu_progress; // @[Frontend.scala:82:7]
wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[Frontend.scala:82:7]
wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[Frontend.scala:82:7]
wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[Frontend.scala:82:7]
wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[Frontend.scala:82:7]
wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[Frontend.scala:82:7]
wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[Frontend.scala:82:7]
wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[Frontend.scala:82:7]
wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[Frontend.scala:82:7]
wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[Frontend.scala:82:7]
wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[Frontend.scala:82:7]
wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[Frontend.scala:82:7]
wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[Frontend.scala:82:7]
wire io_ptw_status_v_0 = io_ptw_status_v; // @[Frontend.scala:82:7]
wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[Frontend.scala:82:7]
wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[Frontend.scala:82:7]
wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[Frontend.scala:82:7]
wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[Frontend.scala:82:7]
wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[Frontend.scala:82:7]
wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[Frontend.scala:82:7]
wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[Frontend.scala:82:7]
wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[Frontend.scala:82:7]
wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[Frontend.scala:82:7]
wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[Frontend.scala:82:7]
wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[Frontend.scala:82:7]
wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[Frontend.scala:82:7]
wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[Frontend.scala:82:7]
wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[Frontend.scala:82:7]
wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[Frontend.scala:82:7]
wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[Frontend.scala:82:7]
wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[Frontend.scala:82:7]
wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[Frontend.scala:82:7]
wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[Frontend.scala:82:7]
wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[Frontend.scala:82:7]
wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[Frontend.scala:82:7]
wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[Frontend.scala:82:7]
wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[Frontend.scala:82:7]
wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[Frontend.scala:82:7]
wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[Frontend.scala:82:7]
wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[Frontend.scala:82:7]
wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[Frontend.scala:82:7]
wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[Frontend.scala:82:7]
wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[Frontend.scala:82:7]
wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[Frontend.scala:82:7]
wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[Frontend.scala:82:7]
wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[Frontend.scala:82:7]
wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[Frontend.scala:82:7]
wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[Frontend.scala:82:7]
wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[Frontend.scala:82:7]
wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[Frontend.scala:82:7]
wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[Frontend.scala:82:7]
wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[Frontend.scala:82:7]
wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[Frontend.scala:82:7]
wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[Frontend.scala:82:7]
wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[Frontend.scala:82:7]
wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[Frontend.scala:82:7]
wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[Frontend.scala:82:7]
wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[Frontend.scala:82:7]
wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[Frontend.scala:82:7]
wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[Frontend.scala:82:7]
wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[Frontend.scala:82:7]
wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[Frontend.scala:82:7]
wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[Frontend.scala:82:7]
wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[Frontend.scala:82:7]
wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[Frontend.scala:82:7]
wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[Frontend.scala:82:7]
wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[Frontend.scala:82:7]
wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[Frontend.scala:82:7]
wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[Frontend.scala:82:7]
wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[Frontend.scala:82:7]
wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[Frontend.scala:82:7]
wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[Frontend.scala:82:7]
wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[Frontend.scala:82:7]
wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[Frontend.scala:82:7]
wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[Frontend.scala:82:7]
wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[Frontend.scala:82:7]
wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[Frontend.scala:82:7]
wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[Frontend.scala:82:7]
wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[Frontend.scala:82:7]
wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[Frontend.scala:82:7]
wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[Frontend.scala:82:7]
wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[Frontend.scala:82:7]
wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[Frontend.scala:82:7]
wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[Frontend.scala:82:7]
wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[Frontend.scala:82:7]
wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[Frontend.scala:82:7]
wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[Frontend.scala:82:7]
wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[Frontend.scala:82:7]
wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[Frontend.scala:82:7]
wire auto_icache_master_out_d_ready = 1'h1; // @[Frontend.scala:82:7]
wire io_cpu_clock_enabled = 1'h1; // @[Frontend.scala:82:7]
wire io_ptw_status_sd = 1'h1; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_sd = 1'h1; // @[Frontend.scala:82:7]
wire clock_en = 1'h1; // @[Frontend.scala:94:31]
wire _taken_rviImm_b19_12_T = 1'h1; // @[RocketCore.scala:1343:26]
wire _taken_rviImm_b11_T_3 = 1'h1; // @[RocketCore.scala:1345:23]
wire _taken_rviImm_b19_12_T_5 = 1'h1; // @[RocketCore.scala:1343:26]
wire _taken_rviImm_b19_12_T_6 = 1'h1; // @[RocketCore.scala:1343:43]
wire _taken_rviImm_b19_12_T_7 = 1'h1; // @[RocketCore.scala:1343:36]
wire _taken_rviImm_b11_T_17 = 1'h1; // @[RocketCore.scala:1346:23]
wire _taken_rviImm_b4_1_T_12 = 1'h1; // @[RocketCore.scala:1349:41]
wire _taken_rviImm_b4_1_T_13 = 1'h1; // @[RocketCore.scala:1349:34]
wire _taken_T_6 = 1'h1; // @[Frontend.scala:270:13]
wire _taken_btb_io_ras_update_bits_cfiType_T_3 = 1'h1; // @[Frontend.scala:276:85]
wire _taken_rviImm_b19_12_T_10 = 1'h1; // @[RocketCore.scala:1343:26]
wire _taken_rviImm_b11_T_25 = 1'h1; // @[RocketCore.scala:1345:23]
wire _taken_rviImm_b19_12_T_15 = 1'h1; // @[RocketCore.scala:1343:26]
wire _taken_rviImm_b19_12_T_16 = 1'h1; // @[RocketCore.scala:1343:43]
wire _taken_rviImm_b19_12_T_17 = 1'h1; // @[RocketCore.scala:1343:36]
wire _taken_rviImm_b11_T_39 = 1'h1; // @[RocketCore.scala:1346:23]
wire _taken_rviImm_b4_1_T_32 = 1'h1; // @[RocketCore.scala:1349:41]
wire _taken_rviImm_b4_1_T_33 = 1'h1; // @[RocketCore.scala:1349:34]
wire _taken_btb_io_ras_update_bits_cfiType_T_11 = 1'h1; // @[Frontend.scala:276:85]
wire _clock_en_reg_T = 1'h1; // @[Frontend.scala:376:19]
wire _clock_en_reg_T_1 = 1'h1; // @[Frontend.scala:376:45]
wire _clock_en_reg_T_2 = 1'h1; // @[Frontend.scala:377:26]
wire _clock_en_reg_T_3 = 1'h1; // @[Frontend.scala:378:34]
wire _clock_en_reg_T_4 = 1'h1; // @[Frontend.scala:379:14]
wire _clock_en_reg_T_6 = 1'h1; // @[Frontend.scala:379:26]
wire _clock_en_reg_T_9 = 1'h1; // @[Frontend.scala:380:23]
wire auto_icache_master_out_a_bits_source = 1'h0; // @[Frontend.scala:82:7]
wire auto_icache_master_out_a_bits_corrupt = 1'h0; // @[Frontend.scala:82:7]
wire auto_icache_master_out_d_bits_source = 1'h0; // @[Frontend.scala:82:7]
wire io_cpu_btb_update_bits_taken = 1'h0; // @[Frontend.scala:82:7]
wire io_cpu_ras_update_valid = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_status_mbe = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_status_sbe = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_status_sd_rv32 = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_status_ube = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_status_upie = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_status_hie = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_status_uie = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_hstatus_vtsr = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_hstatus_vtw = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_hstatus_vtvm = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_hstatus_hu = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_hstatus_vsbe = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[Frontend.scala:82:7]
wire taken_rvcJAL = 1'h0; // @[Frontend.scala:245:35]
wire _taken_rviImm_sign_T = 1'h0; // @[RocketCore.scala:1341:24]
wire _taken_rviImm_b30_20_T = 1'h0; // @[RocketCore.scala:1342:26]
wire _taken_rviImm_b19_12_T_1 = 1'h0; // @[RocketCore.scala:1343:43]
wire _taken_rviImm_b19_12_T_2 = 1'h0; // @[RocketCore.scala:1343:36]
wire _taken_rviImm_b11_T = 1'h0; // @[RocketCore.scala:1344:23]
wire _taken_rviImm_b11_T_1 = 1'h0; // @[RocketCore.scala:1344:40]
wire _taken_rviImm_b11_T_2 = 1'h0; // @[RocketCore.scala:1344:33]
wire _taken_rviImm_b11_T_6 = 1'h0; // @[RocketCore.scala:1346:23]
wire _taken_rviImm_b10_5_T = 1'h0; // @[RocketCore.scala:1347:25]
wire _taken_rviImm_b10_5_T_1 = 1'h0; // @[RocketCore.scala:1347:42]
wire _taken_rviImm_b10_5_T_2 = 1'h0; // @[RocketCore.scala:1347:35]
wire _taken_rviImm_b4_1_T = 1'h0; // @[RocketCore.scala:1348:24]
wire _taken_rviImm_b4_1_T_1 = 1'h0; // @[RocketCore.scala:1349:24]
wire _taken_rviImm_b4_1_T_2 = 1'h0; // @[RocketCore.scala:1349:41]
wire _taken_rviImm_b4_1_T_3 = 1'h0; // @[RocketCore.scala:1349:34]
wire _taken_rviImm_b4_1_T_5 = 1'h0; // @[RocketCore.scala:1350:24]
wire _taken_rviImm_b0_T = 1'h0; // @[RocketCore.scala:1351:22]
wire _taken_rviImm_b0_T_2 = 1'h0; // @[RocketCore.scala:1352:22]
wire _taken_rviImm_b0_T_4 = 1'h0; // @[RocketCore.scala:1353:22]
wire _taken_rviImm_b0_T_6 = 1'h0; // @[RocketCore.scala:1353:17]
wire _taken_rviImm_b0_T_7 = 1'h0; // @[RocketCore.scala:1352:17]
wire taken_rviImm_b0 = 1'h0; // @[RocketCore.scala:1351:17]
wire _taken_rviImm_sign_T_3 = 1'h0; // @[RocketCore.scala:1341:24]
wire _taken_rviImm_b30_20_T_3 = 1'h0; // @[RocketCore.scala:1342:26]
wire _taken_rviImm_b11_T_11 = 1'h0; // @[RocketCore.scala:1344:23]
wire _taken_rviImm_b11_T_12 = 1'h0; // @[RocketCore.scala:1344:40]
wire _taken_rviImm_b11_T_13 = 1'h0; // @[RocketCore.scala:1344:33]
wire _taken_rviImm_b11_T_14 = 1'h0; // @[RocketCore.scala:1345:23]
wire _taken_rviImm_b10_5_T_4 = 1'h0; // @[RocketCore.scala:1347:25]
wire _taken_rviImm_b10_5_T_5 = 1'h0; // @[RocketCore.scala:1347:42]
wire _taken_rviImm_b10_5_T_6 = 1'h0; // @[RocketCore.scala:1347:35]
wire _taken_rviImm_b4_1_T_10 = 1'h0; // @[RocketCore.scala:1348:24]
wire _taken_rviImm_b4_1_T_11 = 1'h0; // @[RocketCore.scala:1349:24]
wire _taken_rviImm_b4_1_T_15 = 1'h0; // @[RocketCore.scala:1350:24]
wire _taken_rviImm_b0_T_8 = 1'h0; // @[RocketCore.scala:1351:22]
wire _taken_rviImm_b0_T_10 = 1'h0; // @[RocketCore.scala:1352:22]
wire _taken_rviImm_b0_T_12 = 1'h0; // @[RocketCore.scala:1353:22]
wire _taken_rviImm_b0_T_14 = 1'h0; // @[RocketCore.scala:1353:17]
wire _taken_rviImm_b0_T_15 = 1'h0; // @[RocketCore.scala:1352:17]
wire taken_rviImm_b0_1 = 1'h0; // @[RocketCore.scala:1351:17]
wire taken_rvcJAL_1 = 1'h0; // @[Frontend.scala:245:35]
wire _taken_rviImm_sign_T_6 = 1'h0; // @[RocketCore.scala:1341:24]
wire _taken_rviImm_b30_20_T_6 = 1'h0; // @[RocketCore.scala:1342:26]
wire _taken_rviImm_b19_12_T_11 = 1'h0; // @[RocketCore.scala:1343:43]
wire _taken_rviImm_b19_12_T_12 = 1'h0; // @[RocketCore.scala:1343:36]
wire _taken_rviImm_b11_T_22 = 1'h0; // @[RocketCore.scala:1344:23]
wire _taken_rviImm_b11_T_23 = 1'h0; // @[RocketCore.scala:1344:40]
wire _taken_rviImm_b11_T_24 = 1'h0; // @[RocketCore.scala:1344:33]
wire _taken_rviImm_b11_T_28 = 1'h0; // @[RocketCore.scala:1346:23]
wire _taken_rviImm_b10_5_T_8 = 1'h0; // @[RocketCore.scala:1347:25]
wire _taken_rviImm_b10_5_T_9 = 1'h0; // @[RocketCore.scala:1347:42]
wire _taken_rviImm_b10_5_T_10 = 1'h0; // @[RocketCore.scala:1347:35]
wire _taken_rviImm_b4_1_T_20 = 1'h0; // @[RocketCore.scala:1348:24]
wire _taken_rviImm_b4_1_T_21 = 1'h0; // @[RocketCore.scala:1349:24]
wire _taken_rviImm_b4_1_T_22 = 1'h0; // @[RocketCore.scala:1349:41]
wire _taken_rviImm_b4_1_T_23 = 1'h0; // @[RocketCore.scala:1349:34]
wire _taken_rviImm_b4_1_T_25 = 1'h0; // @[RocketCore.scala:1350:24]
wire _taken_rviImm_b0_T_16 = 1'h0; // @[RocketCore.scala:1351:22]
wire _taken_rviImm_b0_T_18 = 1'h0; // @[RocketCore.scala:1352:22]
wire _taken_rviImm_b0_T_20 = 1'h0; // @[RocketCore.scala:1353:22]
wire _taken_rviImm_b0_T_22 = 1'h0; // @[RocketCore.scala:1353:17]
wire _taken_rviImm_b0_T_23 = 1'h0; // @[RocketCore.scala:1352:17]
wire taken_rviImm_b0_2 = 1'h0; // @[RocketCore.scala:1351:17]
wire _taken_rviImm_sign_T_9 = 1'h0; // @[RocketCore.scala:1341:24]
wire _taken_rviImm_b30_20_T_9 = 1'h0; // @[RocketCore.scala:1342:26]
wire _taken_rviImm_b11_T_33 = 1'h0; // @[RocketCore.scala:1344:23]
wire _taken_rviImm_b11_T_34 = 1'h0; // @[RocketCore.scala:1344:40]
wire _taken_rviImm_b11_T_35 = 1'h0; // @[RocketCore.scala:1344:33]
wire _taken_rviImm_b11_T_36 = 1'h0; // @[RocketCore.scala:1345:23]
wire _taken_rviImm_b10_5_T_12 = 1'h0; // @[RocketCore.scala:1347:25]
wire _taken_rviImm_b10_5_T_13 = 1'h0; // @[RocketCore.scala:1347:42]
wire _taken_rviImm_b10_5_T_14 = 1'h0; // @[RocketCore.scala:1347:35]
wire _taken_rviImm_b4_1_T_30 = 1'h0; // @[RocketCore.scala:1348:24]
wire _taken_rviImm_b4_1_T_31 = 1'h0; // @[RocketCore.scala:1349:24]
wire _taken_rviImm_b4_1_T_35 = 1'h0; // @[RocketCore.scala:1350:24]
wire _taken_rviImm_b0_T_24 = 1'h0; // @[RocketCore.scala:1351:22]
wire _taken_rviImm_b0_T_26 = 1'h0; // @[RocketCore.scala:1352:22]
wire _taken_rviImm_b0_T_28 = 1'h0; // @[RocketCore.scala:1353:22]
wire _taken_rviImm_b0_T_30 = 1'h0; // @[RocketCore.scala:1353:17]
wire _taken_rviImm_b0_T_31 = 1'h0; // @[RocketCore.scala:1352:17]
wire taken_rviImm_b0_3 = 1'h0; // @[RocketCore.scala:1351:17]
wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[Frontend.scala:82:7]
wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[Frontend.scala:82:7]
wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[Frontend.scala:82:7]
wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[Frontend.scala:82:7]
wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[Frontend.scala:82:7]
wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[Frontend.scala:82:7]
wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[Frontend.scala:82:7]
wire [22:0] io_ptw_status_zero2 = 23'h0; // @[Frontend.scala:82:7]
wire [7:0] io_ptw_status_zero1 = 8'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_status_xs = 2'h3; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_gstatus_xs = 2'h3; // @[Frontend.scala:82:7]
wire [1:0] io_cpu_ras_update_bits_cfiType = 2'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_status_vs = 2'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[Frontend.scala:82:7]
wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[Frontend.scala:82:7]
wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[Frontend.scala:82:7]
wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[Frontend.scala:82:7]
wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_status_sxl = 2'h2; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_status_uxl = 2'h2; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[Frontend.scala:82:7]
wire [2:0] auto_icache_master_out_a_bits_opcode = 3'h4; // @[Frontend.scala:82:7]
wire [2:0] auto_icache_master_out_a_bits_param = 3'h0; // @[Frontend.scala:82:7]
wire [3:0] auto_icache_master_out_a_bits_size = 4'h6; // @[Frontend.scala:82:7]
wire [15:0] auto_icache_master_out_a_bits_mask = 16'hFFFF; // @[Frontend.scala:82:7]
wire [127:0] auto_icache_master_out_a_bits_data = 128'h0; // @[Frontend.scala:82:7]
wire [31:0] auto_reset_vector_sink_in = 32'h10000; // @[Frontend.scala:82:7]
wire [31:0] resetVectorSinkNodeIn = 32'h10000; // @[MixedNode.scala:551:17]
wire [31:0] _s2_pc_T_2 = 32'h10000; // @[Frontend.scala:384:27]
wire [38:0] io_cpu_ras_update_bits_returnAddr = 39'h0; // @[Frontend.scala:82:7]
wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[Frontend.scala:82:7]
wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[Frontend.scala:82:7]
wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[Frontend.scala:82:7]
wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[Frontend.scala:82:7]
wire [31:0] _s2_pc_T = 32'hFFFEFFFF; // @[Frontend.scala:384:29]
wire [31:0] _s2_pc_T_1 = 32'hFFFEFFFF; // @[Frontend.scala:384:33]
wire [39:0] _io_cpu_npc_T_3; // @[Frontend.scala:384:27]
wire _io_cpu_perf_tlbMiss_T; // @[Decoupled.scala:51:35]
wire [31:0] auto_icache_master_out_a_bits_address_0; // @[Frontend.scala:82:7]
wire auto_icache_master_out_a_valid_0; // @[Frontend.scala:82:7]
wire [7:0] io_cpu_resp_bits_btb_bht_history_0; // @[Frontend.scala:82:7]
wire io_cpu_resp_bits_btb_bht_value_0; // @[Frontend.scala:82:7]
wire [1:0] io_cpu_resp_bits_btb_cfiType_0; // @[Frontend.scala:82:7]
wire io_cpu_resp_bits_btb_taken_0; // @[Frontend.scala:82:7]
wire [1:0] io_cpu_resp_bits_btb_mask_0; // @[Frontend.scala:82:7]
wire io_cpu_resp_bits_btb_bridx_0; // @[Frontend.scala:82:7]
wire [38:0] io_cpu_resp_bits_btb_target_0; // @[Frontend.scala:82:7]
wire [4:0] io_cpu_resp_bits_btb_entry_0; // @[Frontend.scala:82:7]
wire io_cpu_resp_bits_xcpt_pf_inst_0; // @[Frontend.scala:82:7]
wire io_cpu_resp_bits_xcpt_gf_inst_0; // @[Frontend.scala:82:7]
wire io_cpu_resp_bits_xcpt_ae_inst_0; // @[Frontend.scala:82:7]
wire [39:0] io_cpu_resp_bits_pc_0; // @[Frontend.scala:82:7]
wire [31:0] io_cpu_resp_bits_data_0; // @[Frontend.scala:82:7]
wire [1:0] io_cpu_resp_bits_mask_0; // @[Frontend.scala:82:7]
wire io_cpu_resp_bits_replay_0; // @[Frontend.scala:82:7]
wire io_cpu_resp_valid_0; // @[Frontend.scala:82:7]
wire io_cpu_gpa_valid_0; // @[Frontend.scala:82:7]
wire [39:0] io_cpu_gpa_bits_0; // @[Frontend.scala:82:7]
wire io_cpu_perf_acquire_0; // @[Frontend.scala:82:7]
wire io_cpu_perf_tlbMiss_0; // @[Frontend.scala:82:7]
wire io_cpu_gpa_is_pte_0; // @[Frontend.scala:82:7]
wire [39:0] io_cpu_npc_0; // @[Frontend.scala:82:7]
wire [26:0] io_ptw_req_bits_bits_addr_0; // @[Frontend.scala:82:7]
wire io_ptw_req_bits_bits_need_gpa_0; // @[Frontend.scala:82:7]
wire io_ptw_req_bits_valid_0; // @[Frontend.scala:82:7]
wire io_ptw_req_valid_0; // @[Frontend.scala:82:7]
wire io_errors_bus_valid; // @[Frontend.scala:82:7]
wire [31:0] io_errors_bus_bits; // @[Frontend.scala:82:7]
reg s1_valid; // @[Frontend.scala:107:21]
reg s2_valid; // @[Frontend.scala:108:25]
wire _s0_fq_has_space_T = _fq_io_mask[2]; // @[Frontend.scala:91:64, :110:16]
wire _s0_fq_has_space_T_1 = ~_s0_fq_has_space_T; // @[Frontend.scala:110:{5,16}]
wire _s0_fq_has_space_T_2 = _fq_io_mask[3]; // @[Frontend.scala:91:64, :111:17]
wire _s0_fq_has_space_T_3 = ~_s0_fq_has_space_T_2; // @[Frontend.scala:111:{6,17}]
wire _s0_fq_has_space_T_4 = ~s1_valid; // @[Frontend.scala:107:21, :111:45]
wire _s0_fq_has_space_T_5 = ~s2_valid; // @[Frontend.scala:108:25, :111:58]
wire _s0_fq_has_space_T_6 = _s0_fq_has_space_T_4 | _s0_fq_has_space_T_5; // @[Frontend.scala:111:{45,55,58}]
wire _s0_fq_has_space_T_7 = _s0_fq_has_space_T_3 & _s0_fq_has_space_T_6; // @[Frontend.scala:111:{6,41,55}]
wire _s0_fq_has_space_T_8 = _s0_fq_has_space_T_1 | _s0_fq_has_space_T_7; // @[Frontend.scala:110:{5,40}, :111:41]
wire _s0_fq_has_space_T_9 = _fq_io_mask[4]; // @[Frontend.scala:91:64, :112:17]
wire _clock_en_reg_T_7 = _fq_io_mask[4]; // @[Frontend.scala:91:64, :112:17, :381:16]
wire _s0_fq_has_space_T_10 = ~_s0_fq_has_space_T_9; // @[Frontend.scala:112:{6,17}]
wire _s0_fq_has_space_T_11 = ~s1_valid; // @[Frontend.scala:107:21, :111:45, :112:45]
wire _s0_fq_has_space_T_12 = ~s2_valid; // @[Frontend.scala:108:25, :111:58, :112:58]
wire _s0_fq_has_space_T_13 = _s0_fq_has_space_T_11 & _s0_fq_has_space_T_12; // @[Frontend.scala:112:{45,55,58}]
wire _s0_fq_has_space_T_14 = _s0_fq_has_space_T_10 & _s0_fq_has_space_T_13; // @[Frontend.scala:112:{6,41,55}]
wire s0_fq_has_space = _s0_fq_has_space_T_8 | _s0_fq_has_space_T_14; // @[Frontend.scala:110:40, :111:70, :112:41]
wire s0_valid = io_cpu_req_valid_0 | s0_fq_has_space; // @[Frontend.scala:82:7, :111:70, :113:35]
reg [39:0] s1_pc; // @[Frontend.scala:115:18]
reg s1_speculative; // @[Frontend.scala:116:27]
reg [39:0] s2_pc; // @[Frontend.scala:117:22]
reg s2_btb_resp_valid; // @[Frontend.scala:118:44]
reg [1:0] s2_btb_resp_bits_cfiType; // @[Frontend.scala:119:29]
reg s2_btb_resp_bits_taken; // @[Frontend.scala:119:29]
reg [1:0] s2_btb_resp_bits_mask; // @[Frontend.scala:119:29]
reg s2_btb_resp_bits_bridx; // @[Frontend.scala:119:29]
wire _taken_T_30 = s2_btb_resp_bits_bridx; // @[Frontend.scala:119:29, :261:69]
reg [38:0] s2_btb_resp_bits_target; // @[Frontend.scala:119:29]
reg [4:0] s2_btb_resp_bits_entry; // @[Frontend.scala:119:29]
reg [7:0] s2_btb_resp_bits_bht_history; // @[Frontend.scala:119:29]
reg s2_btb_resp_bits_bht_value; // @[Frontend.scala:119:29]
wire _taken_predict_taken_T = s2_btb_resp_bits_bht_value; // @[Frontend.scala:119:29]
wire _taken_T_23 = s2_btb_resp_bits_bht_value; // @[Frontend.scala:119:29]
wire _taken_predict_taken_T_1 = s2_btb_resp_bits_bht_value; // @[Frontend.scala:119:29]
wire _taken_T_52 = s2_btb_resp_bits_bht_value; // @[Frontend.scala:119:29]
wire s2_btb_taken = s2_btb_resp_valid & s2_btb_resp_bits_taken; // @[Frontend.scala:118:44, :119:29, :120:40]
reg s2_tlb_resp_miss; // @[Frontend.scala:121:24]
reg [31:0] s2_tlb_resp_paddr; // @[Frontend.scala:121:24]
reg [39:0] s2_tlb_resp_gpa; // @[Frontend.scala:121:24]
reg s2_tlb_resp_pf_ld; // @[Frontend.scala:121:24]
reg s2_tlb_resp_pf_inst; // @[Frontend.scala:121:24]
reg s2_tlb_resp_ae_ld; // @[Frontend.scala:121:24]
reg s2_tlb_resp_ae_inst; // @[Frontend.scala:121:24]
reg s2_tlb_resp_ma_ld; // @[Frontend.scala:121:24]
reg s2_tlb_resp_cacheable; // @[Frontend.scala:121:24]
reg s2_tlb_resp_prefetchable; // @[Frontend.scala:121:24]
wire _s2_xcpt_T = s2_tlb_resp_ae_inst | s2_tlb_resp_pf_inst; // @[Frontend.scala:121:24, :122:37]
wire s2_xcpt = _s2_xcpt_T; // @[Frontend.scala:122:{37,60}]
reg s2_speculative; // @[Frontend.scala:123:31]
reg s2_partial_insn_valid; // @[Frontend.scala:124:38]
reg [15:0] s2_partial_insn; // @[Frontend.scala:125:28]
reg wrong_path; // @[Frontend.scala:126:27]
wire [39:0] _s1_base_pc_T = ~s1_pc; // @[Frontend.scala:115:18, :128:22]
wire [39:0] _s1_base_pc_T_1 = {_s1_base_pc_T[39:2], 2'h3}; // @[Frontend.scala:128:{22,29}]
wire [39:0] s1_base_pc = ~_s1_base_pc_T_1; // @[Frontend.scala:128:{20,29}]
wire [40:0] _ntpc_T = {1'h0, s1_base_pc} + 41'h4; // @[Frontend.scala:128:20, :129:25]
wire [39:0] ntpc = _ntpc_T[39:0]; // @[Frontend.scala:129:25]
wire [39:0] predicted_npc; // @[Frontend.scala:130:34]
wire predicted_taken; // @[Frontend.scala:131:36]
wire _s2_replay_T_5; // @[Frontend.scala:134:46]
wire s2_replay; // @[Frontend.scala:133:23]
wire _fq_io_enq_valid_T_6; // @[Frontend.scala:184:52]
wire _T_37 = _fq_io_enq_ready & _fq_io_enq_valid_T_6; // @[Decoupled.scala:51:35]
wire _s2_replay_T; // @[Decoupled.scala:51:35]
assign _s2_replay_T = _T_37; // @[Decoupled.scala:51:35]
wire _btb_io_btb_update_valid_T; // @[Decoupled.scala:51:35]
assign _btb_io_btb_update_valid_T = _T_37; // @[Decoupled.scala:51:35]
wire _taken_btb_io_ras_update_valid_T; // @[Decoupled.scala:51:35]
assign _taken_btb_io_ras_update_valid_T = _T_37; // @[Decoupled.scala:51:35]
wire _taken_T_8; // @[Decoupled.scala:51:35]
assign _taken_T_8 = _T_37; // @[Decoupled.scala:51:35]
wire _taken_btb_io_bht_advance_valid_T; // @[Decoupled.scala:51:35]
assign _taken_btb_io_bht_advance_valid_T = _T_37; // @[Decoupled.scala:51:35]
wire _taken_btb_io_ras_update_valid_T_9; // @[Decoupled.scala:51:35]
assign _taken_btb_io_ras_update_valid_T_9 = _T_37; // @[Decoupled.scala:51:35]
wire _taken_T_37; // @[Decoupled.scala:51:35]
assign _taken_T_37 = _T_37; // @[Decoupled.scala:51:35]
wire _taken_btb_io_bht_advance_valid_T_3; // @[Decoupled.scala:51:35]
assign _taken_btb_io_bht_advance_valid_T_3 = _T_37; // @[Decoupled.scala:51:35]
wire _taken_T_57; // @[Decoupled.scala:51:35]
assign _taken_T_57 = _T_37; // @[Decoupled.scala:51:35]
wire _s2_replay_T_1 = ~_s2_replay_T; // @[Decoupled.scala:51:35]
wire _s2_replay_T_2 = s2_valid & _s2_replay_T_1; // @[Frontend.scala:108:25, :134:{26,29}]
wire _s2_replay_T_3 = ~s0_valid; // @[Frontend.scala:113:35, :134:70]
wire _s2_replay_T_4 = s2_replay & _s2_replay_T_3; // @[Frontend.scala:133:23, :134:{67,70}]
reg s2_replay_REG; // @[Frontend.scala:134:56]
assign _s2_replay_T_5 = _s2_replay_T_2 | s2_replay_REG; // @[Frontend.scala:134:{26,46,56}]
assign s2_replay = _s2_replay_T_5; // @[Frontend.scala:133:23, :134:46]
wire [39:0] npc = s2_replay ? s2_pc : predicted_npc; // @[Frontend.scala:117:22, :130:34, :133:23, :135:16]
wire _s0_speculative_T = ~s2_speculative; // @[Frontend.scala:123:31, :141:56]
wire _s0_speculative_T_1 = s2_valid & _s0_speculative_T; // @[Frontend.scala:108:25, :141:{53,56}]
wire _s0_speculative_T_2 = s1_speculative | _s0_speculative_T_1; // @[Frontend.scala:116:27, :141:{41,53}]
wire s0_speculative = _s0_speculative_T_2 | predicted_taken; // @[Frontend.scala:131:36, :141:{41,72}]
wire _s1_speculative_T = s2_replay ? s2_speculative : s0_speculative; // @[Frontend.scala:123:31, :133:23, :141:72, :143:75]
wire _s1_speculative_T_1 = io_cpu_req_valid_0 ? io_cpu_req_bits_speculative_0 : _s1_speculative_T; // @[Frontend.scala:82:7, :143:{24,75}]
wire s2_redirect; // @[Frontend.scala:145:32]
wire _s2_valid_T = ~s2_redirect; // @[Frontend.scala:145:32, :148:17]
reg [1:0] recent_progress_counter; // @[Frontend.scala:155:40]
wire recent_progress = |recent_progress_counter; // @[Frontend.scala:155:40, :156:49]
assign _io_cpu_perf_tlbMiss_T = io_ptw_req_ready_0 & io_ptw_req_valid_0; // @[Decoupled.scala:51:35]
wire [2:0] _recent_progress_counter_T = {1'h0, recent_progress_counter} - 3'h1; // @[Frontend.scala:155:40, :157:97]
wire [1:0] _recent_progress_counter_T_1 = _recent_progress_counter_T[1:0]; // @[Frontend.scala:157:97]
wire _s2_kill_speculative_tlb_refill_T = ~recent_progress; // @[Frontend.scala:156:49, :160:58]
wire s2_kill_speculative_tlb_refill = s2_speculative & _s2_kill_speculative_tlb_refill_T; // @[Frontend.scala:123:31, :160:{55,58}]
wire _tlb_io_req_valid_T = ~s2_replay; // @[Frontend.scala:133:23, :147:9, :163:35]
wire _tlb_io_req_valid_T_1 = s1_valid & _tlb_io_req_valid_T; // @[Frontend.scala:107:21, :163:{32,35}]
wire _tlb_io_kill_T = ~s2_valid; // @[Frontend.scala:108:25, :111:58, :171:18]
wire _tlb_io_kill_T_1 = _tlb_io_kill_T | s2_kill_speculative_tlb_refill; // @[Frontend.scala:160:55, :171:{18,28}]
wire _icache_io_s1_kill_T = s2_redirect | _tlb_io_resp_miss; // @[Frontend.scala:105:19, :145:32, :178:36]
wire _icache_io_s1_kill_T_1 = _icache_io_s1_kill_T | s2_replay; // @[Frontend.scala:133:23, :178:{36,56}]
wire _s2_can_speculatively_refill_T = io_ptw_customCSRs_csrs_0_value_0[3]; // @[CustomCSRs.scala:46:69]
wire _s2_can_speculatively_refill_T_1 = ~_s2_can_speculatively_refill_T; // @[CustomCSRs.scala:46:69]
wire s2_can_speculatively_refill = s2_tlb_resp_cacheable & _s2_can_speculatively_refill_T_1; // @[Frontend.scala:121:24, :179:{59,62}]
wire _icache_io_s2_kill_T = ~s2_can_speculatively_refill; // @[Frontend.scala:179:59, :180:42]
wire _icache_io_s2_kill_T_1 = s2_speculative & _icache_io_s2_kill_T; // @[Frontend.scala:123:31, :180:{39,42}]
wire _icache_io_s2_kill_T_2 = _icache_io_s2_kill_T_1 | s2_xcpt; // @[Frontend.scala:122:60, :180:{39,71}]
wire _icache_io_s2_prefetch_T = io_ptw_customCSRs_csrs_0_value_0[17]; // @[RocketCore.scala:115:60]
wire _icache_io_s2_prefetch_T_1 = ~_icache_io_s2_prefetch_T; // @[RocketCore.scala:115:60]
wire _icache_io_s2_prefetch_T_2 = s2_tlb_resp_prefetchable & _icache_io_s2_prefetch_T_1; // @[Frontend.scala:121:24, :182:{53,56}]
reg fq_io_enq_valid_REG; // @[Frontend.scala:184:29]
wire _fq_io_enq_valid_T = fq_io_enq_valid_REG & s2_valid; // @[Frontend.scala:108:25, :184:{29,40}]
wire _GEN = s2_kill_speculative_tlb_refill & s2_tlb_resp_miss; // @[Frontend.scala:121:24, :160:55, :184:112]
wire _fq_io_enq_valid_T_1; // @[Frontend.scala:184:112]
assign _fq_io_enq_valid_T_1 = _GEN; // @[Frontend.scala:184:112]
wire _fq_io_enq_bits_replay_T_5; // @[Frontend.scala:190:150]
assign _fq_io_enq_bits_replay_T_5 = _GEN; // @[Frontend.scala:184:112, :190:150]
wire _fq_io_enq_valid_T_2 = _icache_io_resp_valid | _fq_io_enq_valid_T_1; // @[Frontend.scala:70:26, :184:{77,112}]
wire _fq_io_enq_valid_T_3 = ~s2_tlb_resp_miss; // @[Frontend.scala:121:24, :184:137]
wire _fq_io_enq_valid_T_4 = _fq_io_enq_valid_T_3 & _icache_io_s2_kill_T_2; // @[Frontend.scala:180:71, :184:{137,155}]
wire _fq_io_enq_valid_T_5 = _fq_io_enq_valid_T_2 | _fq_io_enq_valid_T_4; // @[Frontend.scala:184:{77,133,155}]
assign _fq_io_enq_valid_T_6 = _fq_io_enq_valid_T & _fq_io_enq_valid_T_5; // @[Frontend.scala:184:{40,52,133}]
wire [39:0] _io_cpu_npc_T = io_cpu_req_valid_0 ? io_cpu_req_bits_pc_0 : npc; // @[Frontend.scala:82:7, :135:16, :186:28]
wire [39:0] _io_cpu_npc_T_1 = ~_io_cpu_npc_T; // @[Frontend.scala:186:28, :384:29]
wire [39:0] _io_cpu_npc_T_2 = {_io_cpu_npc_T_1[39:1], 1'h1}; // @[Frontend.scala:384:{29,33}]
assign _io_cpu_npc_T_3 = ~_io_cpu_npc_T_2; // @[Frontend.scala:384:{27,33}]
assign io_cpu_npc_0 = _io_cpu_npc_T_3; // @[Frontend.scala:82:7, :384:27]
wire _fq_io_enq_bits_mask_T = s2_pc[1]; // @[package.scala:163:13]
wire [2:0] _fq_io_enq_bits_mask_T_1 = 3'h3 << _fq_io_enq_bits_mask_T; // @[package.scala:163:13]
wire _fq_io_enq_bits_replay_T = ~_icache_io_resp_valid; // @[Frontend.scala:70:26, :190:80]
wire _fq_io_enq_bits_replay_T_1 = _icache_io_s2_kill_T_2 & _fq_io_enq_bits_replay_T; // @[Frontend.scala:180:71, :190:{77,80}]
wire _fq_io_enq_bits_replay_T_2 = ~s2_xcpt; // @[Frontend.scala:122:60, :190:105]
wire _fq_io_enq_bits_replay_T_3 = _fq_io_enq_bits_replay_T_1 & _fq_io_enq_bits_replay_T_2; // @[Frontend.scala:190:{77,102,105}]
wire _fq_io_enq_bits_replay_T_4 = _fq_io_enq_bits_replay_T_3; // @[Frontend.scala:190:{56,102}]
wire _fq_io_enq_bits_replay_T_6 = _fq_io_enq_bits_replay_T_4 | _fq_io_enq_bits_replay_T_5; // @[Frontend.scala:190:{56,115,150}]
wire _btb_io_req_valid_T = ~s2_redirect; // @[Frontend.scala:145:32, :148:17, :209:27]
assign predicted_taken = _btb_io_resp_valid & _btb_io_resp_bits_taken; // @[Frontend.scala:131:36, :198:21, :213:29]
wire _predicted_npc_T = _btb_io_resp_bits_target[38]; // @[package.scala:132:38]
wire [39:0] _predicted_npc_T_1 = {_predicted_npc_T, _btb_io_resp_bits_target}; // @[package.scala:132:{15,38}]
wire [39:0] _s2_base_pc_T = ~s2_pc; // @[Frontend.scala:117:22, :222:24]
wire [39:0] _s2_base_pc_T_1 = {_s2_base_pc_T[39:2], 2'h3}; // @[Frontend.scala:222:{24,31}]
wire [39:0] s2_base_pc = ~_s2_base_pc_T_1; // @[Frontend.scala:222:{22,31}]
wire [39:0] taken_pc = s2_base_pc; // @[Frontend.scala:222:22, :287:33]
wire _taken_T_35; // @[Frontend.scala:270:13]
wire taken_idx; // @[Frontend.scala:223:25]
wire [1:0] after_idx; // @[Frontend.scala:224:25]
wire useRAS; // @[Frontend.scala:225:29]
wire updateBTB; // @[Frontend.scala:226:32]
wire _fetch_bubble_likely_T = _fq_io_mask[1]; // @[Frontend.scala:91:64, :318:44]
wire fetch_bubble_likely = ~_fetch_bubble_likely_T; // @[Frontend.scala:318:{33,44}]
wire _btb_io_btb_update_valid_T_1 = ~wrong_path; // @[Frontend.scala:126:27, :319:52]
wire _btb_io_btb_update_valid_T_2 = _btb_io_btb_update_valid_T & _btb_io_btb_update_valid_T_1; // @[Decoupled.scala:51:35]
wire _btb_io_btb_update_valid_T_3 = _btb_io_btb_update_valid_T_2 & fetch_bubble_likely; // @[Frontend.scala:318:33, :319:{49,64}]
wire _btb_io_btb_update_valid_T_4 = _btb_io_btb_update_valid_T_3 & updateBTB; // @[Frontend.scala:226:32, :319:{64,87}]
wire [1:0] _btb_io_btb_update_bits_br_pc_T = {taken_idx, 1'h0}; // @[Frontend.scala:223:25, :323:63]
wire [39:0] _btb_io_btb_update_bits_br_pc_T_1 = {s2_base_pc[39:2], s2_base_pc[1:0] | _btb_io_btb_update_bits_br_pc_T}; // @[Frontend.scala:222:22, :323:{50,63}]
wire [2:0] _btb_io_ras_update_bits_returnAddr_T = {after_idx, 1'h0}; // @[Frontend.scala:224:25, :327:66]
wire [40:0] _btb_io_ras_update_bits_returnAddr_T_1 = {1'h0, s2_base_pc} + {38'h0, _btb_io_ras_update_bits_returnAddr_T}; // @[Frontend.scala:129:25, :222:22, :327:{53,66}]
wire [39:0] _btb_io_ras_update_bits_returnAddr_T_2 = _btb_io_ras_update_bits_returnAddr_T_1[39:0]; // @[Frontend.scala:327:53]
wire [1:0] _taken_prevRVI_T = s2_partial_insn[1:0]; // @[Frontend.scala:125:28, :233:39]
wire _taken_prevRVI_T_1 = _taken_prevRVI_T != 2'h3; // @[Frontend.scala:233:{39,45}]
wire _taken_prevRVI_T_2 = ~_taken_prevRVI_T_1; // @[Frontend.scala:233:45, :234:34]
wire taken_prevRVI = s2_partial_insn_valid & _taken_prevRVI_T_2; // @[Frontend.scala:124:38, :234:{31,34}]
wire _taken_valid_T = _fq_io_enq_bits_mask_T_1[0]; // @[Frontend.scala:189:50, :235:38]
wire _taken_valid_T_1 = ~taken_prevRVI; // @[Frontend.scala:234:31, :235:47]
wire taken_valid = _taken_valid_T & _taken_valid_T_1; // @[Frontend.scala:235:{38,44,47}]
wire [15:0] taken_bits = _icache_io_resp_bits_data[15:0]; // @[Frontend.scala:70:26, :236:37]
wire [1:0] _taken_rvc_T = taken_bits[1:0]; // @[Frontend.scala:233:39, :236:37]
wire [1:0] _taken_prevRVI_T_3 = taken_bits[1:0]; // @[Frontend.scala:233:39, :236:37]
wire taken_rvc = _taken_rvc_T != 2'h3; // @[Frontend.scala:233:{39,45}]
wire [31:0] taken_rviBits = {taken_bits, s2_partial_insn}; // @[Frontend.scala:125:28, :236:37, :238:24]
wire [6:0] _taken_rviBranch_T = taken_rviBits[6:0]; // @[Frontend.scala:238:24, :239:30]
wire [6:0] _taken_rviJump_T = taken_rviBits[6:0]; // @[Frontend.scala:238:24, :239:30, :240:28]
wire [6:0] _taken_rviJALR_T = taken_rviBits[6:0]; // @[Frontend.scala:238:24, :239:30, :241:28]
wire taken_rviBranch = _taken_rviBranch_T == 7'h63; // @[Frontend.scala:239:{30,36}]
wire taken_rviJump = _taken_rviJump_T == 7'h6F; // @[Frontend.scala:240:{28,34}]
wire taken_rviJALR = _taken_rviJALR_T == 7'h67; // @[Frontend.scala:241:{28,34}]
wire _taken_rviReturn_T = taken_rviBits[7]; // @[Frontend.scala:238:24, :242:42]
wire _taken_rviCall_T_1 = taken_rviBits[7]; // @[Frontend.scala:238:24, :242:42, :243:52]
wire _taken_rviImm_b11_T_7 = taken_rviBits[7]; // @[RocketCore.scala:1346:39]
wire _taken_rviImm_b0_T_1 = taken_rviBits[7]; // @[RocketCore.scala:1351:37]
wire _taken_rviImm_b11_T_18 = taken_rviBits[7]; // @[RocketCore.scala:1346:39]
wire _taken_rviImm_b0_T_9 = taken_rviBits[7]; // @[RocketCore.scala:1351:37]
wire _taken_rviReturn_T_1 = ~_taken_rviReturn_T; // @[Frontend.scala:242:{34,42}]
wire _taken_rviReturn_T_2 = taken_rviJALR & _taken_rviReturn_T_1; // @[Frontend.scala:241:34, :242:{31,34}]
wire [4:0] _taken_rviReturn_T_3 = taken_rviBits[19:15]; // @[Frontend.scala:238:24, :242:77]
wire [4:0] _taken_rviReturn_T_4 = _taken_rviReturn_T_3 & 5'h1B; // @[Frontend.scala:242:{66,77}]
wire _taken_rviReturn_T_5 = _taken_rviReturn_T_4 == 5'h1; // @[Frontend.scala:242:66]
wire taken_rviReturn = _taken_rviReturn_T_2 & _taken_rviReturn_T_5; // @[Frontend.scala:242:{31,46,66}]
wire _GEN_0 = taken_rviJALR | taken_rviJump; // @[Frontend.scala:240:34, :241:34, :243:30]
wire _taken_rviCall_T; // @[Frontend.scala:243:30]
assign _taken_rviCall_T = _GEN_0; // @[Frontend.scala:243:30]
wire _taken_taken_T; // @[Frontend.scala:255:29]
assign _taken_taken_T = _GEN_0; // @[Frontend.scala:243:30, :255:29]
wire taken_rviCall = _taken_rviCall_T & _taken_rviCall_T_1; // @[Frontend.scala:243:{30,42,52}]
wire [15:0] _GEN_1 = taken_bits & 16'hE003; // @[Frontend.scala:236:37, :244:28]
wire [15:0] _taken_rvcBranch_T; // @[Frontend.scala:244:28]
assign _taken_rvcBranch_T = _GEN_1; // @[Frontend.scala:244:28]
wire [15:0] _taken_rvcBranch_T_2; // @[Frontend.scala:244:60]
assign _taken_rvcBranch_T_2 = _GEN_1; // @[Frontend.scala:244:{28,60}]
wire [15:0] _taken_rvcJAL_T; // @[Frontend.scala:245:43]
assign _taken_rvcJAL_T = _GEN_1; // @[Frontend.scala:244:28, :245:43]
wire [15:0] _taken_rvcJump_T; // @[Frontend.scala:246:26]
assign _taken_rvcJump_T = _GEN_1; // @[Frontend.scala:244:28, :246:26]
wire _taken_rvcBranch_T_1 = _taken_rvcBranch_T == 16'hC001; // @[Frontend.scala:244:28]
wire _taken_rvcBranch_T_3 = _taken_rvcBranch_T_2 == 16'hE001; // @[Frontend.scala:244:60]
wire taken_rvcBranch = _taken_rvcBranch_T_1 | _taken_rvcBranch_T_3; // @[Frontend.scala:244:{28,52,60}]
wire _taken_rvcJAL_T_1 = _taken_rvcJAL_T == 16'h2001; // @[Frontend.scala:245:43]
wire _taken_rvcJump_T_1 = _taken_rvcJump_T == 16'hA001; // @[Frontend.scala:246:26]
wire taken_rvcJump = _taken_rvcJump_T_1; // @[Frontend.scala:246:{26,47}]
wire _taken_rvcImm_T = taken_bits[14]; // @[Frontend.scala:236:37, :247:28]
wire _taken_rvcImm_T_1 = taken_bits[12]; // @[RVC.scala:45:27]
wire _taken_rvcImm_T_9 = taken_bits[12]; // @[RVC.scala:44:28, :45:27]
wire [4:0] _taken_rvcImm_T_2 = {5{_taken_rvcImm_T_1}}; // @[RVC.scala:45:{22,27}]
wire [1:0] _taken_rvcImm_T_3 = taken_bits[6:5]; // @[RVC.scala:45:35]
wire _taken_rvcImm_T_4 = taken_bits[2]; // @[RVC.scala:45:43]
wire _taken_rvcImm_T_15 = taken_bits[2]; // @[RVC.scala:44:63, :45:43]
wire [1:0] _taken_rvcImm_T_5 = taken_bits[11:10]; // @[RVC.scala:45:49]
wire [1:0] _taken_rvcImm_T_6 = taken_bits[4:3]; // @[RVC.scala:45:59]
wire [3:0] taken_rvcImm_lo_hi = {_taken_rvcImm_T_5, _taken_rvcImm_T_6}; // @[RVC.scala:45:{17,49,59}]
wire [4:0] taken_rvcImm_lo = {taken_rvcImm_lo_hi, 1'h0}; // @[RVC.scala:45:17]
wire [6:0] taken_rvcImm_hi_hi = {_taken_rvcImm_T_2, _taken_rvcImm_T_3}; // @[RVC.scala:45:{17,22,35}]
wire [7:0] taken_rvcImm_hi = {taken_rvcImm_hi_hi, _taken_rvcImm_T_4}; // @[RVC.scala:45:{17,43}]
wire [12:0] _taken_rvcImm_T_7 = {taken_rvcImm_hi, taken_rvcImm_lo}; // @[RVC.scala:45:17]
wire [12:0] _taken_rvcImm_T_8 = _taken_rvcImm_T_7; // @[RVC.scala:45:17]
wire [9:0] _taken_rvcImm_T_10 = {10{_taken_rvcImm_T_9}}; // @[RVC.scala:44:{22,28}]
wire _taken_rvcImm_T_11 = taken_bits[8]; // @[RVC.scala:44:36]
wire [1:0] _taken_rvcImm_T_12 = taken_bits[10:9]; // @[RVC.scala:44:42]
wire _taken_rvcImm_T_13 = taken_bits[6]; // @[RVC.scala:44:51]
wire _taken_rvcImm_T_14 = taken_bits[7]; // @[RVC.scala:44:57]
wire _taken_rvcImm_T_16 = taken_bits[11]; // @[RVC.scala:44:69]
wire [2:0] _taken_rvcImm_T_17 = taken_bits[5:3]; // @[RVC.scala:44:76]
wire [3:0] taken_rvcImm_lo_lo = {_taken_rvcImm_T_17, 1'h0}; // @[RVC.scala:44:{17,76}]
wire [1:0] taken_rvcImm_lo_hi_1 = {_taken_rvcImm_T_15, _taken_rvcImm_T_16}; // @[RVC.scala:44:{17,63,69}]
wire [5:0] taken_rvcImm_lo_1 = {taken_rvcImm_lo_hi_1, taken_rvcImm_lo_lo}; // @[RVC.scala:44:17]
wire [1:0] taken_rvcImm_hi_lo = {_taken_rvcImm_T_13, _taken_rvcImm_T_14}; // @[RVC.scala:44:{17,51,57}]
wire [10:0] taken_rvcImm_hi_hi_hi = {_taken_rvcImm_T_10, _taken_rvcImm_T_11}; // @[RVC.scala:44:{17,22,36}]
wire [12:0] taken_rvcImm_hi_hi_1 = {taken_rvcImm_hi_hi_hi, _taken_rvcImm_T_12}; // @[RVC.scala:44:{17,42}]
wire [14:0] taken_rvcImm_hi_1 = {taken_rvcImm_hi_hi_1, taken_rvcImm_hi_lo}; // @[RVC.scala:44:17]
wire [20:0] _taken_rvcImm_T_18 = {taken_rvcImm_hi_1, taken_rvcImm_lo_1}; // @[RVC.scala:44:17]
wire [20:0] _taken_rvcImm_T_19 = _taken_rvcImm_T_18; // @[RVC.scala:44:17]
wire [20:0] taken_rvcImm = _taken_rvcImm_T ? {{8{_taken_rvcImm_T_8[12]}}, _taken_rvcImm_T_8} : _taken_rvcImm_T_19; // @[Frontend.scala:247:{23,28,72,118}]
wire [15:0] _GEN_2 = taken_bits & 16'hF003; // @[Frontend.scala:236:37, :248:24]
wire [15:0] _taken_rvcJR_T; // @[Frontend.scala:248:24]
assign _taken_rvcJR_T = _GEN_2; // @[Frontend.scala:248:24]
wire [15:0] _taken_rvcJALR_T; // @[Frontend.scala:250:26]
assign _taken_rvcJALR_T = _GEN_2; // @[Frontend.scala:248:24, :250:26]
wire _taken_rvcJR_T_1 = _taken_rvcJR_T == 16'h8002; // @[Frontend.scala:248:24]
wire [4:0] _taken_rvcJR_T_2 = taken_bits[6:2]; // @[Frontend.scala:236:37, :248:53]
wire [4:0] _taken_rvcJALR_T_2 = taken_bits[6:2]; // @[Frontend.scala:236:37, :248:53, :250:56]
wire _taken_rvcJR_T_3 = _taken_rvcJR_T_2 == 5'h0; // @[Frontend.scala:248:{53,59}]
wire taken_rvcJR = _taken_rvcJR_T_1 & _taken_rvcJR_T_3; // @[Frontend.scala:248:{24,46,59}]
wire [4:0] _taken_rvcReturn_T = taken_bits[11:7]; // @[Frontend.scala:236:37, :249:57]
wire [4:0] _taken_rvcReturn_T_1 = _taken_rvcReturn_T & 5'h1B; // @[Frontend.scala:249:{49,57}]
wire _taken_rvcReturn_T_2 = _taken_rvcReturn_T_1 == 5'h1; // @[Frontend.scala:249:49]
wire taken_rvcReturn = taken_rvcJR & _taken_rvcReturn_T_2; // @[Frontend.scala:248:46, :249:{29,49}]
wire _taken_rvcJALR_T_1 = _taken_rvcJALR_T == 16'h9002; // @[Frontend.scala:250:26]
wire _taken_rvcJALR_T_3 = _taken_rvcJALR_T_2 == 5'h0; // @[Frontend.scala:250:{56,62}]
wire taken_rvcJALR = _taken_rvcJALR_T_1 & _taken_rvcJALR_T_3; // @[Frontend.scala:250:{26,49,62}]
wire taken_rvcCall = taken_rvcJALR; // @[Frontend.scala:250:49, :251:28]
wire _taken_rviImm_T = taken_rviBits[3]; // @[Frontend.scala:238:24, :252:31]
wire _taken_rviImm_sign_T_1 = taken_rviBits[31]; // @[RocketCore.scala:1341:44]
wire _taken_rviImm_sign_T_4 = taken_rviBits[31]; // @[RocketCore.scala:1341:44]
wire _taken_rviImm_sign_T_2 = _taken_rviImm_sign_T_1; // @[RocketCore.scala:1341:{44,49}]
wire taken_rviImm_sign = _taken_rviImm_sign_T_2; // @[RocketCore.scala:1341:{19,49}]
wire _taken_rviImm_b11_T_9 = taken_rviImm_sign; // @[RocketCore.scala:1341:19, :1346:18]
wire taken_rviImm_hi_hi_hi = taken_rviImm_sign; // @[RocketCore.scala:1341:19, :1355:8]
wire [10:0] _taken_rviImm_b30_20_T_1 = taken_rviBits[30:20]; // @[RocketCore.scala:1342:41]
wire [10:0] _taken_rviImm_b30_20_T_4 = taken_rviBits[30:20]; // @[RocketCore.scala:1342:41]
wire [10:0] _taken_rviImm_b30_20_T_2 = _taken_rviImm_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}]
wire [10:0] taken_rviImm_b30_20 = {11{taken_rviImm_sign}}; // @[RocketCore.scala:1341:19, :1342:21]
wire [10:0] taken_rviImm_hi_hi_lo = taken_rviImm_b30_20; // @[RocketCore.scala:1342:21, :1355:8]
wire [7:0] _taken_rviImm_b19_12_T_3 = taken_rviBits[19:12]; // @[RocketCore.scala:1343:65]
wire [7:0] _taken_rviImm_b19_12_T_8 = taken_rviBits[19:12]; // @[RocketCore.scala:1343:65]
wire [7:0] _taken_rviImm_b19_12_T_4 = _taken_rviImm_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}]
wire [7:0] taken_rviImm_b19_12 = _taken_rviImm_b19_12_T_4; // @[RocketCore.scala:1343:{21,73}]
wire [7:0] taken_rviImm_hi_lo_hi = taken_rviImm_b19_12; // @[RocketCore.scala:1343:21, :1355:8]
wire _taken_rviImm_b11_T_4 = taken_rviBits[20]; // @[RocketCore.scala:1345:39]
wire _taken_rviImm_b0_T_3 = taken_rviBits[20]; // @[RocketCore.scala:1345:39, :1352:37]
wire _taken_rviImm_b11_T_15 = taken_rviBits[20]; // @[RocketCore.scala:1345:39]
wire _taken_rviImm_b0_T_11 = taken_rviBits[20]; // @[RocketCore.scala:1345:39, :1352:37]
wire _taken_rviImm_b11_T_5 = _taken_rviImm_b11_T_4; // @[RocketCore.scala:1345:{39,44}]
wire _taken_rviImm_b11_T_10 = _taken_rviImm_b11_T_5; // @[RocketCore.scala:1345:{18,44}]
wire _taken_rviImm_b11_T_8 = _taken_rviImm_b11_T_7; // @[RocketCore.scala:1346:{39,43}]
wire taken_rviImm_b11 = _taken_rviImm_b11_T_10; // @[RocketCore.scala:1344:18, :1345:18]
wire taken_rviImm_hi_lo_lo = taken_rviImm_b11; // @[RocketCore.scala:1344:18, :1355:8]
wire [5:0] _taken_rviImm_b10_5_T_3 = taken_rviBits[30:25]; // @[RocketCore.scala:1347:62]
wire [5:0] _taken_rviImm_b10_5_T_7 = taken_rviBits[30:25]; // @[RocketCore.scala:1347:62]
wire [5:0] taken_rviImm_b10_5 = _taken_rviImm_b10_5_T_3; // @[RocketCore.scala:1347:{20,62}]
wire [3:0] _taken_rviImm_b4_1_T_4 = taken_rviBits[11:8]; // @[RocketCore.scala:1349:57]
wire [3:0] _taken_rviImm_b4_1_T_14 = taken_rviBits[11:8]; // @[RocketCore.scala:1349:57]
wire [3:0] _taken_rviImm_b4_1_T_6 = taken_rviBits[19:16]; // @[RocketCore.scala:1350:39]
wire [3:0] _taken_rviImm_b4_1_T_16 = taken_rviBits[19:16]; // @[RocketCore.scala:1350:39]
wire [3:0] _taken_rviImm_b4_1_T_7 = taken_rviBits[24:21]; // @[RocketCore.scala:1350:52]
wire [3:0] _taken_rviImm_b4_1_T_17 = taken_rviBits[24:21]; // @[RocketCore.scala:1350:52]
wire [3:0] _taken_rviImm_b4_1_T_8 = _taken_rviImm_b4_1_T_7; // @[RocketCore.scala:1350:{19,52}]
wire [3:0] _taken_rviImm_b4_1_T_9 = _taken_rviImm_b4_1_T_8; // @[RocketCore.scala:1349:19, :1350:19]
wire [3:0] taken_rviImm_b4_1 = _taken_rviImm_b4_1_T_9; // @[RocketCore.scala:1348:19, :1349:19]
wire _taken_rviImm_b0_T_5 = taken_rviBits[15]; // @[RocketCore.scala:1353:37]
wire _taken_rviImm_b0_T_13 = taken_rviBits[15]; // @[RocketCore.scala:1353:37]
wire [9:0] taken_rviImm_lo_hi = {taken_rviImm_b10_5, taken_rviImm_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8]
wire [10:0] taken_rviImm_lo = {taken_rviImm_lo_hi, 1'h0}; // @[RocketCore.scala:1355:8]
wire [8:0] taken_rviImm_hi_lo = {taken_rviImm_hi_lo_hi, taken_rviImm_hi_lo_lo}; // @[RocketCore.scala:1355:8]
wire [11:0] taken_rviImm_hi_hi = {taken_rviImm_hi_hi_hi, taken_rviImm_hi_hi_lo}; // @[RocketCore.scala:1355:8]
wire [20:0] taken_rviImm_hi = {taken_rviImm_hi_hi, taken_rviImm_hi_lo}; // @[RocketCore.scala:1355:8]
wire [31:0] _taken_rviImm_T_1 = {taken_rviImm_hi, taken_rviImm_lo}; // @[RocketCore.scala:1355:8]
wire [31:0] _taken_rviImm_T_2 = _taken_rviImm_T_1; // @[RocketCore.scala:1355:{8,53}]
wire _taken_rviImm_sign_T_5 = _taken_rviImm_sign_T_4; // @[RocketCore.scala:1341:{44,49}]
wire taken_rviImm_sign_1 = _taken_rviImm_sign_T_5; // @[RocketCore.scala:1341:{19,49}]
wire taken_rviImm_hi_hi_hi_1 = taken_rviImm_sign_1; // @[RocketCore.scala:1341:19, :1355:8]
wire [10:0] _taken_rviImm_b30_20_T_5 = _taken_rviImm_b30_20_T_4; // @[RocketCore.scala:1342:{41,49}]
wire [10:0] taken_rviImm_b30_20_1 = {11{taken_rviImm_sign_1}}; // @[RocketCore.scala:1341:19, :1342:21]
wire [10:0] taken_rviImm_hi_hi_lo_1 = taken_rviImm_b30_20_1; // @[RocketCore.scala:1342:21, :1355:8]
wire [7:0] _taken_rviImm_b19_12_T_9 = _taken_rviImm_b19_12_T_8; // @[RocketCore.scala:1343:{65,73}]
wire [7:0] taken_rviImm_b19_12_1 = {8{taken_rviImm_sign_1}}; // @[RocketCore.scala:1341:19, :1343:21]
wire [7:0] taken_rviImm_hi_lo_hi_1 = taken_rviImm_b19_12_1; // @[RocketCore.scala:1343:21, :1355:8]
wire _taken_rviImm_b11_T_16 = _taken_rviImm_b11_T_15; // @[RocketCore.scala:1345:{39,44}]
wire _taken_rviImm_b11_T_19 = _taken_rviImm_b11_T_18; // @[RocketCore.scala:1346:{39,43}]
wire _taken_rviImm_b11_T_20 = _taken_rviImm_b11_T_19; // @[RocketCore.scala:1346:{18,43}]
wire _taken_rviImm_b11_T_21 = _taken_rviImm_b11_T_20; // @[RocketCore.scala:1345:18, :1346:18]
wire taken_rviImm_b11_1 = _taken_rviImm_b11_T_21; // @[RocketCore.scala:1344:18, :1345:18]
wire taken_rviImm_hi_lo_lo_1 = taken_rviImm_b11_1; // @[RocketCore.scala:1344:18, :1355:8]
wire [5:0] taken_rviImm_b10_5_1 = _taken_rviImm_b10_5_T_7; // @[RocketCore.scala:1347:{20,62}]
wire [3:0] _taken_rviImm_b4_1_T_19 = _taken_rviImm_b4_1_T_14; // @[RocketCore.scala:1349:{19,57}]
wire [3:0] _taken_rviImm_b4_1_T_18 = _taken_rviImm_b4_1_T_17; // @[RocketCore.scala:1350:{19,52}]
wire [3:0] taken_rviImm_b4_1_1 = _taken_rviImm_b4_1_T_19; // @[RocketCore.scala:1348:19, :1349:19]
wire [9:0] taken_rviImm_lo_hi_1 = {taken_rviImm_b10_5_1, taken_rviImm_b4_1_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8]
wire [10:0] taken_rviImm_lo_1 = {taken_rviImm_lo_hi_1, 1'h0}; // @[RocketCore.scala:1355:8]
wire [8:0] taken_rviImm_hi_lo_1 = {taken_rviImm_hi_lo_hi_1, taken_rviImm_hi_lo_lo_1}; // @[RocketCore.scala:1355:8]
wire [11:0] taken_rviImm_hi_hi_1 = {taken_rviImm_hi_hi_hi_1, taken_rviImm_hi_hi_lo_1}; // @[RocketCore.scala:1355:8]
wire [20:0] taken_rviImm_hi_1 = {taken_rviImm_hi_hi_1, taken_rviImm_hi_lo_1}; // @[RocketCore.scala:1355:8]
wire [31:0] _taken_rviImm_T_3 = {taken_rviImm_hi_1, taken_rviImm_lo_1}; // @[RocketCore.scala:1355:8]
wire [31:0] _taken_rviImm_T_4 = _taken_rviImm_T_3; // @[RocketCore.scala:1355:{8,53}]
wire [31:0] taken_rviImm = _taken_rviImm_T ? _taken_rviImm_T_2 : _taken_rviImm_T_4; // @[RocketCore.scala:1355:53]
wire taken_predict_taken = _taken_predict_taken_T; // @[Frontend.scala:253:54]
wire _taken_taken_T_1 = taken_rviBranch & taken_predict_taken; // @[Frontend.scala:239:36, :253:54, :255:53]
wire _taken_taken_T_2 = _taken_taken_T | _taken_taken_T_1; // @[Frontend.scala:255:{29,40,53}]
wire _taken_taken_T_3 = taken_prevRVI & _taken_taken_T_2; // @[Frontend.scala:234:31, :255:{17,40}]
wire _taken_taken_T_4 = taken_rvcJump | taken_rvcJALR; // @[Frontend.scala:246:47, :250:49, :256:27]
wire _taken_taken_T_5 = _taken_taken_T_4 | taken_rvcJR; // @[Frontend.scala:248:46, :256:{27,38}]
wire _taken_taken_T_6 = taken_rvcBranch & taken_predict_taken; // @[Frontend.scala:244:52, :253:54, :256:60]
wire _taken_taken_T_7 = _taken_taken_T_5 | _taken_taken_T_6; // @[Frontend.scala:256:{38,47,60}]
wire _taken_taken_T_8 = taken_valid & _taken_taken_T_7; // @[Frontend.scala:235:44, :256:{15,47}]
wire taken_taken = _taken_taken_T_3 | _taken_taken_T_8; // @[Frontend.scala:255:{17,71}, :256:15]
wire _taken_T_28 = taken_taken; // @[Frontend.scala:255:71, :313:51]
wire _taken_predictReturn_T = taken_prevRVI & taken_rviReturn; // @[Frontend.scala:234:31, :242:46, :257:61]
wire _taken_predictReturn_T_1 = taken_valid & taken_rvcReturn; // @[Frontend.scala:235:44, :249:29, :257:83]
wire _taken_predictReturn_T_2 = _taken_predictReturn_T | _taken_predictReturn_T_1; // @[Frontend.scala:257:{61,74,83}]
wire taken_predictReturn = _btb_io_ras_head_valid & _taken_predictReturn_T_2; // @[Frontend.scala:198:21, :257:{49,74}]
wire _taken_predictJump_T = taken_prevRVI & taken_rviJump; // @[Frontend.scala:234:31, :240:34, :258:33]
wire _taken_predictJump_T_1 = taken_valid & taken_rvcJump; // @[Frontend.scala:235:44, :246:47, :258:53]
wire taken_predictJump = _taken_predictJump_T | _taken_predictJump_T_1; // @[Frontend.scala:258:{33,44,53}]
wire _GEN_3 = taken_prevRVI & taken_rviBranch; // @[Frontend.scala:234:31, :239:36, :259:53]
wire _taken_predictBranch_T; // @[Frontend.scala:259:53]
assign _taken_predictBranch_T = _GEN_3; // @[Frontend.scala:259:53]
wire _taken_T_19; // @[Frontend.scala:294:23]
assign _taken_T_19 = _GEN_3; // @[Frontend.scala:259:53, :294:23]
wire _GEN_4 = taken_valid & taken_rvcBranch; // @[Frontend.scala:235:44, :244:52, :259:75]
wire _taken_predictBranch_T_1; // @[Frontend.scala:259:75]
assign _taken_predictBranch_T_1 = _GEN_4; // @[Frontend.scala:259:75]
wire _taken_T_20; // @[Frontend.scala:294:45]
assign _taken_T_20 = _GEN_4; // @[Frontend.scala:259:75, :294:45]
wire _taken_predictBranch_T_2 = _taken_predictBranch_T | _taken_predictBranch_T_1; // @[Frontend.scala:259:{53,66,75}]
wire taken_predictBranch = taken_predict_taken & _taken_predictBranch_T_2; // @[Frontend.scala:253:54, :259:{41,66}]
wire _GEN_5 = s2_valid & s2_btb_resp_valid; // @[Frontend.scala:108:25, :118:44, :261:22]
wire _taken_T; // @[Frontend.scala:261:22]
assign _taken_T = _GEN_5; // @[Frontend.scala:261:22]
wire _taken_T_29; // @[Frontend.scala:261:22]
assign _taken_T_29 = _GEN_5; // @[Frontend.scala:261:22]
wire _taken_T_1 = ~s2_btb_resp_bits_bridx; // @[Frontend.scala:119:29, :261:69]
wire _taken_T_2 = _taken_T & _taken_T_1; // @[Frontend.scala:261:{22,43,69}]
wire _taken_T_3 = _taken_T_2 & taken_valid; // @[Frontend.scala:235:44, :261:{43,79}]
wire _taken_T_4 = ~taken_rvc; // @[Frontend.scala:233:45, :261:91]
wire _taken_T_5 = _taken_T_3 & _taken_T_4; // @[Frontend.scala:261:{79,88,91}]
wire _taken_btb_io_ras_update_valid_T_1 = ~wrong_path; // @[Frontend.scala:126:27, :273:54, :319:52]
wire _taken_btb_io_ras_update_valid_T_2 = _taken_btb_io_ras_update_valid_T & _taken_btb_io_ras_update_valid_T_1; // @[Decoupled.scala:51:35]
wire _taken_btb_io_ras_update_valid_T_3 = taken_rviCall | taken_rviReturn; // @[Frontend.scala:242:46, :243:42, :273:90]
wire _taken_btb_io_ras_update_valid_T_4 = taken_prevRVI & _taken_btb_io_ras_update_valid_T_3; // @[Frontend.scala:234:31, :273:{78,90}]
wire _taken_btb_io_ras_update_valid_T_5 = taken_rvcCall | taken_rvcReturn; // @[Frontend.scala:249:29, :251:28, :273:125]
wire _taken_btb_io_ras_update_valid_T_6 = taken_valid & _taken_btb_io_ras_update_valid_T_5; // @[Frontend.scala:235:44, :273:{113,125}]
wire _taken_btb_io_ras_update_valid_T_7 = _taken_btb_io_ras_update_valid_T_4 | _taken_btb_io_ras_update_valid_T_6; // @[Frontend.scala:273:{78,104,113}]
wire _taken_btb_io_ras_update_valid_T_8 = _taken_btb_io_ras_update_valid_T_2 & _taken_btb_io_ras_update_valid_T_7; // @[Frontend.scala:273:{51,66,104}]
wire _taken_btb_io_ras_update_bits_cfiType_T = taken_prevRVI ? taken_rviReturn : taken_rvcReturn; // @[Frontend.scala:234:31, :242:46, :249:29, :274:50]
wire _taken_btb_io_ras_update_bits_cfiType_T_1 = taken_prevRVI ? taken_rviCall : taken_rvcCall; // @[Frontend.scala:234:31, :243:42, :251:28, :275:50]
wire _taken_btb_io_ras_update_bits_cfiType_T_2 = taken_prevRVI ? taken_rviBranch : taken_rvcBranch; // @[Frontend.scala:234:31, :239:36, :244:52, :276:50]
wire _taken_btb_io_ras_update_bits_cfiType_T_4 = _taken_btb_io_ras_update_bits_cfiType_T_2; // @[Frontend.scala:276:{50,82}]
wire _taken_btb_io_ras_update_bits_cfiType_T_5 = ~_taken_btb_io_ras_update_bits_cfiType_T_4; // @[Frontend.scala:276:{46,82}]
wire [1:0] _taken_btb_io_ras_update_bits_cfiType_T_6 = _taken_btb_io_ras_update_bits_cfiType_T_1 ? 2'h2 : {1'h0, _taken_btb_io_ras_update_bits_cfiType_T_5}; // @[Frontend.scala:275:{46,50}, :276:46]
wire [1:0] _taken_btb_io_ras_update_bits_cfiType_T_7 = _taken_btb_io_ras_update_bits_cfiType_T ? 2'h3 : _taken_btb_io_ras_update_bits_cfiType_T_6; // @[Frontend.scala:274:{46,50}, :275:46]
wire _taken_T_7 = ~s2_btb_taken; // @[Frontend.scala:120:40, :279:15]
wire _taken_T_9 = _taken_T_8 & taken_taken; // @[Decoupled.scala:51:35]
wire _taken_T_10 = ~taken_predictBranch; // @[Frontend.scala:259:41, :280:44]
wire _taken_T_11 = _taken_T_9 & _taken_T_10; // @[Frontend.scala:280:{32,41,44}]
wire _taken_T_12 = ~taken_predictJump; // @[Frontend.scala:258:44, :280:62]
wire _taken_T_13 = _taken_T_11 & _taken_T_12; // @[Frontend.scala:280:{41,59,62}]
wire _taken_T_14 = ~taken_predictReturn; // @[Frontend.scala:257:49, :280:78]
wire _taken_T_15 = _taken_T_13 & _taken_T_14; // @[Frontend.scala:280:{59,75,78}]
wire _taken_T_16 = s2_valid & taken_predictReturn; // @[Frontend.scala:108:25, :257:49, :283:26]
wire _taken_T_17 = taken_predictBranch | taken_predictJump; // @[Frontend.scala:258:44, :259:41, :286:44]
wire _taken_T_18 = s2_valid & _taken_T_17; // @[Frontend.scala:108:25, :286:{26,44}]
wire [39:0] _taken_npc_T = taken_pc; // @[Frontend.scala:287:33, :289:32]
wire [32:0] _taken_npc_T_1 = {taken_rviImm[31], taken_rviImm} - 33'h2; // @[Frontend.scala:252:23, :289:61]
wire [32:0] _taken_npc_T_2 = taken_prevRVI ? _taken_npc_T_1 : {{12{taken_rvcImm[20]}}, taken_rvcImm}; // @[Frontend.scala:234:31, :247:23, :289:{44,61}]
wire [40:0] _taken_npc_T_3 = {_taken_npc_T[39], _taken_npc_T} + {{8{_taken_npc_T_2[32]}}, _taken_npc_T_2}; // @[Frontend.scala:289:{32,39,44}]
wire [39:0] _taken_npc_T_4 = _taken_npc_T_3[39:0]; // @[Frontend.scala:289:39]
wire [39:0] taken_npc = _taken_npc_T_4; // @[Frontend.scala:289:39]
wire [39:0] _taken_predicted_npc_T = taken_npc; // @[Frontend.scala:289:39, :291:34]
wire _taken_T_21 = _taken_T_19 | _taken_T_20; // @[Frontend.scala:294:{23,36,45}]
wire _taken_btb_io_bht_advance_valid_T_1 = ~wrong_path; // @[Frontend.scala:126:27, :295:57, :319:52]
wire _taken_btb_io_bht_advance_valid_T_2 = _taken_btb_io_bht_advance_valid_T & _taken_btb_io_bht_advance_valid_T_1; // @[Decoupled.scala:51:35]
wire _taken_T_22 = ~s2_btb_resp_valid; // @[Frontend.scala:118:44, :298:15]
wire _taken_T_24 = taken_predictBranch & _taken_T_23; // @[Frontend.scala:259:41, :298:52]
wire _taken_T_25 = _taken_T_24 | taken_predictJump; // @[Frontend.scala:258:44, :298:{52,91}]
wire _taken_T_26 = _taken_T_25 | taken_predictReturn; // @[Frontend.scala:257:49, :298:{91,106}]
wire _taken_T_27 = _taken_T_22 & _taken_T_26; // @[Frontend.scala:298:{15,34,106}]
wire _taken_prevRVI_T_4 = _taken_prevRVI_T_3 != 2'h3; // @[Frontend.scala:233:{39,45}]
wire _taken_prevRVI_T_5 = ~_taken_prevRVI_T_4; // @[Frontend.scala:233:45, :234:34]
wire taken_prevRVI_1 = taken_valid & _taken_prevRVI_T_5; // @[Frontend.scala:234:{31,34}, :235:44]
wire _taken_valid_T_2 = _fq_io_enq_bits_mask_T_1[1]; // @[Frontend.scala:189:50, :235:38]
wire _taken_valid_T_3 = ~taken_prevRVI_1; // @[Frontend.scala:234:31, :235:47]
wire taken_valid_1 = _taken_valid_T_2 & _taken_valid_T_3; // @[Frontend.scala:235:{38,44,47}]
wire [15:0] taken_bits_1 = _icache_io_resp_bits_data[31:16]; // @[Frontend.scala:70:26, :236:37]
wire [1:0] _taken_rvc_T_1 = taken_bits_1[1:0]; // @[Frontend.scala:233:39, :236:37]
wire taken_rvc_1 = _taken_rvc_T_1 != 2'h3; // @[Frontend.scala:233:{39,45}]
wire [31:0] taken_rviBits_1 = {taken_bits_1, taken_bits}; // @[Frontend.scala:236:37, :238:24]
wire [6:0] _taken_rviBranch_T_1 = taken_rviBits_1[6:0]; // @[Frontend.scala:238:24, :239:30]
wire [6:0] _taken_rviJump_T_1 = taken_rviBits_1[6:0]; // @[Frontend.scala:238:24, :239:30, :240:28]
wire [6:0] _taken_rviJALR_T_1 = taken_rviBits_1[6:0]; // @[Frontend.scala:238:24, :239:30, :241:28]
wire taken_rviBranch_1 = _taken_rviBranch_T_1 == 7'h63; // @[Frontend.scala:239:{30,36}]
wire taken_rviJump_1 = _taken_rviJump_T_1 == 7'h6F; // @[Frontend.scala:240:{28,34}]
wire taken_rviJALR_1 = _taken_rviJALR_T_1 == 7'h67; // @[Frontend.scala:241:{28,34}]
wire _taken_rviReturn_T_6 = taken_rviBits_1[7]; // @[Frontend.scala:238:24, :242:42]
wire _taken_rviCall_T_3 = taken_rviBits_1[7]; // @[Frontend.scala:238:24, :242:42, :243:52]
wire _taken_rviImm_b11_T_29 = taken_rviBits_1[7]; // @[RocketCore.scala:1346:39]
wire _taken_rviImm_b0_T_17 = taken_rviBits_1[7]; // @[RocketCore.scala:1351:37]
wire _taken_rviImm_b11_T_40 = taken_rviBits_1[7]; // @[RocketCore.scala:1346:39]
wire _taken_rviImm_b0_T_25 = taken_rviBits_1[7]; // @[RocketCore.scala:1351:37]
wire _taken_rviReturn_T_7 = ~_taken_rviReturn_T_6; // @[Frontend.scala:242:{34,42}]
wire _taken_rviReturn_T_8 = taken_rviJALR_1 & _taken_rviReturn_T_7; // @[Frontend.scala:241:34, :242:{31,34}]
wire [4:0] _taken_rviReturn_T_9 = taken_rviBits_1[19:15]; // @[Frontend.scala:238:24, :242:77]
wire [4:0] _taken_rviReturn_T_10 = _taken_rviReturn_T_9 & 5'h1B; // @[Frontend.scala:242:{66,77}]
wire _taken_rviReturn_T_11 = _taken_rviReturn_T_10 == 5'h1; // @[Frontend.scala:242:66]
wire taken_rviReturn_1 = _taken_rviReturn_T_8 & _taken_rviReturn_T_11; // @[Frontend.scala:242:{31,46,66}]
wire _GEN_6 = taken_rviJALR_1 | taken_rviJump_1; // @[Frontend.scala:240:34, :241:34, :243:30]
wire _taken_rviCall_T_2; // @[Frontend.scala:243:30]
assign _taken_rviCall_T_2 = _GEN_6; // @[Frontend.scala:243:30]
wire _taken_taken_T_9; // @[Frontend.scala:255:29]
assign _taken_taken_T_9 = _GEN_6; // @[Frontend.scala:243:30, :255:29]
wire taken_rviCall_1 = _taken_rviCall_T_2 & _taken_rviCall_T_3; // @[Frontend.scala:243:{30,42,52}]
wire [15:0] _GEN_7 = taken_bits_1 & 16'hE003; // @[Frontend.scala:236:37, :244:28]
wire [15:0] _taken_rvcBranch_T_4; // @[Frontend.scala:244:28]
assign _taken_rvcBranch_T_4 = _GEN_7; // @[Frontend.scala:244:28]
wire [15:0] _taken_rvcBranch_T_6; // @[Frontend.scala:244:60]
assign _taken_rvcBranch_T_6 = _GEN_7; // @[Frontend.scala:244:{28,60}]
wire [15:0] _taken_rvcJAL_T_2; // @[Frontend.scala:245:43]
assign _taken_rvcJAL_T_2 = _GEN_7; // @[Frontend.scala:244:28, :245:43]
wire [15:0] _taken_rvcJump_T_2; // @[Frontend.scala:246:26]
assign _taken_rvcJump_T_2 = _GEN_7; // @[Frontend.scala:244:28, :246:26]
wire _taken_rvcBranch_T_5 = _taken_rvcBranch_T_4 == 16'hC001; // @[Frontend.scala:244:28]
wire _taken_rvcBranch_T_7 = _taken_rvcBranch_T_6 == 16'hE001; // @[Frontend.scala:244:60]
wire taken_rvcBranch_1 = _taken_rvcBranch_T_5 | _taken_rvcBranch_T_7; // @[Frontend.scala:244:{28,52,60}]
wire _taken_rvcJAL_T_3 = _taken_rvcJAL_T_2 == 16'h2001; // @[Frontend.scala:245:43]
wire _taken_rvcJump_T_3 = _taken_rvcJump_T_2 == 16'hA001; // @[Frontend.scala:246:26]
wire taken_rvcJump_1 = _taken_rvcJump_T_3; // @[Frontend.scala:246:{26,47}]
wire _taken_rvcImm_T_20 = taken_bits_1[14]; // @[Frontend.scala:236:37, :247:28]
wire _taken_rvcImm_T_21 = taken_bits_1[12]; // @[RVC.scala:45:27]
wire _taken_rvcImm_T_29 = taken_bits_1[12]; // @[RVC.scala:44:28, :45:27]
wire [4:0] _taken_rvcImm_T_22 = {5{_taken_rvcImm_T_21}}; // @[RVC.scala:45:{22,27}]
wire [1:0] _taken_rvcImm_T_23 = taken_bits_1[6:5]; // @[RVC.scala:45:35]
wire _taken_rvcImm_T_24 = taken_bits_1[2]; // @[RVC.scala:45:43]
wire _taken_rvcImm_T_35 = taken_bits_1[2]; // @[RVC.scala:44:63, :45:43]
wire [1:0] _taken_rvcImm_T_25 = taken_bits_1[11:10]; // @[RVC.scala:45:49]
wire [1:0] _taken_rvcImm_T_26 = taken_bits_1[4:3]; // @[RVC.scala:45:59]
wire [3:0] taken_rvcImm_lo_hi_2 = {_taken_rvcImm_T_25, _taken_rvcImm_T_26}; // @[RVC.scala:45:{17,49,59}]
wire [4:0] taken_rvcImm_lo_2 = {taken_rvcImm_lo_hi_2, 1'h0}; // @[RVC.scala:45:17]
wire [6:0] taken_rvcImm_hi_hi_2 = {_taken_rvcImm_T_22, _taken_rvcImm_T_23}; // @[RVC.scala:45:{17,22,35}]
wire [7:0] taken_rvcImm_hi_2 = {taken_rvcImm_hi_hi_2, _taken_rvcImm_T_24}; // @[RVC.scala:45:{17,43}]
wire [12:0] _taken_rvcImm_T_27 = {taken_rvcImm_hi_2, taken_rvcImm_lo_2}; // @[RVC.scala:45:17]
wire [12:0] _taken_rvcImm_T_28 = _taken_rvcImm_T_27; // @[RVC.scala:45:17]
wire [9:0] _taken_rvcImm_T_30 = {10{_taken_rvcImm_T_29}}; // @[RVC.scala:44:{22,28}]
wire _taken_rvcImm_T_31 = taken_bits_1[8]; // @[RVC.scala:44:36]
wire [1:0] _taken_rvcImm_T_32 = taken_bits_1[10:9]; // @[RVC.scala:44:42]
wire _taken_rvcImm_T_33 = taken_bits_1[6]; // @[RVC.scala:44:51]
wire _taken_rvcImm_T_34 = taken_bits_1[7]; // @[RVC.scala:44:57]
wire _taken_rvcImm_T_36 = taken_bits_1[11]; // @[RVC.scala:44:69]
wire [2:0] _taken_rvcImm_T_37 = taken_bits_1[5:3]; // @[RVC.scala:44:76]
wire [3:0] taken_rvcImm_lo_lo_1 = {_taken_rvcImm_T_37, 1'h0}; // @[RVC.scala:44:{17,76}]
wire [1:0] taken_rvcImm_lo_hi_3 = {_taken_rvcImm_T_35, _taken_rvcImm_T_36}; // @[RVC.scala:44:{17,63,69}]
wire [5:0] taken_rvcImm_lo_3 = {taken_rvcImm_lo_hi_3, taken_rvcImm_lo_lo_1}; // @[RVC.scala:44:17]
wire [1:0] taken_rvcImm_hi_lo_1 = {_taken_rvcImm_T_33, _taken_rvcImm_T_34}; // @[RVC.scala:44:{17,51,57}]
wire [10:0] taken_rvcImm_hi_hi_hi_1 = {_taken_rvcImm_T_30, _taken_rvcImm_T_31}; // @[RVC.scala:44:{17,22,36}]
wire [12:0] taken_rvcImm_hi_hi_3 = {taken_rvcImm_hi_hi_hi_1, _taken_rvcImm_T_32}; // @[RVC.scala:44:{17,42}]
wire [14:0] taken_rvcImm_hi_3 = {taken_rvcImm_hi_hi_3, taken_rvcImm_hi_lo_1}; // @[RVC.scala:44:17]
wire [20:0] _taken_rvcImm_T_38 = {taken_rvcImm_hi_3, taken_rvcImm_lo_3}; // @[RVC.scala:44:17]
wire [20:0] _taken_rvcImm_T_39 = _taken_rvcImm_T_38; // @[RVC.scala:44:17]
wire [20:0] taken_rvcImm_1 = _taken_rvcImm_T_20 ? {{8{_taken_rvcImm_T_28[12]}}, _taken_rvcImm_T_28} : _taken_rvcImm_T_39; // @[Frontend.scala:247:{23,28,72,118}]
wire [15:0] _GEN_8 = taken_bits_1 & 16'hF003; // @[Frontend.scala:236:37, :248:24]
wire [15:0] _taken_rvcJR_T_4; // @[Frontend.scala:248:24]
assign _taken_rvcJR_T_4 = _GEN_8; // @[Frontend.scala:248:24]
wire [15:0] _taken_rvcJALR_T_4; // @[Frontend.scala:250:26]
assign _taken_rvcJALR_T_4 = _GEN_8; // @[Frontend.scala:248:24, :250:26]
wire _taken_rvcJR_T_5 = _taken_rvcJR_T_4 == 16'h8002; // @[Frontend.scala:248:24]
wire [4:0] _taken_rvcJR_T_6 = taken_bits_1[6:2]; // @[Frontend.scala:236:37, :248:53]
wire [4:0] _taken_rvcJALR_T_6 = taken_bits_1[6:2]; // @[Frontend.scala:236:37, :248:53, :250:56]
wire _taken_rvcJR_T_7 = _taken_rvcJR_T_6 == 5'h0; // @[Frontend.scala:248:{53,59}]
wire taken_rvcJR_1 = _taken_rvcJR_T_5 & _taken_rvcJR_T_7; // @[Frontend.scala:248:{24,46,59}]
wire [4:0] _taken_rvcReturn_T_3 = taken_bits_1[11:7]; // @[Frontend.scala:236:37, :249:57]
wire [4:0] _taken_rvcReturn_T_4 = _taken_rvcReturn_T_3 & 5'h1B; // @[Frontend.scala:249:{49,57}]
wire _taken_rvcReturn_T_5 = _taken_rvcReturn_T_4 == 5'h1; // @[Frontend.scala:249:49]
wire taken_rvcReturn_1 = taken_rvcJR_1 & _taken_rvcReturn_T_5; // @[Frontend.scala:248:46, :249:{29,49}]
wire _taken_rvcJALR_T_5 = _taken_rvcJALR_T_4 == 16'h9002; // @[Frontend.scala:250:26]
wire _taken_rvcJALR_T_7 = _taken_rvcJALR_T_6 == 5'h0; // @[Frontend.scala:250:{56,62}]
wire taken_rvcJALR_1 = _taken_rvcJALR_T_5 & _taken_rvcJALR_T_7; // @[Frontend.scala:250:{26,49,62}]
wire taken_rvcCall_1 = taken_rvcJALR_1; // @[Frontend.scala:250:49, :251:28]
wire _taken_rviImm_T_5 = taken_rviBits_1[3]; // @[Frontend.scala:238:24, :252:31]
wire _taken_rviImm_sign_T_7 = taken_rviBits_1[31]; // @[RocketCore.scala:1341:44]
wire _taken_rviImm_sign_T_10 = taken_rviBits_1[31]; // @[RocketCore.scala:1341:44]
wire _taken_rviImm_sign_T_8 = _taken_rviImm_sign_T_7; // @[RocketCore.scala:1341:{44,49}]
wire taken_rviImm_sign_2 = _taken_rviImm_sign_T_8; // @[RocketCore.scala:1341:{19,49}]
wire _taken_rviImm_b11_T_31 = taken_rviImm_sign_2; // @[RocketCore.scala:1341:19, :1346:18]
wire taken_rviImm_hi_hi_hi_2 = taken_rviImm_sign_2; // @[RocketCore.scala:1341:19, :1355:8]
wire [10:0] _taken_rviImm_b30_20_T_7 = taken_rviBits_1[30:20]; // @[RocketCore.scala:1342:41]
wire [10:0] _taken_rviImm_b30_20_T_10 = taken_rviBits_1[30:20]; // @[RocketCore.scala:1342:41]
wire [10:0] _taken_rviImm_b30_20_T_8 = _taken_rviImm_b30_20_T_7; // @[RocketCore.scala:1342:{41,49}]
wire [10:0] taken_rviImm_b30_20_2 = {11{taken_rviImm_sign_2}}; // @[RocketCore.scala:1341:19, :1342:21]
wire [10:0] taken_rviImm_hi_hi_lo_2 = taken_rviImm_b30_20_2; // @[RocketCore.scala:1342:21, :1355:8]
wire [7:0] _taken_rviImm_b19_12_T_13 = taken_rviBits_1[19:12]; // @[RocketCore.scala:1343:65]
wire [7:0] _taken_rviImm_b19_12_T_18 = taken_rviBits_1[19:12]; // @[RocketCore.scala:1343:65]
wire [7:0] _taken_rviImm_b19_12_T_14 = _taken_rviImm_b19_12_T_13; // @[RocketCore.scala:1343:{65,73}]
wire [7:0] taken_rviImm_b19_12_2 = _taken_rviImm_b19_12_T_14; // @[RocketCore.scala:1343:{21,73}]
wire [7:0] taken_rviImm_hi_lo_hi_2 = taken_rviImm_b19_12_2; // @[RocketCore.scala:1343:21, :1355:8]
wire _taken_rviImm_b11_T_26 = taken_rviBits_1[20]; // @[RocketCore.scala:1345:39]
wire _taken_rviImm_b0_T_19 = taken_rviBits_1[20]; // @[RocketCore.scala:1345:39, :1352:37]
wire _taken_rviImm_b11_T_37 = taken_rviBits_1[20]; // @[RocketCore.scala:1345:39]
wire _taken_rviImm_b0_T_27 = taken_rviBits_1[20]; // @[RocketCore.scala:1345:39, :1352:37]
wire _taken_rviImm_b11_T_27 = _taken_rviImm_b11_T_26; // @[RocketCore.scala:1345:{39,44}]
wire _taken_rviImm_b11_T_32 = _taken_rviImm_b11_T_27; // @[RocketCore.scala:1345:{18,44}]
wire _taken_rviImm_b11_T_30 = _taken_rviImm_b11_T_29; // @[RocketCore.scala:1346:{39,43}]
wire taken_rviImm_b11_2 = _taken_rviImm_b11_T_32; // @[RocketCore.scala:1344:18, :1345:18]
wire taken_rviImm_hi_lo_lo_2 = taken_rviImm_b11_2; // @[RocketCore.scala:1344:18, :1355:8]
wire [5:0] _taken_rviImm_b10_5_T_11 = taken_rviBits_1[30:25]; // @[RocketCore.scala:1347:62]
wire [5:0] _taken_rviImm_b10_5_T_15 = taken_rviBits_1[30:25]; // @[RocketCore.scala:1347:62]
wire [5:0] taken_rviImm_b10_5_2 = _taken_rviImm_b10_5_T_11; // @[RocketCore.scala:1347:{20,62}]
wire [3:0] _taken_rviImm_b4_1_T_24 = taken_rviBits_1[11:8]; // @[RocketCore.scala:1349:57]
wire [3:0] _taken_rviImm_b4_1_T_34 = taken_rviBits_1[11:8]; // @[RocketCore.scala:1349:57]
wire [3:0] _taken_rviImm_b4_1_T_26 = taken_rviBits_1[19:16]; // @[RocketCore.scala:1350:39]
wire [3:0] _taken_rviImm_b4_1_T_36 = taken_rviBits_1[19:16]; // @[RocketCore.scala:1350:39]
wire [3:0] _taken_rviImm_b4_1_T_27 = taken_rviBits_1[24:21]; // @[RocketCore.scala:1350:52]
wire [3:0] _taken_rviImm_b4_1_T_37 = taken_rviBits_1[24:21]; // @[RocketCore.scala:1350:52]
wire [3:0] _taken_rviImm_b4_1_T_28 = _taken_rviImm_b4_1_T_27; // @[RocketCore.scala:1350:{19,52}]
wire [3:0] _taken_rviImm_b4_1_T_29 = _taken_rviImm_b4_1_T_28; // @[RocketCore.scala:1349:19, :1350:19]
wire [3:0] taken_rviImm_b4_1_2 = _taken_rviImm_b4_1_T_29; // @[RocketCore.scala:1348:19, :1349:19]
wire _taken_rviImm_b0_T_21 = taken_rviBits_1[15]; // @[RocketCore.scala:1353:37]
wire _taken_rviImm_b0_T_29 = taken_rviBits_1[15]; // @[RocketCore.scala:1353:37]
wire [9:0] taken_rviImm_lo_hi_2 = {taken_rviImm_b10_5_2, taken_rviImm_b4_1_2}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8]
wire [10:0] taken_rviImm_lo_2 = {taken_rviImm_lo_hi_2, 1'h0}; // @[RocketCore.scala:1355:8]
wire [8:0] taken_rviImm_hi_lo_2 = {taken_rviImm_hi_lo_hi_2, taken_rviImm_hi_lo_lo_2}; // @[RocketCore.scala:1355:8]
wire [11:0] taken_rviImm_hi_hi_2 = {taken_rviImm_hi_hi_hi_2, taken_rviImm_hi_hi_lo_2}; // @[RocketCore.scala:1355:8]
wire [20:0] taken_rviImm_hi_2 = {taken_rviImm_hi_hi_2, taken_rviImm_hi_lo_2}; // @[RocketCore.scala:1355:8]
wire [31:0] _taken_rviImm_T_6 = {taken_rviImm_hi_2, taken_rviImm_lo_2}; // @[RocketCore.scala:1355:8]
wire [31:0] _taken_rviImm_T_7 = _taken_rviImm_T_6; // @[RocketCore.scala:1355:{8,53}]
wire _taken_rviImm_sign_T_11 = _taken_rviImm_sign_T_10; // @[RocketCore.scala:1341:{44,49}]
wire taken_rviImm_sign_3 = _taken_rviImm_sign_T_11; // @[RocketCore.scala:1341:{19,49}]
wire taken_rviImm_hi_hi_hi_3 = taken_rviImm_sign_3; // @[RocketCore.scala:1341:19, :1355:8]
wire [10:0] _taken_rviImm_b30_20_T_11 = _taken_rviImm_b30_20_T_10; // @[RocketCore.scala:1342:{41,49}]
wire [10:0] taken_rviImm_b30_20_3 = {11{taken_rviImm_sign_3}}; // @[RocketCore.scala:1341:19, :1342:21]
wire [10:0] taken_rviImm_hi_hi_lo_3 = taken_rviImm_b30_20_3; // @[RocketCore.scala:1342:21, :1355:8]
wire [7:0] _taken_rviImm_b19_12_T_19 = _taken_rviImm_b19_12_T_18; // @[RocketCore.scala:1343:{65,73}]
wire [7:0] taken_rviImm_b19_12_3 = {8{taken_rviImm_sign_3}}; // @[RocketCore.scala:1341:19, :1343:21]
wire [7:0] taken_rviImm_hi_lo_hi_3 = taken_rviImm_b19_12_3; // @[RocketCore.scala:1343:21, :1355:8]
wire _taken_rviImm_b11_T_38 = _taken_rviImm_b11_T_37; // @[RocketCore.scala:1345:{39,44}]
wire _taken_rviImm_b11_T_41 = _taken_rviImm_b11_T_40; // @[RocketCore.scala:1346:{39,43}]
wire _taken_rviImm_b11_T_42 = _taken_rviImm_b11_T_41; // @[RocketCore.scala:1346:{18,43}]
wire _taken_rviImm_b11_T_43 = _taken_rviImm_b11_T_42; // @[RocketCore.scala:1345:18, :1346:18]
wire taken_rviImm_b11_3 = _taken_rviImm_b11_T_43; // @[RocketCore.scala:1344:18, :1345:18]
wire taken_rviImm_hi_lo_lo_3 = taken_rviImm_b11_3; // @[RocketCore.scala:1344:18, :1355:8]
wire [5:0] taken_rviImm_b10_5_3 = _taken_rviImm_b10_5_T_15; // @[RocketCore.scala:1347:{20,62}]
wire [3:0] _taken_rviImm_b4_1_T_39 = _taken_rviImm_b4_1_T_34; // @[RocketCore.scala:1349:{19,57}]
wire [3:0] _taken_rviImm_b4_1_T_38 = _taken_rviImm_b4_1_T_37; // @[RocketCore.scala:1350:{19,52}]
wire [3:0] taken_rviImm_b4_1_3 = _taken_rviImm_b4_1_T_39; // @[RocketCore.scala:1348:19, :1349:19]
wire [9:0] taken_rviImm_lo_hi_3 = {taken_rviImm_b10_5_3, taken_rviImm_b4_1_3}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8]
wire [10:0] taken_rviImm_lo_3 = {taken_rviImm_lo_hi_3, 1'h0}; // @[RocketCore.scala:1355:8]
wire [8:0] taken_rviImm_hi_lo_3 = {taken_rviImm_hi_lo_hi_3, taken_rviImm_hi_lo_lo_3}; // @[RocketCore.scala:1355:8]
wire [11:0] taken_rviImm_hi_hi_3 = {taken_rviImm_hi_hi_hi_3, taken_rviImm_hi_hi_lo_3}; // @[RocketCore.scala:1355:8]
wire [20:0] taken_rviImm_hi_3 = {taken_rviImm_hi_hi_3, taken_rviImm_hi_lo_3}; // @[RocketCore.scala:1355:8]
wire [31:0] _taken_rviImm_T_8 = {taken_rviImm_hi_3, taken_rviImm_lo_3}; // @[RocketCore.scala:1355:8]
wire [31:0] _taken_rviImm_T_9 = _taken_rviImm_T_8; // @[RocketCore.scala:1355:{8,53}]
wire [31:0] taken_rviImm_1 = _taken_rviImm_T_5 ? _taken_rviImm_T_7 : _taken_rviImm_T_9; // @[RocketCore.scala:1355:53]
wire taken_predict_taken_1 = _taken_predict_taken_T_1; // @[Frontend.scala:253:54]
wire _taken_taken_T_10 = taken_rviBranch_1 & taken_predict_taken_1; // @[Frontend.scala:239:36, :253:54, :255:53]
wire _taken_taken_T_11 = _taken_taken_T_9 | _taken_taken_T_10; // @[Frontend.scala:255:{29,40,53}]
wire _taken_taken_T_12 = taken_prevRVI_1 & _taken_taken_T_11; // @[Frontend.scala:234:31, :255:{17,40}]
wire _taken_taken_T_13 = taken_rvcJump_1 | taken_rvcJALR_1; // @[Frontend.scala:246:47, :250:49, :256:27]
wire _taken_taken_T_14 = _taken_taken_T_13 | taken_rvcJR_1; // @[Frontend.scala:248:46, :256:{27,38}]
wire _taken_taken_T_15 = taken_rvcBranch_1 & taken_predict_taken_1; // @[Frontend.scala:244:52, :253:54, :256:60]
wire _taken_taken_T_16 = _taken_taken_T_14 | _taken_taken_T_15; // @[Frontend.scala:256:{38,47,60}]
wire _taken_taken_T_17 = taken_valid_1 & _taken_taken_T_16; // @[Frontend.scala:235:44, :256:{15,47}]
wire taken_taken_1 = _taken_taken_T_12 | _taken_taken_T_17; // @[Frontend.scala:255:{17,71}, :256:15]
wire _taken_predictReturn_T_3 = taken_prevRVI_1 & taken_rviReturn_1; // @[Frontend.scala:234:31, :242:46, :257:61]
wire _taken_predictReturn_T_4 = taken_valid_1 & taken_rvcReturn_1; // @[Frontend.scala:235:44, :249:29, :257:83]
wire _taken_predictReturn_T_5 = _taken_predictReturn_T_3 | _taken_predictReturn_T_4; // @[Frontend.scala:257:{61,74,83}]
wire taken_predictReturn_1 = _btb_io_ras_head_valid & _taken_predictReturn_T_5; // @[Frontend.scala:198:21, :257:{49,74}]
wire _taken_predictJump_T_2 = taken_prevRVI_1 & taken_rviJump_1; // @[Frontend.scala:234:31, :240:34, :258:33]
wire _taken_predictJump_T_3 = taken_valid_1 & taken_rvcJump_1; // @[Frontend.scala:235:44, :246:47, :258:53]
wire taken_predictJump_1 = _taken_predictJump_T_2 | _taken_predictJump_T_3; // @[Frontend.scala:258:{33,44,53}]
wire _GEN_9 = taken_prevRVI_1 & taken_rviBranch_1; // @[Frontend.scala:234:31, :239:36, :259:53]
wire _taken_predictBranch_T_3; // @[Frontend.scala:259:53]
assign _taken_predictBranch_T_3 = _GEN_9; // @[Frontend.scala:259:53]
wire _taken_T_48; // @[Frontend.scala:294:23]
assign _taken_T_48 = _GEN_9; // @[Frontend.scala:259:53, :294:23]
wire _GEN_10 = taken_valid_1 & taken_rvcBranch_1; // @[Frontend.scala:235:44, :244:52, :259:75]
wire _taken_predictBranch_T_4; // @[Frontend.scala:259:75]
assign _taken_predictBranch_T_4 = _GEN_10; // @[Frontend.scala:259:75]
wire _taken_T_49; // @[Frontend.scala:294:45]
assign _taken_T_49 = _GEN_10; // @[Frontend.scala:259:75, :294:45]
wire _taken_predictBranch_T_5 = _taken_predictBranch_T_3 | _taken_predictBranch_T_4; // @[Frontend.scala:259:{53,66,75}]
wire taken_predictBranch_1 = taken_predict_taken_1 & _taken_predictBranch_T_5; // @[Frontend.scala:253:54, :259:{41,66}]
wire _taken_T_31 = _taken_T_29 & _taken_T_30; // @[Frontend.scala:261:{22,43,69}]
wire _taken_T_32 = _taken_T_31 & taken_valid_1; // @[Frontend.scala:235:44, :261:{43,79}]
wire _taken_T_33 = ~taken_rvc_1; // @[Frontend.scala:233:45, :261:91]
wire _taken_T_34 = _taken_T_32 & _taken_T_33; // @[Frontend.scala:261:{79,88,91}]
assign _taken_T_35 = ~_taken_T_28; // @[Frontend.scala:270:13, :313:51]
assign taken_idx = _taken_T_35; // @[Frontend.scala:223:25, :270:13]
assign after_idx = _taken_T_35 ? 2'h2 : 2'h1; // @[Frontend.scala:224:25, :270:{13,25}, :272:19]
wire _taken_btb_io_ras_update_valid_T_10 = ~wrong_path; // @[Frontend.scala:126:27, :273:54, :319:52]
wire _taken_btb_io_ras_update_valid_T_11 = _taken_btb_io_ras_update_valid_T_9 & _taken_btb_io_ras_update_valid_T_10; // @[Decoupled.scala:51:35]
wire _taken_btb_io_ras_update_valid_T_12 = taken_rviCall_1 | taken_rviReturn_1; // @[Frontend.scala:242:46, :243:42, :273:90]
wire _taken_btb_io_ras_update_valid_T_13 = taken_prevRVI_1 & _taken_btb_io_ras_update_valid_T_12; // @[Frontend.scala:234:31, :273:{78,90}]
wire _taken_btb_io_ras_update_valid_T_14 = taken_rvcCall_1 | taken_rvcReturn_1; // @[Frontend.scala:249:29, :251:28, :273:125]
wire _taken_btb_io_ras_update_valid_T_15 = taken_valid_1 & _taken_btb_io_ras_update_valid_T_14; // @[Frontend.scala:235:44, :273:{113,125}]
wire _taken_btb_io_ras_update_valid_T_16 = _taken_btb_io_ras_update_valid_T_13 | _taken_btb_io_ras_update_valid_T_15; // @[Frontend.scala:273:{78,104,113}]
wire _taken_btb_io_ras_update_valid_T_17 = _taken_btb_io_ras_update_valid_T_11 & _taken_btb_io_ras_update_valid_T_16; // @[Frontend.scala:273:{51,66,104}]
wire _taken_btb_io_ras_update_bits_cfiType_T_8 = taken_prevRVI_1 ? taken_rviReturn_1 : taken_rvcReturn_1; // @[Frontend.scala:234:31, :242:46, :249:29, :274:50]
wire _taken_btb_io_ras_update_bits_cfiType_T_9 = taken_prevRVI_1 ? taken_rviCall_1 : taken_rvcCall_1; // @[Frontend.scala:234:31, :243:42, :251:28, :275:50]
wire _taken_btb_io_ras_update_bits_cfiType_T_10 = taken_prevRVI_1 ? taken_rviBranch_1 : taken_rvcBranch_1; // @[Frontend.scala:234:31, :239:36, :244:52, :276:50]
wire _taken_btb_io_ras_update_bits_cfiType_T_12 = _taken_btb_io_ras_update_bits_cfiType_T_10; // @[Frontend.scala:276:{50,82}]
wire _taken_btb_io_ras_update_bits_cfiType_T_13 = ~_taken_btb_io_ras_update_bits_cfiType_T_12; // @[Frontend.scala:276:{46,82}]
wire [1:0] _taken_btb_io_ras_update_bits_cfiType_T_14 = _taken_btb_io_ras_update_bits_cfiType_T_9 ? 2'h2 : {1'h0, _taken_btb_io_ras_update_bits_cfiType_T_13}; // @[Frontend.scala:275:{46,50}, :276:46]
wire [1:0] _taken_btb_io_ras_update_bits_cfiType_T_15 = _taken_btb_io_ras_update_bits_cfiType_T_8 ? 2'h3 : _taken_btb_io_ras_update_bits_cfiType_T_14; // @[Frontend.scala:274:{46,50}, :275:46]
assign btb_io_ras_update_bits_cfiType = _taken_T_35 ? _taken_btb_io_ras_update_bits_cfiType_T_15 : _taken_btb_io_ras_update_bits_cfiType_T_7; // @[Frontend.scala:270:{13,25}, :274:{40,46}]
wire _taken_T_36 = ~s2_btb_taken; // @[Frontend.scala:120:40, :279:15]
wire _taken_T_38 = _taken_T_37 & taken_taken_1; // @[Decoupled.scala:51:35]
wire _taken_T_39 = ~taken_predictBranch_1; // @[Frontend.scala:259:41, :280:44]
wire _taken_T_40 = _taken_T_38 & _taken_T_39; // @[Frontend.scala:280:{32,41,44}]
wire _taken_T_41 = ~taken_predictJump_1; // @[Frontend.scala:258:44, :280:62]
wire _taken_T_42 = _taken_T_40 & _taken_T_41; // @[Frontend.scala:280:{41,59,62}]
wire _taken_T_43 = ~taken_predictReturn_1; // @[Frontend.scala:257:49, :280:78]
wire _taken_T_44 = _taken_T_42 & _taken_T_43; // @[Frontend.scala:280:{59,75,78}]
wire _taken_T_45 = s2_valid & taken_predictReturn_1; // @[Frontend.scala:108:25, :257:49, :283:26]
assign useRAS = _taken_T_35 & _taken_T_36 & _taken_T_45 | _taken_T_7 & _taken_T_16; // @[Frontend.scala:225:29, :270:{13,25}, :279:{15,30}, :283:{26,44}, :284:20]
wire _taken_T_46 = taken_predictBranch_1 | taken_predictJump_1; // @[Frontend.scala:258:44, :259:41, :286:44]
wire _taken_T_47 = s2_valid & _taken_T_46; // @[Frontend.scala:108:25, :286:{26,44}]
wire [39:0] taken_pc_1 = {s2_base_pc[39:2], s2_base_pc[1:0] | 2'h2}; // @[Frontend.scala:222:22, :287:33, :323:50]
wire [40:0] _taken_npc_T_5 = {1'h0, taken_pc_1} - 41'h2; // @[Frontend.scala:287:33, :290:36]
wire [39:0] _taken_npc_T_6 = _taken_npc_T_5[39:0]; // @[Frontend.scala:290:36]
wire [39:0] _taken_npc_T_7 = taken_prevRVI_1 ? _taken_npc_T_6 : taken_pc_1; // @[Frontend.scala:234:31, :287:33, :290:{23,36}]
wire [39:0] _taken_npc_T_8 = _taken_npc_T_7; // @[Frontend.scala:290:{23,59}]
wire [31:0] _taken_npc_T_9 = taken_prevRVI_1 ? taken_rviImm_1 : {{11{taken_rvcImm_1[20]}}, taken_rvcImm_1}; // @[Frontend.scala:234:31, :247:23, :252:23, :290:71]
wire [40:0] _taken_npc_T_10 = {_taken_npc_T_8[39], _taken_npc_T_8} + {{9{_taken_npc_T_9[31]}}, _taken_npc_T_9}; // @[Frontend.scala:290:{59,66,71}]
wire [39:0] _taken_npc_T_11 = _taken_npc_T_10[39:0]; // @[Frontend.scala:290:66]
wire [39:0] taken_npc_1 = _taken_npc_T_11; // @[Frontend.scala:290:66]
wire [39:0] _taken_predicted_npc_T_1 = taken_npc_1; // @[Frontend.scala:290:66, :291:34]
wire _taken_T_50 = _taken_T_48 | _taken_T_49; // @[Frontend.scala:294:{23,36,45}]
wire _taken_btb_io_bht_advance_valid_T_4 = ~wrong_path; // @[Frontend.scala:126:27, :295:57, :319:52]
wire _taken_btb_io_bht_advance_valid_T_5 = _taken_btb_io_bht_advance_valid_T_3 & _taken_btb_io_bht_advance_valid_T_4; // @[Decoupled.scala:51:35]
wire _taken_T_51 = ~s2_btb_resp_valid; // @[Frontend.scala:118:44, :298:15]
wire _taken_T_53 = taken_predictBranch_1 & _taken_T_52; // @[Frontend.scala:259:41, :298:52]
wire _taken_T_54 = _taken_T_53 | taken_predictJump_1; // @[Frontend.scala:258:44, :298:{52,91}]
wire _taken_T_55 = _taken_T_54 | taken_predictReturn_1; // @[Frontend.scala:257:49, :298:{91,106}]
wire _taken_T_56 = _taken_T_51 & _taken_T_55; // @[Frontend.scala:298:{15,34,106}]
assign updateBTB = _taken_T_35 & _taken_T_56 | _taken_T_27; // @[Frontend.scala:226:32, :270:{13,25}, :298:{34,125}, :299:21]
wire _taken_T_58 = ~_taken_T_28; // @[Frontend.scala:270:13, :306:26, :313:51]
wire _taken_T_59 = taken_valid_1 & _taken_T_58; // @[Frontend.scala:235:44, :306:{23,26}]
wire _taken_T_60 = ~taken_rvc_1; // @[Frontend.scala:233:45, :261:91, :306:40]
wire _taken_T_61 = _taken_T_59 & _taken_T_60; // @[Frontend.scala:306:{23,37,40}]
wire [15:0] _taken_s2_partial_insn_T = {taken_bits_1[15:2], 2'h3}; // @[Frontend.scala:236:37, :308:37]
wire taken = _taken_T_28 | taken_taken_1; // @[Frontend.scala:255:71, :311:19, :313:51]
assign predicted_npc = useRAS ? {1'h0, _btb_io_ras_head_bits} : _taken_T_35 & _taken_T_36 & _taken_T_47 ? _taken_predicted_npc_T_1 : _taken_T_7 & _taken_T_18 ? _taken_predicted_npc_T : predicted_taken ? _predicted_npc_T_1 : ntpc; // @[package.scala:132:15]
wire _GEN_11 = ~s2_btb_taken & taken; // @[Frontend.scala:120:40, :191:22, :311:19, :336:{11,26}, :337:20, :338:34]
assign s2_redirect = ~s2_btb_taken & taken & _T_37 | io_cpu_req_valid_0; // @[Decoupled.scala:51:35] |
Generate the Verilog code corresponding to this FIRRTL code module TLBToNoC :
input clock : Clock
input reset : Reset
output io : { flip protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}}
inst q of Queue1_TLBundleB_a32d128s7k6z4c
connect q.clock, clock
connect q.reset, reset
wire has_body : UInt<1>
node _head_T = and(q.io.deq.ready, q.io.deq.valid)
node _head_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size)
node _head_beats1_decode_T_1 = bits(_head_beats1_decode_T, 11, 0)
node _head_beats1_decode_T_2 = not(_head_beats1_decode_T_1)
node head_beats1_decode = shr(_head_beats1_decode_T_2, 4)
node _head_beats1_opdata_T = bits(q.io.deq.bits.opcode, 2, 2)
node head_beats1_opdata = eq(_head_beats1_opdata_T, UInt<1>(0h0))
node head_beats1 = mux(UInt<1>(0h0), head_beats1_decode, UInt<1>(0h0))
regreset head_counter : UInt<8>, clock, reset, UInt<8>(0h0)
node _head_counter1_T = sub(head_counter, UInt<1>(0h1))
node head_counter1 = tail(_head_counter1_T, 1)
node head = eq(head_counter, UInt<1>(0h0))
node _head_last_T = eq(head_counter, UInt<1>(0h1))
node _head_last_T_1 = eq(head_beats1, UInt<1>(0h0))
node head_last = or(_head_last_T, _head_last_T_1)
node head_done = and(head_last, _head_T)
node _head_count_T = not(head_counter1)
node head_count = and(head_beats1, _head_count_T)
when _head_T :
node _head_counter_T = mux(head, head_beats1, head_counter1)
connect head_counter, _head_counter_T
node _tail_T = and(q.io.deq.ready, q.io.deq.valid)
node _tail_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size)
node _tail_beats1_decode_T_1 = bits(_tail_beats1_decode_T, 11, 0)
node _tail_beats1_decode_T_2 = not(_tail_beats1_decode_T_1)
node tail_beats1_decode = shr(_tail_beats1_decode_T_2, 4)
node _tail_beats1_opdata_T = bits(q.io.deq.bits.opcode, 2, 2)
node tail_beats1_opdata = eq(_tail_beats1_opdata_T, UInt<1>(0h0))
node tail_beats1 = mux(UInt<1>(0h0), tail_beats1_decode, UInt<1>(0h0))
regreset tail_counter : UInt<8>, clock, reset, UInt<8>(0h0)
node _tail_counter1_T = sub(tail_counter, UInt<1>(0h1))
node tail_counter1 = tail(_tail_counter1_T, 1)
node tail_first = eq(tail_counter, UInt<1>(0h0))
node _tail_last_T = eq(tail_counter, UInt<1>(0h1))
node _tail_last_T_1 = eq(tail_beats1, UInt<1>(0h0))
node tail = or(_tail_last_T, _tail_last_T_1)
node tail_done = and(tail, _tail_T)
node _tail_count_T = not(tail_counter1)
node tail_count = and(tail_beats1, _tail_count_T)
when _tail_T :
node _tail_counter_T = mux(tail_first, tail_beats1, tail_counter1)
connect tail_counter, _tail_counter_T
node body_hi = cat(q.io.deq.bits.mask, q.io.deq.bits.data)
node body = cat(body_hi, q.io.deq.bits.corrupt)
node const_lo = cat(q.io.deq.bits.source, q.io.deq.bits.address)
node const_hi_hi = cat(q.io.deq.bits.opcode, q.io.deq.bits.param)
node const_hi = cat(const_hi_hi, q.io.deq.bits.size)
node const = cat(const_hi, const_lo)
regreset is_body : UInt<1>, clock, reset, UInt<1>(0h0)
connect io.flit.valid, q.io.deq.valid
node _q_io_deq_ready_T = eq(has_body, UInt<1>(0h0))
node _q_io_deq_ready_T_1 = or(is_body, _q_io_deq_ready_T)
node _q_io_deq_ready_T_2 = and(io.flit.ready, _q_io_deq_ready_T_1)
connect q.io.deq.ready, _q_io_deq_ready_T_2
node _io_flit_bits_head_T = eq(is_body, UInt<1>(0h0))
node _io_flit_bits_head_T_1 = and(head, _io_flit_bits_head_T)
connect io.flit.bits.head, _io_flit_bits_head_T_1
node _io_flit_bits_tail_T = eq(has_body, UInt<1>(0h0))
node _io_flit_bits_tail_T_1 = or(is_body, _io_flit_bits_tail_T)
node _io_flit_bits_tail_T_2 = and(tail, _io_flit_bits_tail_T_1)
connect io.flit.bits.tail, _io_flit_bits_tail_T_2
node _io_flit_bits_egress_id_requestOH_uncommonBits_T = or(q.io.deq.bits.source, UInt<5>(0h0))
node io_flit_bits_egress_id_requestOH_uncommonBits = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T, 4, 0)
node _io_flit_bits_egress_id_requestOH_T = shr(q.io.deq.bits.source, 5)
node _io_flit_bits_egress_id_requestOH_T_1 = eq(_io_flit_bits_egress_id_requestOH_T, UInt<1>(0h0))
node _io_flit_bits_egress_id_requestOH_T_2 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits)
node _io_flit_bits_egress_id_requestOH_T_3 = and(_io_flit_bits_egress_id_requestOH_T_1, _io_flit_bits_egress_id_requestOH_T_2)
node _io_flit_bits_egress_id_requestOH_T_4 = leq(io_flit_bits_egress_id_requestOH_uncommonBits, UInt<5>(0h1f))
node io_flit_bits_egress_id_requestOH_0 = and(_io_flit_bits_egress_id_requestOH_T_3, _io_flit_bits_egress_id_requestOH_T_4)
node _io_flit_bits_egress_id_requestOH_uncommonBits_T_1 = or(q.io.deq.bits.source, UInt<2>(0h0))
node io_flit_bits_egress_id_requestOH_uncommonBits_1 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_1, 1, 0)
node _io_flit_bits_egress_id_requestOH_T_5 = shr(q.io.deq.bits.source, 2)
node _io_flit_bits_egress_id_requestOH_T_6 = eq(_io_flit_bits_egress_id_requestOH_T_5, UInt<5>(0h13))
node _io_flit_bits_egress_id_requestOH_T_7 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_1)
node _io_flit_bits_egress_id_requestOH_T_8 = and(_io_flit_bits_egress_id_requestOH_T_6, _io_flit_bits_egress_id_requestOH_T_7)
node _io_flit_bits_egress_id_requestOH_T_9 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_1, UInt<2>(0h3))
node io_flit_bits_egress_id_requestOH_1 = and(_io_flit_bits_egress_id_requestOH_T_8, _io_flit_bits_egress_id_requestOH_T_9)
node _io_flit_bits_egress_id_requestOH_uncommonBits_T_2 = or(q.io.deq.bits.source, UInt<2>(0h0))
node io_flit_bits_egress_id_requestOH_uncommonBits_2 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_2, 1, 0)
node _io_flit_bits_egress_id_requestOH_T_10 = shr(q.io.deq.bits.source, 2)
node _io_flit_bits_egress_id_requestOH_T_11 = eq(_io_flit_bits_egress_id_requestOH_T_10, UInt<5>(0h12))
node _io_flit_bits_egress_id_requestOH_T_12 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_2)
node _io_flit_bits_egress_id_requestOH_T_13 = and(_io_flit_bits_egress_id_requestOH_T_11, _io_flit_bits_egress_id_requestOH_T_12)
node _io_flit_bits_egress_id_requestOH_T_14 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_2, UInt<2>(0h3))
node io_flit_bits_egress_id_requestOH_2 = and(_io_flit_bits_egress_id_requestOH_T_13, _io_flit_bits_egress_id_requestOH_T_14)
node _io_flit_bits_egress_id_requestOH_uncommonBits_T_3 = or(q.io.deq.bits.source, UInt<2>(0h0))
node io_flit_bits_egress_id_requestOH_uncommonBits_3 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_3, 1, 0)
node _io_flit_bits_egress_id_requestOH_T_15 = shr(q.io.deq.bits.source, 2)
node _io_flit_bits_egress_id_requestOH_T_16 = eq(_io_flit_bits_egress_id_requestOH_T_15, UInt<5>(0h11))
node _io_flit_bits_egress_id_requestOH_T_17 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_3)
node _io_flit_bits_egress_id_requestOH_T_18 = and(_io_flit_bits_egress_id_requestOH_T_16, _io_flit_bits_egress_id_requestOH_T_17)
node _io_flit_bits_egress_id_requestOH_T_19 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_3, UInt<2>(0h3))
node io_flit_bits_egress_id_requestOH_3 = and(_io_flit_bits_egress_id_requestOH_T_18, _io_flit_bits_egress_id_requestOH_T_19)
node _io_flit_bits_egress_id_requestOH_uncommonBits_T_4 = or(q.io.deq.bits.source, UInt<2>(0h0))
node io_flit_bits_egress_id_requestOH_uncommonBits_4 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_4, 1, 0)
node _io_flit_bits_egress_id_requestOH_T_20 = shr(q.io.deq.bits.source, 2)
node _io_flit_bits_egress_id_requestOH_T_21 = eq(_io_flit_bits_egress_id_requestOH_T_20, UInt<5>(0h10))
node _io_flit_bits_egress_id_requestOH_T_22 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_4)
node _io_flit_bits_egress_id_requestOH_T_23 = and(_io_flit_bits_egress_id_requestOH_T_21, _io_flit_bits_egress_id_requestOH_T_22)
node _io_flit_bits_egress_id_requestOH_T_24 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_4, UInt<2>(0h3))
node io_flit_bits_egress_id_requestOH_4 = and(_io_flit_bits_egress_id_requestOH_T_23, _io_flit_bits_egress_id_requestOH_T_24)
node _io_flit_bits_egress_id_requestOH_uncommonBits_T_5 = or(q.io.deq.bits.source, UInt<2>(0h0))
node io_flit_bits_egress_id_requestOH_uncommonBits_5 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_5, 1, 0)
node _io_flit_bits_egress_id_requestOH_T_25 = shr(q.io.deq.bits.source, 2)
node _io_flit_bits_egress_id_requestOH_T_26 = eq(_io_flit_bits_egress_id_requestOH_T_25, UInt<4>(0hf))
node _io_flit_bits_egress_id_requestOH_T_27 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_5)
node _io_flit_bits_egress_id_requestOH_T_28 = and(_io_flit_bits_egress_id_requestOH_T_26, _io_flit_bits_egress_id_requestOH_T_27)
node _io_flit_bits_egress_id_requestOH_T_29 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_5, UInt<2>(0h3))
node io_flit_bits_egress_id_requestOH_5 = and(_io_flit_bits_egress_id_requestOH_T_28, _io_flit_bits_egress_id_requestOH_T_29)
node _io_flit_bits_egress_id_requestOH_uncommonBits_T_6 = or(q.io.deq.bits.source, UInt<2>(0h0))
node io_flit_bits_egress_id_requestOH_uncommonBits_6 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_6, 1, 0)
node _io_flit_bits_egress_id_requestOH_T_30 = shr(q.io.deq.bits.source, 2)
node _io_flit_bits_egress_id_requestOH_T_31 = eq(_io_flit_bits_egress_id_requestOH_T_30, UInt<4>(0he))
node _io_flit_bits_egress_id_requestOH_T_32 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_6)
node _io_flit_bits_egress_id_requestOH_T_33 = and(_io_flit_bits_egress_id_requestOH_T_31, _io_flit_bits_egress_id_requestOH_T_32)
node _io_flit_bits_egress_id_requestOH_T_34 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_6, UInt<2>(0h3))
node io_flit_bits_egress_id_requestOH_6 = and(_io_flit_bits_egress_id_requestOH_T_33, _io_flit_bits_egress_id_requestOH_T_34)
node _io_flit_bits_egress_id_requestOH_uncommonBits_T_7 = or(q.io.deq.bits.source, UInt<2>(0h0))
node io_flit_bits_egress_id_requestOH_uncommonBits_7 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_7, 1, 0)
node _io_flit_bits_egress_id_requestOH_T_35 = shr(q.io.deq.bits.source, 2)
node _io_flit_bits_egress_id_requestOH_T_36 = eq(_io_flit_bits_egress_id_requestOH_T_35, UInt<4>(0hd))
node _io_flit_bits_egress_id_requestOH_T_37 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_7)
node _io_flit_bits_egress_id_requestOH_T_38 = and(_io_flit_bits_egress_id_requestOH_T_36, _io_flit_bits_egress_id_requestOH_T_37)
node _io_flit_bits_egress_id_requestOH_T_39 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_7, UInt<2>(0h3))
node io_flit_bits_egress_id_requestOH_7 = and(_io_flit_bits_egress_id_requestOH_T_38, _io_flit_bits_egress_id_requestOH_T_39)
node _io_flit_bits_egress_id_requestOH_uncommonBits_T_8 = or(q.io.deq.bits.source, UInt<2>(0h0))
node io_flit_bits_egress_id_requestOH_uncommonBits_8 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_8, 1, 0)
node _io_flit_bits_egress_id_requestOH_T_40 = shr(q.io.deq.bits.source, 2)
node _io_flit_bits_egress_id_requestOH_T_41 = eq(_io_flit_bits_egress_id_requestOH_T_40, UInt<4>(0hc))
node _io_flit_bits_egress_id_requestOH_T_42 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_8)
node _io_flit_bits_egress_id_requestOH_T_43 = and(_io_flit_bits_egress_id_requestOH_T_41, _io_flit_bits_egress_id_requestOH_T_42)
node _io_flit_bits_egress_id_requestOH_T_44 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_8, UInt<2>(0h3))
node io_flit_bits_egress_id_requestOH_8 = and(_io_flit_bits_egress_id_requestOH_T_43, _io_flit_bits_egress_id_requestOH_T_44)
node _io_flit_bits_egress_id_requestOH_uncommonBits_T_9 = or(q.io.deq.bits.source, UInt<2>(0h0))
node io_flit_bits_egress_id_requestOH_uncommonBits_9 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_9, 1, 0)
node _io_flit_bits_egress_id_requestOH_T_45 = shr(q.io.deq.bits.source, 2)
node _io_flit_bits_egress_id_requestOH_T_46 = eq(_io_flit_bits_egress_id_requestOH_T_45, UInt<4>(0hb))
node _io_flit_bits_egress_id_requestOH_T_47 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_9)
node _io_flit_bits_egress_id_requestOH_T_48 = and(_io_flit_bits_egress_id_requestOH_T_46, _io_flit_bits_egress_id_requestOH_T_47)
node _io_flit_bits_egress_id_requestOH_T_49 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_9, UInt<2>(0h3))
node io_flit_bits_egress_id_requestOH_9 = and(_io_flit_bits_egress_id_requestOH_T_48, _io_flit_bits_egress_id_requestOH_T_49)
node _io_flit_bits_egress_id_requestOH_uncommonBits_T_10 = or(q.io.deq.bits.source, UInt<2>(0h0))
node io_flit_bits_egress_id_requestOH_uncommonBits_10 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_10, 1, 0)
node _io_flit_bits_egress_id_requestOH_T_50 = shr(q.io.deq.bits.source, 2)
node _io_flit_bits_egress_id_requestOH_T_51 = eq(_io_flit_bits_egress_id_requestOH_T_50, UInt<4>(0ha))
node _io_flit_bits_egress_id_requestOH_T_52 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_10)
node _io_flit_bits_egress_id_requestOH_T_53 = and(_io_flit_bits_egress_id_requestOH_T_51, _io_flit_bits_egress_id_requestOH_T_52)
node _io_flit_bits_egress_id_requestOH_T_54 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_10, UInt<2>(0h3))
node io_flit_bits_egress_id_requestOH_10 = and(_io_flit_bits_egress_id_requestOH_T_53, _io_flit_bits_egress_id_requestOH_T_54)
node _io_flit_bits_egress_id_requestOH_uncommonBits_T_11 = or(q.io.deq.bits.source, UInt<2>(0h0))
node io_flit_bits_egress_id_requestOH_uncommonBits_11 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_11, 1, 0)
node _io_flit_bits_egress_id_requestOH_T_55 = shr(q.io.deq.bits.source, 2)
node _io_flit_bits_egress_id_requestOH_T_56 = eq(_io_flit_bits_egress_id_requestOH_T_55, UInt<4>(0h9))
node _io_flit_bits_egress_id_requestOH_T_57 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_11)
node _io_flit_bits_egress_id_requestOH_T_58 = and(_io_flit_bits_egress_id_requestOH_T_56, _io_flit_bits_egress_id_requestOH_T_57)
node _io_flit_bits_egress_id_requestOH_T_59 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_11, UInt<2>(0h3))
node io_flit_bits_egress_id_requestOH_11 = and(_io_flit_bits_egress_id_requestOH_T_58, _io_flit_bits_egress_id_requestOH_T_59)
node _io_flit_bits_egress_id_requestOH_uncommonBits_T_12 = or(q.io.deq.bits.source, UInt<2>(0h0))
node io_flit_bits_egress_id_requestOH_uncommonBits_12 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_12, 1, 0)
node _io_flit_bits_egress_id_requestOH_T_60 = shr(q.io.deq.bits.source, 2)
node _io_flit_bits_egress_id_requestOH_T_61 = eq(_io_flit_bits_egress_id_requestOH_T_60, UInt<4>(0h8))
node _io_flit_bits_egress_id_requestOH_T_62 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_12)
node _io_flit_bits_egress_id_requestOH_T_63 = and(_io_flit_bits_egress_id_requestOH_T_61, _io_flit_bits_egress_id_requestOH_T_62)
node _io_flit_bits_egress_id_requestOH_T_64 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_12, UInt<2>(0h3))
node io_flit_bits_egress_id_requestOH_12 = and(_io_flit_bits_egress_id_requestOH_T_63, _io_flit_bits_egress_id_requestOH_T_64)
node _io_flit_bits_egress_id_T = mux(io_flit_bits_egress_id_requestOH_0, UInt<1>(0h0), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_1 = mux(io_flit_bits_egress_id_requestOH_1, UInt<1>(0h1), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_2 = mux(io_flit_bits_egress_id_requestOH_2, UInt<2>(0h2), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_3 = mux(io_flit_bits_egress_id_requestOH_3, UInt<2>(0h3), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_4 = mux(io_flit_bits_egress_id_requestOH_4, UInt<3>(0h4), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_5 = mux(io_flit_bits_egress_id_requestOH_5, UInt<3>(0h5), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_6 = mux(io_flit_bits_egress_id_requestOH_6, UInt<3>(0h6), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_7 = mux(io_flit_bits_egress_id_requestOH_7, UInt<3>(0h7), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_8 = mux(io_flit_bits_egress_id_requestOH_8, UInt<4>(0h8), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_9 = mux(io_flit_bits_egress_id_requestOH_9, UInt<4>(0h9), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_10 = mux(io_flit_bits_egress_id_requestOH_10, UInt<4>(0ha), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_11 = mux(io_flit_bits_egress_id_requestOH_11, UInt<4>(0hb), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_12 = mux(io_flit_bits_egress_id_requestOH_12, UInt<4>(0hc), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_13 = or(_io_flit_bits_egress_id_T, _io_flit_bits_egress_id_T_1)
node _io_flit_bits_egress_id_T_14 = or(_io_flit_bits_egress_id_T_13, _io_flit_bits_egress_id_T_2)
node _io_flit_bits_egress_id_T_15 = or(_io_flit_bits_egress_id_T_14, _io_flit_bits_egress_id_T_3)
node _io_flit_bits_egress_id_T_16 = or(_io_flit_bits_egress_id_T_15, _io_flit_bits_egress_id_T_4)
node _io_flit_bits_egress_id_T_17 = or(_io_flit_bits_egress_id_T_16, _io_flit_bits_egress_id_T_5)
node _io_flit_bits_egress_id_T_18 = or(_io_flit_bits_egress_id_T_17, _io_flit_bits_egress_id_T_6)
node _io_flit_bits_egress_id_T_19 = or(_io_flit_bits_egress_id_T_18, _io_flit_bits_egress_id_T_7)
node _io_flit_bits_egress_id_T_20 = or(_io_flit_bits_egress_id_T_19, _io_flit_bits_egress_id_T_8)
node _io_flit_bits_egress_id_T_21 = or(_io_flit_bits_egress_id_T_20, _io_flit_bits_egress_id_T_9)
node _io_flit_bits_egress_id_T_22 = or(_io_flit_bits_egress_id_T_21, _io_flit_bits_egress_id_T_10)
node _io_flit_bits_egress_id_T_23 = or(_io_flit_bits_egress_id_T_22, _io_flit_bits_egress_id_T_11)
node _io_flit_bits_egress_id_T_24 = or(_io_flit_bits_egress_id_T_23, _io_flit_bits_egress_id_T_12)
wire _io_flit_bits_egress_id_WIRE : UInt<4>
connect _io_flit_bits_egress_id_WIRE, _io_flit_bits_egress_id_T_24
connect io.flit.bits.egress_id, _io_flit_bits_egress_id_WIRE
node _io_flit_bits_payload_T = mux(is_body, body, const)
connect io.flit.bits.payload, _io_flit_bits_payload_T
node _T = and(io.flit.ready, io.flit.valid)
node _T_1 = and(_T, io.flit.bits.head)
when _T_1 :
connect is_body, UInt<1>(0h1)
node _T_2 = and(io.flit.ready, io.flit.valid)
node _T_3 = and(_T_2, io.flit.bits.tail)
when _T_3 :
connect is_body, UInt<1>(0h0)
node _has_body_opdata_T = bits(q.io.deq.bits.opcode, 2, 2)
node has_body_opdata = eq(_has_body_opdata_T, UInt<1>(0h0))
node _has_body_T = not(q.io.deq.bits.mask)
node _has_body_T_1 = neq(_has_body_T, UInt<1>(0h0))
node _has_body_T_2 = or(UInt<1>(0h0), _has_body_T_1)
connect has_body, _has_body_T_2
connect q.io.enq, io.protocol | module TLBToNoC( // @[TilelinkAdapters.scala:133:7]
input clock, // @[TilelinkAdapters.scala:133:7]
input reset, // @[TilelinkAdapters.scala:133:7]
input io_flit_ready, // @[TilelinkAdapters.scala:19:14]
output io_flit_valid, // @[TilelinkAdapters.scala:19:14]
output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14]
output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14]
output [144:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14]
output [3:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14]
);
wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17]
wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17]
wire [1:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17]
wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17]
wire [6:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17]
wire [31:0] _q_io_deq_bits_address; // @[TilelinkAdapters.scala:26:17]
wire [15:0] _q_io_deq_bits_mask; // @[TilelinkAdapters.scala:26:17]
wire [127:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17]
wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17]
reg [7:0] head_counter; // @[Edges.scala:229:27]
wire head = head_counter == 8'h0; // @[Edges.scala:229:27, :231:25]
reg is_body; // @[TilelinkAdapters.scala:39:24]
wire q_io_deq_ready = io_flit_ready & (is_body | (&_q_io_deq_bits_mask)); // @[TilelinkAdapters.scala:26:17, :39:24, :41:{35,47}, :139:70]
wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25]
wire io_flit_bits_tail_0 = is_body | (&_q_io_deq_bits_mask); // @[TilelinkAdapters.scala:26:17, :39:24, :44:47, :139:70]
wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[TilelinkAdapters.scala:133:7]
if (reset) begin // @[TilelinkAdapters.scala:133:7]
head_counter <= 8'h0; // @[Edges.scala:229:27]
is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :133:7]
end
else begin // @[TilelinkAdapters.scala:133:7]
if (q_io_deq_ready & _q_io_deq_valid) // @[Decoupled.scala:51:35]
head_counter <= head ? 8'h0 : head_counter - 8'h1; // @[Edges.scala:229:27, :230:28, :231:25, :236:21]
is_body <= ~(_GEN & io_flit_bits_tail_0) & (_GEN & io_flit_bits_head_0 | is_body); // @[Decoupled.scala:51:35]
end
always @(posedge) |
Generate the Verilog code corresponding to this FIRRTL code module PE_508 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_252
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<32>, clock
reg c2 : SInt<32>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node c1_sign = bits(io.in_d, 19, 19)
node c1_lo_lo_hi = cat(c1_sign, c1_sign)
node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign)
node c1_lo_hi_hi = cat(c1_sign, c1_sign)
node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign)
node c1_lo = cat(c1_lo_hi, c1_lo_lo)
node c1_hi_lo_hi = cat(c1_sign, c1_sign)
node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign)
node c1_hi_hi_hi = cat(c1_sign, c1_sign)
node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign)
node c1_hi = cat(c1_hi_hi, c1_hi_lo)
node _c1_T = cat(c1_hi, c1_lo)
node c1_lo_1 = asUInt(io.in_d)
node _c1_T_1 = cat(_c1_T, c1_lo_1)
wire _c1_WIRE : SInt<32>
node _c1_T_2 = asSInt(_c1_T_1)
connect _c1_WIRE, _c1_T_2
connect c1, _c1_WIRE
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node c2_sign = bits(io.in_d, 19, 19)
node c2_lo_lo_hi = cat(c2_sign, c2_sign)
node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign)
node c2_lo_hi_hi = cat(c2_sign, c2_sign)
node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign)
node c2_lo = cat(c2_lo_hi, c2_lo_lo)
node c2_hi_lo_hi = cat(c2_sign, c2_sign)
node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign)
node c2_hi_hi_hi = cat(c2_sign, c2_sign)
node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign)
node c2_hi = cat(c2_hi_hi, c2_hi_lo)
node _c2_T = cat(c2_hi, c2_lo)
node c2_lo_1 = asUInt(io.in_d)
node _c2_T_1 = cat(_c2_T, c2_lo_1)
wire _c2_WIRE : SInt<32>
node _c2_T_2 = asSInt(_c2_T_1)
connect _c2_WIRE, _c2_T_2
connect c2, _c2_WIRE
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h1), _T_4)
node _T_6 = or(UInt<1>(0h0), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_508( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_252 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_30 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<7>(0h4c))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<7>(0h4d))
node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h4e))
node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<7>(0h49))
node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<7>(0h4a))
node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _source_ok_T_41 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _source_ok_T_42 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _source_ok_T_46 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _source_ok_T_47 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _source_ok_T_48 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _source_ok_T_49 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _source_ok_T_50 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _source_ok_T_51 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _source_ok_T_52 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _source_ok_T_53 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _source_ok_T_54 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _source_ok_T_55 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _source_ok_T_56 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _source_ok_T_57 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _source_ok_T_58 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_T_59 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _source_ok_T_60 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _source_ok_T_61 = eq(io.in.a.bits.source, UInt<8>(0h80))
wire _source_ok_WIRE : UInt<1>[42]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
connect _source_ok_WIRE[7], _source_ok_T_27
connect _source_ok_WIRE[8], _source_ok_T_28
connect _source_ok_WIRE[9], _source_ok_T_29
connect _source_ok_WIRE[10], _source_ok_T_30
connect _source_ok_WIRE[11], _source_ok_T_31
connect _source_ok_WIRE[12], _source_ok_T_32
connect _source_ok_WIRE[13], _source_ok_T_33
connect _source_ok_WIRE[14], _source_ok_T_34
connect _source_ok_WIRE[15], _source_ok_T_35
connect _source_ok_WIRE[16], _source_ok_T_36
connect _source_ok_WIRE[17], _source_ok_T_37
connect _source_ok_WIRE[18], _source_ok_T_38
connect _source_ok_WIRE[19], _source_ok_T_39
connect _source_ok_WIRE[20], _source_ok_T_40
connect _source_ok_WIRE[21], _source_ok_T_41
connect _source_ok_WIRE[22], _source_ok_T_42
connect _source_ok_WIRE[23], _source_ok_T_43
connect _source_ok_WIRE[24], _source_ok_T_44
connect _source_ok_WIRE[25], _source_ok_T_45
connect _source_ok_WIRE[26], _source_ok_T_46
connect _source_ok_WIRE[27], _source_ok_T_47
connect _source_ok_WIRE[28], _source_ok_T_48
connect _source_ok_WIRE[29], _source_ok_T_49
connect _source_ok_WIRE[30], _source_ok_T_50
connect _source_ok_WIRE[31], _source_ok_T_51
connect _source_ok_WIRE[32], _source_ok_T_52
connect _source_ok_WIRE[33], _source_ok_T_53
connect _source_ok_WIRE[34], _source_ok_T_54
connect _source_ok_WIRE[35], _source_ok_T_55
connect _source_ok_WIRE[36], _source_ok_T_56
connect _source_ok_WIRE[37], _source_ok_T_57
connect _source_ok_WIRE[38], _source_ok_T_58
connect _source_ok_WIRE[39], _source_ok_T_59
connect _source_ok_WIRE[40], _source_ok_T_60
connect _source_ok_WIRE[41], _source_ok_T_61
node _source_ok_T_62 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE[2])
node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE[3])
node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE[4])
node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE[5])
node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE[6])
node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE[7])
node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE[8])
node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE[9])
node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE[10])
node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE[11])
node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE[12])
node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE[13])
node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE[14])
node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE[15])
node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE[16])
node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE[17])
node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE[18])
node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE[19])
node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE[20])
node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE[21])
node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE[22])
node _source_ok_T_84 = or(_source_ok_T_83, _source_ok_WIRE[23])
node _source_ok_T_85 = or(_source_ok_T_84, _source_ok_WIRE[24])
node _source_ok_T_86 = or(_source_ok_T_85, _source_ok_WIRE[25])
node _source_ok_T_87 = or(_source_ok_T_86, _source_ok_WIRE[26])
node _source_ok_T_88 = or(_source_ok_T_87, _source_ok_WIRE[27])
node _source_ok_T_89 = or(_source_ok_T_88, _source_ok_WIRE[28])
node _source_ok_T_90 = or(_source_ok_T_89, _source_ok_WIRE[29])
node _source_ok_T_91 = or(_source_ok_T_90, _source_ok_WIRE[30])
node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE[31])
node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE[32])
node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE[33])
node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE[34])
node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE[35])
node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE[36])
node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE[37])
node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE[38])
node _source_ok_T_100 = or(_source_ok_T_99, _source_ok_WIRE[39])
node _source_ok_T_101 = or(_source_ok_T_100, _source_ok_WIRE[40])
node source_ok = or(_source_ok_T_101, _source_ok_WIRE[41])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<7>(0h4c))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<7>(0h4d))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h4e))
node _T_81 = eq(_T_80, UInt<1>(0h0))
node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_83 = cvt(_T_82)
node _T_84 = and(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = asSInt(_T_84)
node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = or(_T_81, _T_86)
node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_89 = eq(_T_88, UInt<1>(0h0))
node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<1>(0h0)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_89, _T_94)
node _T_96 = eq(io.in.a.bits.source, UInt<7>(0h49))
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_99 = cvt(_T_98)
node _T_100 = and(_T_99, asSInt(UInt<1>(0h0)))
node _T_101 = asSInt(_T_100)
node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = or(_T_97, _T_102)
node _T_104 = eq(io.in.a.bits.source, UInt<7>(0h4a))
node _T_105 = eq(_T_104, UInt<1>(0h0))
node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_107 = cvt(_T_106)
node _T_108 = and(_T_107, asSInt(UInt<1>(0h0)))
node _T_109 = asSInt(_T_108)
node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = or(_T_105, _T_110)
node _T_112 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_113 = eq(_T_112, UInt<1>(0h0))
node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_115 = cvt(_T_114)
node _T_116 = and(_T_115, asSInt(UInt<1>(0h0)))
node _T_117 = asSInt(_T_116)
node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0)))
node _T_119 = or(_T_113, _T_118)
node _T_120 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_123 = cvt(_T_122)
node _T_124 = and(_T_123, asSInt(UInt<1>(0h0)))
node _T_125 = asSInt(_T_124)
node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0)))
node _T_127 = or(_T_121, _T_126)
node _T_128 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_129 = eq(_T_128, UInt<1>(0h0))
node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_131 = cvt(_T_130)
node _T_132 = and(_T_131, asSInt(UInt<1>(0h0)))
node _T_133 = asSInt(_T_132)
node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0)))
node _T_135 = or(_T_129, _T_134)
node _T_136 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_137 = eq(_T_136, UInt<1>(0h0))
node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_139 = cvt(_T_138)
node _T_140 = and(_T_139, asSInt(UInt<1>(0h0)))
node _T_141 = asSInt(_T_140)
node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0)))
node _T_143 = or(_T_137, _T_142)
node _T_144 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_145 = eq(_T_144, UInt<1>(0h0))
node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_147 = cvt(_T_146)
node _T_148 = and(_T_147, asSInt(UInt<1>(0h0)))
node _T_149 = asSInt(_T_148)
node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0)))
node _T_151 = or(_T_145, _T_150)
node _T_152 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_155 = cvt(_T_154)
node _T_156 = and(_T_155, asSInt(UInt<1>(0h0)))
node _T_157 = asSInt(_T_156)
node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0)))
node _T_159 = or(_T_153, _T_158)
node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_161 = eq(_T_160, UInt<1>(0h0))
node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_163 = cvt(_T_162)
node _T_164 = and(_T_163, asSInt(UInt<1>(0h0)))
node _T_165 = asSInt(_T_164)
node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0)))
node _T_167 = or(_T_161, _T_166)
node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_169 = eq(_T_168, UInt<1>(0h0))
node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_171 = cvt(_T_170)
node _T_172 = and(_T_171, asSInt(UInt<1>(0h0)))
node _T_173 = asSInt(_T_172)
node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0)))
node _T_175 = or(_T_169, _T_174)
node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_177 = eq(_T_176, UInt<1>(0h0))
node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_179 = cvt(_T_178)
node _T_180 = and(_T_179, asSInt(UInt<1>(0h0)))
node _T_181 = asSInt(_T_180)
node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0)))
node _T_183 = or(_T_177, _T_182)
node _T_184 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_185 = eq(_T_184, UInt<1>(0h0))
node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_187 = cvt(_T_186)
node _T_188 = and(_T_187, asSInt(UInt<1>(0h0)))
node _T_189 = asSInt(_T_188)
node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0)))
node _T_191 = or(_T_185, _T_190)
node _T_192 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_193 = eq(_T_192, UInt<1>(0h0))
node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_195 = cvt(_T_194)
node _T_196 = and(_T_195, asSInt(UInt<1>(0h0)))
node _T_197 = asSInt(_T_196)
node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0)))
node _T_199 = or(_T_193, _T_198)
node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_201 = eq(_T_200, UInt<1>(0h0))
node _T_202 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_203 = cvt(_T_202)
node _T_204 = and(_T_203, asSInt(UInt<1>(0h0)))
node _T_205 = asSInt(_T_204)
node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0)))
node _T_207 = or(_T_201, _T_206)
node _T_208 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_209 = eq(_T_208, UInt<1>(0h0))
node _T_210 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_211 = cvt(_T_210)
node _T_212 = and(_T_211, asSInt(UInt<1>(0h0)))
node _T_213 = asSInt(_T_212)
node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0)))
node _T_215 = or(_T_209, _T_214)
node _T_216 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_217 = eq(_T_216, UInt<1>(0h0))
node _T_218 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_219 = cvt(_T_218)
node _T_220 = and(_T_219, asSInt(UInt<1>(0h0)))
node _T_221 = asSInt(_T_220)
node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0)))
node _T_223 = or(_T_217, _T_222)
node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_225 = eq(_T_224, UInt<1>(0h0))
node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_227 = cvt(_T_226)
node _T_228 = and(_T_227, asSInt(UInt<1>(0h0)))
node _T_229 = asSInt(_T_228)
node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0)))
node _T_231 = or(_T_225, _T_230)
node _T_232 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_233 = eq(_T_232, UInt<1>(0h0))
node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_235 = cvt(_T_234)
node _T_236 = and(_T_235, asSInt(UInt<1>(0h0)))
node _T_237 = asSInt(_T_236)
node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0)))
node _T_239 = or(_T_233, _T_238)
node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_243 = cvt(_T_242)
node _T_244 = and(_T_243, asSInt(UInt<1>(0h0)))
node _T_245 = asSInt(_T_244)
node _T_246 = eq(_T_245, asSInt(UInt<1>(0h0)))
node _T_247 = or(_T_241, _T_246)
node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_249 = eq(_T_248, UInt<1>(0h0))
node _T_250 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_251 = cvt(_T_250)
node _T_252 = and(_T_251, asSInt(UInt<1>(0h0)))
node _T_253 = asSInt(_T_252)
node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0)))
node _T_255 = or(_T_249, _T_254)
node _T_256 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_257 = eq(_T_256, UInt<1>(0h0))
node _T_258 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_259 = cvt(_T_258)
node _T_260 = and(_T_259, asSInt(UInt<1>(0h0)))
node _T_261 = asSInt(_T_260)
node _T_262 = eq(_T_261, asSInt(UInt<1>(0h0)))
node _T_263 = or(_T_257, _T_262)
node _T_264 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_265 = eq(_T_264, UInt<1>(0h0))
node _T_266 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_267 = cvt(_T_266)
node _T_268 = and(_T_267, asSInt(UInt<1>(0h0)))
node _T_269 = asSInt(_T_268)
node _T_270 = eq(_T_269, asSInt(UInt<1>(0h0)))
node _T_271 = or(_T_265, _T_270)
node _T_272 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_273 = eq(_T_272, UInt<1>(0h0))
node _T_274 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_275 = cvt(_T_274)
node _T_276 = and(_T_275, asSInt(UInt<1>(0h0)))
node _T_277 = asSInt(_T_276)
node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0)))
node _T_279 = or(_T_273, _T_278)
node _T_280 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_281 = eq(_T_280, UInt<1>(0h0))
node _T_282 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_283 = cvt(_T_282)
node _T_284 = and(_T_283, asSInt(UInt<1>(0h0)))
node _T_285 = asSInt(_T_284)
node _T_286 = eq(_T_285, asSInt(UInt<1>(0h0)))
node _T_287 = or(_T_281, _T_286)
node _T_288 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_289 = eq(_T_288, UInt<1>(0h0))
node _T_290 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_291 = cvt(_T_290)
node _T_292 = and(_T_291, asSInt(UInt<1>(0h0)))
node _T_293 = asSInt(_T_292)
node _T_294 = eq(_T_293, asSInt(UInt<1>(0h0)))
node _T_295 = or(_T_289, _T_294)
node _T_296 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_297 = eq(_T_296, UInt<1>(0h0))
node _T_298 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_299 = cvt(_T_298)
node _T_300 = and(_T_299, asSInt(UInt<1>(0h0)))
node _T_301 = asSInt(_T_300)
node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0)))
node _T_303 = or(_T_297, _T_302)
node _T_304 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_305 = eq(_T_304, UInt<1>(0h0))
node _T_306 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_307 = cvt(_T_306)
node _T_308 = and(_T_307, asSInt(UInt<1>(0h0)))
node _T_309 = asSInt(_T_308)
node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0)))
node _T_311 = or(_T_305, _T_310)
node _T_312 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_313 = eq(_T_312, UInt<1>(0h0))
node _T_314 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_315 = cvt(_T_314)
node _T_316 = and(_T_315, asSInt(UInt<1>(0h0)))
node _T_317 = asSInt(_T_316)
node _T_318 = eq(_T_317, asSInt(UInt<1>(0h0)))
node _T_319 = or(_T_313, _T_318)
node _T_320 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_321 = eq(_T_320, UInt<1>(0h0))
node _T_322 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_323 = cvt(_T_322)
node _T_324 = and(_T_323, asSInt(UInt<1>(0h0)))
node _T_325 = asSInt(_T_324)
node _T_326 = eq(_T_325, asSInt(UInt<1>(0h0)))
node _T_327 = or(_T_321, _T_326)
node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_329 = eq(_T_328, UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<1>(0h0)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = or(_T_329, _T_334)
node _T_336 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_337 = eq(_T_336, UInt<1>(0h0))
node _T_338 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_339 = cvt(_T_338)
node _T_340 = and(_T_339, asSInt(UInt<1>(0h0)))
node _T_341 = asSInt(_T_340)
node _T_342 = eq(_T_341, asSInt(UInt<1>(0h0)))
node _T_343 = or(_T_337, _T_342)
node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_345 = eq(_T_344, UInt<1>(0h0))
node _T_346 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_347 = cvt(_T_346)
node _T_348 = and(_T_347, asSInt(UInt<1>(0h0)))
node _T_349 = asSInt(_T_348)
node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0)))
node _T_351 = or(_T_345, _T_350)
node _T_352 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_353 = eq(_T_352, UInt<1>(0h0))
node _T_354 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_355 = cvt(_T_354)
node _T_356 = and(_T_355, asSInt(UInt<1>(0h0)))
node _T_357 = asSInt(_T_356)
node _T_358 = eq(_T_357, asSInt(UInt<1>(0h0)))
node _T_359 = or(_T_353, _T_358)
node _T_360 = and(_T_11, _T_24)
node _T_361 = and(_T_360, _T_37)
node _T_362 = and(_T_361, _T_50)
node _T_363 = and(_T_362, _T_63)
node _T_364 = and(_T_363, _T_71)
node _T_365 = and(_T_364, _T_79)
node _T_366 = and(_T_365, _T_87)
node _T_367 = and(_T_366, _T_95)
node _T_368 = and(_T_367, _T_103)
node _T_369 = and(_T_368, _T_111)
node _T_370 = and(_T_369, _T_119)
node _T_371 = and(_T_370, _T_127)
node _T_372 = and(_T_371, _T_135)
node _T_373 = and(_T_372, _T_143)
node _T_374 = and(_T_373, _T_151)
node _T_375 = and(_T_374, _T_159)
node _T_376 = and(_T_375, _T_167)
node _T_377 = and(_T_376, _T_175)
node _T_378 = and(_T_377, _T_183)
node _T_379 = and(_T_378, _T_191)
node _T_380 = and(_T_379, _T_199)
node _T_381 = and(_T_380, _T_207)
node _T_382 = and(_T_381, _T_215)
node _T_383 = and(_T_382, _T_223)
node _T_384 = and(_T_383, _T_231)
node _T_385 = and(_T_384, _T_239)
node _T_386 = and(_T_385, _T_247)
node _T_387 = and(_T_386, _T_255)
node _T_388 = and(_T_387, _T_263)
node _T_389 = and(_T_388, _T_271)
node _T_390 = and(_T_389, _T_279)
node _T_391 = and(_T_390, _T_287)
node _T_392 = and(_T_391, _T_295)
node _T_393 = and(_T_392, _T_303)
node _T_394 = and(_T_393, _T_311)
node _T_395 = and(_T_394, _T_319)
node _T_396 = and(_T_395, _T_327)
node _T_397 = and(_T_396, _T_335)
node _T_398 = and(_T_397, _T_343)
node _T_399 = and(_T_398, _T_351)
node _T_400 = and(_T_399, _T_359)
node _T_401 = asUInt(reset)
node _T_402 = eq(_T_401, UInt<1>(0h0))
when _T_402 :
node _T_403 = eq(_T_400, UInt<1>(0h0))
when _T_403 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_400, UInt<1>(0h1), "") : assert_1
node _T_404 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_404 :
node _T_405 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_406 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_407 = and(_T_405, _T_406)
node _T_408 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_409 = shr(io.in.a.bits.source, 2)
node _T_410 = eq(_T_409, UInt<1>(0h0))
node _T_411 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_412 = and(_T_410, _T_411)
node _T_413 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_414 = and(_T_412, _T_413)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_415 = shr(io.in.a.bits.source, 2)
node _T_416 = eq(_T_415, UInt<1>(0h1))
node _T_417 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_418 = and(_T_416, _T_417)
node _T_419 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_420 = and(_T_418, _T_419)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_421 = shr(io.in.a.bits.source, 2)
node _T_422 = eq(_T_421, UInt<2>(0h2))
node _T_423 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_424 = and(_T_422, _T_423)
node _T_425 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_426 = and(_T_424, _T_425)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_427 = shr(io.in.a.bits.source, 2)
node _T_428 = eq(_T_427, UInt<2>(0h3))
node _T_429 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_430 = and(_T_428, _T_429)
node _T_431 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_432 = and(_T_430, _T_431)
node _T_433 = eq(io.in.a.bits.source, UInt<7>(0h4c))
node _T_434 = eq(io.in.a.bits.source, UInt<7>(0h4d))
node _T_435 = eq(io.in.a.bits.source, UInt<7>(0h4e))
node _T_436 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_437 = eq(io.in.a.bits.source, UInt<7>(0h49))
node _T_438 = eq(io.in.a.bits.source, UInt<7>(0h4a))
node _T_439 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_440 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_441 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_442 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_443 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_444 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_445 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_446 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_447 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_448 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_449 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_450 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_451 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_452 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_453 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_454 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_455 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_456 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_457 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_458 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_459 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_460 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_461 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_462 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_463 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_464 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_465 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_466 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_467 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_468 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_469 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_470 = or(_T_408, _T_414)
node _T_471 = or(_T_470, _T_420)
node _T_472 = or(_T_471, _T_426)
node _T_473 = or(_T_472, _T_432)
node _T_474 = or(_T_473, _T_433)
node _T_475 = or(_T_474, _T_434)
node _T_476 = or(_T_475, _T_435)
node _T_477 = or(_T_476, _T_436)
node _T_478 = or(_T_477, _T_437)
node _T_479 = or(_T_478, _T_438)
node _T_480 = or(_T_479, _T_439)
node _T_481 = or(_T_480, _T_440)
node _T_482 = or(_T_481, _T_441)
node _T_483 = or(_T_482, _T_442)
node _T_484 = or(_T_483, _T_443)
node _T_485 = or(_T_484, _T_444)
node _T_486 = or(_T_485, _T_445)
node _T_487 = or(_T_486, _T_446)
node _T_488 = or(_T_487, _T_447)
node _T_489 = or(_T_488, _T_448)
node _T_490 = or(_T_489, _T_449)
node _T_491 = or(_T_490, _T_450)
node _T_492 = or(_T_491, _T_451)
node _T_493 = or(_T_492, _T_452)
node _T_494 = or(_T_493, _T_453)
node _T_495 = or(_T_494, _T_454)
node _T_496 = or(_T_495, _T_455)
node _T_497 = or(_T_496, _T_456)
node _T_498 = or(_T_497, _T_457)
node _T_499 = or(_T_498, _T_458)
node _T_500 = or(_T_499, _T_459)
node _T_501 = or(_T_500, _T_460)
node _T_502 = or(_T_501, _T_461)
node _T_503 = or(_T_502, _T_462)
node _T_504 = or(_T_503, _T_463)
node _T_505 = or(_T_504, _T_464)
node _T_506 = or(_T_505, _T_465)
node _T_507 = or(_T_506, _T_466)
node _T_508 = or(_T_507, _T_467)
node _T_509 = or(_T_508, _T_468)
node _T_510 = or(_T_509, _T_469)
node _T_511 = and(_T_407, _T_510)
node _T_512 = or(UInt<1>(0h0), _T_511)
node _T_513 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_514 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_515 = cvt(_T_514)
node _T_516 = and(_T_515, asSInt(UInt<14>(0h2000)))
node _T_517 = asSInt(_T_516)
node _T_518 = eq(_T_517, asSInt(UInt<1>(0h0)))
node _T_519 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_520 = cvt(_T_519)
node _T_521 = and(_T_520, asSInt(UInt<13>(0h1000)))
node _T_522 = asSInt(_T_521)
node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0)))
node _T_524 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_525 = cvt(_T_524)
node _T_526 = and(_T_525, asSInt(UInt<17>(0h10000)))
node _T_527 = asSInt(_T_526)
node _T_528 = eq(_T_527, asSInt(UInt<1>(0h0)))
node _T_529 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_530 = cvt(_T_529)
node _T_531 = and(_T_530, asSInt(UInt<18>(0h2f000)))
node _T_532 = asSInt(_T_531)
node _T_533 = eq(_T_532, asSInt(UInt<1>(0h0)))
node _T_534 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_535 = cvt(_T_534)
node _T_536 = and(_T_535, asSInt(UInt<17>(0h10000)))
node _T_537 = asSInt(_T_536)
node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0)))
node _T_539 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_540 = cvt(_T_539)
node _T_541 = and(_T_540, asSInt(UInt<13>(0h1000)))
node _T_542 = asSInt(_T_541)
node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0)))
node _T_544 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_545 = cvt(_T_544)
node _T_546 = and(_T_545, asSInt(UInt<27>(0h4000000)))
node _T_547 = asSInt(_T_546)
node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0)))
node _T_549 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_550 = cvt(_T_549)
node _T_551 = and(_T_550, asSInt(UInt<13>(0h1000)))
node _T_552 = asSInt(_T_551)
node _T_553 = eq(_T_552, asSInt(UInt<1>(0h0)))
node _T_554 = or(_T_518, _T_523)
node _T_555 = or(_T_554, _T_528)
node _T_556 = or(_T_555, _T_533)
node _T_557 = or(_T_556, _T_538)
node _T_558 = or(_T_557, _T_543)
node _T_559 = or(_T_558, _T_548)
node _T_560 = or(_T_559, _T_553)
node _T_561 = and(_T_513, _T_560)
node _T_562 = or(UInt<1>(0h0), _T_561)
node _T_563 = and(_T_512, _T_562)
node _T_564 = asUInt(reset)
node _T_565 = eq(_T_564, UInt<1>(0h0))
when _T_565 :
node _T_566 = eq(_T_563, UInt<1>(0h0))
when _T_566 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_563, UInt<1>(0h1), "") : assert_2
node _T_567 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_568 = shr(io.in.a.bits.source, 2)
node _T_569 = eq(_T_568, UInt<1>(0h0))
node _T_570 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_571 = and(_T_569, _T_570)
node _T_572 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_573 = and(_T_571, _T_572)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_574 = shr(io.in.a.bits.source, 2)
node _T_575 = eq(_T_574, UInt<1>(0h1))
node _T_576 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_577 = and(_T_575, _T_576)
node _T_578 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_579 = and(_T_577, _T_578)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_580 = shr(io.in.a.bits.source, 2)
node _T_581 = eq(_T_580, UInt<2>(0h2))
node _T_582 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_583 = and(_T_581, _T_582)
node _T_584 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_585 = and(_T_583, _T_584)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_586 = shr(io.in.a.bits.source, 2)
node _T_587 = eq(_T_586, UInt<2>(0h3))
node _T_588 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_589 = and(_T_587, _T_588)
node _T_590 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_591 = and(_T_589, _T_590)
node _T_592 = eq(io.in.a.bits.source, UInt<7>(0h4c))
node _T_593 = eq(io.in.a.bits.source, UInt<7>(0h4d))
node _T_594 = eq(io.in.a.bits.source, UInt<7>(0h4e))
node _T_595 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_596 = eq(io.in.a.bits.source, UInt<7>(0h49))
node _T_597 = eq(io.in.a.bits.source, UInt<7>(0h4a))
node _T_598 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_599 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_600 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_601 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_602 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_603 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_604 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_605 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_606 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_607 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_608 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_609 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_610 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_611 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_612 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_613 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_614 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_615 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_616 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_617 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_618 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_619 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_620 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_621 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_622 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_623 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_624 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_625 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_626 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_627 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_628 = eq(io.in.a.bits.source, UInt<8>(0h80))
wire _WIRE : UInt<1>[42]
connect _WIRE[0], _T_567
connect _WIRE[1], _T_573
connect _WIRE[2], _T_579
connect _WIRE[3], _T_585
connect _WIRE[4], _T_591
connect _WIRE[5], _T_592
connect _WIRE[6], _T_593
connect _WIRE[7], _T_594
connect _WIRE[8], _T_595
connect _WIRE[9], _T_596
connect _WIRE[10], _T_597
connect _WIRE[11], _T_598
connect _WIRE[12], _T_599
connect _WIRE[13], _T_600
connect _WIRE[14], _T_601
connect _WIRE[15], _T_602
connect _WIRE[16], _T_603
connect _WIRE[17], _T_604
connect _WIRE[18], _T_605
connect _WIRE[19], _T_606
connect _WIRE[20], _T_607
connect _WIRE[21], _T_608
connect _WIRE[22], _T_609
connect _WIRE[23], _T_610
connect _WIRE[24], _T_611
connect _WIRE[25], _T_612
connect _WIRE[26], _T_613
connect _WIRE[27], _T_614
connect _WIRE[28], _T_615
connect _WIRE[29], _T_616
connect _WIRE[30], _T_617
connect _WIRE[31], _T_618
connect _WIRE[32], _T_619
connect _WIRE[33], _T_620
connect _WIRE[34], _T_621
connect _WIRE[35], _T_622
connect _WIRE[36], _T_623
connect _WIRE[37], _T_624
connect _WIRE[38], _T_625
connect _WIRE[39], _T_626
connect _WIRE[40], _T_627
connect _WIRE[41], _T_628
node _T_629 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_630 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_631 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_632 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_633 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_634 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_635 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_636 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_637 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_638 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_639 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_640 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_641 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_642 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_643 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_644 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_645 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_646 = mux(_WIRE[5], _T_629, UInt<1>(0h0))
node _T_647 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_648 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_649 = mux(_WIRE[8], _T_630, UInt<1>(0h0))
node _T_650 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_651 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_652 = mux(_WIRE[11], _T_631, UInt<1>(0h0))
node _T_653 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_654 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0))
node _T_655 = mux(_WIRE[14], _T_632, UInt<1>(0h0))
node _T_656 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0))
node _T_657 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_658 = mux(_WIRE[17], _T_633, UInt<1>(0h0))
node _T_659 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0))
node _T_660 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0))
node _T_661 = mux(_WIRE[20], _T_634, UInt<1>(0h0))
node _T_662 = mux(_WIRE[21], UInt<1>(0h0), UInt<1>(0h0))
node _T_663 = mux(_WIRE[22], UInt<1>(0h0), UInt<1>(0h0))
node _T_664 = mux(_WIRE[23], _T_635, UInt<1>(0h0))
node _T_665 = mux(_WIRE[24], UInt<1>(0h0), UInt<1>(0h0))
node _T_666 = mux(_WIRE[25], UInt<1>(0h0), UInt<1>(0h0))
node _T_667 = mux(_WIRE[26], _T_636, UInt<1>(0h0))
node _T_668 = mux(_WIRE[27], UInt<1>(0h0), UInt<1>(0h0))
node _T_669 = mux(_WIRE[28], UInt<1>(0h0), UInt<1>(0h0))
node _T_670 = mux(_WIRE[29], _T_637, UInt<1>(0h0))
node _T_671 = mux(_WIRE[30], UInt<1>(0h0), UInt<1>(0h0))
node _T_672 = mux(_WIRE[31], UInt<1>(0h0), UInt<1>(0h0))
node _T_673 = mux(_WIRE[32], _T_638, UInt<1>(0h0))
node _T_674 = mux(_WIRE[33], UInt<1>(0h0), UInt<1>(0h0))
node _T_675 = mux(_WIRE[34], UInt<1>(0h0), UInt<1>(0h0))
node _T_676 = mux(_WIRE[35], _T_639, UInt<1>(0h0))
node _T_677 = mux(_WIRE[36], UInt<1>(0h0), UInt<1>(0h0))
node _T_678 = mux(_WIRE[37], UInt<1>(0h0), UInt<1>(0h0))
node _T_679 = mux(_WIRE[38], _T_640, UInt<1>(0h0))
node _T_680 = mux(_WIRE[39], UInt<1>(0h0), UInt<1>(0h0))
node _T_681 = mux(_WIRE[40], UInt<1>(0h0), UInt<1>(0h0))
node _T_682 = mux(_WIRE[41], UInt<1>(0h0), UInt<1>(0h0))
node _T_683 = or(_T_641, _T_642)
node _T_684 = or(_T_683, _T_643)
node _T_685 = or(_T_684, _T_644)
node _T_686 = or(_T_685, _T_645)
node _T_687 = or(_T_686, _T_646)
node _T_688 = or(_T_687, _T_647)
node _T_689 = or(_T_688, _T_648)
node _T_690 = or(_T_689, _T_649)
node _T_691 = or(_T_690, _T_650)
node _T_692 = or(_T_691, _T_651)
node _T_693 = or(_T_692, _T_652)
node _T_694 = or(_T_693, _T_653)
node _T_695 = or(_T_694, _T_654)
node _T_696 = or(_T_695, _T_655)
node _T_697 = or(_T_696, _T_656)
node _T_698 = or(_T_697, _T_657)
node _T_699 = or(_T_698, _T_658)
node _T_700 = or(_T_699, _T_659)
node _T_701 = or(_T_700, _T_660)
node _T_702 = or(_T_701, _T_661)
node _T_703 = or(_T_702, _T_662)
node _T_704 = or(_T_703, _T_663)
node _T_705 = or(_T_704, _T_664)
node _T_706 = or(_T_705, _T_665)
node _T_707 = or(_T_706, _T_666)
node _T_708 = or(_T_707, _T_667)
node _T_709 = or(_T_708, _T_668)
node _T_710 = or(_T_709, _T_669)
node _T_711 = or(_T_710, _T_670)
node _T_712 = or(_T_711, _T_671)
node _T_713 = or(_T_712, _T_672)
node _T_714 = or(_T_713, _T_673)
node _T_715 = or(_T_714, _T_674)
node _T_716 = or(_T_715, _T_675)
node _T_717 = or(_T_716, _T_676)
node _T_718 = or(_T_717, _T_677)
node _T_719 = or(_T_718, _T_678)
node _T_720 = or(_T_719, _T_679)
node _T_721 = or(_T_720, _T_680)
node _T_722 = or(_T_721, _T_681)
node _T_723 = or(_T_722, _T_682)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_723
node _T_724 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_725 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_726 = and(_T_724, _T_725)
node _T_727 = or(UInt<1>(0h0), _T_726)
node _T_728 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_729 = cvt(_T_728)
node _T_730 = and(_T_729, asSInt(UInt<14>(0h2000)))
node _T_731 = asSInt(_T_730)
node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0)))
node _T_733 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_734 = cvt(_T_733)
node _T_735 = and(_T_734, asSInt(UInt<13>(0h1000)))
node _T_736 = asSInt(_T_735)
node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0)))
node _T_738 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_739 = cvt(_T_738)
node _T_740 = and(_T_739, asSInt(UInt<17>(0h10000)))
node _T_741 = asSInt(_T_740)
node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0)))
node _T_743 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_744 = cvt(_T_743)
node _T_745 = and(_T_744, asSInt(UInt<18>(0h2f000)))
node _T_746 = asSInt(_T_745)
node _T_747 = eq(_T_746, asSInt(UInt<1>(0h0)))
node _T_748 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_749 = cvt(_T_748)
node _T_750 = and(_T_749, asSInt(UInt<17>(0h10000)))
node _T_751 = asSInt(_T_750)
node _T_752 = eq(_T_751, asSInt(UInt<1>(0h0)))
node _T_753 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_754 = cvt(_T_753)
node _T_755 = and(_T_754, asSInt(UInt<13>(0h1000)))
node _T_756 = asSInt(_T_755)
node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0)))
node _T_758 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_759 = cvt(_T_758)
node _T_760 = and(_T_759, asSInt(UInt<27>(0h4000000)))
node _T_761 = asSInt(_T_760)
node _T_762 = eq(_T_761, asSInt(UInt<1>(0h0)))
node _T_763 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_764 = cvt(_T_763)
node _T_765 = and(_T_764, asSInt(UInt<13>(0h1000)))
node _T_766 = asSInt(_T_765)
node _T_767 = eq(_T_766, asSInt(UInt<1>(0h0)))
node _T_768 = or(_T_732, _T_737)
node _T_769 = or(_T_768, _T_742)
node _T_770 = or(_T_769, _T_747)
node _T_771 = or(_T_770, _T_752)
node _T_772 = or(_T_771, _T_757)
node _T_773 = or(_T_772, _T_762)
node _T_774 = or(_T_773, _T_767)
node _T_775 = and(_T_727, _T_774)
node _T_776 = or(UInt<1>(0h0), _T_775)
node _T_777 = and(_WIRE_1, _T_776)
node _T_778 = asUInt(reset)
node _T_779 = eq(_T_778, UInt<1>(0h0))
when _T_779 :
node _T_780 = eq(_T_777, UInt<1>(0h0))
when _T_780 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_777, UInt<1>(0h1), "") : assert_3
node _T_781 = asUInt(reset)
node _T_782 = eq(_T_781, UInt<1>(0h0))
when _T_782 :
node _T_783 = eq(source_ok, UInt<1>(0h0))
when _T_783 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_784 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_785 = asUInt(reset)
node _T_786 = eq(_T_785, UInt<1>(0h0))
when _T_786 :
node _T_787 = eq(_T_784, UInt<1>(0h0))
when _T_787 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_784, UInt<1>(0h1), "") : assert_5
node _T_788 = asUInt(reset)
node _T_789 = eq(_T_788, UInt<1>(0h0))
when _T_789 :
node _T_790 = eq(is_aligned, UInt<1>(0h0))
when _T_790 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_791 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_792 = asUInt(reset)
node _T_793 = eq(_T_792, UInt<1>(0h0))
when _T_793 :
node _T_794 = eq(_T_791, UInt<1>(0h0))
when _T_794 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_791, UInt<1>(0h1), "") : assert_7
node _T_795 = not(io.in.a.bits.mask)
node _T_796 = eq(_T_795, UInt<1>(0h0))
node _T_797 = asUInt(reset)
node _T_798 = eq(_T_797, UInt<1>(0h0))
when _T_798 :
node _T_799 = eq(_T_796, UInt<1>(0h0))
when _T_799 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_796, UInt<1>(0h1), "") : assert_8
node _T_800 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_801 = asUInt(reset)
node _T_802 = eq(_T_801, UInt<1>(0h0))
when _T_802 :
node _T_803 = eq(_T_800, UInt<1>(0h0))
when _T_803 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_800, UInt<1>(0h1), "") : assert_9
node _T_804 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_804 :
node _T_805 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_806 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_807 = and(_T_805, _T_806)
node _T_808 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_809 = shr(io.in.a.bits.source, 2)
node _T_810 = eq(_T_809, UInt<1>(0h0))
node _T_811 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_812 = and(_T_810, _T_811)
node _T_813 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_814 = and(_T_812, _T_813)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_815 = shr(io.in.a.bits.source, 2)
node _T_816 = eq(_T_815, UInt<1>(0h1))
node _T_817 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_818 = and(_T_816, _T_817)
node _T_819 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_820 = and(_T_818, _T_819)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_821 = shr(io.in.a.bits.source, 2)
node _T_822 = eq(_T_821, UInt<2>(0h2))
node _T_823 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_824 = and(_T_822, _T_823)
node _T_825 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_826 = and(_T_824, _T_825)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_827 = shr(io.in.a.bits.source, 2)
node _T_828 = eq(_T_827, UInt<2>(0h3))
node _T_829 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_830 = and(_T_828, _T_829)
node _T_831 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_832 = and(_T_830, _T_831)
node _T_833 = eq(io.in.a.bits.source, UInt<7>(0h4c))
node _T_834 = eq(io.in.a.bits.source, UInt<7>(0h4d))
node _T_835 = eq(io.in.a.bits.source, UInt<7>(0h4e))
node _T_836 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_837 = eq(io.in.a.bits.source, UInt<7>(0h49))
node _T_838 = eq(io.in.a.bits.source, UInt<7>(0h4a))
node _T_839 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_840 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_841 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_842 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_843 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_844 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_845 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_846 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_847 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_848 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_849 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_850 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_851 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_852 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_853 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_854 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_855 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_856 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_857 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_858 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_859 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_860 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_861 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_862 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_863 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_864 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_865 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_866 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_867 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_868 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_869 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_870 = or(_T_808, _T_814)
node _T_871 = or(_T_870, _T_820)
node _T_872 = or(_T_871, _T_826)
node _T_873 = or(_T_872, _T_832)
node _T_874 = or(_T_873, _T_833)
node _T_875 = or(_T_874, _T_834)
node _T_876 = or(_T_875, _T_835)
node _T_877 = or(_T_876, _T_836)
node _T_878 = or(_T_877, _T_837)
node _T_879 = or(_T_878, _T_838)
node _T_880 = or(_T_879, _T_839)
node _T_881 = or(_T_880, _T_840)
node _T_882 = or(_T_881, _T_841)
node _T_883 = or(_T_882, _T_842)
node _T_884 = or(_T_883, _T_843)
node _T_885 = or(_T_884, _T_844)
node _T_886 = or(_T_885, _T_845)
node _T_887 = or(_T_886, _T_846)
node _T_888 = or(_T_887, _T_847)
node _T_889 = or(_T_888, _T_848)
node _T_890 = or(_T_889, _T_849)
node _T_891 = or(_T_890, _T_850)
node _T_892 = or(_T_891, _T_851)
node _T_893 = or(_T_892, _T_852)
node _T_894 = or(_T_893, _T_853)
node _T_895 = or(_T_894, _T_854)
node _T_896 = or(_T_895, _T_855)
node _T_897 = or(_T_896, _T_856)
node _T_898 = or(_T_897, _T_857)
node _T_899 = or(_T_898, _T_858)
node _T_900 = or(_T_899, _T_859)
node _T_901 = or(_T_900, _T_860)
node _T_902 = or(_T_901, _T_861)
node _T_903 = or(_T_902, _T_862)
node _T_904 = or(_T_903, _T_863)
node _T_905 = or(_T_904, _T_864)
node _T_906 = or(_T_905, _T_865)
node _T_907 = or(_T_906, _T_866)
node _T_908 = or(_T_907, _T_867)
node _T_909 = or(_T_908, _T_868)
node _T_910 = or(_T_909, _T_869)
node _T_911 = and(_T_807, _T_910)
node _T_912 = or(UInt<1>(0h0), _T_911)
node _T_913 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_914 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_915 = cvt(_T_914)
node _T_916 = and(_T_915, asSInt(UInt<14>(0h2000)))
node _T_917 = asSInt(_T_916)
node _T_918 = eq(_T_917, asSInt(UInt<1>(0h0)))
node _T_919 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_920 = cvt(_T_919)
node _T_921 = and(_T_920, asSInt(UInt<13>(0h1000)))
node _T_922 = asSInt(_T_921)
node _T_923 = eq(_T_922, asSInt(UInt<1>(0h0)))
node _T_924 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_925 = cvt(_T_924)
node _T_926 = and(_T_925, asSInt(UInt<17>(0h10000)))
node _T_927 = asSInt(_T_926)
node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0)))
node _T_929 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_930 = cvt(_T_929)
node _T_931 = and(_T_930, asSInt(UInt<18>(0h2f000)))
node _T_932 = asSInt(_T_931)
node _T_933 = eq(_T_932, asSInt(UInt<1>(0h0)))
node _T_934 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_935 = cvt(_T_934)
node _T_936 = and(_T_935, asSInt(UInt<17>(0h10000)))
node _T_937 = asSInt(_T_936)
node _T_938 = eq(_T_937, asSInt(UInt<1>(0h0)))
node _T_939 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_940 = cvt(_T_939)
node _T_941 = and(_T_940, asSInt(UInt<13>(0h1000)))
node _T_942 = asSInt(_T_941)
node _T_943 = eq(_T_942, asSInt(UInt<1>(0h0)))
node _T_944 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_945 = cvt(_T_944)
node _T_946 = and(_T_945, asSInt(UInt<27>(0h4000000)))
node _T_947 = asSInt(_T_946)
node _T_948 = eq(_T_947, asSInt(UInt<1>(0h0)))
node _T_949 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_950 = cvt(_T_949)
node _T_951 = and(_T_950, asSInt(UInt<13>(0h1000)))
node _T_952 = asSInt(_T_951)
node _T_953 = eq(_T_952, asSInt(UInt<1>(0h0)))
node _T_954 = or(_T_918, _T_923)
node _T_955 = or(_T_954, _T_928)
node _T_956 = or(_T_955, _T_933)
node _T_957 = or(_T_956, _T_938)
node _T_958 = or(_T_957, _T_943)
node _T_959 = or(_T_958, _T_948)
node _T_960 = or(_T_959, _T_953)
node _T_961 = and(_T_913, _T_960)
node _T_962 = or(UInt<1>(0h0), _T_961)
node _T_963 = and(_T_912, _T_962)
node _T_964 = asUInt(reset)
node _T_965 = eq(_T_964, UInt<1>(0h0))
when _T_965 :
node _T_966 = eq(_T_963, UInt<1>(0h0))
when _T_966 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_963, UInt<1>(0h1), "") : assert_10
node _T_967 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_968 = shr(io.in.a.bits.source, 2)
node _T_969 = eq(_T_968, UInt<1>(0h0))
node _T_970 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_971 = and(_T_969, _T_970)
node _T_972 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_973 = and(_T_971, _T_972)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_974 = shr(io.in.a.bits.source, 2)
node _T_975 = eq(_T_974, UInt<1>(0h1))
node _T_976 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_977 = and(_T_975, _T_976)
node _T_978 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_979 = and(_T_977, _T_978)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_980 = shr(io.in.a.bits.source, 2)
node _T_981 = eq(_T_980, UInt<2>(0h2))
node _T_982 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_983 = and(_T_981, _T_982)
node _T_984 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_985 = and(_T_983, _T_984)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_986 = shr(io.in.a.bits.source, 2)
node _T_987 = eq(_T_986, UInt<2>(0h3))
node _T_988 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_989 = and(_T_987, _T_988)
node _T_990 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_991 = and(_T_989, _T_990)
node _T_992 = eq(io.in.a.bits.source, UInt<7>(0h4c))
node _T_993 = eq(io.in.a.bits.source, UInt<7>(0h4d))
node _T_994 = eq(io.in.a.bits.source, UInt<7>(0h4e))
node _T_995 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_996 = eq(io.in.a.bits.source, UInt<7>(0h49))
node _T_997 = eq(io.in.a.bits.source, UInt<7>(0h4a))
node _T_998 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_999 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_1000 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_1001 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1002 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_1003 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_1004 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_1005 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_1006 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_1007 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_1008 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_1009 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_1010 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_1011 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_1012 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_1013 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_1014 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_1015 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_1016 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1017 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_1018 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1019 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1020 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1021 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1022 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1023 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1024 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1025 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1026 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1027 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1028 = eq(io.in.a.bits.source, UInt<8>(0h80))
wire _WIRE_2 : UInt<1>[42]
connect _WIRE_2[0], _T_967
connect _WIRE_2[1], _T_973
connect _WIRE_2[2], _T_979
connect _WIRE_2[3], _T_985
connect _WIRE_2[4], _T_991
connect _WIRE_2[5], _T_992
connect _WIRE_2[6], _T_993
connect _WIRE_2[7], _T_994
connect _WIRE_2[8], _T_995
connect _WIRE_2[9], _T_996
connect _WIRE_2[10], _T_997
connect _WIRE_2[11], _T_998
connect _WIRE_2[12], _T_999
connect _WIRE_2[13], _T_1000
connect _WIRE_2[14], _T_1001
connect _WIRE_2[15], _T_1002
connect _WIRE_2[16], _T_1003
connect _WIRE_2[17], _T_1004
connect _WIRE_2[18], _T_1005
connect _WIRE_2[19], _T_1006
connect _WIRE_2[20], _T_1007
connect _WIRE_2[21], _T_1008
connect _WIRE_2[22], _T_1009
connect _WIRE_2[23], _T_1010
connect _WIRE_2[24], _T_1011
connect _WIRE_2[25], _T_1012
connect _WIRE_2[26], _T_1013
connect _WIRE_2[27], _T_1014
connect _WIRE_2[28], _T_1015
connect _WIRE_2[29], _T_1016
connect _WIRE_2[30], _T_1017
connect _WIRE_2[31], _T_1018
connect _WIRE_2[32], _T_1019
connect _WIRE_2[33], _T_1020
connect _WIRE_2[34], _T_1021
connect _WIRE_2[35], _T_1022
connect _WIRE_2[36], _T_1023
connect _WIRE_2[37], _T_1024
connect _WIRE_2[38], _T_1025
connect _WIRE_2[39], _T_1026
connect _WIRE_2[40], _T_1027
connect _WIRE_2[41], _T_1028
node _T_1029 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_1030 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_1031 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_1032 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_1033 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_1034 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_1035 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_1036 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_1037 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_1038 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_1039 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_1040 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_1041 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_1042 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_1043 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_1044 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_1045 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_1046 = mux(_WIRE_2[5], _T_1029, UInt<1>(0h0))
node _T_1047 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_1048 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_1049 = mux(_WIRE_2[8], _T_1030, UInt<1>(0h0))
node _T_1050 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_1051 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_1052 = mux(_WIRE_2[11], _T_1031, UInt<1>(0h0))
node _T_1053 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_1054 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0))
node _T_1055 = mux(_WIRE_2[14], _T_1032, UInt<1>(0h0))
node _T_1056 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0))
node _T_1057 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_1058 = mux(_WIRE_2[17], _T_1033, UInt<1>(0h0))
node _T_1059 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0))
node _T_1060 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0))
node _T_1061 = mux(_WIRE_2[20], _T_1034, UInt<1>(0h0))
node _T_1062 = mux(_WIRE_2[21], UInt<1>(0h0), UInt<1>(0h0))
node _T_1063 = mux(_WIRE_2[22], UInt<1>(0h0), UInt<1>(0h0))
node _T_1064 = mux(_WIRE_2[23], _T_1035, UInt<1>(0h0))
node _T_1065 = mux(_WIRE_2[24], UInt<1>(0h0), UInt<1>(0h0))
node _T_1066 = mux(_WIRE_2[25], UInt<1>(0h0), UInt<1>(0h0))
node _T_1067 = mux(_WIRE_2[26], _T_1036, UInt<1>(0h0))
node _T_1068 = mux(_WIRE_2[27], UInt<1>(0h0), UInt<1>(0h0))
node _T_1069 = mux(_WIRE_2[28], UInt<1>(0h0), UInt<1>(0h0))
node _T_1070 = mux(_WIRE_2[29], _T_1037, UInt<1>(0h0))
node _T_1071 = mux(_WIRE_2[30], UInt<1>(0h0), UInt<1>(0h0))
node _T_1072 = mux(_WIRE_2[31], UInt<1>(0h0), UInt<1>(0h0))
node _T_1073 = mux(_WIRE_2[32], _T_1038, UInt<1>(0h0))
node _T_1074 = mux(_WIRE_2[33], UInt<1>(0h0), UInt<1>(0h0))
node _T_1075 = mux(_WIRE_2[34], UInt<1>(0h0), UInt<1>(0h0))
node _T_1076 = mux(_WIRE_2[35], _T_1039, UInt<1>(0h0))
node _T_1077 = mux(_WIRE_2[36], UInt<1>(0h0), UInt<1>(0h0))
node _T_1078 = mux(_WIRE_2[37], UInt<1>(0h0), UInt<1>(0h0))
node _T_1079 = mux(_WIRE_2[38], _T_1040, UInt<1>(0h0))
node _T_1080 = mux(_WIRE_2[39], UInt<1>(0h0), UInt<1>(0h0))
node _T_1081 = mux(_WIRE_2[40], UInt<1>(0h0), UInt<1>(0h0))
node _T_1082 = mux(_WIRE_2[41], UInt<1>(0h0), UInt<1>(0h0))
node _T_1083 = or(_T_1041, _T_1042)
node _T_1084 = or(_T_1083, _T_1043)
node _T_1085 = or(_T_1084, _T_1044)
node _T_1086 = or(_T_1085, _T_1045)
node _T_1087 = or(_T_1086, _T_1046)
node _T_1088 = or(_T_1087, _T_1047)
node _T_1089 = or(_T_1088, _T_1048)
node _T_1090 = or(_T_1089, _T_1049)
node _T_1091 = or(_T_1090, _T_1050)
node _T_1092 = or(_T_1091, _T_1051)
node _T_1093 = or(_T_1092, _T_1052)
node _T_1094 = or(_T_1093, _T_1053)
node _T_1095 = or(_T_1094, _T_1054)
node _T_1096 = or(_T_1095, _T_1055)
node _T_1097 = or(_T_1096, _T_1056)
node _T_1098 = or(_T_1097, _T_1057)
node _T_1099 = or(_T_1098, _T_1058)
node _T_1100 = or(_T_1099, _T_1059)
node _T_1101 = or(_T_1100, _T_1060)
node _T_1102 = or(_T_1101, _T_1061)
node _T_1103 = or(_T_1102, _T_1062)
node _T_1104 = or(_T_1103, _T_1063)
node _T_1105 = or(_T_1104, _T_1064)
node _T_1106 = or(_T_1105, _T_1065)
node _T_1107 = or(_T_1106, _T_1066)
node _T_1108 = or(_T_1107, _T_1067)
node _T_1109 = or(_T_1108, _T_1068)
node _T_1110 = or(_T_1109, _T_1069)
node _T_1111 = or(_T_1110, _T_1070)
node _T_1112 = or(_T_1111, _T_1071)
node _T_1113 = or(_T_1112, _T_1072)
node _T_1114 = or(_T_1113, _T_1073)
node _T_1115 = or(_T_1114, _T_1074)
node _T_1116 = or(_T_1115, _T_1075)
node _T_1117 = or(_T_1116, _T_1076)
node _T_1118 = or(_T_1117, _T_1077)
node _T_1119 = or(_T_1118, _T_1078)
node _T_1120 = or(_T_1119, _T_1079)
node _T_1121 = or(_T_1120, _T_1080)
node _T_1122 = or(_T_1121, _T_1081)
node _T_1123 = or(_T_1122, _T_1082)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_1123
node _T_1124 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1125 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1126 = and(_T_1124, _T_1125)
node _T_1127 = or(UInt<1>(0h0), _T_1126)
node _T_1128 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1129 = cvt(_T_1128)
node _T_1130 = and(_T_1129, asSInt(UInt<14>(0h2000)))
node _T_1131 = asSInt(_T_1130)
node _T_1132 = eq(_T_1131, asSInt(UInt<1>(0h0)))
node _T_1133 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1134 = cvt(_T_1133)
node _T_1135 = and(_T_1134, asSInt(UInt<13>(0h1000)))
node _T_1136 = asSInt(_T_1135)
node _T_1137 = eq(_T_1136, asSInt(UInt<1>(0h0)))
node _T_1138 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1139 = cvt(_T_1138)
node _T_1140 = and(_T_1139, asSInt(UInt<17>(0h10000)))
node _T_1141 = asSInt(_T_1140)
node _T_1142 = eq(_T_1141, asSInt(UInt<1>(0h0)))
node _T_1143 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1144 = cvt(_T_1143)
node _T_1145 = and(_T_1144, asSInt(UInt<18>(0h2f000)))
node _T_1146 = asSInt(_T_1145)
node _T_1147 = eq(_T_1146, asSInt(UInt<1>(0h0)))
node _T_1148 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1149 = cvt(_T_1148)
node _T_1150 = and(_T_1149, asSInt(UInt<17>(0h10000)))
node _T_1151 = asSInt(_T_1150)
node _T_1152 = eq(_T_1151, asSInt(UInt<1>(0h0)))
node _T_1153 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1154 = cvt(_T_1153)
node _T_1155 = and(_T_1154, asSInt(UInt<13>(0h1000)))
node _T_1156 = asSInt(_T_1155)
node _T_1157 = eq(_T_1156, asSInt(UInt<1>(0h0)))
node _T_1158 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1159 = cvt(_T_1158)
node _T_1160 = and(_T_1159, asSInt(UInt<27>(0h4000000)))
node _T_1161 = asSInt(_T_1160)
node _T_1162 = eq(_T_1161, asSInt(UInt<1>(0h0)))
node _T_1163 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1164 = cvt(_T_1163)
node _T_1165 = and(_T_1164, asSInt(UInt<13>(0h1000)))
node _T_1166 = asSInt(_T_1165)
node _T_1167 = eq(_T_1166, asSInt(UInt<1>(0h0)))
node _T_1168 = or(_T_1132, _T_1137)
node _T_1169 = or(_T_1168, _T_1142)
node _T_1170 = or(_T_1169, _T_1147)
node _T_1171 = or(_T_1170, _T_1152)
node _T_1172 = or(_T_1171, _T_1157)
node _T_1173 = or(_T_1172, _T_1162)
node _T_1174 = or(_T_1173, _T_1167)
node _T_1175 = and(_T_1127, _T_1174)
node _T_1176 = or(UInt<1>(0h0), _T_1175)
node _T_1177 = and(_WIRE_3, _T_1176)
node _T_1178 = asUInt(reset)
node _T_1179 = eq(_T_1178, UInt<1>(0h0))
when _T_1179 :
node _T_1180 = eq(_T_1177, UInt<1>(0h0))
when _T_1180 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_1177, UInt<1>(0h1), "") : assert_11
node _T_1181 = asUInt(reset)
node _T_1182 = eq(_T_1181, UInt<1>(0h0))
when _T_1182 :
node _T_1183 = eq(source_ok, UInt<1>(0h0))
when _T_1183 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_1184 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1185 = asUInt(reset)
node _T_1186 = eq(_T_1185, UInt<1>(0h0))
when _T_1186 :
node _T_1187 = eq(_T_1184, UInt<1>(0h0))
when _T_1187 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_1184, UInt<1>(0h1), "") : assert_13
node _T_1188 = asUInt(reset)
node _T_1189 = eq(_T_1188, UInt<1>(0h0))
when _T_1189 :
node _T_1190 = eq(is_aligned, UInt<1>(0h0))
when _T_1190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_1191 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_1192 = asUInt(reset)
node _T_1193 = eq(_T_1192, UInt<1>(0h0))
when _T_1193 :
node _T_1194 = eq(_T_1191, UInt<1>(0h0))
when _T_1194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_1191, UInt<1>(0h1), "") : assert_15
node _T_1195 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_1196 = asUInt(reset)
node _T_1197 = eq(_T_1196, UInt<1>(0h0))
when _T_1197 :
node _T_1198 = eq(_T_1195, UInt<1>(0h0))
when _T_1198 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_1195, UInt<1>(0h1), "") : assert_16
node _T_1199 = not(io.in.a.bits.mask)
node _T_1200 = eq(_T_1199, UInt<1>(0h0))
node _T_1201 = asUInt(reset)
node _T_1202 = eq(_T_1201, UInt<1>(0h0))
when _T_1202 :
node _T_1203 = eq(_T_1200, UInt<1>(0h0))
when _T_1203 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_1200, UInt<1>(0h1), "") : assert_17
node _T_1204 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1205 = asUInt(reset)
node _T_1206 = eq(_T_1205, UInt<1>(0h0))
when _T_1206 :
node _T_1207 = eq(_T_1204, UInt<1>(0h0))
when _T_1207 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_1204, UInt<1>(0h1), "") : assert_18
node _T_1208 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_1208 :
node _T_1209 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1210 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1211 = and(_T_1209, _T_1210)
node _T_1212 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_1213 = shr(io.in.a.bits.source, 2)
node _T_1214 = eq(_T_1213, UInt<1>(0h0))
node _T_1215 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_1216 = and(_T_1214, _T_1215)
node _T_1217 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_1218 = and(_T_1216, _T_1217)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_1219 = shr(io.in.a.bits.source, 2)
node _T_1220 = eq(_T_1219, UInt<1>(0h1))
node _T_1221 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_1222 = and(_T_1220, _T_1221)
node _T_1223 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_1224 = and(_T_1222, _T_1223)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_1225 = shr(io.in.a.bits.source, 2)
node _T_1226 = eq(_T_1225, UInt<2>(0h2))
node _T_1227 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_1228 = and(_T_1226, _T_1227)
node _T_1229 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_1230 = and(_T_1228, _T_1229)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_1231 = shr(io.in.a.bits.source, 2)
node _T_1232 = eq(_T_1231, UInt<2>(0h3))
node _T_1233 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_1234 = and(_T_1232, _T_1233)
node _T_1235 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_1236 = and(_T_1234, _T_1235)
node _T_1237 = eq(io.in.a.bits.source, UInt<7>(0h4c))
node _T_1238 = eq(io.in.a.bits.source, UInt<7>(0h4d))
node _T_1239 = eq(io.in.a.bits.source, UInt<7>(0h4e))
node _T_1240 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_1241 = eq(io.in.a.bits.source, UInt<7>(0h49))
node _T_1242 = eq(io.in.a.bits.source, UInt<7>(0h4a))
node _T_1243 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_1244 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_1245 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_1246 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1247 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_1248 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_1249 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_1250 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_1251 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_1252 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_1253 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_1254 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_1255 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_1256 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_1257 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_1258 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_1259 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_1260 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_1261 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1262 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_1263 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1264 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1265 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1266 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1267 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1268 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1269 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1270 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1271 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1272 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1273 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_1274 = or(_T_1212, _T_1218)
node _T_1275 = or(_T_1274, _T_1224)
node _T_1276 = or(_T_1275, _T_1230)
node _T_1277 = or(_T_1276, _T_1236)
node _T_1278 = or(_T_1277, _T_1237)
node _T_1279 = or(_T_1278, _T_1238)
node _T_1280 = or(_T_1279, _T_1239)
node _T_1281 = or(_T_1280, _T_1240)
node _T_1282 = or(_T_1281, _T_1241)
node _T_1283 = or(_T_1282, _T_1242)
node _T_1284 = or(_T_1283, _T_1243)
node _T_1285 = or(_T_1284, _T_1244)
node _T_1286 = or(_T_1285, _T_1245)
node _T_1287 = or(_T_1286, _T_1246)
node _T_1288 = or(_T_1287, _T_1247)
node _T_1289 = or(_T_1288, _T_1248)
node _T_1290 = or(_T_1289, _T_1249)
node _T_1291 = or(_T_1290, _T_1250)
node _T_1292 = or(_T_1291, _T_1251)
node _T_1293 = or(_T_1292, _T_1252)
node _T_1294 = or(_T_1293, _T_1253)
node _T_1295 = or(_T_1294, _T_1254)
node _T_1296 = or(_T_1295, _T_1255)
node _T_1297 = or(_T_1296, _T_1256)
node _T_1298 = or(_T_1297, _T_1257)
node _T_1299 = or(_T_1298, _T_1258)
node _T_1300 = or(_T_1299, _T_1259)
node _T_1301 = or(_T_1300, _T_1260)
node _T_1302 = or(_T_1301, _T_1261)
node _T_1303 = or(_T_1302, _T_1262)
node _T_1304 = or(_T_1303, _T_1263)
node _T_1305 = or(_T_1304, _T_1264)
node _T_1306 = or(_T_1305, _T_1265)
node _T_1307 = or(_T_1306, _T_1266)
node _T_1308 = or(_T_1307, _T_1267)
node _T_1309 = or(_T_1308, _T_1268)
node _T_1310 = or(_T_1309, _T_1269)
node _T_1311 = or(_T_1310, _T_1270)
node _T_1312 = or(_T_1311, _T_1271)
node _T_1313 = or(_T_1312, _T_1272)
node _T_1314 = or(_T_1313, _T_1273)
node _T_1315 = and(_T_1211, _T_1314)
node _T_1316 = or(UInt<1>(0h0), _T_1315)
node _T_1317 = asUInt(reset)
node _T_1318 = eq(_T_1317, UInt<1>(0h0))
when _T_1318 :
node _T_1319 = eq(_T_1316, UInt<1>(0h0))
when _T_1319 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_1316, UInt<1>(0h1), "") : assert_19
node _T_1320 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1321 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1322 = and(_T_1320, _T_1321)
node _T_1323 = or(UInt<1>(0h0), _T_1322)
node _T_1324 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1325 = cvt(_T_1324)
node _T_1326 = and(_T_1325, asSInt(UInt<13>(0h1000)))
node _T_1327 = asSInt(_T_1326)
node _T_1328 = eq(_T_1327, asSInt(UInt<1>(0h0)))
node _T_1329 = and(_T_1323, _T_1328)
node _T_1330 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1331 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1332 = and(_T_1330, _T_1331)
node _T_1333 = or(UInt<1>(0h0), _T_1332)
node _T_1334 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1335 = cvt(_T_1334)
node _T_1336 = and(_T_1335, asSInt(UInt<14>(0h2000)))
node _T_1337 = asSInt(_T_1336)
node _T_1338 = eq(_T_1337, asSInt(UInt<1>(0h0)))
node _T_1339 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1340 = cvt(_T_1339)
node _T_1341 = and(_T_1340, asSInt(UInt<17>(0h10000)))
node _T_1342 = asSInt(_T_1341)
node _T_1343 = eq(_T_1342, asSInt(UInt<1>(0h0)))
node _T_1344 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1345 = cvt(_T_1344)
node _T_1346 = and(_T_1345, asSInt(UInt<18>(0h2f000)))
node _T_1347 = asSInt(_T_1346)
node _T_1348 = eq(_T_1347, asSInt(UInt<1>(0h0)))
node _T_1349 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1350 = cvt(_T_1349)
node _T_1351 = and(_T_1350, asSInt(UInt<17>(0h10000)))
node _T_1352 = asSInt(_T_1351)
node _T_1353 = eq(_T_1352, asSInt(UInt<1>(0h0)))
node _T_1354 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1355 = cvt(_T_1354)
node _T_1356 = and(_T_1355, asSInt(UInt<13>(0h1000)))
node _T_1357 = asSInt(_T_1356)
node _T_1358 = eq(_T_1357, asSInt(UInt<1>(0h0)))
node _T_1359 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1360 = cvt(_T_1359)
node _T_1361 = and(_T_1360, asSInt(UInt<27>(0h4000000)))
node _T_1362 = asSInt(_T_1361)
node _T_1363 = eq(_T_1362, asSInt(UInt<1>(0h0)))
node _T_1364 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1365 = cvt(_T_1364)
node _T_1366 = and(_T_1365, asSInt(UInt<13>(0h1000)))
node _T_1367 = asSInt(_T_1366)
node _T_1368 = eq(_T_1367, asSInt(UInt<1>(0h0)))
node _T_1369 = or(_T_1338, _T_1343)
node _T_1370 = or(_T_1369, _T_1348)
node _T_1371 = or(_T_1370, _T_1353)
node _T_1372 = or(_T_1371, _T_1358)
node _T_1373 = or(_T_1372, _T_1363)
node _T_1374 = or(_T_1373, _T_1368)
node _T_1375 = and(_T_1333, _T_1374)
node _T_1376 = or(UInt<1>(0h0), _T_1329)
node _T_1377 = or(_T_1376, _T_1375)
node _T_1378 = asUInt(reset)
node _T_1379 = eq(_T_1378, UInt<1>(0h0))
when _T_1379 :
node _T_1380 = eq(_T_1377, UInt<1>(0h0))
when _T_1380 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_1377, UInt<1>(0h1), "") : assert_20
node _T_1381 = asUInt(reset)
node _T_1382 = eq(_T_1381, UInt<1>(0h0))
when _T_1382 :
node _T_1383 = eq(source_ok, UInt<1>(0h0))
when _T_1383 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_1384 = asUInt(reset)
node _T_1385 = eq(_T_1384, UInt<1>(0h0))
when _T_1385 :
node _T_1386 = eq(is_aligned, UInt<1>(0h0))
when _T_1386 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_1387 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_1388 = asUInt(reset)
node _T_1389 = eq(_T_1388, UInt<1>(0h0))
when _T_1389 :
node _T_1390 = eq(_T_1387, UInt<1>(0h0))
when _T_1390 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_1387, UInt<1>(0h1), "") : assert_23
node _T_1391 = eq(io.in.a.bits.mask, mask)
node _T_1392 = asUInt(reset)
node _T_1393 = eq(_T_1392, UInt<1>(0h0))
when _T_1393 :
node _T_1394 = eq(_T_1391, UInt<1>(0h0))
when _T_1394 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_1391, UInt<1>(0h1), "") : assert_24
node _T_1395 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1396 = asUInt(reset)
node _T_1397 = eq(_T_1396, UInt<1>(0h0))
when _T_1397 :
node _T_1398 = eq(_T_1395, UInt<1>(0h0))
when _T_1398 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_1395, UInt<1>(0h1), "") : assert_25
node _T_1399 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_1399 :
node _T_1400 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1401 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1402 = and(_T_1400, _T_1401)
node _T_1403 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_1404 = shr(io.in.a.bits.source, 2)
node _T_1405 = eq(_T_1404, UInt<1>(0h0))
node _T_1406 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_1407 = and(_T_1405, _T_1406)
node _T_1408 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_1409 = and(_T_1407, _T_1408)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_1410 = shr(io.in.a.bits.source, 2)
node _T_1411 = eq(_T_1410, UInt<1>(0h1))
node _T_1412 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_1413 = and(_T_1411, _T_1412)
node _T_1414 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_1415 = and(_T_1413, _T_1414)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_1416 = shr(io.in.a.bits.source, 2)
node _T_1417 = eq(_T_1416, UInt<2>(0h2))
node _T_1418 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_1419 = and(_T_1417, _T_1418)
node _T_1420 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_1421 = and(_T_1419, _T_1420)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_1422 = shr(io.in.a.bits.source, 2)
node _T_1423 = eq(_T_1422, UInt<2>(0h3))
node _T_1424 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_1425 = and(_T_1423, _T_1424)
node _T_1426 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_1427 = and(_T_1425, _T_1426)
node _T_1428 = eq(io.in.a.bits.source, UInt<7>(0h4c))
node _T_1429 = eq(io.in.a.bits.source, UInt<7>(0h4d))
node _T_1430 = eq(io.in.a.bits.source, UInt<7>(0h4e))
node _T_1431 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_1432 = eq(io.in.a.bits.source, UInt<7>(0h49))
node _T_1433 = eq(io.in.a.bits.source, UInt<7>(0h4a))
node _T_1434 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_1435 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_1436 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_1437 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1438 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_1439 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_1440 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_1441 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_1442 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_1443 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_1444 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_1445 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_1446 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_1447 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_1448 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_1449 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_1450 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_1451 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_1452 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1453 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_1454 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1455 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1456 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1457 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1458 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1459 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1460 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1461 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1462 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1463 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1464 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_1465 = or(_T_1403, _T_1409)
node _T_1466 = or(_T_1465, _T_1415)
node _T_1467 = or(_T_1466, _T_1421)
node _T_1468 = or(_T_1467, _T_1427)
node _T_1469 = or(_T_1468, _T_1428)
node _T_1470 = or(_T_1469, _T_1429)
node _T_1471 = or(_T_1470, _T_1430)
node _T_1472 = or(_T_1471, _T_1431)
node _T_1473 = or(_T_1472, _T_1432)
node _T_1474 = or(_T_1473, _T_1433)
node _T_1475 = or(_T_1474, _T_1434)
node _T_1476 = or(_T_1475, _T_1435)
node _T_1477 = or(_T_1476, _T_1436)
node _T_1478 = or(_T_1477, _T_1437)
node _T_1479 = or(_T_1478, _T_1438)
node _T_1480 = or(_T_1479, _T_1439)
node _T_1481 = or(_T_1480, _T_1440)
node _T_1482 = or(_T_1481, _T_1441)
node _T_1483 = or(_T_1482, _T_1442)
node _T_1484 = or(_T_1483, _T_1443)
node _T_1485 = or(_T_1484, _T_1444)
node _T_1486 = or(_T_1485, _T_1445)
node _T_1487 = or(_T_1486, _T_1446)
node _T_1488 = or(_T_1487, _T_1447)
node _T_1489 = or(_T_1488, _T_1448)
node _T_1490 = or(_T_1489, _T_1449)
node _T_1491 = or(_T_1490, _T_1450)
node _T_1492 = or(_T_1491, _T_1451)
node _T_1493 = or(_T_1492, _T_1452)
node _T_1494 = or(_T_1493, _T_1453)
node _T_1495 = or(_T_1494, _T_1454)
node _T_1496 = or(_T_1495, _T_1455)
node _T_1497 = or(_T_1496, _T_1456)
node _T_1498 = or(_T_1497, _T_1457)
node _T_1499 = or(_T_1498, _T_1458)
node _T_1500 = or(_T_1499, _T_1459)
node _T_1501 = or(_T_1500, _T_1460)
node _T_1502 = or(_T_1501, _T_1461)
node _T_1503 = or(_T_1502, _T_1462)
node _T_1504 = or(_T_1503, _T_1463)
node _T_1505 = or(_T_1504, _T_1464)
node _T_1506 = and(_T_1402, _T_1505)
node _T_1507 = or(UInt<1>(0h0), _T_1506)
node _T_1508 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1509 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1510 = and(_T_1508, _T_1509)
node _T_1511 = or(UInt<1>(0h0), _T_1510)
node _T_1512 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1513 = cvt(_T_1512)
node _T_1514 = and(_T_1513, asSInt(UInt<13>(0h1000)))
node _T_1515 = asSInt(_T_1514)
node _T_1516 = eq(_T_1515, asSInt(UInt<1>(0h0)))
node _T_1517 = and(_T_1511, _T_1516)
node _T_1518 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1519 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1520 = and(_T_1518, _T_1519)
node _T_1521 = or(UInt<1>(0h0), _T_1520)
node _T_1522 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1523 = cvt(_T_1522)
node _T_1524 = and(_T_1523, asSInt(UInt<14>(0h2000)))
node _T_1525 = asSInt(_T_1524)
node _T_1526 = eq(_T_1525, asSInt(UInt<1>(0h0)))
node _T_1527 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1528 = cvt(_T_1527)
node _T_1529 = and(_T_1528, asSInt(UInt<18>(0h2f000)))
node _T_1530 = asSInt(_T_1529)
node _T_1531 = eq(_T_1530, asSInt(UInt<1>(0h0)))
node _T_1532 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1533 = cvt(_T_1532)
node _T_1534 = and(_T_1533, asSInt(UInt<17>(0h10000)))
node _T_1535 = asSInt(_T_1534)
node _T_1536 = eq(_T_1535, asSInt(UInt<1>(0h0)))
node _T_1537 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1538 = cvt(_T_1537)
node _T_1539 = and(_T_1538, asSInt(UInt<13>(0h1000)))
node _T_1540 = asSInt(_T_1539)
node _T_1541 = eq(_T_1540, asSInt(UInt<1>(0h0)))
node _T_1542 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1543 = cvt(_T_1542)
node _T_1544 = and(_T_1543, asSInt(UInt<27>(0h4000000)))
node _T_1545 = asSInt(_T_1544)
node _T_1546 = eq(_T_1545, asSInt(UInt<1>(0h0)))
node _T_1547 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1548 = cvt(_T_1547)
node _T_1549 = and(_T_1548, asSInt(UInt<13>(0h1000)))
node _T_1550 = asSInt(_T_1549)
node _T_1551 = eq(_T_1550, asSInt(UInt<1>(0h0)))
node _T_1552 = or(_T_1526, _T_1531)
node _T_1553 = or(_T_1552, _T_1536)
node _T_1554 = or(_T_1553, _T_1541)
node _T_1555 = or(_T_1554, _T_1546)
node _T_1556 = or(_T_1555, _T_1551)
node _T_1557 = and(_T_1521, _T_1556)
node _T_1558 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1559 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1560 = cvt(_T_1559)
node _T_1561 = and(_T_1560, asSInt(UInt<17>(0h10000)))
node _T_1562 = asSInt(_T_1561)
node _T_1563 = eq(_T_1562, asSInt(UInt<1>(0h0)))
node _T_1564 = and(_T_1558, _T_1563)
node _T_1565 = or(UInt<1>(0h0), _T_1517)
node _T_1566 = or(_T_1565, _T_1557)
node _T_1567 = or(_T_1566, _T_1564)
node _T_1568 = and(_T_1507, _T_1567)
node _T_1569 = asUInt(reset)
node _T_1570 = eq(_T_1569, UInt<1>(0h0))
when _T_1570 :
node _T_1571 = eq(_T_1568, UInt<1>(0h0))
when _T_1571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_1568, UInt<1>(0h1), "") : assert_26
node _T_1572 = asUInt(reset)
node _T_1573 = eq(_T_1572, UInt<1>(0h0))
when _T_1573 :
node _T_1574 = eq(source_ok, UInt<1>(0h0))
when _T_1574 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_1575 = asUInt(reset)
node _T_1576 = eq(_T_1575, UInt<1>(0h0))
when _T_1576 :
node _T_1577 = eq(is_aligned, UInt<1>(0h0))
when _T_1577 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_1578 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_1579 = asUInt(reset)
node _T_1580 = eq(_T_1579, UInt<1>(0h0))
when _T_1580 :
node _T_1581 = eq(_T_1578, UInt<1>(0h0))
when _T_1581 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_1578, UInt<1>(0h1), "") : assert_29
node _T_1582 = eq(io.in.a.bits.mask, mask)
node _T_1583 = asUInt(reset)
node _T_1584 = eq(_T_1583, UInt<1>(0h0))
when _T_1584 :
node _T_1585 = eq(_T_1582, UInt<1>(0h0))
when _T_1585 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_1582, UInt<1>(0h1), "") : assert_30
node _T_1586 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_1586 :
node _T_1587 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1588 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1589 = and(_T_1587, _T_1588)
node _T_1590 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_1591 = shr(io.in.a.bits.source, 2)
node _T_1592 = eq(_T_1591, UInt<1>(0h0))
node _T_1593 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_1594 = and(_T_1592, _T_1593)
node _T_1595 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_1596 = and(_T_1594, _T_1595)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_1597 = shr(io.in.a.bits.source, 2)
node _T_1598 = eq(_T_1597, UInt<1>(0h1))
node _T_1599 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_1600 = and(_T_1598, _T_1599)
node _T_1601 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_1602 = and(_T_1600, _T_1601)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_1603 = shr(io.in.a.bits.source, 2)
node _T_1604 = eq(_T_1603, UInt<2>(0h2))
node _T_1605 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_1606 = and(_T_1604, _T_1605)
node _T_1607 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_1608 = and(_T_1606, _T_1607)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_1609 = shr(io.in.a.bits.source, 2)
node _T_1610 = eq(_T_1609, UInt<2>(0h3))
node _T_1611 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_1612 = and(_T_1610, _T_1611)
node _T_1613 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_1614 = and(_T_1612, _T_1613)
node _T_1615 = eq(io.in.a.bits.source, UInt<7>(0h4c))
node _T_1616 = eq(io.in.a.bits.source, UInt<7>(0h4d))
node _T_1617 = eq(io.in.a.bits.source, UInt<7>(0h4e))
node _T_1618 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_1619 = eq(io.in.a.bits.source, UInt<7>(0h49))
node _T_1620 = eq(io.in.a.bits.source, UInt<7>(0h4a))
node _T_1621 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_1622 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_1623 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_1624 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1625 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_1626 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_1627 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_1628 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_1629 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_1630 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_1631 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_1632 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_1633 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_1634 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_1635 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_1636 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_1637 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_1638 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_1639 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1640 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_1641 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1642 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1643 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1644 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1645 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1646 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1647 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1648 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1649 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1650 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1651 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_1652 = or(_T_1590, _T_1596)
node _T_1653 = or(_T_1652, _T_1602)
node _T_1654 = or(_T_1653, _T_1608)
node _T_1655 = or(_T_1654, _T_1614)
node _T_1656 = or(_T_1655, _T_1615)
node _T_1657 = or(_T_1656, _T_1616)
node _T_1658 = or(_T_1657, _T_1617)
node _T_1659 = or(_T_1658, _T_1618)
node _T_1660 = or(_T_1659, _T_1619)
node _T_1661 = or(_T_1660, _T_1620)
node _T_1662 = or(_T_1661, _T_1621)
node _T_1663 = or(_T_1662, _T_1622)
node _T_1664 = or(_T_1663, _T_1623)
node _T_1665 = or(_T_1664, _T_1624)
node _T_1666 = or(_T_1665, _T_1625)
node _T_1667 = or(_T_1666, _T_1626)
node _T_1668 = or(_T_1667, _T_1627)
node _T_1669 = or(_T_1668, _T_1628)
node _T_1670 = or(_T_1669, _T_1629)
node _T_1671 = or(_T_1670, _T_1630)
node _T_1672 = or(_T_1671, _T_1631)
node _T_1673 = or(_T_1672, _T_1632)
node _T_1674 = or(_T_1673, _T_1633)
node _T_1675 = or(_T_1674, _T_1634)
node _T_1676 = or(_T_1675, _T_1635)
node _T_1677 = or(_T_1676, _T_1636)
node _T_1678 = or(_T_1677, _T_1637)
node _T_1679 = or(_T_1678, _T_1638)
node _T_1680 = or(_T_1679, _T_1639)
node _T_1681 = or(_T_1680, _T_1640)
node _T_1682 = or(_T_1681, _T_1641)
node _T_1683 = or(_T_1682, _T_1642)
node _T_1684 = or(_T_1683, _T_1643)
node _T_1685 = or(_T_1684, _T_1644)
node _T_1686 = or(_T_1685, _T_1645)
node _T_1687 = or(_T_1686, _T_1646)
node _T_1688 = or(_T_1687, _T_1647)
node _T_1689 = or(_T_1688, _T_1648)
node _T_1690 = or(_T_1689, _T_1649)
node _T_1691 = or(_T_1690, _T_1650)
node _T_1692 = or(_T_1691, _T_1651)
node _T_1693 = and(_T_1589, _T_1692)
node _T_1694 = or(UInt<1>(0h0), _T_1693)
node _T_1695 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1696 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1697 = and(_T_1695, _T_1696)
node _T_1698 = or(UInt<1>(0h0), _T_1697)
node _T_1699 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1700 = cvt(_T_1699)
node _T_1701 = and(_T_1700, asSInt(UInt<13>(0h1000)))
node _T_1702 = asSInt(_T_1701)
node _T_1703 = eq(_T_1702, asSInt(UInt<1>(0h0)))
node _T_1704 = and(_T_1698, _T_1703)
node _T_1705 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1706 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1707 = and(_T_1705, _T_1706)
node _T_1708 = or(UInt<1>(0h0), _T_1707)
node _T_1709 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1710 = cvt(_T_1709)
node _T_1711 = and(_T_1710, asSInt(UInt<14>(0h2000)))
node _T_1712 = asSInt(_T_1711)
node _T_1713 = eq(_T_1712, asSInt(UInt<1>(0h0)))
node _T_1714 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1715 = cvt(_T_1714)
node _T_1716 = and(_T_1715, asSInt(UInt<18>(0h2f000)))
node _T_1717 = asSInt(_T_1716)
node _T_1718 = eq(_T_1717, asSInt(UInt<1>(0h0)))
node _T_1719 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1720 = cvt(_T_1719)
node _T_1721 = and(_T_1720, asSInt(UInt<17>(0h10000)))
node _T_1722 = asSInt(_T_1721)
node _T_1723 = eq(_T_1722, asSInt(UInt<1>(0h0)))
node _T_1724 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1725 = cvt(_T_1724)
node _T_1726 = and(_T_1725, asSInt(UInt<13>(0h1000)))
node _T_1727 = asSInt(_T_1726)
node _T_1728 = eq(_T_1727, asSInt(UInt<1>(0h0)))
node _T_1729 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1730 = cvt(_T_1729)
node _T_1731 = and(_T_1730, asSInt(UInt<27>(0h4000000)))
node _T_1732 = asSInt(_T_1731)
node _T_1733 = eq(_T_1732, asSInt(UInt<1>(0h0)))
node _T_1734 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1735 = cvt(_T_1734)
node _T_1736 = and(_T_1735, asSInt(UInt<13>(0h1000)))
node _T_1737 = asSInt(_T_1736)
node _T_1738 = eq(_T_1737, asSInt(UInt<1>(0h0)))
node _T_1739 = or(_T_1713, _T_1718)
node _T_1740 = or(_T_1739, _T_1723)
node _T_1741 = or(_T_1740, _T_1728)
node _T_1742 = or(_T_1741, _T_1733)
node _T_1743 = or(_T_1742, _T_1738)
node _T_1744 = and(_T_1708, _T_1743)
node _T_1745 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1746 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1747 = cvt(_T_1746)
node _T_1748 = and(_T_1747, asSInt(UInt<17>(0h10000)))
node _T_1749 = asSInt(_T_1748)
node _T_1750 = eq(_T_1749, asSInt(UInt<1>(0h0)))
node _T_1751 = and(_T_1745, _T_1750)
node _T_1752 = or(UInt<1>(0h0), _T_1704)
node _T_1753 = or(_T_1752, _T_1744)
node _T_1754 = or(_T_1753, _T_1751)
node _T_1755 = and(_T_1694, _T_1754)
node _T_1756 = asUInt(reset)
node _T_1757 = eq(_T_1756, UInt<1>(0h0))
when _T_1757 :
node _T_1758 = eq(_T_1755, UInt<1>(0h0))
when _T_1758 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_1755, UInt<1>(0h1), "") : assert_31
node _T_1759 = asUInt(reset)
node _T_1760 = eq(_T_1759, UInt<1>(0h0))
when _T_1760 :
node _T_1761 = eq(source_ok, UInt<1>(0h0))
when _T_1761 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_1762 = asUInt(reset)
node _T_1763 = eq(_T_1762, UInt<1>(0h0))
when _T_1763 :
node _T_1764 = eq(is_aligned, UInt<1>(0h0))
when _T_1764 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_1765 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_1766 = asUInt(reset)
node _T_1767 = eq(_T_1766, UInt<1>(0h0))
when _T_1767 :
node _T_1768 = eq(_T_1765, UInt<1>(0h0))
when _T_1768 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_1765, UInt<1>(0h1), "") : assert_34
node _T_1769 = not(mask)
node _T_1770 = and(io.in.a.bits.mask, _T_1769)
node _T_1771 = eq(_T_1770, UInt<1>(0h0))
node _T_1772 = asUInt(reset)
node _T_1773 = eq(_T_1772, UInt<1>(0h0))
when _T_1773 :
node _T_1774 = eq(_T_1771, UInt<1>(0h0))
when _T_1774 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_1771, UInt<1>(0h1), "") : assert_35
node _T_1775 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_1775 :
node _T_1776 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1777 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1778 = and(_T_1776, _T_1777)
node _T_1779 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_1780 = shr(io.in.a.bits.source, 2)
node _T_1781 = eq(_T_1780, UInt<1>(0h0))
node _T_1782 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_1783 = and(_T_1781, _T_1782)
node _T_1784 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_1785 = and(_T_1783, _T_1784)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_1786 = shr(io.in.a.bits.source, 2)
node _T_1787 = eq(_T_1786, UInt<1>(0h1))
node _T_1788 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_1789 = and(_T_1787, _T_1788)
node _T_1790 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_1791 = and(_T_1789, _T_1790)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_1792 = shr(io.in.a.bits.source, 2)
node _T_1793 = eq(_T_1792, UInt<2>(0h2))
node _T_1794 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_1795 = and(_T_1793, _T_1794)
node _T_1796 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_1797 = and(_T_1795, _T_1796)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_1798 = shr(io.in.a.bits.source, 2)
node _T_1799 = eq(_T_1798, UInt<2>(0h3))
node _T_1800 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_1801 = and(_T_1799, _T_1800)
node _T_1802 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_1803 = and(_T_1801, _T_1802)
node _T_1804 = eq(io.in.a.bits.source, UInt<7>(0h4c))
node _T_1805 = eq(io.in.a.bits.source, UInt<7>(0h4d))
node _T_1806 = eq(io.in.a.bits.source, UInt<7>(0h4e))
node _T_1807 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_1808 = eq(io.in.a.bits.source, UInt<7>(0h49))
node _T_1809 = eq(io.in.a.bits.source, UInt<7>(0h4a))
node _T_1810 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_1811 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_1812 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_1813 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1814 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_1815 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_1816 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_1817 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_1818 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_1819 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_1820 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_1821 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_1822 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_1823 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_1824 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_1825 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_1826 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_1827 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_1828 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1829 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_1830 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1831 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1832 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1833 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1834 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1835 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1836 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1837 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1838 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1839 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1840 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_1841 = or(_T_1779, _T_1785)
node _T_1842 = or(_T_1841, _T_1791)
node _T_1843 = or(_T_1842, _T_1797)
node _T_1844 = or(_T_1843, _T_1803)
node _T_1845 = or(_T_1844, _T_1804)
node _T_1846 = or(_T_1845, _T_1805)
node _T_1847 = or(_T_1846, _T_1806)
node _T_1848 = or(_T_1847, _T_1807)
node _T_1849 = or(_T_1848, _T_1808)
node _T_1850 = or(_T_1849, _T_1809)
node _T_1851 = or(_T_1850, _T_1810)
node _T_1852 = or(_T_1851, _T_1811)
node _T_1853 = or(_T_1852, _T_1812)
node _T_1854 = or(_T_1853, _T_1813)
node _T_1855 = or(_T_1854, _T_1814)
node _T_1856 = or(_T_1855, _T_1815)
node _T_1857 = or(_T_1856, _T_1816)
node _T_1858 = or(_T_1857, _T_1817)
node _T_1859 = or(_T_1858, _T_1818)
node _T_1860 = or(_T_1859, _T_1819)
node _T_1861 = or(_T_1860, _T_1820)
node _T_1862 = or(_T_1861, _T_1821)
node _T_1863 = or(_T_1862, _T_1822)
node _T_1864 = or(_T_1863, _T_1823)
node _T_1865 = or(_T_1864, _T_1824)
node _T_1866 = or(_T_1865, _T_1825)
node _T_1867 = or(_T_1866, _T_1826)
node _T_1868 = or(_T_1867, _T_1827)
node _T_1869 = or(_T_1868, _T_1828)
node _T_1870 = or(_T_1869, _T_1829)
node _T_1871 = or(_T_1870, _T_1830)
node _T_1872 = or(_T_1871, _T_1831)
node _T_1873 = or(_T_1872, _T_1832)
node _T_1874 = or(_T_1873, _T_1833)
node _T_1875 = or(_T_1874, _T_1834)
node _T_1876 = or(_T_1875, _T_1835)
node _T_1877 = or(_T_1876, _T_1836)
node _T_1878 = or(_T_1877, _T_1837)
node _T_1879 = or(_T_1878, _T_1838)
node _T_1880 = or(_T_1879, _T_1839)
node _T_1881 = or(_T_1880, _T_1840)
node _T_1882 = and(_T_1778, _T_1881)
node _T_1883 = or(UInt<1>(0h0), _T_1882)
node _T_1884 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1885 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1886 = and(_T_1884, _T_1885)
node _T_1887 = or(UInt<1>(0h0), _T_1886)
node _T_1888 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_1889 = cvt(_T_1888)
node _T_1890 = and(_T_1889, asSInt(UInt<15>(0h5000)))
node _T_1891 = asSInt(_T_1890)
node _T_1892 = eq(_T_1891, asSInt(UInt<1>(0h0)))
node _T_1893 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1894 = cvt(_T_1893)
node _T_1895 = and(_T_1894, asSInt(UInt<13>(0h1000)))
node _T_1896 = asSInt(_T_1895)
node _T_1897 = eq(_T_1896, asSInt(UInt<1>(0h0)))
node _T_1898 = or(_T_1892, _T_1897)
node _T_1899 = and(_T_1887, _T_1898)
node _T_1900 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1901 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1902 = cvt(_T_1901)
node _T_1903 = and(_T_1902, asSInt(UInt<13>(0h1000)))
node _T_1904 = asSInt(_T_1903)
node _T_1905 = eq(_T_1904, asSInt(UInt<1>(0h0)))
node _T_1906 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1907 = cvt(_T_1906)
node _T_1908 = and(_T_1907, asSInt(UInt<17>(0h10000)))
node _T_1909 = asSInt(_T_1908)
node _T_1910 = eq(_T_1909, asSInt(UInt<1>(0h0)))
node _T_1911 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1912 = cvt(_T_1911)
node _T_1913 = and(_T_1912, asSInt(UInt<18>(0h2f000)))
node _T_1914 = asSInt(_T_1913)
node _T_1915 = eq(_T_1914, asSInt(UInt<1>(0h0)))
node _T_1916 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1917 = cvt(_T_1916)
node _T_1918 = and(_T_1917, asSInt(UInt<17>(0h10000)))
node _T_1919 = asSInt(_T_1918)
node _T_1920 = eq(_T_1919, asSInt(UInt<1>(0h0)))
node _T_1921 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1922 = cvt(_T_1921)
node _T_1923 = and(_T_1922, asSInt(UInt<13>(0h1000)))
node _T_1924 = asSInt(_T_1923)
node _T_1925 = eq(_T_1924, asSInt(UInt<1>(0h0)))
node _T_1926 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1927 = cvt(_T_1926)
node _T_1928 = and(_T_1927, asSInt(UInt<27>(0h4000000)))
node _T_1929 = asSInt(_T_1928)
node _T_1930 = eq(_T_1929, asSInt(UInt<1>(0h0)))
node _T_1931 = or(_T_1905, _T_1910)
node _T_1932 = or(_T_1931, _T_1915)
node _T_1933 = or(_T_1932, _T_1920)
node _T_1934 = or(_T_1933, _T_1925)
node _T_1935 = or(_T_1934, _T_1930)
node _T_1936 = and(_T_1900, _T_1935)
node _T_1937 = or(UInt<1>(0h0), _T_1899)
node _T_1938 = or(_T_1937, _T_1936)
node _T_1939 = and(_T_1883, _T_1938)
node _T_1940 = asUInt(reset)
node _T_1941 = eq(_T_1940, UInt<1>(0h0))
when _T_1941 :
node _T_1942 = eq(_T_1939, UInt<1>(0h0))
when _T_1942 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_1939, UInt<1>(0h1), "") : assert_36
node _T_1943 = asUInt(reset)
node _T_1944 = eq(_T_1943, UInt<1>(0h0))
when _T_1944 :
node _T_1945 = eq(source_ok, UInt<1>(0h0))
when _T_1945 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_1946 = asUInt(reset)
node _T_1947 = eq(_T_1946, UInt<1>(0h0))
when _T_1947 :
node _T_1948 = eq(is_aligned, UInt<1>(0h0))
when _T_1948 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_1949 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_1950 = asUInt(reset)
node _T_1951 = eq(_T_1950, UInt<1>(0h0))
when _T_1951 :
node _T_1952 = eq(_T_1949, UInt<1>(0h0))
when _T_1952 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_1949, UInt<1>(0h1), "") : assert_39
node _T_1953 = eq(io.in.a.bits.mask, mask)
node _T_1954 = asUInt(reset)
node _T_1955 = eq(_T_1954, UInt<1>(0h0))
when _T_1955 :
node _T_1956 = eq(_T_1953, UInt<1>(0h0))
when _T_1956 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_1953, UInt<1>(0h1), "") : assert_40
node _T_1957 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_1957 :
node _T_1958 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1959 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1960 = and(_T_1958, _T_1959)
node _T_1961 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_1962 = shr(io.in.a.bits.source, 2)
node _T_1963 = eq(_T_1962, UInt<1>(0h0))
node _T_1964 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_1965 = and(_T_1963, _T_1964)
node _T_1966 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_1967 = and(_T_1965, _T_1966)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_1968 = shr(io.in.a.bits.source, 2)
node _T_1969 = eq(_T_1968, UInt<1>(0h1))
node _T_1970 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_1971 = and(_T_1969, _T_1970)
node _T_1972 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_1973 = and(_T_1971, _T_1972)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_1974 = shr(io.in.a.bits.source, 2)
node _T_1975 = eq(_T_1974, UInt<2>(0h2))
node _T_1976 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_1977 = and(_T_1975, _T_1976)
node _T_1978 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_1979 = and(_T_1977, _T_1978)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_1980 = shr(io.in.a.bits.source, 2)
node _T_1981 = eq(_T_1980, UInt<2>(0h3))
node _T_1982 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_1983 = and(_T_1981, _T_1982)
node _T_1984 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_1985 = and(_T_1983, _T_1984)
node _T_1986 = eq(io.in.a.bits.source, UInt<7>(0h4c))
node _T_1987 = eq(io.in.a.bits.source, UInt<7>(0h4d))
node _T_1988 = eq(io.in.a.bits.source, UInt<7>(0h4e))
node _T_1989 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_1990 = eq(io.in.a.bits.source, UInt<7>(0h49))
node _T_1991 = eq(io.in.a.bits.source, UInt<7>(0h4a))
node _T_1992 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_1993 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_1994 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_1995 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1996 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_1997 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_1998 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_1999 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_2000 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_2001 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_2002 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_2003 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_2004 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_2005 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_2006 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_2007 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_2008 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_2009 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_2010 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_2011 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_2012 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_2013 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_2014 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_2015 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_2016 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_2017 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_2018 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_2019 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_2020 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_2021 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_2022 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_2023 = or(_T_1961, _T_1967)
node _T_2024 = or(_T_2023, _T_1973)
node _T_2025 = or(_T_2024, _T_1979)
node _T_2026 = or(_T_2025, _T_1985)
node _T_2027 = or(_T_2026, _T_1986)
node _T_2028 = or(_T_2027, _T_1987)
node _T_2029 = or(_T_2028, _T_1988)
node _T_2030 = or(_T_2029, _T_1989)
node _T_2031 = or(_T_2030, _T_1990)
node _T_2032 = or(_T_2031, _T_1991)
node _T_2033 = or(_T_2032, _T_1992)
node _T_2034 = or(_T_2033, _T_1993)
node _T_2035 = or(_T_2034, _T_1994)
node _T_2036 = or(_T_2035, _T_1995)
node _T_2037 = or(_T_2036, _T_1996)
node _T_2038 = or(_T_2037, _T_1997)
node _T_2039 = or(_T_2038, _T_1998)
node _T_2040 = or(_T_2039, _T_1999)
node _T_2041 = or(_T_2040, _T_2000)
node _T_2042 = or(_T_2041, _T_2001)
node _T_2043 = or(_T_2042, _T_2002)
node _T_2044 = or(_T_2043, _T_2003)
node _T_2045 = or(_T_2044, _T_2004)
node _T_2046 = or(_T_2045, _T_2005)
node _T_2047 = or(_T_2046, _T_2006)
node _T_2048 = or(_T_2047, _T_2007)
node _T_2049 = or(_T_2048, _T_2008)
node _T_2050 = or(_T_2049, _T_2009)
node _T_2051 = or(_T_2050, _T_2010)
node _T_2052 = or(_T_2051, _T_2011)
node _T_2053 = or(_T_2052, _T_2012)
node _T_2054 = or(_T_2053, _T_2013)
node _T_2055 = or(_T_2054, _T_2014)
node _T_2056 = or(_T_2055, _T_2015)
node _T_2057 = or(_T_2056, _T_2016)
node _T_2058 = or(_T_2057, _T_2017)
node _T_2059 = or(_T_2058, _T_2018)
node _T_2060 = or(_T_2059, _T_2019)
node _T_2061 = or(_T_2060, _T_2020)
node _T_2062 = or(_T_2061, _T_2021)
node _T_2063 = or(_T_2062, _T_2022)
node _T_2064 = and(_T_1960, _T_2063)
node _T_2065 = or(UInt<1>(0h0), _T_2064)
node _T_2066 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_2067 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_2068 = and(_T_2066, _T_2067)
node _T_2069 = or(UInt<1>(0h0), _T_2068)
node _T_2070 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_2071 = cvt(_T_2070)
node _T_2072 = and(_T_2071, asSInt(UInt<15>(0h5000)))
node _T_2073 = asSInt(_T_2072)
node _T_2074 = eq(_T_2073, asSInt(UInt<1>(0h0)))
node _T_2075 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_2076 = cvt(_T_2075)
node _T_2077 = and(_T_2076, asSInt(UInt<13>(0h1000)))
node _T_2078 = asSInt(_T_2077)
node _T_2079 = eq(_T_2078, asSInt(UInt<1>(0h0)))
node _T_2080 = or(_T_2074, _T_2079)
node _T_2081 = and(_T_2069, _T_2080)
node _T_2082 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_2083 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_2084 = cvt(_T_2083)
node _T_2085 = and(_T_2084, asSInt(UInt<13>(0h1000)))
node _T_2086 = asSInt(_T_2085)
node _T_2087 = eq(_T_2086, asSInt(UInt<1>(0h0)))
node _T_2088 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_2089 = cvt(_T_2088)
node _T_2090 = and(_T_2089, asSInt(UInt<17>(0h10000)))
node _T_2091 = asSInt(_T_2090)
node _T_2092 = eq(_T_2091, asSInt(UInt<1>(0h0)))
node _T_2093 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_2094 = cvt(_T_2093)
node _T_2095 = and(_T_2094, asSInt(UInt<18>(0h2f000)))
node _T_2096 = asSInt(_T_2095)
node _T_2097 = eq(_T_2096, asSInt(UInt<1>(0h0)))
node _T_2098 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_2099 = cvt(_T_2098)
node _T_2100 = and(_T_2099, asSInt(UInt<17>(0h10000)))
node _T_2101 = asSInt(_T_2100)
node _T_2102 = eq(_T_2101, asSInt(UInt<1>(0h0)))
node _T_2103 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_2104 = cvt(_T_2103)
node _T_2105 = and(_T_2104, asSInt(UInt<13>(0h1000)))
node _T_2106 = asSInt(_T_2105)
node _T_2107 = eq(_T_2106, asSInt(UInt<1>(0h0)))
node _T_2108 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_2109 = cvt(_T_2108)
node _T_2110 = and(_T_2109, asSInt(UInt<27>(0h4000000)))
node _T_2111 = asSInt(_T_2110)
node _T_2112 = eq(_T_2111, asSInt(UInt<1>(0h0)))
node _T_2113 = or(_T_2087, _T_2092)
node _T_2114 = or(_T_2113, _T_2097)
node _T_2115 = or(_T_2114, _T_2102)
node _T_2116 = or(_T_2115, _T_2107)
node _T_2117 = or(_T_2116, _T_2112)
node _T_2118 = and(_T_2082, _T_2117)
node _T_2119 = or(UInt<1>(0h0), _T_2081)
node _T_2120 = or(_T_2119, _T_2118)
node _T_2121 = and(_T_2065, _T_2120)
node _T_2122 = asUInt(reset)
node _T_2123 = eq(_T_2122, UInt<1>(0h0))
when _T_2123 :
node _T_2124 = eq(_T_2121, UInt<1>(0h0))
when _T_2124 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_2121, UInt<1>(0h1), "") : assert_41
node _T_2125 = asUInt(reset)
node _T_2126 = eq(_T_2125, UInt<1>(0h0))
when _T_2126 :
node _T_2127 = eq(source_ok, UInt<1>(0h0))
when _T_2127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_2128 = asUInt(reset)
node _T_2129 = eq(_T_2128, UInt<1>(0h0))
when _T_2129 :
node _T_2130 = eq(is_aligned, UInt<1>(0h0))
when _T_2130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_2131 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_2132 = asUInt(reset)
node _T_2133 = eq(_T_2132, UInt<1>(0h0))
when _T_2133 :
node _T_2134 = eq(_T_2131, UInt<1>(0h0))
when _T_2134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_2131, UInt<1>(0h1), "") : assert_44
node _T_2135 = eq(io.in.a.bits.mask, mask)
node _T_2136 = asUInt(reset)
node _T_2137 = eq(_T_2136, UInt<1>(0h0))
when _T_2137 :
node _T_2138 = eq(_T_2135, UInt<1>(0h0))
when _T_2138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_2135, UInt<1>(0h1), "") : assert_45
node _T_2139 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_2139 :
node _T_2140 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_2141 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_2142 = and(_T_2140, _T_2141)
node _T_2143 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_2144 = shr(io.in.a.bits.source, 2)
node _T_2145 = eq(_T_2144, UInt<1>(0h0))
node _T_2146 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_2147 = and(_T_2145, _T_2146)
node _T_2148 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_2149 = and(_T_2147, _T_2148)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_2150 = shr(io.in.a.bits.source, 2)
node _T_2151 = eq(_T_2150, UInt<1>(0h1))
node _T_2152 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_2153 = and(_T_2151, _T_2152)
node _T_2154 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_2155 = and(_T_2153, _T_2154)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_2156 = shr(io.in.a.bits.source, 2)
node _T_2157 = eq(_T_2156, UInt<2>(0h2))
node _T_2158 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_2159 = and(_T_2157, _T_2158)
node _T_2160 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_2161 = and(_T_2159, _T_2160)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_2162 = shr(io.in.a.bits.source, 2)
node _T_2163 = eq(_T_2162, UInt<2>(0h3))
node _T_2164 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_2165 = and(_T_2163, _T_2164)
node _T_2166 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_2167 = and(_T_2165, _T_2166)
node _T_2168 = eq(io.in.a.bits.source, UInt<7>(0h4c))
node _T_2169 = eq(io.in.a.bits.source, UInt<7>(0h4d))
node _T_2170 = eq(io.in.a.bits.source, UInt<7>(0h4e))
node _T_2171 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_2172 = eq(io.in.a.bits.source, UInt<7>(0h49))
node _T_2173 = eq(io.in.a.bits.source, UInt<7>(0h4a))
node _T_2174 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_2175 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_2176 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_2177 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_2178 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_2179 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_2180 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_2181 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_2182 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_2183 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_2184 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_2185 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_2186 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_2187 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_2188 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_2189 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_2190 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_2191 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_2192 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_2193 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_2194 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_2195 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_2196 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_2197 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_2198 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_2199 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_2200 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_2201 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_2202 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_2203 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_2204 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_2205 = or(_T_2143, _T_2149)
node _T_2206 = or(_T_2205, _T_2155)
node _T_2207 = or(_T_2206, _T_2161)
node _T_2208 = or(_T_2207, _T_2167)
node _T_2209 = or(_T_2208, _T_2168)
node _T_2210 = or(_T_2209, _T_2169)
node _T_2211 = or(_T_2210, _T_2170)
node _T_2212 = or(_T_2211, _T_2171)
node _T_2213 = or(_T_2212, _T_2172)
node _T_2214 = or(_T_2213, _T_2173)
node _T_2215 = or(_T_2214, _T_2174)
node _T_2216 = or(_T_2215, _T_2175)
node _T_2217 = or(_T_2216, _T_2176)
node _T_2218 = or(_T_2217, _T_2177)
node _T_2219 = or(_T_2218, _T_2178)
node _T_2220 = or(_T_2219, _T_2179)
node _T_2221 = or(_T_2220, _T_2180)
node _T_2222 = or(_T_2221, _T_2181)
node _T_2223 = or(_T_2222, _T_2182)
node _T_2224 = or(_T_2223, _T_2183)
node _T_2225 = or(_T_2224, _T_2184)
node _T_2226 = or(_T_2225, _T_2185)
node _T_2227 = or(_T_2226, _T_2186)
node _T_2228 = or(_T_2227, _T_2187)
node _T_2229 = or(_T_2228, _T_2188)
node _T_2230 = or(_T_2229, _T_2189)
node _T_2231 = or(_T_2230, _T_2190)
node _T_2232 = or(_T_2231, _T_2191)
node _T_2233 = or(_T_2232, _T_2192)
node _T_2234 = or(_T_2233, _T_2193)
node _T_2235 = or(_T_2234, _T_2194)
node _T_2236 = or(_T_2235, _T_2195)
node _T_2237 = or(_T_2236, _T_2196)
node _T_2238 = or(_T_2237, _T_2197)
node _T_2239 = or(_T_2238, _T_2198)
node _T_2240 = or(_T_2239, _T_2199)
node _T_2241 = or(_T_2240, _T_2200)
node _T_2242 = or(_T_2241, _T_2201)
node _T_2243 = or(_T_2242, _T_2202)
node _T_2244 = or(_T_2243, _T_2203)
node _T_2245 = or(_T_2244, _T_2204)
node _T_2246 = and(_T_2142, _T_2245)
node _T_2247 = or(UInt<1>(0h0), _T_2246)
node _T_2248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_2249 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_2250 = and(_T_2248, _T_2249)
node _T_2251 = or(UInt<1>(0h0), _T_2250)
node _T_2252 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_2253 = cvt(_T_2252)
node _T_2254 = and(_T_2253, asSInt(UInt<13>(0h1000)))
node _T_2255 = asSInt(_T_2254)
node _T_2256 = eq(_T_2255, asSInt(UInt<1>(0h0)))
node _T_2257 = and(_T_2251, _T_2256)
node _T_2258 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_2259 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_2260 = cvt(_T_2259)
node _T_2261 = and(_T_2260, asSInt(UInt<14>(0h2000)))
node _T_2262 = asSInt(_T_2261)
node _T_2263 = eq(_T_2262, asSInt(UInt<1>(0h0)))
node _T_2264 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_2265 = cvt(_T_2264)
node _T_2266 = and(_T_2265, asSInt(UInt<17>(0h10000)))
node _T_2267 = asSInt(_T_2266)
node _T_2268 = eq(_T_2267, asSInt(UInt<1>(0h0)))
node _T_2269 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_2270 = cvt(_T_2269)
node _T_2271 = and(_T_2270, asSInt(UInt<18>(0h2f000)))
node _T_2272 = asSInt(_T_2271)
node _T_2273 = eq(_T_2272, asSInt(UInt<1>(0h0)))
node _T_2274 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_2275 = cvt(_T_2274)
node _T_2276 = and(_T_2275, asSInt(UInt<17>(0h10000)))
node _T_2277 = asSInt(_T_2276)
node _T_2278 = eq(_T_2277, asSInt(UInt<1>(0h0)))
node _T_2279 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_2280 = cvt(_T_2279)
node _T_2281 = and(_T_2280, asSInt(UInt<13>(0h1000)))
node _T_2282 = asSInt(_T_2281)
node _T_2283 = eq(_T_2282, asSInt(UInt<1>(0h0)))
node _T_2284 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_2285 = cvt(_T_2284)
node _T_2286 = and(_T_2285, asSInt(UInt<27>(0h4000000)))
node _T_2287 = asSInt(_T_2286)
node _T_2288 = eq(_T_2287, asSInt(UInt<1>(0h0)))
node _T_2289 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_2290 = cvt(_T_2289)
node _T_2291 = and(_T_2290, asSInt(UInt<13>(0h1000)))
node _T_2292 = asSInt(_T_2291)
node _T_2293 = eq(_T_2292, asSInt(UInt<1>(0h0)))
node _T_2294 = or(_T_2263, _T_2268)
node _T_2295 = or(_T_2294, _T_2273)
node _T_2296 = or(_T_2295, _T_2278)
node _T_2297 = or(_T_2296, _T_2283)
node _T_2298 = or(_T_2297, _T_2288)
node _T_2299 = or(_T_2298, _T_2293)
node _T_2300 = and(_T_2258, _T_2299)
node _T_2301 = or(UInt<1>(0h0), _T_2257)
node _T_2302 = or(_T_2301, _T_2300)
node _T_2303 = and(_T_2247, _T_2302)
node _T_2304 = asUInt(reset)
node _T_2305 = eq(_T_2304, UInt<1>(0h0))
when _T_2305 :
node _T_2306 = eq(_T_2303, UInt<1>(0h0))
when _T_2306 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_2303, UInt<1>(0h1), "") : assert_46
node _T_2307 = asUInt(reset)
node _T_2308 = eq(_T_2307, UInt<1>(0h0))
when _T_2308 :
node _T_2309 = eq(source_ok, UInt<1>(0h0))
when _T_2309 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_2310 = asUInt(reset)
node _T_2311 = eq(_T_2310, UInt<1>(0h0))
when _T_2311 :
node _T_2312 = eq(is_aligned, UInt<1>(0h0))
when _T_2312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_2313 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_2314 = asUInt(reset)
node _T_2315 = eq(_T_2314, UInt<1>(0h0))
when _T_2315 :
node _T_2316 = eq(_T_2313, UInt<1>(0h0))
when _T_2316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_2313, UInt<1>(0h1), "") : assert_49
node _T_2317 = eq(io.in.a.bits.mask, mask)
node _T_2318 = asUInt(reset)
node _T_2319 = eq(_T_2318, UInt<1>(0h0))
when _T_2319 :
node _T_2320 = eq(_T_2317, UInt<1>(0h0))
when _T_2320 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_2317, UInt<1>(0h1), "") : assert_50
node _T_2321 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_2322 = asUInt(reset)
node _T_2323 = eq(_T_2322, UInt<1>(0h0))
when _T_2323 :
node _T_2324 = eq(_T_2321, UInt<1>(0h0))
when _T_2324 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_2321, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_2325 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2326 = asUInt(reset)
node _T_2327 = eq(_T_2326, UInt<1>(0h0))
when _T_2327 :
node _T_2328 = eq(_T_2325, UInt<1>(0h0))
when _T_2328 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_2325, UInt<1>(0h1), "") : assert_52
node _source_ok_T_102 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_103 = shr(io.in.d.bits.source, 2)
node _source_ok_T_104 = eq(_source_ok_T_103, UInt<1>(0h0))
node _source_ok_T_105 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105)
node _source_ok_T_107 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_109 = shr(io.in.d.bits.source, 2)
node _source_ok_T_110 = eq(_source_ok_T_109, UInt<1>(0h1))
node _source_ok_T_111 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_112 = and(_source_ok_T_110, _source_ok_T_111)
node _source_ok_T_113 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_114 = and(_source_ok_T_112, _source_ok_T_113)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_115 = shr(io.in.d.bits.source, 2)
node _source_ok_T_116 = eq(_source_ok_T_115, UInt<2>(0h2))
node _source_ok_T_117 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_118 = and(_source_ok_T_116, _source_ok_T_117)
node _source_ok_T_119 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_120 = and(_source_ok_T_118, _source_ok_T_119)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_121 = shr(io.in.d.bits.source, 2)
node _source_ok_T_122 = eq(_source_ok_T_121, UInt<2>(0h3))
node _source_ok_T_123 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_124 = and(_source_ok_T_122, _source_ok_T_123)
node _source_ok_T_125 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_126 = and(_source_ok_T_124, _source_ok_T_125)
node _source_ok_T_127 = eq(io.in.d.bits.source, UInt<7>(0h4c))
node _source_ok_T_128 = eq(io.in.d.bits.source, UInt<7>(0h4d))
node _source_ok_T_129 = eq(io.in.d.bits.source, UInt<7>(0h4e))
node _source_ok_T_130 = eq(io.in.d.bits.source, UInt<7>(0h48))
node _source_ok_T_131 = eq(io.in.d.bits.source, UInt<7>(0h49))
node _source_ok_T_132 = eq(io.in.d.bits.source, UInt<7>(0h4a))
node _source_ok_T_133 = eq(io.in.d.bits.source, UInt<7>(0h44))
node _source_ok_T_134 = eq(io.in.d.bits.source, UInt<7>(0h45))
node _source_ok_T_135 = eq(io.in.d.bits.source, UInt<7>(0h46))
node _source_ok_T_136 = eq(io.in.d.bits.source, UInt<7>(0h40))
node _source_ok_T_137 = eq(io.in.d.bits.source, UInt<7>(0h41))
node _source_ok_T_138 = eq(io.in.d.bits.source, UInt<7>(0h42))
node _source_ok_T_139 = eq(io.in.d.bits.source, UInt<6>(0h3c))
node _source_ok_T_140 = eq(io.in.d.bits.source, UInt<6>(0h3d))
node _source_ok_T_141 = eq(io.in.d.bits.source, UInt<6>(0h3e))
node _source_ok_T_142 = eq(io.in.d.bits.source, UInt<6>(0h38))
node _source_ok_T_143 = eq(io.in.d.bits.source, UInt<6>(0h39))
node _source_ok_T_144 = eq(io.in.d.bits.source, UInt<6>(0h3a))
node _source_ok_T_145 = eq(io.in.d.bits.source, UInt<6>(0h34))
node _source_ok_T_146 = eq(io.in.d.bits.source, UInt<6>(0h35))
node _source_ok_T_147 = eq(io.in.d.bits.source, UInt<6>(0h36))
node _source_ok_T_148 = eq(io.in.d.bits.source, UInt<6>(0h30))
node _source_ok_T_149 = eq(io.in.d.bits.source, UInt<6>(0h31))
node _source_ok_T_150 = eq(io.in.d.bits.source, UInt<6>(0h32))
node _source_ok_T_151 = eq(io.in.d.bits.source, UInt<6>(0h2c))
node _source_ok_T_152 = eq(io.in.d.bits.source, UInt<6>(0h2d))
node _source_ok_T_153 = eq(io.in.d.bits.source, UInt<6>(0h2e))
node _source_ok_T_154 = eq(io.in.d.bits.source, UInt<6>(0h28))
node _source_ok_T_155 = eq(io.in.d.bits.source, UInt<6>(0h29))
node _source_ok_T_156 = eq(io.in.d.bits.source, UInt<6>(0h2a))
node _source_ok_T_157 = eq(io.in.d.bits.source, UInt<6>(0h24))
node _source_ok_T_158 = eq(io.in.d.bits.source, UInt<6>(0h25))
node _source_ok_T_159 = eq(io.in.d.bits.source, UInt<6>(0h26))
node _source_ok_T_160 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_T_161 = eq(io.in.d.bits.source, UInt<6>(0h21))
node _source_ok_T_162 = eq(io.in.d.bits.source, UInt<6>(0h22))
node _source_ok_T_163 = eq(io.in.d.bits.source, UInt<8>(0h80))
wire _source_ok_WIRE_1 : UInt<1>[42]
connect _source_ok_WIRE_1[0], _source_ok_T_102
connect _source_ok_WIRE_1[1], _source_ok_T_108
connect _source_ok_WIRE_1[2], _source_ok_T_114
connect _source_ok_WIRE_1[3], _source_ok_T_120
connect _source_ok_WIRE_1[4], _source_ok_T_126
connect _source_ok_WIRE_1[5], _source_ok_T_127
connect _source_ok_WIRE_1[6], _source_ok_T_128
connect _source_ok_WIRE_1[7], _source_ok_T_129
connect _source_ok_WIRE_1[8], _source_ok_T_130
connect _source_ok_WIRE_1[9], _source_ok_T_131
connect _source_ok_WIRE_1[10], _source_ok_T_132
connect _source_ok_WIRE_1[11], _source_ok_T_133
connect _source_ok_WIRE_1[12], _source_ok_T_134
connect _source_ok_WIRE_1[13], _source_ok_T_135
connect _source_ok_WIRE_1[14], _source_ok_T_136
connect _source_ok_WIRE_1[15], _source_ok_T_137
connect _source_ok_WIRE_1[16], _source_ok_T_138
connect _source_ok_WIRE_1[17], _source_ok_T_139
connect _source_ok_WIRE_1[18], _source_ok_T_140
connect _source_ok_WIRE_1[19], _source_ok_T_141
connect _source_ok_WIRE_1[20], _source_ok_T_142
connect _source_ok_WIRE_1[21], _source_ok_T_143
connect _source_ok_WIRE_1[22], _source_ok_T_144
connect _source_ok_WIRE_1[23], _source_ok_T_145
connect _source_ok_WIRE_1[24], _source_ok_T_146
connect _source_ok_WIRE_1[25], _source_ok_T_147
connect _source_ok_WIRE_1[26], _source_ok_T_148
connect _source_ok_WIRE_1[27], _source_ok_T_149
connect _source_ok_WIRE_1[28], _source_ok_T_150
connect _source_ok_WIRE_1[29], _source_ok_T_151
connect _source_ok_WIRE_1[30], _source_ok_T_152
connect _source_ok_WIRE_1[31], _source_ok_T_153
connect _source_ok_WIRE_1[32], _source_ok_T_154
connect _source_ok_WIRE_1[33], _source_ok_T_155
connect _source_ok_WIRE_1[34], _source_ok_T_156
connect _source_ok_WIRE_1[35], _source_ok_T_157
connect _source_ok_WIRE_1[36], _source_ok_T_158
connect _source_ok_WIRE_1[37], _source_ok_T_159
connect _source_ok_WIRE_1[38], _source_ok_T_160
connect _source_ok_WIRE_1[39], _source_ok_T_161
connect _source_ok_WIRE_1[40], _source_ok_T_162
connect _source_ok_WIRE_1[41], _source_ok_T_163
node _source_ok_T_164 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_165 = or(_source_ok_T_164, _source_ok_WIRE_1[2])
node _source_ok_T_166 = or(_source_ok_T_165, _source_ok_WIRE_1[3])
node _source_ok_T_167 = or(_source_ok_T_166, _source_ok_WIRE_1[4])
node _source_ok_T_168 = or(_source_ok_T_167, _source_ok_WIRE_1[5])
node _source_ok_T_169 = or(_source_ok_T_168, _source_ok_WIRE_1[6])
node _source_ok_T_170 = or(_source_ok_T_169, _source_ok_WIRE_1[7])
node _source_ok_T_171 = or(_source_ok_T_170, _source_ok_WIRE_1[8])
node _source_ok_T_172 = or(_source_ok_T_171, _source_ok_WIRE_1[9])
node _source_ok_T_173 = or(_source_ok_T_172, _source_ok_WIRE_1[10])
node _source_ok_T_174 = or(_source_ok_T_173, _source_ok_WIRE_1[11])
node _source_ok_T_175 = or(_source_ok_T_174, _source_ok_WIRE_1[12])
node _source_ok_T_176 = or(_source_ok_T_175, _source_ok_WIRE_1[13])
node _source_ok_T_177 = or(_source_ok_T_176, _source_ok_WIRE_1[14])
node _source_ok_T_178 = or(_source_ok_T_177, _source_ok_WIRE_1[15])
node _source_ok_T_179 = or(_source_ok_T_178, _source_ok_WIRE_1[16])
node _source_ok_T_180 = or(_source_ok_T_179, _source_ok_WIRE_1[17])
node _source_ok_T_181 = or(_source_ok_T_180, _source_ok_WIRE_1[18])
node _source_ok_T_182 = or(_source_ok_T_181, _source_ok_WIRE_1[19])
node _source_ok_T_183 = or(_source_ok_T_182, _source_ok_WIRE_1[20])
node _source_ok_T_184 = or(_source_ok_T_183, _source_ok_WIRE_1[21])
node _source_ok_T_185 = or(_source_ok_T_184, _source_ok_WIRE_1[22])
node _source_ok_T_186 = or(_source_ok_T_185, _source_ok_WIRE_1[23])
node _source_ok_T_187 = or(_source_ok_T_186, _source_ok_WIRE_1[24])
node _source_ok_T_188 = or(_source_ok_T_187, _source_ok_WIRE_1[25])
node _source_ok_T_189 = or(_source_ok_T_188, _source_ok_WIRE_1[26])
node _source_ok_T_190 = or(_source_ok_T_189, _source_ok_WIRE_1[27])
node _source_ok_T_191 = or(_source_ok_T_190, _source_ok_WIRE_1[28])
node _source_ok_T_192 = or(_source_ok_T_191, _source_ok_WIRE_1[29])
node _source_ok_T_193 = or(_source_ok_T_192, _source_ok_WIRE_1[30])
node _source_ok_T_194 = or(_source_ok_T_193, _source_ok_WIRE_1[31])
node _source_ok_T_195 = or(_source_ok_T_194, _source_ok_WIRE_1[32])
node _source_ok_T_196 = or(_source_ok_T_195, _source_ok_WIRE_1[33])
node _source_ok_T_197 = or(_source_ok_T_196, _source_ok_WIRE_1[34])
node _source_ok_T_198 = or(_source_ok_T_197, _source_ok_WIRE_1[35])
node _source_ok_T_199 = or(_source_ok_T_198, _source_ok_WIRE_1[36])
node _source_ok_T_200 = or(_source_ok_T_199, _source_ok_WIRE_1[37])
node _source_ok_T_201 = or(_source_ok_T_200, _source_ok_WIRE_1[38])
node _source_ok_T_202 = or(_source_ok_T_201, _source_ok_WIRE_1[39])
node _source_ok_T_203 = or(_source_ok_T_202, _source_ok_WIRE_1[40])
node source_ok_1 = or(_source_ok_T_203, _source_ok_WIRE_1[41])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_2329 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_2329 :
node _T_2330 = asUInt(reset)
node _T_2331 = eq(_T_2330, UInt<1>(0h0))
when _T_2331 :
node _T_2332 = eq(source_ok_1, UInt<1>(0h0))
when _T_2332 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_2333 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_2334 = asUInt(reset)
node _T_2335 = eq(_T_2334, UInt<1>(0h0))
when _T_2335 :
node _T_2336 = eq(_T_2333, UInt<1>(0h0))
when _T_2336 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_2333, UInt<1>(0h1), "") : assert_54
node _T_2337 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_2338 = asUInt(reset)
node _T_2339 = eq(_T_2338, UInt<1>(0h0))
when _T_2339 :
node _T_2340 = eq(_T_2337, UInt<1>(0h0))
when _T_2340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_2337, UInt<1>(0h1), "") : assert_55
node _T_2341 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_2342 = asUInt(reset)
node _T_2343 = eq(_T_2342, UInt<1>(0h0))
when _T_2343 :
node _T_2344 = eq(_T_2341, UInt<1>(0h0))
when _T_2344 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_2341, UInt<1>(0h1), "") : assert_56
node _T_2345 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_2346 = asUInt(reset)
node _T_2347 = eq(_T_2346, UInt<1>(0h0))
when _T_2347 :
node _T_2348 = eq(_T_2345, UInt<1>(0h0))
when _T_2348 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_2345, UInt<1>(0h1), "") : assert_57
node _T_2349 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_2349 :
node _T_2350 = asUInt(reset)
node _T_2351 = eq(_T_2350, UInt<1>(0h0))
when _T_2351 :
node _T_2352 = eq(source_ok_1, UInt<1>(0h0))
when _T_2352 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_2353 = asUInt(reset)
node _T_2354 = eq(_T_2353, UInt<1>(0h0))
when _T_2354 :
node _T_2355 = eq(sink_ok, UInt<1>(0h0))
when _T_2355 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_2356 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_2357 = asUInt(reset)
node _T_2358 = eq(_T_2357, UInt<1>(0h0))
when _T_2358 :
node _T_2359 = eq(_T_2356, UInt<1>(0h0))
when _T_2359 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_2356, UInt<1>(0h1), "") : assert_60
node _T_2360 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_2361 = asUInt(reset)
node _T_2362 = eq(_T_2361, UInt<1>(0h0))
when _T_2362 :
node _T_2363 = eq(_T_2360, UInt<1>(0h0))
when _T_2363 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_2360, UInt<1>(0h1), "") : assert_61
node _T_2364 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_2365 = asUInt(reset)
node _T_2366 = eq(_T_2365, UInt<1>(0h0))
when _T_2366 :
node _T_2367 = eq(_T_2364, UInt<1>(0h0))
when _T_2367 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_2364, UInt<1>(0h1), "") : assert_62
node _T_2368 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_2369 = asUInt(reset)
node _T_2370 = eq(_T_2369, UInt<1>(0h0))
when _T_2370 :
node _T_2371 = eq(_T_2368, UInt<1>(0h0))
when _T_2371 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_2368, UInt<1>(0h1), "") : assert_63
node _T_2372 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_2373 = or(UInt<1>(0h1), _T_2372)
node _T_2374 = asUInt(reset)
node _T_2375 = eq(_T_2374, UInt<1>(0h0))
when _T_2375 :
node _T_2376 = eq(_T_2373, UInt<1>(0h0))
when _T_2376 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_2373, UInt<1>(0h1), "") : assert_64
node _T_2377 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_2377 :
node _T_2378 = asUInt(reset)
node _T_2379 = eq(_T_2378, UInt<1>(0h0))
when _T_2379 :
node _T_2380 = eq(source_ok_1, UInt<1>(0h0))
when _T_2380 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_2381 = asUInt(reset)
node _T_2382 = eq(_T_2381, UInt<1>(0h0))
when _T_2382 :
node _T_2383 = eq(sink_ok, UInt<1>(0h0))
when _T_2383 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_2384 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_2385 = asUInt(reset)
node _T_2386 = eq(_T_2385, UInt<1>(0h0))
when _T_2386 :
node _T_2387 = eq(_T_2384, UInt<1>(0h0))
when _T_2387 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_2384, UInt<1>(0h1), "") : assert_67
node _T_2388 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_2389 = asUInt(reset)
node _T_2390 = eq(_T_2389, UInt<1>(0h0))
when _T_2390 :
node _T_2391 = eq(_T_2388, UInt<1>(0h0))
when _T_2391 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_2388, UInt<1>(0h1), "") : assert_68
node _T_2392 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_2393 = asUInt(reset)
node _T_2394 = eq(_T_2393, UInt<1>(0h0))
when _T_2394 :
node _T_2395 = eq(_T_2392, UInt<1>(0h0))
when _T_2395 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_2392, UInt<1>(0h1), "") : assert_69
node _T_2396 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_2397 = or(_T_2396, io.in.d.bits.corrupt)
node _T_2398 = asUInt(reset)
node _T_2399 = eq(_T_2398, UInt<1>(0h0))
when _T_2399 :
node _T_2400 = eq(_T_2397, UInt<1>(0h0))
when _T_2400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_2397, UInt<1>(0h1), "") : assert_70
node _T_2401 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_2402 = or(UInt<1>(0h1), _T_2401)
node _T_2403 = asUInt(reset)
node _T_2404 = eq(_T_2403, UInt<1>(0h0))
when _T_2404 :
node _T_2405 = eq(_T_2402, UInt<1>(0h0))
when _T_2405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_2402, UInt<1>(0h1), "") : assert_71
node _T_2406 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_2406 :
node _T_2407 = asUInt(reset)
node _T_2408 = eq(_T_2407, UInt<1>(0h0))
when _T_2408 :
node _T_2409 = eq(source_ok_1, UInt<1>(0h0))
when _T_2409 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_2410 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_2411 = asUInt(reset)
node _T_2412 = eq(_T_2411, UInt<1>(0h0))
when _T_2412 :
node _T_2413 = eq(_T_2410, UInt<1>(0h0))
when _T_2413 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_2410, UInt<1>(0h1), "") : assert_73
node _T_2414 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_2415 = asUInt(reset)
node _T_2416 = eq(_T_2415, UInt<1>(0h0))
when _T_2416 :
node _T_2417 = eq(_T_2414, UInt<1>(0h0))
when _T_2417 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_2414, UInt<1>(0h1), "") : assert_74
node _T_2418 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_2419 = or(UInt<1>(0h1), _T_2418)
node _T_2420 = asUInt(reset)
node _T_2421 = eq(_T_2420, UInt<1>(0h0))
when _T_2421 :
node _T_2422 = eq(_T_2419, UInt<1>(0h0))
when _T_2422 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_2419, UInt<1>(0h1), "") : assert_75
node _T_2423 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_2423 :
node _T_2424 = asUInt(reset)
node _T_2425 = eq(_T_2424, UInt<1>(0h0))
when _T_2425 :
node _T_2426 = eq(source_ok_1, UInt<1>(0h0))
when _T_2426 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_2427 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_2428 = asUInt(reset)
node _T_2429 = eq(_T_2428, UInt<1>(0h0))
when _T_2429 :
node _T_2430 = eq(_T_2427, UInt<1>(0h0))
when _T_2430 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_2427, UInt<1>(0h1), "") : assert_77
node _T_2431 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_2432 = or(_T_2431, io.in.d.bits.corrupt)
node _T_2433 = asUInt(reset)
node _T_2434 = eq(_T_2433, UInt<1>(0h0))
when _T_2434 :
node _T_2435 = eq(_T_2432, UInt<1>(0h0))
when _T_2435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_2432, UInt<1>(0h1), "") : assert_78
node _T_2436 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_2437 = or(UInt<1>(0h1), _T_2436)
node _T_2438 = asUInt(reset)
node _T_2439 = eq(_T_2438, UInt<1>(0h0))
when _T_2439 :
node _T_2440 = eq(_T_2437, UInt<1>(0h0))
when _T_2440 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_2437, UInt<1>(0h1), "") : assert_79
node _T_2441 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_2441 :
node _T_2442 = asUInt(reset)
node _T_2443 = eq(_T_2442, UInt<1>(0h0))
when _T_2443 :
node _T_2444 = eq(source_ok_1, UInt<1>(0h0))
when _T_2444 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_2445 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_2446 = asUInt(reset)
node _T_2447 = eq(_T_2446, UInt<1>(0h0))
when _T_2447 :
node _T_2448 = eq(_T_2445, UInt<1>(0h0))
when _T_2448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_2445, UInt<1>(0h1), "") : assert_81
node _T_2449 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_2450 = asUInt(reset)
node _T_2451 = eq(_T_2450, UInt<1>(0h0))
when _T_2451 :
node _T_2452 = eq(_T_2449, UInt<1>(0h0))
when _T_2452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_2449, UInt<1>(0h1), "") : assert_82
node _T_2453 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_2454 = or(UInt<1>(0h1), _T_2453)
node _T_2455 = asUInt(reset)
node _T_2456 = eq(_T_2455, UInt<1>(0h0))
when _T_2456 :
node _T_2457 = eq(_T_2454, UInt<1>(0h0))
when _T_2457 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_2454, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<29>(0h0)
connect _WIRE_4.bits.source, UInt<8>(0h0)
connect _WIRE_4.bits.size, UInt<4>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_2458 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_2459 = asUInt(reset)
node _T_2460 = eq(_T_2459, UInt<1>(0h0))
when _T_2460 :
node _T_2461 = eq(_T_2458, UInt<1>(0h0))
when _T_2461 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_2458, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<8>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_2462 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_2463 = asUInt(reset)
node _T_2464 = eq(_T_2463, UInt<1>(0h0))
when _T_2464 :
node _T_2465 = eq(_T_2462, UInt<1>(0h0))
when _T_2465 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_2462, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_2466 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_2467 = asUInt(reset)
node _T_2468 = eq(_T_2467, UInt<1>(0h0))
when _T_2468 :
node _T_2469 = eq(_T_2466, UInt<1>(0h0))
when _T_2469 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_2466, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_2470 = eq(a_first, UInt<1>(0h0))
node _T_2471 = and(io.in.a.valid, _T_2470)
when _T_2471 :
node _T_2472 = eq(io.in.a.bits.opcode, opcode)
node _T_2473 = asUInt(reset)
node _T_2474 = eq(_T_2473, UInt<1>(0h0))
when _T_2474 :
node _T_2475 = eq(_T_2472, UInt<1>(0h0))
when _T_2475 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_2472, UInt<1>(0h1), "") : assert_87
node _T_2476 = eq(io.in.a.bits.param, param)
node _T_2477 = asUInt(reset)
node _T_2478 = eq(_T_2477, UInt<1>(0h0))
when _T_2478 :
node _T_2479 = eq(_T_2476, UInt<1>(0h0))
when _T_2479 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_2476, UInt<1>(0h1), "") : assert_88
node _T_2480 = eq(io.in.a.bits.size, size)
node _T_2481 = asUInt(reset)
node _T_2482 = eq(_T_2481, UInt<1>(0h0))
when _T_2482 :
node _T_2483 = eq(_T_2480, UInt<1>(0h0))
when _T_2483 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_2480, UInt<1>(0h1), "") : assert_89
node _T_2484 = eq(io.in.a.bits.source, source)
node _T_2485 = asUInt(reset)
node _T_2486 = eq(_T_2485, UInt<1>(0h0))
when _T_2486 :
node _T_2487 = eq(_T_2484, UInt<1>(0h0))
when _T_2487 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_2484, UInt<1>(0h1), "") : assert_90
node _T_2488 = eq(io.in.a.bits.address, address)
node _T_2489 = asUInt(reset)
node _T_2490 = eq(_T_2489, UInt<1>(0h0))
when _T_2490 :
node _T_2491 = eq(_T_2488, UInt<1>(0h0))
when _T_2491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_2488, UInt<1>(0h1), "") : assert_91
node _T_2492 = and(io.in.a.ready, io.in.a.valid)
node _T_2493 = and(_T_2492, a_first)
when _T_2493 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_2494 = eq(d_first, UInt<1>(0h0))
node _T_2495 = and(io.in.d.valid, _T_2494)
when _T_2495 :
node _T_2496 = eq(io.in.d.bits.opcode, opcode_1)
node _T_2497 = asUInt(reset)
node _T_2498 = eq(_T_2497, UInt<1>(0h0))
when _T_2498 :
node _T_2499 = eq(_T_2496, UInt<1>(0h0))
when _T_2499 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_2496, UInt<1>(0h1), "") : assert_92
node _T_2500 = eq(io.in.d.bits.param, param_1)
node _T_2501 = asUInt(reset)
node _T_2502 = eq(_T_2501, UInt<1>(0h0))
when _T_2502 :
node _T_2503 = eq(_T_2500, UInt<1>(0h0))
when _T_2503 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_2500, UInt<1>(0h1), "") : assert_93
node _T_2504 = eq(io.in.d.bits.size, size_1)
node _T_2505 = asUInt(reset)
node _T_2506 = eq(_T_2505, UInt<1>(0h0))
when _T_2506 :
node _T_2507 = eq(_T_2504, UInt<1>(0h0))
when _T_2507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_2504, UInt<1>(0h1), "") : assert_94
node _T_2508 = eq(io.in.d.bits.source, source_1)
node _T_2509 = asUInt(reset)
node _T_2510 = eq(_T_2509, UInt<1>(0h0))
when _T_2510 :
node _T_2511 = eq(_T_2508, UInt<1>(0h0))
when _T_2511 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_2508, UInt<1>(0h1), "") : assert_95
node _T_2512 = eq(io.in.d.bits.sink, sink)
node _T_2513 = asUInt(reset)
node _T_2514 = eq(_T_2513, UInt<1>(0h0))
when _T_2514 :
node _T_2515 = eq(_T_2512, UInt<1>(0h0))
when _T_2515 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_2512, UInt<1>(0h1), "") : assert_96
node _T_2516 = eq(io.in.d.bits.denied, denied)
node _T_2517 = asUInt(reset)
node _T_2518 = eq(_T_2517, UInt<1>(0h0))
when _T_2518 :
node _T_2519 = eq(_T_2516, UInt<1>(0h0))
when _T_2519 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_2516, UInt<1>(0h1), "") : assert_97
node _T_2520 = and(io.in.d.ready, io.in.d.valid)
node _T_2521 = and(_T_2520, d_first)
when _T_2521 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0)
regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0)
regreset inflight_sizes : UInt<1032>, clock, reset, UInt<1032>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<129>
connect a_set, UInt<129>(0h0)
wire a_set_wo_ready : UInt<129>
connect a_set_wo_ready, UInt<129>(0h0)
wire a_opcodes_set : UInt<516>
connect a_opcodes_set, UInt<516>(0h0)
wire a_sizes_set : UInt<1032>
connect a_sizes_set, UInt<1032>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_2522 = and(io.in.a.valid, a_first_1)
node _T_2523 = and(_T_2522, UInt<1>(0h1))
when _T_2523 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_2524 = and(io.in.a.ready, io.in.a.valid)
node _T_2525 = and(_T_2524, a_first_1)
node _T_2526 = and(_T_2525, UInt<1>(0h1))
when _T_2526 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_2527 = dshr(inflight, io.in.a.bits.source)
node _T_2528 = bits(_T_2527, 0, 0)
node _T_2529 = eq(_T_2528, UInt<1>(0h0))
node _T_2530 = asUInt(reset)
node _T_2531 = eq(_T_2530, UInt<1>(0h0))
when _T_2531 :
node _T_2532 = eq(_T_2529, UInt<1>(0h0))
when _T_2532 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_2529, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<129>
connect d_clr, UInt<129>(0h0)
wire d_clr_wo_ready : UInt<129>
connect d_clr_wo_ready, UInt<129>(0h0)
wire d_opcodes_clr : UInt<516>
connect d_opcodes_clr, UInt<516>(0h0)
wire d_sizes_clr : UInt<1032>
connect d_sizes_clr, UInt<1032>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2533 = and(io.in.d.valid, d_first_1)
node _T_2534 = and(_T_2533, UInt<1>(0h1))
node _T_2535 = eq(d_release_ack, UInt<1>(0h0))
node _T_2536 = and(_T_2534, _T_2535)
when _T_2536 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_2537 = and(io.in.d.ready, io.in.d.valid)
node _T_2538 = and(_T_2537, d_first_1)
node _T_2539 = and(_T_2538, UInt<1>(0h1))
node _T_2540 = eq(d_release_ack, UInt<1>(0h0))
node _T_2541 = and(_T_2539, _T_2540)
when _T_2541 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_2542 = and(io.in.d.valid, d_first_1)
node _T_2543 = and(_T_2542, UInt<1>(0h1))
node _T_2544 = eq(d_release_ack, UInt<1>(0h0))
node _T_2545 = and(_T_2543, _T_2544)
when _T_2545 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_2546 = dshr(inflight, io.in.d.bits.source)
node _T_2547 = bits(_T_2546, 0, 0)
node _T_2548 = or(_T_2547, same_cycle_resp)
node _T_2549 = asUInt(reset)
node _T_2550 = eq(_T_2549, UInt<1>(0h0))
when _T_2550 :
node _T_2551 = eq(_T_2548, UInt<1>(0h0))
when _T_2551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_2548, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_2552 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_2553 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_2554 = or(_T_2552, _T_2553)
node _T_2555 = asUInt(reset)
node _T_2556 = eq(_T_2555, UInt<1>(0h0))
when _T_2556 :
node _T_2557 = eq(_T_2554, UInt<1>(0h0))
when _T_2557 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_2554, UInt<1>(0h1), "") : assert_100
node _T_2558 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_2559 = asUInt(reset)
node _T_2560 = eq(_T_2559, UInt<1>(0h0))
when _T_2560 :
node _T_2561 = eq(_T_2558, UInt<1>(0h0))
when _T_2561 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_2558, UInt<1>(0h1), "") : assert_101
else :
node _T_2562 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_2563 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_2564 = or(_T_2562, _T_2563)
node _T_2565 = asUInt(reset)
node _T_2566 = eq(_T_2565, UInt<1>(0h0))
when _T_2566 :
node _T_2567 = eq(_T_2564, UInt<1>(0h0))
when _T_2567 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_2564, UInt<1>(0h1), "") : assert_102
node _T_2568 = eq(io.in.d.bits.size, a_size_lookup)
node _T_2569 = asUInt(reset)
node _T_2570 = eq(_T_2569, UInt<1>(0h0))
when _T_2570 :
node _T_2571 = eq(_T_2568, UInt<1>(0h0))
when _T_2571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_2568, UInt<1>(0h1), "") : assert_103
node _T_2572 = and(io.in.d.valid, d_first_1)
node _T_2573 = and(_T_2572, a_first_1)
node _T_2574 = and(_T_2573, io.in.a.valid)
node _T_2575 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_2576 = and(_T_2574, _T_2575)
node _T_2577 = eq(d_release_ack, UInt<1>(0h0))
node _T_2578 = and(_T_2576, _T_2577)
when _T_2578 :
node _T_2579 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2580 = or(_T_2579, io.in.a.ready)
node _T_2581 = asUInt(reset)
node _T_2582 = eq(_T_2581, UInt<1>(0h0))
when _T_2582 :
node _T_2583 = eq(_T_2580, UInt<1>(0h0))
when _T_2583 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_2580, UInt<1>(0h1), "") : assert_104
node _T_2584 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_2585 = orr(a_set_wo_ready)
node _T_2586 = eq(_T_2585, UInt<1>(0h0))
node _T_2587 = or(_T_2584, _T_2586)
node _T_2588 = asUInt(reset)
node _T_2589 = eq(_T_2588, UInt<1>(0h0))
when _T_2589 :
node _T_2590 = eq(_T_2587, UInt<1>(0h0))
when _T_2590 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_2587, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_92
node _T_2591 = orr(inflight)
node _T_2592 = eq(_T_2591, UInt<1>(0h0))
node _T_2593 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_2594 = or(_T_2592, _T_2593)
node _T_2595 = lt(watchdog, plusarg_reader.out)
node _T_2596 = or(_T_2594, _T_2595)
node _T_2597 = asUInt(reset)
node _T_2598 = eq(_T_2597, UInt<1>(0h0))
when _T_2598 :
node _T_2599 = eq(_T_2596, UInt<1>(0h0))
when _T_2599 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_2596, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_2600 = and(io.in.a.ready, io.in.a.valid)
node _T_2601 = and(io.in.d.ready, io.in.d.valid)
node _T_2602 = or(_T_2600, _T_2601)
when _T_2602 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0)
regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0)
regreset inflight_sizes_1 : UInt<1032>, clock, reset, UInt<1032>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<29>(0h0)
connect _c_first_WIRE.bits.source, UInt<8>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<8>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<129>
connect c_set, UInt<129>(0h0)
wire c_set_wo_ready : UInt<129>
connect c_set_wo_ready, UInt<129>(0h0)
wire c_opcodes_set : UInt<516>
connect c_opcodes_set, UInt<516>(0h0)
wire c_sizes_set : UInt<1032>
connect c_sizes_set, UInt<1032>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<29>(0h0)
connect _WIRE_10.bits.source, UInt<8>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_2603 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<29>(0h0)
connect _WIRE_12.bits.source, UInt<8>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_2604 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_2605 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_2606 = and(_T_2604, _T_2605)
node _T_2607 = and(_T_2603, _T_2606)
when _T_2607 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<29>(0h0)
connect _WIRE_14.bits.source, UInt<8>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_2608 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_2609 = and(_T_2608, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<29>(0h0)
connect _WIRE_16.bits.source, UInt<8>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_2610 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_2611 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_2612 = and(_T_2610, _T_2611)
node _T_2613 = and(_T_2609, _T_2612)
when _T_2613 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<29>(0h0)
connect _WIRE_18.bits.source, UInt<8>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_2614 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_2615 = bits(_T_2614, 0, 0)
node _T_2616 = eq(_T_2615, UInt<1>(0h0))
node _T_2617 = asUInt(reset)
node _T_2618 = eq(_T_2617, UInt<1>(0h0))
when _T_2618 :
node _T_2619 = eq(_T_2616, UInt<1>(0h0))
when _T_2619 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_2616, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<129>
connect d_clr_1, UInt<129>(0h0)
wire d_clr_wo_ready_1 : UInt<129>
connect d_clr_wo_ready_1, UInt<129>(0h0)
wire d_opcodes_clr_1 : UInt<516>
connect d_opcodes_clr_1, UInt<516>(0h0)
wire d_sizes_clr_1 : UInt<1032>
connect d_sizes_clr_1, UInt<1032>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2620 = and(io.in.d.valid, d_first_2)
node _T_2621 = and(_T_2620, UInt<1>(0h1))
node _T_2622 = and(_T_2621, d_release_ack_1)
when _T_2622 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_2623 = and(io.in.d.ready, io.in.d.valid)
node _T_2624 = and(_T_2623, d_first_2)
node _T_2625 = and(_T_2624, UInt<1>(0h1))
node _T_2626 = and(_T_2625, d_release_ack_1)
when _T_2626 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_2627 = and(io.in.d.valid, d_first_2)
node _T_2628 = and(_T_2627, UInt<1>(0h1))
node _T_2629 = and(_T_2628, d_release_ack_1)
when _T_2629 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_2630 = dshr(inflight_1, io.in.d.bits.source)
node _T_2631 = bits(_T_2630, 0, 0)
node _T_2632 = or(_T_2631, same_cycle_resp_1)
node _T_2633 = asUInt(reset)
node _T_2634 = eq(_T_2633, UInt<1>(0h0))
when _T_2634 :
node _T_2635 = eq(_T_2632, UInt<1>(0h0))
when _T_2635 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_2632, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<29>(0h0)
connect _WIRE_20.bits.source, UInt<8>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_2636 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_2637 = asUInt(reset)
node _T_2638 = eq(_T_2637, UInt<1>(0h0))
when _T_2638 :
node _T_2639 = eq(_T_2636, UInt<1>(0h0))
when _T_2639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_2636, UInt<1>(0h1), "") : assert_109
else :
node _T_2640 = eq(io.in.d.bits.size, c_size_lookup)
node _T_2641 = asUInt(reset)
node _T_2642 = eq(_T_2641, UInt<1>(0h0))
when _T_2642 :
node _T_2643 = eq(_T_2640, UInt<1>(0h0))
when _T_2643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_2640, UInt<1>(0h1), "") : assert_110
node _T_2644 = and(io.in.d.valid, d_first_2)
node _T_2645 = and(_T_2644, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<29>(0h0)
connect _WIRE_22.bits.source, UInt<8>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_2646 = and(_T_2645, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<29>(0h0)
connect _WIRE_24.bits.source, UInt<8>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_2647 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_2648 = and(_T_2646, _T_2647)
node _T_2649 = and(_T_2648, d_release_ack_1)
node _T_2650 = eq(c_probe_ack, UInt<1>(0h0))
node _T_2651 = and(_T_2649, _T_2650)
when _T_2651 :
node _T_2652 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<29>(0h0)
connect _WIRE_26.bits.source, UInt<8>(0h0)
connect _WIRE_26.bits.size, UInt<4>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_2653 = or(_T_2652, _WIRE_27.ready)
node _T_2654 = asUInt(reset)
node _T_2655 = eq(_T_2654, UInt<1>(0h0))
when _T_2655 :
node _T_2656 = eq(_T_2653, UInt<1>(0h0))
when _T_2656 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_2653, UInt<1>(0h1), "") : assert_111
node _T_2657 = orr(c_set_wo_ready)
when _T_2657 :
node _T_2658 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_2659 = asUInt(reset)
node _T_2660 = eq(_T_2659, UInt<1>(0h0))
when _T_2660 :
node _T_2661 = eq(_T_2658, UInt<1>(0h0))
when _T_2661 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_2658, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_93
node _T_2662 = orr(inflight_1)
node _T_2663 = eq(_T_2662, UInt<1>(0h0))
node _T_2664 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_2665 = or(_T_2663, _T_2664)
node _T_2666 = lt(watchdog_1, plusarg_reader_1.out)
node _T_2667 = or(_T_2665, _T_2666)
node _T_2668 = asUInt(reset)
node _T_2669 = eq(_T_2668, UInt<1>(0h0))
when _T_2669 :
node _T_2670 = eq(_T_2667, UInt<1>(0h0))
when _T_2670 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_2667, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<29>(0h0)
connect _WIRE_28.bits.source, UInt<8>(0h0)
connect _WIRE_28.bits.size, UInt<4>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_2671 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_2672 = and(io.in.d.ready, io.in.d.valid)
node _T_2673 = or(_T_2671, _T_2672)
when _T_2673 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_30( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [7:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [7:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [128:0] inflight; // @[Monitor.scala:614:27]
reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [1031:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire [255:0] _GEN_0 = {248'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [255:0] _GEN_3 = {248'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [128:0] inflight_1; // @[Monitor.scala:726:35]
reg [1031:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module Pipeline_5 :
input clock : Clock
input reset : Reset
output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<128>, fromDMA : UInt<1>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<128>, fromDMA : UInt<1>}}, busy : UInt<1>}
reg stages : { data : UInt<128>, fromDMA : UInt<1>}[1], clock
wire _valids_WIRE : UInt<1>[1]
connect _valids_WIRE[0], UInt<1>(0h0)
regreset valids : UInt<1>[1], clock, reset, _valids_WIRE
wire stalling : UInt<1>[1]
connect stalling[0], UInt<1>(0h0)
node _io_busy_T = or(io.in.valid, valids[0])
connect io.busy, _io_busy_T
node _io_in_ready_T = eq(stalling[0], UInt<1>(0h0))
connect io.in.ready, _io_in_ready_T
node _stalling_0_T = eq(io.out.ready, UInt<1>(0h0))
node _stalling_0_T_1 = and(valids[0], _stalling_0_T)
connect stalling[0], _stalling_0_T_1
connect io.out.valid, valids[0]
when io.out.ready :
connect valids[0], UInt<1>(0h0)
node _T = and(io.in.ready, io.in.valid)
when _T :
connect valids[0], UInt<1>(0h1)
node _T_1 = and(io.in.ready, io.in.valid)
when _T_1 :
connect stages[0], io.in.bits
connect io.out.bits, stages[0] | module Pipeline_5( // @[Pipeline.scala:6:7]
input clock, // @[Pipeline.scala:6:7]
input reset, // @[Pipeline.scala:6:7]
output io_in_ready, // @[Pipeline.scala:7:14]
input io_in_valid, // @[Pipeline.scala:7:14]
input [127:0] io_in_bits_data, // @[Pipeline.scala:7:14]
input io_in_bits_fromDMA, // @[Pipeline.scala:7:14]
input io_out_ready, // @[Pipeline.scala:7:14]
output io_out_valid, // @[Pipeline.scala:7:14]
output [127:0] io_out_bits_data, // @[Pipeline.scala:7:14]
output io_out_bits_fromDMA // @[Pipeline.scala:7:14]
);
wire io_in_valid_0 = io_in_valid; // @[Pipeline.scala:6:7]
wire [127:0] io_in_bits_data_0 = io_in_bits_data; // @[Pipeline.scala:6:7]
wire io_in_bits_fromDMA_0 = io_in_bits_fromDMA; // @[Pipeline.scala:6:7]
wire io_out_ready_0 = io_out_ready; // @[Pipeline.scala:6:7]
wire _valids_WIRE_0 = 1'h0; // @[Pipeline.scala:22:33]
wire _io_in_ready_T; // @[Pipeline.scala:27:20]
wire _io_busy_T; // @[Pipeline.scala:24:28]
wire io_in_ready_0; // @[Pipeline.scala:6:7]
wire [127:0] io_out_bits_data_0; // @[Pipeline.scala:6:7]
wire io_out_bits_fromDMA_0; // @[Pipeline.scala:6:7]
wire io_out_valid_0; // @[Pipeline.scala:6:7]
wire io_busy; // @[Pipeline.scala:6:7]
reg [127:0] stages_0_data; // @[Pipeline.scala:21:21]
assign io_out_bits_data_0 = stages_0_data; // @[Pipeline.scala:6:7, :21:21]
reg stages_0_fromDMA; // @[Pipeline.scala:21:21]
assign io_out_bits_fromDMA_0 = stages_0_fromDMA; // @[Pipeline.scala:6:7, :21:21]
reg valids_0; // @[Pipeline.scala:22:25]
assign io_out_valid_0 = valids_0; // @[Pipeline.scala:6:7, :22:25]
wire _stalling_0_T_1; // @[Pipeline.scala:28:34]
wire stalling_0; // @[Pipeline.scala:23:27]
assign _io_busy_T = io_in_valid_0 | valids_0; // @[Pipeline.scala:6:7, :22:25, :24:28]
assign io_busy = _io_busy_T; // @[Pipeline.scala:6:7, :24:28]
assign _io_in_ready_T = ~stalling_0; // @[Pipeline.scala:23:27, :27:20]
assign io_in_ready_0 = _io_in_ready_T; // @[Pipeline.scala:6:7, :27:20]
wire _stalling_0_T = ~io_out_ready_0; // @[Pipeline.scala:6:7, :28:37]
assign _stalling_0_T_1 = valids_0 & _stalling_0_T; // @[Pipeline.scala:22:25, :28:{34,37}]
assign stalling_0 = _stalling_0_T_1; // @[Pipeline.scala:23:27, :28:34]
wire _T_1 = io_in_ready_0 & io_in_valid_0; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[Pipeline.scala:6:7]
if (_T_1) begin // @[Decoupled.scala:51:35]
stages_0_data <= io_in_bits_data_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_fromDMA <= io_in_bits_fromDMA_0; // @[Pipeline.scala:6:7, :21:21]
end
if (reset) // @[Pipeline.scala:6:7]
valids_0 <= 1'h0; // @[Pipeline.scala:22:25]
else // @[Pipeline.scala:6:7]
valids_0 <= _T_1 | ~io_out_ready_0 & valids_0; // @[Decoupled.scala:51:35]
always @(posedge)
assign io_in_ready = io_in_ready_0; // @[Pipeline.scala:6:7]
assign io_out_valid = io_out_valid_0; // @[Pipeline.scala:6:7]
assign io_out_bits_data = io_out_bits_data_0; // @[Pipeline.scala:6:7]
assign io_out_bits_fromDMA = io_out_bits_fromDMA_0; // @[Pipeline.scala:6:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ReRoCCMsgArbiter_3 :
input clock : Clock
input reset : Reset
output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}[5], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}}
regreset lockIdx : UInt<3>, clock, reset, UInt<3>(0h0)
regreset locked : UInt<1>, clock, reset, UInt<1>(0h0)
node _choice_T = mux(io.in[3].valid, UInt<2>(0h3), UInt<3>(0h4))
node _choice_T_1 = mux(io.in[2].valid, UInt<2>(0h2), _choice_T)
node _choice_T_2 = mux(io.in[1].valid, UInt<1>(0h1), _choice_T_1)
node choice = mux(io.in[0].valid, UInt<1>(0h0), _choice_T_2)
node chosen = mux(locked, lockIdx, choice)
node _io_in_0_ready_T = eq(chosen, UInt<1>(0h0))
node _io_in_0_ready_T_1 = and(io.out.ready, _io_in_0_ready_T)
connect io.in[0].ready, _io_in_0_ready_T_1
node _io_in_1_ready_T = eq(chosen, UInt<1>(0h1))
node _io_in_1_ready_T_1 = and(io.out.ready, _io_in_1_ready_T)
connect io.in[1].ready, _io_in_1_ready_T_1
node _io_in_2_ready_T = eq(chosen, UInt<2>(0h2))
node _io_in_2_ready_T_1 = and(io.out.ready, _io_in_2_ready_T)
connect io.in[2].ready, _io_in_2_ready_T_1
node _io_in_3_ready_T = eq(chosen, UInt<2>(0h3))
node _io_in_3_ready_T_1 = and(io.out.ready, _io_in_3_ready_T)
connect io.in[3].ready, _io_in_3_ready_T_1
node _io_in_4_ready_T = eq(chosen, UInt<3>(0h4))
node _io_in_4_ready_T_1 = and(io.out.ready, _io_in_4_ready_T)
connect io.in[4].ready, _io_in_4_ready_T_1
connect io.out.valid, io.in[chosen].valid
connect io.out.bits, io.in[chosen].bits
node _T = and(io.out.ready, io.out.valid)
when _T :
node _T_1 = eq(locked, UInt<1>(0h0))
when _T_1 :
connect lockIdx, choice
connect locked, UInt<1>(0h1)
regreset beat : UInt<2>, clock, reset, UInt<2>(0h0)
regreset max_beat : UInt<2>, clock, reset, UInt<2>(0h0)
node first = eq(beat, UInt<1>(0h0))
wire last : UInt<1>
wire inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}
wire _inst_WIRE : UInt<32>
connect _inst_WIRE, io.out.bits.data
node _inst_T = bits(_inst_WIRE, 6, 0)
connect inst.opcode, _inst_T
node _inst_T_1 = bits(_inst_WIRE, 11, 7)
connect inst.rd, _inst_T_1
node _inst_T_2 = bits(_inst_WIRE, 12, 12)
connect inst.xs2, _inst_T_2
node _inst_T_3 = bits(_inst_WIRE, 13, 13)
connect inst.xs1, _inst_T_3
node _inst_T_4 = bits(_inst_WIRE, 14, 14)
connect inst.xd, _inst_T_4
node _inst_T_5 = bits(_inst_WIRE, 19, 15)
connect inst.rs1, _inst_T_5
node _inst_T_6 = bits(_inst_WIRE, 24, 20)
connect inst.rs2, _inst_T_6
node _inst_T_7 = bits(_inst_WIRE, 31, 25)
connect inst.funct, _inst_T_7
node _T_2 = and(io.out.ready, io.out.valid)
node _T_3 = and(_T_2, first)
when _T_3 :
connect max_beat, UInt<1>(0h0)
node _T_4 = eq(io.out.bits.opcode, UInt<3>(0h2))
when _T_4 :
connect max_beat, UInt<1>(0h1)
connect last, UInt<1>(0h1)
node _T_5 = eq(io.out.bits.opcode, UInt<3>(0h2))
when _T_5 :
node _last_T = eq(beat, max_beat)
node _last_T_1 = eq(first, UInt<1>(0h0))
node _last_T_2 = and(_last_T, _last_T_1)
connect last, _last_T_2
node _T_6 = and(io.out.ready, io.out.valid)
when _T_6 :
node _beat_T = add(beat, UInt<1>(0h1))
node _beat_T_1 = tail(_beat_T, 1)
connect beat, _beat_T_1
node _T_7 = and(io.out.ready, io.out.valid)
node _T_8 = and(_T_7, last)
when _T_8 :
connect max_beat, UInt<1>(0h0)
connect beat, UInt<1>(0h0)
when last :
connect locked, UInt<1>(0h0) | module ReRoCCMsgArbiter_3( // @[Arbiter.scala:7:7]
input clock, // @[Arbiter.scala:7:7]
input reset, // @[Arbiter.scala:7:7]
output io_in_0_ready, // @[Arbiters.scala:14:14]
input io_in_0_valid, // @[Arbiters.scala:14:14]
input [3:0] io_in_0_bits_client_id, // @[Arbiters.scala:14:14]
input io_in_0_bits_manager_id, // @[Arbiters.scala:14:14]
input [63:0] io_in_0_bits_data, // @[Arbiters.scala:14:14]
output io_in_1_ready, // @[Arbiters.scala:14:14]
input io_in_1_valid, // @[Arbiters.scala:14:14]
input [3:0] io_in_1_bits_client_id, // @[Arbiters.scala:14:14]
input io_in_1_bits_manager_id, // @[Arbiters.scala:14:14]
output io_in_2_ready, // @[Arbiters.scala:14:14]
input io_in_2_valid, // @[Arbiters.scala:14:14]
input [3:0] io_in_2_bits_client_id, // @[Arbiters.scala:14:14]
input io_in_2_bits_manager_id, // @[Arbiters.scala:14:14]
input [63:0] io_in_2_bits_data, // @[Arbiters.scala:14:14]
output io_in_3_ready, // @[Arbiters.scala:14:14]
input io_in_3_valid, // @[Arbiters.scala:14:14]
input [3:0] io_in_3_bits_client_id, // @[Arbiters.scala:14:14]
input io_in_3_bits_manager_id, // @[Arbiters.scala:14:14]
output io_in_4_ready, // @[Arbiters.scala:14:14]
input io_in_4_valid, // @[Arbiters.scala:14:14]
input [3:0] io_in_4_bits_client_id, // @[Arbiters.scala:14:14]
input io_in_4_bits_manager_id, // @[Arbiters.scala:14:14]
input io_out_ready, // @[Arbiters.scala:14:14]
output io_out_valid, // @[Arbiters.scala:14:14]
output [2:0] io_out_bits_opcode, // @[Arbiters.scala:14:14]
output [3:0] io_out_bits_client_id, // @[Arbiters.scala:14:14]
output io_out_bits_manager_id, // @[Arbiters.scala:14:14]
output [63:0] io_out_bits_data // @[Arbiters.scala:14:14]
);
wire io_in_0_valid_0 = io_in_0_valid; // @[Arbiter.scala:7:7]
wire [3:0] io_in_0_bits_client_id_0 = io_in_0_bits_client_id; // @[Arbiter.scala:7:7]
wire io_in_0_bits_manager_id_0 = io_in_0_bits_manager_id; // @[Arbiter.scala:7:7]
wire [63:0] io_in_0_bits_data_0 = io_in_0_bits_data; // @[Arbiter.scala:7:7]
wire io_in_1_valid_0 = io_in_1_valid; // @[Arbiter.scala:7:7]
wire [3:0] io_in_1_bits_client_id_0 = io_in_1_bits_client_id; // @[Arbiter.scala:7:7]
wire io_in_1_bits_manager_id_0 = io_in_1_bits_manager_id; // @[Arbiter.scala:7:7]
wire io_in_2_valid_0 = io_in_2_valid; // @[Arbiter.scala:7:7]
wire [3:0] io_in_2_bits_client_id_0 = io_in_2_bits_client_id; // @[Arbiter.scala:7:7]
wire io_in_2_bits_manager_id_0 = io_in_2_bits_manager_id; // @[Arbiter.scala:7:7]
wire [63:0] io_in_2_bits_data_0 = io_in_2_bits_data; // @[Arbiter.scala:7:7]
wire io_in_3_valid_0 = io_in_3_valid; // @[Arbiter.scala:7:7]
wire [3:0] io_in_3_bits_client_id_0 = io_in_3_bits_client_id; // @[Arbiter.scala:7:7]
wire io_in_3_bits_manager_id_0 = io_in_3_bits_manager_id; // @[Arbiter.scala:7:7]
wire io_in_4_valid_0 = io_in_4_valid; // @[Arbiter.scala:7:7]
wire [3:0] io_in_4_bits_client_id_0 = io_in_4_bits_client_id; // @[Arbiter.scala:7:7]
wire io_in_4_bits_manager_id_0 = io_in_4_bits_manager_id; // @[Arbiter.scala:7:7]
wire io_out_ready_0 = io_out_ready; // @[Arbiter.scala:7:7]
wire [7:0][2:0] _GEN = '{3'h0, 3'h0, 3'h0, 3'h4, 3'h3, 3'h2, 3'h1, 3'h0};
wire [2:0] io_in_4_bits_opcode = 3'h4; // @[Arbiter.scala:7:7]
wire [2:0] io_in_3_bits_opcode = 3'h3; // @[Arbiters.scala:40:46]
wire [2:0] io_in_2_bits_opcode = 3'h2; // @[Arbiters.scala:40:46]
wire [63:0] io_in_1_bits_data = 64'h0; // @[Arbiters.scala:14:14]
wire [63:0] io_in_3_bits_data = 64'h0; // @[Arbiters.scala:14:14]
wire [63:0] io_in_4_bits_data = 64'h0; // @[Arbiters.scala:14:14]
wire [2:0] io_in_1_bits_opcode = 3'h1; // @[Arbiters.scala:40:46]
wire [2:0] io_in_0_bits_opcode = 3'h0; // @[Arbiter.scala:7:7]
wire _io_in_0_ready_T_1; // @[Arbiters.scala:40:36]
wire _io_in_1_ready_T_1; // @[Arbiters.scala:40:36]
wire _io_in_2_ready_T_1; // @[Arbiters.scala:40:36]
wire _io_in_3_ready_T_1; // @[Arbiters.scala:40:36]
wire _io_in_4_ready_T_1; // @[Arbiters.scala:40:36]
wire io_in_0_ready_0; // @[Arbiter.scala:7:7]
wire io_in_1_ready_0; // @[Arbiter.scala:7:7]
wire io_in_2_ready_0; // @[Arbiter.scala:7:7]
wire io_in_3_ready_0; // @[Arbiter.scala:7:7]
wire io_in_4_ready_0; // @[Arbiter.scala:7:7]
wire [2:0] io_out_bits_opcode_0; // @[Arbiter.scala:7:7]
wire [3:0] io_out_bits_client_id_0; // @[Arbiter.scala:7:7]
wire io_out_bits_manager_id_0; // @[Arbiter.scala:7:7]
wire [63:0] io_out_bits_data_0; // @[Arbiter.scala:7:7]
wire io_out_valid_0; // @[Arbiter.scala:7:7]
reg [2:0] lockIdx; // @[Arbiters.scala:26:24]
reg locked; // @[Arbiters.scala:27:23]
wire [2:0] _choice_T = io_in_3_valid_0 ? 3'h3 : 3'h4; // @[Mux.scala:50:70]
wire [2:0] _choice_T_1 = io_in_2_valid_0 ? 3'h2 : _choice_T; // @[Mux.scala:50:70]
wire [2:0] _choice_T_2 = io_in_1_valid_0 ? 3'h1 : _choice_T_1; // @[Mux.scala:50:70]
wire [2:0] choice = io_in_0_valid_0 ? 3'h0 : _choice_T_2; // @[Mux.scala:50:70]
wire [2:0] chosen = locked ? lockIdx : choice; // @[Mux.scala:50:70]
wire _io_in_0_ready_T = chosen == 3'h0; // @[Arbiters.scala:37:19, :40:46]
assign _io_in_0_ready_T_1 = io_out_ready_0 & _io_in_0_ready_T; // @[Arbiters.scala:40:{36,46}]
assign io_in_0_ready_0 = _io_in_0_ready_T_1; // @[Arbiters.scala:40:36]
wire _io_in_1_ready_T = chosen == 3'h1; // @[Arbiters.scala:37:19, :40:46]
assign _io_in_1_ready_T_1 = io_out_ready_0 & _io_in_1_ready_T; // @[Arbiters.scala:40:{36,46}]
assign io_in_1_ready_0 = _io_in_1_ready_T_1; // @[Arbiters.scala:40:36]
wire _io_in_2_ready_T = chosen == 3'h2; // @[Arbiters.scala:37:19, :40:46]
assign _io_in_2_ready_T_1 = io_out_ready_0 & _io_in_2_ready_T; // @[Arbiters.scala:40:{36,46}]
assign io_in_2_ready_0 = _io_in_2_ready_T_1; // @[Arbiters.scala:40:36]
wire _io_in_3_ready_T = chosen == 3'h3; // @[Arbiters.scala:37:19, :40:46]
assign _io_in_3_ready_T_1 = io_out_ready_0 & _io_in_3_ready_T; // @[Arbiters.scala:40:{36,46}]
assign io_in_3_ready_0 = _io_in_3_ready_T_1; // @[Arbiters.scala:40:36]
wire _io_in_4_ready_T = chosen == 3'h4; // @[Arbiters.scala:37:19, :40:46]
assign _io_in_4_ready_T_1 = io_out_ready_0 & _io_in_4_ready_T; // @[Arbiters.scala:40:{36,46}]
assign io_in_4_ready_0 = _io_in_4_ready_T_1; // @[Arbiters.scala:40:36]
wire [7:0] _GEN_0 = {{io_in_0_valid_0}, {io_in_0_valid_0}, {io_in_0_valid_0}, {io_in_4_valid_0}, {io_in_3_valid_0}, {io_in_2_valid_0}, {io_in_1_valid_0}, {io_in_0_valid_0}}; // @[Arbiters.scala:43:16]
assign io_out_valid_0 = _GEN_0[chosen]; // @[Arbiters.scala:37:19, :43:16]
assign io_out_bits_opcode_0 = _GEN[chosen]; // @[Arbiters.scala:37:19, :43:16]
wire [7:0][3:0] _GEN_1 = {{io_in_0_bits_client_id_0}, {io_in_0_bits_client_id_0}, {io_in_0_bits_client_id_0}, {io_in_4_bits_client_id_0}, {io_in_3_bits_client_id_0}, {io_in_2_bits_client_id_0}, {io_in_1_bits_client_id_0}, {io_in_0_bits_client_id_0}}; // @[Arbiters.scala:43:16]
assign io_out_bits_client_id_0 = _GEN_1[chosen]; // @[Arbiters.scala:37:19, :43:16]
wire [7:0] _GEN_2 = {{io_in_0_bits_manager_id_0}, {io_in_0_bits_manager_id_0}, {io_in_0_bits_manager_id_0}, {io_in_4_bits_manager_id_0}, {io_in_3_bits_manager_id_0}, {io_in_2_bits_manager_id_0}, {io_in_1_bits_manager_id_0}, {io_in_0_bits_manager_id_0}}; // @[Arbiters.scala:43:16]
assign io_out_bits_manager_id_0 = _GEN_2[chosen]; // @[Arbiters.scala:37:19, :43:16]
wire [7:0][63:0] _GEN_3 = {{io_in_0_bits_data_0}, {io_in_0_bits_data_0}, {io_in_0_bits_data_0}, {64'h0}, {64'h0}, {io_in_2_bits_data_0}, {64'h0}, {io_in_0_bits_data_0}}; // @[Arbiters.scala:14:14, :43:16]
assign io_out_bits_data_0 = _GEN_3[chosen]; // @[Arbiters.scala:37:19, :43:16]
reg [1:0] beat; // @[Protocol.scala:54:23]
reg [1:0] max_beat; // @[Protocol.scala:55:27]
wire first = beat == 2'h0; // @[Protocol.scala:54:23, :56:22]
wire last; // @[Protocol.scala:57:20]
wire [6:0] _inst_T_7; // @[Protocol.scala:58:36]
wire [4:0] _inst_T_6; // @[Protocol.scala:58:36]
wire [4:0] _inst_T_5; // @[Protocol.scala:58:36]
wire _inst_T_4; // @[Protocol.scala:58:36]
wire _inst_T_3; // @[Protocol.scala:58:36]
wire _inst_T_2; // @[Protocol.scala:58:36]
wire [4:0] _inst_T_1; // @[Protocol.scala:58:36]
wire [6:0] _inst_T; // @[Protocol.scala:58:36]
wire [6:0] inst_funct; // @[Protocol.scala:58:36]
wire [4:0] inst_rs2; // @[Protocol.scala:58:36]
wire [4:0] inst_rs1; // @[Protocol.scala:58:36]
wire inst_xd; // @[Protocol.scala:58:36]
wire inst_xs1; // @[Protocol.scala:58:36]
wire inst_xs2; // @[Protocol.scala:58:36]
wire [4:0] inst_rd; // @[Protocol.scala:58:36]
wire [6:0] inst_opcode; // @[Protocol.scala:58:36]
wire [31:0] _inst_WIRE = io_out_bits_data_0[31:0]; // @[Protocol.scala:58:36]
assign _inst_T = _inst_WIRE[6:0]; // @[Protocol.scala:58:36]
assign inst_opcode = _inst_T; // @[Protocol.scala:58:36]
assign _inst_T_1 = _inst_WIRE[11:7]; // @[Protocol.scala:58:36]
assign inst_rd = _inst_T_1; // @[Protocol.scala:58:36]
assign _inst_T_2 = _inst_WIRE[12]; // @[Protocol.scala:58:36]
assign inst_xs2 = _inst_T_2; // @[Protocol.scala:58:36]
assign _inst_T_3 = _inst_WIRE[13]; // @[Protocol.scala:58:36]
assign inst_xs1 = _inst_T_3; // @[Protocol.scala:58:36]
assign _inst_T_4 = _inst_WIRE[14]; // @[Protocol.scala:58:36]
assign inst_xd = _inst_T_4; // @[Protocol.scala:58:36]
assign _inst_T_5 = _inst_WIRE[19:15]; // @[Protocol.scala:58:36]
assign inst_rs1 = _inst_T_5; // @[Protocol.scala:58:36]
assign _inst_T_6 = _inst_WIRE[24:20]; // @[Protocol.scala:58:36]
assign inst_rs2 = _inst_T_6; // @[Protocol.scala:58:36]
assign _inst_T_7 = _inst_WIRE[31:25]; // @[Protocol.scala:58:36]
assign inst_funct = _inst_T_7; // @[Protocol.scala:58:36]
wire _last_T = beat == max_beat; // @[Protocol.scala:54:23, :55:27, :83:22]
wire _last_T_1 = ~first; // @[Protocol.scala:56:22, :83:38]
wire _last_T_2 = _last_T & _last_T_1; // @[Protocol.scala:83:{22,35,38}]
assign last = io_out_bits_opcode_0 != 3'h2 | _last_T_2; // @[Arbiters.scala:40:46]
wire [2:0] _beat_T = {1'h0, beat} + 3'h1; // @[Arbiters.scala:40:46]
wire [1:0] _beat_T_1 = _beat_T[1:0]; // @[Protocol.scala:87:34]
wire _T_7 = io_out_ready_0 & io_out_valid_0; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[Arbiter.scala:7:7]
if (reset) begin // @[Arbiter.scala:7:7]
lockIdx <= 3'h0; // @[Arbiters.scala:26:24]
locked <= 1'h0; // @[Arbiters.scala:27:23]
beat <= 2'h0; // @[Protocol.scala:54:23]
max_beat <= 2'h0; // @[Protocol.scala:55:27]
end
else begin // @[Arbiter.scala:7:7]
if (_T_7 & ~locked) // @[Decoupled.scala:51:35]
lockIdx <= choice; // @[Mux.scala:50:70]
if (_T_7) // @[Decoupled.scala:51:35]
locked <= ~last; // @[Arbiters.scala:27:23]
if (_T_7 & last) begin // @[Decoupled.scala:51:35]
beat <= 2'h0; // @[Protocol.scala:54:23]
max_beat <= 2'h0; // @[Protocol.scala:55:27]
end
else begin // @[Protocol.scala:88:18]
if (_T_7) // @[Decoupled.scala:51:35]
beat <= _beat_T_1; // @[Protocol.scala:54:23, :87:34]
if (_T_7 & first) // @[Decoupled.scala:51:35]
max_beat <= {1'h0, io_out_bits_opcode_0 == 3'h2}; // @[Arbiters.scala:40:46]
end
end
always @(posedge)
assign io_in_0_ready = io_in_0_ready_0; // @[Arbiter.scala:7:7]
assign io_in_1_ready = io_in_1_ready_0; // @[Arbiter.scala:7:7]
assign io_in_2_ready = io_in_2_ready_0; // @[Arbiter.scala:7:7]
assign io_in_3_ready = io_in_3_ready_0; // @[Arbiter.scala:7:7]
assign io_in_4_ready = io_in_4_ready_0; // @[Arbiter.scala:7:7]
assign io_out_valid = io_out_valid_0; // @[Arbiter.scala:7:7]
assign io_out_bits_opcode = io_out_bits_opcode_0; // @[Arbiter.scala:7:7]
assign io_out_bits_client_id = io_out_bits_client_id_0; // @[Arbiter.scala:7:7]
assign io_out_bits_manager_id = io_out_bits_manager_id_0; // @[Arbiter.scala:7:7]
assign io_out_bits_data = io_out_bits_data_0; // @[Arbiter.scala:7:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_4 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h11))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE : UInt<1>[10]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
connect _source_ok_WIRE[7], _source_ok_T_27
connect _source_ok_WIRE[8], _source_ok_T_28
connect _source_ok_WIRE[9], _source_ok_T_29
node _source_ok_T_30 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[2])
node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[3])
node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[4])
node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[5])
node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[6])
node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[7])
node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[8])
node source_ok = or(_source_ok_T_37, _source_ok_WIRE[9])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_81 = eq(_T_80, UInt<1>(0h0))
node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_83 = cvt(_T_82)
node _T_84 = and(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = asSInt(_T_84)
node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = or(_T_81, _T_86)
node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_89 = eq(_T_88, UInt<1>(0h0))
node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<1>(0h0)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_89, _T_94)
node _T_96 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_99 = cvt(_T_98)
node _T_100 = and(_T_99, asSInt(UInt<1>(0h0)))
node _T_101 = asSInt(_T_100)
node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = or(_T_97, _T_102)
node _T_104 = and(_T_11, _T_24)
node _T_105 = and(_T_104, _T_37)
node _T_106 = and(_T_105, _T_50)
node _T_107 = and(_T_106, _T_63)
node _T_108 = and(_T_107, _T_71)
node _T_109 = and(_T_108, _T_79)
node _T_110 = and(_T_109, _T_87)
node _T_111 = and(_T_110, _T_95)
node _T_112 = and(_T_111, _T_103)
node _T_113 = asUInt(reset)
node _T_114 = eq(_T_113, UInt<1>(0h0))
when _T_114 :
node _T_115 = eq(_T_112, UInt<1>(0h0))
when _T_115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_112, UInt<1>(0h1), "") : assert_1
node _T_116 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_116 :
node _T_117 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_118 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_119 = and(_T_117, _T_118)
node _T_120 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_121 = shr(io.in.a.bits.source, 2)
node _T_122 = eq(_T_121, UInt<1>(0h0))
node _T_123 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_124 = and(_T_122, _T_123)
node _T_125 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_126 = and(_T_124, _T_125)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_127 = shr(io.in.a.bits.source, 2)
node _T_128 = eq(_T_127, UInt<1>(0h1))
node _T_129 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_130 = and(_T_128, _T_129)
node _T_131 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_132 = and(_T_130, _T_131)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_133 = shr(io.in.a.bits.source, 2)
node _T_134 = eq(_T_133, UInt<2>(0h2))
node _T_135 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_136 = and(_T_134, _T_135)
node _T_137 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_138 = and(_T_136, _T_137)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_139 = shr(io.in.a.bits.source, 2)
node _T_140 = eq(_T_139, UInt<2>(0h3))
node _T_141 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_142 = and(_T_140, _T_141)
node _T_143 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_144 = and(_T_142, _T_143)
node _T_145 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_146 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_147 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_148 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_149 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_150 = or(_T_120, _T_126)
node _T_151 = or(_T_150, _T_132)
node _T_152 = or(_T_151, _T_138)
node _T_153 = or(_T_152, _T_144)
node _T_154 = or(_T_153, _T_145)
node _T_155 = or(_T_154, _T_146)
node _T_156 = or(_T_155, _T_147)
node _T_157 = or(_T_156, _T_148)
node _T_158 = or(_T_157, _T_149)
node _T_159 = and(_T_119, _T_158)
node _T_160 = or(UInt<1>(0h0), _T_159)
node _T_161 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_162 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_163 = cvt(_T_162)
node _T_164 = and(_T_163, asSInt(UInt<13>(0h1000)))
node _T_165 = asSInt(_T_164)
node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0)))
node _T_167 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<11>(0h400)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = xor(io.in.a.bits.address, UInt<14>(0h2400))
node _T_173 = cvt(_T_172)
node _T_174 = and(_T_173, asSInt(UInt<9>(0h100)))
node _T_175 = asSInt(_T_174)
node _T_176 = eq(_T_175, asSInt(UInt<1>(0h0)))
node _T_177 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_178 = cvt(_T_177)
node _T_179 = and(_T_178, asSInt(UInt<13>(0h1000)))
node _T_180 = asSInt(_T_179)
node _T_181 = eq(_T_180, asSInt(UInt<1>(0h0)))
node _T_182 = or(_T_166, _T_171)
node _T_183 = or(_T_182, _T_176)
node _T_184 = or(_T_183, _T_181)
node _T_185 = and(_T_161, _T_184)
node _T_186 = or(UInt<1>(0h0), _T_185)
node _T_187 = and(_T_160, _T_186)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_187, UInt<1>(0h1), "") : assert_2
node _T_191 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_192 = shr(io.in.a.bits.source, 2)
node _T_193 = eq(_T_192, UInt<1>(0h0))
node _T_194 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_195 = and(_T_193, _T_194)
node _T_196 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_197 = and(_T_195, _T_196)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_198 = shr(io.in.a.bits.source, 2)
node _T_199 = eq(_T_198, UInt<1>(0h1))
node _T_200 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_201 = and(_T_199, _T_200)
node _T_202 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_203 = and(_T_201, _T_202)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_204 = shr(io.in.a.bits.source, 2)
node _T_205 = eq(_T_204, UInt<2>(0h2))
node _T_206 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_207 = and(_T_205, _T_206)
node _T_208 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_209 = and(_T_207, _T_208)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_210 = shr(io.in.a.bits.source, 2)
node _T_211 = eq(_T_210, UInt<2>(0h3))
node _T_212 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_213 = and(_T_211, _T_212)
node _T_214 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_215 = and(_T_213, _T_214)
node _T_216 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_217 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_218 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_219 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_220 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE : UInt<1>[10]
connect _WIRE[0], _T_191
connect _WIRE[1], _T_197
connect _WIRE[2], _T_203
connect _WIRE[3], _T_209
connect _WIRE[4], _T_215
connect _WIRE[5], _T_216
connect _WIRE[6], _T_217
connect _WIRE[7], _T_218
connect _WIRE[8], _T_219
connect _WIRE[9], _T_220
node _T_221 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_222 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_223 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_224 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_225 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_226 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_227 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_228 = mux(_WIRE[6], _T_221, UInt<1>(0h0))
node _T_229 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_230 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_231 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_232 = or(_T_222, _T_223)
node _T_233 = or(_T_232, _T_224)
node _T_234 = or(_T_233, _T_225)
node _T_235 = or(_T_234, _T_226)
node _T_236 = or(_T_235, _T_227)
node _T_237 = or(_T_236, _T_228)
node _T_238 = or(_T_237, _T_229)
node _T_239 = or(_T_238, _T_230)
node _T_240 = or(_T_239, _T_231)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_240
node _T_241 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_242 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_243 = and(_T_241, _T_242)
node _T_244 = or(UInt<1>(0h0), _T_243)
node _T_245 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_246 = cvt(_T_245)
node _T_247 = and(_T_246, asSInt(UInt<13>(0h1000)))
node _T_248 = asSInt(_T_247)
node _T_249 = eq(_T_248, asSInt(UInt<1>(0h0)))
node _T_250 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_251 = cvt(_T_250)
node _T_252 = and(_T_251, asSInt(UInt<11>(0h400)))
node _T_253 = asSInt(_T_252)
node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0)))
node _T_255 = xor(io.in.a.bits.address, UInt<14>(0h2400))
node _T_256 = cvt(_T_255)
node _T_257 = and(_T_256, asSInt(UInt<9>(0h100)))
node _T_258 = asSInt(_T_257)
node _T_259 = eq(_T_258, asSInt(UInt<1>(0h0)))
node _T_260 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_261 = cvt(_T_260)
node _T_262 = and(_T_261, asSInt(UInt<13>(0h1000)))
node _T_263 = asSInt(_T_262)
node _T_264 = eq(_T_263, asSInt(UInt<1>(0h0)))
node _T_265 = or(_T_249, _T_254)
node _T_266 = or(_T_265, _T_259)
node _T_267 = or(_T_266, _T_264)
node _T_268 = and(_T_244, _T_267)
node _T_269 = or(UInt<1>(0h0), _T_268)
node _T_270 = and(_WIRE_1, _T_269)
node _T_271 = asUInt(reset)
node _T_272 = eq(_T_271, UInt<1>(0h0))
when _T_272 :
node _T_273 = eq(_T_270, UInt<1>(0h0))
when _T_273 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_270, UInt<1>(0h1), "") : assert_3
node _T_274 = asUInt(reset)
node _T_275 = eq(_T_274, UInt<1>(0h0))
when _T_275 :
node _T_276 = eq(source_ok, UInt<1>(0h0))
when _T_276 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_277 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_278 = asUInt(reset)
node _T_279 = eq(_T_278, UInt<1>(0h0))
when _T_279 :
node _T_280 = eq(_T_277, UInt<1>(0h0))
when _T_280 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_277, UInt<1>(0h1), "") : assert_5
node _T_281 = asUInt(reset)
node _T_282 = eq(_T_281, UInt<1>(0h0))
when _T_282 :
node _T_283 = eq(is_aligned, UInt<1>(0h0))
when _T_283 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_284 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(_T_284, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_284, UInt<1>(0h1), "") : assert_7
node _T_288 = not(io.in.a.bits.mask)
node _T_289 = eq(_T_288, UInt<1>(0h0))
node _T_290 = asUInt(reset)
node _T_291 = eq(_T_290, UInt<1>(0h0))
when _T_291 :
node _T_292 = eq(_T_289, UInt<1>(0h0))
when _T_292 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_289, UInt<1>(0h1), "") : assert_8
node _T_293 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_294 = asUInt(reset)
node _T_295 = eq(_T_294, UInt<1>(0h0))
when _T_295 :
node _T_296 = eq(_T_293, UInt<1>(0h0))
when _T_296 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_293, UInt<1>(0h1), "") : assert_9
node _T_297 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_297 :
node _T_298 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_299 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_300 = and(_T_298, _T_299)
node _T_301 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_302 = shr(io.in.a.bits.source, 2)
node _T_303 = eq(_T_302, UInt<1>(0h0))
node _T_304 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_305 = and(_T_303, _T_304)
node _T_306 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_307 = and(_T_305, _T_306)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_308 = shr(io.in.a.bits.source, 2)
node _T_309 = eq(_T_308, UInt<1>(0h1))
node _T_310 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_311 = and(_T_309, _T_310)
node _T_312 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_313 = and(_T_311, _T_312)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_314 = shr(io.in.a.bits.source, 2)
node _T_315 = eq(_T_314, UInt<2>(0h2))
node _T_316 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_317 = and(_T_315, _T_316)
node _T_318 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_319 = and(_T_317, _T_318)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_320 = shr(io.in.a.bits.source, 2)
node _T_321 = eq(_T_320, UInt<2>(0h3))
node _T_322 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_323 = and(_T_321, _T_322)
node _T_324 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_325 = and(_T_323, _T_324)
node _T_326 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_330 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_331 = or(_T_301, _T_307)
node _T_332 = or(_T_331, _T_313)
node _T_333 = or(_T_332, _T_319)
node _T_334 = or(_T_333, _T_325)
node _T_335 = or(_T_334, _T_326)
node _T_336 = or(_T_335, _T_327)
node _T_337 = or(_T_336, _T_328)
node _T_338 = or(_T_337, _T_329)
node _T_339 = or(_T_338, _T_330)
node _T_340 = and(_T_300, _T_339)
node _T_341 = or(UInt<1>(0h0), _T_340)
node _T_342 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_343 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_344 = cvt(_T_343)
node _T_345 = and(_T_344, asSInt(UInt<13>(0h1000)))
node _T_346 = asSInt(_T_345)
node _T_347 = eq(_T_346, asSInt(UInt<1>(0h0)))
node _T_348 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_349 = cvt(_T_348)
node _T_350 = and(_T_349, asSInt(UInt<11>(0h400)))
node _T_351 = asSInt(_T_350)
node _T_352 = eq(_T_351, asSInt(UInt<1>(0h0)))
node _T_353 = xor(io.in.a.bits.address, UInt<14>(0h2400))
node _T_354 = cvt(_T_353)
node _T_355 = and(_T_354, asSInt(UInt<9>(0h100)))
node _T_356 = asSInt(_T_355)
node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0)))
node _T_358 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_359 = cvt(_T_358)
node _T_360 = and(_T_359, asSInt(UInt<13>(0h1000)))
node _T_361 = asSInt(_T_360)
node _T_362 = eq(_T_361, asSInt(UInt<1>(0h0)))
node _T_363 = or(_T_347, _T_352)
node _T_364 = or(_T_363, _T_357)
node _T_365 = or(_T_364, _T_362)
node _T_366 = and(_T_342, _T_365)
node _T_367 = or(UInt<1>(0h0), _T_366)
node _T_368 = and(_T_341, _T_367)
node _T_369 = asUInt(reset)
node _T_370 = eq(_T_369, UInt<1>(0h0))
when _T_370 :
node _T_371 = eq(_T_368, UInt<1>(0h0))
when _T_371 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_368, UInt<1>(0h1), "") : assert_10
node _T_372 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_373 = shr(io.in.a.bits.source, 2)
node _T_374 = eq(_T_373, UInt<1>(0h0))
node _T_375 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_376 = and(_T_374, _T_375)
node _T_377 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_378 = and(_T_376, _T_377)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_379 = shr(io.in.a.bits.source, 2)
node _T_380 = eq(_T_379, UInt<1>(0h1))
node _T_381 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_382 = and(_T_380, _T_381)
node _T_383 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_384 = and(_T_382, _T_383)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_385 = shr(io.in.a.bits.source, 2)
node _T_386 = eq(_T_385, UInt<2>(0h2))
node _T_387 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_388 = and(_T_386, _T_387)
node _T_389 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_390 = and(_T_388, _T_389)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_391 = shr(io.in.a.bits.source, 2)
node _T_392 = eq(_T_391, UInt<2>(0h3))
node _T_393 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_394 = and(_T_392, _T_393)
node _T_395 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_396 = and(_T_394, _T_395)
node _T_397 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_398 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_399 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_400 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_401 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE_2 : UInt<1>[10]
connect _WIRE_2[0], _T_372
connect _WIRE_2[1], _T_378
connect _WIRE_2[2], _T_384
connect _WIRE_2[3], _T_390
connect _WIRE_2[4], _T_396
connect _WIRE_2[5], _T_397
connect _WIRE_2[6], _T_398
connect _WIRE_2[7], _T_399
connect _WIRE_2[8], _T_400
connect _WIRE_2[9], _T_401
node _T_402 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_403 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_404 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_405 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_406 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_407 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_408 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_409 = mux(_WIRE_2[6], _T_402, UInt<1>(0h0))
node _T_410 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_411 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_412 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_413 = or(_T_403, _T_404)
node _T_414 = or(_T_413, _T_405)
node _T_415 = or(_T_414, _T_406)
node _T_416 = or(_T_415, _T_407)
node _T_417 = or(_T_416, _T_408)
node _T_418 = or(_T_417, _T_409)
node _T_419 = or(_T_418, _T_410)
node _T_420 = or(_T_419, _T_411)
node _T_421 = or(_T_420, _T_412)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_421
node _T_422 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_423 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_424 = and(_T_422, _T_423)
node _T_425 = or(UInt<1>(0h0), _T_424)
node _T_426 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_427 = cvt(_T_426)
node _T_428 = and(_T_427, asSInt(UInt<13>(0h1000)))
node _T_429 = asSInt(_T_428)
node _T_430 = eq(_T_429, asSInt(UInt<1>(0h0)))
node _T_431 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_432 = cvt(_T_431)
node _T_433 = and(_T_432, asSInt(UInt<11>(0h400)))
node _T_434 = asSInt(_T_433)
node _T_435 = eq(_T_434, asSInt(UInt<1>(0h0)))
node _T_436 = xor(io.in.a.bits.address, UInt<14>(0h2400))
node _T_437 = cvt(_T_436)
node _T_438 = and(_T_437, asSInt(UInt<9>(0h100)))
node _T_439 = asSInt(_T_438)
node _T_440 = eq(_T_439, asSInt(UInt<1>(0h0)))
node _T_441 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_442 = cvt(_T_441)
node _T_443 = and(_T_442, asSInt(UInt<13>(0h1000)))
node _T_444 = asSInt(_T_443)
node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0)))
node _T_446 = or(_T_430, _T_435)
node _T_447 = or(_T_446, _T_440)
node _T_448 = or(_T_447, _T_445)
node _T_449 = and(_T_425, _T_448)
node _T_450 = or(UInt<1>(0h0), _T_449)
node _T_451 = and(_WIRE_3, _T_450)
node _T_452 = asUInt(reset)
node _T_453 = eq(_T_452, UInt<1>(0h0))
when _T_453 :
node _T_454 = eq(_T_451, UInt<1>(0h0))
when _T_454 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_451, UInt<1>(0h1), "") : assert_11
node _T_455 = asUInt(reset)
node _T_456 = eq(_T_455, UInt<1>(0h0))
when _T_456 :
node _T_457 = eq(source_ok, UInt<1>(0h0))
when _T_457 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_458 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_459 = asUInt(reset)
node _T_460 = eq(_T_459, UInt<1>(0h0))
when _T_460 :
node _T_461 = eq(_T_458, UInt<1>(0h0))
when _T_461 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_458, UInt<1>(0h1), "") : assert_13
node _T_462 = asUInt(reset)
node _T_463 = eq(_T_462, UInt<1>(0h0))
when _T_463 :
node _T_464 = eq(is_aligned, UInt<1>(0h0))
when _T_464 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_465 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_466 = asUInt(reset)
node _T_467 = eq(_T_466, UInt<1>(0h0))
when _T_467 :
node _T_468 = eq(_T_465, UInt<1>(0h0))
when _T_468 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_465, UInt<1>(0h1), "") : assert_15
node _T_469 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_469, UInt<1>(0h1), "") : assert_16
node _T_473 = not(io.in.a.bits.mask)
node _T_474 = eq(_T_473, UInt<1>(0h0))
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_474, UInt<1>(0h1), "") : assert_17
node _T_478 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_T_478, UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_478, UInt<1>(0h1), "") : assert_18
node _T_482 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_482 :
node _T_483 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_484 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_485 = and(_T_483, _T_484)
node _T_486 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_487 = shr(io.in.a.bits.source, 2)
node _T_488 = eq(_T_487, UInt<1>(0h0))
node _T_489 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_490 = and(_T_488, _T_489)
node _T_491 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_492 = and(_T_490, _T_491)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_493 = shr(io.in.a.bits.source, 2)
node _T_494 = eq(_T_493, UInt<1>(0h1))
node _T_495 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_496 = and(_T_494, _T_495)
node _T_497 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_498 = and(_T_496, _T_497)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_499 = shr(io.in.a.bits.source, 2)
node _T_500 = eq(_T_499, UInt<2>(0h2))
node _T_501 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_502 = and(_T_500, _T_501)
node _T_503 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_504 = and(_T_502, _T_503)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_505 = shr(io.in.a.bits.source, 2)
node _T_506 = eq(_T_505, UInt<2>(0h3))
node _T_507 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_508 = and(_T_506, _T_507)
node _T_509 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_510 = and(_T_508, _T_509)
node _T_511 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_512 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_513 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_514 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_515 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_516 = or(_T_486, _T_492)
node _T_517 = or(_T_516, _T_498)
node _T_518 = or(_T_517, _T_504)
node _T_519 = or(_T_518, _T_510)
node _T_520 = or(_T_519, _T_511)
node _T_521 = or(_T_520, _T_512)
node _T_522 = or(_T_521, _T_513)
node _T_523 = or(_T_522, _T_514)
node _T_524 = or(_T_523, _T_515)
node _T_525 = and(_T_485, _T_524)
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_526, UInt<1>(0h1), "") : assert_19
node _T_530 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_531 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_532 = and(_T_530, _T_531)
node _T_533 = or(UInt<1>(0h0), _T_532)
node _T_534 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_535 = cvt(_T_534)
node _T_536 = and(_T_535, asSInt(UInt<13>(0h1000)))
node _T_537 = asSInt(_T_536)
node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0)))
node _T_539 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_540 = cvt(_T_539)
node _T_541 = and(_T_540, asSInt(UInt<11>(0h400)))
node _T_542 = asSInt(_T_541)
node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0)))
node _T_544 = xor(io.in.a.bits.address, UInt<14>(0h2400))
node _T_545 = cvt(_T_544)
node _T_546 = and(_T_545, asSInt(UInt<9>(0h100)))
node _T_547 = asSInt(_T_546)
node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0)))
node _T_549 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_550 = cvt(_T_549)
node _T_551 = and(_T_550, asSInt(UInt<13>(0h1000)))
node _T_552 = asSInt(_T_551)
node _T_553 = eq(_T_552, asSInt(UInt<1>(0h0)))
node _T_554 = or(_T_538, _T_543)
node _T_555 = or(_T_554, _T_548)
node _T_556 = or(_T_555, _T_553)
node _T_557 = and(_T_533, _T_556)
node _T_558 = or(UInt<1>(0h0), _T_557)
node _T_559 = asUInt(reset)
node _T_560 = eq(_T_559, UInt<1>(0h0))
when _T_560 :
node _T_561 = eq(_T_558, UInt<1>(0h0))
when _T_561 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_558, UInt<1>(0h1), "") : assert_20
node _T_562 = asUInt(reset)
node _T_563 = eq(_T_562, UInt<1>(0h0))
when _T_563 :
node _T_564 = eq(source_ok, UInt<1>(0h0))
when _T_564 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_565 = asUInt(reset)
node _T_566 = eq(_T_565, UInt<1>(0h0))
when _T_566 :
node _T_567 = eq(is_aligned, UInt<1>(0h0))
when _T_567 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_568 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_568, UInt<1>(0h1), "") : assert_23
node _T_572 = eq(io.in.a.bits.mask, mask)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_572, UInt<1>(0h1), "") : assert_24
node _T_576 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_576, UInt<1>(0h1), "") : assert_25
node _T_580 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_580 :
node _T_581 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_582 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_583 = and(_T_581, _T_582)
node _T_584 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_585 = shr(io.in.a.bits.source, 2)
node _T_586 = eq(_T_585, UInt<1>(0h0))
node _T_587 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_588 = and(_T_586, _T_587)
node _T_589 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_590 = and(_T_588, _T_589)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_591 = shr(io.in.a.bits.source, 2)
node _T_592 = eq(_T_591, UInt<1>(0h1))
node _T_593 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_594 = and(_T_592, _T_593)
node _T_595 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_596 = and(_T_594, _T_595)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_597 = shr(io.in.a.bits.source, 2)
node _T_598 = eq(_T_597, UInt<2>(0h2))
node _T_599 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_600 = and(_T_598, _T_599)
node _T_601 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_602 = and(_T_600, _T_601)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_603 = shr(io.in.a.bits.source, 2)
node _T_604 = eq(_T_603, UInt<2>(0h3))
node _T_605 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_606 = and(_T_604, _T_605)
node _T_607 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_608 = and(_T_606, _T_607)
node _T_609 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_610 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_611 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_612 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_613 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_614 = or(_T_584, _T_590)
node _T_615 = or(_T_614, _T_596)
node _T_616 = or(_T_615, _T_602)
node _T_617 = or(_T_616, _T_608)
node _T_618 = or(_T_617, _T_609)
node _T_619 = or(_T_618, _T_610)
node _T_620 = or(_T_619, _T_611)
node _T_621 = or(_T_620, _T_612)
node _T_622 = or(_T_621, _T_613)
node _T_623 = and(_T_583, _T_622)
node _T_624 = or(UInt<1>(0h0), _T_623)
node _T_625 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_626 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_627 = and(_T_625, _T_626)
node _T_628 = or(UInt<1>(0h0), _T_627)
node _T_629 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_630 = cvt(_T_629)
node _T_631 = and(_T_630, asSInt(UInt<13>(0h1000)))
node _T_632 = asSInt(_T_631)
node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0)))
node _T_634 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_635 = cvt(_T_634)
node _T_636 = and(_T_635, asSInt(UInt<11>(0h400)))
node _T_637 = asSInt(_T_636)
node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0)))
node _T_639 = xor(io.in.a.bits.address, UInt<14>(0h2400))
node _T_640 = cvt(_T_639)
node _T_641 = and(_T_640, asSInt(UInt<9>(0h100)))
node _T_642 = asSInt(_T_641)
node _T_643 = eq(_T_642, asSInt(UInt<1>(0h0)))
node _T_644 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_645 = cvt(_T_644)
node _T_646 = and(_T_645, asSInt(UInt<13>(0h1000)))
node _T_647 = asSInt(_T_646)
node _T_648 = eq(_T_647, asSInt(UInt<1>(0h0)))
node _T_649 = or(_T_633, _T_638)
node _T_650 = or(_T_649, _T_643)
node _T_651 = or(_T_650, _T_648)
node _T_652 = and(_T_628, _T_651)
node _T_653 = or(UInt<1>(0h0), _T_652)
node _T_654 = and(_T_624, _T_653)
node _T_655 = asUInt(reset)
node _T_656 = eq(_T_655, UInt<1>(0h0))
when _T_656 :
node _T_657 = eq(_T_654, UInt<1>(0h0))
when _T_657 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_654, UInt<1>(0h1), "") : assert_26
node _T_658 = asUInt(reset)
node _T_659 = eq(_T_658, UInt<1>(0h0))
when _T_659 :
node _T_660 = eq(source_ok, UInt<1>(0h0))
when _T_660 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_661 = asUInt(reset)
node _T_662 = eq(_T_661, UInt<1>(0h0))
when _T_662 :
node _T_663 = eq(is_aligned, UInt<1>(0h0))
when _T_663 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_664 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_665 = asUInt(reset)
node _T_666 = eq(_T_665, UInt<1>(0h0))
when _T_666 :
node _T_667 = eq(_T_664, UInt<1>(0h0))
when _T_667 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_664, UInt<1>(0h1), "") : assert_29
node _T_668 = eq(io.in.a.bits.mask, mask)
node _T_669 = asUInt(reset)
node _T_670 = eq(_T_669, UInt<1>(0h0))
when _T_670 :
node _T_671 = eq(_T_668, UInt<1>(0h0))
when _T_671 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_668, UInt<1>(0h1), "") : assert_30
node _T_672 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_672 :
node _T_673 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_674 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_675 = and(_T_673, _T_674)
node _T_676 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_677 = shr(io.in.a.bits.source, 2)
node _T_678 = eq(_T_677, UInt<1>(0h0))
node _T_679 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_680 = and(_T_678, _T_679)
node _T_681 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_682 = and(_T_680, _T_681)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_683 = shr(io.in.a.bits.source, 2)
node _T_684 = eq(_T_683, UInt<1>(0h1))
node _T_685 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_686 = and(_T_684, _T_685)
node _T_687 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_688 = and(_T_686, _T_687)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_689 = shr(io.in.a.bits.source, 2)
node _T_690 = eq(_T_689, UInt<2>(0h2))
node _T_691 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_692 = and(_T_690, _T_691)
node _T_693 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_694 = and(_T_692, _T_693)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_695 = shr(io.in.a.bits.source, 2)
node _T_696 = eq(_T_695, UInt<2>(0h3))
node _T_697 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_698 = and(_T_696, _T_697)
node _T_699 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_700 = and(_T_698, _T_699)
node _T_701 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_702 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_703 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_704 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_705 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_706 = or(_T_676, _T_682)
node _T_707 = or(_T_706, _T_688)
node _T_708 = or(_T_707, _T_694)
node _T_709 = or(_T_708, _T_700)
node _T_710 = or(_T_709, _T_701)
node _T_711 = or(_T_710, _T_702)
node _T_712 = or(_T_711, _T_703)
node _T_713 = or(_T_712, _T_704)
node _T_714 = or(_T_713, _T_705)
node _T_715 = and(_T_675, _T_714)
node _T_716 = or(UInt<1>(0h0), _T_715)
node _T_717 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_718 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_719 = and(_T_717, _T_718)
node _T_720 = or(UInt<1>(0h0), _T_719)
node _T_721 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_722 = cvt(_T_721)
node _T_723 = and(_T_722, asSInt(UInt<13>(0h1000)))
node _T_724 = asSInt(_T_723)
node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0)))
node _T_726 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_727 = cvt(_T_726)
node _T_728 = and(_T_727, asSInt(UInt<11>(0h400)))
node _T_729 = asSInt(_T_728)
node _T_730 = eq(_T_729, asSInt(UInt<1>(0h0)))
node _T_731 = xor(io.in.a.bits.address, UInt<14>(0h2400))
node _T_732 = cvt(_T_731)
node _T_733 = and(_T_732, asSInt(UInt<9>(0h100)))
node _T_734 = asSInt(_T_733)
node _T_735 = eq(_T_734, asSInt(UInt<1>(0h0)))
node _T_736 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_737 = cvt(_T_736)
node _T_738 = and(_T_737, asSInt(UInt<13>(0h1000)))
node _T_739 = asSInt(_T_738)
node _T_740 = eq(_T_739, asSInt(UInt<1>(0h0)))
node _T_741 = or(_T_725, _T_730)
node _T_742 = or(_T_741, _T_735)
node _T_743 = or(_T_742, _T_740)
node _T_744 = and(_T_720, _T_743)
node _T_745 = or(UInt<1>(0h0), _T_744)
node _T_746 = and(_T_716, _T_745)
node _T_747 = asUInt(reset)
node _T_748 = eq(_T_747, UInt<1>(0h0))
when _T_748 :
node _T_749 = eq(_T_746, UInt<1>(0h0))
when _T_749 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_746, UInt<1>(0h1), "") : assert_31
node _T_750 = asUInt(reset)
node _T_751 = eq(_T_750, UInt<1>(0h0))
when _T_751 :
node _T_752 = eq(source_ok, UInt<1>(0h0))
when _T_752 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_753 = asUInt(reset)
node _T_754 = eq(_T_753, UInt<1>(0h0))
when _T_754 :
node _T_755 = eq(is_aligned, UInt<1>(0h0))
when _T_755 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_756 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_757 = asUInt(reset)
node _T_758 = eq(_T_757, UInt<1>(0h0))
when _T_758 :
node _T_759 = eq(_T_756, UInt<1>(0h0))
when _T_759 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_756, UInt<1>(0h1), "") : assert_34
node _T_760 = not(mask)
node _T_761 = and(io.in.a.bits.mask, _T_760)
node _T_762 = eq(_T_761, UInt<1>(0h0))
node _T_763 = asUInt(reset)
node _T_764 = eq(_T_763, UInt<1>(0h0))
when _T_764 :
node _T_765 = eq(_T_762, UInt<1>(0h0))
when _T_765 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_762, UInt<1>(0h1), "") : assert_35
node _T_766 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_766 :
node _T_767 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_768 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_769 = and(_T_767, _T_768)
node _T_770 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_771 = shr(io.in.a.bits.source, 2)
node _T_772 = eq(_T_771, UInt<1>(0h0))
node _T_773 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_774 = and(_T_772, _T_773)
node _T_775 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_776 = and(_T_774, _T_775)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_777 = shr(io.in.a.bits.source, 2)
node _T_778 = eq(_T_777, UInt<1>(0h1))
node _T_779 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_780 = and(_T_778, _T_779)
node _T_781 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_782 = and(_T_780, _T_781)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_783 = shr(io.in.a.bits.source, 2)
node _T_784 = eq(_T_783, UInt<2>(0h2))
node _T_785 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_786 = and(_T_784, _T_785)
node _T_787 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_788 = and(_T_786, _T_787)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_789 = shr(io.in.a.bits.source, 2)
node _T_790 = eq(_T_789, UInt<2>(0h3))
node _T_791 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_792 = and(_T_790, _T_791)
node _T_793 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_794 = and(_T_792, _T_793)
node _T_795 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_796 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_797 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_798 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_799 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_800 = or(_T_770, _T_776)
node _T_801 = or(_T_800, _T_782)
node _T_802 = or(_T_801, _T_788)
node _T_803 = or(_T_802, _T_794)
node _T_804 = or(_T_803, _T_795)
node _T_805 = or(_T_804, _T_796)
node _T_806 = or(_T_805, _T_797)
node _T_807 = or(_T_806, _T_798)
node _T_808 = or(_T_807, _T_799)
node _T_809 = and(_T_769, _T_808)
node _T_810 = or(UInt<1>(0h0), _T_809)
node _T_811 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_812 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_813 = and(_T_811, _T_812)
node _T_814 = or(UInt<1>(0h0), _T_813)
node _T_815 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_816 = cvt(_T_815)
node _T_817 = and(_T_816, asSInt(UInt<13>(0h1000)))
node _T_818 = asSInt(_T_817)
node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0)))
node _T_820 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_821 = cvt(_T_820)
node _T_822 = and(_T_821, asSInt(UInt<11>(0h400)))
node _T_823 = asSInt(_T_822)
node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0)))
node _T_825 = xor(io.in.a.bits.address, UInt<14>(0h2400))
node _T_826 = cvt(_T_825)
node _T_827 = and(_T_826, asSInt(UInt<9>(0h100)))
node _T_828 = asSInt(_T_827)
node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0)))
node _T_830 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_831 = cvt(_T_830)
node _T_832 = and(_T_831, asSInt(UInt<13>(0h1000)))
node _T_833 = asSInt(_T_832)
node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0)))
node _T_835 = or(_T_819, _T_824)
node _T_836 = or(_T_835, _T_829)
node _T_837 = or(_T_836, _T_834)
node _T_838 = and(_T_814, _T_837)
node _T_839 = or(UInt<1>(0h0), _T_838)
node _T_840 = and(_T_810, _T_839)
node _T_841 = asUInt(reset)
node _T_842 = eq(_T_841, UInt<1>(0h0))
when _T_842 :
node _T_843 = eq(_T_840, UInt<1>(0h0))
when _T_843 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_840, UInt<1>(0h1), "") : assert_36
node _T_844 = asUInt(reset)
node _T_845 = eq(_T_844, UInt<1>(0h0))
when _T_845 :
node _T_846 = eq(source_ok, UInt<1>(0h0))
when _T_846 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_847 = asUInt(reset)
node _T_848 = eq(_T_847, UInt<1>(0h0))
when _T_848 :
node _T_849 = eq(is_aligned, UInt<1>(0h0))
when _T_849 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_850 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_851 = asUInt(reset)
node _T_852 = eq(_T_851, UInt<1>(0h0))
when _T_852 :
node _T_853 = eq(_T_850, UInt<1>(0h0))
when _T_853 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_850, UInt<1>(0h1), "") : assert_39
node _T_854 = eq(io.in.a.bits.mask, mask)
node _T_855 = asUInt(reset)
node _T_856 = eq(_T_855, UInt<1>(0h0))
when _T_856 :
node _T_857 = eq(_T_854, UInt<1>(0h0))
when _T_857 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_854, UInt<1>(0h1), "") : assert_40
node _T_858 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_858 :
node _T_859 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_860 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_861 = and(_T_859, _T_860)
node _T_862 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_863 = shr(io.in.a.bits.source, 2)
node _T_864 = eq(_T_863, UInt<1>(0h0))
node _T_865 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_866 = and(_T_864, _T_865)
node _T_867 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_868 = and(_T_866, _T_867)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_869 = shr(io.in.a.bits.source, 2)
node _T_870 = eq(_T_869, UInt<1>(0h1))
node _T_871 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_872 = and(_T_870, _T_871)
node _T_873 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_874 = and(_T_872, _T_873)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_875 = shr(io.in.a.bits.source, 2)
node _T_876 = eq(_T_875, UInt<2>(0h2))
node _T_877 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_878 = and(_T_876, _T_877)
node _T_879 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_880 = and(_T_878, _T_879)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_881 = shr(io.in.a.bits.source, 2)
node _T_882 = eq(_T_881, UInt<2>(0h3))
node _T_883 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_884 = and(_T_882, _T_883)
node _T_885 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_886 = and(_T_884, _T_885)
node _T_887 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_888 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_889 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_890 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_891 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_892 = or(_T_862, _T_868)
node _T_893 = or(_T_892, _T_874)
node _T_894 = or(_T_893, _T_880)
node _T_895 = or(_T_894, _T_886)
node _T_896 = or(_T_895, _T_887)
node _T_897 = or(_T_896, _T_888)
node _T_898 = or(_T_897, _T_889)
node _T_899 = or(_T_898, _T_890)
node _T_900 = or(_T_899, _T_891)
node _T_901 = and(_T_861, _T_900)
node _T_902 = or(UInt<1>(0h0), _T_901)
node _T_903 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_904 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_905 = and(_T_903, _T_904)
node _T_906 = or(UInt<1>(0h0), _T_905)
node _T_907 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_908 = cvt(_T_907)
node _T_909 = and(_T_908, asSInt(UInt<13>(0h1000)))
node _T_910 = asSInt(_T_909)
node _T_911 = eq(_T_910, asSInt(UInt<1>(0h0)))
node _T_912 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_913 = cvt(_T_912)
node _T_914 = and(_T_913, asSInt(UInt<11>(0h400)))
node _T_915 = asSInt(_T_914)
node _T_916 = eq(_T_915, asSInt(UInt<1>(0h0)))
node _T_917 = xor(io.in.a.bits.address, UInt<14>(0h2400))
node _T_918 = cvt(_T_917)
node _T_919 = and(_T_918, asSInt(UInt<9>(0h100)))
node _T_920 = asSInt(_T_919)
node _T_921 = eq(_T_920, asSInt(UInt<1>(0h0)))
node _T_922 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_923 = cvt(_T_922)
node _T_924 = and(_T_923, asSInt(UInt<13>(0h1000)))
node _T_925 = asSInt(_T_924)
node _T_926 = eq(_T_925, asSInt(UInt<1>(0h0)))
node _T_927 = or(_T_911, _T_916)
node _T_928 = or(_T_927, _T_921)
node _T_929 = or(_T_928, _T_926)
node _T_930 = and(_T_906, _T_929)
node _T_931 = or(UInt<1>(0h0), _T_930)
node _T_932 = and(_T_902, _T_931)
node _T_933 = asUInt(reset)
node _T_934 = eq(_T_933, UInt<1>(0h0))
when _T_934 :
node _T_935 = eq(_T_932, UInt<1>(0h0))
when _T_935 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_932, UInt<1>(0h1), "") : assert_41
node _T_936 = asUInt(reset)
node _T_937 = eq(_T_936, UInt<1>(0h0))
when _T_937 :
node _T_938 = eq(source_ok, UInt<1>(0h0))
when _T_938 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_939 = asUInt(reset)
node _T_940 = eq(_T_939, UInt<1>(0h0))
when _T_940 :
node _T_941 = eq(is_aligned, UInt<1>(0h0))
when _T_941 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_942 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_943 = asUInt(reset)
node _T_944 = eq(_T_943, UInt<1>(0h0))
when _T_944 :
node _T_945 = eq(_T_942, UInt<1>(0h0))
when _T_945 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_942, UInt<1>(0h1), "") : assert_44
node _T_946 = eq(io.in.a.bits.mask, mask)
node _T_947 = asUInt(reset)
node _T_948 = eq(_T_947, UInt<1>(0h0))
when _T_948 :
node _T_949 = eq(_T_946, UInt<1>(0h0))
when _T_949 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_946, UInt<1>(0h1), "") : assert_45
node _T_950 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_950 :
node _T_951 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_952 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_953 = and(_T_951, _T_952)
node _T_954 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_955 = shr(io.in.a.bits.source, 2)
node _T_956 = eq(_T_955, UInt<1>(0h0))
node _T_957 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_958 = and(_T_956, _T_957)
node _T_959 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_960 = and(_T_958, _T_959)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_961 = shr(io.in.a.bits.source, 2)
node _T_962 = eq(_T_961, UInt<1>(0h1))
node _T_963 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_964 = and(_T_962, _T_963)
node _T_965 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_966 = and(_T_964, _T_965)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_967 = shr(io.in.a.bits.source, 2)
node _T_968 = eq(_T_967, UInt<2>(0h2))
node _T_969 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_970 = and(_T_968, _T_969)
node _T_971 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_972 = and(_T_970, _T_971)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_973 = shr(io.in.a.bits.source, 2)
node _T_974 = eq(_T_973, UInt<2>(0h3))
node _T_975 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_976 = and(_T_974, _T_975)
node _T_977 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_978 = and(_T_976, _T_977)
node _T_979 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_980 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_981 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_982 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_983 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_984 = or(_T_954, _T_960)
node _T_985 = or(_T_984, _T_966)
node _T_986 = or(_T_985, _T_972)
node _T_987 = or(_T_986, _T_978)
node _T_988 = or(_T_987, _T_979)
node _T_989 = or(_T_988, _T_980)
node _T_990 = or(_T_989, _T_981)
node _T_991 = or(_T_990, _T_982)
node _T_992 = or(_T_991, _T_983)
node _T_993 = and(_T_953, _T_992)
node _T_994 = or(UInt<1>(0h0), _T_993)
node _T_995 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_996 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_997 = cvt(_T_996)
node _T_998 = and(_T_997, asSInt(UInt<13>(0h1000)))
node _T_999 = asSInt(_T_998)
node _T_1000 = eq(_T_999, asSInt(UInt<1>(0h0)))
node _T_1001 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_1002 = cvt(_T_1001)
node _T_1003 = and(_T_1002, asSInt(UInt<11>(0h400)))
node _T_1004 = asSInt(_T_1003)
node _T_1005 = eq(_T_1004, asSInt(UInt<1>(0h0)))
node _T_1006 = xor(io.in.a.bits.address, UInt<14>(0h2400))
node _T_1007 = cvt(_T_1006)
node _T_1008 = and(_T_1007, asSInt(UInt<9>(0h100)))
node _T_1009 = asSInt(_T_1008)
node _T_1010 = eq(_T_1009, asSInt(UInt<1>(0h0)))
node _T_1011 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1012 = cvt(_T_1011)
node _T_1013 = and(_T_1012, asSInt(UInt<13>(0h1000)))
node _T_1014 = asSInt(_T_1013)
node _T_1015 = eq(_T_1014, asSInt(UInt<1>(0h0)))
node _T_1016 = or(_T_1000, _T_1005)
node _T_1017 = or(_T_1016, _T_1010)
node _T_1018 = or(_T_1017, _T_1015)
node _T_1019 = and(_T_995, _T_1018)
node _T_1020 = or(UInt<1>(0h0), _T_1019)
node _T_1021 = and(_T_994, _T_1020)
node _T_1022 = asUInt(reset)
node _T_1023 = eq(_T_1022, UInt<1>(0h0))
when _T_1023 :
node _T_1024 = eq(_T_1021, UInt<1>(0h0))
when _T_1024 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1021, UInt<1>(0h1), "") : assert_46
node _T_1025 = asUInt(reset)
node _T_1026 = eq(_T_1025, UInt<1>(0h0))
when _T_1026 :
node _T_1027 = eq(source_ok, UInt<1>(0h0))
when _T_1027 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1028 = asUInt(reset)
node _T_1029 = eq(_T_1028, UInt<1>(0h0))
when _T_1029 :
node _T_1030 = eq(is_aligned, UInt<1>(0h0))
when _T_1030 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1031 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1032 = asUInt(reset)
node _T_1033 = eq(_T_1032, UInt<1>(0h0))
when _T_1033 :
node _T_1034 = eq(_T_1031, UInt<1>(0h0))
when _T_1034 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1031, UInt<1>(0h1), "") : assert_49
node _T_1035 = eq(io.in.a.bits.mask, mask)
node _T_1036 = asUInt(reset)
node _T_1037 = eq(_T_1036, UInt<1>(0h0))
when _T_1037 :
node _T_1038 = eq(_T_1035, UInt<1>(0h0))
when _T_1038 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1035, UInt<1>(0h1), "") : assert_50
node _T_1039 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1040 = asUInt(reset)
node _T_1041 = eq(_T_1040, UInt<1>(0h0))
when _T_1041 :
node _T_1042 = eq(_T_1039, UInt<1>(0h0))
when _T_1042 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1039, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1043 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1044 = asUInt(reset)
node _T_1045 = eq(_T_1044, UInt<1>(0h0))
when _T_1045 :
node _T_1046 = eq(_T_1043, UInt<1>(0h0))
when _T_1046 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1043, UInt<1>(0h1), "") : assert_52
node _source_ok_T_38 = eq(io.in.d.bits.source, UInt<5>(0h11))
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_39 = shr(io.in.d.bits.source, 2)
node _source_ok_T_40 = eq(_source_ok_T_39, UInt<1>(0h0))
node _source_ok_T_41 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41)
node _source_ok_T_43 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_45 = shr(io.in.d.bits.source, 2)
node _source_ok_T_46 = eq(_source_ok_T_45, UInt<1>(0h1))
node _source_ok_T_47 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47)
node _source_ok_T_49 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_51 = shr(io.in.d.bits.source, 2)
node _source_ok_T_52 = eq(_source_ok_T_51, UInt<2>(0h2))
node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53)
node _source_ok_T_55 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_57 = shr(io.in.d.bits.source, 2)
node _source_ok_T_58 = eq(_source_ok_T_57, UInt<2>(0h3))
node _source_ok_T_59 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59)
node _source_ok_T_61 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61)
node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_T_65 = eq(io.in.d.bits.source, UInt<6>(0h21))
node _source_ok_T_66 = eq(io.in.d.bits.source, UInt<6>(0h22))
node _source_ok_T_67 = eq(io.in.d.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE_1 : UInt<1>[10]
connect _source_ok_WIRE_1[0], _source_ok_T_38
connect _source_ok_WIRE_1[1], _source_ok_T_44
connect _source_ok_WIRE_1[2], _source_ok_T_50
connect _source_ok_WIRE_1[3], _source_ok_T_56
connect _source_ok_WIRE_1[4], _source_ok_T_62
connect _source_ok_WIRE_1[5], _source_ok_T_63
connect _source_ok_WIRE_1[6], _source_ok_T_64
connect _source_ok_WIRE_1[7], _source_ok_T_65
connect _source_ok_WIRE_1[8], _source_ok_T_66
connect _source_ok_WIRE_1[9], _source_ok_T_67
node _source_ok_T_68 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[2])
node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[3])
node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[4])
node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE_1[5])
node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE_1[6])
node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE_1[7])
node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE_1[8])
node source_ok_1 = or(_source_ok_T_75, _source_ok_WIRE_1[9])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1047 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1047 :
node _T_1048 = asUInt(reset)
node _T_1049 = eq(_T_1048, UInt<1>(0h0))
when _T_1049 :
node _T_1050 = eq(source_ok_1, UInt<1>(0h0))
when _T_1050 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1051 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1052 = asUInt(reset)
node _T_1053 = eq(_T_1052, UInt<1>(0h0))
when _T_1053 :
node _T_1054 = eq(_T_1051, UInt<1>(0h0))
when _T_1054 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1051, UInt<1>(0h1), "") : assert_54
node _T_1055 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1056 = asUInt(reset)
node _T_1057 = eq(_T_1056, UInt<1>(0h0))
when _T_1057 :
node _T_1058 = eq(_T_1055, UInt<1>(0h0))
when _T_1058 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1055, UInt<1>(0h1), "") : assert_55
node _T_1059 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1060 = asUInt(reset)
node _T_1061 = eq(_T_1060, UInt<1>(0h0))
when _T_1061 :
node _T_1062 = eq(_T_1059, UInt<1>(0h0))
when _T_1062 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1059, UInt<1>(0h1), "") : assert_56
node _T_1063 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1064 = asUInt(reset)
node _T_1065 = eq(_T_1064, UInt<1>(0h0))
when _T_1065 :
node _T_1066 = eq(_T_1063, UInt<1>(0h0))
when _T_1066 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1063, UInt<1>(0h1), "") : assert_57
node _T_1067 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1067 :
node _T_1068 = asUInt(reset)
node _T_1069 = eq(_T_1068, UInt<1>(0h0))
when _T_1069 :
node _T_1070 = eq(source_ok_1, UInt<1>(0h0))
when _T_1070 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1071 = asUInt(reset)
node _T_1072 = eq(_T_1071, UInt<1>(0h0))
when _T_1072 :
node _T_1073 = eq(sink_ok, UInt<1>(0h0))
when _T_1073 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1074 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1075 = asUInt(reset)
node _T_1076 = eq(_T_1075, UInt<1>(0h0))
when _T_1076 :
node _T_1077 = eq(_T_1074, UInt<1>(0h0))
when _T_1077 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1074, UInt<1>(0h1), "") : assert_60
node _T_1078 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1079 = asUInt(reset)
node _T_1080 = eq(_T_1079, UInt<1>(0h0))
when _T_1080 :
node _T_1081 = eq(_T_1078, UInt<1>(0h0))
when _T_1081 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1078, UInt<1>(0h1), "") : assert_61
node _T_1082 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1083 = asUInt(reset)
node _T_1084 = eq(_T_1083, UInt<1>(0h0))
when _T_1084 :
node _T_1085 = eq(_T_1082, UInt<1>(0h0))
when _T_1085 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1082, UInt<1>(0h1), "") : assert_62
node _T_1086 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1087 = asUInt(reset)
node _T_1088 = eq(_T_1087, UInt<1>(0h0))
when _T_1088 :
node _T_1089 = eq(_T_1086, UInt<1>(0h0))
when _T_1089 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1086, UInt<1>(0h1), "") : assert_63
node _T_1090 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1091 = or(UInt<1>(0h0), _T_1090)
node _T_1092 = asUInt(reset)
node _T_1093 = eq(_T_1092, UInt<1>(0h0))
when _T_1093 :
node _T_1094 = eq(_T_1091, UInt<1>(0h0))
when _T_1094 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1091, UInt<1>(0h1), "") : assert_64
node _T_1095 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1095 :
node _T_1096 = asUInt(reset)
node _T_1097 = eq(_T_1096, UInt<1>(0h0))
when _T_1097 :
node _T_1098 = eq(source_ok_1, UInt<1>(0h0))
when _T_1098 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1099 = asUInt(reset)
node _T_1100 = eq(_T_1099, UInt<1>(0h0))
when _T_1100 :
node _T_1101 = eq(sink_ok, UInt<1>(0h0))
when _T_1101 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1102 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1103 = asUInt(reset)
node _T_1104 = eq(_T_1103, UInt<1>(0h0))
when _T_1104 :
node _T_1105 = eq(_T_1102, UInt<1>(0h0))
when _T_1105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1102, UInt<1>(0h1), "") : assert_67
node _T_1106 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1107 = asUInt(reset)
node _T_1108 = eq(_T_1107, UInt<1>(0h0))
when _T_1108 :
node _T_1109 = eq(_T_1106, UInt<1>(0h0))
when _T_1109 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1106, UInt<1>(0h1), "") : assert_68
node _T_1110 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1111 = asUInt(reset)
node _T_1112 = eq(_T_1111, UInt<1>(0h0))
when _T_1112 :
node _T_1113 = eq(_T_1110, UInt<1>(0h0))
when _T_1113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1110, UInt<1>(0h1), "") : assert_69
node _T_1114 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1115 = or(_T_1114, io.in.d.bits.corrupt)
node _T_1116 = asUInt(reset)
node _T_1117 = eq(_T_1116, UInt<1>(0h0))
when _T_1117 :
node _T_1118 = eq(_T_1115, UInt<1>(0h0))
when _T_1118 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1115, UInt<1>(0h1), "") : assert_70
node _T_1119 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1120 = or(UInt<1>(0h0), _T_1119)
node _T_1121 = asUInt(reset)
node _T_1122 = eq(_T_1121, UInt<1>(0h0))
when _T_1122 :
node _T_1123 = eq(_T_1120, UInt<1>(0h0))
when _T_1123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1120, UInt<1>(0h1), "") : assert_71
node _T_1124 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1124 :
node _T_1125 = asUInt(reset)
node _T_1126 = eq(_T_1125, UInt<1>(0h0))
when _T_1126 :
node _T_1127 = eq(source_ok_1, UInt<1>(0h0))
when _T_1127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1128 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1129 = asUInt(reset)
node _T_1130 = eq(_T_1129, UInt<1>(0h0))
when _T_1130 :
node _T_1131 = eq(_T_1128, UInt<1>(0h0))
when _T_1131 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1128, UInt<1>(0h1), "") : assert_73
node _T_1132 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1133 = asUInt(reset)
node _T_1134 = eq(_T_1133, UInt<1>(0h0))
when _T_1134 :
node _T_1135 = eq(_T_1132, UInt<1>(0h0))
when _T_1135 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1132, UInt<1>(0h1), "") : assert_74
node _T_1136 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1137 = or(UInt<1>(0h0), _T_1136)
node _T_1138 = asUInt(reset)
node _T_1139 = eq(_T_1138, UInt<1>(0h0))
when _T_1139 :
node _T_1140 = eq(_T_1137, UInt<1>(0h0))
when _T_1140 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1137, UInt<1>(0h1), "") : assert_75
node _T_1141 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1141 :
node _T_1142 = asUInt(reset)
node _T_1143 = eq(_T_1142, UInt<1>(0h0))
when _T_1143 :
node _T_1144 = eq(source_ok_1, UInt<1>(0h0))
when _T_1144 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1145 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1146 = asUInt(reset)
node _T_1147 = eq(_T_1146, UInt<1>(0h0))
when _T_1147 :
node _T_1148 = eq(_T_1145, UInt<1>(0h0))
when _T_1148 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1145, UInt<1>(0h1), "") : assert_77
node _T_1149 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1150 = or(_T_1149, io.in.d.bits.corrupt)
node _T_1151 = asUInt(reset)
node _T_1152 = eq(_T_1151, UInt<1>(0h0))
when _T_1152 :
node _T_1153 = eq(_T_1150, UInt<1>(0h0))
when _T_1153 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1150, UInt<1>(0h1), "") : assert_78
node _T_1154 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1155 = or(UInt<1>(0h0), _T_1154)
node _T_1156 = asUInt(reset)
node _T_1157 = eq(_T_1156, UInt<1>(0h0))
when _T_1157 :
node _T_1158 = eq(_T_1155, UInt<1>(0h0))
when _T_1158 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1155, UInt<1>(0h1), "") : assert_79
node _T_1159 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1159 :
node _T_1160 = asUInt(reset)
node _T_1161 = eq(_T_1160, UInt<1>(0h0))
when _T_1161 :
node _T_1162 = eq(source_ok_1, UInt<1>(0h0))
when _T_1162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1163 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1164 = asUInt(reset)
node _T_1165 = eq(_T_1164, UInt<1>(0h0))
when _T_1165 :
node _T_1166 = eq(_T_1163, UInt<1>(0h0))
when _T_1166 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1163, UInt<1>(0h1), "") : assert_81
node _T_1167 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1168 = asUInt(reset)
node _T_1169 = eq(_T_1168, UInt<1>(0h0))
when _T_1169 :
node _T_1170 = eq(_T_1167, UInt<1>(0h0))
when _T_1170 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1167, UInt<1>(0h1), "") : assert_82
node _T_1171 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1172 = or(UInt<1>(0h0), _T_1171)
node _T_1173 = asUInt(reset)
node _T_1174 = eq(_T_1173, UInt<1>(0h0))
when _T_1174 :
node _T_1175 = eq(_T_1172, UInt<1>(0h0))
when _T_1175 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1172, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<29>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1176 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1177 = asUInt(reset)
node _T_1178 = eq(_T_1177, UInt<1>(0h0))
when _T_1178 :
node _T_1179 = eq(_T_1176, UInt<1>(0h0))
when _T_1179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1176, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1180 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1181 = asUInt(reset)
node _T_1182 = eq(_T_1181, UInt<1>(0h0))
when _T_1182 :
node _T_1183 = eq(_T_1180, UInt<1>(0h0))
when _T_1183 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1180, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1184 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1185 = asUInt(reset)
node _T_1186 = eq(_T_1185, UInt<1>(0h0))
when _T_1186 :
node _T_1187 = eq(_T_1184, UInt<1>(0h0))
when _T_1187 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1184, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1188 = eq(a_first, UInt<1>(0h0))
node _T_1189 = and(io.in.a.valid, _T_1188)
when _T_1189 :
node _T_1190 = eq(io.in.a.bits.opcode, opcode)
node _T_1191 = asUInt(reset)
node _T_1192 = eq(_T_1191, UInt<1>(0h0))
when _T_1192 :
node _T_1193 = eq(_T_1190, UInt<1>(0h0))
when _T_1193 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1190, UInt<1>(0h1), "") : assert_87
node _T_1194 = eq(io.in.a.bits.param, param)
node _T_1195 = asUInt(reset)
node _T_1196 = eq(_T_1195, UInt<1>(0h0))
when _T_1196 :
node _T_1197 = eq(_T_1194, UInt<1>(0h0))
when _T_1197 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1194, UInt<1>(0h1), "") : assert_88
node _T_1198 = eq(io.in.a.bits.size, size)
node _T_1199 = asUInt(reset)
node _T_1200 = eq(_T_1199, UInt<1>(0h0))
when _T_1200 :
node _T_1201 = eq(_T_1198, UInt<1>(0h0))
when _T_1201 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1198, UInt<1>(0h1), "") : assert_89
node _T_1202 = eq(io.in.a.bits.source, source)
node _T_1203 = asUInt(reset)
node _T_1204 = eq(_T_1203, UInt<1>(0h0))
when _T_1204 :
node _T_1205 = eq(_T_1202, UInt<1>(0h0))
when _T_1205 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1202, UInt<1>(0h1), "") : assert_90
node _T_1206 = eq(io.in.a.bits.address, address)
node _T_1207 = asUInt(reset)
node _T_1208 = eq(_T_1207, UInt<1>(0h0))
when _T_1208 :
node _T_1209 = eq(_T_1206, UInt<1>(0h0))
when _T_1209 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1206, UInt<1>(0h1), "") : assert_91
node _T_1210 = and(io.in.a.ready, io.in.a.valid)
node _T_1211 = and(_T_1210, a_first)
when _T_1211 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1212 = eq(d_first, UInt<1>(0h0))
node _T_1213 = and(io.in.d.valid, _T_1212)
when _T_1213 :
node _T_1214 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1215 = asUInt(reset)
node _T_1216 = eq(_T_1215, UInt<1>(0h0))
when _T_1216 :
node _T_1217 = eq(_T_1214, UInt<1>(0h0))
when _T_1217 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1214, UInt<1>(0h1), "") : assert_92
node _T_1218 = eq(io.in.d.bits.param, param_1)
node _T_1219 = asUInt(reset)
node _T_1220 = eq(_T_1219, UInt<1>(0h0))
when _T_1220 :
node _T_1221 = eq(_T_1218, UInt<1>(0h0))
when _T_1221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1218, UInt<1>(0h1), "") : assert_93
node _T_1222 = eq(io.in.d.bits.size, size_1)
node _T_1223 = asUInt(reset)
node _T_1224 = eq(_T_1223, UInt<1>(0h0))
when _T_1224 :
node _T_1225 = eq(_T_1222, UInt<1>(0h0))
when _T_1225 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1222, UInt<1>(0h1), "") : assert_94
node _T_1226 = eq(io.in.d.bits.source, source_1)
node _T_1227 = asUInt(reset)
node _T_1228 = eq(_T_1227, UInt<1>(0h0))
when _T_1228 :
node _T_1229 = eq(_T_1226, UInt<1>(0h0))
when _T_1229 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1226, UInt<1>(0h1), "") : assert_95
node _T_1230 = eq(io.in.d.bits.sink, sink)
node _T_1231 = asUInt(reset)
node _T_1232 = eq(_T_1231, UInt<1>(0h0))
when _T_1232 :
node _T_1233 = eq(_T_1230, UInt<1>(0h0))
when _T_1233 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1230, UInt<1>(0h1), "") : assert_96
node _T_1234 = eq(io.in.d.bits.denied, denied)
node _T_1235 = asUInt(reset)
node _T_1236 = eq(_T_1235, UInt<1>(0h0))
when _T_1236 :
node _T_1237 = eq(_T_1234, UInt<1>(0h0))
when _T_1237 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1234, UInt<1>(0h1), "") : assert_97
node _T_1238 = and(io.in.d.ready, io.in.d.valid)
node _T_1239 = and(_T_1238, d_first)
when _T_1239 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<65>
connect a_set, UInt<65>(0h0)
wire a_set_wo_ready : UInt<65>
connect a_set_wo_ready, UInt<65>(0h0)
wire a_opcodes_set : UInt<260>
connect a_opcodes_set, UInt<260>(0h0)
wire a_sizes_set : UInt<260>
connect a_sizes_set, UInt<260>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1240 = and(io.in.a.valid, a_first_1)
node _T_1241 = and(_T_1240, UInt<1>(0h1))
when _T_1241 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1242 = and(io.in.a.ready, io.in.a.valid)
node _T_1243 = and(_T_1242, a_first_1)
node _T_1244 = and(_T_1243, UInt<1>(0h1))
when _T_1244 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1245 = dshr(inflight, io.in.a.bits.source)
node _T_1246 = bits(_T_1245, 0, 0)
node _T_1247 = eq(_T_1246, UInt<1>(0h0))
node _T_1248 = asUInt(reset)
node _T_1249 = eq(_T_1248, UInt<1>(0h0))
when _T_1249 :
node _T_1250 = eq(_T_1247, UInt<1>(0h0))
when _T_1250 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1247, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<65>
connect d_clr, UInt<65>(0h0)
wire d_clr_wo_ready : UInt<65>
connect d_clr_wo_ready, UInt<65>(0h0)
wire d_opcodes_clr : UInt<260>
connect d_opcodes_clr, UInt<260>(0h0)
wire d_sizes_clr : UInt<260>
connect d_sizes_clr, UInt<260>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1251 = and(io.in.d.valid, d_first_1)
node _T_1252 = and(_T_1251, UInt<1>(0h1))
node _T_1253 = eq(d_release_ack, UInt<1>(0h0))
node _T_1254 = and(_T_1252, _T_1253)
when _T_1254 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1255 = and(io.in.d.ready, io.in.d.valid)
node _T_1256 = and(_T_1255, d_first_1)
node _T_1257 = and(_T_1256, UInt<1>(0h1))
node _T_1258 = eq(d_release_ack, UInt<1>(0h0))
node _T_1259 = and(_T_1257, _T_1258)
when _T_1259 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1260 = and(io.in.d.valid, d_first_1)
node _T_1261 = and(_T_1260, UInt<1>(0h1))
node _T_1262 = eq(d_release_ack, UInt<1>(0h0))
node _T_1263 = and(_T_1261, _T_1262)
when _T_1263 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1264 = dshr(inflight, io.in.d.bits.source)
node _T_1265 = bits(_T_1264, 0, 0)
node _T_1266 = or(_T_1265, same_cycle_resp)
node _T_1267 = asUInt(reset)
node _T_1268 = eq(_T_1267, UInt<1>(0h0))
when _T_1268 :
node _T_1269 = eq(_T_1266, UInt<1>(0h0))
when _T_1269 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1266, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1270 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1271 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1272 = or(_T_1270, _T_1271)
node _T_1273 = asUInt(reset)
node _T_1274 = eq(_T_1273, UInt<1>(0h0))
when _T_1274 :
node _T_1275 = eq(_T_1272, UInt<1>(0h0))
when _T_1275 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1272, UInt<1>(0h1), "") : assert_100
node _T_1276 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1277 = asUInt(reset)
node _T_1278 = eq(_T_1277, UInt<1>(0h0))
when _T_1278 :
node _T_1279 = eq(_T_1276, UInt<1>(0h0))
when _T_1279 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1276, UInt<1>(0h1), "") : assert_101
else :
node _T_1280 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1281 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1282 = or(_T_1280, _T_1281)
node _T_1283 = asUInt(reset)
node _T_1284 = eq(_T_1283, UInt<1>(0h0))
when _T_1284 :
node _T_1285 = eq(_T_1282, UInt<1>(0h0))
when _T_1285 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1282, UInt<1>(0h1), "") : assert_102
node _T_1286 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1287 = asUInt(reset)
node _T_1288 = eq(_T_1287, UInt<1>(0h0))
when _T_1288 :
node _T_1289 = eq(_T_1286, UInt<1>(0h0))
when _T_1289 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1286, UInt<1>(0h1), "") : assert_103
node _T_1290 = and(io.in.d.valid, d_first_1)
node _T_1291 = and(_T_1290, a_first_1)
node _T_1292 = and(_T_1291, io.in.a.valid)
node _T_1293 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1294 = and(_T_1292, _T_1293)
node _T_1295 = eq(d_release_ack, UInt<1>(0h0))
node _T_1296 = and(_T_1294, _T_1295)
when _T_1296 :
node _T_1297 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1298 = or(_T_1297, io.in.a.ready)
node _T_1299 = asUInt(reset)
node _T_1300 = eq(_T_1299, UInt<1>(0h0))
when _T_1300 :
node _T_1301 = eq(_T_1298, UInt<1>(0h0))
when _T_1301 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1298, UInt<1>(0h1), "") : assert_104
node _T_1302 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1303 = orr(a_set_wo_ready)
node _T_1304 = eq(_T_1303, UInt<1>(0h0))
node _T_1305 = or(_T_1302, _T_1304)
node _T_1306 = asUInt(reset)
node _T_1307 = eq(_T_1306, UInt<1>(0h0))
when _T_1307 :
node _T_1308 = eq(_T_1305, UInt<1>(0h0))
when _T_1308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1305, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_8
node _T_1309 = orr(inflight)
node _T_1310 = eq(_T_1309, UInt<1>(0h0))
node _T_1311 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1312 = or(_T_1310, _T_1311)
node _T_1313 = lt(watchdog, plusarg_reader.out)
node _T_1314 = or(_T_1312, _T_1313)
node _T_1315 = asUInt(reset)
node _T_1316 = eq(_T_1315, UInt<1>(0h0))
when _T_1316 :
node _T_1317 = eq(_T_1314, UInt<1>(0h0))
when _T_1317 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1314, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1318 = and(io.in.a.ready, io.in.a.valid)
node _T_1319 = and(io.in.d.ready, io.in.d.valid)
node _T_1320 = or(_T_1318, _T_1319)
when _T_1320 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<29>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<65>
connect c_set, UInt<65>(0h0)
wire c_set_wo_ready : UInt<65>
connect c_set_wo_ready, UInt<65>(0h0)
wire c_opcodes_set : UInt<260>
connect c_opcodes_set, UInt<260>(0h0)
wire c_sizes_set : UInt<260>
connect c_sizes_set, UInt<260>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<29>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1321 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<29>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1322 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1323 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1324 = and(_T_1322, _T_1323)
node _T_1325 = and(_T_1321, _T_1324)
when _T_1325 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<29>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1326 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1327 = and(_T_1326, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<29>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1328 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1329 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1330 = and(_T_1328, _T_1329)
node _T_1331 = and(_T_1327, _T_1330)
when _T_1331 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<29>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1332 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1333 = bits(_T_1332, 0, 0)
node _T_1334 = eq(_T_1333, UInt<1>(0h0))
node _T_1335 = asUInt(reset)
node _T_1336 = eq(_T_1335, UInt<1>(0h0))
when _T_1336 :
node _T_1337 = eq(_T_1334, UInt<1>(0h0))
when _T_1337 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1334, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<65>
connect d_clr_1, UInt<65>(0h0)
wire d_clr_wo_ready_1 : UInt<65>
connect d_clr_wo_ready_1, UInt<65>(0h0)
wire d_opcodes_clr_1 : UInt<260>
connect d_opcodes_clr_1, UInt<260>(0h0)
wire d_sizes_clr_1 : UInt<260>
connect d_sizes_clr_1, UInt<260>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1338 = and(io.in.d.valid, d_first_2)
node _T_1339 = and(_T_1338, UInt<1>(0h1))
node _T_1340 = and(_T_1339, d_release_ack_1)
when _T_1340 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1341 = and(io.in.d.ready, io.in.d.valid)
node _T_1342 = and(_T_1341, d_first_2)
node _T_1343 = and(_T_1342, UInt<1>(0h1))
node _T_1344 = and(_T_1343, d_release_ack_1)
when _T_1344 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1345 = and(io.in.d.valid, d_first_2)
node _T_1346 = and(_T_1345, UInt<1>(0h1))
node _T_1347 = and(_T_1346, d_release_ack_1)
when _T_1347 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1348 = dshr(inflight_1, io.in.d.bits.source)
node _T_1349 = bits(_T_1348, 0, 0)
node _T_1350 = or(_T_1349, same_cycle_resp_1)
node _T_1351 = asUInt(reset)
node _T_1352 = eq(_T_1351, UInt<1>(0h0))
when _T_1352 :
node _T_1353 = eq(_T_1350, UInt<1>(0h0))
when _T_1353 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1350, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<29>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1354 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1355 = asUInt(reset)
node _T_1356 = eq(_T_1355, UInt<1>(0h0))
when _T_1356 :
node _T_1357 = eq(_T_1354, UInt<1>(0h0))
when _T_1357 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1354, UInt<1>(0h1), "") : assert_109
else :
node _T_1358 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1359 = asUInt(reset)
node _T_1360 = eq(_T_1359, UInt<1>(0h0))
when _T_1360 :
node _T_1361 = eq(_T_1358, UInt<1>(0h0))
when _T_1361 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1358, UInt<1>(0h1), "") : assert_110
node _T_1362 = and(io.in.d.valid, d_first_2)
node _T_1363 = and(_T_1362, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<29>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1364 = and(_T_1363, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<29>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1365 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1366 = and(_T_1364, _T_1365)
node _T_1367 = and(_T_1366, d_release_ack_1)
node _T_1368 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1369 = and(_T_1367, _T_1368)
when _T_1369 :
node _T_1370 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<29>(0h0)
connect _WIRE_26.bits.source, UInt<7>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1371 = or(_T_1370, _WIRE_27.ready)
node _T_1372 = asUInt(reset)
node _T_1373 = eq(_T_1372, UInt<1>(0h0))
when _T_1373 :
node _T_1374 = eq(_T_1371, UInt<1>(0h0))
when _T_1374 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1371, UInt<1>(0h1), "") : assert_111
node _T_1375 = orr(c_set_wo_ready)
when _T_1375 :
node _T_1376 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1377 = asUInt(reset)
node _T_1378 = eq(_T_1377, UInt<1>(0h0))
when _T_1378 :
node _T_1379 = eq(_T_1376, UInt<1>(0h0))
when _T_1379 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1376, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_9
node _T_1380 = orr(inflight_1)
node _T_1381 = eq(_T_1380, UInt<1>(0h0))
node _T_1382 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1383 = or(_T_1381, _T_1382)
node _T_1384 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1385 = or(_T_1383, _T_1384)
node _T_1386 = asUInt(reset)
node _T_1387 = eq(_T_1386, UInt<1>(0h0))
when _T_1387 :
node _T_1388 = eq(_T_1385, UInt<1>(0h0))
when _T_1388 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1385, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<29>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1389 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1390 = and(io.in.d.ready, io.in.d.valid)
node _T_1391 = or(_T_1389, _T_1390)
when _T_1391 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_4( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire [127:0] _GEN_0 = {121'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [127:0] _GEN_3 = {121'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLCFromNoC_5 :
input clock : Clock
input reset : Reset
output io : { protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<65>, ingress_id : UInt}}}
wire protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
regreset is_const : UInt<1>, clock, reset, UInt<1>(0h1)
reg const_reg : UInt<46>, clock
node const = mux(io.flit.bits.head, io.flit.bits.payload, const_reg)
node _io_flit_ready_T = eq(io.flit.bits.tail, UInt<1>(0h0))
node _io_flit_ready_T_1 = and(is_const, _io_flit_ready_T)
node _io_flit_ready_T_2 = or(_io_flit_ready_T_1, protocol.ready)
connect io.flit.ready, _io_flit_ready_T_2
node _protocol_valid_T = eq(is_const, UInt<1>(0h0))
node _protocol_valid_T_1 = or(_protocol_valid_T, io.flit.bits.tail)
node _protocol_valid_T_2 = and(_protocol_valid_T_1, io.flit.valid)
connect protocol.valid, _protocol_valid_T_2
wire _protocol_bits_echo_WIRE : { }
wire _protocol_bits_echo_WIRE_1 : UInt<0>
connect _protocol_bits_echo_WIRE_1, const
connect protocol.bits.echo, _protocol_bits_echo_WIRE
node _T = shr(const, 0)
wire _protocol_bits_user_WIRE : { }
wire _protocol_bits_user_WIRE_1 : UInt<0>
connect _protocol_bits_user_WIRE_1, _T
connect protocol.bits.user, _protocol_bits_user_WIRE
node _T_1 = shr(_T, 0)
wire _protocol_bits_address_WIRE : UInt<29>
connect _protocol_bits_address_WIRE, _T_1
connect protocol.bits.address, _protocol_bits_address_WIRE
node _T_2 = shr(_T_1, 29)
wire _protocol_bits_source_WIRE : UInt<7>
connect _protocol_bits_source_WIRE, _T_2
connect protocol.bits.source, _protocol_bits_source_WIRE
node _T_3 = shr(_T_2, 7)
wire _protocol_bits_size_WIRE : UInt<4>
connect _protocol_bits_size_WIRE, _T_3
connect protocol.bits.size, _protocol_bits_size_WIRE
node _T_4 = shr(_T_3, 4)
wire _protocol_bits_param_WIRE : UInt<3>
connect _protocol_bits_param_WIRE, _T_4
connect protocol.bits.param, _protocol_bits_param_WIRE
node _T_5 = shr(_T_4, 3)
wire _protocol_bits_opcode_WIRE : UInt<3>
connect _protocol_bits_opcode_WIRE, _T_5
connect protocol.bits.opcode, _protocol_bits_opcode_WIRE
node _T_6 = shr(_T_5, 3)
wire _protocol_bits_corrupt_WIRE : UInt<1>
connect _protocol_bits_corrupt_WIRE, io.flit.bits.payload
connect protocol.bits.corrupt, _protocol_bits_corrupt_WIRE
node _T_7 = shr(io.flit.bits.payload, 1)
wire _protocol_bits_data_WIRE : UInt<64>
connect _protocol_bits_data_WIRE, _T_7
connect protocol.bits.data, _protocol_bits_data_WIRE
node _T_8 = shr(_T_7, 64)
node _T_9 = and(io.flit.ready, io.flit.valid)
node _T_10 = and(_T_9, io.flit.bits.head)
when _T_10 :
connect is_const, UInt<1>(0h0)
connect const_reg, io.flit.bits.payload
node _T_11 = and(io.flit.ready, io.flit.valid)
node _T_12 = and(_T_11, io.flit.bits.tail)
when _T_12 :
connect is_const, UInt<1>(0h1)
connect io.protocol, protocol | module TLCFromNoC_5( // @[TilelinkAdapters.scala:167:7]
input clock, // @[TilelinkAdapters.scala:167:7]
input reset, // @[TilelinkAdapters.scala:167:7]
output io_flit_ready, // @[TilelinkAdapters.scala:56:14]
input io_flit_valid, // @[TilelinkAdapters.scala:56:14]
input io_flit_bits_head, // @[TilelinkAdapters.scala:56:14]
input io_flit_bits_tail // @[TilelinkAdapters.scala:56:14]
);
reg is_const; // @[TilelinkAdapters.scala:68:25]
wire io_flit_ready_0 = is_const & ~io_flit_bits_tail; // @[TilelinkAdapters.scala:68:25, :71:{30,33}]
wire _GEN = io_flit_ready_0 & io_flit_valid; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[TilelinkAdapters.scala:167:7]
if (reset) // @[TilelinkAdapters.scala:167:7]
is_const <= 1'h1; // @[TilelinkAdapters.scala:68:25, :167:7]
else // @[TilelinkAdapters.scala:167:7]
is_const <= _GEN & io_flit_bits_tail | ~(_GEN & io_flit_bits_head) & is_const; // @[Decoupled.scala:51:35]
always @(posedge) |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_71 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0)
node _source_ok_T_31 = shr(io.in.a.bits.source, 3)
node _source_ok_T_32 = eq(_source_ok_T_31, UInt<3>(0h6))
node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33)
node _source_ok_T_35 = leq(source_ok_uncommonBits_4, UInt<3>(0h4))
node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35)
node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 2, 0)
node _source_ok_T_39 = shr(io.in.a.bits.source, 3)
node _source_ok_T_40 = eq(_source_ok_T_39, UInt<3>(0h4))
node _source_ok_T_41 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41)
node _source_ok_T_43 = leq(source_ok_uncommonBits_5, UInt<3>(0h4))
node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43)
node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _source_ok_T_46 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _source_ok_T_47 = eq(io.in.a.bits.source, UInt<8>(0h80))
wire _source_ok_WIRE : UInt<1>[18]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
connect _source_ok_WIRE[7], _source_ok_T_27
connect _source_ok_WIRE[8], _source_ok_T_28
connect _source_ok_WIRE[9], _source_ok_T_29
connect _source_ok_WIRE[10], _source_ok_T_30
connect _source_ok_WIRE[11], _source_ok_T_36
connect _source_ok_WIRE[12], _source_ok_T_37
connect _source_ok_WIRE[13], _source_ok_T_38
connect _source_ok_WIRE[14], _source_ok_T_44
connect _source_ok_WIRE[15], _source_ok_T_45
connect _source_ok_WIRE[16], _source_ok_T_46
connect _source_ok_WIRE[17], _source_ok_T_47
node _source_ok_T_48 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[2])
node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[3])
node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[4])
node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[5])
node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[6])
node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[7])
node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE[8])
node _source_ok_T_56 = or(_source_ok_T_55, _source_ok_WIRE[9])
node _source_ok_T_57 = or(_source_ok_T_56, _source_ok_WIRE[10])
node _source_ok_T_58 = or(_source_ok_T_57, _source_ok_WIRE[11])
node _source_ok_T_59 = or(_source_ok_T_58, _source_ok_WIRE[12])
node _source_ok_T_60 = or(_source_ok_T_59, _source_ok_WIRE[13])
node _source_ok_T_61 = or(_source_ok_T_60, _source_ok_WIRE[14])
node _source_ok_T_62 = or(_source_ok_T_61, _source_ok_WIRE[15])
node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE[16])
node source_ok = or(_source_ok_T_63, _source_ok_WIRE[17])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_81 = eq(_T_80, UInt<1>(0h0))
node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_83 = cvt(_T_82)
node _T_84 = and(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = asSInt(_T_84)
node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = or(_T_81, _T_86)
node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_89 = eq(_T_88, UInt<1>(0h0))
node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<1>(0h0)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_89, _T_94)
node _T_96 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_99 = cvt(_T_98)
node _T_100 = and(_T_99, asSInt(UInt<1>(0h0)))
node _T_101 = asSInt(_T_100)
node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = or(_T_97, _T_102)
node _T_104 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_105 = eq(_T_104, UInt<1>(0h0))
node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_107 = cvt(_T_106)
node _T_108 = and(_T_107, asSInt(UInt<1>(0h0)))
node _T_109 = asSInt(_T_108)
node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = or(_T_105, _T_110)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0)
node _T_112 = shr(io.in.a.bits.source, 3)
node _T_113 = eq(_T_112, UInt<3>(0h6))
node _T_114 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_115 = and(_T_113, _T_114)
node _T_116 = leq(uncommonBits_4, UInt<3>(0h4))
node _T_117 = and(_T_115, _T_116)
node _T_118 = eq(_T_117, UInt<1>(0h0))
node _T_119 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_120 = cvt(_T_119)
node _T_121 = and(_T_120, asSInt(UInt<1>(0h0)))
node _T_122 = asSInt(_T_121)
node _T_123 = eq(_T_122, asSInt(UInt<1>(0h0)))
node _T_124 = or(_T_118, _T_123)
node _T_125 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_126 = eq(_T_125, UInt<1>(0h0))
node _T_127 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_128 = cvt(_T_127)
node _T_129 = and(_T_128, asSInt(UInt<1>(0h0)))
node _T_130 = asSInt(_T_129)
node _T_131 = eq(_T_130, asSInt(UInt<1>(0h0)))
node _T_132 = or(_T_126, _T_131)
node _T_133 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_134 = eq(_T_133, UInt<1>(0h0))
node _T_135 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_136 = cvt(_T_135)
node _T_137 = and(_T_136, asSInt(UInt<1>(0h0)))
node _T_138 = asSInt(_T_137)
node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0)))
node _T_140 = or(_T_134, _T_139)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0)
node _T_141 = shr(io.in.a.bits.source, 3)
node _T_142 = eq(_T_141, UInt<3>(0h4))
node _T_143 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_144 = and(_T_142, _T_143)
node _T_145 = leq(uncommonBits_5, UInt<3>(0h4))
node _T_146 = and(_T_144, _T_145)
node _T_147 = eq(_T_146, UInt<1>(0h0))
node _T_148 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_149 = cvt(_T_148)
node _T_150 = and(_T_149, asSInt(UInt<1>(0h0)))
node _T_151 = asSInt(_T_150)
node _T_152 = eq(_T_151, asSInt(UInt<1>(0h0)))
node _T_153 = or(_T_147, _T_152)
node _T_154 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_155 = eq(_T_154, UInt<1>(0h0))
node _T_156 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_157 = cvt(_T_156)
node _T_158 = and(_T_157, asSInt(UInt<1>(0h0)))
node _T_159 = asSInt(_T_158)
node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0)))
node _T_161 = or(_T_155, _T_160)
node _T_162 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_163 = eq(_T_162, UInt<1>(0h0))
node _T_164 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_165 = cvt(_T_164)
node _T_166 = and(_T_165, asSInt(UInt<1>(0h0)))
node _T_167 = asSInt(_T_166)
node _T_168 = eq(_T_167, asSInt(UInt<1>(0h0)))
node _T_169 = or(_T_163, _T_168)
node _T_170 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_171 = eq(_T_170, UInt<1>(0h0))
node _T_172 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_173 = cvt(_T_172)
node _T_174 = and(_T_173, asSInt(UInt<1>(0h0)))
node _T_175 = asSInt(_T_174)
node _T_176 = eq(_T_175, asSInt(UInt<1>(0h0)))
node _T_177 = or(_T_171, _T_176)
node _T_178 = and(_T_11, _T_24)
node _T_179 = and(_T_178, _T_37)
node _T_180 = and(_T_179, _T_50)
node _T_181 = and(_T_180, _T_63)
node _T_182 = and(_T_181, _T_71)
node _T_183 = and(_T_182, _T_79)
node _T_184 = and(_T_183, _T_87)
node _T_185 = and(_T_184, _T_95)
node _T_186 = and(_T_185, _T_103)
node _T_187 = and(_T_186, _T_111)
node _T_188 = and(_T_187, _T_124)
node _T_189 = and(_T_188, _T_132)
node _T_190 = and(_T_189, _T_140)
node _T_191 = and(_T_190, _T_153)
node _T_192 = and(_T_191, _T_161)
node _T_193 = and(_T_192, _T_169)
node _T_194 = and(_T_193, _T_177)
node _T_195 = asUInt(reset)
node _T_196 = eq(_T_195, UInt<1>(0h0))
when _T_196 :
node _T_197 = eq(_T_194, UInt<1>(0h0))
when _T_197 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_194, UInt<1>(0h1), "") : assert_1
node _T_198 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_198 :
node _T_199 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_200 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_201 = and(_T_199, _T_200)
node _T_202 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_203 = shr(io.in.a.bits.source, 2)
node _T_204 = eq(_T_203, UInt<1>(0h0))
node _T_205 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_206 = and(_T_204, _T_205)
node _T_207 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_208 = and(_T_206, _T_207)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_209 = shr(io.in.a.bits.source, 2)
node _T_210 = eq(_T_209, UInt<1>(0h1))
node _T_211 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_212 = and(_T_210, _T_211)
node _T_213 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_214 = and(_T_212, _T_213)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_215 = shr(io.in.a.bits.source, 2)
node _T_216 = eq(_T_215, UInt<2>(0h2))
node _T_217 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_218 = and(_T_216, _T_217)
node _T_219 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_220 = and(_T_218, _T_219)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_221 = shr(io.in.a.bits.source, 2)
node _T_222 = eq(_T_221, UInt<2>(0h3))
node _T_223 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_224 = and(_T_222, _T_223)
node _T_225 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_226 = and(_T_224, _T_225)
node _T_227 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_228 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_229 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_230 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_231 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_232 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 2, 0)
node _T_233 = shr(io.in.a.bits.source, 3)
node _T_234 = eq(_T_233, UInt<3>(0h6))
node _T_235 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_236 = and(_T_234, _T_235)
node _T_237 = leq(uncommonBits_10, UInt<3>(0h4))
node _T_238 = and(_T_236, _T_237)
node _T_239 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0)
node _T_241 = shr(io.in.a.bits.source, 3)
node _T_242 = eq(_T_241, UInt<3>(0h4))
node _T_243 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_244 = and(_T_242, _T_243)
node _T_245 = leq(uncommonBits_11, UInt<3>(0h4))
node _T_246 = and(_T_244, _T_245)
node _T_247 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_249 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_250 = or(_T_202, _T_208)
node _T_251 = or(_T_250, _T_214)
node _T_252 = or(_T_251, _T_220)
node _T_253 = or(_T_252, _T_226)
node _T_254 = or(_T_253, _T_227)
node _T_255 = or(_T_254, _T_228)
node _T_256 = or(_T_255, _T_229)
node _T_257 = or(_T_256, _T_230)
node _T_258 = or(_T_257, _T_231)
node _T_259 = or(_T_258, _T_232)
node _T_260 = or(_T_259, _T_238)
node _T_261 = or(_T_260, _T_239)
node _T_262 = or(_T_261, _T_240)
node _T_263 = or(_T_262, _T_246)
node _T_264 = or(_T_263, _T_247)
node _T_265 = or(_T_264, _T_248)
node _T_266 = or(_T_265, _T_249)
node _T_267 = and(_T_201, _T_266)
node _T_268 = or(UInt<1>(0h0), _T_267)
node _T_269 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_270 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_271 = cvt(_T_270)
node _T_272 = and(_T_271, asSInt(UInt<13>(0h1000)))
node _T_273 = asSInt(_T_272)
node _T_274 = eq(_T_273, asSInt(UInt<1>(0h0)))
node _T_275 = and(_T_269, _T_274)
node _T_276 = or(UInt<1>(0h0), _T_275)
node _T_277 = and(_T_268, _T_276)
node _T_278 = asUInt(reset)
node _T_279 = eq(_T_278, UInt<1>(0h0))
when _T_279 :
node _T_280 = eq(_T_277, UInt<1>(0h0))
when _T_280 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_277, UInt<1>(0h1), "") : assert_2
node _T_281 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_282 = shr(io.in.a.bits.source, 2)
node _T_283 = eq(_T_282, UInt<1>(0h0))
node _T_284 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_285 = and(_T_283, _T_284)
node _T_286 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_287 = and(_T_285, _T_286)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_288 = shr(io.in.a.bits.source, 2)
node _T_289 = eq(_T_288, UInt<1>(0h1))
node _T_290 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_291 = and(_T_289, _T_290)
node _T_292 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_293 = and(_T_291, _T_292)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_294 = shr(io.in.a.bits.source, 2)
node _T_295 = eq(_T_294, UInt<2>(0h2))
node _T_296 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_297 = and(_T_295, _T_296)
node _T_298 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_299 = and(_T_297, _T_298)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_300 = shr(io.in.a.bits.source, 2)
node _T_301 = eq(_T_300, UInt<2>(0h3))
node _T_302 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_303 = and(_T_301, _T_302)
node _T_304 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_305 = and(_T_303, _T_304)
node _T_306 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_307 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_308 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_309 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_310 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_311 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 2, 0)
node _T_312 = shr(io.in.a.bits.source, 3)
node _T_313 = eq(_T_312, UInt<3>(0h6))
node _T_314 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_315 = and(_T_313, _T_314)
node _T_316 = leq(uncommonBits_16, UInt<3>(0h4))
node _T_317 = and(_T_315, _T_316)
node _T_318 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_319 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 2, 0)
node _T_320 = shr(io.in.a.bits.source, 3)
node _T_321 = eq(_T_320, UInt<3>(0h4))
node _T_322 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_323 = and(_T_321, _T_322)
node _T_324 = leq(uncommonBits_17, UInt<3>(0h4))
node _T_325 = and(_T_323, _T_324)
node _T_326 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_328 = eq(io.in.a.bits.source, UInt<8>(0h80))
wire _WIRE : UInt<1>[18]
connect _WIRE[0], _T_281
connect _WIRE[1], _T_287
connect _WIRE[2], _T_293
connect _WIRE[3], _T_299
connect _WIRE[4], _T_305
connect _WIRE[5], _T_306
connect _WIRE[6], _T_307
connect _WIRE[7], _T_308
connect _WIRE[8], _T_309
connect _WIRE[9], _T_310
connect _WIRE[10], _T_311
connect _WIRE[11], _T_317
connect _WIRE[12], _T_318
connect _WIRE[13], _T_319
connect _WIRE[14], _T_325
connect _WIRE[15], _T_326
connect _WIRE[16], _T_327
connect _WIRE[17], _T_328
node _T_329 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_330 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_331 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_332 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_333 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_334 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_335 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_336 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_337 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_338 = mux(_WIRE[5], _T_329, UInt<1>(0h0))
node _T_339 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_340 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_341 = mux(_WIRE[8], _T_330, UInt<1>(0h0))
node _T_342 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_343 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_344 = mux(_WIRE[11], _T_331, UInt<1>(0h0))
node _T_345 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_346 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0))
node _T_347 = mux(_WIRE[14], _T_332, UInt<1>(0h0))
node _T_348 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0))
node _T_349 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_350 = mux(_WIRE[17], UInt<1>(0h0), UInt<1>(0h0))
node _T_351 = or(_T_333, _T_334)
node _T_352 = or(_T_351, _T_335)
node _T_353 = or(_T_352, _T_336)
node _T_354 = or(_T_353, _T_337)
node _T_355 = or(_T_354, _T_338)
node _T_356 = or(_T_355, _T_339)
node _T_357 = or(_T_356, _T_340)
node _T_358 = or(_T_357, _T_341)
node _T_359 = or(_T_358, _T_342)
node _T_360 = or(_T_359, _T_343)
node _T_361 = or(_T_360, _T_344)
node _T_362 = or(_T_361, _T_345)
node _T_363 = or(_T_362, _T_346)
node _T_364 = or(_T_363, _T_347)
node _T_365 = or(_T_364, _T_348)
node _T_366 = or(_T_365, _T_349)
node _T_367 = or(_T_366, _T_350)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_367
node _T_368 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_369 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_370 = and(_T_368, _T_369)
node _T_371 = or(UInt<1>(0h0), _T_370)
node _T_372 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_373 = cvt(_T_372)
node _T_374 = and(_T_373, asSInt(UInt<13>(0h1000)))
node _T_375 = asSInt(_T_374)
node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0)))
node _T_377 = and(_T_371, _T_376)
node _T_378 = or(UInt<1>(0h0), _T_377)
node _T_379 = and(_WIRE_1, _T_378)
node _T_380 = asUInt(reset)
node _T_381 = eq(_T_380, UInt<1>(0h0))
when _T_381 :
node _T_382 = eq(_T_379, UInt<1>(0h0))
when _T_382 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_379, UInt<1>(0h1), "") : assert_3
node _T_383 = asUInt(reset)
node _T_384 = eq(_T_383, UInt<1>(0h0))
when _T_384 :
node _T_385 = eq(source_ok, UInt<1>(0h0))
when _T_385 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_386 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_387 = asUInt(reset)
node _T_388 = eq(_T_387, UInt<1>(0h0))
when _T_388 :
node _T_389 = eq(_T_386, UInt<1>(0h0))
when _T_389 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_386, UInt<1>(0h1), "") : assert_5
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(is_aligned, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_393 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_393, UInt<1>(0h1), "") : assert_7
node _T_397 = not(io.in.a.bits.mask)
node _T_398 = eq(_T_397, UInt<1>(0h0))
node _T_399 = asUInt(reset)
node _T_400 = eq(_T_399, UInt<1>(0h0))
when _T_400 :
node _T_401 = eq(_T_398, UInt<1>(0h0))
when _T_401 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_398, UInt<1>(0h1), "") : assert_8
node _T_402 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_403 = asUInt(reset)
node _T_404 = eq(_T_403, UInt<1>(0h0))
when _T_404 :
node _T_405 = eq(_T_402, UInt<1>(0h0))
when _T_405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_402, UInt<1>(0h1), "") : assert_9
node _T_406 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_406 :
node _T_407 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_408 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_409 = and(_T_407, _T_408)
node _T_410 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_411 = shr(io.in.a.bits.source, 2)
node _T_412 = eq(_T_411, UInt<1>(0h0))
node _T_413 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_414 = and(_T_412, _T_413)
node _T_415 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_416 = and(_T_414, _T_415)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_417 = shr(io.in.a.bits.source, 2)
node _T_418 = eq(_T_417, UInt<1>(0h1))
node _T_419 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_420 = and(_T_418, _T_419)
node _T_421 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_422 = and(_T_420, _T_421)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_423 = shr(io.in.a.bits.source, 2)
node _T_424 = eq(_T_423, UInt<2>(0h2))
node _T_425 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_426 = and(_T_424, _T_425)
node _T_427 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_428 = and(_T_426, _T_427)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_429 = shr(io.in.a.bits.source, 2)
node _T_430 = eq(_T_429, UInt<2>(0h3))
node _T_431 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_432 = and(_T_430, _T_431)
node _T_433 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_434 = and(_T_432, _T_433)
node _T_435 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_436 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_437 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_438 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_439 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_440 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 2, 0)
node _T_441 = shr(io.in.a.bits.source, 3)
node _T_442 = eq(_T_441, UInt<3>(0h6))
node _T_443 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_444 = and(_T_442, _T_443)
node _T_445 = leq(uncommonBits_22, UInt<3>(0h4))
node _T_446 = and(_T_444, _T_445)
node _T_447 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_448 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 2, 0)
node _T_449 = shr(io.in.a.bits.source, 3)
node _T_450 = eq(_T_449, UInt<3>(0h4))
node _T_451 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_452 = and(_T_450, _T_451)
node _T_453 = leq(uncommonBits_23, UInt<3>(0h4))
node _T_454 = and(_T_452, _T_453)
node _T_455 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_456 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_457 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_458 = or(_T_410, _T_416)
node _T_459 = or(_T_458, _T_422)
node _T_460 = or(_T_459, _T_428)
node _T_461 = or(_T_460, _T_434)
node _T_462 = or(_T_461, _T_435)
node _T_463 = or(_T_462, _T_436)
node _T_464 = or(_T_463, _T_437)
node _T_465 = or(_T_464, _T_438)
node _T_466 = or(_T_465, _T_439)
node _T_467 = or(_T_466, _T_440)
node _T_468 = or(_T_467, _T_446)
node _T_469 = or(_T_468, _T_447)
node _T_470 = or(_T_469, _T_448)
node _T_471 = or(_T_470, _T_454)
node _T_472 = or(_T_471, _T_455)
node _T_473 = or(_T_472, _T_456)
node _T_474 = or(_T_473, _T_457)
node _T_475 = and(_T_409, _T_474)
node _T_476 = or(UInt<1>(0h0), _T_475)
node _T_477 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_478 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_479 = cvt(_T_478)
node _T_480 = and(_T_479, asSInt(UInt<13>(0h1000)))
node _T_481 = asSInt(_T_480)
node _T_482 = eq(_T_481, asSInt(UInt<1>(0h0)))
node _T_483 = and(_T_477, _T_482)
node _T_484 = or(UInt<1>(0h0), _T_483)
node _T_485 = and(_T_476, _T_484)
node _T_486 = asUInt(reset)
node _T_487 = eq(_T_486, UInt<1>(0h0))
when _T_487 :
node _T_488 = eq(_T_485, UInt<1>(0h0))
when _T_488 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_485, UInt<1>(0h1), "") : assert_10
node _T_489 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_490 = shr(io.in.a.bits.source, 2)
node _T_491 = eq(_T_490, UInt<1>(0h0))
node _T_492 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_493 = and(_T_491, _T_492)
node _T_494 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_495 = and(_T_493, _T_494)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_496 = shr(io.in.a.bits.source, 2)
node _T_497 = eq(_T_496, UInt<1>(0h1))
node _T_498 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_499 = and(_T_497, _T_498)
node _T_500 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_501 = and(_T_499, _T_500)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_502 = shr(io.in.a.bits.source, 2)
node _T_503 = eq(_T_502, UInt<2>(0h2))
node _T_504 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_505 = and(_T_503, _T_504)
node _T_506 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_507 = and(_T_505, _T_506)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_508 = shr(io.in.a.bits.source, 2)
node _T_509 = eq(_T_508, UInt<2>(0h3))
node _T_510 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_511 = and(_T_509, _T_510)
node _T_512 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_513 = and(_T_511, _T_512)
node _T_514 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_515 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_516 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_517 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_518 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_519 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 2, 0)
node _T_520 = shr(io.in.a.bits.source, 3)
node _T_521 = eq(_T_520, UInt<3>(0h6))
node _T_522 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_523 = and(_T_521, _T_522)
node _T_524 = leq(uncommonBits_28, UInt<3>(0h4))
node _T_525 = and(_T_523, _T_524)
node _T_526 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_527 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 2, 0)
node _T_528 = shr(io.in.a.bits.source, 3)
node _T_529 = eq(_T_528, UInt<3>(0h4))
node _T_530 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_531 = and(_T_529, _T_530)
node _T_532 = leq(uncommonBits_29, UInt<3>(0h4))
node _T_533 = and(_T_531, _T_532)
node _T_534 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_535 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_536 = eq(io.in.a.bits.source, UInt<8>(0h80))
wire _WIRE_2 : UInt<1>[18]
connect _WIRE_2[0], _T_489
connect _WIRE_2[1], _T_495
connect _WIRE_2[2], _T_501
connect _WIRE_2[3], _T_507
connect _WIRE_2[4], _T_513
connect _WIRE_2[5], _T_514
connect _WIRE_2[6], _T_515
connect _WIRE_2[7], _T_516
connect _WIRE_2[8], _T_517
connect _WIRE_2[9], _T_518
connect _WIRE_2[10], _T_519
connect _WIRE_2[11], _T_525
connect _WIRE_2[12], _T_526
connect _WIRE_2[13], _T_527
connect _WIRE_2[14], _T_533
connect _WIRE_2[15], _T_534
connect _WIRE_2[16], _T_535
connect _WIRE_2[17], _T_536
node _T_537 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_538 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_539 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_540 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_541 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_542 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_543 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_544 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_545 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_546 = mux(_WIRE_2[5], _T_537, UInt<1>(0h0))
node _T_547 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_548 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_549 = mux(_WIRE_2[8], _T_538, UInt<1>(0h0))
node _T_550 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_551 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_552 = mux(_WIRE_2[11], _T_539, UInt<1>(0h0))
node _T_553 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_554 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0))
node _T_555 = mux(_WIRE_2[14], _T_540, UInt<1>(0h0))
node _T_556 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0))
node _T_557 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_558 = mux(_WIRE_2[17], UInt<1>(0h0), UInt<1>(0h0))
node _T_559 = or(_T_541, _T_542)
node _T_560 = or(_T_559, _T_543)
node _T_561 = or(_T_560, _T_544)
node _T_562 = or(_T_561, _T_545)
node _T_563 = or(_T_562, _T_546)
node _T_564 = or(_T_563, _T_547)
node _T_565 = or(_T_564, _T_548)
node _T_566 = or(_T_565, _T_549)
node _T_567 = or(_T_566, _T_550)
node _T_568 = or(_T_567, _T_551)
node _T_569 = or(_T_568, _T_552)
node _T_570 = or(_T_569, _T_553)
node _T_571 = or(_T_570, _T_554)
node _T_572 = or(_T_571, _T_555)
node _T_573 = or(_T_572, _T_556)
node _T_574 = or(_T_573, _T_557)
node _T_575 = or(_T_574, _T_558)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_575
node _T_576 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_577 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_578 = and(_T_576, _T_577)
node _T_579 = or(UInt<1>(0h0), _T_578)
node _T_580 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_581 = cvt(_T_580)
node _T_582 = and(_T_581, asSInt(UInt<13>(0h1000)))
node _T_583 = asSInt(_T_582)
node _T_584 = eq(_T_583, asSInt(UInt<1>(0h0)))
node _T_585 = and(_T_579, _T_584)
node _T_586 = or(UInt<1>(0h0), _T_585)
node _T_587 = and(_WIRE_3, _T_586)
node _T_588 = asUInt(reset)
node _T_589 = eq(_T_588, UInt<1>(0h0))
when _T_589 :
node _T_590 = eq(_T_587, UInt<1>(0h0))
when _T_590 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_587, UInt<1>(0h1), "") : assert_11
node _T_591 = asUInt(reset)
node _T_592 = eq(_T_591, UInt<1>(0h0))
when _T_592 :
node _T_593 = eq(source_ok, UInt<1>(0h0))
when _T_593 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_594 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_595 = asUInt(reset)
node _T_596 = eq(_T_595, UInt<1>(0h0))
when _T_596 :
node _T_597 = eq(_T_594, UInt<1>(0h0))
when _T_597 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_594, UInt<1>(0h1), "") : assert_13
node _T_598 = asUInt(reset)
node _T_599 = eq(_T_598, UInt<1>(0h0))
when _T_599 :
node _T_600 = eq(is_aligned, UInt<1>(0h0))
when _T_600 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_601 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_601, UInt<1>(0h1), "") : assert_15
node _T_605 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_606 = asUInt(reset)
node _T_607 = eq(_T_606, UInt<1>(0h0))
when _T_607 :
node _T_608 = eq(_T_605, UInt<1>(0h0))
when _T_608 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_605, UInt<1>(0h1), "") : assert_16
node _T_609 = not(io.in.a.bits.mask)
node _T_610 = eq(_T_609, UInt<1>(0h0))
node _T_611 = asUInt(reset)
node _T_612 = eq(_T_611, UInt<1>(0h0))
when _T_612 :
node _T_613 = eq(_T_610, UInt<1>(0h0))
when _T_613 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_610, UInt<1>(0h1), "") : assert_17
node _T_614 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_615 = asUInt(reset)
node _T_616 = eq(_T_615, UInt<1>(0h0))
when _T_616 :
node _T_617 = eq(_T_614, UInt<1>(0h0))
when _T_617 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_614, UInt<1>(0h1), "") : assert_18
node _T_618 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_618 :
node _T_619 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_620 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_621 = and(_T_619, _T_620)
node _T_622 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_623 = shr(io.in.a.bits.source, 2)
node _T_624 = eq(_T_623, UInt<1>(0h0))
node _T_625 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_626 = and(_T_624, _T_625)
node _T_627 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_628 = and(_T_626, _T_627)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_629 = shr(io.in.a.bits.source, 2)
node _T_630 = eq(_T_629, UInt<1>(0h1))
node _T_631 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_632 = and(_T_630, _T_631)
node _T_633 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_634 = and(_T_632, _T_633)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_635 = shr(io.in.a.bits.source, 2)
node _T_636 = eq(_T_635, UInt<2>(0h2))
node _T_637 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_638 = and(_T_636, _T_637)
node _T_639 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_640 = and(_T_638, _T_639)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_641 = shr(io.in.a.bits.source, 2)
node _T_642 = eq(_T_641, UInt<2>(0h3))
node _T_643 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_644 = and(_T_642, _T_643)
node _T_645 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_646 = and(_T_644, _T_645)
node _T_647 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_648 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_649 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_650 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_651 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_652 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0)
node _T_653 = shr(io.in.a.bits.source, 3)
node _T_654 = eq(_T_653, UInt<3>(0h6))
node _T_655 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_656 = and(_T_654, _T_655)
node _T_657 = leq(uncommonBits_34, UInt<3>(0h4))
node _T_658 = and(_T_656, _T_657)
node _T_659 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_660 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 2, 0)
node _T_661 = shr(io.in.a.bits.source, 3)
node _T_662 = eq(_T_661, UInt<3>(0h4))
node _T_663 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_664 = and(_T_662, _T_663)
node _T_665 = leq(uncommonBits_35, UInt<3>(0h4))
node _T_666 = and(_T_664, _T_665)
node _T_667 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_668 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_669 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_670 = or(_T_622, _T_628)
node _T_671 = or(_T_670, _T_634)
node _T_672 = or(_T_671, _T_640)
node _T_673 = or(_T_672, _T_646)
node _T_674 = or(_T_673, _T_647)
node _T_675 = or(_T_674, _T_648)
node _T_676 = or(_T_675, _T_649)
node _T_677 = or(_T_676, _T_650)
node _T_678 = or(_T_677, _T_651)
node _T_679 = or(_T_678, _T_652)
node _T_680 = or(_T_679, _T_658)
node _T_681 = or(_T_680, _T_659)
node _T_682 = or(_T_681, _T_660)
node _T_683 = or(_T_682, _T_666)
node _T_684 = or(_T_683, _T_667)
node _T_685 = or(_T_684, _T_668)
node _T_686 = or(_T_685, _T_669)
node _T_687 = and(_T_621, _T_686)
node _T_688 = or(UInt<1>(0h0), _T_687)
node _T_689 = asUInt(reset)
node _T_690 = eq(_T_689, UInt<1>(0h0))
when _T_690 :
node _T_691 = eq(_T_688, UInt<1>(0h0))
when _T_691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_688, UInt<1>(0h1), "") : assert_19
node _T_692 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_693 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_694 = and(_T_692, _T_693)
node _T_695 = or(UInt<1>(0h0), _T_694)
node _T_696 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_697 = cvt(_T_696)
node _T_698 = and(_T_697, asSInt(UInt<13>(0h1000)))
node _T_699 = asSInt(_T_698)
node _T_700 = eq(_T_699, asSInt(UInt<1>(0h0)))
node _T_701 = and(_T_695, _T_700)
node _T_702 = or(UInt<1>(0h0), _T_701)
node _T_703 = asUInt(reset)
node _T_704 = eq(_T_703, UInt<1>(0h0))
when _T_704 :
node _T_705 = eq(_T_702, UInt<1>(0h0))
when _T_705 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_702, UInt<1>(0h1), "") : assert_20
node _T_706 = asUInt(reset)
node _T_707 = eq(_T_706, UInt<1>(0h0))
when _T_707 :
node _T_708 = eq(source_ok, UInt<1>(0h0))
when _T_708 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_709 = asUInt(reset)
node _T_710 = eq(_T_709, UInt<1>(0h0))
when _T_710 :
node _T_711 = eq(is_aligned, UInt<1>(0h0))
when _T_711 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_712 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_712, UInt<1>(0h1), "") : assert_23
node _T_716 = eq(io.in.a.bits.mask, mask)
node _T_717 = asUInt(reset)
node _T_718 = eq(_T_717, UInt<1>(0h0))
when _T_718 :
node _T_719 = eq(_T_716, UInt<1>(0h0))
when _T_719 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_716, UInt<1>(0h1), "") : assert_24
node _T_720 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_721 = asUInt(reset)
node _T_722 = eq(_T_721, UInt<1>(0h0))
when _T_722 :
node _T_723 = eq(_T_720, UInt<1>(0h0))
when _T_723 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_720, UInt<1>(0h1), "") : assert_25
node _T_724 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_724 :
node _T_725 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_726 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_727 = and(_T_725, _T_726)
node _T_728 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_729 = shr(io.in.a.bits.source, 2)
node _T_730 = eq(_T_729, UInt<1>(0h0))
node _T_731 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_732 = and(_T_730, _T_731)
node _T_733 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_734 = and(_T_732, _T_733)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_735 = shr(io.in.a.bits.source, 2)
node _T_736 = eq(_T_735, UInt<1>(0h1))
node _T_737 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_738 = and(_T_736, _T_737)
node _T_739 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_740 = and(_T_738, _T_739)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_741 = shr(io.in.a.bits.source, 2)
node _T_742 = eq(_T_741, UInt<2>(0h2))
node _T_743 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_744 = and(_T_742, _T_743)
node _T_745 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_746 = and(_T_744, _T_745)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_747 = shr(io.in.a.bits.source, 2)
node _T_748 = eq(_T_747, UInt<2>(0h3))
node _T_749 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_750 = and(_T_748, _T_749)
node _T_751 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_752 = and(_T_750, _T_751)
node _T_753 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_754 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_755 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_756 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_757 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_758 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 2, 0)
node _T_759 = shr(io.in.a.bits.source, 3)
node _T_760 = eq(_T_759, UInt<3>(0h6))
node _T_761 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_762 = and(_T_760, _T_761)
node _T_763 = leq(uncommonBits_40, UInt<3>(0h4))
node _T_764 = and(_T_762, _T_763)
node _T_765 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_766 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 2, 0)
node _T_767 = shr(io.in.a.bits.source, 3)
node _T_768 = eq(_T_767, UInt<3>(0h4))
node _T_769 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_770 = and(_T_768, _T_769)
node _T_771 = leq(uncommonBits_41, UInt<3>(0h4))
node _T_772 = and(_T_770, _T_771)
node _T_773 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_774 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_775 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_776 = or(_T_728, _T_734)
node _T_777 = or(_T_776, _T_740)
node _T_778 = or(_T_777, _T_746)
node _T_779 = or(_T_778, _T_752)
node _T_780 = or(_T_779, _T_753)
node _T_781 = or(_T_780, _T_754)
node _T_782 = or(_T_781, _T_755)
node _T_783 = or(_T_782, _T_756)
node _T_784 = or(_T_783, _T_757)
node _T_785 = or(_T_784, _T_758)
node _T_786 = or(_T_785, _T_764)
node _T_787 = or(_T_786, _T_765)
node _T_788 = or(_T_787, _T_766)
node _T_789 = or(_T_788, _T_772)
node _T_790 = or(_T_789, _T_773)
node _T_791 = or(_T_790, _T_774)
node _T_792 = or(_T_791, _T_775)
node _T_793 = and(_T_727, _T_792)
node _T_794 = or(UInt<1>(0h0), _T_793)
node _T_795 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_796 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_797 = and(_T_795, _T_796)
node _T_798 = or(UInt<1>(0h0), _T_797)
node _T_799 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_800 = cvt(_T_799)
node _T_801 = and(_T_800, asSInt(UInt<13>(0h1000)))
node _T_802 = asSInt(_T_801)
node _T_803 = eq(_T_802, asSInt(UInt<1>(0h0)))
node _T_804 = and(_T_798, _T_803)
node _T_805 = or(UInt<1>(0h0), _T_804)
node _T_806 = and(_T_794, _T_805)
node _T_807 = asUInt(reset)
node _T_808 = eq(_T_807, UInt<1>(0h0))
when _T_808 :
node _T_809 = eq(_T_806, UInt<1>(0h0))
when _T_809 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_806, UInt<1>(0h1), "") : assert_26
node _T_810 = asUInt(reset)
node _T_811 = eq(_T_810, UInt<1>(0h0))
when _T_811 :
node _T_812 = eq(source_ok, UInt<1>(0h0))
when _T_812 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_813 = asUInt(reset)
node _T_814 = eq(_T_813, UInt<1>(0h0))
when _T_814 :
node _T_815 = eq(is_aligned, UInt<1>(0h0))
when _T_815 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_816 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_817 = asUInt(reset)
node _T_818 = eq(_T_817, UInt<1>(0h0))
when _T_818 :
node _T_819 = eq(_T_816, UInt<1>(0h0))
when _T_819 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_816, UInt<1>(0h1), "") : assert_29
node _T_820 = eq(io.in.a.bits.mask, mask)
node _T_821 = asUInt(reset)
node _T_822 = eq(_T_821, UInt<1>(0h0))
when _T_822 :
node _T_823 = eq(_T_820, UInt<1>(0h0))
when _T_823 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_820, UInt<1>(0h1), "") : assert_30
node _T_824 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_824 :
node _T_825 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_826 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_827 = and(_T_825, _T_826)
node _T_828 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_829 = shr(io.in.a.bits.source, 2)
node _T_830 = eq(_T_829, UInt<1>(0h0))
node _T_831 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_832 = and(_T_830, _T_831)
node _T_833 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_834 = and(_T_832, _T_833)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_835 = shr(io.in.a.bits.source, 2)
node _T_836 = eq(_T_835, UInt<1>(0h1))
node _T_837 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_838 = and(_T_836, _T_837)
node _T_839 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_840 = and(_T_838, _T_839)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_841 = shr(io.in.a.bits.source, 2)
node _T_842 = eq(_T_841, UInt<2>(0h2))
node _T_843 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_844 = and(_T_842, _T_843)
node _T_845 = leq(uncommonBits_44, UInt<2>(0h3))
node _T_846 = and(_T_844, _T_845)
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_847 = shr(io.in.a.bits.source, 2)
node _T_848 = eq(_T_847, UInt<2>(0h3))
node _T_849 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_850 = and(_T_848, _T_849)
node _T_851 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_852 = and(_T_850, _T_851)
node _T_853 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_854 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_855 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_856 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_857 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_858 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 2, 0)
node _T_859 = shr(io.in.a.bits.source, 3)
node _T_860 = eq(_T_859, UInt<3>(0h6))
node _T_861 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_862 = and(_T_860, _T_861)
node _T_863 = leq(uncommonBits_46, UInt<3>(0h4))
node _T_864 = and(_T_862, _T_863)
node _T_865 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_866 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 2, 0)
node _T_867 = shr(io.in.a.bits.source, 3)
node _T_868 = eq(_T_867, UInt<3>(0h4))
node _T_869 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_870 = and(_T_868, _T_869)
node _T_871 = leq(uncommonBits_47, UInt<3>(0h4))
node _T_872 = and(_T_870, _T_871)
node _T_873 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_874 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_875 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_876 = or(_T_828, _T_834)
node _T_877 = or(_T_876, _T_840)
node _T_878 = or(_T_877, _T_846)
node _T_879 = or(_T_878, _T_852)
node _T_880 = or(_T_879, _T_853)
node _T_881 = or(_T_880, _T_854)
node _T_882 = or(_T_881, _T_855)
node _T_883 = or(_T_882, _T_856)
node _T_884 = or(_T_883, _T_857)
node _T_885 = or(_T_884, _T_858)
node _T_886 = or(_T_885, _T_864)
node _T_887 = or(_T_886, _T_865)
node _T_888 = or(_T_887, _T_866)
node _T_889 = or(_T_888, _T_872)
node _T_890 = or(_T_889, _T_873)
node _T_891 = or(_T_890, _T_874)
node _T_892 = or(_T_891, _T_875)
node _T_893 = and(_T_827, _T_892)
node _T_894 = or(UInt<1>(0h0), _T_893)
node _T_895 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_896 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_897 = and(_T_895, _T_896)
node _T_898 = or(UInt<1>(0h0), _T_897)
node _T_899 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_900 = cvt(_T_899)
node _T_901 = and(_T_900, asSInt(UInt<13>(0h1000)))
node _T_902 = asSInt(_T_901)
node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0)))
node _T_904 = and(_T_898, _T_903)
node _T_905 = or(UInt<1>(0h0), _T_904)
node _T_906 = and(_T_894, _T_905)
node _T_907 = asUInt(reset)
node _T_908 = eq(_T_907, UInt<1>(0h0))
when _T_908 :
node _T_909 = eq(_T_906, UInt<1>(0h0))
when _T_909 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_906, UInt<1>(0h1), "") : assert_31
node _T_910 = asUInt(reset)
node _T_911 = eq(_T_910, UInt<1>(0h0))
when _T_911 :
node _T_912 = eq(source_ok, UInt<1>(0h0))
when _T_912 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_913 = asUInt(reset)
node _T_914 = eq(_T_913, UInt<1>(0h0))
when _T_914 :
node _T_915 = eq(is_aligned, UInt<1>(0h0))
when _T_915 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_916 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_917 = asUInt(reset)
node _T_918 = eq(_T_917, UInt<1>(0h0))
when _T_918 :
node _T_919 = eq(_T_916, UInt<1>(0h0))
when _T_919 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_916, UInt<1>(0h1), "") : assert_34
node _T_920 = not(mask)
node _T_921 = and(io.in.a.bits.mask, _T_920)
node _T_922 = eq(_T_921, UInt<1>(0h0))
node _T_923 = asUInt(reset)
node _T_924 = eq(_T_923, UInt<1>(0h0))
when _T_924 :
node _T_925 = eq(_T_922, UInt<1>(0h0))
when _T_925 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_922, UInt<1>(0h1), "") : assert_35
node _T_926 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_926 :
node _T_927 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_928 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_929 = and(_T_927, _T_928)
node _T_930 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0)
node _T_931 = shr(io.in.a.bits.source, 2)
node _T_932 = eq(_T_931, UInt<1>(0h0))
node _T_933 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_934 = and(_T_932, _T_933)
node _T_935 = leq(uncommonBits_48, UInt<2>(0h3))
node _T_936 = and(_T_934, _T_935)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0)
node _T_937 = shr(io.in.a.bits.source, 2)
node _T_938 = eq(_T_937, UInt<1>(0h1))
node _T_939 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_940 = and(_T_938, _T_939)
node _T_941 = leq(uncommonBits_49, UInt<2>(0h3))
node _T_942 = and(_T_940, _T_941)
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_943 = shr(io.in.a.bits.source, 2)
node _T_944 = eq(_T_943, UInt<2>(0h2))
node _T_945 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_946 = and(_T_944, _T_945)
node _T_947 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_948 = and(_T_946, _T_947)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_949 = shr(io.in.a.bits.source, 2)
node _T_950 = eq(_T_949, UInt<2>(0h3))
node _T_951 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_952 = and(_T_950, _T_951)
node _T_953 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_954 = and(_T_952, _T_953)
node _T_955 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_956 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_957 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_958 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_959 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_960 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 2, 0)
node _T_961 = shr(io.in.a.bits.source, 3)
node _T_962 = eq(_T_961, UInt<3>(0h6))
node _T_963 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_964 = and(_T_962, _T_963)
node _T_965 = leq(uncommonBits_52, UInt<3>(0h4))
node _T_966 = and(_T_964, _T_965)
node _T_967 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_968 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 2, 0)
node _T_969 = shr(io.in.a.bits.source, 3)
node _T_970 = eq(_T_969, UInt<3>(0h4))
node _T_971 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_972 = and(_T_970, _T_971)
node _T_973 = leq(uncommonBits_53, UInt<3>(0h4))
node _T_974 = and(_T_972, _T_973)
node _T_975 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_976 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_977 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_978 = or(_T_930, _T_936)
node _T_979 = or(_T_978, _T_942)
node _T_980 = or(_T_979, _T_948)
node _T_981 = or(_T_980, _T_954)
node _T_982 = or(_T_981, _T_955)
node _T_983 = or(_T_982, _T_956)
node _T_984 = or(_T_983, _T_957)
node _T_985 = or(_T_984, _T_958)
node _T_986 = or(_T_985, _T_959)
node _T_987 = or(_T_986, _T_960)
node _T_988 = or(_T_987, _T_966)
node _T_989 = or(_T_988, _T_967)
node _T_990 = or(_T_989, _T_968)
node _T_991 = or(_T_990, _T_974)
node _T_992 = or(_T_991, _T_975)
node _T_993 = or(_T_992, _T_976)
node _T_994 = or(_T_993, _T_977)
node _T_995 = and(_T_929, _T_994)
node _T_996 = or(UInt<1>(0h0), _T_995)
node _T_997 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_998 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_999 = cvt(_T_998)
node _T_1000 = and(_T_999, asSInt(UInt<13>(0h1000)))
node _T_1001 = asSInt(_T_1000)
node _T_1002 = eq(_T_1001, asSInt(UInt<1>(0h0)))
node _T_1003 = and(_T_997, _T_1002)
node _T_1004 = or(UInt<1>(0h0), _T_1003)
node _T_1005 = and(_T_996, _T_1004)
node _T_1006 = asUInt(reset)
node _T_1007 = eq(_T_1006, UInt<1>(0h0))
when _T_1007 :
node _T_1008 = eq(_T_1005, UInt<1>(0h0))
when _T_1008 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_1005, UInt<1>(0h1), "") : assert_36
node _T_1009 = asUInt(reset)
node _T_1010 = eq(_T_1009, UInt<1>(0h0))
when _T_1010 :
node _T_1011 = eq(source_ok, UInt<1>(0h0))
when _T_1011 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_1012 = asUInt(reset)
node _T_1013 = eq(_T_1012, UInt<1>(0h0))
when _T_1013 :
node _T_1014 = eq(is_aligned, UInt<1>(0h0))
when _T_1014 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_1015 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_1016 = asUInt(reset)
node _T_1017 = eq(_T_1016, UInt<1>(0h0))
when _T_1017 :
node _T_1018 = eq(_T_1015, UInt<1>(0h0))
when _T_1018 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_1015, UInt<1>(0h1), "") : assert_39
node _T_1019 = eq(io.in.a.bits.mask, mask)
node _T_1020 = asUInt(reset)
node _T_1021 = eq(_T_1020, UInt<1>(0h0))
when _T_1021 :
node _T_1022 = eq(_T_1019, UInt<1>(0h0))
when _T_1022 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_1019, UInt<1>(0h1), "") : assert_40
node _T_1023 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_1023 :
node _T_1024 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1025 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1026 = and(_T_1024, _T_1025)
node _T_1027 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0)
node _T_1028 = shr(io.in.a.bits.source, 2)
node _T_1029 = eq(_T_1028, UInt<1>(0h0))
node _T_1030 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_1031 = and(_T_1029, _T_1030)
node _T_1032 = leq(uncommonBits_54, UInt<2>(0h3))
node _T_1033 = and(_T_1031, _T_1032)
node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0)
node _T_1034 = shr(io.in.a.bits.source, 2)
node _T_1035 = eq(_T_1034, UInt<1>(0h1))
node _T_1036 = leq(UInt<1>(0h0), uncommonBits_55)
node _T_1037 = and(_T_1035, _T_1036)
node _T_1038 = leq(uncommonBits_55, UInt<2>(0h3))
node _T_1039 = and(_T_1037, _T_1038)
node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0)
node _T_1040 = shr(io.in.a.bits.source, 2)
node _T_1041 = eq(_T_1040, UInt<2>(0h2))
node _T_1042 = leq(UInt<1>(0h0), uncommonBits_56)
node _T_1043 = and(_T_1041, _T_1042)
node _T_1044 = leq(uncommonBits_56, UInt<2>(0h3))
node _T_1045 = and(_T_1043, _T_1044)
node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0)
node _T_1046 = shr(io.in.a.bits.source, 2)
node _T_1047 = eq(_T_1046, UInt<2>(0h3))
node _T_1048 = leq(UInt<1>(0h0), uncommonBits_57)
node _T_1049 = and(_T_1047, _T_1048)
node _T_1050 = leq(uncommonBits_57, UInt<2>(0h3))
node _T_1051 = and(_T_1049, _T_1050)
node _T_1052 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_1053 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_1054 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_1055 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1056 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_1057 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_58 = bits(_uncommonBits_T_58, 2, 0)
node _T_1058 = shr(io.in.a.bits.source, 3)
node _T_1059 = eq(_T_1058, UInt<3>(0h6))
node _T_1060 = leq(UInt<1>(0h0), uncommonBits_58)
node _T_1061 = and(_T_1059, _T_1060)
node _T_1062 = leq(uncommonBits_58, UInt<3>(0h4))
node _T_1063 = and(_T_1061, _T_1062)
node _T_1064 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_1065 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_59 = bits(_uncommonBits_T_59, 2, 0)
node _T_1066 = shr(io.in.a.bits.source, 3)
node _T_1067 = eq(_T_1066, UInt<3>(0h4))
node _T_1068 = leq(UInt<1>(0h0), uncommonBits_59)
node _T_1069 = and(_T_1067, _T_1068)
node _T_1070 = leq(uncommonBits_59, UInt<3>(0h4))
node _T_1071 = and(_T_1069, _T_1070)
node _T_1072 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1073 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1074 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_1075 = or(_T_1027, _T_1033)
node _T_1076 = or(_T_1075, _T_1039)
node _T_1077 = or(_T_1076, _T_1045)
node _T_1078 = or(_T_1077, _T_1051)
node _T_1079 = or(_T_1078, _T_1052)
node _T_1080 = or(_T_1079, _T_1053)
node _T_1081 = or(_T_1080, _T_1054)
node _T_1082 = or(_T_1081, _T_1055)
node _T_1083 = or(_T_1082, _T_1056)
node _T_1084 = or(_T_1083, _T_1057)
node _T_1085 = or(_T_1084, _T_1063)
node _T_1086 = or(_T_1085, _T_1064)
node _T_1087 = or(_T_1086, _T_1065)
node _T_1088 = or(_T_1087, _T_1071)
node _T_1089 = or(_T_1088, _T_1072)
node _T_1090 = or(_T_1089, _T_1073)
node _T_1091 = or(_T_1090, _T_1074)
node _T_1092 = and(_T_1026, _T_1091)
node _T_1093 = or(UInt<1>(0h0), _T_1092)
node _T_1094 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1095 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1096 = cvt(_T_1095)
node _T_1097 = and(_T_1096, asSInt(UInt<13>(0h1000)))
node _T_1098 = asSInt(_T_1097)
node _T_1099 = eq(_T_1098, asSInt(UInt<1>(0h0)))
node _T_1100 = and(_T_1094, _T_1099)
node _T_1101 = or(UInt<1>(0h0), _T_1100)
node _T_1102 = and(_T_1093, _T_1101)
node _T_1103 = asUInt(reset)
node _T_1104 = eq(_T_1103, UInt<1>(0h0))
when _T_1104 :
node _T_1105 = eq(_T_1102, UInt<1>(0h0))
when _T_1105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1102, UInt<1>(0h1), "") : assert_41
node _T_1106 = asUInt(reset)
node _T_1107 = eq(_T_1106, UInt<1>(0h0))
when _T_1107 :
node _T_1108 = eq(source_ok, UInt<1>(0h0))
when _T_1108 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1109 = asUInt(reset)
node _T_1110 = eq(_T_1109, UInt<1>(0h0))
when _T_1110 :
node _T_1111 = eq(is_aligned, UInt<1>(0h0))
when _T_1111 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1112 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1113 = asUInt(reset)
node _T_1114 = eq(_T_1113, UInt<1>(0h0))
when _T_1114 :
node _T_1115 = eq(_T_1112, UInt<1>(0h0))
when _T_1115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1112, UInt<1>(0h1), "") : assert_44
node _T_1116 = eq(io.in.a.bits.mask, mask)
node _T_1117 = asUInt(reset)
node _T_1118 = eq(_T_1117, UInt<1>(0h0))
when _T_1118 :
node _T_1119 = eq(_T_1116, UInt<1>(0h0))
when _T_1119 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1116, UInt<1>(0h1), "") : assert_45
node _T_1120 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1120 :
node _T_1121 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1122 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1123 = and(_T_1121, _T_1122)
node _T_1124 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0)
node _T_1125 = shr(io.in.a.bits.source, 2)
node _T_1126 = eq(_T_1125, UInt<1>(0h0))
node _T_1127 = leq(UInt<1>(0h0), uncommonBits_60)
node _T_1128 = and(_T_1126, _T_1127)
node _T_1129 = leq(uncommonBits_60, UInt<2>(0h3))
node _T_1130 = and(_T_1128, _T_1129)
node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0)
node _T_1131 = shr(io.in.a.bits.source, 2)
node _T_1132 = eq(_T_1131, UInt<1>(0h1))
node _T_1133 = leq(UInt<1>(0h0), uncommonBits_61)
node _T_1134 = and(_T_1132, _T_1133)
node _T_1135 = leq(uncommonBits_61, UInt<2>(0h3))
node _T_1136 = and(_T_1134, _T_1135)
node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0)
node _T_1137 = shr(io.in.a.bits.source, 2)
node _T_1138 = eq(_T_1137, UInt<2>(0h2))
node _T_1139 = leq(UInt<1>(0h0), uncommonBits_62)
node _T_1140 = and(_T_1138, _T_1139)
node _T_1141 = leq(uncommonBits_62, UInt<2>(0h3))
node _T_1142 = and(_T_1140, _T_1141)
node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0)
node _T_1143 = shr(io.in.a.bits.source, 2)
node _T_1144 = eq(_T_1143, UInt<2>(0h3))
node _T_1145 = leq(UInt<1>(0h0), uncommonBits_63)
node _T_1146 = and(_T_1144, _T_1145)
node _T_1147 = leq(uncommonBits_63, UInt<2>(0h3))
node _T_1148 = and(_T_1146, _T_1147)
node _T_1149 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_1150 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_1151 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_1152 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1153 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_1154 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_64 = bits(_uncommonBits_T_64, 2, 0)
node _T_1155 = shr(io.in.a.bits.source, 3)
node _T_1156 = eq(_T_1155, UInt<3>(0h6))
node _T_1157 = leq(UInt<1>(0h0), uncommonBits_64)
node _T_1158 = and(_T_1156, _T_1157)
node _T_1159 = leq(uncommonBits_64, UInt<3>(0h4))
node _T_1160 = and(_T_1158, _T_1159)
node _T_1161 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_1162 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_65 = bits(_uncommonBits_T_65, 2, 0)
node _T_1163 = shr(io.in.a.bits.source, 3)
node _T_1164 = eq(_T_1163, UInt<3>(0h4))
node _T_1165 = leq(UInt<1>(0h0), uncommonBits_65)
node _T_1166 = and(_T_1164, _T_1165)
node _T_1167 = leq(uncommonBits_65, UInt<3>(0h4))
node _T_1168 = and(_T_1166, _T_1167)
node _T_1169 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1170 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1171 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_1172 = or(_T_1124, _T_1130)
node _T_1173 = or(_T_1172, _T_1136)
node _T_1174 = or(_T_1173, _T_1142)
node _T_1175 = or(_T_1174, _T_1148)
node _T_1176 = or(_T_1175, _T_1149)
node _T_1177 = or(_T_1176, _T_1150)
node _T_1178 = or(_T_1177, _T_1151)
node _T_1179 = or(_T_1178, _T_1152)
node _T_1180 = or(_T_1179, _T_1153)
node _T_1181 = or(_T_1180, _T_1154)
node _T_1182 = or(_T_1181, _T_1160)
node _T_1183 = or(_T_1182, _T_1161)
node _T_1184 = or(_T_1183, _T_1162)
node _T_1185 = or(_T_1184, _T_1168)
node _T_1186 = or(_T_1185, _T_1169)
node _T_1187 = or(_T_1186, _T_1170)
node _T_1188 = or(_T_1187, _T_1171)
node _T_1189 = and(_T_1123, _T_1188)
node _T_1190 = or(UInt<1>(0h0), _T_1189)
node _T_1191 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1192 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1193 = cvt(_T_1192)
node _T_1194 = and(_T_1193, asSInt(UInt<13>(0h1000)))
node _T_1195 = asSInt(_T_1194)
node _T_1196 = eq(_T_1195, asSInt(UInt<1>(0h0)))
node _T_1197 = and(_T_1191, _T_1196)
node _T_1198 = or(UInt<1>(0h0), _T_1197)
node _T_1199 = and(_T_1190, _T_1198)
node _T_1200 = asUInt(reset)
node _T_1201 = eq(_T_1200, UInt<1>(0h0))
when _T_1201 :
node _T_1202 = eq(_T_1199, UInt<1>(0h0))
when _T_1202 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1199, UInt<1>(0h1), "") : assert_46
node _T_1203 = asUInt(reset)
node _T_1204 = eq(_T_1203, UInt<1>(0h0))
when _T_1204 :
node _T_1205 = eq(source_ok, UInt<1>(0h0))
when _T_1205 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1206 = asUInt(reset)
node _T_1207 = eq(_T_1206, UInt<1>(0h0))
when _T_1207 :
node _T_1208 = eq(is_aligned, UInt<1>(0h0))
when _T_1208 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1209 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1210 = asUInt(reset)
node _T_1211 = eq(_T_1210, UInt<1>(0h0))
when _T_1211 :
node _T_1212 = eq(_T_1209, UInt<1>(0h0))
when _T_1212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1209, UInt<1>(0h1), "") : assert_49
node _T_1213 = eq(io.in.a.bits.mask, mask)
node _T_1214 = asUInt(reset)
node _T_1215 = eq(_T_1214, UInt<1>(0h0))
when _T_1215 :
node _T_1216 = eq(_T_1213, UInt<1>(0h0))
when _T_1216 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1213, UInt<1>(0h1), "") : assert_50
node _T_1217 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1218 = asUInt(reset)
node _T_1219 = eq(_T_1218, UInt<1>(0h0))
when _T_1219 :
node _T_1220 = eq(_T_1217, UInt<1>(0h0))
when _T_1220 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1217, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1221 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1222 = asUInt(reset)
node _T_1223 = eq(_T_1222, UInt<1>(0h0))
when _T_1223 :
node _T_1224 = eq(_T_1221, UInt<1>(0h0))
when _T_1224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1221, UInt<1>(0h1), "") : assert_52
node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_65 = shr(io.in.d.bits.source, 2)
node _source_ok_T_66 = eq(_source_ok_T_65, UInt<1>(0h0))
node _source_ok_T_67 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67)
node _source_ok_T_69 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_71 = shr(io.in.d.bits.source, 2)
node _source_ok_T_72 = eq(_source_ok_T_71, UInt<1>(0h1))
node _source_ok_T_73 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_74 = and(_source_ok_T_72, _source_ok_T_73)
node _source_ok_T_75 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_77 = shr(io.in.d.bits.source, 2)
node _source_ok_T_78 = eq(_source_ok_T_77, UInt<2>(0h2))
node _source_ok_T_79 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79)
node _source_ok_T_81 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0)
node _source_ok_T_83 = shr(io.in.d.bits.source, 2)
node _source_ok_T_84 = eq(_source_ok_T_83, UInt<2>(0h3))
node _source_ok_T_85 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_86 = and(_source_ok_T_84, _source_ok_T_85)
node _source_ok_T_87 = leq(source_ok_uncommonBits_9, UInt<2>(0h3))
node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87)
node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<7>(0h44))
node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<7>(0h45))
node _source_ok_T_91 = eq(io.in.d.bits.source, UInt<7>(0h46))
node _source_ok_T_92 = eq(io.in.d.bits.source, UInt<7>(0h40))
node _source_ok_T_93 = eq(io.in.d.bits.source, UInt<7>(0h41))
node _source_ok_T_94 = eq(io.in.d.bits.source, UInt<7>(0h42))
node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 2, 0)
node _source_ok_T_95 = shr(io.in.d.bits.source, 3)
node _source_ok_T_96 = eq(_source_ok_T_95, UInt<3>(0h6))
node _source_ok_T_97 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_98 = and(_source_ok_T_96, _source_ok_T_97)
node _source_ok_T_99 = leq(source_ok_uncommonBits_10, UInt<3>(0h4))
node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99)
node _source_ok_T_101 = eq(io.in.d.bits.source, UInt<6>(0h35))
node _source_ok_T_102 = eq(io.in.d.bits.source, UInt<6>(0h38))
node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 2, 0)
node _source_ok_T_103 = shr(io.in.d.bits.source, 3)
node _source_ok_T_104 = eq(_source_ok_T_103, UInt<3>(0h4))
node _source_ok_T_105 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105)
node _source_ok_T_107 = leq(source_ok_uncommonBits_11, UInt<3>(0h4))
node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107)
node _source_ok_T_109 = eq(io.in.d.bits.source, UInt<6>(0h25))
node _source_ok_T_110 = eq(io.in.d.bits.source, UInt<6>(0h28))
node _source_ok_T_111 = eq(io.in.d.bits.source, UInt<8>(0h80))
wire _source_ok_WIRE_1 : UInt<1>[18]
connect _source_ok_WIRE_1[0], _source_ok_T_64
connect _source_ok_WIRE_1[1], _source_ok_T_70
connect _source_ok_WIRE_1[2], _source_ok_T_76
connect _source_ok_WIRE_1[3], _source_ok_T_82
connect _source_ok_WIRE_1[4], _source_ok_T_88
connect _source_ok_WIRE_1[5], _source_ok_T_89
connect _source_ok_WIRE_1[6], _source_ok_T_90
connect _source_ok_WIRE_1[7], _source_ok_T_91
connect _source_ok_WIRE_1[8], _source_ok_T_92
connect _source_ok_WIRE_1[9], _source_ok_T_93
connect _source_ok_WIRE_1[10], _source_ok_T_94
connect _source_ok_WIRE_1[11], _source_ok_T_100
connect _source_ok_WIRE_1[12], _source_ok_T_101
connect _source_ok_WIRE_1[13], _source_ok_T_102
connect _source_ok_WIRE_1[14], _source_ok_T_108
connect _source_ok_WIRE_1[15], _source_ok_T_109
connect _source_ok_WIRE_1[16], _source_ok_T_110
connect _source_ok_WIRE_1[17], _source_ok_T_111
node _source_ok_T_112 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_113 = or(_source_ok_T_112, _source_ok_WIRE_1[2])
node _source_ok_T_114 = or(_source_ok_T_113, _source_ok_WIRE_1[3])
node _source_ok_T_115 = or(_source_ok_T_114, _source_ok_WIRE_1[4])
node _source_ok_T_116 = or(_source_ok_T_115, _source_ok_WIRE_1[5])
node _source_ok_T_117 = or(_source_ok_T_116, _source_ok_WIRE_1[6])
node _source_ok_T_118 = or(_source_ok_T_117, _source_ok_WIRE_1[7])
node _source_ok_T_119 = or(_source_ok_T_118, _source_ok_WIRE_1[8])
node _source_ok_T_120 = or(_source_ok_T_119, _source_ok_WIRE_1[9])
node _source_ok_T_121 = or(_source_ok_T_120, _source_ok_WIRE_1[10])
node _source_ok_T_122 = or(_source_ok_T_121, _source_ok_WIRE_1[11])
node _source_ok_T_123 = or(_source_ok_T_122, _source_ok_WIRE_1[12])
node _source_ok_T_124 = or(_source_ok_T_123, _source_ok_WIRE_1[13])
node _source_ok_T_125 = or(_source_ok_T_124, _source_ok_WIRE_1[14])
node _source_ok_T_126 = or(_source_ok_T_125, _source_ok_WIRE_1[15])
node _source_ok_T_127 = or(_source_ok_T_126, _source_ok_WIRE_1[16])
node source_ok_1 = or(_source_ok_T_127, _source_ok_WIRE_1[17])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1225 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1225 :
node _T_1226 = asUInt(reset)
node _T_1227 = eq(_T_1226, UInt<1>(0h0))
when _T_1227 :
node _T_1228 = eq(source_ok_1, UInt<1>(0h0))
when _T_1228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1229 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1230 = asUInt(reset)
node _T_1231 = eq(_T_1230, UInt<1>(0h0))
when _T_1231 :
node _T_1232 = eq(_T_1229, UInt<1>(0h0))
when _T_1232 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1229, UInt<1>(0h1), "") : assert_54
node _T_1233 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1234 = asUInt(reset)
node _T_1235 = eq(_T_1234, UInt<1>(0h0))
when _T_1235 :
node _T_1236 = eq(_T_1233, UInt<1>(0h0))
when _T_1236 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1233, UInt<1>(0h1), "") : assert_55
node _T_1237 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1238 = asUInt(reset)
node _T_1239 = eq(_T_1238, UInt<1>(0h0))
when _T_1239 :
node _T_1240 = eq(_T_1237, UInt<1>(0h0))
when _T_1240 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1237, UInt<1>(0h1), "") : assert_56
node _T_1241 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1242 = asUInt(reset)
node _T_1243 = eq(_T_1242, UInt<1>(0h0))
when _T_1243 :
node _T_1244 = eq(_T_1241, UInt<1>(0h0))
when _T_1244 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1241, UInt<1>(0h1), "") : assert_57
node _T_1245 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1245 :
node _T_1246 = asUInt(reset)
node _T_1247 = eq(_T_1246, UInt<1>(0h0))
when _T_1247 :
node _T_1248 = eq(source_ok_1, UInt<1>(0h0))
when _T_1248 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1249 = asUInt(reset)
node _T_1250 = eq(_T_1249, UInt<1>(0h0))
when _T_1250 :
node _T_1251 = eq(sink_ok, UInt<1>(0h0))
when _T_1251 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1252 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1253 = asUInt(reset)
node _T_1254 = eq(_T_1253, UInt<1>(0h0))
when _T_1254 :
node _T_1255 = eq(_T_1252, UInt<1>(0h0))
when _T_1255 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1252, UInt<1>(0h1), "") : assert_60
node _T_1256 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1257 = asUInt(reset)
node _T_1258 = eq(_T_1257, UInt<1>(0h0))
when _T_1258 :
node _T_1259 = eq(_T_1256, UInt<1>(0h0))
when _T_1259 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1256, UInt<1>(0h1), "") : assert_61
node _T_1260 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1261 = asUInt(reset)
node _T_1262 = eq(_T_1261, UInt<1>(0h0))
when _T_1262 :
node _T_1263 = eq(_T_1260, UInt<1>(0h0))
when _T_1263 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1260, UInt<1>(0h1), "") : assert_62
node _T_1264 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1265 = asUInt(reset)
node _T_1266 = eq(_T_1265, UInt<1>(0h0))
when _T_1266 :
node _T_1267 = eq(_T_1264, UInt<1>(0h0))
when _T_1267 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1264, UInt<1>(0h1), "") : assert_63
node _T_1268 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1269 = or(UInt<1>(0h0), _T_1268)
node _T_1270 = asUInt(reset)
node _T_1271 = eq(_T_1270, UInt<1>(0h0))
when _T_1271 :
node _T_1272 = eq(_T_1269, UInt<1>(0h0))
when _T_1272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1269, UInt<1>(0h1), "") : assert_64
node _T_1273 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1273 :
node _T_1274 = asUInt(reset)
node _T_1275 = eq(_T_1274, UInt<1>(0h0))
when _T_1275 :
node _T_1276 = eq(source_ok_1, UInt<1>(0h0))
when _T_1276 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1277 = asUInt(reset)
node _T_1278 = eq(_T_1277, UInt<1>(0h0))
when _T_1278 :
node _T_1279 = eq(sink_ok, UInt<1>(0h0))
when _T_1279 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1280 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1281 = asUInt(reset)
node _T_1282 = eq(_T_1281, UInt<1>(0h0))
when _T_1282 :
node _T_1283 = eq(_T_1280, UInt<1>(0h0))
when _T_1283 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1280, UInt<1>(0h1), "") : assert_67
node _T_1284 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1285 = asUInt(reset)
node _T_1286 = eq(_T_1285, UInt<1>(0h0))
when _T_1286 :
node _T_1287 = eq(_T_1284, UInt<1>(0h0))
when _T_1287 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1284, UInt<1>(0h1), "") : assert_68
node _T_1288 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1289 = asUInt(reset)
node _T_1290 = eq(_T_1289, UInt<1>(0h0))
when _T_1290 :
node _T_1291 = eq(_T_1288, UInt<1>(0h0))
when _T_1291 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1288, UInt<1>(0h1), "") : assert_69
node _T_1292 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1293 = or(_T_1292, io.in.d.bits.corrupt)
node _T_1294 = asUInt(reset)
node _T_1295 = eq(_T_1294, UInt<1>(0h0))
when _T_1295 :
node _T_1296 = eq(_T_1293, UInt<1>(0h0))
when _T_1296 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1293, UInt<1>(0h1), "") : assert_70
node _T_1297 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1298 = or(UInt<1>(0h0), _T_1297)
node _T_1299 = asUInt(reset)
node _T_1300 = eq(_T_1299, UInt<1>(0h0))
when _T_1300 :
node _T_1301 = eq(_T_1298, UInt<1>(0h0))
when _T_1301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1298, UInt<1>(0h1), "") : assert_71
node _T_1302 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1302 :
node _T_1303 = asUInt(reset)
node _T_1304 = eq(_T_1303, UInt<1>(0h0))
when _T_1304 :
node _T_1305 = eq(source_ok_1, UInt<1>(0h0))
when _T_1305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1306 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1307 = asUInt(reset)
node _T_1308 = eq(_T_1307, UInt<1>(0h0))
when _T_1308 :
node _T_1309 = eq(_T_1306, UInt<1>(0h0))
when _T_1309 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1306, UInt<1>(0h1), "") : assert_73
node _T_1310 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1311 = asUInt(reset)
node _T_1312 = eq(_T_1311, UInt<1>(0h0))
when _T_1312 :
node _T_1313 = eq(_T_1310, UInt<1>(0h0))
when _T_1313 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1310, UInt<1>(0h1), "") : assert_74
node _T_1314 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1315 = or(UInt<1>(0h0), _T_1314)
node _T_1316 = asUInt(reset)
node _T_1317 = eq(_T_1316, UInt<1>(0h0))
when _T_1317 :
node _T_1318 = eq(_T_1315, UInt<1>(0h0))
when _T_1318 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1315, UInt<1>(0h1), "") : assert_75
node _T_1319 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1319 :
node _T_1320 = asUInt(reset)
node _T_1321 = eq(_T_1320, UInt<1>(0h0))
when _T_1321 :
node _T_1322 = eq(source_ok_1, UInt<1>(0h0))
when _T_1322 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1323 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1324 = asUInt(reset)
node _T_1325 = eq(_T_1324, UInt<1>(0h0))
when _T_1325 :
node _T_1326 = eq(_T_1323, UInt<1>(0h0))
when _T_1326 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1323, UInt<1>(0h1), "") : assert_77
node _T_1327 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1328 = or(_T_1327, io.in.d.bits.corrupt)
node _T_1329 = asUInt(reset)
node _T_1330 = eq(_T_1329, UInt<1>(0h0))
when _T_1330 :
node _T_1331 = eq(_T_1328, UInt<1>(0h0))
when _T_1331 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1328, UInt<1>(0h1), "") : assert_78
node _T_1332 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1333 = or(UInt<1>(0h0), _T_1332)
node _T_1334 = asUInt(reset)
node _T_1335 = eq(_T_1334, UInt<1>(0h0))
when _T_1335 :
node _T_1336 = eq(_T_1333, UInt<1>(0h0))
when _T_1336 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1333, UInt<1>(0h1), "") : assert_79
node _T_1337 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1337 :
node _T_1338 = asUInt(reset)
node _T_1339 = eq(_T_1338, UInt<1>(0h0))
when _T_1339 :
node _T_1340 = eq(source_ok_1, UInt<1>(0h0))
when _T_1340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1341 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1342 = asUInt(reset)
node _T_1343 = eq(_T_1342, UInt<1>(0h0))
when _T_1343 :
node _T_1344 = eq(_T_1341, UInt<1>(0h0))
when _T_1344 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1341, UInt<1>(0h1), "") : assert_81
node _T_1345 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1346 = asUInt(reset)
node _T_1347 = eq(_T_1346, UInt<1>(0h0))
when _T_1347 :
node _T_1348 = eq(_T_1345, UInt<1>(0h0))
when _T_1348 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1345, UInt<1>(0h1), "") : assert_82
node _T_1349 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1350 = or(UInt<1>(0h0), _T_1349)
node _T_1351 = asUInt(reset)
node _T_1352 = eq(_T_1351, UInt<1>(0h0))
when _T_1352 :
node _T_1353 = eq(_T_1350, UInt<1>(0h0))
when _T_1353 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1350, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<21>(0h0)
connect _WIRE_4.bits.source, UInt<8>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1354 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1355 = asUInt(reset)
node _T_1356 = eq(_T_1355, UInt<1>(0h0))
when _T_1356 :
node _T_1357 = eq(_T_1354, UInt<1>(0h0))
when _T_1357 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1354, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<21>(0h0)
connect _WIRE_6.bits.source, UInt<8>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1358 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1359 = asUInt(reset)
node _T_1360 = eq(_T_1359, UInt<1>(0h0))
when _T_1360 :
node _T_1361 = eq(_T_1358, UInt<1>(0h0))
when _T_1361 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1358, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1362 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1363 = asUInt(reset)
node _T_1364 = eq(_T_1363, UInt<1>(0h0))
when _T_1364 :
node _T_1365 = eq(_T_1362, UInt<1>(0h0))
when _T_1365 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1362, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1366 = eq(a_first, UInt<1>(0h0))
node _T_1367 = and(io.in.a.valid, _T_1366)
when _T_1367 :
node _T_1368 = eq(io.in.a.bits.opcode, opcode)
node _T_1369 = asUInt(reset)
node _T_1370 = eq(_T_1369, UInt<1>(0h0))
when _T_1370 :
node _T_1371 = eq(_T_1368, UInt<1>(0h0))
when _T_1371 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1368, UInt<1>(0h1), "") : assert_87
node _T_1372 = eq(io.in.a.bits.param, param)
node _T_1373 = asUInt(reset)
node _T_1374 = eq(_T_1373, UInt<1>(0h0))
when _T_1374 :
node _T_1375 = eq(_T_1372, UInt<1>(0h0))
when _T_1375 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1372, UInt<1>(0h1), "") : assert_88
node _T_1376 = eq(io.in.a.bits.size, size)
node _T_1377 = asUInt(reset)
node _T_1378 = eq(_T_1377, UInt<1>(0h0))
when _T_1378 :
node _T_1379 = eq(_T_1376, UInt<1>(0h0))
when _T_1379 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1376, UInt<1>(0h1), "") : assert_89
node _T_1380 = eq(io.in.a.bits.source, source)
node _T_1381 = asUInt(reset)
node _T_1382 = eq(_T_1381, UInt<1>(0h0))
when _T_1382 :
node _T_1383 = eq(_T_1380, UInt<1>(0h0))
when _T_1383 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1380, UInt<1>(0h1), "") : assert_90
node _T_1384 = eq(io.in.a.bits.address, address)
node _T_1385 = asUInt(reset)
node _T_1386 = eq(_T_1385, UInt<1>(0h0))
when _T_1386 :
node _T_1387 = eq(_T_1384, UInt<1>(0h0))
when _T_1387 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1384, UInt<1>(0h1), "") : assert_91
node _T_1388 = and(io.in.a.ready, io.in.a.valid)
node _T_1389 = and(_T_1388, a_first)
when _T_1389 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1390 = eq(d_first, UInt<1>(0h0))
node _T_1391 = and(io.in.d.valid, _T_1390)
when _T_1391 :
node _T_1392 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1393 = asUInt(reset)
node _T_1394 = eq(_T_1393, UInt<1>(0h0))
when _T_1394 :
node _T_1395 = eq(_T_1392, UInt<1>(0h0))
when _T_1395 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1392, UInt<1>(0h1), "") : assert_92
node _T_1396 = eq(io.in.d.bits.param, param_1)
node _T_1397 = asUInt(reset)
node _T_1398 = eq(_T_1397, UInt<1>(0h0))
when _T_1398 :
node _T_1399 = eq(_T_1396, UInt<1>(0h0))
when _T_1399 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1396, UInt<1>(0h1), "") : assert_93
node _T_1400 = eq(io.in.d.bits.size, size_1)
node _T_1401 = asUInt(reset)
node _T_1402 = eq(_T_1401, UInt<1>(0h0))
when _T_1402 :
node _T_1403 = eq(_T_1400, UInt<1>(0h0))
when _T_1403 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1400, UInt<1>(0h1), "") : assert_94
node _T_1404 = eq(io.in.d.bits.source, source_1)
node _T_1405 = asUInt(reset)
node _T_1406 = eq(_T_1405, UInt<1>(0h0))
when _T_1406 :
node _T_1407 = eq(_T_1404, UInt<1>(0h0))
when _T_1407 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1404, UInt<1>(0h1), "") : assert_95
node _T_1408 = eq(io.in.d.bits.sink, sink)
node _T_1409 = asUInt(reset)
node _T_1410 = eq(_T_1409, UInt<1>(0h0))
when _T_1410 :
node _T_1411 = eq(_T_1408, UInt<1>(0h0))
when _T_1411 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1408, UInt<1>(0h1), "") : assert_96
node _T_1412 = eq(io.in.d.bits.denied, denied)
node _T_1413 = asUInt(reset)
node _T_1414 = eq(_T_1413, UInt<1>(0h0))
when _T_1414 :
node _T_1415 = eq(_T_1412, UInt<1>(0h0))
when _T_1415 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1412, UInt<1>(0h1), "") : assert_97
node _T_1416 = and(io.in.d.ready, io.in.d.valid)
node _T_1417 = and(_T_1416, d_first)
when _T_1417 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0)
regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0)
regreset inflight_sizes : UInt<516>, clock, reset, UInt<516>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<129>
connect a_set, UInt<129>(0h0)
wire a_set_wo_ready : UInt<129>
connect a_set_wo_ready, UInt<129>(0h0)
wire a_opcodes_set : UInt<516>
connect a_opcodes_set, UInt<516>(0h0)
wire a_sizes_set : UInt<516>
connect a_sizes_set, UInt<516>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1418 = and(io.in.a.valid, a_first_1)
node _T_1419 = and(_T_1418, UInt<1>(0h1))
when _T_1419 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1420 = and(io.in.a.ready, io.in.a.valid)
node _T_1421 = and(_T_1420, a_first_1)
node _T_1422 = and(_T_1421, UInt<1>(0h1))
when _T_1422 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1423 = dshr(inflight, io.in.a.bits.source)
node _T_1424 = bits(_T_1423, 0, 0)
node _T_1425 = eq(_T_1424, UInt<1>(0h0))
node _T_1426 = asUInt(reset)
node _T_1427 = eq(_T_1426, UInt<1>(0h0))
when _T_1427 :
node _T_1428 = eq(_T_1425, UInt<1>(0h0))
when _T_1428 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1425, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<129>
connect d_clr, UInt<129>(0h0)
wire d_clr_wo_ready : UInt<129>
connect d_clr_wo_ready, UInt<129>(0h0)
wire d_opcodes_clr : UInt<516>
connect d_opcodes_clr, UInt<516>(0h0)
wire d_sizes_clr : UInt<516>
connect d_sizes_clr, UInt<516>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1429 = and(io.in.d.valid, d_first_1)
node _T_1430 = and(_T_1429, UInt<1>(0h1))
node _T_1431 = eq(d_release_ack, UInt<1>(0h0))
node _T_1432 = and(_T_1430, _T_1431)
when _T_1432 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1433 = and(io.in.d.ready, io.in.d.valid)
node _T_1434 = and(_T_1433, d_first_1)
node _T_1435 = and(_T_1434, UInt<1>(0h1))
node _T_1436 = eq(d_release_ack, UInt<1>(0h0))
node _T_1437 = and(_T_1435, _T_1436)
when _T_1437 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1438 = and(io.in.d.valid, d_first_1)
node _T_1439 = and(_T_1438, UInt<1>(0h1))
node _T_1440 = eq(d_release_ack, UInt<1>(0h0))
node _T_1441 = and(_T_1439, _T_1440)
when _T_1441 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1442 = dshr(inflight, io.in.d.bits.source)
node _T_1443 = bits(_T_1442, 0, 0)
node _T_1444 = or(_T_1443, same_cycle_resp)
node _T_1445 = asUInt(reset)
node _T_1446 = eq(_T_1445, UInt<1>(0h0))
when _T_1446 :
node _T_1447 = eq(_T_1444, UInt<1>(0h0))
when _T_1447 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1444, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1448 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1449 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1450 = or(_T_1448, _T_1449)
node _T_1451 = asUInt(reset)
node _T_1452 = eq(_T_1451, UInt<1>(0h0))
when _T_1452 :
node _T_1453 = eq(_T_1450, UInt<1>(0h0))
when _T_1453 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1450, UInt<1>(0h1), "") : assert_100
node _T_1454 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1455 = asUInt(reset)
node _T_1456 = eq(_T_1455, UInt<1>(0h0))
when _T_1456 :
node _T_1457 = eq(_T_1454, UInt<1>(0h0))
when _T_1457 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1454, UInt<1>(0h1), "") : assert_101
else :
node _T_1458 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1459 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1460 = or(_T_1458, _T_1459)
node _T_1461 = asUInt(reset)
node _T_1462 = eq(_T_1461, UInt<1>(0h0))
when _T_1462 :
node _T_1463 = eq(_T_1460, UInt<1>(0h0))
when _T_1463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1460, UInt<1>(0h1), "") : assert_102
node _T_1464 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1465 = asUInt(reset)
node _T_1466 = eq(_T_1465, UInt<1>(0h0))
when _T_1466 :
node _T_1467 = eq(_T_1464, UInt<1>(0h0))
when _T_1467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1464, UInt<1>(0h1), "") : assert_103
node _T_1468 = and(io.in.d.valid, d_first_1)
node _T_1469 = and(_T_1468, a_first_1)
node _T_1470 = and(_T_1469, io.in.a.valid)
node _T_1471 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1472 = and(_T_1470, _T_1471)
node _T_1473 = eq(d_release_ack, UInt<1>(0h0))
node _T_1474 = and(_T_1472, _T_1473)
when _T_1474 :
node _T_1475 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1476 = or(_T_1475, io.in.a.ready)
node _T_1477 = asUInt(reset)
node _T_1478 = eq(_T_1477, UInt<1>(0h0))
when _T_1478 :
node _T_1479 = eq(_T_1476, UInt<1>(0h0))
when _T_1479 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1476, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_146
node _T_1480 = orr(inflight)
node _T_1481 = eq(_T_1480, UInt<1>(0h0))
node _T_1482 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1483 = or(_T_1481, _T_1482)
node _T_1484 = lt(watchdog, plusarg_reader.out)
node _T_1485 = or(_T_1483, _T_1484)
node _T_1486 = asUInt(reset)
node _T_1487 = eq(_T_1486, UInt<1>(0h0))
when _T_1487 :
node _T_1488 = eq(_T_1485, UInt<1>(0h0))
when _T_1488 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1485, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1489 = and(io.in.a.ready, io.in.a.valid)
node _T_1490 = and(io.in.d.ready, io.in.d.valid)
node _T_1491 = or(_T_1489, _T_1490)
when _T_1491 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0)
regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0)
regreset inflight_sizes_1 : UInt<516>, clock, reset, UInt<516>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<21>(0h0)
connect _c_first_WIRE.bits.source, UInt<8>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<8>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<129>
connect c_set, UInt<129>(0h0)
wire c_set_wo_ready : UInt<129>
connect c_set_wo_ready, UInt<129>(0h0)
wire c_opcodes_set : UInt<516>
connect c_opcodes_set, UInt<516>(0h0)
wire c_sizes_set : UInt<516>
connect c_sizes_set, UInt<516>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<21>(0h0)
connect _WIRE_10.bits.source, UInt<8>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1492 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<21>(0h0)
connect _WIRE_12.bits.source, UInt<8>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1493 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1494 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1495 = and(_T_1493, _T_1494)
node _T_1496 = and(_T_1492, _T_1495)
when _T_1496 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<21>(0h0)
connect _WIRE_14.bits.source, UInt<8>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1497 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1498 = and(_T_1497, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<21>(0h0)
connect _WIRE_16.bits.source, UInt<8>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1499 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1500 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1501 = and(_T_1499, _T_1500)
node _T_1502 = and(_T_1498, _T_1501)
when _T_1502 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<21>(0h0)
connect _WIRE_18.bits.source, UInt<8>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1503 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1504 = bits(_T_1503, 0, 0)
node _T_1505 = eq(_T_1504, UInt<1>(0h0))
node _T_1506 = asUInt(reset)
node _T_1507 = eq(_T_1506, UInt<1>(0h0))
when _T_1507 :
node _T_1508 = eq(_T_1505, UInt<1>(0h0))
when _T_1508 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1505, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<129>
connect d_clr_1, UInt<129>(0h0)
wire d_clr_wo_ready_1 : UInt<129>
connect d_clr_wo_ready_1, UInt<129>(0h0)
wire d_opcodes_clr_1 : UInt<516>
connect d_opcodes_clr_1, UInt<516>(0h0)
wire d_sizes_clr_1 : UInt<516>
connect d_sizes_clr_1, UInt<516>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1509 = and(io.in.d.valid, d_first_2)
node _T_1510 = and(_T_1509, UInt<1>(0h1))
node _T_1511 = and(_T_1510, d_release_ack_1)
when _T_1511 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1512 = and(io.in.d.ready, io.in.d.valid)
node _T_1513 = and(_T_1512, d_first_2)
node _T_1514 = and(_T_1513, UInt<1>(0h1))
node _T_1515 = and(_T_1514, d_release_ack_1)
when _T_1515 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1516 = and(io.in.d.valid, d_first_2)
node _T_1517 = and(_T_1516, UInt<1>(0h1))
node _T_1518 = and(_T_1517, d_release_ack_1)
when _T_1518 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1519 = dshr(inflight_1, io.in.d.bits.source)
node _T_1520 = bits(_T_1519, 0, 0)
node _T_1521 = or(_T_1520, same_cycle_resp_1)
node _T_1522 = asUInt(reset)
node _T_1523 = eq(_T_1522, UInt<1>(0h0))
when _T_1523 :
node _T_1524 = eq(_T_1521, UInt<1>(0h0))
when _T_1524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_1521, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<21>(0h0)
connect _WIRE_20.bits.source, UInt<8>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1525 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1526 = asUInt(reset)
node _T_1527 = eq(_T_1526, UInt<1>(0h0))
when _T_1527 :
node _T_1528 = eq(_T_1525, UInt<1>(0h0))
when _T_1528 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1525, UInt<1>(0h1), "") : assert_108
else :
node _T_1529 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1530 = asUInt(reset)
node _T_1531 = eq(_T_1530, UInt<1>(0h0))
when _T_1531 :
node _T_1532 = eq(_T_1529, UInt<1>(0h0))
when _T_1532 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1529, UInt<1>(0h1), "") : assert_109
node _T_1533 = and(io.in.d.valid, d_first_2)
node _T_1534 = and(_T_1533, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<21>(0h0)
connect _WIRE_22.bits.source, UInt<8>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1535 = and(_T_1534, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<21>(0h0)
connect _WIRE_24.bits.source, UInt<8>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1536 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1537 = and(_T_1535, _T_1536)
node _T_1538 = and(_T_1537, d_release_ack_1)
node _T_1539 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1540 = and(_T_1538, _T_1539)
when _T_1540 :
node _T_1541 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<21>(0h0)
connect _WIRE_26.bits.source, UInt<8>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1542 = or(_T_1541, _WIRE_27.ready)
node _T_1543 = asUInt(reset)
node _T_1544 = eq(_T_1543, UInt<1>(0h0))
when _T_1544 :
node _T_1545 = eq(_T_1542, UInt<1>(0h0))
when _T_1545 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1542, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_147
node _T_1546 = orr(inflight_1)
node _T_1547 = eq(_T_1546, UInt<1>(0h0))
node _T_1548 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1549 = or(_T_1547, _T_1548)
node _T_1550 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1551 = or(_T_1549, _T_1550)
node _T_1552 = asUInt(reset)
node _T_1553 = eq(_T_1552, UInt<1>(0h0))
when _T_1553 :
node _T_1554 = eq(_T_1551, UInt<1>(0h0))
when _T_1554 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1551, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<21>(0h0)
connect _WIRE_28.bits.source, UInt<8>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1555 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1556 = and(io.in.d.ready, io.in.d.valid)
node _T_1557 = or(_T_1555, _T_1556)
when _T_1557 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_71( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_97 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_105 = 1'h1; // @[Parameters.scala:56:32]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54]
wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52]
wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79]
wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35]
wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35]
wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34]
wire [515:0] c_sizes_set = 516'h0; // @[Monitor.scala:741:34]
wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34]
wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 8'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 6'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 6'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 6'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 6'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 8'h44; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = io_in_a_bits_source_0 == 8'h45; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31]
wire _source_ok_T_27 = io_in_a_bits_source_0 == 8'h46; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31]
wire _source_ok_T_28 = io_in_a_bits_source_0 == 8'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31]
wire _source_ok_T_29 = io_in_a_bits_source_0 == 8'h41; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31]
wire _source_ok_T_30 = io_in_a_bits_source_0 == 8'h42; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_31 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_39 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_32 = _source_ok_T_31 == 5'h6; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_35 = source_ok_uncommonBits_4 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_36 = _source_ok_T_34 & _source_ok_T_35; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_11 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire _source_ok_T_37 = io_in_a_bits_source_0 == 8'h35; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_12 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire _source_ok_T_38 = io_in_a_bits_source_0 == 8'h38; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_13 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_40 = _source_ok_T_39 == 5'h4; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_43 = source_ok_uncommonBits_5 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_44 = _source_ok_T_42 & _source_ok_T_43; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_14 = _source_ok_T_44; // @[Parameters.scala:1138:31]
wire _source_ok_T_45 = io_in_a_bits_source_0 == 8'h25; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_15 = _source_ok_T_45; // @[Parameters.scala:1138:31]
wire _source_ok_T_46 = io_in_a_bits_source_0 == 8'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_16 = _source_ok_T_46; // @[Parameters.scala:1138:31]
wire _source_ok_T_47 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_17 = _source_ok_T_47; // @[Parameters.scala:1138:31]
wire _source_ok_T_48 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_53 = _source_ok_T_52 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_55 = _source_ok_T_54 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_56 = _source_ok_T_55 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_57 = _source_ok_T_56 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_58 = _source_ok_T_57 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_59 = _source_ok_T_58 | _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_60 = _source_ok_T_59 | _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_61 = _source_ok_T_60 | _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_62 = _source_ok_T_61 | _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_63 | _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_10 = _uncommonBits_T_10[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_16 = _uncommonBits_T_16[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_17 = _uncommonBits_T_17[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_22 = _uncommonBits_T_22[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_23 = _uncommonBits_T_23[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_28 = _uncommonBits_T_28[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_35 = _uncommonBits_T_35[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_52 = _uncommonBits_T_52[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_58 = _uncommonBits_T_58[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_59 = _uncommonBits_T_59[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_64 = _uncommonBits_T_64[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_65 = _uncommonBits_T_65[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_64 = io_in_d_bits_source_0 == 8'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_64; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_65 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_71 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_77 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_83 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_66 = _source_ok_T_65 == 6'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_70; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_72 = _source_ok_T_71 == 6'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_76; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_78 = _source_ok_T_77 == 6'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_82; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_84 = _source_ok_T_83 == 6'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_88; // @[Parameters.scala:1138:31]
wire _source_ok_T_89 = io_in_d_bits_source_0 == 8'h44; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_89; // @[Parameters.scala:1138:31]
wire _source_ok_T_90 = io_in_d_bits_source_0 == 8'h45; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_90; // @[Parameters.scala:1138:31]
wire _source_ok_T_91 = io_in_d_bits_source_0 == 8'h46; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_91; // @[Parameters.scala:1138:31]
wire _source_ok_T_92 = io_in_d_bits_source_0 == 8'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_92; // @[Parameters.scala:1138:31]
wire _source_ok_T_93 = io_in_d_bits_source_0 == 8'h41; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_93; // @[Parameters.scala:1138:31]
wire _source_ok_T_94 = io_in_d_bits_source_0 == 8'h42; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_94; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[2:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_95 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_103 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_96 = _source_ok_T_95 == 5'h6; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_98 = _source_ok_T_96; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_99 = source_ok_uncommonBits_10 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_100 = _source_ok_T_98 & _source_ok_T_99; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_11 = _source_ok_T_100; // @[Parameters.scala:1138:31]
wire _source_ok_T_101 = io_in_d_bits_source_0 == 8'h35; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_12 = _source_ok_T_101; // @[Parameters.scala:1138:31]
wire _source_ok_T_102 = io_in_d_bits_source_0 == 8'h38; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_13 = _source_ok_T_102; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_104 = _source_ok_T_103 == 5'h4; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_106 = _source_ok_T_104; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_107 = source_ok_uncommonBits_11 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_108 = _source_ok_T_106 & _source_ok_T_107; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_14 = _source_ok_T_108; // @[Parameters.scala:1138:31]
wire _source_ok_T_109 = io_in_d_bits_source_0 == 8'h25; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_15 = _source_ok_T_109; // @[Parameters.scala:1138:31]
wire _source_ok_T_110 = io_in_d_bits_source_0 == 8'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_16 = _source_ok_T_110; // @[Parameters.scala:1138:31]
wire _source_ok_T_111 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_17 = _source_ok_T_111; // @[Parameters.scala:1138:31]
wire _source_ok_T_112 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_113 = _source_ok_T_112 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_114 = _source_ok_T_113 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_115 = _source_ok_T_114 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_116 = _source_ok_T_115 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_117 = _source_ok_T_116 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_118 = _source_ok_T_117 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_119 = _source_ok_T_118 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_120 = _source_ok_T_119 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_121 = _source_ok_T_120 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_122 = _source_ok_T_121 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_123 = _source_ok_T_122 | _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_124 = _source_ok_T_123 | _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_125 = _source_ok_T_124 | _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_126 = _source_ok_T_125 | _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_127 = _source_ok_T_126 | _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_127 | _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1489 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1489; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1489; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [7:0] source; // @[Monitor.scala:390:22]
reg [20:0] address; // @[Monitor.scala:391:22]
wire _T_1557 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1557; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1557; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1557; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [7:0] source_1; // @[Monitor.scala:541:22]
reg [128:0] inflight; // @[Monitor.scala:614:27]
reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [515:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [128:0] a_set; // @[Monitor.scala:626:34]
wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [515:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [515:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [515:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [515:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[515:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [255:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1422 = _T_1489 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1422 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1422 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1422 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1422 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1422 ? _a_sizes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [128:0] d_clr; // @[Monitor.scala:664:34]
wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [515:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1468 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1468 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1437 = _T_1557 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1437 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1437 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1437 ? _d_sizes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [128:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [515:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [515:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [515:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [515:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [128:0] inflight_1; // @[Monitor.scala:726:35]
wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [515:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [515:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [515:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [515:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[515:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [128:0] d_clr_1; // @[Monitor.scala:774:34]
wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [515:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1533 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1533 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1515 = _T_1557 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1515 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1515 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1515 ? _d_sizes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113]
wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [515:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [515:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module BTBBranchPredictorBank_2 :
input clock : Clock
input reset : Reset
output io : { flip f0_valid : UInt<1>, flip f0_pc : UInt<40>, flip f0_mask : UInt<4>, flip f1_ghist : UInt<64>, flip f1_lhist : UInt<1>, flip resp_in : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}[1], resp : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}, f3_meta : UInt<120>, flip f3_fire : UInt<1>, flip update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}}
connect io.resp, io.resp_in[0]
connect io.f3_meta, UInt<1>(0h0)
node s0_idx = shr(io.f0_pc, 4)
reg s1_idx : UInt, clock
connect s1_idx, s0_idx
reg s2_idx : UInt, clock
connect s2_idx, s1_idx
reg s3_idx : UInt, clock
connect s3_idx, s2_idx
reg s1_valid : UInt<1>, clock
connect s1_valid, io.f0_valid
reg s2_valid : UInt<1>, clock
connect s2_valid, s1_valid
reg s3_valid : UInt<1>, clock
connect s3_valid, s2_valid
reg s1_mask : UInt, clock
connect s1_mask, io.f0_mask
reg s2_mask : UInt, clock
connect s2_mask, s1_mask
reg s3_mask : UInt, clock
connect s3_mask, s2_mask
reg s1_pc : UInt, clock
connect s1_pc, io.f0_pc
node s0_update_idx = shr(io.update.bits.pc, 4)
reg s1_update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}, clock
connect s1_update.bits.meta, io.update.bits.meta
connect s1_update.bits.target, io.update.bits.target
connect s1_update.bits.lhist, io.update.bits.lhist
connect s1_update.bits.ghist, io.update.bits.ghist
connect s1_update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr
connect s1_update.bits.cfi_is_jal, io.update.bits.cfi_is_jal
connect s1_update.bits.cfi_is_br, io.update.bits.cfi_is_br
connect s1_update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted
connect s1_update.bits.cfi_taken, io.update.bits.cfi_taken
connect s1_update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits
connect s1_update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid
connect s1_update.bits.br_mask, io.update.bits.br_mask
connect s1_update.bits.pc, io.update.bits.pc
connect s1_update.bits.btb_mispredicts, io.update.bits.btb_mispredicts
connect s1_update.bits.is_repair_update, io.update.bits.is_repair_update
connect s1_update.bits.is_mispredict_update, io.update.bits.is_mispredict_update
connect s1_update.valid, io.update.valid
reg s1_update_idx : UInt, clock
connect s1_update_idx, s0_update_idx
reg s1_update_valid : UInt<1>, clock
connect s1_update_valid, io.update.valid
wire s1_meta : { write_way : UInt<1>}
reg f3_meta_REG : { write_way : UInt<1>}, clock
connect f3_meta_REG, s1_meta
reg f3_meta : { write_way : UInt<1>}, clock
connect f3_meta, f3_meta_REG
connect io.f3_meta, f3_meta.write_way
regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1)
regreset reset_idx : UInt<7>, clock, reset, UInt<7>(0h0)
node _reset_idx_T = add(reset_idx, doing_reset)
node _reset_idx_T_1 = tail(_reset_idx_T, 1)
connect reset_idx, _reset_idx_T_1
node _T = eq(reset_idx, UInt<7>(0h7f))
when _T :
connect doing_reset, UInt<1>(0h0)
smem meta_0 : UInt<30>[4] [128]
smem meta_1 : UInt<30>[4] [128]
smem btb_0 : UInt<14>[4] [128]
smem btb_1 : UInt<14>[4] [128]
smem ebtb : UInt<40> [128]
wire _s1_req_rbtb_WIRE : UInt<36>
invalidate _s1_req_rbtb_WIRE
when io.f0_valid :
connect _s1_req_rbtb_WIRE, s0_idx
node _s1_req_rbtb_T = bits(_s1_req_rbtb_WIRE, 6, 0)
read mport s1_req_rbtb_MPORT = btb_0[_s1_req_rbtb_T], clock
wire _s1_req_rbtb_WIRE_1 : { offset : SInt<13>, extended : UInt<1>}
wire _s1_req_rbtb_WIRE_2 : UInt<14>
connect _s1_req_rbtb_WIRE_2, s1_req_rbtb_MPORT[0]
node _s1_req_rbtb_T_1 = bits(_s1_req_rbtb_WIRE_2, 0, 0)
connect _s1_req_rbtb_WIRE_1.extended, _s1_req_rbtb_T_1
node _s1_req_rbtb_T_2 = bits(_s1_req_rbtb_WIRE_2, 13, 1)
node _s1_req_rbtb_T_3 = asSInt(_s1_req_rbtb_T_2)
connect _s1_req_rbtb_WIRE_1.offset, _s1_req_rbtb_T_3
wire _s1_req_rbtb_WIRE_3 : { offset : SInt<13>, extended : UInt<1>}
wire _s1_req_rbtb_WIRE_4 : UInt<14>
connect _s1_req_rbtb_WIRE_4, s1_req_rbtb_MPORT[1]
node _s1_req_rbtb_T_4 = bits(_s1_req_rbtb_WIRE_4, 0, 0)
connect _s1_req_rbtb_WIRE_3.extended, _s1_req_rbtb_T_4
node _s1_req_rbtb_T_5 = bits(_s1_req_rbtb_WIRE_4, 13, 1)
node _s1_req_rbtb_T_6 = asSInt(_s1_req_rbtb_T_5)
connect _s1_req_rbtb_WIRE_3.offset, _s1_req_rbtb_T_6
wire _s1_req_rbtb_WIRE_5 : { offset : SInt<13>, extended : UInt<1>}
wire _s1_req_rbtb_WIRE_6 : UInt<14>
connect _s1_req_rbtb_WIRE_6, s1_req_rbtb_MPORT[2]
node _s1_req_rbtb_T_7 = bits(_s1_req_rbtb_WIRE_6, 0, 0)
connect _s1_req_rbtb_WIRE_5.extended, _s1_req_rbtb_T_7
node _s1_req_rbtb_T_8 = bits(_s1_req_rbtb_WIRE_6, 13, 1)
node _s1_req_rbtb_T_9 = asSInt(_s1_req_rbtb_T_8)
connect _s1_req_rbtb_WIRE_5.offset, _s1_req_rbtb_T_9
wire _s1_req_rbtb_WIRE_7 : { offset : SInt<13>, extended : UInt<1>}
wire _s1_req_rbtb_WIRE_8 : UInt<14>
connect _s1_req_rbtb_WIRE_8, s1_req_rbtb_MPORT[3]
node _s1_req_rbtb_T_10 = bits(_s1_req_rbtb_WIRE_8, 0, 0)
connect _s1_req_rbtb_WIRE_7.extended, _s1_req_rbtb_T_10
node _s1_req_rbtb_T_11 = bits(_s1_req_rbtb_WIRE_8, 13, 1)
node _s1_req_rbtb_T_12 = asSInt(_s1_req_rbtb_T_11)
connect _s1_req_rbtb_WIRE_7.offset, _s1_req_rbtb_T_12
wire _s1_req_rbtb_WIRE_9 : { offset : SInt<13>, extended : UInt<1>}[4]
connect _s1_req_rbtb_WIRE_9[0].extended, _s1_req_rbtb_WIRE_1.extended
connect _s1_req_rbtb_WIRE_9[0].offset, _s1_req_rbtb_WIRE_1.offset
connect _s1_req_rbtb_WIRE_9[1].extended, _s1_req_rbtb_WIRE_3.extended
connect _s1_req_rbtb_WIRE_9[1].offset, _s1_req_rbtb_WIRE_3.offset
connect _s1_req_rbtb_WIRE_9[2].extended, _s1_req_rbtb_WIRE_5.extended
connect _s1_req_rbtb_WIRE_9[2].offset, _s1_req_rbtb_WIRE_5.offset
connect _s1_req_rbtb_WIRE_9[3].extended, _s1_req_rbtb_WIRE_7.extended
connect _s1_req_rbtb_WIRE_9[3].offset, _s1_req_rbtb_WIRE_7.offset
wire _s1_req_rbtb_WIRE_10 : UInt<36>
invalidate _s1_req_rbtb_WIRE_10
when io.f0_valid :
connect _s1_req_rbtb_WIRE_10, s0_idx
node _s1_req_rbtb_T_13 = bits(_s1_req_rbtb_WIRE_10, 6, 0)
read mport s1_req_rbtb_MPORT_1 = btb_1[_s1_req_rbtb_T_13], clock
wire _s1_req_rbtb_WIRE_11 : { offset : SInt<13>, extended : UInt<1>}
wire _s1_req_rbtb_WIRE_12 : UInt<14>
connect _s1_req_rbtb_WIRE_12, s1_req_rbtb_MPORT_1[0]
node _s1_req_rbtb_T_14 = bits(_s1_req_rbtb_WIRE_12, 0, 0)
connect _s1_req_rbtb_WIRE_11.extended, _s1_req_rbtb_T_14
node _s1_req_rbtb_T_15 = bits(_s1_req_rbtb_WIRE_12, 13, 1)
node _s1_req_rbtb_T_16 = asSInt(_s1_req_rbtb_T_15)
connect _s1_req_rbtb_WIRE_11.offset, _s1_req_rbtb_T_16
wire _s1_req_rbtb_WIRE_13 : { offset : SInt<13>, extended : UInt<1>}
wire _s1_req_rbtb_WIRE_14 : UInt<14>
connect _s1_req_rbtb_WIRE_14, s1_req_rbtb_MPORT_1[1]
node _s1_req_rbtb_T_17 = bits(_s1_req_rbtb_WIRE_14, 0, 0)
connect _s1_req_rbtb_WIRE_13.extended, _s1_req_rbtb_T_17
node _s1_req_rbtb_T_18 = bits(_s1_req_rbtb_WIRE_14, 13, 1)
node _s1_req_rbtb_T_19 = asSInt(_s1_req_rbtb_T_18)
connect _s1_req_rbtb_WIRE_13.offset, _s1_req_rbtb_T_19
wire _s1_req_rbtb_WIRE_15 : { offset : SInt<13>, extended : UInt<1>}
wire _s1_req_rbtb_WIRE_16 : UInt<14>
connect _s1_req_rbtb_WIRE_16, s1_req_rbtb_MPORT_1[2]
node _s1_req_rbtb_T_20 = bits(_s1_req_rbtb_WIRE_16, 0, 0)
connect _s1_req_rbtb_WIRE_15.extended, _s1_req_rbtb_T_20
node _s1_req_rbtb_T_21 = bits(_s1_req_rbtb_WIRE_16, 13, 1)
node _s1_req_rbtb_T_22 = asSInt(_s1_req_rbtb_T_21)
connect _s1_req_rbtb_WIRE_15.offset, _s1_req_rbtb_T_22
wire _s1_req_rbtb_WIRE_17 : { offset : SInt<13>, extended : UInt<1>}
wire _s1_req_rbtb_WIRE_18 : UInt<14>
connect _s1_req_rbtb_WIRE_18, s1_req_rbtb_MPORT_1[3]
node _s1_req_rbtb_T_23 = bits(_s1_req_rbtb_WIRE_18, 0, 0)
connect _s1_req_rbtb_WIRE_17.extended, _s1_req_rbtb_T_23
node _s1_req_rbtb_T_24 = bits(_s1_req_rbtb_WIRE_18, 13, 1)
node _s1_req_rbtb_T_25 = asSInt(_s1_req_rbtb_T_24)
connect _s1_req_rbtb_WIRE_17.offset, _s1_req_rbtb_T_25
wire _s1_req_rbtb_WIRE_19 : { offset : SInt<13>, extended : UInt<1>}[4]
connect _s1_req_rbtb_WIRE_19[0].extended, _s1_req_rbtb_WIRE_11.extended
connect _s1_req_rbtb_WIRE_19[0].offset, _s1_req_rbtb_WIRE_11.offset
connect _s1_req_rbtb_WIRE_19[1].extended, _s1_req_rbtb_WIRE_13.extended
connect _s1_req_rbtb_WIRE_19[1].offset, _s1_req_rbtb_WIRE_13.offset
connect _s1_req_rbtb_WIRE_19[2].extended, _s1_req_rbtb_WIRE_15.extended
connect _s1_req_rbtb_WIRE_19[2].offset, _s1_req_rbtb_WIRE_15.offset
connect _s1_req_rbtb_WIRE_19[3].extended, _s1_req_rbtb_WIRE_17.extended
connect _s1_req_rbtb_WIRE_19[3].offset, _s1_req_rbtb_WIRE_17.offset
wire s1_req_rbtb : { offset : SInt<13>, extended : UInt<1>}[4][2]
connect s1_req_rbtb[0], _s1_req_rbtb_WIRE_9
connect s1_req_rbtb[1], _s1_req_rbtb_WIRE_19
wire _s1_req_rmeta_WIRE : UInt<36>
invalidate _s1_req_rmeta_WIRE
when io.f0_valid :
connect _s1_req_rmeta_WIRE, s0_idx
node _s1_req_rmeta_T = bits(_s1_req_rmeta_WIRE, 6, 0)
read mport s1_req_rmeta_MPORT = meta_0[_s1_req_rmeta_T], clock
wire _s1_req_rmeta_WIRE_1 : { is_br : UInt<1>, tag : UInt<29>}
wire _s1_req_rmeta_WIRE_2 : UInt<30>
connect _s1_req_rmeta_WIRE_2, s1_req_rmeta_MPORT[0]
node _s1_req_rmeta_T_1 = bits(_s1_req_rmeta_WIRE_2, 28, 0)
connect _s1_req_rmeta_WIRE_1.tag, _s1_req_rmeta_T_1
node _s1_req_rmeta_T_2 = bits(_s1_req_rmeta_WIRE_2, 29, 29)
connect _s1_req_rmeta_WIRE_1.is_br, _s1_req_rmeta_T_2
wire _s1_req_rmeta_WIRE_3 : { is_br : UInt<1>, tag : UInt<29>}
wire _s1_req_rmeta_WIRE_4 : UInt<30>
connect _s1_req_rmeta_WIRE_4, s1_req_rmeta_MPORT[1]
node _s1_req_rmeta_T_3 = bits(_s1_req_rmeta_WIRE_4, 28, 0)
connect _s1_req_rmeta_WIRE_3.tag, _s1_req_rmeta_T_3
node _s1_req_rmeta_T_4 = bits(_s1_req_rmeta_WIRE_4, 29, 29)
connect _s1_req_rmeta_WIRE_3.is_br, _s1_req_rmeta_T_4
wire _s1_req_rmeta_WIRE_5 : { is_br : UInt<1>, tag : UInt<29>}
wire _s1_req_rmeta_WIRE_6 : UInt<30>
connect _s1_req_rmeta_WIRE_6, s1_req_rmeta_MPORT[2]
node _s1_req_rmeta_T_5 = bits(_s1_req_rmeta_WIRE_6, 28, 0)
connect _s1_req_rmeta_WIRE_5.tag, _s1_req_rmeta_T_5
node _s1_req_rmeta_T_6 = bits(_s1_req_rmeta_WIRE_6, 29, 29)
connect _s1_req_rmeta_WIRE_5.is_br, _s1_req_rmeta_T_6
wire _s1_req_rmeta_WIRE_7 : { is_br : UInt<1>, tag : UInt<29>}
wire _s1_req_rmeta_WIRE_8 : UInt<30>
connect _s1_req_rmeta_WIRE_8, s1_req_rmeta_MPORT[3]
node _s1_req_rmeta_T_7 = bits(_s1_req_rmeta_WIRE_8, 28, 0)
connect _s1_req_rmeta_WIRE_7.tag, _s1_req_rmeta_T_7
node _s1_req_rmeta_T_8 = bits(_s1_req_rmeta_WIRE_8, 29, 29)
connect _s1_req_rmeta_WIRE_7.is_br, _s1_req_rmeta_T_8
wire _s1_req_rmeta_WIRE_9 : { is_br : UInt<1>, tag : UInt<29>}[4]
connect _s1_req_rmeta_WIRE_9[0].tag, _s1_req_rmeta_WIRE_1.tag
connect _s1_req_rmeta_WIRE_9[0].is_br, _s1_req_rmeta_WIRE_1.is_br
connect _s1_req_rmeta_WIRE_9[1].tag, _s1_req_rmeta_WIRE_3.tag
connect _s1_req_rmeta_WIRE_9[1].is_br, _s1_req_rmeta_WIRE_3.is_br
connect _s1_req_rmeta_WIRE_9[2].tag, _s1_req_rmeta_WIRE_5.tag
connect _s1_req_rmeta_WIRE_9[2].is_br, _s1_req_rmeta_WIRE_5.is_br
connect _s1_req_rmeta_WIRE_9[3].tag, _s1_req_rmeta_WIRE_7.tag
connect _s1_req_rmeta_WIRE_9[3].is_br, _s1_req_rmeta_WIRE_7.is_br
wire _s1_req_rmeta_WIRE_10 : UInt<36>
invalidate _s1_req_rmeta_WIRE_10
when io.f0_valid :
connect _s1_req_rmeta_WIRE_10, s0_idx
node _s1_req_rmeta_T_9 = bits(_s1_req_rmeta_WIRE_10, 6, 0)
read mport s1_req_rmeta_MPORT_1 = meta_1[_s1_req_rmeta_T_9], clock
wire _s1_req_rmeta_WIRE_11 : { is_br : UInt<1>, tag : UInt<29>}
wire _s1_req_rmeta_WIRE_12 : UInt<30>
connect _s1_req_rmeta_WIRE_12, s1_req_rmeta_MPORT_1[0]
node _s1_req_rmeta_T_10 = bits(_s1_req_rmeta_WIRE_12, 28, 0)
connect _s1_req_rmeta_WIRE_11.tag, _s1_req_rmeta_T_10
node _s1_req_rmeta_T_11 = bits(_s1_req_rmeta_WIRE_12, 29, 29)
connect _s1_req_rmeta_WIRE_11.is_br, _s1_req_rmeta_T_11
wire _s1_req_rmeta_WIRE_13 : { is_br : UInt<1>, tag : UInt<29>}
wire _s1_req_rmeta_WIRE_14 : UInt<30>
connect _s1_req_rmeta_WIRE_14, s1_req_rmeta_MPORT_1[1]
node _s1_req_rmeta_T_12 = bits(_s1_req_rmeta_WIRE_14, 28, 0)
connect _s1_req_rmeta_WIRE_13.tag, _s1_req_rmeta_T_12
node _s1_req_rmeta_T_13 = bits(_s1_req_rmeta_WIRE_14, 29, 29)
connect _s1_req_rmeta_WIRE_13.is_br, _s1_req_rmeta_T_13
wire _s1_req_rmeta_WIRE_15 : { is_br : UInt<1>, tag : UInt<29>}
wire _s1_req_rmeta_WIRE_16 : UInt<30>
connect _s1_req_rmeta_WIRE_16, s1_req_rmeta_MPORT_1[2]
node _s1_req_rmeta_T_14 = bits(_s1_req_rmeta_WIRE_16, 28, 0)
connect _s1_req_rmeta_WIRE_15.tag, _s1_req_rmeta_T_14
node _s1_req_rmeta_T_15 = bits(_s1_req_rmeta_WIRE_16, 29, 29)
connect _s1_req_rmeta_WIRE_15.is_br, _s1_req_rmeta_T_15
wire _s1_req_rmeta_WIRE_17 : { is_br : UInt<1>, tag : UInt<29>}
wire _s1_req_rmeta_WIRE_18 : UInt<30>
connect _s1_req_rmeta_WIRE_18, s1_req_rmeta_MPORT_1[3]
node _s1_req_rmeta_T_16 = bits(_s1_req_rmeta_WIRE_18, 28, 0)
connect _s1_req_rmeta_WIRE_17.tag, _s1_req_rmeta_T_16
node _s1_req_rmeta_T_17 = bits(_s1_req_rmeta_WIRE_18, 29, 29)
connect _s1_req_rmeta_WIRE_17.is_br, _s1_req_rmeta_T_17
wire _s1_req_rmeta_WIRE_19 : { is_br : UInt<1>, tag : UInt<29>}[4]
connect _s1_req_rmeta_WIRE_19[0].tag, _s1_req_rmeta_WIRE_11.tag
connect _s1_req_rmeta_WIRE_19[0].is_br, _s1_req_rmeta_WIRE_11.is_br
connect _s1_req_rmeta_WIRE_19[1].tag, _s1_req_rmeta_WIRE_13.tag
connect _s1_req_rmeta_WIRE_19[1].is_br, _s1_req_rmeta_WIRE_13.is_br
connect _s1_req_rmeta_WIRE_19[2].tag, _s1_req_rmeta_WIRE_15.tag
connect _s1_req_rmeta_WIRE_19[2].is_br, _s1_req_rmeta_WIRE_15.is_br
connect _s1_req_rmeta_WIRE_19[3].tag, _s1_req_rmeta_WIRE_17.tag
connect _s1_req_rmeta_WIRE_19[3].is_br, _s1_req_rmeta_WIRE_17.is_br
wire s1_req_rmeta : { is_br : UInt<1>, tag : UInt<29>}[4][2]
connect s1_req_rmeta[0], _s1_req_rmeta_WIRE_9
connect s1_req_rmeta[1], _s1_req_rmeta_WIRE_19
wire _s1_req_rebtb_WIRE : UInt<36>
invalidate _s1_req_rebtb_WIRE
when io.f0_valid :
connect _s1_req_rebtb_WIRE, s0_idx
node _s1_req_rebtb_T = bits(_s1_req_rebtb_WIRE, 6, 0)
read mport s1_req_rebtb = ebtb[_s1_req_rebtb_T], clock
node s1_req_tag = shr(s1_idx, 7)
wire s1_resp : { valid : UInt<1>, bits : UInt<40>}[4]
wire s1_is_br : UInt<1>[4]
wire s1_is_jal : UInt<1>[4]
node _s1_hit_ohs_T = bits(s1_req_tag, 28, 0)
node _s1_hit_ohs_T_1 = eq(s1_req_rmeta[0][0].tag, _s1_hit_ohs_T)
node _s1_hit_ohs_T_2 = bits(s1_req_tag, 28, 0)
node _s1_hit_ohs_T_3 = eq(s1_req_rmeta[1][0].tag, _s1_hit_ohs_T_2)
wire _s1_hit_ohs_WIRE : UInt<1>[2]
connect _s1_hit_ohs_WIRE[0], _s1_hit_ohs_T_1
connect _s1_hit_ohs_WIRE[1], _s1_hit_ohs_T_3
node _s1_hit_ohs_T_4 = bits(s1_req_tag, 28, 0)
node _s1_hit_ohs_T_5 = eq(s1_req_rmeta[0][1].tag, _s1_hit_ohs_T_4)
node _s1_hit_ohs_T_6 = bits(s1_req_tag, 28, 0)
node _s1_hit_ohs_T_7 = eq(s1_req_rmeta[1][1].tag, _s1_hit_ohs_T_6)
wire _s1_hit_ohs_WIRE_1 : UInt<1>[2]
connect _s1_hit_ohs_WIRE_1[0], _s1_hit_ohs_T_5
connect _s1_hit_ohs_WIRE_1[1], _s1_hit_ohs_T_7
node _s1_hit_ohs_T_8 = bits(s1_req_tag, 28, 0)
node _s1_hit_ohs_T_9 = eq(s1_req_rmeta[0][2].tag, _s1_hit_ohs_T_8)
node _s1_hit_ohs_T_10 = bits(s1_req_tag, 28, 0)
node _s1_hit_ohs_T_11 = eq(s1_req_rmeta[1][2].tag, _s1_hit_ohs_T_10)
wire _s1_hit_ohs_WIRE_2 : UInt<1>[2]
connect _s1_hit_ohs_WIRE_2[0], _s1_hit_ohs_T_9
connect _s1_hit_ohs_WIRE_2[1], _s1_hit_ohs_T_11
node _s1_hit_ohs_T_12 = bits(s1_req_tag, 28, 0)
node _s1_hit_ohs_T_13 = eq(s1_req_rmeta[0][3].tag, _s1_hit_ohs_T_12)
node _s1_hit_ohs_T_14 = bits(s1_req_tag, 28, 0)
node _s1_hit_ohs_T_15 = eq(s1_req_rmeta[1][3].tag, _s1_hit_ohs_T_14)
wire _s1_hit_ohs_WIRE_3 : UInt<1>[2]
connect _s1_hit_ohs_WIRE_3[0], _s1_hit_ohs_T_13
connect _s1_hit_ohs_WIRE_3[1], _s1_hit_ohs_T_15
wire s1_hit_ohs : UInt<1>[2][4]
connect s1_hit_ohs[0], _s1_hit_ohs_WIRE
connect s1_hit_ohs[1], _s1_hit_ohs_WIRE_1
connect s1_hit_ohs[2], _s1_hit_ohs_WIRE_2
connect s1_hit_ohs[3], _s1_hit_ohs_WIRE_3
node s1_hits_0 = or(s1_hit_ohs[0][0], s1_hit_ohs[0][1])
node s1_hits_1 = or(s1_hit_ohs[1][0], s1_hit_ohs[1][1])
node s1_hits_2 = or(s1_hit_ohs[2][0], s1_hit_ohs[2][1])
node s1_hits_3 = or(s1_hit_ohs[3][0], s1_hit_ohs[3][1])
node s1_hit_ways_0 = mux(s1_hit_ohs[0][0], UInt<1>(0h0), UInt<1>(0h1))
node s1_hit_ways_1 = mux(s1_hit_ohs[1][0], UInt<1>(0h0), UInt<1>(0h1))
node s1_hit_ways_2 = mux(s1_hit_ohs[2][0], UInt<1>(0h0), UInt<1>(0h1))
node s1_hit_ways_3 = mux(s1_hit_ohs[3][0], UInt<1>(0h0), UInt<1>(0h1))
node _s1_resp_0_valid_T = eq(doing_reset, UInt<1>(0h0))
node _s1_resp_0_valid_T_1 = and(_s1_resp_0_valid_T, s1_valid)
node _s1_resp_0_valid_T_2 = and(_s1_resp_0_valid_T_1, s1_hits_0)
connect s1_resp[0].valid, _s1_resp_0_valid_T_2
node _s1_resp_0_bits_T = asSInt(s1_pc)
node _s1_resp_0_bits_T_1 = add(_s1_resp_0_bits_T, asSInt(UInt<1>(0h0)))
node _s1_resp_0_bits_T_2 = tail(_s1_resp_0_bits_T_1, 1)
node _s1_resp_0_bits_T_3 = asSInt(_s1_resp_0_bits_T_2)
node _s1_resp_0_bits_T_4 = add(_s1_resp_0_bits_T_3, s1_req_rbtb[s1_hit_ways_0][0].offset)
node _s1_resp_0_bits_T_5 = tail(_s1_resp_0_bits_T_4, 1)
node _s1_resp_0_bits_T_6 = asSInt(_s1_resp_0_bits_T_5)
node _s1_resp_0_bits_T_7 = asUInt(_s1_resp_0_bits_T_6)
node _s1_resp_0_bits_T_8 = mux(s1_req_rbtb[s1_hit_ways_0][0].extended, s1_req_rebtb, _s1_resp_0_bits_T_7)
connect s1_resp[0].bits, _s1_resp_0_bits_T_8
node _s1_is_br_0_T = eq(doing_reset, UInt<1>(0h0))
node _s1_is_br_0_T_1 = and(_s1_is_br_0_T, s1_resp[0].valid)
node _s1_is_br_0_T_2 = and(_s1_is_br_0_T_1, s1_req_rmeta[s1_hit_ways_0][0].is_br)
connect s1_is_br[0], _s1_is_br_0_T_2
node _s1_is_jal_0_T = eq(doing_reset, UInt<1>(0h0))
node _s1_is_jal_0_T_1 = and(_s1_is_jal_0_T, s1_resp[0].valid)
node _s1_is_jal_0_T_2 = eq(s1_req_rmeta[s1_hit_ways_0][0].is_br, UInt<1>(0h0))
node _s1_is_jal_0_T_3 = and(_s1_is_jal_0_T_1, _s1_is_jal_0_T_2)
connect s1_is_jal[0], _s1_is_jal_0_T_3
connect io.resp.f2[0], io.resp_in[0].f2[0]
connect io.resp.f3[0], io.resp_in[0].f3[0]
reg REG : UInt<1>, clock
connect REG, s1_hits_0
when REG :
reg io_resp_f2_0_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock
connect io_resp_f2_0_predicted_pc_REG, s1_resp[0]
connect io.resp.f2[0].predicted_pc, io_resp_f2_0_predicted_pc_REG
reg io_resp_f2_0_is_br_REG : UInt<1>, clock
connect io_resp_f2_0_is_br_REG, s1_is_br[0]
connect io.resp.f2[0].is_br, io_resp_f2_0_is_br_REG
reg io_resp_f2_0_is_jal_REG : UInt<1>, clock
connect io_resp_f2_0_is_jal_REG, s1_is_jal[0]
connect io.resp.f2[0].is_jal, io_resp_f2_0_is_jal_REG
reg REG_1 : UInt<1>, clock
connect REG_1, s1_is_jal[0]
when REG_1 :
connect io.resp.f2[0].taken, UInt<1>(0h1)
reg REG_2 : UInt<1>, clock
connect REG_2, s1_hits_0
reg REG_3 : UInt<1>, clock
connect REG_3, REG_2
when REG_3 :
reg io_resp_f3_0_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock
connect io_resp_f3_0_predicted_pc_REG.bits, io.resp.f2[0].predicted_pc.bits
connect io_resp_f3_0_predicted_pc_REG.valid, io.resp.f2[0].predicted_pc.valid
connect io.resp.f3[0].predicted_pc, io_resp_f3_0_predicted_pc_REG
reg io_resp_f3_0_is_br_REG : UInt<1>, clock
connect io_resp_f3_0_is_br_REG, io.resp.f2[0].is_br
connect io.resp.f3[0].is_br, io_resp_f3_0_is_br_REG
reg io_resp_f3_0_is_jal_REG : UInt<1>, clock
connect io_resp_f3_0_is_jal_REG, io.resp.f2[0].is_jal
connect io.resp.f3[0].is_jal, io_resp_f3_0_is_jal_REG
reg REG_4 : UInt<1>, clock
connect REG_4, s1_is_jal[0]
reg REG_5 : UInt<1>, clock
connect REG_5, REG_4
when REG_5 :
connect io.resp.f3[0].taken, UInt<1>(0h1)
node _s1_resp_1_valid_T = eq(doing_reset, UInt<1>(0h0))
node _s1_resp_1_valid_T_1 = and(_s1_resp_1_valid_T, s1_valid)
node _s1_resp_1_valid_T_2 = and(_s1_resp_1_valid_T_1, s1_hits_1)
connect s1_resp[1].valid, _s1_resp_1_valid_T_2
node _s1_resp_1_bits_T = asSInt(s1_pc)
node _s1_resp_1_bits_T_1 = add(_s1_resp_1_bits_T, asSInt(UInt<3>(0h2)))
node _s1_resp_1_bits_T_2 = tail(_s1_resp_1_bits_T_1, 1)
node _s1_resp_1_bits_T_3 = asSInt(_s1_resp_1_bits_T_2)
node _s1_resp_1_bits_T_4 = add(_s1_resp_1_bits_T_3, s1_req_rbtb[s1_hit_ways_1][1].offset)
node _s1_resp_1_bits_T_5 = tail(_s1_resp_1_bits_T_4, 1)
node _s1_resp_1_bits_T_6 = asSInt(_s1_resp_1_bits_T_5)
node _s1_resp_1_bits_T_7 = asUInt(_s1_resp_1_bits_T_6)
node _s1_resp_1_bits_T_8 = mux(s1_req_rbtb[s1_hit_ways_1][1].extended, s1_req_rebtb, _s1_resp_1_bits_T_7)
connect s1_resp[1].bits, _s1_resp_1_bits_T_8
node _s1_is_br_1_T = eq(doing_reset, UInt<1>(0h0))
node _s1_is_br_1_T_1 = and(_s1_is_br_1_T, s1_resp[1].valid)
node _s1_is_br_1_T_2 = and(_s1_is_br_1_T_1, s1_req_rmeta[s1_hit_ways_1][1].is_br)
connect s1_is_br[1], _s1_is_br_1_T_2
node _s1_is_jal_1_T = eq(doing_reset, UInt<1>(0h0))
node _s1_is_jal_1_T_1 = and(_s1_is_jal_1_T, s1_resp[1].valid)
node _s1_is_jal_1_T_2 = eq(s1_req_rmeta[s1_hit_ways_1][1].is_br, UInt<1>(0h0))
node _s1_is_jal_1_T_3 = and(_s1_is_jal_1_T_1, _s1_is_jal_1_T_2)
connect s1_is_jal[1], _s1_is_jal_1_T_3
connect io.resp.f2[1], io.resp_in[0].f2[1]
connect io.resp.f3[1], io.resp_in[0].f3[1]
reg REG_6 : UInt<1>, clock
connect REG_6, s1_hits_1
when REG_6 :
reg io_resp_f2_1_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock
connect io_resp_f2_1_predicted_pc_REG, s1_resp[1]
connect io.resp.f2[1].predicted_pc, io_resp_f2_1_predicted_pc_REG
reg io_resp_f2_1_is_br_REG : UInt<1>, clock
connect io_resp_f2_1_is_br_REG, s1_is_br[1]
connect io.resp.f2[1].is_br, io_resp_f2_1_is_br_REG
reg io_resp_f2_1_is_jal_REG : UInt<1>, clock
connect io_resp_f2_1_is_jal_REG, s1_is_jal[1]
connect io.resp.f2[1].is_jal, io_resp_f2_1_is_jal_REG
reg REG_7 : UInt<1>, clock
connect REG_7, s1_is_jal[1]
when REG_7 :
connect io.resp.f2[1].taken, UInt<1>(0h1)
reg REG_8 : UInt<1>, clock
connect REG_8, s1_hits_1
reg REG_9 : UInt<1>, clock
connect REG_9, REG_8
when REG_9 :
reg io_resp_f3_1_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock
connect io_resp_f3_1_predicted_pc_REG.bits, io.resp.f2[1].predicted_pc.bits
connect io_resp_f3_1_predicted_pc_REG.valid, io.resp.f2[1].predicted_pc.valid
connect io.resp.f3[1].predicted_pc, io_resp_f3_1_predicted_pc_REG
reg io_resp_f3_1_is_br_REG : UInt<1>, clock
connect io_resp_f3_1_is_br_REG, io.resp.f2[1].is_br
connect io.resp.f3[1].is_br, io_resp_f3_1_is_br_REG
reg io_resp_f3_1_is_jal_REG : UInt<1>, clock
connect io_resp_f3_1_is_jal_REG, io.resp.f2[1].is_jal
connect io.resp.f3[1].is_jal, io_resp_f3_1_is_jal_REG
reg REG_10 : UInt<1>, clock
connect REG_10, s1_is_jal[1]
reg REG_11 : UInt<1>, clock
connect REG_11, REG_10
when REG_11 :
connect io.resp.f3[1].taken, UInt<1>(0h1)
node _s1_resp_2_valid_T = eq(doing_reset, UInt<1>(0h0))
node _s1_resp_2_valid_T_1 = and(_s1_resp_2_valid_T, s1_valid)
node _s1_resp_2_valid_T_2 = and(_s1_resp_2_valid_T_1, s1_hits_2)
connect s1_resp[2].valid, _s1_resp_2_valid_T_2
node _s1_resp_2_bits_T = asSInt(s1_pc)
node _s1_resp_2_bits_T_1 = add(_s1_resp_2_bits_T, asSInt(UInt<4>(0h4)))
node _s1_resp_2_bits_T_2 = tail(_s1_resp_2_bits_T_1, 1)
node _s1_resp_2_bits_T_3 = asSInt(_s1_resp_2_bits_T_2)
node _s1_resp_2_bits_T_4 = add(_s1_resp_2_bits_T_3, s1_req_rbtb[s1_hit_ways_2][2].offset)
node _s1_resp_2_bits_T_5 = tail(_s1_resp_2_bits_T_4, 1)
node _s1_resp_2_bits_T_6 = asSInt(_s1_resp_2_bits_T_5)
node _s1_resp_2_bits_T_7 = asUInt(_s1_resp_2_bits_T_6)
node _s1_resp_2_bits_T_8 = mux(s1_req_rbtb[s1_hit_ways_2][2].extended, s1_req_rebtb, _s1_resp_2_bits_T_7)
connect s1_resp[2].bits, _s1_resp_2_bits_T_8
node _s1_is_br_2_T = eq(doing_reset, UInt<1>(0h0))
node _s1_is_br_2_T_1 = and(_s1_is_br_2_T, s1_resp[2].valid)
node _s1_is_br_2_T_2 = and(_s1_is_br_2_T_1, s1_req_rmeta[s1_hit_ways_2][2].is_br)
connect s1_is_br[2], _s1_is_br_2_T_2
node _s1_is_jal_2_T = eq(doing_reset, UInt<1>(0h0))
node _s1_is_jal_2_T_1 = and(_s1_is_jal_2_T, s1_resp[2].valid)
node _s1_is_jal_2_T_2 = eq(s1_req_rmeta[s1_hit_ways_2][2].is_br, UInt<1>(0h0))
node _s1_is_jal_2_T_3 = and(_s1_is_jal_2_T_1, _s1_is_jal_2_T_2)
connect s1_is_jal[2], _s1_is_jal_2_T_3
connect io.resp.f2[2], io.resp_in[0].f2[2]
connect io.resp.f3[2], io.resp_in[0].f3[2]
reg REG_12 : UInt<1>, clock
connect REG_12, s1_hits_2
when REG_12 :
reg io_resp_f2_2_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock
connect io_resp_f2_2_predicted_pc_REG, s1_resp[2]
connect io.resp.f2[2].predicted_pc, io_resp_f2_2_predicted_pc_REG
reg io_resp_f2_2_is_br_REG : UInt<1>, clock
connect io_resp_f2_2_is_br_REG, s1_is_br[2]
connect io.resp.f2[2].is_br, io_resp_f2_2_is_br_REG
reg io_resp_f2_2_is_jal_REG : UInt<1>, clock
connect io_resp_f2_2_is_jal_REG, s1_is_jal[2]
connect io.resp.f2[2].is_jal, io_resp_f2_2_is_jal_REG
reg REG_13 : UInt<1>, clock
connect REG_13, s1_is_jal[2]
when REG_13 :
connect io.resp.f2[2].taken, UInt<1>(0h1)
reg REG_14 : UInt<1>, clock
connect REG_14, s1_hits_2
reg REG_15 : UInt<1>, clock
connect REG_15, REG_14
when REG_15 :
reg io_resp_f3_2_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock
connect io_resp_f3_2_predicted_pc_REG.bits, io.resp.f2[2].predicted_pc.bits
connect io_resp_f3_2_predicted_pc_REG.valid, io.resp.f2[2].predicted_pc.valid
connect io.resp.f3[2].predicted_pc, io_resp_f3_2_predicted_pc_REG
reg io_resp_f3_2_is_br_REG : UInt<1>, clock
connect io_resp_f3_2_is_br_REG, io.resp.f2[2].is_br
connect io.resp.f3[2].is_br, io_resp_f3_2_is_br_REG
reg io_resp_f3_2_is_jal_REG : UInt<1>, clock
connect io_resp_f3_2_is_jal_REG, io.resp.f2[2].is_jal
connect io.resp.f3[2].is_jal, io_resp_f3_2_is_jal_REG
reg REG_16 : UInt<1>, clock
connect REG_16, s1_is_jal[2]
reg REG_17 : UInt<1>, clock
connect REG_17, REG_16
when REG_17 :
connect io.resp.f3[2].taken, UInt<1>(0h1)
node _s1_resp_3_valid_T = eq(doing_reset, UInt<1>(0h0))
node _s1_resp_3_valid_T_1 = and(_s1_resp_3_valid_T, s1_valid)
node _s1_resp_3_valid_T_2 = and(_s1_resp_3_valid_T_1, s1_hits_3)
connect s1_resp[3].valid, _s1_resp_3_valid_T_2
node _s1_resp_3_bits_T = asSInt(s1_pc)
node _s1_resp_3_bits_T_1 = add(_s1_resp_3_bits_T, asSInt(UInt<4>(0h6)))
node _s1_resp_3_bits_T_2 = tail(_s1_resp_3_bits_T_1, 1)
node _s1_resp_3_bits_T_3 = asSInt(_s1_resp_3_bits_T_2)
node _s1_resp_3_bits_T_4 = add(_s1_resp_3_bits_T_3, s1_req_rbtb[s1_hit_ways_3][3].offset)
node _s1_resp_3_bits_T_5 = tail(_s1_resp_3_bits_T_4, 1)
node _s1_resp_3_bits_T_6 = asSInt(_s1_resp_3_bits_T_5)
node _s1_resp_3_bits_T_7 = asUInt(_s1_resp_3_bits_T_6)
node _s1_resp_3_bits_T_8 = mux(s1_req_rbtb[s1_hit_ways_3][3].extended, s1_req_rebtb, _s1_resp_3_bits_T_7)
connect s1_resp[3].bits, _s1_resp_3_bits_T_8
node _s1_is_br_3_T = eq(doing_reset, UInt<1>(0h0))
node _s1_is_br_3_T_1 = and(_s1_is_br_3_T, s1_resp[3].valid)
node _s1_is_br_3_T_2 = and(_s1_is_br_3_T_1, s1_req_rmeta[s1_hit_ways_3][3].is_br)
connect s1_is_br[3], _s1_is_br_3_T_2
node _s1_is_jal_3_T = eq(doing_reset, UInt<1>(0h0))
node _s1_is_jal_3_T_1 = and(_s1_is_jal_3_T, s1_resp[3].valid)
node _s1_is_jal_3_T_2 = eq(s1_req_rmeta[s1_hit_ways_3][3].is_br, UInt<1>(0h0))
node _s1_is_jal_3_T_3 = and(_s1_is_jal_3_T_1, _s1_is_jal_3_T_2)
connect s1_is_jal[3], _s1_is_jal_3_T_3
connect io.resp.f2[3], io.resp_in[0].f2[3]
connect io.resp.f3[3], io.resp_in[0].f3[3]
reg REG_18 : UInt<1>, clock
connect REG_18, s1_hits_3
when REG_18 :
reg io_resp_f2_3_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock
connect io_resp_f2_3_predicted_pc_REG, s1_resp[3]
connect io.resp.f2[3].predicted_pc, io_resp_f2_3_predicted_pc_REG
reg io_resp_f2_3_is_br_REG : UInt<1>, clock
connect io_resp_f2_3_is_br_REG, s1_is_br[3]
connect io.resp.f2[3].is_br, io_resp_f2_3_is_br_REG
reg io_resp_f2_3_is_jal_REG : UInt<1>, clock
connect io_resp_f2_3_is_jal_REG, s1_is_jal[3]
connect io.resp.f2[3].is_jal, io_resp_f2_3_is_jal_REG
reg REG_19 : UInt<1>, clock
connect REG_19, s1_is_jal[3]
when REG_19 :
connect io.resp.f2[3].taken, UInt<1>(0h1)
reg REG_20 : UInt<1>, clock
connect REG_20, s1_hits_3
reg REG_21 : UInt<1>, clock
connect REG_21, REG_20
when REG_21 :
reg io_resp_f3_3_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock
connect io_resp_f3_3_predicted_pc_REG.bits, io.resp.f2[3].predicted_pc.bits
connect io_resp_f3_3_predicted_pc_REG.valid, io.resp.f2[3].predicted_pc.valid
connect io.resp.f3[3].predicted_pc, io_resp_f3_3_predicted_pc_REG
reg io_resp_f3_3_is_br_REG : UInt<1>, clock
connect io_resp_f3_3_is_br_REG, io.resp.f2[3].is_br
connect io.resp.f3[3].is_br, io_resp_f3_3_is_br_REG
reg io_resp_f3_3_is_jal_REG : UInt<1>, clock
connect io_resp_f3_3_is_jal_REG, io.resp.f2[3].is_jal
connect io.resp.f3[3].is_jal, io_resp_f3_3_is_jal_REG
reg REG_22 : UInt<1>, clock
connect REG_22, s1_is_jal[3]
reg REG_23 : UInt<1>, clock
connect REG_23, REG_22
when REG_23 :
connect io.resp.f3[3].taken, UInt<1>(0h1)
wire _alloc_way_r_metas_WIRE : UInt<29>[4]
connect _alloc_way_r_metas_WIRE[0], s1_req_rmeta[0][0].tag
connect _alloc_way_r_metas_WIRE[1], s1_req_rmeta[0][1].tag
connect _alloc_way_r_metas_WIRE[2], s1_req_rmeta[0][2].tag
connect _alloc_way_r_metas_WIRE[3], s1_req_rmeta[0][3].tag
wire _alloc_way_r_metas_WIRE_1 : UInt<29>[4]
connect _alloc_way_r_metas_WIRE_1[0], s1_req_rmeta[1][0].tag
connect _alloc_way_r_metas_WIRE_1[1], s1_req_rmeta[1][1].tag
connect _alloc_way_r_metas_WIRE_1[2], s1_req_rmeta[1][2].tag
connect _alloc_way_r_metas_WIRE_1[3], s1_req_rmeta[1][3].tag
wire _alloc_way_r_metas_WIRE_2 : UInt<29>[4][2]
connect _alloc_way_r_metas_WIRE_2[0], _alloc_way_r_metas_WIRE
connect _alloc_way_r_metas_WIRE_2[1], _alloc_way_r_metas_WIRE_1
node alloc_way_r_metas_lo = cat(_alloc_way_r_metas_WIRE_2[0][1], _alloc_way_r_metas_WIRE_2[0][0])
node alloc_way_r_metas_hi = cat(_alloc_way_r_metas_WIRE_2[0][3], _alloc_way_r_metas_WIRE_2[0][2])
node _alloc_way_r_metas_T = cat(alloc_way_r_metas_hi, alloc_way_r_metas_lo)
node alloc_way_r_metas_lo_1 = cat(_alloc_way_r_metas_WIRE_2[1][1], _alloc_way_r_metas_WIRE_2[1][0])
node alloc_way_r_metas_hi_1 = cat(_alloc_way_r_metas_WIRE_2[1][3], _alloc_way_r_metas_WIRE_2[1][2])
node _alloc_way_r_metas_T_1 = cat(alloc_way_r_metas_hi_1, alloc_way_r_metas_lo_1)
node _alloc_way_r_metas_T_2 = cat(_alloc_way_r_metas_T_1, _alloc_way_r_metas_T)
node _alloc_way_r_metas_T_3 = bits(s1_req_tag, 28, 0)
node alloc_way_r_metas = cat(_alloc_way_r_metas_T_2, _alloc_way_r_metas_T_3)
node alloc_way_chunks_0 = bits(alloc_way_r_metas, 0, 0)
node alloc_way_chunks_1 = bits(alloc_way_r_metas, 1, 1)
node alloc_way_chunks_2 = bits(alloc_way_r_metas, 2, 2)
node alloc_way_chunks_3 = bits(alloc_way_r_metas, 3, 3)
node alloc_way_chunks_4 = bits(alloc_way_r_metas, 4, 4)
node alloc_way_chunks_5 = bits(alloc_way_r_metas, 5, 5)
node alloc_way_chunks_6 = bits(alloc_way_r_metas, 6, 6)
node alloc_way_chunks_7 = bits(alloc_way_r_metas, 7, 7)
node alloc_way_chunks_8 = bits(alloc_way_r_metas, 8, 8)
node alloc_way_chunks_9 = bits(alloc_way_r_metas, 9, 9)
node alloc_way_chunks_10 = bits(alloc_way_r_metas, 10, 10)
node alloc_way_chunks_11 = bits(alloc_way_r_metas, 11, 11)
node alloc_way_chunks_12 = bits(alloc_way_r_metas, 12, 12)
node alloc_way_chunks_13 = bits(alloc_way_r_metas, 13, 13)
node alloc_way_chunks_14 = bits(alloc_way_r_metas, 14, 14)
node alloc_way_chunks_15 = bits(alloc_way_r_metas, 15, 15)
node alloc_way_chunks_16 = bits(alloc_way_r_metas, 16, 16)
node alloc_way_chunks_17 = bits(alloc_way_r_metas, 17, 17)
node alloc_way_chunks_18 = bits(alloc_way_r_metas, 18, 18)
node alloc_way_chunks_19 = bits(alloc_way_r_metas, 19, 19)
node alloc_way_chunks_20 = bits(alloc_way_r_metas, 20, 20)
node alloc_way_chunks_21 = bits(alloc_way_r_metas, 21, 21)
node alloc_way_chunks_22 = bits(alloc_way_r_metas, 22, 22)
node alloc_way_chunks_23 = bits(alloc_way_r_metas, 23, 23)
node alloc_way_chunks_24 = bits(alloc_way_r_metas, 24, 24)
node alloc_way_chunks_25 = bits(alloc_way_r_metas, 25, 25)
node alloc_way_chunks_26 = bits(alloc_way_r_metas, 26, 26)
node alloc_way_chunks_27 = bits(alloc_way_r_metas, 27, 27)
node alloc_way_chunks_28 = bits(alloc_way_r_metas, 28, 28)
node alloc_way_chunks_29 = bits(alloc_way_r_metas, 29, 29)
node alloc_way_chunks_30 = bits(alloc_way_r_metas, 30, 30)
node alloc_way_chunks_31 = bits(alloc_way_r_metas, 31, 31)
node alloc_way_chunks_32 = bits(alloc_way_r_metas, 32, 32)
node alloc_way_chunks_33 = bits(alloc_way_r_metas, 33, 33)
node alloc_way_chunks_34 = bits(alloc_way_r_metas, 34, 34)
node alloc_way_chunks_35 = bits(alloc_way_r_metas, 35, 35)
node alloc_way_chunks_36 = bits(alloc_way_r_metas, 36, 36)
node alloc_way_chunks_37 = bits(alloc_way_r_metas, 37, 37)
node alloc_way_chunks_38 = bits(alloc_way_r_metas, 38, 38)
node alloc_way_chunks_39 = bits(alloc_way_r_metas, 39, 39)
node alloc_way_chunks_40 = bits(alloc_way_r_metas, 40, 40)
node alloc_way_chunks_41 = bits(alloc_way_r_metas, 41, 41)
node alloc_way_chunks_42 = bits(alloc_way_r_metas, 42, 42)
node alloc_way_chunks_43 = bits(alloc_way_r_metas, 43, 43)
node alloc_way_chunks_44 = bits(alloc_way_r_metas, 44, 44)
node alloc_way_chunks_45 = bits(alloc_way_r_metas, 45, 45)
node alloc_way_chunks_46 = bits(alloc_way_r_metas, 46, 46)
node alloc_way_chunks_47 = bits(alloc_way_r_metas, 47, 47)
node alloc_way_chunks_48 = bits(alloc_way_r_metas, 48, 48)
node alloc_way_chunks_49 = bits(alloc_way_r_metas, 49, 49)
node alloc_way_chunks_50 = bits(alloc_way_r_metas, 50, 50)
node alloc_way_chunks_51 = bits(alloc_way_r_metas, 51, 51)
node alloc_way_chunks_52 = bits(alloc_way_r_metas, 52, 52)
node alloc_way_chunks_53 = bits(alloc_way_r_metas, 53, 53)
node alloc_way_chunks_54 = bits(alloc_way_r_metas, 54, 54)
node alloc_way_chunks_55 = bits(alloc_way_r_metas, 55, 55)
node alloc_way_chunks_56 = bits(alloc_way_r_metas, 56, 56)
node alloc_way_chunks_57 = bits(alloc_way_r_metas, 57, 57)
node alloc_way_chunks_58 = bits(alloc_way_r_metas, 58, 58)
node alloc_way_chunks_59 = bits(alloc_way_r_metas, 59, 59)
node alloc_way_chunks_60 = bits(alloc_way_r_metas, 60, 60)
node alloc_way_chunks_61 = bits(alloc_way_r_metas, 61, 61)
node alloc_way_chunks_62 = bits(alloc_way_r_metas, 62, 62)
node alloc_way_chunks_63 = bits(alloc_way_r_metas, 63, 63)
node alloc_way_chunks_64 = bits(alloc_way_r_metas, 64, 64)
node alloc_way_chunks_65 = bits(alloc_way_r_metas, 65, 65)
node alloc_way_chunks_66 = bits(alloc_way_r_metas, 66, 66)
node alloc_way_chunks_67 = bits(alloc_way_r_metas, 67, 67)
node alloc_way_chunks_68 = bits(alloc_way_r_metas, 68, 68)
node alloc_way_chunks_69 = bits(alloc_way_r_metas, 69, 69)
node alloc_way_chunks_70 = bits(alloc_way_r_metas, 70, 70)
node alloc_way_chunks_71 = bits(alloc_way_r_metas, 71, 71)
node alloc_way_chunks_72 = bits(alloc_way_r_metas, 72, 72)
node alloc_way_chunks_73 = bits(alloc_way_r_metas, 73, 73)
node alloc_way_chunks_74 = bits(alloc_way_r_metas, 74, 74)
node alloc_way_chunks_75 = bits(alloc_way_r_metas, 75, 75)
node alloc_way_chunks_76 = bits(alloc_way_r_metas, 76, 76)
node alloc_way_chunks_77 = bits(alloc_way_r_metas, 77, 77)
node alloc_way_chunks_78 = bits(alloc_way_r_metas, 78, 78)
node alloc_way_chunks_79 = bits(alloc_way_r_metas, 79, 79)
node alloc_way_chunks_80 = bits(alloc_way_r_metas, 80, 80)
node alloc_way_chunks_81 = bits(alloc_way_r_metas, 81, 81)
node alloc_way_chunks_82 = bits(alloc_way_r_metas, 82, 82)
node alloc_way_chunks_83 = bits(alloc_way_r_metas, 83, 83)
node alloc_way_chunks_84 = bits(alloc_way_r_metas, 84, 84)
node alloc_way_chunks_85 = bits(alloc_way_r_metas, 85, 85)
node alloc_way_chunks_86 = bits(alloc_way_r_metas, 86, 86)
node alloc_way_chunks_87 = bits(alloc_way_r_metas, 87, 87)
node alloc_way_chunks_88 = bits(alloc_way_r_metas, 88, 88)
node alloc_way_chunks_89 = bits(alloc_way_r_metas, 89, 89)
node alloc_way_chunks_90 = bits(alloc_way_r_metas, 90, 90)
node alloc_way_chunks_91 = bits(alloc_way_r_metas, 91, 91)
node alloc_way_chunks_92 = bits(alloc_way_r_metas, 92, 92)
node alloc_way_chunks_93 = bits(alloc_way_r_metas, 93, 93)
node alloc_way_chunks_94 = bits(alloc_way_r_metas, 94, 94)
node alloc_way_chunks_95 = bits(alloc_way_r_metas, 95, 95)
node alloc_way_chunks_96 = bits(alloc_way_r_metas, 96, 96)
node alloc_way_chunks_97 = bits(alloc_way_r_metas, 97, 97)
node alloc_way_chunks_98 = bits(alloc_way_r_metas, 98, 98)
node alloc_way_chunks_99 = bits(alloc_way_r_metas, 99, 99)
node alloc_way_chunks_100 = bits(alloc_way_r_metas, 100, 100)
node alloc_way_chunks_101 = bits(alloc_way_r_metas, 101, 101)
node alloc_way_chunks_102 = bits(alloc_way_r_metas, 102, 102)
node alloc_way_chunks_103 = bits(alloc_way_r_metas, 103, 103)
node alloc_way_chunks_104 = bits(alloc_way_r_metas, 104, 104)
node alloc_way_chunks_105 = bits(alloc_way_r_metas, 105, 105)
node alloc_way_chunks_106 = bits(alloc_way_r_metas, 106, 106)
node alloc_way_chunks_107 = bits(alloc_way_r_metas, 107, 107)
node alloc_way_chunks_108 = bits(alloc_way_r_metas, 108, 108)
node alloc_way_chunks_109 = bits(alloc_way_r_metas, 109, 109)
node alloc_way_chunks_110 = bits(alloc_way_r_metas, 110, 110)
node alloc_way_chunks_111 = bits(alloc_way_r_metas, 111, 111)
node alloc_way_chunks_112 = bits(alloc_way_r_metas, 112, 112)
node alloc_way_chunks_113 = bits(alloc_way_r_metas, 113, 113)
node alloc_way_chunks_114 = bits(alloc_way_r_metas, 114, 114)
node alloc_way_chunks_115 = bits(alloc_way_r_metas, 115, 115)
node alloc_way_chunks_116 = bits(alloc_way_r_metas, 116, 116)
node alloc_way_chunks_117 = bits(alloc_way_r_metas, 117, 117)
node alloc_way_chunks_118 = bits(alloc_way_r_metas, 118, 118)
node alloc_way_chunks_119 = bits(alloc_way_r_metas, 119, 119)
node alloc_way_chunks_120 = bits(alloc_way_r_metas, 120, 120)
node alloc_way_chunks_121 = bits(alloc_way_r_metas, 121, 121)
node alloc_way_chunks_122 = bits(alloc_way_r_metas, 122, 122)
node alloc_way_chunks_123 = bits(alloc_way_r_metas, 123, 123)
node alloc_way_chunks_124 = bits(alloc_way_r_metas, 124, 124)
node alloc_way_chunks_125 = bits(alloc_way_r_metas, 125, 125)
node alloc_way_chunks_126 = bits(alloc_way_r_metas, 126, 126)
node alloc_way_chunks_127 = bits(alloc_way_r_metas, 127, 127)
node alloc_way_chunks_128 = bits(alloc_way_r_metas, 128, 128)
node alloc_way_chunks_129 = bits(alloc_way_r_metas, 129, 129)
node alloc_way_chunks_130 = bits(alloc_way_r_metas, 130, 130)
node alloc_way_chunks_131 = bits(alloc_way_r_metas, 131, 131)
node alloc_way_chunks_132 = bits(alloc_way_r_metas, 132, 132)
node alloc_way_chunks_133 = bits(alloc_way_r_metas, 133, 133)
node alloc_way_chunks_134 = bits(alloc_way_r_metas, 134, 134)
node alloc_way_chunks_135 = bits(alloc_way_r_metas, 135, 135)
node alloc_way_chunks_136 = bits(alloc_way_r_metas, 136, 136)
node alloc_way_chunks_137 = bits(alloc_way_r_metas, 137, 137)
node alloc_way_chunks_138 = bits(alloc_way_r_metas, 138, 138)
node alloc_way_chunks_139 = bits(alloc_way_r_metas, 139, 139)
node alloc_way_chunks_140 = bits(alloc_way_r_metas, 140, 140)
node alloc_way_chunks_141 = bits(alloc_way_r_metas, 141, 141)
node alloc_way_chunks_142 = bits(alloc_way_r_metas, 142, 142)
node alloc_way_chunks_143 = bits(alloc_way_r_metas, 143, 143)
node alloc_way_chunks_144 = bits(alloc_way_r_metas, 144, 144)
node alloc_way_chunks_145 = bits(alloc_way_r_metas, 145, 145)
node alloc_way_chunks_146 = bits(alloc_way_r_metas, 146, 146)
node alloc_way_chunks_147 = bits(alloc_way_r_metas, 147, 147)
node alloc_way_chunks_148 = bits(alloc_way_r_metas, 148, 148)
node alloc_way_chunks_149 = bits(alloc_way_r_metas, 149, 149)
node alloc_way_chunks_150 = bits(alloc_way_r_metas, 150, 150)
node alloc_way_chunks_151 = bits(alloc_way_r_metas, 151, 151)
node alloc_way_chunks_152 = bits(alloc_way_r_metas, 152, 152)
node alloc_way_chunks_153 = bits(alloc_way_r_metas, 153, 153)
node alloc_way_chunks_154 = bits(alloc_way_r_metas, 154, 154)
node alloc_way_chunks_155 = bits(alloc_way_r_metas, 155, 155)
node alloc_way_chunks_156 = bits(alloc_way_r_metas, 156, 156)
node alloc_way_chunks_157 = bits(alloc_way_r_metas, 157, 157)
node alloc_way_chunks_158 = bits(alloc_way_r_metas, 158, 158)
node alloc_way_chunks_159 = bits(alloc_way_r_metas, 159, 159)
node alloc_way_chunks_160 = bits(alloc_way_r_metas, 160, 160)
node alloc_way_chunks_161 = bits(alloc_way_r_metas, 161, 161)
node alloc_way_chunks_162 = bits(alloc_way_r_metas, 162, 162)
node alloc_way_chunks_163 = bits(alloc_way_r_metas, 163, 163)
node alloc_way_chunks_164 = bits(alloc_way_r_metas, 164, 164)
node alloc_way_chunks_165 = bits(alloc_way_r_metas, 165, 165)
node alloc_way_chunks_166 = bits(alloc_way_r_metas, 166, 166)
node alloc_way_chunks_167 = bits(alloc_way_r_metas, 167, 167)
node alloc_way_chunks_168 = bits(alloc_way_r_metas, 168, 168)
node alloc_way_chunks_169 = bits(alloc_way_r_metas, 169, 169)
node alloc_way_chunks_170 = bits(alloc_way_r_metas, 170, 170)
node alloc_way_chunks_171 = bits(alloc_way_r_metas, 171, 171)
node alloc_way_chunks_172 = bits(alloc_way_r_metas, 172, 172)
node alloc_way_chunks_173 = bits(alloc_way_r_metas, 173, 173)
node alloc_way_chunks_174 = bits(alloc_way_r_metas, 174, 174)
node alloc_way_chunks_175 = bits(alloc_way_r_metas, 175, 175)
node alloc_way_chunks_176 = bits(alloc_way_r_metas, 176, 176)
node alloc_way_chunks_177 = bits(alloc_way_r_metas, 177, 177)
node alloc_way_chunks_178 = bits(alloc_way_r_metas, 178, 178)
node alloc_way_chunks_179 = bits(alloc_way_r_metas, 179, 179)
node alloc_way_chunks_180 = bits(alloc_way_r_metas, 180, 180)
node alloc_way_chunks_181 = bits(alloc_way_r_metas, 181, 181)
node alloc_way_chunks_182 = bits(alloc_way_r_metas, 182, 182)
node alloc_way_chunks_183 = bits(alloc_way_r_metas, 183, 183)
node alloc_way_chunks_184 = bits(alloc_way_r_metas, 184, 184)
node alloc_way_chunks_185 = bits(alloc_way_r_metas, 185, 185)
node alloc_way_chunks_186 = bits(alloc_way_r_metas, 186, 186)
node alloc_way_chunks_187 = bits(alloc_way_r_metas, 187, 187)
node alloc_way_chunks_188 = bits(alloc_way_r_metas, 188, 188)
node alloc_way_chunks_189 = bits(alloc_way_r_metas, 189, 189)
node alloc_way_chunks_190 = bits(alloc_way_r_metas, 190, 190)
node alloc_way_chunks_191 = bits(alloc_way_r_metas, 191, 191)
node alloc_way_chunks_192 = bits(alloc_way_r_metas, 192, 192)
node alloc_way_chunks_193 = bits(alloc_way_r_metas, 193, 193)
node alloc_way_chunks_194 = bits(alloc_way_r_metas, 194, 194)
node alloc_way_chunks_195 = bits(alloc_way_r_metas, 195, 195)
node alloc_way_chunks_196 = bits(alloc_way_r_metas, 196, 196)
node alloc_way_chunks_197 = bits(alloc_way_r_metas, 197, 197)
node alloc_way_chunks_198 = bits(alloc_way_r_metas, 198, 198)
node alloc_way_chunks_199 = bits(alloc_way_r_metas, 199, 199)
node alloc_way_chunks_200 = bits(alloc_way_r_metas, 200, 200)
node alloc_way_chunks_201 = bits(alloc_way_r_metas, 201, 201)
node alloc_way_chunks_202 = bits(alloc_way_r_metas, 202, 202)
node alloc_way_chunks_203 = bits(alloc_way_r_metas, 203, 203)
node alloc_way_chunks_204 = bits(alloc_way_r_metas, 204, 204)
node alloc_way_chunks_205 = bits(alloc_way_r_metas, 205, 205)
node alloc_way_chunks_206 = bits(alloc_way_r_metas, 206, 206)
node alloc_way_chunks_207 = bits(alloc_way_r_metas, 207, 207)
node alloc_way_chunks_208 = bits(alloc_way_r_metas, 208, 208)
node alloc_way_chunks_209 = bits(alloc_way_r_metas, 209, 209)
node alloc_way_chunks_210 = bits(alloc_way_r_metas, 210, 210)
node alloc_way_chunks_211 = bits(alloc_way_r_metas, 211, 211)
node alloc_way_chunks_212 = bits(alloc_way_r_metas, 212, 212)
node alloc_way_chunks_213 = bits(alloc_way_r_metas, 213, 213)
node alloc_way_chunks_214 = bits(alloc_way_r_metas, 214, 214)
node alloc_way_chunks_215 = bits(alloc_way_r_metas, 215, 215)
node alloc_way_chunks_216 = bits(alloc_way_r_metas, 216, 216)
node alloc_way_chunks_217 = bits(alloc_way_r_metas, 217, 217)
node alloc_way_chunks_218 = bits(alloc_way_r_metas, 218, 218)
node alloc_way_chunks_219 = bits(alloc_way_r_metas, 219, 219)
node alloc_way_chunks_220 = bits(alloc_way_r_metas, 220, 220)
node alloc_way_chunks_221 = bits(alloc_way_r_metas, 221, 221)
node alloc_way_chunks_222 = bits(alloc_way_r_metas, 222, 222)
node alloc_way_chunks_223 = bits(alloc_way_r_metas, 223, 223)
node alloc_way_chunks_224 = bits(alloc_way_r_metas, 224, 224)
node alloc_way_chunks_225 = bits(alloc_way_r_metas, 225, 225)
node alloc_way_chunks_226 = bits(alloc_way_r_metas, 226, 226)
node alloc_way_chunks_227 = bits(alloc_way_r_metas, 227, 227)
node alloc_way_chunks_228 = bits(alloc_way_r_metas, 228, 228)
node alloc_way_chunks_229 = bits(alloc_way_r_metas, 229, 229)
node alloc_way_chunks_230 = bits(alloc_way_r_metas, 230, 230)
node alloc_way_chunks_231 = bits(alloc_way_r_metas, 231, 231)
node alloc_way_chunks_232 = bits(alloc_way_r_metas, 232, 232)
node alloc_way_chunks_233 = bits(alloc_way_r_metas, 233, 233)
node alloc_way_chunks_234 = bits(alloc_way_r_metas, 234, 234)
node alloc_way_chunks_235 = bits(alloc_way_r_metas, 235, 235)
node alloc_way_chunks_236 = bits(alloc_way_r_metas, 236, 236)
node alloc_way_chunks_237 = bits(alloc_way_r_metas, 237, 237)
node alloc_way_chunks_238 = bits(alloc_way_r_metas, 238, 238)
node alloc_way_chunks_239 = bits(alloc_way_r_metas, 239, 239)
node alloc_way_chunks_240 = bits(alloc_way_r_metas, 240, 240)
node alloc_way_chunks_241 = bits(alloc_way_r_metas, 241, 241)
node alloc_way_chunks_242 = bits(alloc_way_r_metas, 242, 242)
node alloc_way_chunks_243 = bits(alloc_way_r_metas, 243, 243)
node alloc_way_chunks_244 = bits(alloc_way_r_metas, 244, 244)
node alloc_way_chunks_245 = bits(alloc_way_r_metas, 245, 245)
node alloc_way_chunks_246 = bits(alloc_way_r_metas, 246, 246)
node alloc_way_chunks_247 = bits(alloc_way_r_metas, 247, 247)
node alloc_way_chunks_248 = bits(alloc_way_r_metas, 248, 248)
node alloc_way_chunks_249 = bits(alloc_way_r_metas, 249, 249)
node alloc_way_chunks_250 = bits(alloc_way_r_metas, 250, 250)
node alloc_way_chunks_251 = bits(alloc_way_r_metas, 251, 251)
node alloc_way_chunks_252 = bits(alloc_way_r_metas, 252, 252)
node alloc_way_chunks_253 = bits(alloc_way_r_metas, 253, 253)
node alloc_way_chunks_254 = bits(alloc_way_r_metas, 254, 254)
node alloc_way_chunks_255 = bits(alloc_way_r_metas, 255, 255)
node alloc_way_chunks_256 = bits(alloc_way_r_metas, 256, 256)
node alloc_way_chunks_257 = bits(alloc_way_r_metas, 257, 257)
node alloc_way_chunks_258 = bits(alloc_way_r_metas, 258, 258)
node alloc_way_chunks_259 = bits(alloc_way_r_metas, 259, 259)
node alloc_way_chunks_260 = bits(alloc_way_r_metas, 260, 260)
node _alloc_way_T = xor(alloc_way_chunks_0, alloc_way_chunks_1)
node _alloc_way_T_1 = xor(_alloc_way_T, alloc_way_chunks_2)
node _alloc_way_T_2 = xor(_alloc_way_T_1, alloc_way_chunks_3)
node _alloc_way_T_3 = xor(_alloc_way_T_2, alloc_way_chunks_4)
node _alloc_way_T_4 = xor(_alloc_way_T_3, alloc_way_chunks_5)
node _alloc_way_T_5 = xor(_alloc_way_T_4, alloc_way_chunks_6)
node _alloc_way_T_6 = xor(_alloc_way_T_5, alloc_way_chunks_7)
node _alloc_way_T_7 = xor(_alloc_way_T_6, alloc_way_chunks_8)
node _alloc_way_T_8 = xor(_alloc_way_T_7, alloc_way_chunks_9)
node _alloc_way_T_9 = xor(_alloc_way_T_8, alloc_way_chunks_10)
node _alloc_way_T_10 = xor(_alloc_way_T_9, alloc_way_chunks_11)
node _alloc_way_T_11 = xor(_alloc_way_T_10, alloc_way_chunks_12)
node _alloc_way_T_12 = xor(_alloc_way_T_11, alloc_way_chunks_13)
node _alloc_way_T_13 = xor(_alloc_way_T_12, alloc_way_chunks_14)
node _alloc_way_T_14 = xor(_alloc_way_T_13, alloc_way_chunks_15)
node _alloc_way_T_15 = xor(_alloc_way_T_14, alloc_way_chunks_16)
node _alloc_way_T_16 = xor(_alloc_way_T_15, alloc_way_chunks_17)
node _alloc_way_T_17 = xor(_alloc_way_T_16, alloc_way_chunks_18)
node _alloc_way_T_18 = xor(_alloc_way_T_17, alloc_way_chunks_19)
node _alloc_way_T_19 = xor(_alloc_way_T_18, alloc_way_chunks_20)
node _alloc_way_T_20 = xor(_alloc_way_T_19, alloc_way_chunks_21)
node _alloc_way_T_21 = xor(_alloc_way_T_20, alloc_way_chunks_22)
node _alloc_way_T_22 = xor(_alloc_way_T_21, alloc_way_chunks_23)
node _alloc_way_T_23 = xor(_alloc_way_T_22, alloc_way_chunks_24)
node _alloc_way_T_24 = xor(_alloc_way_T_23, alloc_way_chunks_25)
node _alloc_way_T_25 = xor(_alloc_way_T_24, alloc_way_chunks_26)
node _alloc_way_T_26 = xor(_alloc_way_T_25, alloc_way_chunks_27)
node _alloc_way_T_27 = xor(_alloc_way_T_26, alloc_way_chunks_28)
node _alloc_way_T_28 = xor(_alloc_way_T_27, alloc_way_chunks_29)
node _alloc_way_T_29 = xor(_alloc_way_T_28, alloc_way_chunks_30)
node _alloc_way_T_30 = xor(_alloc_way_T_29, alloc_way_chunks_31)
node _alloc_way_T_31 = xor(_alloc_way_T_30, alloc_way_chunks_32)
node _alloc_way_T_32 = xor(_alloc_way_T_31, alloc_way_chunks_33)
node _alloc_way_T_33 = xor(_alloc_way_T_32, alloc_way_chunks_34)
node _alloc_way_T_34 = xor(_alloc_way_T_33, alloc_way_chunks_35)
node _alloc_way_T_35 = xor(_alloc_way_T_34, alloc_way_chunks_36)
node _alloc_way_T_36 = xor(_alloc_way_T_35, alloc_way_chunks_37)
node _alloc_way_T_37 = xor(_alloc_way_T_36, alloc_way_chunks_38)
node _alloc_way_T_38 = xor(_alloc_way_T_37, alloc_way_chunks_39)
node _alloc_way_T_39 = xor(_alloc_way_T_38, alloc_way_chunks_40)
node _alloc_way_T_40 = xor(_alloc_way_T_39, alloc_way_chunks_41)
node _alloc_way_T_41 = xor(_alloc_way_T_40, alloc_way_chunks_42)
node _alloc_way_T_42 = xor(_alloc_way_T_41, alloc_way_chunks_43)
node _alloc_way_T_43 = xor(_alloc_way_T_42, alloc_way_chunks_44)
node _alloc_way_T_44 = xor(_alloc_way_T_43, alloc_way_chunks_45)
node _alloc_way_T_45 = xor(_alloc_way_T_44, alloc_way_chunks_46)
node _alloc_way_T_46 = xor(_alloc_way_T_45, alloc_way_chunks_47)
node _alloc_way_T_47 = xor(_alloc_way_T_46, alloc_way_chunks_48)
node _alloc_way_T_48 = xor(_alloc_way_T_47, alloc_way_chunks_49)
node _alloc_way_T_49 = xor(_alloc_way_T_48, alloc_way_chunks_50)
node _alloc_way_T_50 = xor(_alloc_way_T_49, alloc_way_chunks_51)
node _alloc_way_T_51 = xor(_alloc_way_T_50, alloc_way_chunks_52)
node _alloc_way_T_52 = xor(_alloc_way_T_51, alloc_way_chunks_53)
node _alloc_way_T_53 = xor(_alloc_way_T_52, alloc_way_chunks_54)
node _alloc_way_T_54 = xor(_alloc_way_T_53, alloc_way_chunks_55)
node _alloc_way_T_55 = xor(_alloc_way_T_54, alloc_way_chunks_56)
node _alloc_way_T_56 = xor(_alloc_way_T_55, alloc_way_chunks_57)
node _alloc_way_T_57 = xor(_alloc_way_T_56, alloc_way_chunks_58)
node _alloc_way_T_58 = xor(_alloc_way_T_57, alloc_way_chunks_59)
node _alloc_way_T_59 = xor(_alloc_way_T_58, alloc_way_chunks_60)
node _alloc_way_T_60 = xor(_alloc_way_T_59, alloc_way_chunks_61)
node _alloc_way_T_61 = xor(_alloc_way_T_60, alloc_way_chunks_62)
node _alloc_way_T_62 = xor(_alloc_way_T_61, alloc_way_chunks_63)
node _alloc_way_T_63 = xor(_alloc_way_T_62, alloc_way_chunks_64)
node _alloc_way_T_64 = xor(_alloc_way_T_63, alloc_way_chunks_65)
node _alloc_way_T_65 = xor(_alloc_way_T_64, alloc_way_chunks_66)
node _alloc_way_T_66 = xor(_alloc_way_T_65, alloc_way_chunks_67)
node _alloc_way_T_67 = xor(_alloc_way_T_66, alloc_way_chunks_68)
node _alloc_way_T_68 = xor(_alloc_way_T_67, alloc_way_chunks_69)
node _alloc_way_T_69 = xor(_alloc_way_T_68, alloc_way_chunks_70)
node _alloc_way_T_70 = xor(_alloc_way_T_69, alloc_way_chunks_71)
node _alloc_way_T_71 = xor(_alloc_way_T_70, alloc_way_chunks_72)
node _alloc_way_T_72 = xor(_alloc_way_T_71, alloc_way_chunks_73)
node _alloc_way_T_73 = xor(_alloc_way_T_72, alloc_way_chunks_74)
node _alloc_way_T_74 = xor(_alloc_way_T_73, alloc_way_chunks_75)
node _alloc_way_T_75 = xor(_alloc_way_T_74, alloc_way_chunks_76)
node _alloc_way_T_76 = xor(_alloc_way_T_75, alloc_way_chunks_77)
node _alloc_way_T_77 = xor(_alloc_way_T_76, alloc_way_chunks_78)
node _alloc_way_T_78 = xor(_alloc_way_T_77, alloc_way_chunks_79)
node _alloc_way_T_79 = xor(_alloc_way_T_78, alloc_way_chunks_80)
node _alloc_way_T_80 = xor(_alloc_way_T_79, alloc_way_chunks_81)
node _alloc_way_T_81 = xor(_alloc_way_T_80, alloc_way_chunks_82)
node _alloc_way_T_82 = xor(_alloc_way_T_81, alloc_way_chunks_83)
node _alloc_way_T_83 = xor(_alloc_way_T_82, alloc_way_chunks_84)
node _alloc_way_T_84 = xor(_alloc_way_T_83, alloc_way_chunks_85)
node _alloc_way_T_85 = xor(_alloc_way_T_84, alloc_way_chunks_86)
node _alloc_way_T_86 = xor(_alloc_way_T_85, alloc_way_chunks_87)
node _alloc_way_T_87 = xor(_alloc_way_T_86, alloc_way_chunks_88)
node _alloc_way_T_88 = xor(_alloc_way_T_87, alloc_way_chunks_89)
node _alloc_way_T_89 = xor(_alloc_way_T_88, alloc_way_chunks_90)
node _alloc_way_T_90 = xor(_alloc_way_T_89, alloc_way_chunks_91)
node _alloc_way_T_91 = xor(_alloc_way_T_90, alloc_way_chunks_92)
node _alloc_way_T_92 = xor(_alloc_way_T_91, alloc_way_chunks_93)
node _alloc_way_T_93 = xor(_alloc_way_T_92, alloc_way_chunks_94)
node _alloc_way_T_94 = xor(_alloc_way_T_93, alloc_way_chunks_95)
node _alloc_way_T_95 = xor(_alloc_way_T_94, alloc_way_chunks_96)
node _alloc_way_T_96 = xor(_alloc_way_T_95, alloc_way_chunks_97)
node _alloc_way_T_97 = xor(_alloc_way_T_96, alloc_way_chunks_98)
node _alloc_way_T_98 = xor(_alloc_way_T_97, alloc_way_chunks_99)
node _alloc_way_T_99 = xor(_alloc_way_T_98, alloc_way_chunks_100)
node _alloc_way_T_100 = xor(_alloc_way_T_99, alloc_way_chunks_101)
node _alloc_way_T_101 = xor(_alloc_way_T_100, alloc_way_chunks_102)
node _alloc_way_T_102 = xor(_alloc_way_T_101, alloc_way_chunks_103)
node _alloc_way_T_103 = xor(_alloc_way_T_102, alloc_way_chunks_104)
node _alloc_way_T_104 = xor(_alloc_way_T_103, alloc_way_chunks_105)
node _alloc_way_T_105 = xor(_alloc_way_T_104, alloc_way_chunks_106)
node _alloc_way_T_106 = xor(_alloc_way_T_105, alloc_way_chunks_107)
node _alloc_way_T_107 = xor(_alloc_way_T_106, alloc_way_chunks_108)
node _alloc_way_T_108 = xor(_alloc_way_T_107, alloc_way_chunks_109)
node _alloc_way_T_109 = xor(_alloc_way_T_108, alloc_way_chunks_110)
node _alloc_way_T_110 = xor(_alloc_way_T_109, alloc_way_chunks_111)
node _alloc_way_T_111 = xor(_alloc_way_T_110, alloc_way_chunks_112)
node _alloc_way_T_112 = xor(_alloc_way_T_111, alloc_way_chunks_113)
node _alloc_way_T_113 = xor(_alloc_way_T_112, alloc_way_chunks_114)
node _alloc_way_T_114 = xor(_alloc_way_T_113, alloc_way_chunks_115)
node _alloc_way_T_115 = xor(_alloc_way_T_114, alloc_way_chunks_116)
node _alloc_way_T_116 = xor(_alloc_way_T_115, alloc_way_chunks_117)
node _alloc_way_T_117 = xor(_alloc_way_T_116, alloc_way_chunks_118)
node _alloc_way_T_118 = xor(_alloc_way_T_117, alloc_way_chunks_119)
node _alloc_way_T_119 = xor(_alloc_way_T_118, alloc_way_chunks_120)
node _alloc_way_T_120 = xor(_alloc_way_T_119, alloc_way_chunks_121)
node _alloc_way_T_121 = xor(_alloc_way_T_120, alloc_way_chunks_122)
node _alloc_way_T_122 = xor(_alloc_way_T_121, alloc_way_chunks_123)
node _alloc_way_T_123 = xor(_alloc_way_T_122, alloc_way_chunks_124)
node _alloc_way_T_124 = xor(_alloc_way_T_123, alloc_way_chunks_125)
node _alloc_way_T_125 = xor(_alloc_way_T_124, alloc_way_chunks_126)
node _alloc_way_T_126 = xor(_alloc_way_T_125, alloc_way_chunks_127)
node _alloc_way_T_127 = xor(_alloc_way_T_126, alloc_way_chunks_128)
node _alloc_way_T_128 = xor(_alloc_way_T_127, alloc_way_chunks_129)
node _alloc_way_T_129 = xor(_alloc_way_T_128, alloc_way_chunks_130)
node _alloc_way_T_130 = xor(_alloc_way_T_129, alloc_way_chunks_131)
node _alloc_way_T_131 = xor(_alloc_way_T_130, alloc_way_chunks_132)
node _alloc_way_T_132 = xor(_alloc_way_T_131, alloc_way_chunks_133)
node _alloc_way_T_133 = xor(_alloc_way_T_132, alloc_way_chunks_134)
node _alloc_way_T_134 = xor(_alloc_way_T_133, alloc_way_chunks_135)
node _alloc_way_T_135 = xor(_alloc_way_T_134, alloc_way_chunks_136)
node _alloc_way_T_136 = xor(_alloc_way_T_135, alloc_way_chunks_137)
node _alloc_way_T_137 = xor(_alloc_way_T_136, alloc_way_chunks_138)
node _alloc_way_T_138 = xor(_alloc_way_T_137, alloc_way_chunks_139)
node _alloc_way_T_139 = xor(_alloc_way_T_138, alloc_way_chunks_140)
node _alloc_way_T_140 = xor(_alloc_way_T_139, alloc_way_chunks_141)
node _alloc_way_T_141 = xor(_alloc_way_T_140, alloc_way_chunks_142)
node _alloc_way_T_142 = xor(_alloc_way_T_141, alloc_way_chunks_143)
node _alloc_way_T_143 = xor(_alloc_way_T_142, alloc_way_chunks_144)
node _alloc_way_T_144 = xor(_alloc_way_T_143, alloc_way_chunks_145)
node _alloc_way_T_145 = xor(_alloc_way_T_144, alloc_way_chunks_146)
node _alloc_way_T_146 = xor(_alloc_way_T_145, alloc_way_chunks_147)
node _alloc_way_T_147 = xor(_alloc_way_T_146, alloc_way_chunks_148)
node _alloc_way_T_148 = xor(_alloc_way_T_147, alloc_way_chunks_149)
node _alloc_way_T_149 = xor(_alloc_way_T_148, alloc_way_chunks_150)
node _alloc_way_T_150 = xor(_alloc_way_T_149, alloc_way_chunks_151)
node _alloc_way_T_151 = xor(_alloc_way_T_150, alloc_way_chunks_152)
node _alloc_way_T_152 = xor(_alloc_way_T_151, alloc_way_chunks_153)
node _alloc_way_T_153 = xor(_alloc_way_T_152, alloc_way_chunks_154)
node _alloc_way_T_154 = xor(_alloc_way_T_153, alloc_way_chunks_155)
node _alloc_way_T_155 = xor(_alloc_way_T_154, alloc_way_chunks_156)
node _alloc_way_T_156 = xor(_alloc_way_T_155, alloc_way_chunks_157)
node _alloc_way_T_157 = xor(_alloc_way_T_156, alloc_way_chunks_158)
node _alloc_way_T_158 = xor(_alloc_way_T_157, alloc_way_chunks_159)
node _alloc_way_T_159 = xor(_alloc_way_T_158, alloc_way_chunks_160)
node _alloc_way_T_160 = xor(_alloc_way_T_159, alloc_way_chunks_161)
node _alloc_way_T_161 = xor(_alloc_way_T_160, alloc_way_chunks_162)
node _alloc_way_T_162 = xor(_alloc_way_T_161, alloc_way_chunks_163)
node _alloc_way_T_163 = xor(_alloc_way_T_162, alloc_way_chunks_164)
node _alloc_way_T_164 = xor(_alloc_way_T_163, alloc_way_chunks_165)
node _alloc_way_T_165 = xor(_alloc_way_T_164, alloc_way_chunks_166)
node _alloc_way_T_166 = xor(_alloc_way_T_165, alloc_way_chunks_167)
node _alloc_way_T_167 = xor(_alloc_way_T_166, alloc_way_chunks_168)
node _alloc_way_T_168 = xor(_alloc_way_T_167, alloc_way_chunks_169)
node _alloc_way_T_169 = xor(_alloc_way_T_168, alloc_way_chunks_170)
node _alloc_way_T_170 = xor(_alloc_way_T_169, alloc_way_chunks_171)
node _alloc_way_T_171 = xor(_alloc_way_T_170, alloc_way_chunks_172)
node _alloc_way_T_172 = xor(_alloc_way_T_171, alloc_way_chunks_173)
node _alloc_way_T_173 = xor(_alloc_way_T_172, alloc_way_chunks_174)
node _alloc_way_T_174 = xor(_alloc_way_T_173, alloc_way_chunks_175)
node _alloc_way_T_175 = xor(_alloc_way_T_174, alloc_way_chunks_176)
node _alloc_way_T_176 = xor(_alloc_way_T_175, alloc_way_chunks_177)
node _alloc_way_T_177 = xor(_alloc_way_T_176, alloc_way_chunks_178)
node _alloc_way_T_178 = xor(_alloc_way_T_177, alloc_way_chunks_179)
node _alloc_way_T_179 = xor(_alloc_way_T_178, alloc_way_chunks_180)
node _alloc_way_T_180 = xor(_alloc_way_T_179, alloc_way_chunks_181)
node _alloc_way_T_181 = xor(_alloc_way_T_180, alloc_way_chunks_182)
node _alloc_way_T_182 = xor(_alloc_way_T_181, alloc_way_chunks_183)
node _alloc_way_T_183 = xor(_alloc_way_T_182, alloc_way_chunks_184)
node _alloc_way_T_184 = xor(_alloc_way_T_183, alloc_way_chunks_185)
node _alloc_way_T_185 = xor(_alloc_way_T_184, alloc_way_chunks_186)
node _alloc_way_T_186 = xor(_alloc_way_T_185, alloc_way_chunks_187)
node _alloc_way_T_187 = xor(_alloc_way_T_186, alloc_way_chunks_188)
node _alloc_way_T_188 = xor(_alloc_way_T_187, alloc_way_chunks_189)
node _alloc_way_T_189 = xor(_alloc_way_T_188, alloc_way_chunks_190)
node _alloc_way_T_190 = xor(_alloc_way_T_189, alloc_way_chunks_191)
node _alloc_way_T_191 = xor(_alloc_way_T_190, alloc_way_chunks_192)
node _alloc_way_T_192 = xor(_alloc_way_T_191, alloc_way_chunks_193)
node _alloc_way_T_193 = xor(_alloc_way_T_192, alloc_way_chunks_194)
node _alloc_way_T_194 = xor(_alloc_way_T_193, alloc_way_chunks_195)
node _alloc_way_T_195 = xor(_alloc_way_T_194, alloc_way_chunks_196)
node _alloc_way_T_196 = xor(_alloc_way_T_195, alloc_way_chunks_197)
node _alloc_way_T_197 = xor(_alloc_way_T_196, alloc_way_chunks_198)
node _alloc_way_T_198 = xor(_alloc_way_T_197, alloc_way_chunks_199)
node _alloc_way_T_199 = xor(_alloc_way_T_198, alloc_way_chunks_200)
node _alloc_way_T_200 = xor(_alloc_way_T_199, alloc_way_chunks_201)
node _alloc_way_T_201 = xor(_alloc_way_T_200, alloc_way_chunks_202)
node _alloc_way_T_202 = xor(_alloc_way_T_201, alloc_way_chunks_203)
node _alloc_way_T_203 = xor(_alloc_way_T_202, alloc_way_chunks_204)
node _alloc_way_T_204 = xor(_alloc_way_T_203, alloc_way_chunks_205)
node _alloc_way_T_205 = xor(_alloc_way_T_204, alloc_way_chunks_206)
node _alloc_way_T_206 = xor(_alloc_way_T_205, alloc_way_chunks_207)
node _alloc_way_T_207 = xor(_alloc_way_T_206, alloc_way_chunks_208)
node _alloc_way_T_208 = xor(_alloc_way_T_207, alloc_way_chunks_209)
node _alloc_way_T_209 = xor(_alloc_way_T_208, alloc_way_chunks_210)
node _alloc_way_T_210 = xor(_alloc_way_T_209, alloc_way_chunks_211)
node _alloc_way_T_211 = xor(_alloc_way_T_210, alloc_way_chunks_212)
node _alloc_way_T_212 = xor(_alloc_way_T_211, alloc_way_chunks_213)
node _alloc_way_T_213 = xor(_alloc_way_T_212, alloc_way_chunks_214)
node _alloc_way_T_214 = xor(_alloc_way_T_213, alloc_way_chunks_215)
node _alloc_way_T_215 = xor(_alloc_way_T_214, alloc_way_chunks_216)
node _alloc_way_T_216 = xor(_alloc_way_T_215, alloc_way_chunks_217)
node _alloc_way_T_217 = xor(_alloc_way_T_216, alloc_way_chunks_218)
node _alloc_way_T_218 = xor(_alloc_way_T_217, alloc_way_chunks_219)
node _alloc_way_T_219 = xor(_alloc_way_T_218, alloc_way_chunks_220)
node _alloc_way_T_220 = xor(_alloc_way_T_219, alloc_way_chunks_221)
node _alloc_way_T_221 = xor(_alloc_way_T_220, alloc_way_chunks_222)
node _alloc_way_T_222 = xor(_alloc_way_T_221, alloc_way_chunks_223)
node _alloc_way_T_223 = xor(_alloc_way_T_222, alloc_way_chunks_224)
node _alloc_way_T_224 = xor(_alloc_way_T_223, alloc_way_chunks_225)
node _alloc_way_T_225 = xor(_alloc_way_T_224, alloc_way_chunks_226)
node _alloc_way_T_226 = xor(_alloc_way_T_225, alloc_way_chunks_227)
node _alloc_way_T_227 = xor(_alloc_way_T_226, alloc_way_chunks_228)
node _alloc_way_T_228 = xor(_alloc_way_T_227, alloc_way_chunks_229)
node _alloc_way_T_229 = xor(_alloc_way_T_228, alloc_way_chunks_230)
node _alloc_way_T_230 = xor(_alloc_way_T_229, alloc_way_chunks_231)
node _alloc_way_T_231 = xor(_alloc_way_T_230, alloc_way_chunks_232)
node _alloc_way_T_232 = xor(_alloc_way_T_231, alloc_way_chunks_233)
node _alloc_way_T_233 = xor(_alloc_way_T_232, alloc_way_chunks_234)
node _alloc_way_T_234 = xor(_alloc_way_T_233, alloc_way_chunks_235)
node _alloc_way_T_235 = xor(_alloc_way_T_234, alloc_way_chunks_236)
node _alloc_way_T_236 = xor(_alloc_way_T_235, alloc_way_chunks_237)
node _alloc_way_T_237 = xor(_alloc_way_T_236, alloc_way_chunks_238)
node _alloc_way_T_238 = xor(_alloc_way_T_237, alloc_way_chunks_239)
node _alloc_way_T_239 = xor(_alloc_way_T_238, alloc_way_chunks_240)
node _alloc_way_T_240 = xor(_alloc_way_T_239, alloc_way_chunks_241)
node _alloc_way_T_241 = xor(_alloc_way_T_240, alloc_way_chunks_242)
node _alloc_way_T_242 = xor(_alloc_way_T_241, alloc_way_chunks_243)
node _alloc_way_T_243 = xor(_alloc_way_T_242, alloc_way_chunks_244)
node _alloc_way_T_244 = xor(_alloc_way_T_243, alloc_way_chunks_245)
node _alloc_way_T_245 = xor(_alloc_way_T_244, alloc_way_chunks_246)
node _alloc_way_T_246 = xor(_alloc_way_T_245, alloc_way_chunks_247)
node _alloc_way_T_247 = xor(_alloc_way_T_246, alloc_way_chunks_248)
node _alloc_way_T_248 = xor(_alloc_way_T_247, alloc_way_chunks_249)
node _alloc_way_T_249 = xor(_alloc_way_T_248, alloc_way_chunks_250)
node _alloc_way_T_250 = xor(_alloc_way_T_249, alloc_way_chunks_251)
node _alloc_way_T_251 = xor(_alloc_way_T_250, alloc_way_chunks_252)
node _alloc_way_T_252 = xor(_alloc_way_T_251, alloc_way_chunks_253)
node _alloc_way_T_253 = xor(_alloc_way_T_252, alloc_way_chunks_254)
node _alloc_way_T_254 = xor(_alloc_way_T_253, alloc_way_chunks_255)
node _alloc_way_T_255 = xor(_alloc_way_T_254, alloc_way_chunks_256)
node _alloc_way_T_256 = xor(_alloc_way_T_255, alloc_way_chunks_257)
node _alloc_way_T_257 = xor(_alloc_way_T_256, alloc_way_chunks_258)
node _alloc_way_T_258 = xor(_alloc_way_T_257, alloc_way_chunks_259)
node alloc_way = xor(_alloc_way_T_258, alloc_way_chunks_260)
node _s1_meta_write_way_T = or(s1_hits_0, s1_hits_1)
node _s1_meta_write_way_T_1 = or(_s1_meta_write_way_T, s1_hits_2)
node _s1_meta_write_way_T_2 = or(_s1_meta_write_way_T_1, s1_hits_3)
node _s1_meta_write_way_T_3 = cat(s1_hit_ohs[0][1], s1_hit_ohs[0][0])
node _s1_meta_write_way_T_4 = cat(s1_hit_ohs[1][1], s1_hit_ohs[1][0])
node _s1_meta_write_way_T_5 = cat(s1_hit_ohs[2][1], s1_hit_ohs[2][0])
node _s1_meta_write_way_T_6 = cat(s1_hit_ohs[3][1], s1_hit_ohs[3][0])
node _s1_meta_write_way_T_7 = or(_s1_meta_write_way_T_3, _s1_meta_write_way_T_4)
node _s1_meta_write_way_T_8 = or(_s1_meta_write_way_T_7, _s1_meta_write_way_T_5)
node _s1_meta_write_way_T_9 = or(_s1_meta_write_way_T_8, _s1_meta_write_way_T_6)
node _s1_meta_write_way_T_10 = bits(_s1_meta_write_way_T_9, 0, 0)
node _s1_meta_write_way_T_11 = bits(_s1_meta_write_way_T_9, 1, 1)
node _s1_meta_write_way_T_12 = mux(_s1_meta_write_way_T_10, UInt<1>(0h0), UInt<1>(0h1))
node _s1_meta_write_way_T_13 = mux(_s1_meta_write_way_T_2, _s1_meta_write_way_T_12, alloc_way)
connect s1_meta.write_way, _s1_meta_write_way_T_13
wire s1_update_meta : { write_way : UInt<1>}
wire _s1_update_meta_WIRE : UInt<1>
connect _s1_update_meta_WIRE, s1_update.bits.meta
node _s1_update_meta_T = bits(_s1_update_meta_WIRE, 0, 0)
connect s1_update_meta.write_way, _s1_update_meta_T
node _max_offset_value_T = not(UInt<12>(0h0))
node _max_offset_value_T_1 = cat(UInt<1>(0h0), _max_offset_value_T)
node max_offset_value = asSInt(_max_offset_value_T_1)
node _min_offset_value_T = cat(UInt<1>(0h1), UInt<12>(0h0))
node min_offset_value = asSInt(_min_offset_value_T)
node _new_offset_value_T = asSInt(s1_update.bits.target)
node _new_offset_value_T_1 = shl(s1_update.bits.cfi_idx.bits, 1)
node _new_offset_value_T_2 = add(s1_update.bits.pc, _new_offset_value_T_1)
node _new_offset_value_T_3 = tail(_new_offset_value_T_2, 1)
node _new_offset_value_T_4 = asSInt(_new_offset_value_T_3)
node _new_offset_value_T_5 = sub(_new_offset_value_T, _new_offset_value_T_4)
node _new_offset_value_T_6 = tail(_new_offset_value_T_5, 1)
node new_offset_value = asSInt(_new_offset_value_T_6)
node _offset_is_extended_T = gt(new_offset_value, max_offset_value)
node _offset_is_extended_T_1 = lt(new_offset_value, min_offset_value)
node offset_is_extended = or(_offset_is_extended_T, _offset_is_extended_T_1)
wire s1_update_wbtb_data : { offset : SInt<13>, extended : UInt<1>}
connect s1_update_wbtb_data.extended, offset_is_extended
connect s1_update_wbtb_data.offset, new_offset_value
node _s1_update_wbtb_mask_T = dshl(UInt<1>(0h1), s1_update.bits.cfi_idx.bits)
node _s1_update_wbtb_mask_T_1 = and(s1_update.bits.cfi_idx.valid, s1_update.valid)
node _s1_update_wbtb_mask_T_2 = and(_s1_update_wbtb_mask_T_1, s1_update.bits.cfi_taken)
node _s1_update_wbtb_mask_T_3 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update)
node _s1_update_wbtb_mask_T_4 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0))
node _s1_update_wbtb_mask_T_5 = or(_s1_update_wbtb_mask_T_3, _s1_update_wbtb_mask_T_4)
node _s1_update_wbtb_mask_T_6 = eq(_s1_update_wbtb_mask_T_5, UInt<1>(0h0))
node _s1_update_wbtb_mask_T_7 = and(_s1_update_wbtb_mask_T_2, _s1_update_wbtb_mask_T_6)
node _s1_update_wbtb_mask_T_8 = mux(_s1_update_wbtb_mask_T_7, UInt<4>(0hf), UInt<4>(0h0))
node s1_update_wbtb_mask = and(_s1_update_wbtb_mask_T, _s1_update_wbtb_mask_T_8)
node _s1_update_wmeta_mask_T = or(s1_update_wbtb_mask, s1_update.bits.br_mask)
node _s1_update_wmeta_mask_T_1 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update)
node _s1_update_wmeta_mask_T_2 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0))
node _s1_update_wmeta_mask_T_3 = or(_s1_update_wmeta_mask_T_1, _s1_update_wmeta_mask_T_2)
node _s1_update_wmeta_mask_T_4 = eq(_s1_update_wmeta_mask_T_3, UInt<1>(0h0))
node _s1_update_wmeta_mask_T_5 = and(s1_update.valid, _s1_update_wmeta_mask_T_4)
node _s1_update_wmeta_mask_T_6 = mux(_s1_update_wmeta_mask_T_5, UInt<4>(0hf), UInt<4>(0h0))
node _s1_update_wmeta_mask_T_7 = mux(s1_update.valid, UInt<4>(0hf), UInt<4>(0h0))
node _s1_update_wmeta_mask_T_8 = and(_s1_update_wmeta_mask_T_7, s1_update.bits.btb_mispredicts)
node _s1_update_wmeta_mask_T_9 = or(_s1_update_wmeta_mask_T_6, _s1_update_wmeta_mask_T_8)
node s1_update_wmeta_mask = and(_s1_update_wmeta_mask_T, _s1_update_wmeta_mask_T_9)
wire s1_update_wmeta_data : { is_br : UInt<1>, tag : UInt<29>}[4]
node _s1_update_wmeta_data_0_tag_T = bits(s1_update.bits.btb_mispredicts, 0, 0)
node _s1_update_wmeta_data_0_tag_T_1 = shr(s1_update_idx, 7)
node _s1_update_wmeta_data_0_tag_T_2 = mux(_s1_update_wmeta_data_0_tag_T, UInt<1>(0h0), _s1_update_wmeta_data_0_tag_T_1)
connect s1_update_wmeta_data[0].tag, _s1_update_wmeta_data_0_tag_T_2
node _s1_update_wmeta_data_0_is_br_T = bits(s1_update.bits.br_mask, 0, 0)
connect s1_update_wmeta_data[0].is_br, _s1_update_wmeta_data_0_is_br_T
node _s1_update_wmeta_data_1_tag_T = bits(s1_update.bits.btb_mispredicts, 1, 1)
node _s1_update_wmeta_data_1_tag_T_1 = shr(s1_update_idx, 7)
node _s1_update_wmeta_data_1_tag_T_2 = mux(_s1_update_wmeta_data_1_tag_T, UInt<1>(0h0), _s1_update_wmeta_data_1_tag_T_1)
connect s1_update_wmeta_data[1].tag, _s1_update_wmeta_data_1_tag_T_2
node _s1_update_wmeta_data_1_is_br_T = bits(s1_update.bits.br_mask, 1, 1)
connect s1_update_wmeta_data[1].is_br, _s1_update_wmeta_data_1_is_br_T
node _s1_update_wmeta_data_2_tag_T = bits(s1_update.bits.btb_mispredicts, 2, 2)
node _s1_update_wmeta_data_2_tag_T_1 = shr(s1_update_idx, 7)
node _s1_update_wmeta_data_2_tag_T_2 = mux(_s1_update_wmeta_data_2_tag_T, UInt<1>(0h0), _s1_update_wmeta_data_2_tag_T_1)
connect s1_update_wmeta_data[2].tag, _s1_update_wmeta_data_2_tag_T_2
node _s1_update_wmeta_data_2_is_br_T = bits(s1_update.bits.br_mask, 2, 2)
connect s1_update_wmeta_data[2].is_br, _s1_update_wmeta_data_2_is_br_T
node _s1_update_wmeta_data_3_tag_T = bits(s1_update.bits.btb_mispredicts, 3, 3)
node _s1_update_wmeta_data_3_tag_T_1 = shr(s1_update_idx, 7)
node _s1_update_wmeta_data_3_tag_T_2 = mux(_s1_update_wmeta_data_3_tag_T, UInt<1>(0h0), _s1_update_wmeta_data_3_tag_T_1)
connect s1_update_wmeta_data[3].tag, _s1_update_wmeta_data_3_tag_T_2
node _s1_update_wmeta_data_3_is_br_T = bits(s1_update.bits.br_mask, 3, 3)
connect s1_update_wmeta_data[3].is_br, _s1_update_wmeta_data_3_is_br_T
node _T_1 = eq(s1_update_meta.write_way, UInt<1>(0h0))
node _T_2 = or(doing_reset, _T_1)
node _T_3 = or(_T_2, UInt<1>(0h0))
when _T_3 :
node _T_4 = mux(doing_reset, reset_idx, s1_update_idx)
wire _WIRE : UInt<14>[4]
connect _WIRE[0], UInt<14>(0h0)
connect _WIRE[1], UInt<14>(0h0)
connect _WIRE[2], UInt<14>(0h0)
connect _WIRE[3], UInt<14>(0h0)
node _T_5 = asUInt(s1_update_wbtb_data.offset)
node _T_6 = cat(_T_5, s1_update_wbtb_data.extended)
node _T_7 = asUInt(s1_update_wbtb_data.offset)
node _T_8 = cat(_T_7, s1_update_wbtb_data.extended)
node _T_9 = asUInt(s1_update_wbtb_data.offset)
node _T_10 = cat(_T_9, s1_update_wbtb_data.extended)
node _T_11 = asUInt(s1_update_wbtb_data.offset)
node _T_12 = cat(_T_11, s1_update_wbtb_data.extended)
wire _WIRE_1 : UInt<14>[4]
connect _WIRE_1[0], _T_6
connect _WIRE_1[1], _T_8
connect _WIRE_1[2], _T_10
connect _WIRE_1[3], _T_12
node _T_13 = mux(doing_reset, _WIRE, _WIRE_1)
node _T_14 = not(UInt<4>(0h0))
node _T_15 = mux(doing_reset, _T_14, s1_update_wbtb_mask)
node _T_16 = bits(_T_15, 0, 0)
node _T_17 = bits(_T_15, 1, 1)
node _T_18 = bits(_T_15, 2, 2)
node _T_19 = bits(_T_15, 3, 3)
node _T_20 = or(_T_4, UInt<7>(0h0))
node _T_21 = bits(_T_20, 6, 0)
write mport MPORT = btb_0[_T_21], clock
when _T_16 :
connect MPORT[0], _T_13[0]
when _T_17 :
connect MPORT[1], _T_13[1]
when _T_18 :
connect MPORT[2], _T_13[2]
when _T_19 :
connect MPORT[3], _T_13[3]
node _T_22 = mux(doing_reset, reset_idx, s1_update_idx)
wire _WIRE_2 : UInt<30>[4]
connect _WIRE_2[0], UInt<30>(0h0)
connect _WIRE_2[1], UInt<30>(0h0)
connect _WIRE_2[2], UInt<30>(0h0)
connect _WIRE_2[3], UInt<30>(0h0)
node _T_23 = cat(s1_update_wmeta_data[0].is_br, s1_update_wmeta_data[0].tag)
node _T_24 = cat(s1_update_wmeta_data[1].is_br, s1_update_wmeta_data[1].tag)
node _T_25 = cat(s1_update_wmeta_data[2].is_br, s1_update_wmeta_data[2].tag)
node _T_26 = cat(s1_update_wmeta_data[3].is_br, s1_update_wmeta_data[3].tag)
wire _WIRE_3 : UInt<30>[4]
connect _WIRE_3[0], _T_23
connect _WIRE_3[1], _T_24
connect _WIRE_3[2], _T_25
connect _WIRE_3[3], _T_26
node _T_27 = mux(doing_reset, _WIRE_2, _WIRE_3)
node _T_28 = not(UInt<4>(0h0))
node _T_29 = mux(doing_reset, _T_28, s1_update_wmeta_mask)
node _T_30 = bits(_T_29, 0, 0)
node _T_31 = bits(_T_29, 1, 1)
node _T_32 = bits(_T_29, 2, 2)
node _T_33 = bits(_T_29, 3, 3)
node _T_34 = or(_T_22, UInt<7>(0h0))
node _T_35 = bits(_T_34, 6, 0)
write mport MPORT_1 = meta_0[_T_35], clock
when _T_30 :
connect MPORT_1[0], _T_27[0]
when _T_31 :
connect MPORT_1[1], _T_27[1]
when _T_32 :
connect MPORT_1[2], _T_27[2]
when _T_33 :
connect MPORT_1[3], _T_27[3]
node _T_36 = eq(s1_update_meta.write_way, UInt<1>(0h1))
node _T_37 = or(doing_reset, _T_36)
node _T_38 = or(_T_37, UInt<1>(0h0))
when _T_38 :
node _T_39 = mux(doing_reset, reset_idx, s1_update_idx)
wire _WIRE_4 : UInt<14>[4]
connect _WIRE_4[0], UInt<14>(0h0)
connect _WIRE_4[1], UInt<14>(0h0)
connect _WIRE_4[2], UInt<14>(0h0)
connect _WIRE_4[3], UInt<14>(0h0)
node _T_40 = asUInt(s1_update_wbtb_data.offset)
node _T_41 = cat(_T_40, s1_update_wbtb_data.extended)
node _T_42 = asUInt(s1_update_wbtb_data.offset)
node _T_43 = cat(_T_42, s1_update_wbtb_data.extended)
node _T_44 = asUInt(s1_update_wbtb_data.offset)
node _T_45 = cat(_T_44, s1_update_wbtb_data.extended)
node _T_46 = asUInt(s1_update_wbtb_data.offset)
node _T_47 = cat(_T_46, s1_update_wbtb_data.extended)
wire _WIRE_5 : UInt<14>[4]
connect _WIRE_5[0], _T_41
connect _WIRE_5[1], _T_43
connect _WIRE_5[2], _T_45
connect _WIRE_5[3], _T_47
node _T_48 = mux(doing_reset, _WIRE_4, _WIRE_5)
node _T_49 = not(UInt<4>(0h0))
node _T_50 = mux(doing_reset, _T_49, s1_update_wbtb_mask)
node _T_51 = bits(_T_50, 0, 0)
node _T_52 = bits(_T_50, 1, 1)
node _T_53 = bits(_T_50, 2, 2)
node _T_54 = bits(_T_50, 3, 3)
node _T_55 = or(_T_39, UInt<7>(0h0))
node _T_56 = bits(_T_55, 6, 0)
write mport MPORT_2 = btb_1[_T_56], clock
when _T_51 :
connect MPORT_2[0], _T_48[0]
when _T_52 :
connect MPORT_2[1], _T_48[1]
when _T_53 :
connect MPORT_2[2], _T_48[2]
when _T_54 :
connect MPORT_2[3], _T_48[3]
node _T_57 = mux(doing_reset, reset_idx, s1_update_idx)
wire _WIRE_6 : UInt<30>[4]
connect _WIRE_6[0], UInt<30>(0h0)
connect _WIRE_6[1], UInt<30>(0h0)
connect _WIRE_6[2], UInt<30>(0h0)
connect _WIRE_6[3], UInt<30>(0h0)
node _T_58 = cat(s1_update_wmeta_data[0].is_br, s1_update_wmeta_data[0].tag)
node _T_59 = cat(s1_update_wmeta_data[1].is_br, s1_update_wmeta_data[1].tag)
node _T_60 = cat(s1_update_wmeta_data[2].is_br, s1_update_wmeta_data[2].tag)
node _T_61 = cat(s1_update_wmeta_data[3].is_br, s1_update_wmeta_data[3].tag)
wire _WIRE_7 : UInt<30>[4]
connect _WIRE_7[0], _T_58
connect _WIRE_7[1], _T_59
connect _WIRE_7[2], _T_60
connect _WIRE_7[3], _T_61
node _T_62 = mux(doing_reset, _WIRE_6, _WIRE_7)
node _T_63 = not(UInt<4>(0h0))
node _T_64 = mux(doing_reset, _T_63, s1_update_wmeta_mask)
node _T_65 = bits(_T_64, 0, 0)
node _T_66 = bits(_T_64, 1, 1)
node _T_67 = bits(_T_64, 2, 2)
node _T_68 = bits(_T_64, 3, 3)
node _T_69 = or(_T_57, UInt<7>(0h0))
node _T_70 = bits(_T_69, 6, 0)
write mport MPORT_3 = meta_1[_T_70], clock
when _T_65 :
connect MPORT_3[0], _T_62[0]
when _T_66 :
connect MPORT_3[1], _T_62[1]
when _T_67 :
connect MPORT_3[2], _T_62[2]
when _T_68 :
connect MPORT_3[3], _T_62[3]
node _T_71 = neq(s1_update_wbtb_mask, UInt<1>(0h0))
node _T_72 = and(_T_71, offset_is_extended)
when _T_72 :
node _T_73 = or(s1_update_idx, UInt<7>(0h0))
node _T_74 = bits(_T_73, 6, 0)
write mport MPORT_4 = ebtb[_T_74], clock
connect MPORT_4, s1_update.bits.target | module BTBBranchPredictorBank_2( // @[btb.scala:23:7]
input clock, // @[btb.scala:23:7]
input reset, // @[btb.scala:23:7]
input io_f0_valid, // @[predictor.scala:140:14]
input [39:0] io_f0_pc, // @[predictor.scala:140:14]
input [3:0] io_f0_mask, // @[predictor.scala:140:14]
input [63:0] io_f1_ghist, // @[predictor.scala:140:14]
input io_resp_in_0_f1_0_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f1_0_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f1_0_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f1_0_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f1_0_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f1_1_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f1_1_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f1_1_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f1_1_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f1_1_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f1_2_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f1_2_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f1_2_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f1_2_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f1_2_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f1_3_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f1_3_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f1_3_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f1_3_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f1_3_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f2_0_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f2_0_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f2_0_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f2_0_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f2_0_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f2_1_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f2_1_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f2_1_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f2_1_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f2_1_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f2_2_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f2_2_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f2_2_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f2_2_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f2_2_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f2_3_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f2_3_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f2_3_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f2_3_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f2_3_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f3_0_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f3_0_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f3_0_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f3_0_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f3_0_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f3_1_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f3_1_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f3_1_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f3_1_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f3_1_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f3_2_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f3_2_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f3_2_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f3_2_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f3_2_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f3_3_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f3_3_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f3_3_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f3_3_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f3_3_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f1_0_taken, // @[predictor.scala:140:14]
output io_resp_f1_0_is_br, // @[predictor.scala:140:14]
output io_resp_f1_0_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_0_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_0_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f1_1_taken, // @[predictor.scala:140:14]
output io_resp_f1_1_is_br, // @[predictor.scala:140:14]
output io_resp_f1_1_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_1_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_1_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f1_2_taken, // @[predictor.scala:140:14]
output io_resp_f1_2_is_br, // @[predictor.scala:140:14]
output io_resp_f1_2_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_2_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_2_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f1_3_taken, // @[predictor.scala:140:14]
output io_resp_f1_3_is_br, // @[predictor.scala:140:14]
output io_resp_f1_3_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_3_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_3_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_0_taken, // @[predictor.scala:140:14]
output io_resp_f2_0_is_br, // @[predictor.scala:140:14]
output io_resp_f2_0_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_0_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_0_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_1_taken, // @[predictor.scala:140:14]
output io_resp_f2_1_is_br, // @[predictor.scala:140:14]
output io_resp_f2_1_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_1_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_1_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_2_taken, // @[predictor.scala:140:14]
output io_resp_f2_2_is_br, // @[predictor.scala:140:14]
output io_resp_f2_2_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_2_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_2_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_3_taken, // @[predictor.scala:140:14]
output io_resp_f2_3_is_br, // @[predictor.scala:140:14]
output io_resp_f2_3_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_3_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_3_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_0_taken, // @[predictor.scala:140:14]
output io_resp_f3_0_is_br, // @[predictor.scala:140:14]
output io_resp_f3_0_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_0_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_0_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_1_taken, // @[predictor.scala:140:14]
output io_resp_f3_1_is_br, // @[predictor.scala:140:14]
output io_resp_f3_1_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_1_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_1_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_2_taken, // @[predictor.scala:140:14]
output io_resp_f3_2_is_br, // @[predictor.scala:140:14]
output io_resp_f3_2_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_2_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_2_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_3_taken, // @[predictor.scala:140:14]
output io_resp_f3_3_is_br, // @[predictor.scala:140:14]
output io_resp_f3_3_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_3_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_3_predicted_pc_bits, // @[predictor.scala:140:14]
output [119:0] io_f3_meta, // @[predictor.scala:140:14]
input io_f3_fire, // @[predictor.scala:140:14]
input io_update_valid, // @[predictor.scala:140:14]
input io_update_bits_is_mispredict_update, // @[predictor.scala:140:14]
input io_update_bits_is_repair_update, // @[predictor.scala:140:14]
input [3:0] io_update_bits_btb_mispredicts, // @[predictor.scala:140:14]
input [39:0] io_update_bits_pc, // @[predictor.scala:140:14]
input [3:0] io_update_bits_br_mask, // @[predictor.scala:140:14]
input io_update_bits_cfi_idx_valid, // @[predictor.scala:140:14]
input [1:0] io_update_bits_cfi_idx_bits, // @[predictor.scala:140:14]
input io_update_bits_cfi_taken, // @[predictor.scala:140:14]
input io_update_bits_cfi_mispredicted, // @[predictor.scala:140:14]
input io_update_bits_cfi_is_br, // @[predictor.scala:140:14]
input io_update_bits_cfi_is_jal, // @[predictor.scala:140:14]
input io_update_bits_cfi_is_jalr, // @[predictor.scala:140:14]
input [63:0] io_update_bits_ghist, // @[predictor.scala:140:14]
input io_update_bits_lhist, // @[predictor.scala:140:14]
input [39:0] io_update_bits_target, // @[predictor.scala:140:14]
input [119:0] io_update_bits_meta // @[predictor.scala:140:14]
);
wire [29:0] meta_1_MPORT_3_data_3; // @[btb.scala:183:12]
wire [29:0] meta_1_MPORT_3_data_2; // @[btb.scala:183:12]
wire [29:0] meta_1_MPORT_3_data_1; // @[btb.scala:183:12]
wire [29:0] meta_1_MPORT_3_data_0; // @[btb.scala:183:12]
wire [13:0] btb_1_MPORT_2_data_3; // @[btb.scala:172:12]
wire [13:0] btb_1_MPORT_2_data_2; // @[btb.scala:172:12]
wire [13:0] btb_1_MPORT_2_data_1; // @[btb.scala:172:12]
wire [13:0] btb_1_MPORT_2_data_0; // @[btb.scala:172:12]
wire [29:0] meta_0_MPORT_1_data_3; // @[btb.scala:183:12]
wire [29:0] meta_0_MPORT_1_data_2; // @[btb.scala:183:12]
wire [29:0] meta_0_MPORT_1_data_1; // @[btb.scala:183:12]
wire [29:0] meta_0_MPORT_1_data_0; // @[btb.scala:183:12]
wire [13:0] btb_0_MPORT_data_3; // @[btb.scala:172:12]
wire [13:0] btb_0_MPORT_data_2; // @[btb.scala:172:12]
wire [13:0] btb_0_MPORT_data_1; // @[btb.scala:172:12]
wire [13:0] btb_0_MPORT_data_0; // @[btb.scala:172:12]
wire _s1_update_meta_WIRE; // @[btb.scala:138:55]
wire _s1_req_rmeta_WIRE_17_is_br; // @[btb.scala:74:93]
wire [28:0] _s1_req_rmeta_WIRE_17_tag; // @[btb.scala:74:93]
wire _s1_req_rmeta_WIRE_15_is_br; // @[btb.scala:74:93]
wire [28:0] _s1_req_rmeta_WIRE_15_tag; // @[btb.scala:74:93]
wire _s1_req_rmeta_WIRE_13_is_br; // @[btb.scala:74:93]
wire [28:0] _s1_req_rmeta_WIRE_13_tag; // @[btb.scala:74:93]
wire _s1_req_rmeta_WIRE_11_is_br; // @[btb.scala:74:93]
wire [28:0] _s1_req_rmeta_WIRE_11_tag; // @[btb.scala:74:93]
wire _s1_req_rmeta_WIRE_7_is_br; // @[btb.scala:74:93]
wire [28:0] _s1_req_rmeta_WIRE_7_tag; // @[btb.scala:74:93]
wire _s1_req_rmeta_WIRE_5_is_br; // @[btb.scala:74:93]
wire [28:0] _s1_req_rmeta_WIRE_5_tag; // @[btb.scala:74:93]
wire _s1_req_rmeta_WIRE_3_is_br; // @[btb.scala:74:93]
wire [28:0] _s1_req_rmeta_WIRE_3_tag; // @[btb.scala:74:93]
wire _s1_req_rmeta_WIRE_1_is_br; // @[btb.scala:74:93]
wire [28:0] _s1_req_rmeta_WIRE_1_tag; // @[btb.scala:74:93]
wire [12:0] _s1_req_rbtb_WIRE_17_offset; // @[btb.scala:73:93]
wire _s1_req_rbtb_WIRE_17_extended; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_WIRE_15_offset; // @[btb.scala:73:93]
wire _s1_req_rbtb_WIRE_15_extended; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_WIRE_13_offset; // @[btb.scala:73:93]
wire _s1_req_rbtb_WIRE_13_extended; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_WIRE_11_offset; // @[btb.scala:73:93]
wire _s1_req_rbtb_WIRE_11_extended; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_WIRE_7_offset; // @[btb.scala:73:93]
wire _s1_req_rbtb_WIRE_7_extended; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_WIRE_5_offset; // @[btb.scala:73:93]
wire _s1_req_rbtb_WIRE_5_extended; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_WIRE_3_offset; // @[btb.scala:73:93]
wire _s1_req_rbtb_WIRE_3_extended; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_WIRE_1_offset; // @[btb.scala:73:93]
wire _s1_req_rbtb_WIRE_1_extended; // @[btb.scala:73:93]
wire [39:0] _ebtb_R0_data; // @[btb.scala:67:29]
wire [55:0] _btb_1_R0_data; // @[btb.scala:66:47]
wire [55:0] _btb_0_R0_data; // @[btb.scala:66:47]
wire [119:0] _meta_1_R0_data; // @[btb.scala:65:47]
wire [119:0] _meta_0_R0_data; // @[btb.scala:65:47]
wire io_f0_valid_0 = io_f0_valid; // @[btb.scala:23:7]
wire [39:0] io_f0_pc_0 = io_f0_pc; // @[btb.scala:23:7]
wire [3:0] io_f0_mask_0 = io_f0_mask; // @[btb.scala:23:7]
wire [63:0] io_f1_ghist_0 = io_f1_ghist; // @[btb.scala:23:7]
wire io_resp_in_0_f1_0_taken_0 = io_resp_in_0_f1_0_taken; // @[btb.scala:23:7]
wire io_resp_in_0_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br; // @[btb.scala:23:7]
wire io_resp_in_0_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal; // @[btb.scala:23:7]
wire io_resp_in_0_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid; // @[btb.scala:23:7]
wire [39:0] io_resp_in_0_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits; // @[btb.scala:23:7]
wire io_resp_in_0_f1_1_taken_0 = io_resp_in_0_f1_1_taken; // @[btb.scala:23:7]
wire io_resp_in_0_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br; // @[btb.scala:23:7]
wire io_resp_in_0_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal; // @[btb.scala:23:7]
wire io_resp_in_0_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid; // @[btb.scala:23:7]
wire [39:0] io_resp_in_0_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits; // @[btb.scala:23:7]
wire io_resp_in_0_f1_2_taken_0 = io_resp_in_0_f1_2_taken; // @[btb.scala:23:7]
wire io_resp_in_0_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br; // @[btb.scala:23:7]
wire io_resp_in_0_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal; // @[btb.scala:23:7]
wire io_resp_in_0_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid; // @[btb.scala:23:7]
wire [39:0] io_resp_in_0_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits; // @[btb.scala:23:7]
wire io_resp_in_0_f1_3_taken_0 = io_resp_in_0_f1_3_taken; // @[btb.scala:23:7]
wire io_resp_in_0_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br; // @[btb.scala:23:7]
wire io_resp_in_0_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal; // @[btb.scala:23:7]
wire io_resp_in_0_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid; // @[btb.scala:23:7]
wire [39:0] io_resp_in_0_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits; // @[btb.scala:23:7]
wire io_resp_in_0_f2_0_taken_0 = io_resp_in_0_f2_0_taken; // @[btb.scala:23:7]
wire io_resp_in_0_f2_0_is_br_0 = io_resp_in_0_f2_0_is_br; // @[btb.scala:23:7]
wire io_resp_in_0_f2_0_is_jal_0 = io_resp_in_0_f2_0_is_jal; // @[btb.scala:23:7]
wire io_resp_in_0_f2_0_predicted_pc_valid_0 = io_resp_in_0_f2_0_predicted_pc_valid; // @[btb.scala:23:7]
wire [39:0] io_resp_in_0_f2_0_predicted_pc_bits_0 = io_resp_in_0_f2_0_predicted_pc_bits; // @[btb.scala:23:7]
wire io_resp_in_0_f2_1_taken_0 = io_resp_in_0_f2_1_taken; // @[btb.scala:23:7]
wire io_resp_in_0_f2_1_is_br_0 = io_resp_in_0_f2_1_is_br; // @[btb.scala:23:7]
wire io_resp_in_0_f2_1_is_jal_0 = io_resp_in_0_f2_1_is_jal; // @[btb.scala:23:7]
wire io_resp_in_0_f2_1_predicted_pc_valid_0 = io_resp_in_0_f2_1_predicted_pc_valid; // @[btb.scala:23:7]
wire [39:0] io_resp_in_0_f2_1_predicted_pc_bits_0 = io_resp_in_0_f2_1_predicted_pc_bits; // @[btb.scala:23:7]
wire io_resp_in_0_f2_2_taken_0 = io_resp_in_0_f2_2_taken; // @[btb.scala:23:7]
wire io_resp_in_0_f2_2_is_br_0 = io_resp_in_0_f2_2_is_br; // @[btb.scala:23:7]
wire io_resp_in_0_f2_2_is_jal_0 = io_resp_in_0_f2_2_is_jal; // @[btb.scala:23:7]
wire io_resp_in_0_f2_2_predicted_pc_valid_0 = io_resp_in_0_f2_2_predicted_pc_valid; // @[btb.scala:23:7]
wire [39:0] io_resp_in_0_f2_2_predicted_pc_bits_0 = io_resp_in_0_f2_2_predicted_pc_bits; // @[btb.scala:23:7]
wire io_resp_in_0_f2_3_taken_0 = io_resp_in_0_f2_3_taken; // @[btb.scala:23:7]
wire io_resp_in_0_f2_3_is_br_0 = io_resp_in_0_f2_3_is_br; // @[btb.scala:23:7]
wire io_resp_in_0_f2_3_is_jal_0 = io_resp_in_0_f2_3_is_jal; // @[btb.scala:23:7]
wire io_resp_in_0_f2_3_predicted_pc_valid_0 = io_resp_in_0_f2_3_predicted_pc_valid; // @[btb.scala:23:7]
wire [39:0] io_resp_in_0_f2_3_predicted_pc_bits_0 = io_resp_in_0_f2_3_predicted_pc_bits; // @[btb.scala:23:7]
wire io_resp_in_0_f3_0_taken_0 = io_resp_in_0_f3_0_taken; // @[btb.scala:23:7]
wire io_resp_in_0_f3_0_is_br_0 = io_resp_in_0_f3_0_is_br; // @[btb.scala:23:7]
wire io_resp_in_0_f3_0_is_jal_0 = io_resp_in_0_f3_0_is_jal; // @[btb.scala:23:7]
wire io_resp_in_0_f3_0_predicted_pc_valid_0 = io_resp_in_0_f3_0_predicted_pc_valid; // @[btb.scala:23:7]
wire [39:0] io_resp_in_0_f3_0_predicted_pc_bits_0 = io_resp_in_0_f3_0_predicted_pc_bits; // @[btb.scala:23:7]
wire io_resp_in_0_f3_1_taken_0 = io_resp_in_0_f3_1_taken; // @[btb.scala:23:7]
wire io_resp_in_0_f3_1_is_br_0 = io_resp_in_0_f3_1_is_br; // @[btb.scala:23:7]
wire io_resp_in_0_f3_1_is_jal_0 = io_resp_in_0_f3_1_is_jal; // @[btb.scala:23:7]
wire io_resp_in_0_f3_1_predicted_pc_valid_0 = io_resp_in_0_f3_1_predicted_pc_valid; // @[btb.scala:23:7]
wire [39:0] io_resp_in_0_f3_1_predicted_pc_bits_0 = io_resp_in_0_f3_1_predicted_pc_bits; // @[btb.scala:23:7]
wire io_resp_in_0_f3_2_taken_0 = io_resp_in_0_f3_2_taken; // @[btb.scala:23:7]
wire io_resp_in_0_f3_2_is_br_0 = io_resp_in_0_f3_2_is_br; // @[btb.scala:23:7]
wire io_resp_in_0_f3_2_is_jal_0 = io_resp_in_0_f3_2_is_jal; // @[btb.scala:23:7]
wire io_resp_in_0_f3_2_predicted_pc_valid_0 = io_resp_in_0_f3_2_predicted_pc_valid; // @[btb.scala:23:7]
wire [39:0] io_resp_in_0_f3_2_predicted_pc_bits_0 = io_resp_in_0_f3_2_predicted_pc_bits; // @[btb.scala:23:7]
wire io_resp_in_0_f3_3_taken_0 = io_resp_in_0_f3_3_taken; // @[btb.scala:23:7]
wire io_resp_in_0_f3_3_is_br_0 = io_resp_in_0_f3_3_is_br; // @[btb.scala:23:7]
wire io_resp_in_0_f3_3_is_jal_0 = io_resp_in_0_f3_3_is_jal; // @[btb.scala:23:7]
wire io_resp_in_0_f3_3_predicted_pc_valid_0 = io_resp_in_0_f3_3_predicted_pc_valid; // @[btb.scala:23:7]
wire [39:0] io_resp_in_0_f3_3_predicted_pc_bits_0 = io_resp_in_0_f3_3_predicted_pc_bits; // @[btb.scala:23:7]
wire io_f3_fire_0 = io_f3_fire; // @[btb.scala:23:7]
wire io_update_valid_0 = io_update_valid; // @[btb.scala:23:7]
wire io_update_bits_is_mispredict_update_0 = io_update_bits_is_mispredict_update; // @[btb.scala:23:7]
wire io_update_bits_is_repair_update_0 = io_update_bits_is_repair_update; // @[btb.scala:23:7]
wire [3:0] io_update_bits_btb_mispredicts_0 = io_update_bits_btb_mispredicts; // @[btb.scala:23:7]
wire [39:0] io_update_bits_pc_0 = io_update_bits_pc; // @[btb.scala:23:7]
wire [3:0] io_update_bits_br_mask_0 = io_update_bits_br_mask; // @[btb.scala:23:7]
wire io_update_bits_cfi_idx_valid_0 = io_update_bits_cfi_idx_valid; // @[btb.scala:23:7]
wire [1:0] io_update_bits_cfi_idx_bits_0 = io_update_bits_cfi_idx_bits; // @[btb.scala:23:7]
wire io_update_bits_cfi_taken_0 = io_update_bits_cfi_taken; // @[btb.scala:23:7]
wire io_update_bits_cfi_mispredicted_0 = io_update_bits_cfi_mispredicted; // @[btb.scala:23:7]
wire io_update_bits_cfi_is_br_0 = io_update_bits_cfi_is_br; // @[btb.scala:23:7]
wire io_update_bits_cfi_is_jal_0 = io_update_bits_cfi_is_jal; // @[btb.scala:23:7]
wire io_update_bits_cfi_is_jalr_0 = io_update_bits_cfi_is_jalr; // @[btb.scala:23:7]
wire [63:0] io_update_bits_ghist_0 = io_update_bits_ghist; // @[btb.scala:23:7]
wire io_update_bits_lhist_0 = io_update_bits_lhist; // @[btb.scala:23:7]
wire [39:0] io_update_bits_target_0 = io_update_bits_target; // @[btb.scala:23:7]
wire [119:0] io_update_bits_meta_0 = io_update_bits_meta; // @[btb.scala:23:7]
wire [11:0] _max_offset_value_T = 12'hFFF; // @[btb.scala:140:35]
wire [12:0] _max_offset_value_T_1 = 13'hFFF; // @[btb.scala:140:{29,59}]
wire [12:0] max_offset_value = 13'hFFF; // @[btb.scala:140:59]
wire [12:0] _min_offset_value_T = 13'h1000; // @[btb.scala:141:{29,59}]
wire [12:0] min_offset_value = 13'h1000; // @[btb.scala:141:59]
wire io_f1_lhist = 1'h0; // @[btb.scala:23:7]
wire io_resp_f1_0_taken_0 = io_resp_in_0_f1_0_taken_0; // @[btb.scala:23:7]
wire io_resp_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br_0; // @[btb.scala:23:7]
wire io_resp_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal_0; // @[btb.scala:23:7]
wire io_resp_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid_0; // @[btb.scala:23:7]
wire [39:0] io_resp_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits_0; // @[btb.scala:23:7]
wire io_resp_f1_1_taken_0 = io_resp_in_0_f1_1_taken_0; // @[btb.scala:23:7]
wire io_resp_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br_0; // @[btb.scala:23:7]
wire io_resp_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal_0; // @[btb.scala:23:7]
wire io_resp_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid_0; // @[btb.scala:23:7]
wire [39:0] io_resp_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits_0; // @[btb.scala:23:7]
wire io_resp_f1_2_taken_0 = io_resp_in_0_f1_2_taken_0; // @[btb.scala:23:7]
wire io_resp_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br_0; // @[btb.scala:23:7]
wire io_resp_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal_0; // @[btb.scala:23:7]
wire io_resp_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid_0; // @[btb.scala:23:7]
wire [39:0] io_resp_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits_0; // @[btb.scala:23:7]
wire io_resp_f1_3_taken_0 = io_resp_in_0_f1_3_taken_0; // @[btb.scala:23:7]
wire io_resp_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br_0; // @[btb.scala:23:7]
wire io_resp_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal_0; // @[btb.scala:23:7]
wire io_resp_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid_0; // @[btb.scala:23:7]
wire [39:0] io_resp_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits_0; // @[btb.scala:23:7]
wire io_resp_f2_0_predicted_pc_valid_0; // @[btb.scala:23:7]
wire [39:0] io_resp_f2_0_predicted_pc_bits_0; // @[btb.scala:23:7]
wire io_resp_f2_0_taken_0; // @[btb.scala:23:7]
wire io_resp_f2_0_is_br_0; // @[btb.scala:23:7]
wire io_resp_f2_0_is_jal_0; // @[btb.scala:23:7]
wire io_resp_f2_1_predicted_pc_valid_0; // @[btb.scala:23:7]
wire [39:0] io_resp_f2_1_predicted_pc_bits_0; // @[btb.scala:23:7]
wire io_resp_f2_1_taken_0; // @[btb.scala:23:7]
wire io_resp_f2_1_is_br_0; // @[btb.scala:23:7]
wire io_resp_f2_1_is_jal_0; // @[btb.scala:23:7]
wire io_resp_f2_2_predicted_pc_valid_0; // @[btb.scala:23:7]
wire [39:0] io_resp_f2_2_predicted_pc_bits_0; // @[btb.scala:23:7]
wire io_resp_f2_2_taken_0; // @[btb.scala:23:7]
wire io_resp_f2_2_is_br_0; // @[btb.scala:23:7]
wire io_resp_f2_2_is_jal_0; // @[btb.scala:23:7]
wire io_resp_f2_3_predicted_pc_valid_0; // @[btb.scala:23:7]
wire [39:0] io_resp_f2_3_predicted_pc_bits_0; // @[btb.scala:23:7]
wire io_resp_f2_3_taken_0; // @[btb.scala:23:7]
wire io_resp_f2_3_is_br_0; // @[btb.scala:23:7]
wire io_resp_f2_3_is_jal_0; // @[btb.scala:23:7]
wire io_resp_f3_0_predicted_pc_valid_0; // @[btb.scala:23:7]
wire [39:0] io_resp_f3_0_predicted_pc_bits_0; // @[btb.scala:23:7]
wire io_resp_f3_0_taken_0; // @[btb.scala:23:7]
wire io_resp_f3_0_is_br_0; // @[btb.scala:23:7]
wire io_resp_f3_0_is_jal_0; // @[btb.scala:23:7]
wire io_resp_f3_1_predicted_pc_valid_0; // @[btb.scala:23:7]
wire [39:0] io_resp_f3_1_predicted_pc_bits_0; // @[btb.scala:23:7]
wire io_resp_f3_1_taken_0; // @[btb.scala:23:7]
wire io_resp_f3_1_is_br_0; // @[btb.scala:23:7]
wire io_resp_f3_1_is_jal_0; // @[btb.scala:23:7]
wire io_resp_f3_2_predicted_pc_valid_0; // @[btb.scala:23:7]
wire [39:0] io_resp_f3_2_predicted_pc_bits_0; // @[btb.scala:23:7]
wire io_resp_f3_2_taken_0; // @[btb.scala:23:7]
wire io_resp_f3_2_is_br_0; // @[btb.scala:23:7]
wire io_resp_f3_2_is_jal_0; // @[btb.scala:23:7]
wire io_resp_f3_3_predicted_pc_valid_0; // @[btb.scala:23:7]
wire [39:0] io_resp_f3_3_predicted_pc_bits_0; // @[btb.scala:23:7]
wire io_resp_f3_3_taken_0; // @[btb.scala:23:7]
wire io_resp_f3_3_is_br_0; // @[btb.scala:23:7]
wire io_resp_f3_3_is_jal_0; // @[btb.scala:23:7]
wire [119:0] io_f3_meta_0; // @[btb.scala:23:7]
wire [35:0] s0_idx = io_f0_pc_0[39:4]; // @[frontend.scala:162:35]
wire [35:0] _s1_req_rbtb_WIRE = s0_idx; // @[frontend.scala:162:35]
wire [35:0] _s1_req_rbtb_WIRE_10 = s0_idx; // @[frontend.scala:162:35]
wire [35:0] _s1_req_rmeta_WIRE = s0_idx; // @[frontend.scala:162:35]
wire [35:0] _s1_req_rmeta_WIRE_10 = s0_idx; // @[frontend.scala:162:35]
wire [35:0] _s1_req_rebtb_WIRE = s0_idx; // @[frontend.scala:162:35]
reg [35:0] s1_idx; // @[predictor.scala:163:29]
reg [35:0] s2_idx; // @[predictor.scala:164:29]
reg [35:0] s3_idx; // @[predictor.scala:165:29]
reg s1_valid; // @[predictor.scala:168:25]
reg s2_valid; // @[predictor.scala:169:25]
reg s3_valid; // @[predictor.scala:170:25]
reg [3:0] s1_mask; // @[predictor.scala:173:24]
reg [3:0] s2_mask; // @[predictor.scala:174:24]
reg [3:0] s3_mask; // @[predictor.scala:175:24]
reg [39:0] s1_pc; // @[predictor.scala:178:22]
wire [39:0] _s1_resp_0_bits_T = s1_pc; // @[predictor.scala:178:22]
wire [39:0] _s1_resp_1_bits_T = s1_pc; // @[predictor.scala:178:22]
wire [39:0] _s1_resp_2_bits_T = s1_pc; // @[predictor.scala:178:22]
wire [39:0] _s1_resp_3_bits_T = s1_pc; // @[predictor.scala:178:22]
wire [35:0] s0_update_idx = io_update_bits_pc_0[39:4]; // @[frontend.scala:162:35]
reg s1_update_valid; // @[predictor.scala:184:30]
reg s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30]
reg s1_update_bits_is_repair_update; // @[predictor.scala:184:30]
reg [3:0] s1_update_bits_btb_mispredicts; // @[predictor.scala:184:30]
reg [39:0] s1_update_bits_pc; // @[predictor.scala:184:30]
reg [3:0] s1_update_bits_br_mask; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_idx_valid; // @[predictor.scala:184:30]
reg [1:0] s1_update_bits_cfi_idx_bits; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_taken; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_is_br; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_is_jal; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_is_jalr; // @[predictor.scala:184:30]
reg [63:0] s1_update_bits_ghist; // @[predictor.scala:184:30]
reg s1_update_bits_lhist; // @[predictor.scala:184:30]
reg [39:0] s1_update_bits_target; // @[predictor.scala:184:30]
wire [39:0] _new_offset_value_T = s1_update_bits_target; // @[predictor.scala:184:30]
reg [119:0] s1_update_bits_meta; // @[predictor.scala:184:30]
reg [35:0] s1_update_idx; // @[predictor.scala:185:30]
reg s1_update_valid_0; // @[predictor.scala:186:32]
wire _s1_meta_write_way_T_13; // @[btb.scala:133:27]
wire s1_meta_write_way; // @[btb.scala:52:21]
reg f3_meta_REG_write_way; // @[btb.scala:53:32]
reg f3_meta_write_way; // @[btb.scala:53:24]
assign io_f3_meta_0 = {119'h0, f3_meta_write_way}; // @[btb.scala:23:7, :53:24, :56:14]
reg doing_reset; // @[btb.scala:60:28]
reg [6:0] reset_idx; // @[btb.scala:61:28]
wire [7:0] _reset_idx_T = {1'h0, reset_idx} + {7'h0, doing_reset}; // @[btb.scala:60:28, :61:28, :62:26]
wire [6:0] _reset_idx_T_1 = _reset_idx_T[6:0]; // @[btb.scala:62:26]
wire [29:0] _s1_req_rmeta_WIRE_2 = _meta_0_R0_data[29:0]; // @[btb.scala:65:47, :74:93]
wire [29:0] _s1_req_rmeta_WIRE_4 = _meta_0_R0_data[59:30]; // @[btb.scala:65:47, :74:93]
wire [29:0] _s1_req_rmeta_WIRE_6 = _meta_0_R0_data[89:60]; // @[btb.scala:65:47, :74:93]
wire [29:0] _s1_req_rmeta_WIRE_8 = _meta_0_R0_data[119:90]; // @[btb.scala:65:47, :74:93]
wire [29:0] _s1_req_rmeta_WIRE_12 = _meta_1_R0_data[29:0]; // @[btb.scala:65:47, :74:93]
wire [29:0] _s1_req_rmeta_WIRE_14 = _meta_1_R0_data[59:30]; // @[btb.scala:65:47, :74:93]
wire [29:0] _s1_req_rmeta_WIRE_16 = _meta_1_R0_data[89:60]; // @[btb.scala:65:47, :74:93]
wire [29:0] _s1_req_rmeta_WIRE_18 = _meta_1_R0_data[119:90]; // @[btb.scala:65:47, :74:93]
wire [13:0] _s1_req_rbtb_WIRE_2 = _btb_0_R0_data[13:0]; // @[btb.scala:66:47, :73:93]
wire [13:0] _s1_req_rbtb_WIRE_4 = _btb_0_R0_data[27:14]; // @[btb.scala:66:47, :73:93]
wire [13:0] _s1_req_rbtb_WIRE_6 = _btb_0_R0_data[41:28]; // @[btb.scala:66:47, :73:93]
wire [13:0] _s1_req_rbtb_WIRE_8 = _btb_0_R0_data[55:42]; // @[btb.scala:66:47, :73:93]
wire [13:0] _s1_req_rbtb_WIRE_12 = _btb_1_R0_data[13:0]; // @[btb.scala:66:47, :73:93]
wire [13:0] _s1_req_rbtb_WIRE_14 = _btb_1_R0_data[27:14]; // @[btb.scala:66:47, :73:93]
wire [13:0] _s1_req_rbtb_WIRE_16 = _btb_1_R0_data[41:28]; // @[btb.scala:66:47, :73:93]
wire [13:0] _s1_req_rbtb_WIRE_18 = _btb_1_R0_data[55:42]; // @[btb.scala:66:47, :73:93]
wire [6:0] _s1_req_rbtb_T = _s1_req_rbtb_WIRE[6:0]; // @[btb.scala:73:59]
wire [12:0] _s1_req_rbtb_T_3; // @[btb.scala:73:93]
wire _s1_req_rbtb_T_1; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_WIRE_9_0_offset = _s1_req_rbtb_WIRE_1_offset; // @[btb.scala:73:{52,93}]
wire _s1_req_rbtb_WIRE_9_0_extended = _s1_req_rbtb_WIRE_1_extended; // @[btb.scala:73:{52,93}]
assign _s1_req_rbtb_T_1 = _s1_req_rbtb_WIRE_2[0]; // @[btb.scala:73:93]
assign _s1_req_rbtb_WIRE_1_extended = _s1_req_rbtb_T_1; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_T_2 = _s1_req_rbtb_WIRE_2[13:1]; // @[btb.scala:73:93]
assign _s1_req_rbtb_T_3 = _s1_req_rbtb_T_2; // @[btb.scala:73:93]
assign _s1_req_rbtb_WIRE_1_offset = _s1_req_rbtb_T_3; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_T_6; // @[btb.scala:73:93]
wire _s1_req_rbtb_T_4; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_WIRE_9_1_offset = _s1_req_rbtb_WIRE_3_offset; // @[btb.scala:73:{52,93}]
wire _s1_req_rbtb_WIRE_9_1_extended = _s1_req_rbtb_WIRE_3_extended; // @[btb.scala:73:{52,93}]
assign _s1_req_rbtb_T_4 = _s1_req_rbtb_WIRE_4[0]; // @[btb.scala:73:93]
assign _s1_req_rbtb_WIRE_3_extended = _s1_req_rbtb_T_4; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_T_5 = _s1_req_rbtb_WIRE_4[13:1]; // @[btb.scala:73:93]
assign _s1_req_rbtb_T_6 = _s1_req_rbtb_T_5; // @[btb.scala:73:93]
assign _s1_req_rbtb_WIRE_3_offset = _s1_req_rbtb_T_6; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_T_9; // @[btb.scala:73:93]
wire _s1_req_rbtb_T_7; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_WIRE_9_2_offset = _s1_req_rbtb_WIRE_5_offset; // @[btb.scala:73:{52,93}]
wire _s1_req_rbtb_WIRE_9_2_extended = _s1_req_rbtb_WIRE_5_extended; // @[btb.scala:73:{52,93}]
assign _s1_req_rbtb_T_7 = _s1_req_rbtb_WIRE_6[0]; // @[btb.scala:73:93]
assign _s1_req_rbtb_WIRE_5_extended = _s1_req_rbtb_T_7; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_T_8 = _s1_req_rbtb_WIRE_6[13:1]; // @[btb.scala:73:93]
assign _s1_req_rbtb_T_9 = _s1_req_rbtb_T_8; // @[btb.scala:73:93]
assign _s1_req_rbtb_WIRE_5_offset = _s1_req_rbtb_T_9; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_T_12; // @[btb.scala:73:93]
wire _s1_req_rbtb_T_10; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_WIRE_9_3_offset = _s1_req_rbtb_WIRE_7_offset; // @[btb.scala:73:{52,93}]
wire _s1_req_rbtb_WIRE_9_3_extended = _s1_req_rbtb_WIRE_7_extended; // @[btb.scala:73:{52,93}]
assign _s1_req_rbtb_T_10 = _s1_req_rbtb_WIRE_8[0]; // @[btb.scala:73:93]
assign _s1_req_rbtb_WIRE_7_extended = _s1_req_rbtb_T_10; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_T_11 = _s1_req_rbtb_WIRE_8[13:1]; // @[btb.scala:73:93]
assign _s1_req_rbtb_T_12 = _s1_req_rbtb_T_11; // @[btb.scala:73:93]
assign _s1_req_rbtb_WIRE_7_offset = _s1_req_rbtb_T_12; // @[btb.scala:73:93]
wire [12:0] s1_req_rbtb_0_0_offset = _s1_req_rbtb_WIRE_9_0_offset; // @[btb.scala:73:{29,52}]
wire s1_req_rbtb_0_0_extended = _s1_req_rbtb_WIRE_9_0_extended; // @[btb.scala:73:{29,52}]
wire [12:0] s1_req_rbtb_0_1_offset = _s1_req_rbtb_WIRE_9_1_offset; // @[btb.scala:73:{29,52}]
wire s1_req_rbtb_0_1_extended = _s1_req_rbtb_WIRE_9_1_extended; // @[btb.scala:73:{29,52}]
wire [12:0] s1_req_rbtb_0_2_offset = _s1_req_rbtb_WIRE_9_2_offset; // @[btb.scala:73:{29,52}]
wire s1_req_rbtb_0_2_extended = _s1_req_rbtb_WIRE_9_2_extended; // @[btb.scala:73:{29,52}]
wire [12:0] s1_req_rbtb_0_3_offset = _s1_req_rbtb_WIRE_9_3_offset; // @[btb.scala:73:{29,52}]
wire s1_req_rbtb_0_3_extended = _s1_req_rbtb_WIRE_9_3_extended; // @[btb.scala:73:{29,52}]
wire [6:0] _s1_req_rbtb_T_13 = _s1_req_rbtb_WIRE_10[6:0]; // @[btb.scala:73:59]
wire [12:0] _s1_req_rbtb_T_16; // @[btb.scala:73:93]
wire _s1_req_rbtb_T_14; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_WIRE_19_0_offset = _s1_req_rbtb_WIRE_11_offset; // @[btb.scala:73:{52,93}]
wire _s1_req_rbtb_WIRE_19_0_extended = _s1_req_rbtb_WIRE_11_extended; // @[btb.scala:73:{52,93}]
assign _s1_req_rbtb_T_14 = _s1_req_rbtb_WIRE_12[0]; // @[btb.scala:73:93]
assign _s1_req_rbtb_WIRE_11_extended = _s1_req_rbtb_T_14; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_T_15 = _s1_req_rbtb_WIRE_12[13:1]; // @[btb.scala:73:93]
assign _s1_req_rbtb_T_16 = _s1_req_rbtb_T_15; // @[btb.scala:73:93]
assign _s1_req_rbtb_WIRE_11_offset = _s1_req_rbtb_T_16; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_T_19; // @[btb.scala:73:93]
wire _s1_req_rbtb_T_17; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_WIRE_19_1_offset = _s1_req_rbtb_WIRE_13_offset; // @[btb.scala:73:{52,93}]
wire _s1_req_rbtb_WIRE_19_1_extended = _s1_req_rbtb_WIRE_13_extended; // @[btb.scala:73:{52,93}]
assign _s1_req_rbtb_T_17 = _s1_req_rbtb_WIRE_14[0]; // @[btb.scala:73:93]
assign _s1_req_rbtb_WIRE_13_extended = _s1_req_rbtb_T_17; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_T_18 = _s1_req_rbtb_WIRE_14[13:1]; // @[btb.scala:73:93]
assign _s1_req_rbtb_T_19 = _s1_req_rbtb_T_18; // @[btb.scala:73:93]
assign _s1_req_rbtb_WIRE_13_offset = _s1_req_rbtb_T_19; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_T_22; // @[btb.scala:73:93]
wire _s1_req_rbtb_T_20; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_WIRE_19_2_offset = _s1_req_rbtb_WIRE_15_offset; // @[btb.scala:73:{52,93}]
wire _s1_req_rbtb_WIRE_19_2_extended = _s1_req_rbtb_WIRE_15_extended; // @[btb.scala:73:{52,93}]
assign _s1_req_rbtb_T_20 = _s1_req_rbtb_WIRE_16[0]; // @[btb.scala:73:93]
assign _s1_req_rbtb_WIRE_15_extended = _s1_req_rbtb_T_20; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_T_21 = _s1_req_rbtb_WIRE_16[13:1]; // @[btb.scala:73:93]
assign _s1_req_rbtb_T_22 = _s1_req_rbtb_T_21; // @[btb.scala:73:93]
assign _s1_req_rbtb_WIRE_15_offset = _s1_req_rbtb_T_22; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_T_25; // @[btb.scala:73:93]
wire _s1_req_rbtb_T_23; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_WIRE_19_3_offset = _s1_req_rbtb_WIRE_17_offset; // @[btb.scala:73:{52,93}]
wire _s1_req_rbtb_WIRE_19_3_extended = _s1_req_rbtb_WIRE_17_extended; // @[btb.scala:73:{52,93}]
assign _s1_req_rbtb_T_23 = _s1_req_rbtb_WIRE_18[0]; // @[btb.scala:73:93]
assign _s1_req_rbtb_WIRE_17_extended = _s1_req_rbtb_T_23; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_T_24 = _s1_req_rbtb_WIRE_18[13:1]; // @[btb.scala:73:93]
assign _s1_req_rbtb_T_25 = _s1_req_rbtb_T_24; // @[btb.scala:73:93]
assign _s1_req_rbtb_WIRE_17_offset = _s1_req_rbtb_T_25; // @[btb.scala:73:93]
wire [12:0] s1_req_rbtb_1_0_offset = _s1_req_rbtb_WIRE_19_0_offset; // @[btb.scala:73:{29,52}]
wire s1_req_rbtb_1_0_extended = _s1_req_rbtb_WIRE_19_0_extended; // @[btb.scala:73:{29,52}]
wire [12:0] s1_req_rbtb_1_1_offset = _s1_req_rbtb_WIRE_19_1_offset; // @[btb.scala:73:{29,52}]
wire s1_req_rbtb_1_1_extended = _s1_req_rbtb_WIRE_19_1_extended; // @[btb.scala:73:{29,52}]
wire [12:0] s1_req_rbtb_1_2_offset = _s1_req_rbtb_WIRE_19_2_offset; // @[btb.scala:73:{29,52}]
wire s1_req_rbtb_1_2_extended = _s1_req_rbtb_WIRE_19_2_extended; // @[btb.scala:73:{29,52}]
wire [12:0] s1_req_rbtb_1_3_offset = _s1_req_rbtb_WIRE_19_3_offset; // @[btb.scala:73:{29,52}]
wire s1_req_rbtb_1_3_extended = _s1_req_rbtb_WIRE_19_3_extended; // @[btb.scala:73:{29,52}]
wire [6:0] _s1_req_rmeta_T = _s1_req_rmeta_WIRE[6:0]; // @[btb.scala:74:60]
wire _s1_req_rmeta_T_2; // @[btb.scala:74:93]
wire [28:0] _s1_req_rmeta_T_1; // @[btb.scala:74:93]
wire _s1_req_rmeta_WIRE_9_0_is_br = _s1_req_rmeta_WIRE_1_is_br; // @[btb.scala:74:{53,93}]
wire [28:0] _s1_req_rmeta_WIRE_9_0_tag = _s1_req_rmeta_WIRE_1_tag; // @[btb.scala:74:{53,93}]
assign _s1_req_rmeta_T_1 = _s1_req_rmeta_WIRE_2[28:0]; // @[btb.scala:74:93]
assign _s1_req_rmeta_WIRE_1_tag = _s1_req_rmeta_T_1; // @[btb.scala:74:93]
assign _s1_req_rmeta_T_2 = _s1_req_rmeta_WIRE_2[29]; // @[btb.scala:74:93]
assign _s1_req_rmeta_WIRE_1_is_br = _s1_req_rmeta_T_2; // @[btb.scala:74:93]
wire _s1_req_rmeta_T_4; // @[btb.scala:74:93]
wire [28:0] _s1_req_rmeta_T_3; // @[btb.scala:74:93]
wire _s1_req_rmeta_WIRE_9_1_is_br = _s1_req_rmeta_WIRE_3_is_br; // @[btb.scala:74:{53,93}]
wire [28:0] _s1_req_rmeta_WIRE_9_1_tag = _s1_req_rmeta_WIRE_3_tag; // @[btb.scala:74:{53,93}]
assign _s1_req_rmeta_T_3 = _s1_req_rmeta_WIRE_4[28:0]; // @[btb.scala:74:93]
assign _s1_req_rmeta_WIRE_3_tag = _s1_req_rmeta_T_3; // @[btb.scala:74:93]
assign _s1_req_rmeta_T_4 = _s1_req_rmeta_WIRE_4[29]; // @[btb.scala:74:93]
assign _s1_req_rmeta_WIRE_3_is_br = _s1_req_rmeta_T_4; // @[btb.scala:74:93]
wire _s1_req_rmeta_T_6; // @[btb.scala:74:93]
wire [28:0] _s1_req_rmeta_T_5; // @[btb.scala:74:93]
wire _s1_req_rmeta_WIRE_9_2_is_br = _s1_req_rmeta_WIRE_5_is_br; // @[btb.scala:74:{53,93}]
wire [28:0] _s1_req_rmeta_WIRE_9_2_tag = _s1_req_rmeta_WIRE_5_tag; // @[btb.scala:74:{53,93}]
assign _s1_req_rmeta_T_5 = _s1_req_rmeta_WIRE_6[28:0]; // @[btb.scala:74:93]
assign _s1_req_rmeta_WIRE_5_tag = _s1_req_rmeta_T_5; // @[btb.scala:74:93]
assign _s1_req_rmeta_T_6 = _s1_req_rmeta_WIRE_6[29]; // @[btb.scala:74:93]
assign _s1_req_rmeta_WIRE_5_is_br = _s1_req_rmeta_T_6; // @[btb.scala:74:93]
wire _s1_req_rmeta_T_8; // @[btb.scala:74:93]
wire [28:0] _s1_req_rmeta_T_7; // @[btb.scala:74:93]
wire _s1_req_rmeta_WIRE_9_3_is_br = _s1_req_rmeta_WIRE_7_is_br; // @[btb.scala:74:{53,93}]
wire [28:0] _s1_req_rmeta_WIRE_9_3_tag = _s1_req_rmeta_WIRE_7_tag; // @[btb.scala:74:{53,93}]
assign _s1_req_rmeta_T_7 = _s1_req_rmeta_WIRE_8[28:0]; // @[btb.scala:74:93]
assign _s1_req_rmeta_WIRE_7_tag = _s1_req_rmeta_T_7; // @[btb.scala:74:93]
assign _s1_req_rmeta_T_8 = _s1_req_rmeta_WIRE_8[29]; // @[btb.scala:74:93]
assign _s1_req_rmeta_WIRE_7_is_br = _s1_req_rmeta_T_8; // @[btb.scala:74:93]
wire s1_req_rmeta_0_0_is_br = _s1_req_rmeta_WIRE_9_0_is_br; // @[btb.scala:74:{29,53}]
wire [28:0] s1_req_rmeta_0_0_tag = _s1_req_rmeta_WIRE_9_0_tag; // @[btb.scala:74:{29,53}]
wire s1_req_rmeta_0_1_is_br = _s1_req_rmeta_WIRE_9_1_is_br; // @[btb.scala:74:{29,53}]
wire [28:0] s1_req_rmeta_0_1_tag = _s1_req_rmeta_WIRE_9_1_tag; // @[btb.scala:74:{29,53}]
wire s1_req_rmeta_0_2_is_br = _s1_req_rmeta_WIRE_9_2_is_br; // @[btb.scala:74:{29,53}]
wire [28:0] s1_req_rmeta_0_2_tag = _s1_req_rmeta_WIRE_9_2_tag; // @[btb.scala:74:{29,53}]
wire s1_req_rmeta_0_3_is_br = _s1_req_rmeta_WIRE_9_3_is_br; // @[btb.scala:74:{29,53}]
wire [28:0] s1_req_rmeta_0_3_tag = _s1_req_rmeta_WIRE_9_3_tag; // @[btb.scala:74:{29,53}]
wire [6:0] _s1_req_rmeta_T_9 = _s1_req_rmeta_WIRE_10[6:0]; // @[btb.scala:74:60]
wire _s1_req_rmeta_T_11; // @[btb.scala:74:93]
wire [28:0] _s1_req_rmeta_T_10; // @[btb.scala:74:93]
wire _s1_req_rmeta_WIRE_19_0_is_br = _s1_req_rmeta_WIRE_11_is_br; // @[btb.scala:74:{53,93}]
wire [28:0] _s1_req_rmeta_WIRE_19_0_tag = _s1_req_rmeta_WIRE_11_tag; // @[btb.scala:74:{53,93}]
assign _s1_req_rmeta_T_10 = _s1_req_rmeta_WIRE_12[28:0]; // @[btb.scala:74:93]
assign _s1_req_rmeta_WIRE_11_tag = _s1_req_rmeta_T_10; // @[btb.scala:74:93]
assign _s1_req_rmeta_T_11 = _s1_req_rmeta_WIRE_12[29]; // @[btb.scala:74:93]
assign _s1_req_rmeta_WIRE_11_is_br = _s1_req_rmeta_T_11; // @[btb.scala:74:93]
wire _s1_req_rmeta_T_13; // @[btb.scala:74:93]
wire [28:0] _s1_req_rmeta_T_12; // @[btb.scala:74:93]
wire _s1_req_rmeta_WIRE_19_1_is_br = _s1_req_rmeta_WIRE_13_is_br; // @[btb.scala:74:{53,93}]
wire [28:0] _s1_req_rmeta_WIRE_19_1_tag = _s1_req_rmeta_WIRE_13_tag; // @[btb.scala:74:{53,93}]
assign _s1_req_rmeta_T_12 = _s1_req_rmeta_WIRE_14[28:0]; // @[btb.scala:74:93]
assign _s1_req_rmeta_WIRE_13_tag = _s1_req_rmeta_T_12; // @[btb.scala:74:93]
assign _s1_req_rmeta_T_13 = _s1_req_rmeta_WIRE_14[29]; // @[btb.scala:74:93]
assign _s1_req_rmeta_WIRE_13_is_br = _s1_req_rmeta_T_13; // @[btb.scala:74:93]
wire _s1_req_rmeta_T_15; // @[btb.scala:74:93]
wire [28:0] _s1_req_rmeta_T_14; // @[btb.scala:74:93]
wire _s1_req_rmeta_WIRE_19_2_is_br = _s1_req_rmeta_WIRE_15_is_br; // @[btb.scala:74:{53,93}]
wire [28:0] _s1_req_rmeta_WIRE_19_2_tag = _s1_req_rmeta_WIRE_15_tag; // @[btb.scala:74:{53,93}]
assign _s1_req_rmeta_T_14 = _s1_req_rmeta_WIRE_16[28:0]; // @[btb.scala:74:93]
assign _s1_req_rmeta_WIRE_15_tag = _s1_req_rmeta_T_14; // @[btb.scala:74:93]
assign _s1_req_rmeta_T_15 = _s1_req_rmeta_WIRE_16[29]; // @[btb.scala:74:93]
assign _s1_req_rmeta_WIRE_15_is_br = _s1_req_rmeta_T_15; // @[btb.scala:74:93]
wire _s1_req_rmeta_T_17; // @[btb.scala:74:93]
wire [28:0] _s1_req_rmeta_T_16; // @[btb.scala:74:93]
wire _s1_req_rmeta_WIRE_19_3_is_br = _s1_req_rmeta_WIRE_17_is_br; // @[btb.scala:74:{53,93}]
wire [28:0] _s1_req_rmeta_WIRE_19_3_tag = _s1_req_rmeta_WIRE_17_tag; // @[btb.scala:74:{53,93}]
assign _s1_req_rmeta_T_16 = _s1_req_rmeta_WIRE_18[28:0]; // @[btb.scala:74:93]
assign _s1_req_rmeta_WIRE_17_tag = _s1_req_rmeta_T_16; // @[btb.scala:74:93]
assign _s1_req_rmeta_T_17 = _s1_req_rmeta_WIRE_18[29]; // @[btb.scala:74:93]
assign _s1_req_rmeta_WIRE_17_is_br = _s1_req_rmeta_T_17; // @[btb.scala:74:93]
wire s1_req_rmeta_1_0_is_br = _s1_req_rmeta_WIRE_19_0_is_br; // @[btb.scala:74:{29,53}]
wire [28:0] s1_req_rmeta_1_0_tag = _s1_req_rmeta_WIRE_19_0_tag; // @[btb.scala:74:{29,53}]
wire s1_req_rmeta_1_1_is_br = _s1_req_rmeta_WIRE_19_1_is_br; // @[btb.scala:74:{29,53}]
wire [28:0] s1_req_rmeta_1_1_tag = _s1_req_rmeta_WIRE_19_1_tag; // @[btb.scala:74:{29,53}]
wire s1_req_rmeta_1_2_is_br = _s1_req_rmeta_WIRE_19_2_is_br; // @[btb.scala:74:{29,53}]
wire [28:0] s1_req_rmeta_1_2_tag = _s1_req_rmeta_WIRE_19_2_tag; // @[btb.scala:74:{29,53}]
wire s1_req_rmeta_1_3_is_br = _s1_req_rmeta_WIRE_19_3_is_br; // @[btb.scala:74:{29,53}]
wire [28:0] s1_req_rmeta_1_3_tag = _s1_req_rmeta_WIRE_19_3_tag; // @[btb.scala:74:{29,53}]
wire [28:0] _alloc_way_r_metas_WIRE_0 = s1_req_rmeta_0_0_tag; // @[btb.scala:74:29, :123:62]
wire [28:0] _alloc_way_r_metas_WIRE_1 = s1_req_rmeta_0_1_tag; // @[btb.scala:74:29, :123:62]
wire [28:0] _alloc_way_r_metas_WIRE_2 = s1_req_rmeta_0_2_tag; // @[btb.scala:74:29, :123:62]
wire [28:0] _alloc_way_r_metas_WIRE_3 = s1_req_rmeta_0_3_tag; // @[btb.scala:74:29, :123:62]
wire [28:0] _alloc_way_r_metas_WIRE_1_0 = s1_req_rmeta_1_0_tag; // @[btb.scala:74:29, :123:62]
wire [28:0] _alloc_way_r_metas_WIRE_1_1 = s1_req_rmeta_1_1_tag; // @[btb.scala:74:29, :123:62]
wire [28:0] _alloc_way_r_metas_WIRE_1_2 = s1_req_rmeta_1_2_tag; // @[btb.scala:74:29, :123:62]
wire [28:0] _alloc_way_r_metas_WIRE_1_3 = s1_req_rmeta_1_3_tag; // @[btb.scala:74:29, :123:62]
wire [6:0] _s1_req_rebtb_T = _s1_req_rebtb_WIRE[6:0]; // @[btb.scala:75:31]
wire [28:0] s1_req_tag = s1_idx[35:7]; // @[predictor.scala:163:29]
wire [28:0] _s1_hit_ohs_T = s1_req_tag; // @[btb.scala:76:29, :84:44]
wire [28:0] _s1_hit_ohs_T_2 = s1_req_tag; // @[btb.scala:76:29, :84:44]
wire [28:0] _s1_hit_ohs_T_4 = s1_req_tag; // @[btb.scala:76:29, :84:44]
wire [28:0] _s1_hit_ohs_T_6 = s1_req_tag; // @[btb.scala:76:29, :84:44]
wire [28:0] _s1_hit_ohs_T_8 = s1_req_tag; // @[btb.scala:76:29, :84:44]
wire [28:0] _s1_hit_ohs_T_10 = s1_req_tag; // @[btb.scala:76:29, :84:44]
wire [28:0] _s1_hit_ohs_T_12 = s1_req_tag; // @[btb.scala:76:29, :84:44]
wire [28:0] _s1_hit_ohs_T_14 = s1_req_tag; // @[btb.scala:76:29, :84:44]
wire [28:0] _alloc_way_r_metas_T_3 = s1_req_tag; // @[btb.scala:76:29, :123:98]
wire _s1_resp_0_valid_T_2; // @[btb.scala:93:50]
wire [39:0] _s1_resp_0_bits_T_8; // @[btb.scala:94:28]
wire _s1_resp_1_valid_T_2; // @[btb.scala:93:50]
wire [39:0] _s1_resp_1_bits_T_8; // @[btb.scala:94:28]
wire _s1_resp_2_valid_T_2; // @[btb.scala:93:50]
wire [39:0] _s1_resp_2_bits_T_8; // @[btb.scala:94:28]
wire _s1_resp_3_valid_T_2; // @[btb.scala:93:50]
wire [39:0] _s1_resp_3_bits_T_8; // @[btb.scala:94:28]
wire s1_resp_0_valid; // @[btb.scala:78:23]
wire [39:0] s1_resp_0_bits; // @[btb.scala:78:23]
wire s1_resp_1_valid; // @[btb.scala:78:23]
wire [39:0] s1_resp_1_bits; // @[btb.scala:78:23]
wire s1_resp_2_valid; // @[btb.scala:78:23]
wire [39:0] s1_resp_2_bits; // @[btb.scala:78:23]
wire s1_resp_3_valid; // @[btb.scala:78:23]
wire [39:0] s1_resp_3_bits; // @[btb.scala:78:23]
wire _s1_is_br_0_T_2; // @[btb.scala:98:54]
wire _s1_is_br_1_T_2; // @[btb.scala:98:54]
wire _s1_is_br_2_T_2; // @[btb.scala:98:54]
wire _s1_is_br_3_T_2; // @[btb.scala:98:54]
wire s1_is_br_0; // @[btb.scala:79:23]
wire s1_is_br_1; // @[btb.scala:79:23]
wire s1_is_br_2; // @[btb.scala:79:23]
wire s1_is_br_3; // @[btb.scala:79:23]
wire _s1_is_jal_0_T_3; // @[btb.scala:99:54]
wire _s1_is_jal_1_T_3; // @[btb.scala:99:54]
wire _s1_is_jal_2_T_3; // @[btb.scala:99:54]
wire _s1_is_jal_3_T_3; // @[btb.scala:99:54]
wire s1_is_jal_0; // @[btb.scala:80:23]
wire s1_is_jal_1; // @[btb.scala:80:23]
wire s1_is_jal_2; // @[btb.scala:80:23]
wire s1_is_jal_3; // @[btb.scala:80:23]
wire _s1_hit_ohs_T_1 = s1_req_rmeta_0_0_tag == _s1_hit_ohs_T; // @[btb.scala:74:29, :84:{30,44}]
wire _s1_hit_ohs_WIRE_0 = _s1_hit_ohs_T_1; // @[btb.scala:83:12, :84:30]
wire _s1_hit_ohs_T_3 = s1_req_rmeta_1_0_tag == _s1_hit_ohs_T_2; // @[btb.scala:74:29, :84:{30,44}]
wire _s1_hit_ohs_WIRE_1 = _s1_hit_ohs_T_3; // @[btb.scala:83:12, :84:30]
wire s1_hit_ohs_0_0 = _s1_hit_ohs_WIRE_0; // @[btb.scala:82:27, :83:12]
wire s1_hit_ohs_0_1 = _s1_hit_ohs_WIRE_1; // @[btb.scala:82:27, :83:12]
wire _s1_hit_ohs_T_5 = s1_req_rmeta_0_1_tag == _s1_hit_ohs_T_4; // @[btb.scala:74:29, :84:{30,44}]
wire _s1_hit_ohs_WIRE_1_0 = _s1_hit_ohs_T_5; // @[btb.scala:83:12, :84:30]
wire _s1_hit_ohs_T_7 = s1_req_rmeta_1_1_tag == _s1_hit_ohs_T_6; // @[btb.scala:74:29, :84:{30,44}]
wire _s1_hit_ohs_WIRE_1_1 = _s1_hit_ohs_T_7; // @[btb.scala:83:12, :84:30]
wire s1_hit_ohs_1_0 = _s1_hit_ohs_WIRE_1_0; // @[btb.scala:82:27, :83:12]
wire s1_hit_ohs_1_1 = _s1_hit_ohs_WIRE_1_1; // @[btb.scala:82:27, :83:12]
wire _s1_hit_ohs_T_9 = s1_req_rmeta_0_2_tag == _s1_hit_ohs_T_8; // @[btb.scala:74:29, :84:{30,44}]
wire _s1_hit_ohs_WIRE_2_0 = _s1_hit_ohs_T_9; // @[btb.scala:83:12, :84:30]
wire _s1_hit_ohs_T_11 = s1_req_rmeta_1_2_tag == _s1_hit_ohs_T_10; // @[btb.scala:74:29, :84:{30,44}]
wire _s1_hit_ohs_WIRE_2_1 = _s1_hit_ohs_T_11; // @[btb.scala:83:12, :84:30]
wire s1_hit_ohs_2_0 = _s1_hit_ohs_WIRE_2_0; // @[btb.scala:82:27, :83:12]
wire s1_hit_ohs_2_1 = _s1_hit_ohs_WIRE_2_1; // @[btb.scala:82:27, :83:12]
wire _s1_hit_ohs_T_13 = s1_req_rmeta_0_3_tag == _s1_hit_ohs_T_12; // @[btb.scala:74:29, :84:{30,44}]
wire _s1_hit_ohs_WIRE_3_0 = _s1_hit_ohs_T_13; // @[btb.scala:83:12, :84:30]
wire _s1_hit_ohs_T_15 = s1_req_rmeta_1_3_tag == _s1_hit_ohs_T_14; // @[btb.scala:74:29, :84:{30,44}]
wire _s1_hit_ohs_WIRE_3_1 = _s1_hit_ohs_T_15; // @[btb.scala:83:12, :84:30]
wire s1_hit_ohs_3_0 = _s1_hit_ohs_WIRE_3_0; // @[btb.scala:82:27, :83:12]
wire s1_hit_ohs_3_1 = _s1_hit_ohs_WIRE_3_1; // @[btb.scala:82:27, :83:12]
wire s1_hits_0 = s1_hit_ohs_0_0 | s1_hit_ohs_0_1; // @[btb.scala:82:27, :87:55]
wire s1_hits_1 = s1_hit_ohs_1_0 | s1_hit_ohs_1_1; // @[btb.scala:82:27, :87:55]
wire s1_hits_2 = s1_hit_ohs_2_0 | s1_hit_ohs_2_1; // @[btb.scala:82:27, :87:55]
wire s1_hits_3 = s1_hit_ohs_3_0 | s1_hit_ohs_3_1; // @[btb.scala:82:27, :87:55]
wire s1_hit_ways_0 = ~s1_hit_ohs_0_0; // @[Mux.scala:50:70]
wire s1_hit_ways_1 = ~s1_hit_ohs_1_0; // @[Mux.scala:50:70]
wire s1_hit_ways_2 = ~s1_hit_ohs_2_0; // @[Mux.scala:50:70]
wire s1_hit_ways_3 = ~s1_hit_ohs_3_0; // @[Mux.scala:50:70]
wire _s1_resp_0_valid_T = ~doing_reset; // @[btb.scala:60:28, :93:25]
wire _s1_resp_0_valid_T_1 = _s1_resp_0_valid_T & s1_valid; // @[predictor.scala:168:25]
assign _s1_resp_0_valid_T_2 = _s1_resp_0_valid_T_1 & s1_hits_0; // @[btb.scala:87:55, :93:{38,50}]
assign s1_resp_0_valid = _s1_resp_0_valid_T_2; // @[btb.scala:78:23, :93:50]
wire [40:0] _s1_resp_0_bits_T_1 = {_s1_resp_0_bits_T[39], _s1_resp_0_bits_T}; // @[btb.scala:97:{14,21}]
wire [39:0] _s1_resp_0_bits_T_2 = _s1_resp_0_bits_T_1[39:0]; // @[btb.scala:97:21]
wire [39:0] _s1_resp_0_bits_T_3 = _s1_resp_0_bits_T_2; // @[btb.scala:97:21]
wire [12:0] _GEN = s1_hit_ways_0 ? s1_req_rbtb_1_0_offset : s1_req_rbtb_0_0_offset; // @[Mux.scala:50:70]
wire [40:0] _s1_resp_0_bits_T_4 = {_s1_resp_0_bits_T_3[39], _s1_resp_0_bits_T_3} + {{28{_GEN[12]}}, _GEN}; // @[btb.scala:97:{21,34}]
wire [39:0] _s1_resp_0_bits_T_5 = _s1_resp_0_bits_T_4[39:0]; // @[btb.scala:97:34]
wire [39:0] _s1_resp_0_bits_T_6 = _s1_resp_0_bits_T_5; // @[btb.scala:97:34]
wire [39:0] _s1_resp_0_bits_T_7 = _s1_resp_0_bits_T_6; // @[btb.scala:97:{34,54}]
assign _s1_resp_0_bits_T_8 = (s1_hit_ways_0 ? s1_req_rbtb_1_0_extended : s1_req_rbtb_0_0_extended) ? _ebtb_R0_data : _s1_resp_0_bits_T_7; // @[Mux.scala:50:70]
assign s1_resp_0_bits = _s1_resp_0_bits_T_8; // @[btb.scala:78:23, :94:28]
wire _s1_is_br_0_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :98:21]
wire _s1_is_br_0_T_1 = _s1_is_br_0_T & s1_resp_0_valid; // @[btb.scala:78:23, :98:{21,34}]
wire _GEN_0 = s1_hit_ways_0 ? s1_req_rmeta_1_0_is_br : s1_req_rmeta_0_0_is_br; // @[Mux.scala:50:70]
assign _s1_is_br_0_T_2 = _s1_is_br_0_T_1 & _GEN_0; // @[btb.scala:98:{34,54}]
assign s1_is_br_0 = _s1_is_br_0_T_2; // @[btb.scala:79:23, :98:54]
wire _s1_is_jal_0_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :99:21]
wire _s1_is_jal_0_T_1 = _s1_is_jal_0_T & s1_resp_0_valid; // @[btb.scala:78:23, :99:{21,34}]
wire _s1_is_jal_0_T_2 = ~_GEN_0; // @[btb.scala:98:54, :99:57]
assign _s1_is_jal_0_T_3 = _s1_is_jal_0_T_1 & _s1_is_jal_0_T_2; // @[btb.scala:99:{34,54,57}]
assign s1_is_jal_0 = _s1_is_jal_0_T_3; // @[btb.scala:80:23, :99:54]
reg REG; // @[btb.scala:104:18]
reg io_resp_f2_0_predicted_pc_REG_valid; // @[btb.scala:105:44]
reg [39:0] io_resp_f2_0_predicted_pc_REG_bits; // @[btb.scala:105:44]
assign io_resp_f2_0_predicted_pc_valid_0 = REG ? io_resp_f2_0_predicted_pc_REG_valid : io_resp_in_0_f2_0_predicted_pc_valid_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}]
assign io_resp_f2_0_predicted_pc_bits_0 = REG ? io_resp_f2_0_predicted_pc_REG_bits : io_resp_in_0_f2_0_predicted_pc_bits_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}]
reg io_resp_f2_0_is_br_REG; // @[btb.scala:106:44]
assign io_resp_f2_0_is_br_0 = REG ? io_resp_f2_0_is_br_REG : io_resp_in_0_f2_0_is_br_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :106:{34,44}]
reg io_resp_f2_0_is_jal_REG; // @[btb.scala:107:44]
assign io_resp_f2_0_is_jal_0 = REG ? io_resp_f2_0_is_jal_REG : io_resp_in_0_f2_0_is_jal_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :107:{34,44}]
reg REG_1; // @[btb.scala:108:20]
assign io_resp_f2_0_taken_0 = REG & REG_1 | io_resp_in_0_f2_0_taken_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :108:{20,36}, :109:34]
reg REG_2; // @[btb.scala:112:26]
reg REG_3; // @[btb.scala:112:18]
reg io_resp_f3_0_predicted_pc_REG_valid; // @[btb.scala:113:44]
reg [39:0] io_resp_f3_0_predicted_pc_REG_bits; // @[btb.scala:113:44]
assign io_resp_f3_0_predicted_pc_valid_0 = REG_3 ? io_resp_f3_0_predicted_pc_REG_valid : io_resp_in_0_f3_0_predicted_pc_valid_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}]
assign io_resp_f3_0_predicted_pc_bits_0 = REG_3 ? io_resp_f3_0_predicted_pc_REG_bits : io_resp_in_0_f3_0_predicted_pc_bits_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}]
reg io_resp_f3_0_is_br_REG; // @[btb.scala:114:44]
assign io_resp_f3_0_is_br_0 = REG_3 ? io_resp_f3_0_is_br_REG : io_resp_in_0_f3_0_is_br_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :114:{34,44}]
reg io_resp_f3_0_is_jal_REG; // @[btb.scala:115:44]
assign io_resp_f3_0_is_jal_0 = REG_3 ? io_resp_f3_0_is_jal_REG : io_resp_in_0_f3_0_is_jal_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :115:{34,44}]
reg REG_4; // @[btb.scala:116:28]
reg REG_5; // @[btb.scala:116:20]
assign io_resp_f3_0_taken_0 = REG_3 & REG_5 | io_resp_in_0_f3_0_taken_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :116:{20,45}, :117:34]
wire _s1_resp_1_valid_T = ~doing_reset; // @[btb.scala:60:28, :93:25]
wire _s1_resp_1_valid_T_1 = _s1_resp_1_valid_T & s1_valid; // @[predictor.scala:168:25]
assign _s1_resp_1_valid_T_2 = _s1_resp_1_valid_T_1 & s1_hits_1; // @[btb.scala:87:55, :93:{38,50}]
assign s1_resp_1_valid = _s1_resp_1_valid_T_2; // @[btb.scala:78:23, :93:50]
wire [40:0] _s1_resp_1_bits_T_1 = {_s1_resp_1_bits_T[39], _s1_resp_1_bits_T} + 41'h2; // @[btb.scala:97:{14,21}]
wire [39:0] _s1_resp_1_bits_T_2 = _s1_resp_1_bits_T_1[39:0]; // @[btb.scala:97:21]
wire [39:0] _s1_resp_1_bits_T_3 = _s1_resp_1_bits_T_2; // @[btb.scala:97:21]
wire [12:0] _GEN_1 = s1_hit_ways_1 ? s1_req_rbtb_1_1_offset : s1_req_rbtb_0_1_offset; // @[Mux.scala:50:70]
wire [40:0] _s1_resp_1_bits_T_4 = {_s1_resp_1_bits_T_3[39], _s1_resp_1_bits_T_3} + {{28{_GEN_1[12]}}, _GEN_1}; // @[btb.scala:97:{21,34}]
wire [39:0] _s1_resp_1_bits_T_5 = _s1_resp_1_bits_T_4[39:0]; // @[btb.scala:97:34]
wire [39:0] _s1_resp_1_bits_T_6 = _s1_resp_1_bits_T_5; // @[btb.scala:97:34]
wire [39:0] _s1_resp_1_bits_T_7 = _s1_resp_1_bits_T_6; // @[btb.scala:97:{34,54}]
assign _s1_resp_1_bits_T_8 = (s1_hit_ways_1 ? s1_req_rbtb_1_1_extended : s1_req_rbtb_0_1_extended) ? _ebtb_R0_data : _s1_resp_1_bits_T_7; // @[Mux.scala:50:70]
assign s1_resp_1_bits = _s1_resp_1_bits_T_8; // @[btb.scala:78:23, :94:28]
wire _s1_is_br_1_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :98:21]
wire _s1_is_br_1_T_1 = _s1_is_br_1_T & s1_resp_1_valid; // @[btb.scala:78:23, :98:{21,34}]
wire _GEN_2 = s1_hit_ways_1 ? s1_req_rmeta_1_1_is_br : s1_req_rmeta_0_1_is_br; // @[Mux.scala:50:70]
assign _s1_is_br_1_T_2 = _s1_is_br_1_T_1 & _GEN_2; // @[btb.scala:98:{34,54}]
assign s1_is_br_1 = _s1_is_br_1_T_2; // @[btb.scala:79:23, :98:54]
wire _s1_is_jal_1_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :99:21]
wire _s1_is_jal_1_T_1 = _s1_is_jal_1_T & s1_resp_1_valid; // @[btb.scala:78:23, :99:{21,34}]
wire _s1_is_jal_1_T_2 = ~_GEN_2; // @[btb.scala:98:54, :99:57]
assign _s1_is_jal_1_T_3 = _s1_is_jal_1_T_1 & _s1_is_jal_1_T_2; // @[btb.scala:99:{34,54,57}]
assign s1_is_jal_1 = _s1_is_jal_1_T_3; // @[btb.scala:80:23, :99:54]
reg REG_6; // @[btb.scala:104:18]
reg io_resp_f2_1_predicted_pc_REG_valid; // @[btb.scala:105:44]
reg [39:0] io_resp_f2_1_predicted_pc_REG_bits; // @[btb.scala:105:44]
assign io_resp_f2_1_predicted_pc_valid_0 = REG_6 ? io_resp_f2_1_predicted_pc_REG_valid : io_resp_in_0_f2_1_predicted_pc_valid_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}]
assign io_resp_f2_1_predicted_pc_bits_0 = REG_6 ? io_resp_f2_1_predicted_pc_REG_bits : io_resp_in_0_f2_1_predicted_pc_bits_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}]
reg io_resp_f2_1_is_br_REG; // @[btb.scala:106:44]
assign io_resp_f2_1_is_br_0 = REG_6 ? io_resp_f2_1_is_br_REG : io_resp_in_0_f2_1_is_br_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :106:{34,44}]
reg io_resp_f2_1_is_jal_REG; // @[btb.scala:107:44]
assign io_resp_f2_1_is_jal_0 = REG_6 ? io_resp_f2_1_is_jal_REG : io_resp_in_0_f2_1_is_jal_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :107:{34,44}]
reg REG_7; // @[btb.scala:108:20]
assign io_resp_f2_1_taken_0 = REG_6 & REG_7 | io_resp_in_0_f2_1_taken_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :108:{20,36}, :109:34]
reg REG_8; // @[btb.scala:112:26]
reg REG_9; // @[btb.scala:112:18]
reg io_resp_f3_1_predicted_pc_REG_valid; // @[btb.scala:113:44]
reg [39:0] io_resp_f3_1_predicted_pc_REG_bits; // @[btb.scala:113:44]
assign io_resp_f3_1_predicted_pc_valid_0 = REG_9 ? io_resp_f3_1_predicted_pc_REG_valid : io_resp_in_0_f3_1_predicted_pc_valid_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}]
assign io_resp_f3_1_predicted_pc_bits_0 = REG_9 ? io_resp_f3_1_predicted_pc_REG_bits : io_resp_in_0_f3_1_predicted_pc_bits_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}]
reg io_resp_f3_1_is_br_REG; // @[btb.scala:114:44]
assign io_resp_f3_1_is_br_0 = REG_9 ? io_resp_f3_1_is_br_REG : io_resp_in_0_f3_1_is_br_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :114:{34,44}]
reg io_resp_f3_1_is_jal_REG; // @[btb.scala:115:44]
assign io_resp_f3_1_is_jal_0 = REG_9 ? io_resp_f3_1_is_jal_REG : io_resp_in_0_f3_1_is_jal_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :115:{34,44}]
reg REG_10; // @[btb.scala:116:28]
reg REG_11; // @[btb.scala:116:20]
assign io_resp_f3_1_taken_0 = REG_9 & REG_11 | io_resp_in_0_f3_1_taken_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :116:{20,45}, :117:34]
wire _s1_resp_2_valid_T = ~doing_reset; // @[btb.scala:60:28, :93:25]
wire _s1_resp_2_valid_T_1 = _s1_resp_2_valid_T & s1_valid; // @[predictor.scala:168:25]
assign _s1_resp_2_valid_T_2 = _s1_resp_2_valid_T_1 & s1_hits_2; // @[btb.scala:87:55, :93:{38,50}]
assign s1_resp_2_valid = _s1_resp_2_valid_T_2; // @[btb.scala:78:23, :93:50]
wire [40:0] _s1_resp_2_bits_T_1 = {_s1_resp_2_bits_T[39], _s1_resp_2_bits_T} + 41'h4; // @[btb.scala:97:{14,21}]
wire [39:0] _s1_resp_2_bits_T_2 = _s1_resp_2_bits_T_1[39:0]; // @[btb.scala:97:21]
wire [39:0] _s1_resp_2_bits_T_3 = _s1_resp_2_bits_T_2; // @[btb.scala:97:21]
wire [12:0] _GEN_3 = s1_hit_ways_2 ? s1_req_rbtb_1_2_offset : s1_req_rbtb_0_2_offset; // @[Mux.scala:50:70]
wire [40:0] _s1_resp_2_bits_T_4 = {_s1_resp_2_bits_T_3[39], _s1_resp_2_bits_T_3} + {{28{_GEN_3[12]}}, _GEN_3}; // @[btb.scala:97:{21,34}]
wire [39:0] _s1_resp_2_bits_T_5 = _s1_resp_2_bits_T_4[39:0]; // @[btb.scala:97:34]
wire [39:0] _s1_resp_2_bits_T_6 = _s1_resp_2_bits_T_5; // @[btb.scala:97:34]
wire [39:0] _s1_resp_2_bits_T_7 = _s1_resp_2_bits_T_6; // @[btb.scala:97:{34,54}]
assign _s1_resp_2_bits_T_8 = (s1_hit_ways_2 ? s1_req_rbtb_1_2_extended : s1_req_rbtb_0_2_extended) ? _ebtb_R0_data : _s1_resp_2_bits_T_7; // @[Mux.scala:50:70]
assign s1_resp_2_bits = _s1_resp_2_bits_T_8; // @[btb.scala:78:23, :94:28]
wire _s1_is_br_2_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :98:21]
wire _s1_is_br_2_T_1 = _s1_is_br_2_T & s1_resp_2_valid; // @[btb.scala:78:23, :98:{21,34}]
wire _GEN_4 = s1_hit_ways_2 ? s1_req_rmeta_1_2_is_br : s1_req_rmeta_0_2_is_br; // @[Mux.scala:50:70]
assign _s1_is_br_2_T_2 = _s1_is_br_2_T_1 & _GEN_4; // @[btb.scala:98:{34,54}]
assign s1_is_br_2 = _s1_is_br_2_T_2; // @[btb.scala:79:23, :98:54]
wire _s1_is_jal_2_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :99:21]
wire _s1_is_jal_2_T_1 = _s1_is_jal_2_T & s1_resp_2_valid; // @[btb.scala:78:23, :99:{21,34}]
wire _s1_is_jal_2_T_2 = ~_GEN_4; // @[btb.scala:98:54, :99:57]
assign _s1_is_jal_2_T_3 = _s1_is_jal_2_T_1 & _s1_is_jal_2_T_2; // @[btb.scala:99:{34,54,57}]
assign s1_is_jal_2 = _s1_is_jal_2_T_3; // @[btb.scala:80:23, :99:54]
reg REG_12; // @[btb.scala:104:18]
reg io_resp_f2_2_predicted_pc_REG_valid; // @[btb.scala:105:44]
reg [39:0] io_resp_f2_2_predicted_pc_REG_bits; // @[btb.scala:105:44]
assign io_resp_f2_2_predicted_pc_valid_0 = REG_12 ? io_resp_f2_2_predicted_pc_REG_valid : io_resp_in_0_f2_2_predicted_pc_valid_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}]
assign io_resp_f2_2_predicted_pc_bits_0 = REG_12 ? io_resp_f2_2_predicted_pc_REG_bits : io_resp_in_0_f2_2_predicted_pc_bits_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}]
reg io_resp_f2_2_is_br_REG; // @[btb.scala:106:44]
assign io_resp_f2_2_is_br_0 = REG_12 ? io_resp_f2_2_is_br_REG : io_resp_in_0_f2_2_is_br_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :106:{34,44}]
reg io_resp_f2_2_is_jal_REG; // @[btb.scala:107:44]
assign io_resp_f2_2_is_jal_0 = REG_12 ? io_resp_f2_2_is_jal_REG : io_resp_in_0_f2_2_is_jal_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :107:{34,44}]
reg REG_13; // @[btb.scala:108:20]
assign io_resp_f2_2_taken_0 = REG_12 & REG_13 | io_resp_in_0_f2_2_taken_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :108:{20,36}, :109:34]
reg REG_14; // @[btb.scala:112:26]
reg REG_15; // @[btb.scala:112:18]
reg io_resp_f3_2_predicted_pc_REG_valid; // @[btb.scala:113:44]
reg [39:0] io_resp_f3_2_predicted_pc_REG_bits; // @[btb.scala:113:44]
assign io_resp_f3_2_predicted_pc_valid_0 = REG_15 ? io_resp_f3_2_predicted_pc_REG_valid : io_resp_in_0_f3_2_predicted_pc_valid_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}]
assign io_resp_f3_2_predicted_pc_bits_0 = REG_15 ? io_resp_f3_2_predicted_pc_REG_bits : io_resp_in_0_f3_2_predicted_pc_bits_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}]
reg io_resp_f3_2_is_br_REG; // @[btb.scala:114:44]
assign io_resp_f3_2_is_br_0 = REG_15 ? io_resp_f3_2_is_br_REG : io_resp_in_0_f3_2_is_br_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :114:{34,44}]
reg io_resp_f3_2_is_jal_REG; // @[btb.scala:115:44]
assign io_resp_f3_2_is_jal_0 = REG_15 ? io_resp_f3_2_is_jal_REG : io_resp_in_0_f3_2_is_jal_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :115:{34,44}]
reg REG_16; // @[btb.scala:116:28]
reg REG_17; // @[btb.scala:116:20]
assign io_resp_f3_2_taken_0 = REG_15 & REG_17 | io_resp_in_0_f3_2_taken_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :116:{20,45}, :117:34]
wire _s1_resp_3_valid_T = ~doing_reset; // @[btb.scala:60:28, :93:25]
wire _s1_resp_3_valid_T_1 = _s1_resp_3_valid_T & s1_valid; // @[predictor.scala:168:25]
assign _s1_resp_3_valid_T_2 = _s1_resp_3_valid_T_1 & s1_hits_3; // @[btb.scala:87:55, :93:{38,50}]
assign s1_resp_3_valid = _s1_resp_3_valid_T_2; // @[btb.scala:78:23, :93:50]
wire [40:0] _s1_resp_3_bits_T_1 = {_s1_resp_3_bits_T[39], _s1_resp_3_bits_T} + 41'h6; // @[btb.scala:97:{14,21}]
wire [39:0] _s1_resp_3_bits_T_2 = _s1_resp_3_bits_T_1[39:0]; // @[btb.scala:97:21]
wire [39:0] _s1_resp_3_bits_T_3 = _s1_resp_3_bits_T_2; // @[btb.scala:97:21]
wire [12:0] _GEN_5 = s1_hit_ways_3 ? s1_req_rbtb_1_3_offset : s1_req_rbtb_0_3_offset; // @[Mux.scala:50:70]
wire [40:0] _s1_resp_3_bits_T_4 = {_s1_resp_3_bits_T_3[39], _s1_resp_3_bits_T_3} + {{28{_GEN_5[12]}}, _GEN_5}; // @[btb.scala:97:{21,34}]
wire [39:0] _s1_resp_3_bits_T_5 = _s1_resp_3_bits_T_4[39:0]; // @[btb.scala:97:34]
wire [39:0] _s1_resp_3_bits_T_6 = _s1_resp_3_bits_T_5; // @[btb.scala:97:34]
wire [39:0] _s1_resp_3_bits_T_7 = _s1_resp_3_bits_T_6; // @[btb.scala:97:{34,54}]
assign _s1_resp_3_bits_T_8 = (s1_hit_ways_3 ? s1_req_rbtb_1_3_extended : s1_req_rbtb_0_3_extended) ? _ebtb_R0_data : _s1_resp_3_bits_T_7; // @[Mux.scala:50:70]
assign s1_resp_3_bits = _s1_resp_3_bits_T_8; // @[btb.scala:78:23, :94:28]
wire _s1_is_br_3_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :98:21]
wire _s1_is_br_3_T_1 = _s1_is_br_3_T & s1_resp_3_valid; // @[btb.scala:78:23, :98:{21,34}]
wire _GEN_6 = s1_hit_ways_3 ? s1_req_rmeta_1_3_is_br : s1_req_rmeta_0_3_is_br; // @[Mux.scala:50:70]
assign _s1_is_br_3_T_2 = _s1_is_br_3_T_1 & _GEN_6; // @[btb.scala:98:{34,54}]
assign s1_is_br_3 = _s1_is_br_3_T_2; // @[btb.scala:79:23, :98:54]
wire _s1_is_jal_3_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :99:21]
wire _s1_is_jal_3_T_1 = _s1_is_jal_3_T & s1_resp_3_valid; // @[btb.scala:78:23, :99:{21,34}]
wire _s1_is_jal_3_T_2 = ~_GEN_6; // @[btb.scala:98:54, :99:57]
assign _s1_is_jal_3_T_3 = _s1_is_jal_3_T_1 & _s1_is_jal_3_T_2; // @[btb.scala:99:{34,54,57}]
assign s1_is_jal_3 = _s1_is_jal_3_T_3; // @[btb.scala:80:23, :99:54]
reg REG_18; // @[btb.scala:104:18]
reg io_resp_f2_3_predicted_pc_REG_valid; // @[btb.scala:105:44]
reg [39:0] io_resp_f2_3_predicted_pc_REG_bits; // @[btb.scala:105:44]
assign io_resp_f2_3_predicted_pc_valid_0 = REG_18 ? io_resp_f2_3_predicted_pc_REG_valid : io_resp_in_0_f2_3_predicted_pc_valid_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}]
assign io_resp_f2_3_predicted_pc_bits_0 = REG_18 ? io_resp_f2_3_predicted_pc_REG_bits : io_resp_in_0_f2_3_predicted_pc_bits_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}]
reg io_resp_f2_3_is_br_REG; // @[btb.scala:106:44]
assign io_resp_f2_3_is_br_0 = REG_18 ? io_resp_f2_3_is_br_REG : io_resp_in_0_f2_3_is_br_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :106:{34,44}]
reg io_resp_f2_3_is_jal_REG; // @[btb.scala:107:44]
assign io_resp_f2_3_is_jal_0 = REG_18 ? io_resp_f2_3_is_jal_REG : io_resp_in_0_f2_3_is_jal_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :107:{34,44}]
reg REG_19; // @[btb.scala:108:20]
assign io_resp_f2_3_taken_0 = REG_18 & REG_19 | io_resp_in_0_f2_3_taken_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :108:{20,36}, :109:34]
reg REG_20; // @[btb.scala:112:26]
reg REG_21; // @[btb.scala:112:18]
reg io_resp_f3_3_predicted_pc_REG_valid; // @[btb.scala:113:44]
reg [39:0] io_resp_f3_3_predicted_pc_REG_bits; // @[btb.scala:113:44]
assign io_resp_f3_3_predicted_pc_valid_0 = REG_21 ? io_resp_f3_3_predicted_pc_REG_valid : io_resp_in_0_f3_3_predicted_pc_valid_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}]
assign io_resp_f3_3_predicted_pc_bits_0 = REG_21 ? io_resp_f3_3_predicted_pc_REG_bits : io_resp_in_0_f3_3_predicted_pc_bits_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}]
reg io_resp_f3_3_is_br_REG; // @[btb.scala:114:44]
assign io_resp_f3_3_is_br_0 = REG_21 ? io_resp_f3_3_is_br_REG : io_resp_in_0_f3_3_is_br_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :114:{34,44}]
reg io_resp_f3_3_is_jal_REG; // @[btb.scala:115:44]
assign io_resp_f3_3_is_jal_0 = REG_21 ? io_resp_f3_3_is_jal_REG : io_resp_in_0_f3_3_is_jal_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :115:{34,44}]
reg REG_22; // @[btb.scala:116:28]
reg REG_23; // @[btb.scala:116:20]
assign io_resp_f3_3_taken_0 = REG_21 & REG_23 | io_resp_in_0_f3_3_taken_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :116:{20,45}, :117:34]
wire [28:0] _alloc_way_r_metas_WIRE_2_0_0 = _alloc_way_r_metas_WIRE_0; // @[btb.scala:123:{30,62}]
wire [28:0] _alloc_way_r_metas_WIRE_2_0_1 = _alloc_way_r_metas_WIRE_1; // @[btb.scala:123:{30,62}]
wire [28:0] _alloc_way_r_metas_WIRE_2_0_2 = _alloc_way_r_metas_WIRE_2; // @[btb.scala:123:{30,62}]
wire [28:0] _alloc_way_r_metas_WIRE_2_0_3 = _alloc_way_r_metas_WIRE_3; // @[btb.scala:123:{30,62}]
wire [28:0] _alloc_way_r_metas_WIRE_2_1_0 = _alloc_way_r_metas_WIRE_1_0; // @[btb.scala:123:{30,62}]
wire [28:0] _alloc_way_r_metas_WIRE_2_1_1 = _alloc_way_r_metas_WIRE_1_1; // @[btb.scala:123:{30,62}]
wire [28:0] _alloc_way_r_metas_WIRE_2_1_2 = _alloc_way_r_metas_WIRE_1_2; // @[btb.scala:123:{30,62}]
wire [28:0] _alloc_way_r_metas_WIRE_2_1_3 = _alloc_way_r_metas_WIRE_1_3; // @[btb.scala:123:{30,62}]
wire [57:0] alloc_way_r_metas_lo = {_alloc_way_r_metas_WIRE_2_0_1, _alloc_way_r_metas_WIRE_2_0_0}; // @[btb.scala:123:{30,80}]
wire [57:0] alloc_way_r_metas_hi = {_alloc_way_r_metas_WIRE_2_0_3, _alloc_way_r_metas_WIRE_2_0_2}; // @[btb.scala:123:{30,80}]
wire [115:0] _alloc_way_r_metas_T = {alloc_way_r_metas_hi, alloc_way_r_metas_lo}; // @[btb.scala:123:80]
wire [57:0] alloc_way_r_metas_lo_1 = {_alloc_way_r_metas_WIRE_2_1_1, _alloc_way_r_metas_WIRE_2_1_0}; // @[btb.scala:123:{30,80}]
wire [57:0] alloc_way_r_metas_hi_1 = {_alloc_way_r_metas_WIRE_2_1_3, _alloc_way_r_metas_WIRE_2_1_2}; // @[btb.scala:123:{30,80}]
wire [115:0] _alloc_way_r_metas_T_1 = {alloc_way_r_metas_hi_1, alloc_way_r_metas_lo_1}; // @[btb.scala:123:80]
wire [231:0] _alloc_way_r_metas_T_2 = {_alloc_way_r_metas_T_1, _alloc_way_r_metas_T}; // @[btb.scala:123:80]
wire [260:0] alloc_way_r_metas = {_alloc_way_r_metas_T_2, _alloc_way_r_metas_T_3}; // @[btb.scala:123:{22,80,98}]
wire alloc_way_chunks_0 = alloc_way_r_metas[0]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_1 = alloc_way_r_metas[1]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_2 = alloc_way_r_metas[2]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_3 = alloc_way_r_metas[3]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_4 = alloc_way_r_metas[4]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_5 = alloc_way_r_metas[5]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_6 = alloc_way_r_metas[6]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_7 = alloc_way_r_metas[7]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_8 = alloc_way_r_metas[8]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_9 = alloc_way_r_metas[9]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_10 = alloc_way_r_metas[10]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_11 = alloc_way_r_metas[11]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_12 = alloc_way_r_metas[12]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_13 = alloc_way_r_metas[13]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_14 = alloc_way_r_metas[14]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_15 = alloc_way_r_metas[15]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_16 = alloc_way_r_metas[16]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_17 = alloc_way_r_metas[17]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_18 = alloc_way_r_metas[18]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_19 = alloc_way_r_metas[19]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_20 = alloc_way_r_metas[20]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_21 = alloc_way_r_metas[21]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_22 = alloc_way_r_metas[22]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_23 = alloc_way_r_metas[23]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_24 = alloc_way_r_metas[24]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_25 = alloc_way_r_metas[25]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_26 = alloc_way_r_metas[26]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_27 = alloc_way_r_metas[27]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_28 = alloc_way_r_metas[28]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_29 = alloc_way_r_metas[29]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_30 = alloc_way_r_metas[30]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_31 = alloc_way_r_metas[31]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_32 = alloc_way_r_metas[32]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_33 = alloc_way_r_metas[33]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_34 = alloc_way_r_metas[34]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_35 = alloc_way_r_metas[35]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_36 = alloc_way_r_metas[36]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_37 = alloc_way_r_metas[37]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_38 = alloc_way_r_metas[38]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_39 = alloc_way_r_metas[39]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_40 = alloc_way_r_metas[40]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_41 = alloc_way_r_metas[41]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_42 = alloc_way_r_metas[42]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_43 = alloc_way_r_metas[43]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_44 = alloc_way_r_metas[44]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_45 = alloc_way_r_metas[45]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_46 = alloc_way_r_metas[46]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_47 = alloc_way_r_metas[47]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_48 = alloc_way_r_metas[48]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_49 = alloc_way_r_metas[49]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_50 = alloc_way_r_metas[50]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_51 = alloc_way_r_metas[51]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_52 = alloc_way_r_metas[52]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_53 = alloc_way_r_metas[53]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_54 = alloc_way_r_metas[54]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_55 = alloc_way_r_metas[55]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_56 = alloc_way_r_metas[56]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_57 = alloc_way_r_metas[57]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_58 = alloc_way_r_metas[58]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_59 = alloc_way_r_metas[59]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_60 = alloc_way_r_metas[60]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_61 = alloc_way_r_metas[61]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_62 = alloc_way_r_metas[62]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_63 = alloc_way_r_metas[63]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_64 = alloc_way_r_metas[64]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_65 = alloc_way_r_metas[65]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_66 = alloc_way_r_metas[66]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_67 = alloc_way_r_metas[67]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_68 = alloc_way_r_metas[68]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_69 = alloc_way_r_metas[69]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_70 = alloc_way_r_metas[70]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_71 = alloc_way_r_metas[71]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_72 = alloc_way_r_metas[72]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_73 = alloc_way_r_metas[73]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_74 = alloc_way_r_metas[74]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_75 = alloc_way_r_metas[75]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_76 = alloc_way_r_metas[76]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_77 = alloc_way_r_metas[77]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_78 = alloc_way_r_metas[78]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_79 = alloc_way_r_metas[79]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_80 = alloc_way_r_metas[80]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_81 = alloc_way_r_metas[81]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_82 = alloc_way_r_metas[82]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_83 = alloc_way_r_metas[83]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_84 = alloc_way_r_metas[84]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_85 = alloc_way_r_metas[85]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_86 = alloc_way_r_metas[86]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_87 = alloc_way_r_metas[87]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_88 = alloc_way_r_metas[88]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_89 = alloc_way_r_metas[89]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_90 = alloc_way_r_metas[90]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_91 = alloc_way_r_metas[91]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_92 = alloc_way_r_metas[92]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_93 = alloc_way_r_metas[93]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_94 = alloc_way_r_metas[94]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_95 = alloc_way_r_metas[95]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_96 = alloc_way_r_metas[96]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_97 = alloc_way_r_metas[97]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_98 = alloc_way_r_metas[98]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_99 = alloc_way_r_metas[99]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_100 = alloc_way_r_metas[100]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_101 = alloc_way_r_metas[101]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_102 = alloc_way_r_metas[102]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_103 = alloc_way_r_metas[103]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_104 = alloc_way_r_metas[104]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_105 = alloc_way_r_metas[105]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_106 = alloc_way_r_metas[106]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_107 = alloc_way_r_metas[107]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_108 = alloc_way_r_metas[108]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_109 = alloc_way_r_metas[109]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_110 = alloc_way_r_metas[110]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_111 = alloc_way_r_metas[111]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_112 = alloc_way_r_metas[112]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_113 = alloc_way_r_metas[113]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_114 = alloc_way_r_metas[114]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_115 = alloc_way_r_metas[115]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_116 = alloc_way_r_metas[116]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_117 = alloc_way_r_metas[117]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_118 = alloc_way_r_metas[118]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_119 = alloc_way_r_metas[119]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_120 = alloc_way_r_metas[120]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_121 = alloc_way_r_metas[121]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_122 = alloc_way_r_metas[122]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_123 = alloc_way_r_metas[123]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_124 = alloc_way_r_metas[124]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_125 = alloc_way_r_metas[125]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_126 = alloc_way_r_metas[126]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_127 = alloc_way_r_metas[127]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_128 = alloc_way_r_metas[128]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_129 = alloc_way_r_metas[129]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_130 = alloc_way_r_metas[130]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_131 = alloc_way_r_metas[131]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_132 = alloc_way_r_metas[132]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_133 = alloc_way_r_metas[133]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_134 = alloc_way_r_metas[134]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_135 = alloc_way_r_metas[135]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_136 = alloc_way_r_metas[136]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_137 = alloc_way_r_metas[137]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_138 = alloc_way_r_metas[138]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_139 = alloc_way_r_metas[139]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_140 = alloc_way_r_metas[140]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_141 = alloc_way_r_metas[141]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_142 = alloc_way_r_metas[142]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_143 = alloc_way_r_metas[143]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_144 = alloc_way_r_metas[144]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_145 = alloc_way_r_metas[145]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_146 = alloc_way_r_metas[146]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_147 = alloc_way_r_metas[147]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_148 = alloc_way_r_metas[148]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_149 = alloc_way_r_metas[149]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_150 = alloc_way_r_metas[150]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_151 = alloc_way_r_metas[151]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_152 = alloc_way_r_metas[152]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_153 = alloc_way_r_metas[153]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_154 = alloc_way_r_metas[154]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_155 = alloc_way_r_metas[155]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_156 = alloc_way_r_metas[156]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_157 = alloc_way_r_metas[157]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_158 = alloc_way_r_metas[158]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_159 = alloc_way_r_metas[159]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_160 = alloc_way_r_metas[160]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_161 = alloc_way_r_metas[161]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_162 = alloc_way_r_metas[162]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_163 = alloc_way_r_metas[163]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_164 = alloc_way_r_metas[164]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_165 = alloc_way_r_metas[165]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_166 = alloc_way_r_metas[166]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_167 = alloc_way_r_metas[167]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_168 = alloc_way_r_metas[168]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_169 = alloc_way_r_metas[169]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_170 = alloc_way_r_metas[170]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_171 = alloc_way_r_metas[171]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_172 = alloc_way_r_metas[172]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_173 = alloc_way_r_metas[173]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_174 = alloc_way_r_metas[174]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_175 = alloc_way_r_metas[175]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_176 = alloc_way_r_metas[176]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_177 = alloc_way_r_metas[177]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_178 = alloc_way_r_metas[178]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_179 = alloc_way_r_metas[179]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_180 = alloc_way_r_metas[180]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_181 = alloc_way_r_metas[181]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_182 = alloc_way_r_metas[182]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_183 = alloc_way_r_metas[183]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_184 = alloc_way_r_metas[184]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_185 = alloc_way_r_metas[185]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_186 = alloc_way_r_metas[186]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_187 = alloc_way_r_metas[187]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_188 = alloc_way_r_metas[188]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_189 = alloc_way_r_metas[189]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_190 = alloc_way_r_metas[190]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_191 = alloc_way_r_metas[191]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_192 = alloc_way_r_metas[192]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_193 = alloc_way_r_metas[193]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_194 = alloc_way_r_metas[194]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_195 = alloc_way_r_metas[195]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_196 = alloc_way_r_metas[196]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_197 = alloc_way_r_metas[197]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_198 = alloc_way_r_metas[198]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_199 = alloc_way_r_metas[199]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_200 = alloc_way_r_metas[200]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_201 = alloc_way_r_metas[201]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_202 = alloc_way_r_metas[202]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_203 = alloc_way_r_metas[203]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_204 = alloc_way_r_metas[204]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_205 = alloc_way_r_metas[205]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_206 = alloc_way_r_metas[206]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_207 = alloc_way_r_metas[207]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_208 = alloc_way_r_metas[208]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_209 = alloc_way_r_metas[209]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_210 = alloc_way_r_metas[210]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_211 = alloc_way_r_metas[211]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_212 = alloc_way_r_metas[212]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_213 = alloc_way_r_metas[213]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_214 = alloc_way_r_metas[214]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_215 = alloc_way_r_metas[215]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_216 = alloc_way_r_metas[216]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_217 = alloc_way_r_metas[217]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_218 = alloc_way_r_metas[218]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_219 = alloc_way_r_metas[219]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_220 = alloc_way_r_metas[220]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_221 = alloc_way_r_metas[221]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_222 = alloc_way_r_metas[222]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_223 = alloc_way_r_metas[223]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_224 = alloc_way_r_metas[224]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_225 = alloc_way_r_metas[225]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_226 = alloc_way_r_metas[226]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_227 = alloc_way_r_metas[227]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_228 = alloc_way_r_metas[228]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_229 = alloc_way_r_metas[229]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_230 = alloc_way_r_metas[230]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_231 = alloc_way_r_metas[231]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_232 = alloc_way_r_metas[232]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_233 = alloc_way_r_metas[233]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_234 = alloc_way_r_metas[234]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_235 = alloc_way_r_metas[235]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_236 = alloc_way_r_metas[236]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_237 = alloc_way_r_metas[237]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_238 = alloc_way_r_metas[238]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_239 = alloc_way_r_metas[239]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_240 = alloc_way_r_metas[240]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_241 = alloc_way_r_metas[241]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_242 = alloc_way_r_metas[242]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_243 = alloc_way_r_metas[243]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_244 = alloc_way_r_metas[244]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_245 = alloc_way_r_metas[245]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_246 = alloc_way_r_metas[246]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_247 = alloc_way_r_metas[247]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_248 = alloc_way_r_metas[248]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_249 = alloc_way_r_metas[249]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_250 = alloc_way_r_metas[250]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_251 = alloc_way_r_metas[251]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_252 = alloc_way_r_metas[252]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_253 = alloc_way_r_metas[253]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_254 = alloc_way_r_metas[254]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_255 = alloc_way_r_metas[255]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_256 = alloc_way_r_metas[256]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_257 = alloc_way_r_metas[257]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_258 = alloc_way_r_metas[258]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_259 = alloc_way_r_metas[259]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_260 = alloc_way_r_metas[260]; // @[btb.scala:123:22, :127:14]
wire _alloc_way_T = alloc_way_chunks_0 ^ alloc_way_chunks_1; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_1 = _alloc_way_T ^ alloc_way_chunks_2; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_2 = _alloc_way_T_1 ^ alloc_way_chunks_3; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_3 = _alloc_way_T_2 ^ alloc_way_chunks_4; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_4 = _alloc_way_T_3 ^ alloc_way_chunks_5; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_5 = _alloc_way_T_4 ^ alloc_way_chunks_6; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_6 = _alloc_way_T_5 ^ alloc_way_chunks_7; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_7 = _alloc_way_T_6 ^ alloc_way_chunks_8; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_8 = _alloc_way_T_7 ^ alloc_way_chunks_9; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_9 = _alloc_way_T_8 ^ alloc_way_chunks_10; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_10 = _alloc_way_T_9 ^ alloc_way_chunks_11; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_11 = _alloc_way_T_10 ^ alloc_way_chunks_12; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_12 = _alloc_way_T_11 ^ alloc_way_chunks_13; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_13 = _alloc_way_T_12 ^ alloc_way_chunks_14; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_14 = _alloc_way_T_13 ^ alloc_way_chunks_15; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_15 = _alloc_way_T_14 ^ alloc_way_chunks_16; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_16 = _alloc_way_T_15 ^ alloc_way_chunks_17; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_17 = _alloc_way_T_16 ^ alloc_way_chunks_18; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_18 = _alloc_way_T_17 ^ alloc_way_chunks_19; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_19 = _alloc_way_T_18 ^ alloc_way_chunks_20; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_20 = _alloc_way_T_19 ^ alloc_way_chunks_21; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_21 = _alloc_way_T_20 ^ alloc_way_chunks_22; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_22 = _alloc_way_T_21 ^ alloc_way_chunks_23; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_23 = _alloc_way_T_22 ^ alloc_way_chunks_24; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_24 = _alloc_way_T_23 ^ alloc_way_chunks_25; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_25 = _alloc_way_T_24 ^ alloc_way_chunks_26; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_26 = _alloc_way_T_25 ^ alloc_way_chunks_27; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_27 = _alloc_way_T_26 ^ alloc_way_chunks_28; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_28 = _alloc_way_T_27 ^ alloc_way_chunks_29; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_29 = _alloc_way_T_28 ^ alloc_way_chunks_30; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_30 = _alloc_way_T_29 ^ alloc_way_chunks_31; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_31 = _alloc_way_T_30 ^ alloc_way_chunks_32; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_32 = _alloc_way_T_31 ^ alloc_way_chunks_33; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_33 = _alloc_way_T_32 ^ alloc_way_chunks_34; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_34 = _alloc_way_T_33 ^ alloc_way_chunks_35; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_35 = _alloc_way_T_34 ^ alloc_way_chunks_36; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_36 = _alloc_way_T_35 ^ alloc_way_chunks_37; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_37 = _alloc_way_T_36 ^ alloc_way_chunks_38; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_38 = _alloc_way_T_37 ^ alloc_way_chunks_39; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_39 = _alloc_way_T_38 ^ alloc_way_chunks_40; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_40 = _alloc_way_T_39 ^ alloc_way_chunks_41; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_41 = _alloc_way_T_40 ^ alloc_way_chunks_42; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_42 = _alloc_way_T_41 ^ alloc_way_chunks_43; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_43 = _alloc_way_T_42 ^ alloc_way_chunks_44; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_44 = _alloc_way_T_43 ^ alloc_way_chunks_45; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_45 = _alloc_way_T_44 ^ alloc_way_chunks_46; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_46 = _alloc_way_T_45 ^ alloc_way_chunks_47; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_47 = _alloc_way_T_46 ^ alloc_way_chunks_48; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_48 = _alloc_way_T_47 ^ alloc_way_chunks_49; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_49 = _alloc_way_T_48 ^ alloc_way_chunks_50; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_50 = _alloc_way_T_49 ^ alloc_way_chunks_51; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_51 = _alloc_way_T_50 ^ alloc_way_chunks_52; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_52 = _alloc_way_T_51 ^ alloc_way_chunks_53; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_53 = _alloc_way_T_52 ^ alloc_way_chunks_54; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_54 = _alloc_way_T_53 ^ alloc_way_chunks_55; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_55 = _alloc_way_T_54 ^ alloc_way_chunks_56; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_56 = _alloc_way_T_55 ^ alloc_way_chunks_57; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_57 = _alloc_way_T_56 ^ alloc_way_chunks_58; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_58 = _alloc_way_T_57 ^ alloc_way_chunks_59; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_59 = _alloc_way_T_58 ^ alloc_way_chunks_60; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_60 = _alloc_way_T_59 ^ alloc_way_chunks_61; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_61 = _alloc_way_T_60 ^ alloc_way_chunks_62; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_62 = _alloc_way_T_61 ^ alloc_way_chunks_63; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_63 = _alloc_way_T_62 ^ alloc_way_chunks_64; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_64 = _alloc_way_T_63 ^ alloc_way_chunks_65; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_65 = _alloc_way_T_64 ^ alloc_way_chunks_66; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_66 = _alloc_way_T_65 ^ alloc_way_chunks_67; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_67 = _alloc_way_T_66 ^ alloc_way_chunks_68; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_68 = _alloc_way_T_67 ^ alloc_way_chunks_69; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_69 = _alloc_way_T_68 ^ alloc_way_chunks_70; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_70 = _alloc_way_T_69 ^ alloc_way_chunks_71; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_71 = _alloc_way_T_70 ^ alloc_way_chunks_72; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_72 = _alloc_way_T_71 ^ alloc_way_chunks_73; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_73 = _alloc_way_T_72 ^ alloc_way_chunks_74; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_74 = _alloc_way_T_73 ^ alloc_way_chunks_75; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_75 = _alloc_way_T_74 ^ alloc_way_chunks_76; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_76 = _alloc_way_T_75 ^ alloc_way_chunks_77; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_77 = _alloc_way_T_76 ^ alloc_way_chunks_78; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_78 = _alloc_way_T_77 ^ alloc_way_chunks_79; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_79 = _alloc_way_T_78 ^ alloc_way_chunks_80; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_80 = _alloc_way_T_79 ^ alloc_way_chunks_81; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_81 = _alloc_way_T_80 ^ alloc_way_chunks_82; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_82 = _alloc_way_T_81 ^ alloc_way_chunks_83; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_83 = _alloc_way_T_82 ^ alloc_way_chunks_84; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_84 = _alloc_way_T_83 ^ alloc_way_chunks_85; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_85 = _alloc_way_T_84 ^ alloc_way_chunks_86; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_86 = _alloc_way_T_85 ^ alloc_way_chunks_87; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_87 = _alloc_way_T_86 ^ alloc_way_chunks_88; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_88 = _alloc_way_T_87 ^ alloc_way_chunks_89; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_89 = _alloc_way_T_88 ^ alloc_way_chunks_90; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_90 = _alloc_way_T_89 ^ alloc_way_chunks_91; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_91 = _alloc_way_T_90 ^ alloc_way_chunks_92; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_92 = _alloc_way_T_91 ^ alloc_way_chunks_93; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_93 = _alloc_way_T_92 ^ alloc_way_chunks_94; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_94 = _alloc_way_T_93 ^ alloc_way_chunks_95; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_95 = _alloc_way_T_94 ^ alloc_way_chunks_96; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_96 = _alloc_way_T_95 ^ alloc_way_chunks_97; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_97 = _alloc_way_T_96 ^ alloc_way_chunks_98; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_98 = _alloc_way_T_97 ^ alloc_way_chunks_99; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_99 = _alloc_way_T_98 ^ alloc_way_chunks_100; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_100 = _alloc_way_T_99 ^ alloc_way_chunks_101; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_101 = _alloc_way_T_100 ^ alloc_way_chunks_102; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_102 = _alloc_way_T_101 ^ alloc_way_chunks_103; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_103 = _alloc_way_T_102 ^ alloc_way_chunks_104; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_104 = _alloc_way_T_103 ^ alloc_way_chunks_105; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_105 = _alloc_way_T_104 ^ alloc_way_chunks_106; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_106 = _alloc_way_T_105 ^ alloc_way_chunks_107; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_107 = _alloc_way_T_106 ^ alloc_way_chunks_108; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_108 = _alloc_way_T_107 ^ alloc_way_chunks_109; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_109 = _alloc_way_T_108 ^ alloc_way_chunks_110; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_110 = _alloc_way_T_109 ^ alloc_way_chunks_111; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_111 = _alloc_way_T_110 ^ alloc_way_chunks_112; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_112 = _alloc_way_T_111 ^ alloc_way_chunks_113; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_113 = _alloc_way_T_112 ^ alloc_way_chunks_114; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_114 = _alloc_way_T_113 ^ alloc_way_chunks_115; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_115 = _alloc_way_T_114 ^ alloc_way_chunks_116; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_116 = _alloc_way_T_115 ^ alloc_way_chunks_117; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_117 = _alloc_way_T_116 ^ alloc_way_chunks_118; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_118 = _alloc_way_T_117 ^ alloc_way_chunks_119; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_119 = _alloc_way_T_118 ^ alloc_way_chunks_120; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_120 = _alloc_way_T_119 ^ alloc_way_chunks_121; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_121 = _alloc_way_T_120 ^ alloc_way_chunks_122; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_122 = _alloc_way_T_121 ^ alloc_way_chunks_123; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_123 = _alloc_way_T_122 ^ alloc_way_chunks_124; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_124 = _alloc_way_T_123 ^ alloc_way_chunks_125; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_125 = _alloc_way_T_124 ^ alloc_way_chunks_126; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_126 = _alloc_way_T_125 ^ alloc_way_chunks_127; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_127 = _alloc_way_T_126 ^ alloc_way_chunks_128; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_128 = _alloc_way_T_127 ^ alloc_way_chunks_129; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_129 = _alloc_way_T_128 ^ alloc_way_chunks_130; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_130 = _alloc_way_T_129 ^ alloc_way_chunks_131; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_131 = _alloc_way_T_130 ^ alloc_way_chunks_132; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_132 = _alloc_way_T_131 ^ alloc_way_chunks_133; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_133 = _alloc_way_T_132 ^ alloc_way_chunks_134; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_134 = _alloc_way_T_133 ^ alloc_way_chunks_135; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_135 = _alloc_way_T_134 ^ alloc_way_chunks_136; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_136 = _alloc_way_T_135 ^ alloc_way_chunks_137; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_137 = _alloc_way_T_136 ^ alloc_way_chunks_138; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_138 = _alloc_way_T_137 ^ alloc_way_chunks_139; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_139 = _alloc_way_T_138 ^ alloc_way_chunks_140; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_140 = _alloc_way_T_139 ^ alloc_way_chunks_141; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_141 = _alloc_way_T_140 ^ alloc_way_chunks_142; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_142 = _alloc_way_T_141 ^ alloc_way_chunks_143; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_143 = _alloc_way_T_142 ^ alloc_way_chunks_144; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_144 = _alloc_way_T_143 ^ alloc_way_chunks_145; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_145 = _alloc_way_T_144 ^ alloc_way_chunks_146; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_146 = _alloc_way_T_145 ^ alloc_way_chunks_147; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_147 = _alloc_way_T_146 ^ alloc_way_chunks_148; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_148 = _alloc_way_T_147 ^ alloc_way_chunks_149; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_149 = _alloc_way_T_148 ^ alloc_way_chunks_150; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_150 = _alloc_way_T_149 ^ alloc_way_chunks_151; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_151 = _alloc_way_T_150 ^ alloc_way_chunks_152; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_152 = _alloc_way_T_151 ^ alloc_way_chunks_153; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_153 = _alloc_way_T_152 ^ alloc_way_chunks_154; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_154 = _alloc_way_T_153 ^ alloc_way_chunks_155; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_155 = _alloc_way_T_154 ^ alloc_way_chunks_156; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_156 = _alloc_way_T_155 ^ alloc_way_chunks_157; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_157 = _alloc_way_T_156 ^ alloc_way_chunks_158; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_158 = _alloc_way_T_157 ^ alloc_way_chunks_159; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_159 = _alloc_way_T_158 ^ alloc_way_chunks_160; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_160 = _alloc_way_T_159 ^ alloc_way_chunks_161; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_161 = _alloc_way_T_160 ^ alloc_way_chunks_162; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_162 = _alloc_way_T_161 ^ alloc_way_chunks_163; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_163 = _alloc_way_T_162 ^ alloc_way_chunks_164; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_164 = _alloc_way_T_163 ^ alloc_way_chunks_165; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_165 = _alloc_way_T_164 ^ alloc_way_chunks_166; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_166 = _alloc_way_T_165 ^ alloc_way_chunks_167; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_167 = _alloc_way_T_166 ^ alloc_way_chunks_168; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_168 = _alloc_way_T_167 ^ alloc_way_chunks_169; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_169 = _alloc_way_T_168 ^ alloc_way_chunks_170; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_170 = _alloc_way_T_169 ^ alloc_way_chunks_171; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_171 = _alloc_way_T_170 ^ alloc_way_chunks_172; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_172 = _alloc_way_T_171 ^ alloc_way_chunks_173; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_173 = _alloc_way_T_172 ^ alloc_way_chunks_174; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_174 = _alloc_way_T_173 ^ alloc_way_chunks_175; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_175 = _alloc_way_T_174 ^ alloc_way_chunks_176; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_176 = _alloc_way_T_175 ^ alloc_way_chunks_177; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_177 = _alloc_way_T_176 ^ alloc_way_chunks_178; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_178 = _alloc_way_T_177 ^ alloc_way_chunks_179; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_179 = _alloc_way_T_178 ^ alloc_way_chunks_180; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_180 = _alloc_way_T_179 ^ alloc_way_chunks_181; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_181 = _alloc_way_T_180 ^ alloc_way_chunks_182; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_182 = _alloc_way_T_181 ^ alloc_way_chunks_183; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_183 = _alloc_way_T_182 ^ alloc_way_chunks_184; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_184 = _alloc_way_T_183 ^ alloc_way_chunks_185; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_185 = _alloc_way_T_184 ^ alloc_way_chunks_186; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_186 = _alloc_way_T_185 ^ alloc_way_chunks_187; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_187 = _alloc_way_T_186 ^ alloc_way_chunks_188; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_188 = _alloc_way_T_187 ^ alloc_way_chunks_189; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_189 = _alloc_way_T_188 ^ alloc_way_chunks_190; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_190 = _alloc_way_T_189 ^ alloc_way_chunks_191; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_191 = _alloc_way_T_190 ^ alloc_way_chunks_192; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_192 = _alloc_way_T_191 ^ alloc_way_chunks_193; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_193 = _alloc_way_T_192 ^ alloc_way_chunks_194; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_194 = _alloc_way_T_193 ^ alloc_way_chunks_195; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_195 = _alloc_way_T_194 ^ alloc_way_chunks_196; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_196 = _alloc_way_T_195 ^ alloc_way_chunks_197; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_197 = _alloc_way_T_196 ^ alloc_way_chunks_198; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_198 = _alloc_way_T_197 ^ alloc_way_chunks_199; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_199 = _alloc_way_T_198 ^ alloc_way_chunks_200; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_200 = _alloc_way_T_199 ^ alloc_way_chunks_201; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_201 = _alloc_way_T_200 ^ alloc_way_chunks_202; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_202 = _alloc_way_T_201 ^ alloc_way_chunks_203; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_203 = _alloc_way_T_202 ^ alloc_way_chunks_204; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_204 = _alloc_way_T_203 ^ alloc_way_chunks_205; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_205 = _alloc_way_T_204 ^ alloc_way_chunks_206; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_206 = _alloc_way_T_205 ^ alloc_way_chunks_207; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_207 = _alloc_way_T_206 ^ alloc_way_chunks_208; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_208 = _alloc_way_T_207 ^ alloc_way_chunks_209; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_209 = _alloc_way_T_208 ^ alloc_way_chunks_210; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_210 = _alloc_way_T_209 ^ alloc_way_chunks_211; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_211 = _alloc_way_T_210 ^ alloc_way_chunks_212; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_212 = _alloc_way_T_211 ^ alloc_way_chunks_213; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_213 = _alloc_way_T_212 ^ alloc_way_chunks_214; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_214 = _alloc_way_T_213 ^ alloc_way_chunks_215; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_215 = _alloc_way_T_214 ^ alloc_way_chunks_216; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_216 = _alloc_way_T_215 ^ alloc_way_chunks_217; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_217 = _alloc_way_T_216 ^ alloc_way_chunks_218; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_218 = _alloc_way_T_217 ^ alloc_way_chunks_219; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_219 = _alloc_way_T_218 ^ alloc_way_chunks_220; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_220 = _alloc_way_T_219 ^ alloc_way_chunks_221; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_221 = _alloc_way_T_220 ^ alloc_way_chunks_222; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_222 = _alloc_way_T_221 ^ alloc_way_chunks_223; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_223 = _alloc_way_T_222 ^ alloc_way_chunks_224; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_224 = _alloc_way_T_223 ^ alloc_way_chunks_225; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_225 = _alloc_way_T_224 ^ alloc_way_chunks_226; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_226 = _alloc_way_T_225 ^ alloc_way_chunks_227; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_227 = _alloc_way_T_226 ^ alloc_way_chunks_228; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_228 = _alloc_way_T_227 ^ alloc_way_chunks_229; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_229 = _alloc_way_T_228 ^ alloc_way_chunks_230; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_230 = _alloc_way_T_229 ^ alloc_way_chunks_231; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_231 = _alloc_way_T_230 ^ alloc_way_chunks_232; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_232 = _alloc_way_T_231 ^ alloc_way_chunks_233; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_233 = _alloc_way_T_232 ^ alloc_way_chunks_234; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_234 = _alloc_way_T_233 ^ alloc_way_chunks_235; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_235 = _alloc_way_T_234 ^ alloc_way_chunks_236; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_236 = _alloc_way_T_235 ^ alloc_way_chunks_237; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_237 = _alloc_way_T_236 ^ alloc_way_chunks_238; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_238 = _alloc_way_T_237 ^ alloc_way_chunks_239; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_239 = _alloc_way_T_238 ^ alloc_way_chunks_240; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_240 = _alloc_way_T_239 ^ alloc_way_chunks_241; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_241 = _alloc_way_T_240 ^ alloc_way_chunks_242; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_242 = _alloc_way_T_241 ^ alloc_way_chunks_243; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_243 = _alloc_way_T_242 ^ alloc_way_chunks_244; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_244 = _alloc_way_T_243 ^ alloc_way_chunks_245; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_245 = _alloc_way_T_244 ^ alloc_way_chunks_246; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_246 = _alloc_way_T_245 ^ alloc_way_chunks_247; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_247 = _alloc_way_T_246 ^ alloc_way_chunks_248; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_248 = _alloc_way_T_247 ^ alloc_way_chunks_249; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_249 = _alloc_way_T_248 ^ alloc_way_chunks_250; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_250 = _alloc_way_T_249 ^ alloc_way_chunks_251; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_251 = _alloc_way_T_250 ^ alloc_way_chunks_252; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_252 = _alloc_way_T_251 ^ alloc_way_chunks_253; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_253 = _alloc_way_T_252 ^ alloc_way_chunks_254; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_254 = _alloc_way_T_253 ^ alloc_way_chunks_255; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_255 = _alloc_way_T_254 ^ alloc_way_chunks_256; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_256 = _alloc_way_T_255 ^ alloc_way_chunks_257; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_257 = _alloc_way_T_256 ^ alloc_way_chunks_258; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_258 = _alloc_way_T_257 ^ alloc_way_chunks_259; // @[btb.scala:127:14, :129:20]
wire alloc_way = _alloc_way_T_258 ^ alloc_way_chunks_260; // @[btb.scala:127:14, :129:20]
wire _s1_meta_write_way_T = s1_hits_0 | s1_hits_1; // @[btb.scala:87:55, :133:44]
wire _s1_meta_write_way_T_1 = _s1_meta_write_way_T | s1_hits_2; // @[btb.scala:87:55, :133:44]
wire _s1_meta_write_way_T_2 = _s1_meta_write_way_T_1 | s1_hits_3; // @[btb.scala:87:55, :133:44]
wire [1:0] _s1_meta_write_way_T_3 = {s1_hit_ohs_0_1, s1_hit_ohs_0_0}; // @[btb.scala:82:27, :134:38]
wire [1:0] _s1_meta_write_way_T_4 = {s1_hit_ohs_1_1, s1_hit_ohs_1_0}; // @[btb.scala:82:27, :134:38]
wire [1:0] _s1_meta_write_way_T_5 = {s1_hit_ohs_2_1, s1_hit_ohs_2_0}; // @[btb.scala:82:27, :134:38]
wire [1:0] _s1_meta_write_way_T_6 = {s1_hit_ohs_3_1, s1_hit_ohs_3_0}; // @[btb.scala:82:27, :134:38]
wire [1:0] _s1_meta_write_way_T_7 = _s1_meta_write_way_T_3 | _s1_meta_write_way_T_4; // @[btb.scala:134:{38,54}]
wire [1:0] _s1_meta_write_way_T_8 = _s1_meta_write_way_T_7 | _s1_meta_write_way_T_5; // @[btb.scala:134:{38,54}]
wire [1:0] _s1_meta_write_way_T_9 = _s1_meta_write_way_T_8 | _s1_meta_write_way_T_6; // @[btb.scala:134:{38,54}]
wire _s1_meta_write_way_T_10 = _s1_meta_write_way_T_9[0]; // @[OneHot.scala:48:45]
wire _s1_meta_write_way_T_11 = _s1_meta_write_way_T_9[1]; // @[OneHot.scala:48:45]
wire _s1_meta_write_way_T_12 = ~_s1_meta_write_way_T_10; // @[OneHot.scala:48:45]
assign _s1_meta_write_way_T_13 = _s1_meta_write_way_T_2 ? _s1_meta_write_way_T_12 : alloc_way; // @[Mux.scala:50:70]
assign s1_meta_write_way = _s1_meta_write_way_T_13; // @[btb.scala:52:21, :133:27]
wire _s1_update_meta_T; // @[btb.scala:138:55]
wire s1_update_meta_write_way; // @[btb.scala:138:55]
assign _s1_update_meta_T = _s1_update_meta_WIRE; // @[btb.scala:138:55]
assign _s1_update_meta_WIRE = s1_update_bits_meta[0]; // @[predictor.scala:184:30]
assign s1_update_meta_write_way = _s1_update_meta_T; // @[btb.scala:138:55]
wire [2:0] _new_offset_value_T_1 = {s1_update_bits_cfi_idx_bits, 1'h0}; // @[predictor.scala:184:30]
wire [40:0] _new_offset_value_T_2 = {1'h0, s1_update_bits_pc} + {38'h0, _new_offset_value_T_1}; // @[predictor.scala:184:30]
wire [39:0] _new_offset_value_T_3 = _new_offset_value_T_2[39:0]; // @[btb.scala:143:24]
wire [39:0] _new_offset_value_T_4 = _new_offset_value_T_3; // @[btb.scala:143:{24,62}]
wire [40:0] _new_offset_value_T_5 = {_new_offset_value_T[39], _new_offset_value_T} - {_new_offset_value_T_4[39], _new_offset_value_T_4}; // @[btb.scala:142:{49,56}, :143:62]
wire [39:0] _new_offset_value_T_6 = _new_offset_value_T_5[39:0]; // @[btb.scala:142:56]
wire [39:0] new_offset_value = _new_offset_value_T_6; // @[btb.scala:142:56]
wire _offset_is_extended_T = $signed(new_offset_value) > 40'shFFF; // @[btb.scala:142:56, :144:46]
wire _offset_is_extended_T_1 = $signed(new_offset_value) < -40'sh1000; // @[btb.scala:142:56, :145:46]
wire offset_is_extended = _offset_is_extended_T | _offset_is_extended_T_1; // @[btb.scala:144:{46,65}, :145:46]
wire s1_update_wbtb_data_extended = offset_is_extended; // @[btb.scala:144:65, :148:34]
wire [12:0] s1_update_wbtb_data_offset; // @[btb.scala:148:34]
assign s1_update_wbtb_data_offset = new_offset_value[12:0]; // @[btb.scala:142:56, :148:34, :150:32]
wire [3:0] _s1_update_wbtb_mask_T = 4'h1 << s1_update_bits_cfi_idx_bits; // @[OneHot.scala:58:35]
wire _s1_update_wbtb_mask_T_1 = s1_update_bits_cfi_idx_valid & s1_update_valid; // @[predictor.scala:184:30]
wire _s1_update_wbtb_mask_T_2 = _s1_update_wbtb_mask_T_1 & s1_update_bits_cfi_taken; // @[predictor.scala:184:30]
wire _GEN_7 = s1_update_bits_is_mispredict_update | s1_update_bits_is_repair_update; // @[predictor.scala:96:49, :184:30]
wire _s1_update_wbtb_mask_T_3; // @[predictor.scala:96:49]
assign _s1_update_wbtb_mask_T_3 = _GEN_7; // @[predictor.scala:96:49]
wire _s1_update_wmeta_mask_T_1; // @[predictor.scala:96:49]
assign _s1_update_wmeta_mask_T_1 = _GEN_7; // @[predictor.scala:96:49]
wire _s1_update_wbtb_mask_T_4 = |s1_update_bits_btb_mispredicts; // @[predictor.scala:94:50, :184:30]
wire _s1_update_wbtb_mask_T_5 = _s1_update_wbtb_mask_T_3 | _s1_update_wbtb_mask_T_4; // @[predictor.scala:94:50, :96:{49,69}]
wire _s1_update_wbtb_mask_T_6 = ~_s1_update_wbtb_mask_T_5; // @[predictor.scala:96:{26,69}]
wire _s1_update_wbtb_mask_T_7 = _s1_update_wbtb_mask_T_2 & _s1_update_wbtb_mask_T_6; // @[predictor.scala:96:26]
wire [3:0] _s1_update_wbtb_mask_T_8 = {4{_s1_update_wbtb_mask_T_7}}; // @[btb.scala:152:{9,97}]
wire [3:0] s1_update_wbtb_mask = _s1_update_wbtb_mask_T & _s1_update_wbtb_mask_T_8; // @[OneHot.scala:58:35]
wire [3:0] _s1_update_wmeta_mask_T = s1_update_wbtb_mask | s1_update_bits_br_mask; // @[predictor.scala:184:30]
wire _s1_update_wmeta_mask_T_2 = |s1_update_bits_btb_mispredicts; // @[predictor.scala:94:50, :184:30]
wire _s1_update_wmeta_mask_T_3 = _s1_update_wmeta_mask_T_1 | _s1_update_wmeta_mask_T_2; // @[predictor.scala:94:50, :96:{49,69}]
wire _s1_update_wmeta_mask_T_4 = ~_s1_update_wmeta_mask_T_3; // @[predictor.scala:96:{26,69}]
wire _s1_update_wmeta_mask_T_5 = s1_update_valid & _s1_update_wmeta_mask_T_4; // @[predictor.scala:96:26, :184:30]
wire [3:0] _s1_update_wmeta_mask_T_6 = {4{_s1_update_wmeta_mask_T_5}}; // @[btb.scala:155:{10,38}]
wire [3:0] _s1_update_wmeta_mask_T_7 = {4{s1_update_valid}}; // @[predictor.scala:184:30]
wire [3:0] _s1_update_wmeta_mask_T_8 = _s1_update_wmeta_mask_T_7 & s1_update_bits_btb_mispredicts; // @[predictor.scala:184:30]
wire [3:0] _s1_update_wmeta_mask_T_9 = _s1_update_wmeta_mask_T_6 | _s1_update_wmeta_mask_T_8; // @[btb.scala:155:{10,74}, :156:40]
wire [3:0] s1_update_wmeta_mask = _s1_update_wmeta_mask_T & _s1_update_wmeta_mask_T_9; // @[btb.scala:154:{52,78}, :155:74]
wire _s1_update_wmeta_data_0_is_br_T; // @[btb.scala:163:62]
wire [28:0] _s1_update_wmeta_data_0_tag_T_2; // @[btb.scala:162:43]
wire _s1_update_wmeta_data_1_is_br_T; // @[btb.scala:163:62]
wire [28:0] _s1_update_wmeta_data_1_tag_T_2; // @[btb.scala:162:43]
wire _s1_update_wmeta_data_2_is_br_T; // @[btb.scala:163:62]
wire [28:0] _s1_update_wmeta_data_2_tag_T_2; // @[btb.scala:162:43]
wire _s1_update_wmeta_data_3_is_br_T; // @[btb.scala:163:62]
wire [28:0] _s1_update_wmeta_data_3_tag_T_2; // @[btb.scala:162:43]
wire s1_update_wmeta_data_0_is_br; // @[btb.scala:159:34]
wire [28:0] s1_update_wmeta_data_0_tag; // @[btb.scala:159:34]
wire s1_update_wmeta_data_1_is_br; // @[btb.scala:159:34]
wire [28:0] s1_update_wmeta_data_1_tag; // @[btb.scala:159:34]
wire s1_update_wmeta_data_2_is_br; // @[btb.scala:159:34]
wire [28:0] s1_update_wmeta_data_2_tag; // @[btb.scala:159:34]
wire s1_update_wmeta_data_3_is_br; // @[btb.scala:159:34]
wire [28:0] s1_update_wmeta_data_3_tag; // @[btb.scala:159:34]
wire _s1_update_wmeta_data_0_tag_T = s1_update_bits_btb_mispredicts[0]; // @[predictor.scala:184:30]
wire [28:0] _s1_update_wmeta_data_0_tag_T_1 = s1_update_idx[35:7]; // @[predictor.scala:185:30]
wire [28:0] _s1_update_wmeta_data_1_tag_T_1 = s1_update_idx[35:7]; // @[predictor.scala:185:30]
wire [28:0] _s1_update_wmeta_data_2_tag_T_1 = s1_update_idx[35:7]; // @[predictor.scala:185:30]
wire [28:0] _s1_update_wmeta_data_3_tag_T_1 = s1_update_idx[35:7]; // @[predictor.scala:185:30]
assign _s1_update_wmeta_data_0_tag_T_2 = _s1_update_wmeta_data_0_tag_T ? 29'h0 : _s1_update_wmeta_data_0_tag_T_1; // @[btb.scala:162:{43,74,98}]
assign s1_update_wmeta_data_0_tag = _s1_update_wmeta_data_0_tag_T_2; // @[btb.scala:159:34, :162:43]
assign _s1_update_wmeta_data_0_is_br_T = s1_update_bits_br_mask[0]; // @[predictor.scala:184:30]
assign s1_update_wmeta_data_0_is_br = _s1_update_wmeta_data_0_is_br_T; // @[btb.scala:159:34, :163:62]
wire _s1_update_wmeta_data_1_tag_T = s1_update_bits_btb_mispredicts[1]; // @[predictor.scala:184:30]
assign _s1_update_wmeta_data_1_tag_T_2 = _s1_update_wmeta_data_1_tag_T ? 29'h0 : _s1_update_wmeta_data_1_tag_T_1; // @[btb.scala:162:{43,74,98}]
assign s1_update_wmeta_data_1_tag = _s1_update_wmeta_data_1_tag_T_2; // @[btb.scala:159:34, :162:43]
assign _s1_update_wmeta_data_1_is_br_T = s1_update_bits_br_mask[1]; // @[predictor.scala:184:30]
assign s1_update_wmeta_data_1_is_br = _s1_update_wmeta_data_1_is_br_T; // @[btb.scala:159:34, :163:62]
wire _s1_update_wmeta_data_2_tag_T = s1_update_bits_btb_mispredicts[2]; // @[predictor.scala:184:30]
assign _s1_update_wmeta_data_2_tag_T_2 = _s1_update_wmeta_data_2_tag_T ? 29'h0 : _s1_update_wmeta_data_2_tag_T_1; // @[btb.scala:162:{43,74,98}]
assign s1_update_wmeta_data_2_tag = _s1_update_wmeta_data_2_tag_T_2; // @[btb.scala:159:34, :162:43]
assign _s1_update_wmeta_data_2_is_br_T = s1_update_bits_br_mask[2]; // @[predictor.scala:184:30]
assign s1_update_wmeta_data_2_is_br = _s1_update_wmeta_data_2_is_br_T; // @[btb.scala:159:34, :163:62]
wire _s1_update_wmeta_data_3_tag_T = s1_update_bits_btb_mispredicts[3]; // @[predictor.scala:184:30]
assign _s1_update_wmeta_data_3_tag_T_2 = _s1_update_wmeta_data_3_tag_T ? 29'h0 : _s1_update_wmeta_data_3_tag_T_1; // @[btb.scala:162:{43,74,98}]
assign s1_update_wmeta_data_3_tag = _s1_update_wmeta_data_3_tag_T_2; // @[btb.scala:159:34, :162:43]
assign _s1_update_wmeta_data_3_is_br_T = s1_update_bits_br_mask[3]; // @[predictor.scala:184:30]
assign s1_update_wmeta_data_3_is_br = _s1_update_wmeta_data_3_is_br_T; // @[btb.scala:159:34, :163:62]
wire btb_0_MPORT_en = doing_reset | ~s1_update_meta_write_way; // @[btb.scala:60:28, :138:55, :167:{23,51}]
wire [6:0] _T_34 = doing_reset ? reset_idx : s1_update_idx[6:0]; // @[predictor.scala:185:30]
assign btb_0_MPORT_data_0 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61]
assign btb_0_MPORT_data_1 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61]
assign btb_0_MPORT_data_2 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61]
assign btb_0_MPORT_data_3 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61]
assign meta_0_MPORT_1_data_0 = doing_reset ? 30'h0 : {s1_update_wmeta_data_0_is_br, s1_update_wmeta_data_0_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46]
assign meta_0_MPORT_1_data_1 = doing_reset ? 30'h0 : {s1_update_wmeta_data_1_is_br, s1_update_wmeta_data_1_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46]
assign meta_0_MPORT_1_data_2 = doing_reset ? 30'h0 : {s1_update_wmeta_data_2_is_br, s1_update_wmeta_data_2_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46]
assign meta_0_MPORT_1_data_3 = doing_reset ? 30'h0 : {s1_update_wmeta_data_3_is_br, s1_update_wmeta_data_3_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46]
wire btb_1_MPORT_2_en = doing_reset | s1_update_meta_write_way; // @[btb.scala:60:28, :138:55, :167:23]
wire [6:0] _T_69 = doing_reset ? reset_idx : s1_update_idx[6:0]; // @[predictor.scala:185:30]
assign btb_1_MPORT_2_data_0 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61]
assign btb_1_MPORT_2_data_1 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61]
assign btb_1_MPORT_2_data_2 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61]
assign btb_1_MPORT_2_data_3 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61]
assign meta_1_MPORT_3_data_0 = doing_reset ? 30'h0 : {s1_update_wmeta_data_0_is_br, s1_update_wmeta_data_0_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46]
assign meta_1_MPORT_3_data_1 = doing_reset ? 30'h0 : {s1_update_wmeta_data_1_is_br, s1_update_wmeta_data_1_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46]
assign meta_1_MPORT_3_data_2 = doing_reset ? 30'h0 : {s1_update_wmeta_data_2_is_br, s1_update_wmeta_data_2_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46]
assign meta_1_MPORT_3_data_3 = doing_reset ? 30'h0 : {s1_update_wmeta_data_3_is_br, s1_update_wmeta_data_3_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46]
always @(posedge clock) begin // @[btb.scala:23:7]
s1_idx <= s0_idx; // @[frontend.scala:162:35]
s2_idx <= s1_idx; // @[predictor.scala:163:29, :164:29]
s3_idx <= s2_idx; // @[predictor.scala:164:29, :165:29]
s1_valid <= io_f0_valid_0; // @[predictor.scala:168:25]
s2_valid <= s1_valid; // @[predictor.scala:168:25, :169:25]
s3_valid <= s2_valid; // @[predictor.scala:169:25, :170:25]
s1_mask <= io_f0_mask_0; // @[predictor.scala:173:24]
s2_mask <= s1_mask; // @[predictor.scala:173:24, :174:24]
s3_mask <= s2_mask; // @[predictor.scala:174:24, :175:24]
s1_pc <= io_f0_pc_0; // @[predictor.scala:178:22]
s1_update_valid <= io_update_valid_0; // @[predictor.scala:184:30]
s1_update_bits_is_mispredict_update <= io_update_bits_is_mispredict_update_0; // @[predictor.scala:184:30]
s1_update_bits_is_repair_update <= io_update_bits_is_repair_update_0; // @[predictor.scala:184:30]
s1_update_bits_btb_mispredicts <= io_update_bits_btb_mispredicts_0; // @[predictor.scala:184:30]
s1_update_bits_pc <= io_update_bits_pc_0; // @[predictor.scala:184:30]
s1_update_bits_br_mask <= io_update_bits_br_mask_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_idx_valid <= io_update_bits_cfi_idx_valid_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_idx_bits <= io_update_bits_cfi_idx_bits_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_taken <= io_update_bits_cfi_taken_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_mispredicted <= io_update_bits_cfi_mispredicted_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_is_br <= io_update_bits_cfi_is_br_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_is_jal <= io_update_bits_cfi_is_jal_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_is_jalr <= io_update_bits_cfi_is_jalr_0; // @[predictor.scala:184:30]
s1_update_bits_ghist <= io_update_bits_ghist_0; // @[predictor.scala:184:30]
s1_update_bits_lhist <= io_update_bits_lhist_0; // @[predictor.scala:184:30]
s1_update_bits_target <= io_update_bits_target_0; // @[predictor.scala:184:30]
s1_update_bits_meta <= io_update_bits_meta_0; // @[predictor.scala:184:30]
s1_update_idx <= s0_update_idx; // @[frontend.scala:162:35]
s1_update_valid_0 <= io_update_valid_0; // @[predictor.scala:186:32]
f3_meta_REG_write_way <= s1_meta_write_way; // @[btb.scala:52:21, :53:32]
f3_meta_write_way <= f3_meta_REG_write_way; // @[btb.scala:53:{24,32}]
REG <= s1_hits_0; // @[btb.scala:87:55, :104:18]
io_resp_f2_0_predicted_pc_REG_valid <= s1_resp_0_valid; // @[btb.scala:78:23, :105:44]
io_resp_f2_0_predicted_pc_REG_bits <= s1_resp_0_bits; // @[btb.scala:78:23, :105:44]
io_resp_f2_0_is_br_REG <= s1_is_br_0; // @[btb.scala:79:23, :106:44]
io_resp_f2_0_is_jal_REG <= s1_is_jal_0; // @[btb.scala:80:23, :107:44]
REG_1 <= s1_is_jal_0; // @[btb.scala:80:23, :108:20]
REG_2 <= s1_hits_0; // @[btb.scala:87:55, :112:26]
REG_3 <= REG_2; // @[btb.scala:112:{18,26}]
io_resp_f3_0_predicted_pc_REG_valid <= io_resp_f2_0_predicted_pc_valid_0; // @[btb.scala:23:7, :113:44]
io_resp_f3_0_predicted_pc_REG_bits <= io_resp_f2_0_predicted_pc_bits_0; // @[btb.scala:23:7, :113:44]
io_resp_f3_0_is_br_REG <= io_resp_f2_0_is_br_0; // @[btb.scala:23:7, :114:44]
io_resp_f3_0_is_jal_REG <= io_resp_f2_0_is_jal_0; // @[btb.scala:23:7, :115:44]
REG_4 <= s1_is_jal_0; // @[btb.scala:80:23, :116:28]
REG_5 <= REG_4; // @[btb.scala:116:{20,28}]
REG_6 <= s1_hits_1; // @[btb.scala:87:55, :104:18]
io_resp_f2_1_predicted_pc_REG_valid <= s1_resp_1_valid; // @[btb.scala:78:23, :105:44]
io_resp_f2_1_predicted_pc_REG_bits <= s1_resp_1_bits; // @[btb.scala:78:23, :105:44]
io_resp_f2_1_is_br_REG <= s1_is_br_1; // @[btb.scala:79:23, :106:44]
io_resp_f2_1_is_jal_REG <= s1_is_jal_1; // @[btb.scala:80:23, :107:44]
REG_7 <= s1_is_jal_1; // @[btb.scala:80:23, :108:20]
REG_8 <= s1_hits_1; // @[btb.scala:87:55, :112:26]
REG_9 <= REG_8; // @[btb.scala:112:{18,26}]
io_resp_f3_1_predicted_pc_REG_valid <= io_resp_f2_1_predicted_pc_valid_0; // @[btb.scala:23:7, :113:44]
io_resp_f3_1_predicted_pc_REG_bits <= io_resp_f2_1_predicted_pc_bits_0; // @[btb.scala:23:7, :113:44]
io_resp_f3_1_is_br_REG <= io_resp_f2_1_is_br_0; // @[btb.scala:23:7, :114:44]
io_resp_f3_1_is_jal_REG <= io_resp_f2_1_is_jal_0; // @[btb.scala:23:7, :115:44]
REG_10 <= s1_is_jal_1; // @[btb.scala:80:23, :116:28]
REG_11 <= REG_10; // @[btb.scala:116:{20,28}]
REG_12 <= s1_hits_2; // @[btb.scala:87:55, :104:18]
io_resp_f2_2_predicted_pc_REG_valid <= s1_resp_2_valid; // @[btb.scala:78:23, :105:44]
io_resp_f2_2_predicted_pc_REG_bits <= s1_resp_2_bits; // @[btb.scala:78:23, :105:44]
io_resp_f2_2_is_br_REG <= s1_is_br_2; // @[btb.scala:79:23, :106:44]
io_resp_f2_2_is_jal_REG <= s1_is_jal_2; // @[btb.scala:80:23, :107:44]
REG_13 <= s1_is_jal_2; // @[btb.scala:80:23, :108:20]
REG_14 <= s1_hits_2; // @[btb.scala:87:55, :112:26]
REG_15 <= REG_14; // @[btb.scala:112:{18,26}]
io_resp_f3_2_predicted_pc_REG_valid <= io_resp_f2_2_predicted_pc_valid_0; // @[btb.scala:23:7, :113:44]
io_resp_f3_2_predicted_pc_REG_bits <= io_resp_f2_2_predicted_pc_bits_0; // @[btb.scala:23:7, :113:44]
io_resp_f3_2_is_br_REG <= io_resp_f2_2_is_br_0; // @[btb.scala:23:7, :114:44]
io_resp_f3_2_is_jal_REG <= io_resp_f2_2_is_jal_0; // @[btb.scala:23:7, :115:44]
REG_16 <= s1_is_jal_2; // @[btb.scala:80:23, :116:28]
REG_17 <= REG_16; // @[btb.scala:116:{20,28}]
REG_18 <= s1_hits_3; // @[btb.scala:87:55, :104:18]
io_resp_f2_3_predicted_pc_REG_valid <= s1_resp_3_valid; // @[btb.scala:78:23, :105:44]
io_resp_f2_3_predicted_pc_REG_bits <= s1_resp_3_bits; // @[btb.scala:78:23, :105:44]
io_resp_f2_3_is_br_REG <= s1_is_br_3; // @[btb.scala:79:23, :106:44]
io_resp_f2_3_is_jal_REG <= s1_is_jal_3; // @[btb.scala:80:23, :107:44]
REG_19 <= s1_is_jal_3; // @[btb.scala:80:23, :108:20]
REG_20 <= s1_hits_3; // @[btb.scala:87:55, :112:26]
REG_21 <= REG_20; // @[btb.scala:112:{18,26}]
io_resp_f3_3_predicted_pc_REG_valid <= io_resp_f2_3_predicted_pc_valid_0; // @[btb.scala:23:7, :113:44]
io_resp_f3_3_predicted_pc_REG_bits <= io_resp_f2_3_predicted_pc_bits_0; // @[btb.scala:23:7, :113:44]
io_resp_f3_3_is_br_REG <= io_resp_f2_3_is_br_0; // @[btb.scala:23:7, :114:44]
io_resp_f3_3_is_jal_REG <= io_resp_f2_3_is_jal_0; // @[btb.scala:23:7, :115:44]
REG_22 <= s1_is_jal_3; // @[btb.scala:80:23, :116:28]
REG_23 <= REG_22; // @[btb.scala:116:{20,28}]
if (reset) begin // @[btb.scala:23:7]
doing_reset <= 1'h1; // @[btb.scala:60:28]
reset_idx <= 7'h0; // @[btb.scala:61:28]
end
else begin // @[btb.scala:23:7]
doing_reset <= reset_idx != 7'h7F & doing_reset; // @[btb.scala:60:28, :61:28, :63:{19,36,50}]
reset_idx <= _reset_idx_T_1; // @[btb.scala:61:28, :62:26]
end
always @(posedge)
meta_0_1 meta_0 ( // @[btb.scala:65:47]
.R0_addr (_s1_req_rmeta_T), // @[btb.scala:74:60]
.R0_en (io_f0_valid_0), // @[btb.scala:23:7]
.R0_clk (clock),
.R0_data (_meta_0_R0_data),
.W0_addr (_T_34), // @[btb.scala:169:12]
.W0_en (btb_0_MPORT_en), // @[btb.scala:167:23]
.W0_clk (clock),
.W0_data ({meta_0_MPORT_1_data_3, meta_0_MPORT_1_data_2, meta_0_MPORT_1_data_1, meta_0_MPORT_1_data_0}), // @[btb.scala:65:47, :183:12]
.W0_mask (doing_reset ? 4'hF : s1_update_wmeta_mask) // @[btb.scala:60:28, :154:78, :186:12]
); // @[btb.scala:65:47]
meta_1_1 meta_1 ( // @[btb.scala:65:47]
.R0_addr (_s1_req_rmeta_T_9), // @[btb.scala:74:60]
.R0_en (io_f0_valid_0), // @[btb.scala:23:7]
.R0_clk (clock),
.R0_data (_meta_1_R0_data),
.W0_addr (_T_69), // @[btb.scala:169:12]
.W0_en (btb_1_MPORT_2_en), // @[btb.scala:167:23]
.W0_clk (clock),
.W0_data ({meta_1_MPORT_3_data_3, meta_1_MPORT_3_data_2, meta_1_MPORT_3_data_1, meta_1_MPORT_3_data_0}), // @[btb.scala:65:47, :183:12]
.W0_mask (doing_reset ? 4'hF : s1_update_wmeta_mask) // @[btb.scala:60:28, :154:78, :186:12]
); // @[btb.scala:65:47]
btb_0_1 btb_0 ( // @[btb.scala:66:47]
.R0_addr (_s1_req_rbtb_T), // @[btb.scala:73:59]
.R0_en (io_f0_valid_0), // @[btb.scala:23:7]
.R0_clk (clock),
.R0_data (_btb_0_R0_data),
.W0_addr (_T_34), // @[btb.scala:169:12]
.W0_en (btb_0_MPORT_en), // @[btb.scala:167:23]
.W0_clk (clock),
.W0_data ({btb_0_MPORT_data_3, btb_0_MPORT_data_2, btb_0_MPORT_data_1, btb_0_MPORT_data_0}), // @[btb.scala:66:47, :172:12]
.W0_mask (doing_reset ? 4'hF : s1_update_wbtb_mask) // @[btb.scala:60:28, :151:58, :175:12]
); // @[btb.scala:66:47]
btb_1_1 btb_1 ( // @[btb.scala:66:47]
.R0_addr (_s1_req_rbtb_T_13), // @[btb.scala:73:59]
.R0_en (io_f0_valid_0), // @[btb.scala:23:7]
.R0_clk (clock),
.R0_data (_btb_1_R0_data),
.W0_addr (_T_69), // @[btb.scala:169:12]
.W0_en (btb_1_MPORT_2_en), // @[btb.scala:167:23]
.W0_clk (clock),
.W0_data ({btb_1_MPORT_2_data_3, btb_1_MPORT_2_data_2, btb_1_MPORT_2_data_1, btb_1_MPORT_2_data_0}), // @[btb.scala:66:47, :172:12]
.W0_mask (doing_reset ? 4'hF : s1_update_wbtb_mask) // @[btb.scala:60:28, :151:58, :175:12]
); // @[btb.scala:66:47]
ebtb_1 ebtb ( // @[btb.scala:67:29]
.R0_addr (_s1_req_rebtb_T), // @[btb.scala:75:31]
.R0_en (io_f0_valid_0), // @[btb.scala:23:7]
.R0_clk (clock),
.R0_data (_ebtb_R0_data),
.W0_addr (s1_update_idx[6:0]), // @[predictor.scala:185:30]
.W0_en ((|s1_update_wbtb_mask) & offset_is_extended), // @[btb.scala:144:65, :151:58, :194:{29,37}]
.W0_clk (clock),
.W0_data (s1_update_bits_target) // @[predictor.scala:184:30]
); // @[btb.scala:67:29]
assign io_resp_f1_0_taken = io_resp_f1_0_taken_0; // @[btb.scala:23:7]
assign io_resp_f1_0_is_br = io_resp_f1_0_is_br_0; // @[btb.scala:23:7]
assign io_resp_f1_0_is_jal = io_resp_f1_0_is_jal_0; // @[btb.scala:23:7]
assign io_resp_f1_0_predicted_pc_valid = io_resp_f1_0_predicted_pc_valid_0; // @[btb.scala:23:7]
assign io_resp_f1_0_predicted_pc_bits = io_resp_f1_0_predicted_pc_bits_0; // @[btb.scala:23:7]
assign io_resp_f1_1_taken = io_resp_f1_1_taken_0; // @[btb.scala:23:7]
assign io_resp_f1_1_is_br = io_resp_f1_1_is_br_0; // @[btb.scala:23:7]
assign io_resp_f1_1_is_jal = io_resp_f1_1_is_jal_0; // @[btb.scala:23:7]
assign io_resp_f1_1_predicted_pc_valid = io_resp_f1_1_predicted_pc_valid_0; // @[btb.scala:23:7]
assign io_resp_f1_1_predicted_pc_bits = io_resp_f1_1_predicted_pc_bits_0; // @[btb.scala:23:7]
assign io_resp_f1_2_taken = io_resp_f1_2_taken_0; // @[btb.scala:23:7]
assign io_resp_f1_2_is_br = io_resp_f1_2_is_br_0; // @[btb.scala:23:7]
assign io_resp_f1_2_is_jal = io_resp_f1_2_is_jal_0; // @[btb.scala:23:7]
assign io_resp_f1_2_predicted_pc_valid = io_resp_f1_2_predicted_pc_valid_0; // @[btb.scala:23:7]
assign io_resp_f1_2_predicted_pc_bits = io_resp_f1_2_predicted_pc_bits_0; // @[btb.scala:23:7]
assign io_resp_f1_3_taken = io_resp_f1_3_taken_0; // @[btb.scala:23:7]
assign io_resp_f1_3_is_br = io_resp_f1_3_is_br_0; // @[btb.scala:23:7]
assign io_resp_f1_3_is_jal = io_resp_f1_3_is_jal_0; // @[btb.scala:23:7]
assign io_resp_f1_3_predicted_pc_valid = io_resp_f1_3_predicted_pc_valid_0; // @[btb.scala:23:7]
assign io_resp_f1_3_predicted_pc_bits = io_resp_f1_3_predicted_pc_bits_0; // @[btb.scala:23:7]
assign io_resp_f2_0_taken = io_resp_f2_0_taken_0; // @[btb.scala:23:7]
assign io_resp_f2_0_is_br = io_resp_f2_0_is_br_0; // @[btb.scala:23:7]
assign io_resp_f2_0_is_jal = io_resp_f2_0_is_jal_0; // @[btb.scala:23:7]
assign io_resp_f2_0_predicted_pc_valid = io_resp_f2_0_predicted_pc_valid_0; // @[btb.scala:23:7]
assign io_resp_f2_0_predicted_pc_bits = io_resp_f2_0_predicted_pc_bits_0; // @[btb.scala:23:7]
assign io_resp_f2_1_taken = io_resp_f2_1_taken_0; // @[btb.scala:23:7]
assign io_resp_f2_1_is_br = io_resp_f2_1_is_br_0; // @[btb.scala:23:7]
assign io_resp_f2_1_is_jal = io_resp_f2_1_is_jal_0; // @[btb.scala:23:7]
assign io_resp_f2_1_predicted_pc_valid = io_resp_f2_1_predicted_pc_valid_0; // @[btb.scala:23:7]
assign io_resp_f2_1_predicted_pc_bits = io_resp_f2_1_predicted_pc_bits_0; // @[btb.scala:23:7]
assign io_resp_f2_2_taken = io_resp_f2_2_taken_0; // @[btb.scala:23:7]
assign io_resp_f2_2_is_br = io_resp_f2_2_is_br_0; // @[btb.scala:23:7]
assign io_resp_f2_2_is_jal = io_resp_f2_2_is_jal_0; // @[btb.scala:23:7]
assign io_resp_f2_2_predicted_pc_valid = io_resp_f2_2_predicted_pc_valid_0; // @[btb.scala:23:7]
assign io_resp_f2_2_predicted_pc_bits = io_resp_f2_2_predicted_pc_bits_0; // @[btb.scala:23:7]
assign io_resp_f2_3_taken = io_resp_f2_3_taken_0; // @[btb.scala:23:7]
assign io_resp_f2_3_is_br = io_resp_f2_3_is_br_0; // @[btb.scala:23:7]
assign io_resp_f2_3_is_jal = io_resp_f2_3_is_jal_0; // @[btb.scala:23:7]
assign io_resp_f2_3_predicted_pc_valid = io_resp_f2_3_predicted_pc_valid_0; // @[btb.scala:23:7]
assign io_resp_f2_3_predicted_pc_bits = io_resp_f2_3_predicted_pc_bits_0; // @[btb.scala:23:7]
assign io_resp_f3_0_taken = io_resp_f3_0_taken_0; // @[btb.scala:23:7]
assign io_resp_f3_0_is_br = io_resp_f3_0_is_br_0; // @[btb.scala:23:7]
assign io_resp_f3_0_is_jal = io_resp_f3_0_is_jal_0; // @[btb.scala:23:7]
assign io_resp_f3_0_predicted_pc_valid = io_resp_f3_0_predicted_pc_valid_0; // @[btb.scala:23:7]
assign io_resp_f3_0_predicted_pc_bits = io_resp_f3_0_predicted_pc_bits_0; // @[btb.scala:23:7]
assign io_resp_f3_1_taken = io_resp_f3_1_taken_0; // @[btb.scala:23:7]
assign io_resp_f3_1_is_br = io_resp_f3_1_is_br_0; // @[btb.scala:23:7]
assign io_resp_f3_1_is_jal = io_resp_f3_1_is_jal_0; // @[btb.scala:23:7]
assign io_resp_f3_1_predicted_pc_valid = io_resp_f3_1_predicted_pc_valid_0; // @[btb.scala:23:7]
assign io_resp_f3_1_predicted_pc_bits = io_resp_f3_1_predicted_pc_bits_0; // @[btb.scala:23:7]
assign io_resp_f3_2_taken = io_resp_f3_2_taken_0; // @[btb.scala:23:7]
assign io_resp_f3_2_is_br = io_resp_f3_2_is_br_0; // @[btb.scala:23:7]
assign io_resp_f3_2_is_jal = io_resp_f3_2_is_jal_0; // @[btb.scala:23:7]
assign io_resp_f3_2_predicted_pc_valid = io_resp_f3_2_predicted_pc_valid_0; // @[btb.scala:23:7]
assign io_resp_f3_2_predicted_pc_bits = io_resp_f3_2_predicted_pc_bits_0; // @[btb.scala:23:7]
assign io_resp_f3_3_taken = io_resp_f3_3_taken_0; // @[btb.scala:23:7]
assign io_resp_f3_3_is_br = io_resp_f3_3_is_br_0; // @[btb.scala:23:7]
assign io_resp_f3_3_is_jal = io_resp_f3_3_is_jal_0; // @[btb.scala:23:7]
assign io_resp_f3_3_predicted_pc_valid = io_resp_f3_3_predicted_pc_valid_0; // @[btb.scala:23:7]
assign io_resp_f3_3_predicted_pc_bits = io_resp_f3_3_predicted_pc_bits_0; // @[btb.scala:23:7]
assign io_f3_meta = io_f3_meta_0; // @[btb.scala:23:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module DCacheDataArray_4 :
input clock : Clock
input reset : Reset
output io : { flip req : { valid : UInt<1>, bits : { addr : UInt<12>, write : UInt<1>, wdata : UInt<64>, wordMask : UInt<1>, eccMask : UInt<8>, way_en : UInt<8>}}, resp : UInt<64>[8]}
node eccMask_0 = bits(io.req.bits.eccMask, 0, 0)
node eccMask_1 = bits(io.req.bits.eccMask, 1, 1)
node eccMask_2 = bits(io.req.bits.eccMask, 2, 2)
node eccMask_3 = bits(io.req.bits.eccMask, 3, 3)
node eccMask_4 = bits(io.req.bits.eccMask, 4, 4)
node eccMask_5 = bits(io.req.bits.eccMask, 5, 5)
node eccMask_6 = bits(io.req.bits.eccMask, 6, 6)
node eccMask_7 = bits(io.req.bits.eccMask, 7, 7)
node _wMask_T = bits(io.req.bits.way_en, 0, 0)
node wMask_0 = and(eccMask_0, _wMask_T)
node _wMask_T_1 = bits(io.req.bits.way_en, 0, 0)
node wMask_1 = and(eccMask_1, _wMask_T_1)
node _wMask_T_2 = bits(io.req.bits.way_en, 0, 0)
node wMask_2 = and(eccMask_2, _wMask_T_2)
node _wMask_T_3 = bits(io.req.bits.way_en, 0, 0)
node wMask_3 = and(eccMask_3, _wMask_T_3)
node _wMask_T_4 = bits(io.req.bits.way_en, 0, 0)
node wMask_4 = and(eccMask_4, _wMask_T_4)
node _wMask_T_5 = bits(io.req.bits.way_en, 0, 0)
node wMask_5 = and(eccMask_5, _wMask_T_5)
node _wMask_T_6 = bits(io.req.bits.way_en, 0, 0)
node wMask_6 = and(eccMask_6, _wMask_T_6)
node _wMask_T_7 = bits(io.req.bits.way_en, 0, 0)
node wMask_7 = and(eccMask_7, _wMask_T_7)
node _wMask_T_8 = bits(io.req.bits.way_en, 1, 1)
node wMask_8 = and(eccMask_0, _wMask_T_8)
node _wMask_T_9 = bits(io.req.bits.way_en, 1, 1)
node wMask_9 = and(eccMask_1, _wMask_T_9)
node _wMask_T_10 = bits(io.req.bits.way_en, 1, 1)
node wMask_10 = and(eccMask_2, _wMask_T_10)
node _wMask_T_11 = bits(io.req.bits.way_en, 1, 1)
node wMask_11 = and(eccMask_3, _wMask_T_11)
node _wMask_T_12 = bits(io.req.bits.way_en, 1, 1)
node wMask_12 = and(eccMask_4, _wMask_T_12)
node _wMask_T_13 = bits(io.req.bits.way_en, 1, 1)
node wMask_13 = and(eccMask_5, _wMask_T_13)
node _wMask_T_14 = bits(io.req.bits.way_en, 1, 1)
node wMask_14 = and(eccMask_6, _wMask_T_14)
node _wMask_T_15 = bits(io.req.bits.way_en, 1, 1)
node wMask_15 = and(eccMask_7, _wMask_T_15)
node _wMask_T_16 = bits(io.req.bits.way_en, 2, 2)
node wMask_16 = and(eccMask_0, _wMask_T_16)
node _wMask_T_17 = bits(io.req.bits.way_en, 2, 2)
node wMask_17 = and(eccMask_1, _wMask_T_17)
node _wMask_T_18 = bits(io.req.bits.way_en, 2, 2)
node wMask_18 = and(eccMask_2, _wMask_T_18)
node _wMask_T_19 = bits(io.req.bits.way_en, 2, 2)
node wMask_19 = and(eccMask_3, _wMask_T_19)
node _wMask_T_20 = bits(io.req.bits.way_en, 2, 2)
node wMask_20 = and(eccMask_4, _wMask_T_20)
node _wMask_T_21 = bits(io.req.bits.way_en, 2, 2)
node wMask_21 = and(eccMask_5, _wMask_T_21)
node _wMask_T_22 = bits(io.req.bits.way_en, 2, 2)
node wMask_22 = and(eccMask_6, _wMask_T_22)
node _wMask_T_23 = bits(io.req.bits.way_en, 2, 2)
node wMask_23 = and(eccMask_7, _wMask_T_23)
node _wMask_T_24 = bits(io.req.bits.way_en, 3, 3)
node wMask_24 = and(eccMask_0, _wMask_T_24)
node _wMask_T_25 = bits(io.req.bits.way_en, 3, 3)
node wMask_25 = and(eccMask_1, _wMask_T_25)
node _wMask_T_26 = bits(io.req.bits.way_en, 3, 3)
node wMask_26 = and(eccMask_2, _wMask_T_26)
node _wMask_T_27 = bits(io.req.bits.way_en, 3, 3)
node wMask_27 = and(eccMask_3, _wMask_T_27)
node _wMask_T_28 = bits(io.req.bits.way_en, 3, 3)
node wMask_28 = and(eccMask_4, _wMask_T_28)
node _wMask_T_29 = bits(io.req.bits.way_en, 3, 3)
node wMask_29 = and(eccMask_5, _wMask_T_29)
node _wMask_T_30 = bits(io.req.bits.way_en, 3, 3)
node wMask_30 = and(eccMask_6, _wMask_T_30)
node _wMask_T_31 = bits(io.req.bits.way_en, 3, 3)
node wMask_31 = and(eccMask_7, _wMask_T_31)
node _wMask_T_32 = bits(io.req.bits.way_en, 4, 4)
node wMask_32 = and(eccMask_0, _wMask_T_32)
node _wMask_T_33 = bits(io.req.bits.way_en, 4, 4)
node wMask_33 = and(eccMask_1, _wMask_T_33)
node _wMask_T_34 = bits(io.req.bits.way_en, 4, 4)
node wMask_34 = and(eccMask_2, _wMask_T_34)
node _wMask_T_35 = bits(io.req.bits.way_en, 4, 4)
node wMask_35 = and(eccMask_3, _wMask_T_35)
node _wMask_T_36 = bits(io.req.bits.way_en, 4, 4)
node wMask_36 = and(eccMask_4, _wMask_T_36)
node _wMask_T_37 = bits(io.req.bits.way_en, 4, 4)
node wMask_37 = and(eccMask_5, _wMask_T_37)
node _wMask_T_38 = bits(io.req.bits.way_en, 4, 4)
node wMask_38 = and(eccMask_6, _wMask_T_38)
node _wMask_T_39 = bits(io.req.bits.way_en, 4, 4)
node wMask_39 = and(eccMask_7, _wMask_T_39)
node _wMask_T_40 = bits(io.req.bits.way_en, 5, 5)
node wMask_40 = and(eccMask_0, _wMask_T_40)
node _wMask_T_41 = bits(io.req.bits.way_en, 5, 5)
node wMask_41 = and(eccMask_1, _wMask_T_41)
node _wMask_T_42 = bits(io.req.bits.way_en, 5, 5)
node wMask_42 = and(eccMask_2, _wMask_T_42)
node _wMask_T_43 = bits(io.req.bits.way_en, 5, 5)
node wMask_43 = and(eccMask_3, _wMask_T_43)
node _wMask_T_44 = bits(io.req.bits.way_en, 5, 5)
node wMask_44 = and(eccMask_4, _wMask_T_44)
node _wMask_T_45 = bits(io.req.bits.way_en, 5, 5)
node wMask_45 = and(eccMask_5, _wMask_T_45)
node _wMask_T_46 = bits(io.req.bits.way_en, 5, 5)
node wMask_46 = and(eccMask_6, _wMask_T_46)
node _wMask_T_47 = bits(io.req.bits.way_en, 5, 5)
node wMask_47 = and(eccMask_7, _wMask_T_47)
node _wMask_T_48 = bits(io.req.bits.way_en, 6, 6)
node wMask_48 = and(eccMask_0, _wMask_T_48)
node _wMask_T_49 = bits(io.req.bits.way_en, 6, 6)
node wMask_49 = and(eccMask_1, _wMask_T_49)
node _wMask_T_50 = bits(io.req.bits.way_en, 6, 6)
node wMask_50 = and(eccMask_2, _wMask_T_50)
node _wMask_T_51 = bits(io.req.bits.way_en, 6, 6)
node wMask_51 = and(eccMask_3, _wMask_T_51)
node _wMask_T_52 = bits(io.req.bits.way_en, 6, 6)
node wMask_52 = and(eccMask_4, _wMask_T_52)
node _wMask_T_53 = bits(io.req.bits.way_en, 6, 6)
node wMask_53 = and(eccMask_5, _wMask_T_53)
node _wMask_T_54 = bits(io.req.bits.way_en, 6, 6)
node wMask_54 = and(eccMask_6, _wMask_T_54)
node _wMask_T_55 = bits(io.req.bits.way_en, 6, 6)
node wMask_55 = and(eccMask_7, _wMask_T_55)
node _wMask_T_56 = bits(io.req.bits.way_en, 7, 7)
node wMask_56 = and(eccMask_0, _wMask_T_56)
node _wMask_T_57 = bits(io.req.bits.way_en, 7, 7)
node wMask_57 = and(eccMask_1, _wMask_T_57)
node _wMask_T_58 = bits(io.req.bits.way_en, 7, 7)
node wMask_58 = and(eccMask_2, _wMask_T_58)
node _wMask_T_59 = bits(io.req.bits.way_en, 7, 7)
node wMask_59 = and(eccMask_3, _wMask_T_59)
node _wMask_T_60 = bits(io.req.bits.way_en, 7, 7)
node wMask_60 = and(eccMask_4, _wMask_T_60)
node _wMask_T_61 = bits(io.req.bits.way_en, 7, 7)
node wMask_61 = and(eccMask_5, _wMask_T_61)
node _wMask_T_62 = bits(io.req.bits.way_en, 7, 7)
node wMask_62 = and(eccMask_6, _wMask_T_62)
node _wMask_T_63 = bits(io.req.bits.way_en, 7, 7)
node wMask_63 = and(eccMask_7, _wMask_T_63)
node wWords_0 = bits(io.req.bits.wdata, 63, 0)
node addr = shr(io.req.bits.addr, 3)
smem rockettile_dcache_data_arrays_0 : UInt<8>[64] [512]
node _rdata_valid_T = bits(io.req.bits.wordMask, 0, 0)
node _rdata_valid_T_1 = or(UInt<1>(0h1), _rdata_valid_T)
node rdata_valid = and(io.req.valid, _rdata_valid_T_1)
node _rdata_T = and(rdata_valid, io.req.bits.write)
when _rdata_T :
node rdata_wData_0 = bits(wWords_0, 7, 0)
node rdata_wData_1 = bits(wWords_0, 15, 8)
node rdata_wData_2 = bits(wWords_0, 23, 16)
node rdata_wData_3 = bits(wWords_0, 31, 24)
node rdata_wData_4 = bits(wWords_0, 39, 32)
node rdata_wData_5 = bits(wWords_0, 47, 40)
node rdata_wData_6 = bits(wWords_0, 55, 48)
node rdata_wData_7 = bits(wWords_0, 63, 56)
wire _rdata_WIRE : UInt<8>[64]
connect _rdata_WIRE[0], rdata_wData_0
connect _rdata_WIRE[1], rdata_wData_1
connect _rdata_WIRE[2], rdata_wData_2
connect _rdata_WIRE[3], rdata_wData_3
connect _rdata_WIRE[4], rdata_wData_4
connect _rdata_WIRE[5], rdata_wData_5
connect _rdata_WIRE[6], rdata_wData_6
connect _rdata_WIRE[7], rdata_wData_7
connect _rdata_WIRE[8], rdata_wData_0
connect _rdata_WIRE[9], rdata_wData_1
connect _rdata_WIRE[10], rdata_wData_2
connect _rdata_WIRE[11], rdata_wData_3
connect _rdata_WIRE[12], rdata_wData_4
connect _rdata_WIRE[13], rdata_wData_5
connect _rdata_WIRE[14], rdata_wData_6
connect _rdata_WIRE[15], rdata_wData_7
connect _rdata_WIRE[16], rdata_wData_0
connect _rdata_WIRE[17], rdata_wData_1
connect _rdata_WIRE[18], rdata_wData_2
connect _rdata_WIRE[19], rdata_wData_3
connect _rdata_WIRE[20], rdata_wData_4
connect _rdata_WIRE[21], rdata_wData_5
connect _rdata_WIRE[22], rdata_wData_6
connect _rdata_WIRE[23], rdata_wData_7
connect _rdata_WIRE[24], rdata_wData_0
connect _rdata_WIRE[25], rdata_wData_1
connect _rdata_WIRE[26], rdata_wData_2
connect _rdata_WIRE[27], rdata_wData_3
connect _rdata_WIRE[28], rdata_wData_4
connect _rdata_WIRE[29], rdata_wData_5
connect _rdata_WIRE[30], rdata_wData_6
connect _rdata_WIRE[31], rdata_wData_7
connect _rdata_WIRE[32], rdata_wData_0
connect _rdata_WIRE[33], rdata_wData_1
connect _rdata_WIRE[34], rdata_wData_2
connect _rdata_WIRE[35], rdata_wData_3
connect _rdata_WIRE[36], rdata_wData_4
connect _rdata_WIRE[37], rdata_wData_5
connect _rdata_WIRE[38], rdata_wData_6
connect _rdata_WIRE[39], rdata_wData_7
connect _rdata_WIRE[40], rdata_wData_0
connect _rdata_WIRE[41], rdata_wData_1
connect _rdata_WIRE[42], rdata_wData_2
connect _rdata_WIRE[43], rdata_wData_3
connect _rdata_WIRE[44], rdata_wData_4
connect _rdata_WIRE[45], rdata_wData_5
connect _rdata_WIRE[46], rdata_wData_6
connect _rdata_WIRE[47], rdata_wData_7
connect _rdata_WIRE[48], rdata_wData_0
connect _rdata_WIRE[49], rdata_wData_1
connect _rdata_WIRE[50], rdata_wData_2
connect _rdata_WIRE[51], rdata_wData_3
connect _rdata_WIRE[52], rdata_wData_4
connect _rdata_WIRE[53], rdata_wData_5
connect _rdata_WIRE[54], rdata_wData_6
connect _rdata_WIRE[55], rdata_wData_7
connect _rdata_WIRE[56], rdata_wData_0
connect _rdata_WIRE[57], rdata_wData_1
connect _rdata_WIRE[58], rdata_wData_2
connect _rdata_WIRE[59], rdata_wData_3
connect _rdata_WIRE[60], rdata_wData_4
connect _rdata_WIRE[61], rdata_wData_5
connect _rdata_WIRE[62], rdata_wData_6
connect _rdata_WIRE[63], rdata_wData_7
write mport rdata_MPORT = rockettile_dcache_data_arrays_0[addr], clock
when wMask_0 :
connect rdata_MPORT[0], _rdata_WIRE[0]
when wMask_1 :
connect rdata_MPORT[1], _rdata_WIRE[1]
when wMask_2 :
connect rdata_MPORT[2], _rdata_WIRE[2]
when wMask_3 :
connect rdata_MPORT[3], _rdata_WIRE[3]
when wMask_4 :
connect rdata_MPORT[4], _rdata_WIRE[4]
when wMask_5 :
connect rdata_MPORT[5], _rdata_WIRE[5]
when wMask_6 :
connect rdata_MPORT[6], _rdata_WIRE[6]
when wMask_7 :
connect rdata_MPORT[7], _rdata_WIRE[7]
when wMask_8 :
connect rdata_MPORT[8], _rdata_WIRE[8]
when wMask_9 :
connect rdata_MPORT[9], _rdata_WIRE[9]
when wMask_10 :
connect rdata_MPORT[10], _rdata_WIRE[10]
when wMask_11 :
connect rdata_MPORT[11], _rdata_WIRE[11]
when wMask_12 :
connect rdata_MPORT[12], _rdata_WIRE[12]
when wMask_13 :
connect rdata_MPORT[13], _rdata_WIRE[13]
when wMask_14 :
connect rdata_MPORT[14], _rdata_WIRE[14]
when wMask_15 :
connect rdata_MPORT[15], _rdata_WIRE[15]
when wMask_16 :
connect rdata_MPORT[16], _rdata_WIRE[16]
when wMask_17 :
connect rdata_MPORT[17], _rdata_WIRE[17]
when wMask_18 :
connect rdata_MPORT[18], _rdata_WIRE[18]
when wMask_19 :
connect rdata_MPORT[19], _rdata_WIRE[19]
when wMask_20 :
connect rdata_MPORT[20], _rdata_WIRE[20]
when wMask_21 :
connect rdata_MPORT[21], _rdata_WIRE[21]
when wMask_22 :
connect rdata_MPORT[22], _rdata_WIRE[22]
when wMask_23 :
connect rdata_MPORT[23], _rdata_WIRE[23]
when wMask_24 :
connect rdata_MPORT[24], _rdata_WIRE[24]
when wMask_25 :
connect rdata_MPORT[25], _rdata_WIRE[25]
when wMask_26 :
connect rdata_MPORT[26], _rdata_WIRE[26]
when wMask_27 :
connect rdata_MPORT[27], _rdata_WIRE[27]
when wMask_28 :
connect rdata_MPORT[28], _rdata_WIRE[28]
when wMask_29 :
connect rdata_MPORT[29], _rdata_WIRE[29]
when wMask_30 :
connect rdata_MPORT[30], _rdata_WIRE[30]
when wMask_31 :
connect rdata_MPORT[31], _rdata_WIRE[31]
when wMask_32 :
connect rdata_MPORT[32], _rdata_WIRE[32]
when wMask_33 :
connect rdata_MPORT[33], _rdata_WIRE[33]
when wMask_34 :
connect rdata_MPORT[34], _rdata_WIRE[34]
when wMask_35 :
connect rdata_MPORT[35], _rdata_WIRE[35]
when wMask_36 :
connect rdata_MPORT[36], _rdata_WIRE[36]
when wMask_37 :
connect rdata_MPORT[37], _rdata_WIRE[37]
when wMask_38 :
connect rdata_MPORT[38], _rdata_WIRE[38]
when wMask_39 :
connect rdata_MPORT[39], _rdata_WIRE[39]
when wMask_40 :
connect rdata_MPORT[40], _rdata_WIRE[40]
when wMask_41 :
connect rdata_MPORT[41], _rdata_WIRE[41]
when wMask_42 :
connect rdata_MPORT[42], _rdata_WIRE[42]
when wMask_43 :
connect rdata_MPORT[43], _rdata_WIRE[43]
when wMask_44 :
connect rdata_MPORT[44], _rdata_WIRE[44]
when wMask_45 :
connect rdata_MPORT[45], _rdata_WIRE[45]
when wMask_46 :
connect rdata_MPORT[46], _rdata_WIRE[46]
when wMask_47 :
connect rdata_MPORT[47], _rdata_WIRE[47]
when wMask_48 :
connect rdata_MPORT[48], _rdata_WIRE[48]
when wMask_49 :
connect rdata_MPORT[49], _rdata_WIRE[49]
when wMask_50 :
connect rdata_MPORT[50], _rdata_WIRE[50]
when wMask_51 :
connect rdata_MPORT[51], _rdata_WIRE[51]
when wMask_52 :
connect rdata_MPORT[52], _rdata_WIRE[52]
when wMask_53 :
connect rdata_MPORT[53], _rdata_WIRE[53]
when wMask_54 :
connect rdata_MPORT[54], _rdata_WIRE[54]
when wMask_55 :
connect rdata_MPORT[55], _rdata_WIRE[55]
when wMask_56 :
connect rdata_MPORT[56], _rdata_WIRE[56]
when wMask_57 :
connect rdata_MPORT[57], _rdata_WIRE[57]
when wMask_58 :
connect rdata_MPORT[58], _rdata_WIRE[58]
when wMask_59 :
connect rdata_MPORT[59], _rdata_WIRE[59]
when wMask_60 :
connect rdata_MPORT[60], _rdata_WIRE[60]
when wMask_61 :
connect rdata_MPORT[61], _rdata_WIRE[61]
when wMask_62 :
connect rdata_MPORT[62], _rdata_WIRE[62]
when wMask_63 :
connect rdata_MPORT[63], _rdata_WIRE[63]
node _rdata_data_T = eq(io.req.bits.write, UInt<1>(0h0))
node _rdata_data_T_1 = and(rdata_valid, _rdata_data_T)
wire _rdata_data_WIRE : UInt<9>
invalidate _rdata_data_WIRE
when _rdata_data_T_1 :
connect _rdata_data_WIRE, addr
read mport rdata_data = rockettile_dcache_data_arrays_0[_rdata_data_WIRE], clock
node rdata_lo_lo = cat(rdata_data[1], rdata_data[0])
node rdata_lo_hi = cat(rdata_data[3], rdata_data[2])
node rdata_lo = cat(rdata_lo_hi, rdata_lo_lo)
node rdata_hi_lo = cat(rdata_data[5], rdata_data[4])
node rdata_hi_hi = cat(rdata_data[7], rdata_data[6])
node rdata_hi = cat(rdata_hi_hi, rdata_hi_lo)
node rdata_0_0 = cat(rdata_hi, rdata_lo)
node rdata_lo_lo_1 = cat(rdata_data[9], rdata_data[8])
node rdata_lo_hi_1 = cat(rdata_data[11], rdata_data[10])
node rdata_lo_1 = cat(rdata_lo_hi_1, rdata_lo_lo_1)
node rdata_hi_lo_1 = cat(rdata_data[13], rdata_data[12])
node rdata_hi_hi_1 = cat(rdata_data[15], rdata_data[14])
node rdata_hi_1 = cat(rdata_hi_hi_1, rdata_hi_lo_1)
node rdata_0_1 = cat(rdata_hi_1, rdata_lo_1)
node rdata_lo_lo_2 = cat(rdata_data[17], rdata_data[16])
node rdata_lo_hi_2 = cat(rdata_data[19], rdata_data[18])
node rdata_lo_2 = cat(rdata_lo_hi_2, rdata_lo_lo_2)
node rdata_hi_lo_2 = cat(rdata_data[21], rdata_data[20])
node rdata_hi_hi_2 = cat(rdata_data[23], rdata_data[22])
node rdata_hi_2 = cat(rdata_hi_hi_2, rdata_hi_lo_2)
node rdata_0_2 = cat(rdata_hi_2, rdata_lo_2)
node rdata_lo_lo_3 = cat(rdata_data[25], rdata_data[24])
node rdata_lo_hi_3 = cat(rdata_data[27], rdata_data[26])
node rdata_lo_3 = cat(rdata_lo_hi_3, rdata_lo_lo_3)
node rdata_hi_lo_3 = cat(rdata_data[29], rdata_data[28])
node rdata_hi_hi_3 = cat(rdata_data[31], rdata_data[30])
node rdata_hi_3 = cat(rdata_hi_hi_3, rdata_hi_lo_3)
node rdata_0_3 = cat(rdata_hi_3, rdata_lo_3)
node rdata_lo_lo_4 = cat(rdata_data[33], rdata_data[32])
node rdata_lo_hi_4 = cat(rdata_data[35], rdata_data[34])
node rdata_lo_4 = cat(rdata_lo_hi_4, rdata_lo_lo_4)
node rdata_hi_lo_4 = cat(rdata_data[37], rdata_data[36])
node rdata_hi_hi_4 = cat(rdata_data[39], rdata_data[38])
node rdata_hi_4 = cat(rdata_hi_hi_4, rdata_hi_lo_4)
node rdata_0_4 = cat(rdata_hi_4, rdata_lo_4)
node rdata_lo_lo_5 = cat(rdata_data[41], rdata_data[40])
node rdata_lo_hi_5 = cat(rdata_data[43], rdata_data[42])
node rdata_lo_5 = cat(rdata_lo_hi_5, rdata_lo_lo_5)
node rdata_hi_lo_5 = cat(rdata_data[45], rdata_data[44])
node rdata_hi_hi_5 = cat(rdata_data[47], rdata_data[46])
node rdata_hi_5 = cat(rdata_hi_hi_5, rdata_hi_lo_5)
node rdata_0_5 = cat(rdata_hi_5, rdata_lo_5)
node rdata_lo_lo_6 = cat(rdata_data[49], rdata_data[48])
node rdata_lo_hi_6 = cat(rdata_data[51], rdata_data[50])
node rdata_lo_6 = cat(rdata_lo_hi_6, rdata_lo_lo_6)
node rdata_hi_lo_6 = cat(rdata_data[53], rdata_data[52])
node rdata_hi_hi_6 = cat(rdata_data[55], rdata_data[54])
node rdata_hi_6 = cat(rdata_hi_hi_6, rdata_hi_lo_6)
node rdata_0_6 = cat(rdata_hi_6, rdata_lo_6)
node rdata_lo_lo_7 = cat(rdata_data[57], rdata_data[56])
node rdata_lo_hi_7 = cat(rdata_data[59], rdata_data[58])
node rdata_lo_7 = cat(rdata_lo_hi_7, rdata_lo_lo_7)
node rdata_hi_lo_7 = cat(rdata_data[61], rdata_data[60])
node rdata_hi_hi_7 = cat(rdata_data[63], rdata_data[62])
node rdata_hi_7 = cat(rdata_hi_hi_7, rdata_hi_lo_7)
node rdata_0_7 = cat(rdata_hi_7, rdata_lo_7)
connect io.resp[0], rdata_0_0
connect io.resp[1], rdata_0_1
connect io.resp[2], rdata_0_2
connect io.resp[3], rdata_0_3
connect io.resp[4], rdata_0_4
connect io.resp[5], rdata_0_5
connect io.resp[6], rdata_0_6
connect io.resp[7], rdata_0_7 | module DCacheDataArray_4( // @[DCache.scala:49:7]
input clock, // @[DCache.scala:49:7]
input reset, // @[DCache.scala:49:7]
input io_req_valid, // @[DCache.scala:50:14]
input [11:0] io_req_bits_addr, // @[DCache.scala:50:14]
input io_req_bits_write, // @[DCache.scala:50:14]
input [63:0] io_req_bits_wdata, // @[DCache.scala:50:14]
input io_req_bits_wordMask, // @[DCache.scala:50:14]
input [7:0] io_req_bits_eccMask, // @[DCache.scala:50:14]
input [7:0] io_req_bits_way_en, // @[DCache.scala:50:14]
output [63:0] io_resp_0, // @[DCache.scala:50:14]
output [63:0] io_resp_1, // @[DCache.scala:50:14]
output [63:0] io_resp_2, // @[DCache.scala:50:14]
output [63:0] io_resp_3, // @[DCache.scala:50:14]
output [63:0] io_resp_4, // @[DCache.scala:50:14]
output [63:0] io_resp_5, // @[DCache.scala:50:14]
output [63:0] io_resp_6, // @[DCache.scala:50:14]
output [63:0] io_resp_7 // @[DCache.scala:50:14]
);
wire [511:0] _rockettile_dcache_data_arrays_0_RW0_rdata; // @[DescribedSRAM.scala:17:26]
wire io_req_valid_0 = io_req_valid; // @[DCache.scala:49:7]
wire [11:0] io_req_bits_addr_0 = io_req_bits_addr; // @[DCache.scala:49:7]
wire io_req_bits_write_0 = io_req_bits_write; // @[DCache.scala:49:7]
wire [63:0] io_req_bits_wdata_0 = io_req_bits_wdata; // @[DCache.scala:49:7]
wire io_req_bits_wordMask_0 = io_req_bits_wordMask; // @[DCache.scala:49:7]
wire [7:0] io_req_bits_eccMask_0 = io_req_bits_eccMask; // @[DCache.scala:49:7]
wire [7:0] io_req_bits_way_en_0 = io_req_bits_way_en; // @[DCache.scala:49:7]
wire _rdata_valid_T_1 = 1'h1; // @[DCache.scala:71:60]
wire rdata_valid = io_req_valid_0; // @[DCache.scala:49:7, :71:30]
wire [63:0] wWords_0 = io_req_bits_wdata_0; // @[package.scala:211:50]
wire _rdata_valid_T = io_req_bits_wordMask_0; // @[DCache.scala:49:7, :71:83]
wire [63:0] rdata_0_0; // @[package.scala:45:27]
wire [63:0] rdata_0_1; // @[package.scala:45:27]
wire [63:0] rdata_0_2; // @[package.scala:45:27]
wire [63:0] rdata_0_3; // @[package.scala:45:27]
wire [63:0] rdata_0_4; // @[package.scala:45:27]
wire [63:0] rdata_0_5; // @[package.scala:45:27]
wire [63:0] rdata_0_6; // @[package.scala:45:27]
wire [63:0] rdata_0_7; // @[package.scala:45:27]
wire [63:0] io_resp_0_0; // @[DCache.scala:49:7]
wire [63:0] io_resp_1_0; // @[DCache.scala:49:7]
wire [63:0] io_resp_2_0; // @[DCache.scala:49:7]
wire [63:0] io_resp_3_0; // @[DCache.scala:49:7]
wire [63:0] io_resp_4_0; // @[DCache.scala:49:7]
wire [63:0] io_resp_5_0; // @[DCache.scala:49:7]
wire [63:0] io_resp_6_0; // @[DCache.scala:49:7]
wire [63:0] io_resp_7_0; // @[DCache.scala:49:7]
wire eccMask_0 = io_req_bits_eccMask_0[0]; // @[DCache.scala:49:7, :56:82]
wire eccMask_1 = io_req_bits_eccMask_0[1]; // @[DCache.scala:49:7, :56:82]
wire eccMask_2 = io_req_bits_eccMask_0[2]; // @[DCache.scala:49:7, :56:82]
wire eccMask_3 = io_req_bits_eccMask_0[3]; // @[DCache.scala:49:7, :56:82]
wire eccMask_4 = io_req_bits_eccMask_0[4]; // @[DCache.scala:49:7, :56:82]
wire eccMask_5 = io_req_bits_eccMask_0[5]; // @[DCache.scala:49:7, :56:82]
wire eccMask_6 = io_req_bits_eccMask_0[6]; // @[DCache.scala:49:7, :56:82]
wire eccMask_7 = io_req_bits_eccMask_0[7]; // @[DCache.scala:49:7, :56:82]
wire _wMask_T = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_1 = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_2 = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_3 = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_4 = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_5 = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_6 = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_7 = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108]
wire wMask_0 = eccMask_0 & _wMask_T; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_1 = eccMask_1 & _wMask_T_1; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_2 = eccMask_2 & _wMask_T_2; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_3 = eccMask_3 & _wMask_T_3; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_4 = eccMask_4 & _wMask_T_4; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_5 = eccMask_5 & _wMask_T_5; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_6 = eccMask_6 & _wMask_T_6; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_7 = eccMask_7 & _wMask_T_7; // @[DCache.scala:56:82, :57:{87,108}]
wire _wMask_T_8 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_9 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_10 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_11 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_12 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_13 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_14 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_15 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108]
wire wMask_8 = eccMask_0 & _wMask_T_8; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_9 = eccMask_1 & _wMask_T_9; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_10 = eccMask_2 & _wMask_T_10; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_11 = eccMask_3 & _wMask_T_11; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_12 = eccMask_4 & _wMask_T_12; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_13 = eccMask_5 & _wMask_T_13; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_14 = eccMask_6 & _wMask_T_14; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_15 = eccMask_7 & _wMask_T_15; // @[DCache.scala:56:82, :57:{87,108}]
wire _wMask_T_16 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_17 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_18 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_19 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_20 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_21 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_22 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_23 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108]
wire wMask_16 = eccMask_0 & _wMask_T_16; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_17 = eccMask_1 & _wMask_T_17; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_18 = eccMask_2 & _wMask_T_18; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_19 = eccMask_3 & _wMask_T_19; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_20 = eccMask_4 & _wMask_T_20; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_21 = eccMask_5 & _wMask_T_21; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_22 = eccMask_6 & _wMask_T_22; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_23 = eccMask_7 & _wMask_T_23; // @[DCache.scala:56:82, :57:{87,108}]
wire _wMask_T_24 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_25 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_26 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_27 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_28 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_29 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_30 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_31 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108]
wire wMask_24 = eccMask_0 & _wMask_T_24; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_25 = eccMask_1 & _wMask_T_25; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_26 = eccMask_2 & _wMask_T_26; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_27 = eccMask_3 & _wMask_T_27; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_28 = eccMask_4 & _wMask_T_28; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_29 = eccMask_5 & _wMask_T_29; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_30 = eccMask_6 & _wMask_T_30; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_31 = eccMask_7 & _wMask_T_31; // @[DCache.scala:56:82, :57:{87,108}]
wire _wMask_T_32 = io_req_bits_way_en_0[4]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_33 = io_req_bits_way_en_0[4]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_34 = io_req_bits_way_en_0[4]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_35 = io_req_bits_way_en_0[4]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_36 = io_req_bits_way_en_0[4]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_37 = io_req_bits_way_en_0[4]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_38 = io_req_bits_way_en_0[4]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_39 = io_req_bits_way_en_0[4]; // @[DCache.scala:49:7, :57:108]
wire wMask_32 = eccMask_0 & _wMask_T_32; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_33 = eccMask_1 & _wMask_T_33; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_34 = eccMask_2 & _wMask_T_34; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_35 = eccMask_3 & _wMask_T_35; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_36 = eccMask_4 & _wMask_T_36; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_37 = eccMask_5 & _wMask_T_37; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_38 = eccMask_6 & _wMask_T_38; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_39 = eccMask_7 & _wMask_T_39; // @[DCache.scala:56:82, :57:{87,108}]
wire _wMask_T_40 = io_req_bits_way_en_0[5]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_41 = io_req_bits_way_en_0[5]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_42 = io_req_bits_way_en_0[5]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_43 = io_req_bits_way_en_0[5]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_44 = io_req_bits_way_en_0[5]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_45 = io_req_bits_way_en_0[5]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_46 = io_req_bits_way_en_0[5]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_47 = io_req_bits_way_en_0[5]; // @[DCache.scala:49:7, :57:108]
wire wMask_40 = eccMask_0 & _wMask_T_40; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_41 = eccMask_1 & _wMask_T_41; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_42 = eccMask_2 & _wMask_T_42; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_43 = eccMask_3 & _wMask_T_43; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_44 = eccMask_4 & _wMask_T_44; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_45 = eccMask_5 & _wMask_T_45; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_46 = eccMask_6 & _wMask_T_46; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_47 = eccMask_7 & _wMask_T_47; // @[DCache.scala:56:82, :57:{87,108}]
wire _wMask_T_48 = io_req_bits_way_en_0[6]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_49 = io_req_bits_way_en_0[6]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_50 = io_req_bits_way_en_0[6]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_51 = io_req_bits_way_en_0[6]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_52 = io_req_bits_way_en_0[6]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_53 = io_req_bits_way_en_0[6]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_54 = io_req_bits_way_en_0[6]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_55 = io_req_bits_way_en_0[6]; // @[DCache.scala:49:7, :57:108]
wire wMask_48 = eccMask_0 & _wMask_T_48; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_49 = eccMask_1 & _wMask_T_49; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_50 = eccMask_2 & _wMask_T_50; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_51 = eccMask_3 & _wMask_T_51; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_52 = eccMask_4 & _wMask_T_52; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_53 = eccMask_5 & _wMask_T_53; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_54 = eccMask_6 & _wMask_T_54; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_55 = eccMask_7 & _wMask_T_55; // @[DCache.scala:56:82, :57:{87,108}]
wire _wMask_T_56 = io_req_bits_way_en_0[7]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_57 = io_req_bits_way_en_0[7]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_58 = io_req_bits_way_en_0[7]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_59 = io_req_bits_way_en_0[7]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_60 = io_req_bits_way_en_0[7]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_61 = io_req_bits_way_en_0[7]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_62 = io_req_bits_way_en_0[7]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_63 = io_req_bits_way_en_0[7]; // @[DCache.scala:49:7, :57:108]
wire wMask_56 = eccMask_0 & _wMask_T_56; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_57 = eccMask_1 & _wMask_T_57; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_58 = eccMask_2 & _wMask_T_58; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_59 = eccMask_3 & _wMask_T_59; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_60 = eccMask_4 & _wMask_T_60; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_61 = eccMask_5 & _wMask_T_61; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_62 = eccMask_6 & _wMask_T_62; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_63 = eccMask_7 & _wMask_T_63; // @[DCache.scala:56:82, :57:{87,108}]
wire [8:0] addr = io_req_bits_addr_0[11:3]; // @[DCache.scala:49:7, :59:31]
wire [8:0] _rdata_data_WIRE = addr; // @[DCache.scala:59:31, :77:26]
wire _rdata_T; // @[DCache.scala:72:17]
wire _rdata_data_T_1; // @[DCache.scala:77:39]
wire [7:0] _rdata_WIRE_0; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_1; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_2; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_3; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_4; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_5; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_6; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_7; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_8; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_9; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_10; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_11; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_12; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_13; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_14; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_15; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_16; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_17; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_18; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_19; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_20; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_21; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_22; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_23; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_24; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_25; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_26; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_27; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_28; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_29; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_30; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_31; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_32; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_33; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_34; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_35; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_36; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_37; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_38; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_39; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_40; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_41; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_42; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_43; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_44; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_45; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_46; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_47; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_48; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_49; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_50; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_51; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_52; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_53; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_54; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_55; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_56; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_57; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_58; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_59; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_60; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_61; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_62; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_63; // @[DCache.scala:75:32]
assign _rdata_T = rdata_valid & io_req_bits_write_0; // @[DCache.scala:49:7, :71:30, :72:17]
wire [7:0] rdata_wData_0 = wWords_0[7:0]; // @[package.scala:211:50]
assign _rdata_WIRE_0 = rdata_wData_0; // @[package.scala:211:50]
assign _rdata_WIRE_8 = rdata_wData_0; // @[package.scala:211:50]
assign _rdata_WIRE_16 = rdata_wData_0; // @[package.scala:211:50]
assign _rdata_WIRE_24 = rdata_wData_0; // @[package.scala:211:50]
assign _rdata_WIRE_32 = rdata_wData_0; // @[package.scala:211:50]
assign _rdata_WIRE_40 = rdata_wData_0; // @[package.scala:211:50]
assign _rdata_WIRE_48 = rdata_wData_0; // @[package.scala:211:50]
assign _rdata_WIRE_56 = rdata_wData_0; // @[package.scala:211:50]
wire [7:0] rdata_wData_1 = wWords_0[15:8]; // @[package.scala:211:50]
assign _rdata_WIRE_1 = rdata_wData_1; // @[package.scala:211:50]
assign _rdata_WIRE_9 = rdata_wData_1; // @[package.scala:211:50]
assign _rdata_WIRE_17 = rdata_wData_1; // @[package.scala:211:50]
assign _rdata_WIRE_25 = rdata_wData_1; // @[package.scala:211:50]
assign _rdata_WIRE_33 = rdata_wData_1; // @[package.scala:211:50]
assign _rdata_WIRE_41 = rdata_wData_1; // @[package.scala:211:50]
assign _rdata_WIRE_49 = rdata_wData_1; // @[package.scala:211:50]
assign _rdata_WIRE_57 = rdata_wData_1; // @[package.scala:211:50]
wire [7:0] rdata_wData_2 = wWords_0[23:16]; // @[package.scala:211:50]
assign _rdata_WIRE_2 = rdata_wData_2; // @[package.scala:211:50]
assign _rdata_WIRE_10 = rdata_wData_2; // @[package.scala:211:50]
assign _rdata_WIRE_18 = rdata_wData_2; // @[package.scala:211:50]
assign _rdata_WIRE_26 = rdata_wData_2; // @[package.scala:211:50]
assign _rdata_WIRE_34 = rdata_wData_2; // @[package.scala:211:50]
assign _rdata_WIRE_42 = rdata_wData_2; // @[package.scala:211:50]
assign _rdata_WIRE_50 = rdata_wData_2; // @[package.scala:211:50]
assign _rdata_WIRE_58 = rdata_wData_2; // @[package.scala:211:50]
wire [7:0] rdata_wData_3 = wWords_0[31:24]; // @[package.scala:211:50]
assign _rdata_WIRE_3 = rdata_wData_3; // @[package.scala:211:50]
assign _rdata_WIRE_11 = rdata_wData_3; // @[package.scala:211:50]
assign _rdata_WIRE_19 = rdata_wData_3; // @[package.scala:211:50]
assign _rdata_WIRE_27 = rdata_wData_3; // @[package.scala:211:50]
assign _rdata_WIRE_35 = rdata_wData_3; // @[package.scala:211:50]
assign _rdata_WIRE_43 = rdata_wData_3; // @[package.scala:211:50]
assign _rdata_WIRE_51 = rdata_wData_3; // @[package.scala:211:50]
assign _rdata_WIRE_59 = rdata_wData_3; // @[package.scala:211:50]
wire [7:0] rdata_wData_4 = wWords_0[39:32]; // @[package.scala:211:50]
assign _rdata_WIRE_4 = rdata_wData_4; // @[package.scala:211:50]
assign _rdata_WIRE_12 = rdata_wData_4; // @[package.scala:211:50]
assign _rdata_WIRE_20 = rdata_wData_4; // @[package.scala:211:50]
assign _rdata_WIRE_28 = rdata_wData_4; // @[package.scala:211:50]
assign _rdata_WIRE_36 = rdata_wData_4; // @[package.scala:211:50]
assign _rdata_WIRE_44 = rdata_wData_4; // @[package.scala:211:50]
assign _rdata_WIRE_52 = rdata_wData_4; // @[package.scala:211:50]
assign _rdata_WIRE_60 = rdata_wData_4; // @[package.scala:211:50]
wire [7:0] rdata_wData_5 = wWords_0[47:40]; // @[package.scala:211:50]
assign _rdata_WIRE_5 = rdata_wData_5; // @[package.scala:211:50]
assign _rdata_WIRE_13 = rdata_wData_5; // @[package.scala:211:50]
assign _rdata_WIRE_21 = rdata_wData_5; // @[package.scala:211:50]
assign _rdata_WIRE_29 = rdata_wData_5; // @[package.scala:211:50]
assign _rdata_WIRE_37 = rdata_wData_5; // @[package.scala:211:50]
assign _rdata_WIRE_45 = rdata_wData_5; // @[package.scala:211:50]
assign _rdata_WIRE_53 = rdata_wData_5; // @[package.scala:211:50]
assign _rdata_WIRE_61 = rdata_wData_5; // @[package.scala:211:50]
wire [7:0] rdata_wData_6 = wWords_0[55:48]; // @[package.scala:211:50]
assign _rdata_WIRE_6 = rdata_wData_6; // @[package.scala:211:50]
assign _rdata_WIRE_14 = rdata_wData_6; // @[package.scala:211:50]
assign _rdata_WIRE_22 = rdata_wData_6; // @[package.scala:211:50]
assign _rdata_WIRE_30 = rdata_wData_6; // @[package.scala:211:50]
assign _rdata_WIRE_38 = rdata_wData_6; // @[package.scala:211:50]
assign _rdata_WIRE_46 = rdata_wData_6; // @[package.scala:211:50]
assign _rdata_WIRE_54 = rdata_wData_6; // @[package.scala:211:50]
assign _rdata_WIRE_62 = rdata_wData_6; // @[package.scala:211:50]
wire [7:0] rdata_wData_7 = wWords_0[63:56]; // @[package.scala:211:50]
assign _rdata_WIRE_7 = rdata_wData_7; // @[package.scala:211:50]
assign _rdata_WIRE_15 = rdata_wData_7; // @[package.scala:211:50]
assign _rdata_WIRE_23 = rdata_wData_7; // @[package.scala:211:50]
assign _rdata_WIRE_31 = rdata_wData_7; // @[package.scala:211:50]
assign _rdata_WIRE_39 = rdata_wData_7; // @[package.scala:211:50]
assign _rdata_WIRE_47 = rdata_wData_7; // @[package.scala:211:50]
assign _rdata_WIRE_55 = rdata_wData_7; // @[package.scala:211:50]
assign _rdata_WIRE_63 = rdata_wData_7; // @[package.scala:211:50]
wire _rdata_data_T = ~io_req_bits_write_0; // @[DCache.scala:49:7, :77:42]
assign _rdata_data_T_1 = rdata_valid & _rdata_data_T; // @[DCache.scala:71:30, :77:{39,42}]
wire [15:0] rdata_lo_lo = _rockettile_dcache_data_arrays_0_RW0_rdata[15:0]; // @[package.scala:45:27]
wire [15:0] rdata_lo_hi = _rockettile_dcache_data_arrays_0_RW0_rdata[31:16]; // @[package.scala:45:27]
wire [31:0] rdata_lo = {rdata_lo_hi, rdata_lo_lo}; // @[package.scala:45:27]
wire [15:0] rdata_hi_lo = _rockettile_dcache_data_arrays_0_RW0_rdata[47:32]; // @[package.scala:45:27]
wire [15:0] rdata_hi_hi = _rockettile_dcache_data_arrays_0_RW0_rdata[63:48]; // @[package.scala:45:27]
wire [31:0] rdata_hi = {rdata_hi_hi, rdata_hi_lo}; // @[package.scala:45:27]
assign rdata_0_0 = {rdata_hi, rdata_lo}; // @[package.scala:45:27]
assign io_resp_0_0 = rdata_0_0; // @[package.scala:45:27]
wire [15:0] rdata_lo_lo_1 = _rockettile_dcache_data_arrays_0_RW0_rdata[79:64]; // @[package.scala:45:27]
wire [15:0] rdata_lo_hi_1 = _rockettile_dcache_data_arrays_0_RW0_rdata[95:80]; // @[package.scala:45:27]
wire [31:0] rdata_lo_1 = {rdata_lo_hi_1, rdata_lo_lo_1}; // @[package.scala:45:27]
wire [15:0] rdata_hi_lo_1 = _rockettile_dcache_data_arrays_0_RW0_rdata[111:96]; // @[package.scala:45:27]
wire [15:0] rdata_hi_hi_1 = _rockettile_dcache_data_arrays_0_RW0_rdata[127:112]; // @[package.scala:45:27]
wire [31:0] rdata_hi_1 = {rdata_hi_hi_1, rdata_hi_lo_1}; // @[package.scala:45:27]
assign rdata_0_1 = {rdata_hi_1, rdata_lo_1}; // @[package.scala:45:27]
assign io_resp_1_0 = rdata_0_1; // @[package.scala:45:27]
wire [15:0] rdata_lo_lo_2 = _rockettile_dcache_data_arrays_0_RW0_rdata[143:128]; // @[package.scala:45:27]
wire [15:0] rdata_lo_hi_2 = _rockettile_dcache_data_arrays_0_RW0_rdata[159:144]; // @[package.scala:45:27]
wire [31:0] rdata_lo_2 = {rdata_lo_hi_2, rdata_lo_lo_2}; // @[package.scala:45:27]
wire [15:0] rdata_hi_lo_2 = _rockettile_dcache_data_arrays_0_RW0_rdata[175:160]; // @[package.scala:45:27]
wire [15:0] rdata_hi_hi_2 = _rockettile_dcache_data_arrays_0_RW0_rdata[191:176]; // @[package.scala:45:27]
wire [31:0] rdata_hi_2 = {rdata_hi_hi_2, rdata_hi_lo_2}; // @[package.scala:45:27]
assign rdata_0_2 = {rdata_hi_2, rdata_lo_2}; // @[package.scala:45:27]
assign io_resp_2_0 = rdata_0_2; // @[package.scala:45:27]
wire [15:0] rdata_lo_lo_3 = _rockettile_dcache_data_arrays_0_RW0_rdata[207:192]; // @[package.scala:45:27]
wire [15:0] rdata_lo_hi_3 = _rockettile_dcache_data_arrays_0_RW0_rdata[223:208]; // @[package.scala:45:27]
wire [31:0] rdata_lo_3 = {rdata_lo_hi_3, rdata_lo_lo_3}; // @[package.scala:45:27]
wire [15:0] rdata_hi_lo_3 = _rockettile_dcache_data_arrays_0_RW0_rdata[239:224]; // @[package.scala:45:27]
wire [15:0] rdata_hi_hi_3 = _rockettile_dcache_data_arrays_0_RW0_rdata[255:240]; // @[package.scala:45:27]
wire [31:0] rdata_hi_3 = {rdata_hi_hi_3, rdata_hi_lo_3}; // @[package.scala:45:27]
assign rdata_0_3 = {rdata_hi_3, rdata_lo_3}; // @[package.scala:45:27]
assign io_resp_3_0 = rdata_0_3; // @[package.scala:45:27]
wire [15:0] rdata_lo_lo_4 = _rockettile_dcache_data_arrays_0_RW0_rdata[271:256]; // @[package.scala:45:27]
wire [15:0] rdata_lo_hi_4 = _rockettile_dcache_data_arrays_0_RW0_rdata[287:272]; // @[package.scala:45:27]
wire [31:0] rdata_lo_4 = {rdata_lo_hi_4, rdata_lo_lo_4}; // @[package.scala:45:27]
wire [15:0] rdata_hi_lo_4 = _rockettile_dcache_data_arrays_0_RW0_rdata[303:288]; // @[package.scala:45:27]
wire [15:0] rdata_hi_hi_4 = _rockettile_dcache_data_arrays_0_RW0_rdata[319:304]; // @[package.scala:45:27]
wire [31:0] rdata_hi_4 = {rdata_hi_hi_4, rdata_hi_lo_4}; // @[package.scala:45:27]
assign rdata_0_4 = {rdata_hi_4, rdata_lo_4}; // @[package.scala:45:27]
assign io_resp_4_0 = rdata_0_4; // @[package.scala:45:27]
wire [15:0] rdata_lo_lo_5 = _rockettile_dcache_data_arrays_0_RW0_rdata[335:320]; // @[package.scala:45:27]
wire [15:0] rdata_lo_hi_5 = _rockettile_dcache_data_arrays_0_RW0_rdata[351:336]; // @[package.scala:45:27]
wire [31:0] rdata_lo_5 = {rdata_lo_hi_5, rdata_lo_lo_5}; // @[package.scala:45:27]
wire [15:0] rdata_hi_lo_5 = _rockettile_dcache_data_arrays_0_RW0_rdata[367:352]; // @[package.scala:45:27]
wire [15:0] rdata_hi_hi_5 = _rockettile_dcache_data_arrays_0_RW0_rdata[383:368]; // @[package.scala:45:27]
wire [31:0] rdata_hi_5 = {rdata_hi_hi_5, rdata_hi_lo_5}; // @[package.scala:45:27]
assign rdata_0_5 = {rdata_hi_5, rdata_lo_5}; // @[package.scala:45:27]
assign io_resp_5_0 = rdata_0_5; // @[package.scala:45:27]
wire [15:0] rdata_lo_lo_6 = _rockettile_dcache_data_arrays_0_RW0_rdata[399:384]; // @[package.scala:45:27]
wire [15:0] rdata_lo_hi_6 = _rockettile_dcache_data_arrays_0_RW0_rdata[415:400]; // @[package.scala:45:27]
wire [31:0] rdata_lo_6 = {rdata_lo_hi_6, rdata_lo_lo_6}; // @[package.scala:45:27]
wire [15:0] rdata_hi_lo_6 = _rockettile_dcache_data_arrays_0_RW0_rdata[431:416]; // @[package.scala:45:27]
wire [15:0] rdata_hi_hi_6 = _rockettile_dcache_data_arrays_0_RW0_rdata[447:432]; // @[package.scala:45:27]
wire [31:0] rdata_hi_6 = {rdata_hi_hi_6, rdata_hi_lo_6}; // @[package.scala:45:27]
assign rdata_0_6 = {rdata_hi_6, rdata_lo_6}; // @[package.scala:45:27]
assign io_resp_6_0 = rdata_0_6; // @[package.scala:45:27]
wire [15:0] rdata_lo_lo_7 = _rockettile_dcache_data_arrays_0_RW0_rdata[463:448]; // @[package.scala:45:27]
wire [15:0] rdata_lo_hi_7 = _rockettile_dcache_data_arrays_0_RW0_rdata[479:464]; // @[package.scala:45:27]
wire [31:0] rdata_lo_7 = {rdata_lo_hi_7, rdata_lo_lo_7}; // @[package.scala:45:27]
wire [15:0] rdata_hi_lo_7 = _rockettile_dcache_data_arrays_0_RW0_rdata[495:480]; // @[package.scala:45:27]
wire [15:0] rdata_hi_hi_7 = _rockettile_dcache_data_arrays_0_RW0_rdata[511:496]; // @[package.scala:45:27]
wire [31:0] rdata_hi_7 = {rdata_hi_hi_7, rdata_hi_lo_7}; // @[package.scala:45:27]
assign rdata_0_7 = {rdata_hi_7, rdata_lo_7}; // @[package.scala:45:27]
assign io_resp_7_0 = rdata_0_7; // @[package.scala:45:27]
rockettile_dcache_data_arrays_0_3 rockettile_dcache_data_arrays_0 ( // @[DescribedSRAM.scala:17:26]
.RW0_addr (_rdata_T ? addr : _rdata_data_WIRE), // @[DescribedSRAM.scala:17:26]
.RW0_en (_rdata_data_T_1 | _rdata_T), // @[DescribedSRAM.scala:17:26]
.RW0_clk (clock),
.RW0_wmode (io_req_bits_write_0), // @[DCache.scala:49:7]
.RW0_wdata ({_rdata_WIRE_63, _rdata_WIRE_62, _rdata_WIRE_61, _rdata_WIRE_60, _rdata_WIRE_59, _rdata_WIRE_58, _rdata_WIRE_57, _rdata_WIRE_56, _rdata_WIRE_55, _rdata_WIRE_54, _rdata_WIRE_53, _rdata_WIRE_52, _rdata_WIRE_51, _rdata_WIRE_50, _rdata_WIRE_49, _rdata_WIRE_48, _rdata_WIRE_47, _rdata_WIRE_46, _rdata_WIRE_45, _rdata_WIRE_44, _rdata_WIRE_43, _rdata_WIRE_42, _rdata_WIRE_41, _rdata_WIRE_40, _rdata_WIRE_39, _rdata_WIRE_38, _rdata_WIRE_37, _rdata_WIRE_36, _rdata_WIRE_35, _rdata_WIRE_34, _rdata_WIRE_33, _rdata_WIRE_32, _rdata_WIRE_31, _rdata_WIRE_30, _rdata_WIRE_29, _rdata_WIRE_28, _rdata_WIRE_27, _rdata_WIRE_26, _rdata_WIRE_25, _rdata_WIRE_24, _rdata_WIRE_23, _rdata_WIRE_22, _rdata_WIRE_21, _rdata_WIRE_20, _rdata_WIRE_19, _rdata_WIRE_18, _rdata_WIRE_17, _rdata_WIRE_16, _rdata_WIRE_15, _rdata_WIRE_14, _rdata_WIRE_13, _rdata_WIRE_12, _rdata_WIRE_11, _rdata_WIRE_10, _rdata_WIRE_9, _rdata_WIRE_8, _rdata_WIRE_7, _rdata_WIRE_6, _rdata_WIRE_5, _rdata_WIRE_4, _rdata_WIRE_3, _rdata_WIRE_2, _rdata_WIRE_1, _rdata_WIRE_0}), // @[DescribedSRAM.scala:17:26]
.RW0_rdata (_rockettile_dcache_data_arrays_0_RW0_rdata),
.RW0_wmask ({wMask_63, wMask_62, wMask_61, wMask_60, wMask_59, wMask_58, wMask_57, wMask_56, wMask_55, wMask_54, wMask_53, wMask_52, wMask_51, wMask_50, wMask_49, wMask_48, wMask_47, wMask_46, wMask_45, wMask_44, wMask_43, wMask_42, wMask_41, wMask_40, wMask_39, wMask_38, wMask_37, wMask_36, wMask_35, wMask_34, wMask_33, wMask_32, wMask_31, wMask_30, wMask_29, wMask_28, wMask_27, wMask_26, wMask_25, wMask_24, wMask_23, wMask_22, wMask_21, wMask_20, wMask_19, wMask_18, wMask_17, wMask_16, wMask_15, wMask_14, wMask_13, wMask_12, wMask_11, wMask_10, wMask_9, wMask_8, wMask_7, wMask_6, wMask_5, wMask_4, wMask_3, wMask_2, wMask_1, wMask_0}) // @[DescribedSRAM.scala:17:26]
); // @[DescribedSRAM.scala:17:26]
assign io_resp_0 = io_resp_0_0; // @[DCache.scala:49:7]
assign io_resp_1 = io_resp_1_0; // @[DCache.scala:49:7]
assign io_resp_2 = io_resp_2_0; // @[DCache.scala:49:7]
assign io_resp_3 = io_resp_3_0; // @[DCache.scala:49:7]
assign io_resp_4 = io_resp_4_0; // @[DCache.scala:49:7]
assign io_resp_5 = io_resp_5_0; // @[DCache.scala:49:7]
assign io_resp_6 = io_resp_6_0; // @[DCache.scala:49:7]
assign io_resp_7 = io_resp_7_0; // @[DCache.scala:49:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Tile_2 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_258
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_2( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_258 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLFragmenter_BootAddrReg :
input clock : Clock
input reset : Reset
output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn.d.bits.corrupt
invalidate anonIn.d.bits.data
invalidate anonIn.d.bits.denied
invalidate anonIn.d.bits.sink
invalidate anonIn.d.bits.source
invalidate anonIn.d.bits.size
invalidate anonIn.d.bits.param
invalidate anonIn.d.bits.opcode
invalidate anonIn.d.valid
invalidate anonIn.d.ready
invalidate anonIn.a.bits.corrupt
invalidate anonIn.a.bits.data
invalidate anonIn.a.bits.mask
invalidate anonIn.a.bits.address
invalidate anonIn.a.bits.source
invalidate anonIn.a.bits.size
invalidate anonIn.a.bits.param
invalidate anonIn.a.bits.opcode
invalidate anonIn.a.valid
invalidate anonIn.a.ready
inst monitor of TLMonitor_11
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, anonIn.d.bits.data
connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied
connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink
connect monitor.io.in.d.bits.source, anonIn.d.bits.source
connect monitor.io.in.d.bits.size, anonIn.d.bits.size
connect monitor.io.in.d.bits.param, anonIn.d.bits.param
connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode
connect monitor.io.in.d.valid, anonIn.d.valid
connect monitor.io.in.d.ready, anonIn.d.ready
connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, anonIn.a.bits.data
connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask
connect monitor.io.in.a.bits.address, anonIn.a.bits.address
connect monitor.io.in.a.bits.source, anonIn.a.bits.source
connect monitor.io.in.a.bits.size, anonIn.a.bits.size
connect monitor.io.in.a.bits.param, anonIn.a.bits.param
connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode
connect monitor.io.in.a.valid, anonIn.a.valid
connect monitor.io.in.a.ready, anonIn.a.ready
wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonOut.d.bits.corrupt
invalidate anonOut.d.bits.data
invalidate anonOut.d.bits.denied
invalidate anonOut.d.bits.sink
invalidate anonOut.d.bits.source
invalidate anonOut.d.bits.size
invalidate anonOut.d.bits.param
invalidate anonOut.d.bits.opcode
invalidate anonOut.d.valid
invalidate anonOut.d.ready
invalidate anonOut.a.bits.corrupt
invalidate anonOut.a.bits.data
invalidate anonOut.a.bits.mask
invalidate anonOut.a.bits.address
invalidate anonOut.a.bits.source
invalidate anonOut.a.bits.size
invalidate anonOut.a.bits.param
invalidate anonOut.a.bits.opcode
invalidate anonOut.a.valid
invalidate anonOut.a.ready
connect auto.anon_out, anonOut
connect anonIn, auto.anon_in
regreset acknum : UInt<3>, clock, reset, UInt<3>(0h0)
reg dOrig : UInt, clock
regreset dToggle : UInt<1>, clock, reset, UInt<1>(0h0)
node dFragnum = bits(anonOut.d.bits.source, 2, 0)
node dFirst = eq(acknum, UInt<1>(0h0))
node dLast = eq(dFragnum, UInt<1>(0h0))
node dsizeOH_shiftAmount = bits(anonOut.d.bits.size, 1, 0)
node _dsizeOH_T = dshl(UInt<1>(0h1), dsizeOH_shiftAmount)
node dsizeOH = bits(_dsizeOH_T, 3, 0)
node _dsizeOH1_T = dshl(UInt<3>(0h7), anonOut.d.bits.size)
node _dsizeOH1_T_1 = bits(_dsizeOH1_T, 2, 0)
node dsizeOH1 = not(_dsizeOH1_T_1)
node dHasData = bits(anonOut.d.bits.opcode, 0, 0)
node acknum_fragment = shl(dFragnum, 0)
node acknum_size = shr(dsizeOH1, 3)
node _T = eq(anonOut.d.valid, UInt<1>(0h0))
node _T_1 = and(acknum_fragment, acknum_size)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = or(_T, _T_2)
node _T_4 = asUInt(reset)
node _T_5 = eq(_T_4, UInt<1>(0h0))
when _T_5 :
node _T_6 = eq(_T_3, UInt<1>(0h0))
when _T_6 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:214 assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U)\n") : printf
assert(clock, _T_3, UInt<1>(0h1), "") : assert
node _dFirst_acknum_T = mux(dHasData, acknum_size, UInt<1>(0h0))
node dFirst_acknum = or(acknum_fragment, _dFirst_acknum_T)
node _ack_decrement_T = shr(dsizeOH, 3)
node ack_decrement = mux(dHasData, UInt<1>(0h1), _ack_decrement_T)
node _dFirst_size_T = shl(dFragnum, 3)
node _dFirst_size_T_1 = or(_dFirst_size_T, dsizeOH1)
node _dFirst_size_T_2 = shl(_dFirst_size_T_1, 1)
node _dFirst_size_T_3 = or(_dFirst_size_T_2, UInt<1>(0h1))
node _dFirst_size_T_4 = cat(UInt<1>(0h0), _dFirst_size_T_1)
node _dFirst_size_T_5 = not(_dFirst_size_T_4)
node _dFirst_size_T_6 = and(_dFirst_size_T_3, _dFirst_size_T_5)
node dFirst_size_hi = bits(_dFirst_size_T_6, 6, 4)
node dFirst_size_lo = bits(_dFirst_size_T_6, 3, 0)
node _dFirst_size_T_7 = orr(dFirst_size_hi)
node _dFirst_size_T_8 = or(dFirst_size_hi, dFirst_size_lo)
node dFirst_size_hi_1 = bits(_dFirst_size_T_8, 3, 2)
node dFirst_size_lo_1 = bits(_dFirst_size_T_8, 1, 0)
node _dFirst_size_T_9 = orr(dFirst_size_hi_1)
node _dFirst_size_T_10 = or(dFirst_size_hi_1, dFirst_size_lo_1)
node _dFirst_size_T_11 = bits(_dFirst_size_T_10, 1, 1)
node _dFirst_size_T_12 = cat(_dFirst_size_T_9, _dFirst_size_T_11)
node dFirst_size = cat(_dFirst_size_T_7, _dFirst_size_T_12)
node _T_7 = and(anonOut.d.ready, anonOut.d.valid)
when _T_7 :
node _acknum_T = sub(acknum, ack_decrement)
node _acknum_T_1 = tail(_acknum_T, 1)
node _acknum_T_2 = mux(dFirst, dFirst_acknum, _acknum_T_1)
connect acknum, _acknum_T_2
when dFirst :
connect dOrig, dFirst_size
node _dToggle_T = bits(anonOut.d.bits.source, 3, 3)
connect dToggle, _dToggle_T
node _drop_T = eq(dHasData, UInt<1>(0h0))
node _drop_T_1 = mux(UInt<1>(0h0), dFirst, dLast)
node _drop_T_2 = eq(_drop_T_1, UInt<1>(0h0))
node drop = and(_drop_T, _drop_T_2)
node _anonOut_d_ready_T = or(anonIn.d.ready, drop)
connect anonOut.d.ready, _anonOut_d_ready_T
node _anonIn_d_valid_T = eq(drop, UInt<1>(0h0))
node _anonIn_d_valid_T_1 = and(anonOut.d.valid, _anonIn_d_valid_T)
connect anonIn.d.valid, _anonIn_d_valid_T_1
connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt
connect anonIn.d.bits.data, anonOut.d.bits.data
connect anonIn.d.bits.denied, anonOut.d.bits.denied
connect anonIn.d.bits.sink, anonOut.d.bits.sink
connect anonIn.d.bits.source, anonOut.d.bits.source
connect anonIn.d.bits.size, anonOut.d.bits.size
connect anonIn.d.bits.param, anonOut.d.bits.param
connect anonIn.d.bits.opcode, anonOut.d.bits.opcode
node _anonIn_d_bits_source_T = shr(anonOut.d.bits.source, 4)
connect anonIn.d.bits.source, _anonIn_d_bits_source_T
node _anonIn_d_bits_size_T = mux(dFirst, dFirst_size, dOrig)
connect anonIn.d.bits.size, _anonIn_d_bits_size_T
inst repeater of Repeater_TLBundleA_a13d64s10k1z3u
connect repeater.clock, clock
connect repeater.reset, reset
connect repeater.io.enq, anonIn.a
node _find_T = xor(repeater.io.deq.bits.address, UInt<1>(0h0))
node _find_T_1 = cvt(_find_T)
node _find_T_2 = and(_find_T_1, asSInt(UInt<1>(0h0)))
node _find_T_3 = asSInt(_find_T_2)
node _find_T_4 = eq(_find_T_3, asSInt(UInt<1>(0h0)))
wire find : UInt<1>[1]
connect find[0], _find_T_4
node _limit_T = eq(UInt<1>(0h0), repeater.io.deq.bits.opcode)
node _limit_T_1 = mux(_limit_T, UInt<2>(0h3), UInt<2>(0h3))
node _limit_T_2 = eq(UInt<1>(0h1), repeater.io.deq.bits.opcode)
node _limit_T_3 = mux(_limit_T_2, UInt<2>(0h3), _limit_T_1)
node _limit_T_4 = eq(UInt<2>(0h2), repeater.io.deq.bits.opcode)
node _limit_T_5 = mux(_limit_T_4, UInt<2>(0h3), _limit_T_3)
node _limit_T_6 = eq(UInt<2>(0h3), repeater.io.deq.bits.opcode)
node _limit_T_7 = mux(_limit_T_6, UInt<2>(0h3), _limit_T_5)
node _limit_T_8 = eq(UInt<3>(0h4), repeater.io.deq.bits.opcode)
node _limit_T_9 = mux(_limit_T_8, UInt<2>(0h3), _limit_T_7)
node _limit_T_10 = eq(UInt<3>(0h5), repeater.io.deq.bits.opcode)
node limit = mux(_limit_T_10, UInt<2>(0h3), _limit_T_9)
node _aFrag_T = gt(repeater.io.deq.bits.size, limit)
node aFrag = mux(_aFrag_T, limit, repeater.io.deq.bits.size)
node _aOrigOH1_T = dshl(UInt<6>(0h3f), repeater.io.deq.bits.size)
node _aOrigOH1_T_1 = bits(_aOrigOH1_T, 5, 0)
node aOrigOH1 = not(_aOrigOH1_T_1)
node _aFragOH1_T = dshl(UInt<3>(0h7), aFrag)
node _aFragOH1_T_1 = bits(_aFragOH1_T, 2, 0)
node aFragOH1 = not(_aFragOH1_T_1)
node _aHasData_opdata_T = bits(repeater.io.deq.bits.opcode, 2, 2)
node aHasData = eq(_aHasData_opdata_T, UInt<1>(0h0))
node aMask = mux(aHasData, UInt<1>(0h0), aFragOH1)
regreset gennum : UInt<3>, clock, reset, UInt<3>(0h0)
node aFirst = eq(gennum, UInt<1>(0h0))
node _old_gennum1_T = shr(aOrigOH1, 3)
node _old_gennum1_T_1 = sub(gennum, UInt<1>(0h1))
node _old_gennum1_T_2 = tail(_old_gennum1_T_1, 1)
node old_gennum1 = mux(aFirst, _old_gennum1_T, _old_gennum1_T_2)
node _new_gennum_T = not(old_gennum1)
node _new_gennum_T_1 = shr(aMask, 3)
node _new_gennum_T_2 = or(_new_gennum_T, _new_gennum_T_1)
node new_gennum = not(_new_gennum_T_2)
node _aFragnum_T = shr(old_gennum1, 0)
node _aFragnum_T_1 = not(_aFragnum_T)
node _aFragnum_T_2 = shr(aFragOH1, 3)
node _aFragnum_T_3 = or(_aFragnum_T_1, _aFragnum_T_2)
node aFragnum = not(_aFragnum_T_3)
node aLast = eq(aFragnum, UInt<1>(0h0))
reg aToggle_r : UInt<1>, clock
when aFirst :
connect aToggle_r, dToggle
node _aToggle_T = mux(aFirst, dToggle, aToggle_r)
node aToggle = eq(_aToggle_T, UInt<1>(0h0))
node _T_8 = and(anonOut.a.ready, anonOut.a.valid)
when _T_8 :
connect gennum, new_gennum
node _repeater_io_repeat_T = eq(aHasData, UInt<1>(0h0))
node _repeater_io_repeat_T_1 = neq(aFragnum, UInt<1>(0h0))
node _repeater_io_repeat_T_2 = and(_repeater_io_repeat_T, _repeater_io_repeat_T_1)
connect repeater.io.repeat, _repeater_io_repeat_T_2
connect anonOut.a.bits, repeater.io.deq.bits
connect anonOut.a.valid, repeater.io.deq.valid
connect repeater.io.deq.ready, anonOut.a.ready
node _anonOut_a_bits_address_T = shl(old_gennum1, 3)
node _anonOut_a_bits_address_T_1 = not(aOrigOH1)
node _anonOut_a_bits_address_T_2 = or(_anonOut_a_bits_address_T, _anonOut_a_bits_address_T_1)
node _anonOut_a_bits_address_T_3 = or(_anonOut_a_bits_address_T_2, aFragOH1)
node _anonOut_a_bits_address_T_4 = or(_anonOut_a_bits_address_T_3, UInt<3>(0h7))
node _anonOut_a_bits_address_T_5 = not(_anonOut_a_bits_address_T_4)
node _anonOut_a_bits_address_T_6 = or(repeater.io.deq.bits.address, _anonOut_a_bits_address_T_5)
connect anonOut.a.bits.address, _anonOut_a_bits_address_T_6
node anonOut_a_bits_source_hi = cat(repeater.io.deq.bits.source, aToggle)
node _anonOut_a_bits_source_T = cat(anonOut_a_bits_source_hi, aFragnum)
connect anonOut.a.bits.source, _anonOut_a_bits_source_T
connect anonOut.a.bits.size, aFrag
node _T_9 = eq(repeater.io.full, UInt<1>(0h0))
node _T_10 = eq(aHasData, UInt<1>(0h0))
node _T_11 = or(_T_9, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:321 assert (!repeater.io.full || !aHasData)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
connect anonOut.a.bits.data, anonIn.a.bits.data
node _T_15 = eq(repeater.io.full, UInt<1>(0h0))
node _T_16 = eq(repeater.io.deq.bits.mask, UInt<8>(0hff))
node _T_17 = or(_T_15, _T_16)
node _T_18 = asUInt(reset)
node _T_19 = eq(_T_18, UInt<1>(0h0))
when _T_19 :
node _T_20 = eq(_T_17, UInt<1>(0h0))
when _T_20 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:324 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n") : printf_2
assert(clock, _T_17, UInt<1>(0h1), "") : assert_2
node _anonOut_a_bits_mask_T = mux(repeater.io.full, UInt<8>(0hff), anonIn.a.bits.mask)
connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T
wire anonOut_a_bits_user_out : { }
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<13>(0h0)
connect _WIRE.bits.source, UInt<10>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<13>(0h0)
connect _WIRE_2.bits.source, UInt<10>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<13>(0h0)
connect _WIRE_6.bits.source, UInt<14>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<13>(0h0)
connect _WIRE_8.bits.source, UInt<14>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_10.bits.sink, UInt<1>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0) | module TLFragmenter_BootAddrReg( // @[Fragmenter.scala:92:9]
input clock, // @[Fragmenter.scala:92:9]
input reset, // @[Fragmenter.scala:92:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [12:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [13:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [12:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [13:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire _repeater_io_full; // @[Fragmenter.scala:274:30]
wire _repeater_io_enq_ready; // @[Fragmenter.scala:274:30]
wire _repeater_io_deq_valid; // @[Fragmenter.scala:274:30]
wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30]
wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30]
wire [9:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30]
wire [12:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30]
wire [7:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30]
reg [2:0] acknum; // @[Fragmenter.scala:201:29]
reg [2:0] dOrig; // @[Fragmenter.scala:202:24]
reg dToggle; // @[Fragmenter.scala:203:30]
wire dFirst = acknum == 3'h0; // @[Fragmenter.scala:201:29, :205:29]
wire [5:0] _dsizeOH1_T = 6'h7 << auto_anon_out_d_bits_size; // @[package.scala:243:71]
wire [2:0] _GEN = ~(auto_anon_out_d_bits_source[2:0]); // @[package.scala:241:49]
wire [2:0] dFirst_size_hi = auto_anon_out_d_bits_source[2:0] & {1'h1, _GEN[2:1]}; // @[OneHot.scala:30:18]
wire [2:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi[2:1]} | ~(_dsizeOH1_T[2:0]) & {_GEN[0], _dsizeOH1_T[2:1]}; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [2:0] dFirst_size = {|dFirst_size_hi, |(_dFirst_size_T_8[2:1]), _dFirst_size_T_8[2] | _dFirst_size_T_8[0]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire drop = ~(auto_anon_out_d_bits_opcode[0]) & (|(auto_anon_out_d_bits_source[2:0])); // @[Fragmenter.scala:204:41, :206:30, :234:{20,30}]
wire anonOut_d_ready = auto_anon_in_d_ready | drop; // @[Fragmenter.scala:234:30, :235:35]
wire anonIn_d_valid = auto_anon_out_d_valid & ~drop; // @[Fragmenter.scala:234:30, :236:{36,39}]
wire [2:0] anonIn_d_bits_size = dFirst ? dFirst_size : dOrig; // @[OneHot.scala:32:10]
wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71]
reg [2:0] gennum; // @[Fragmenter.scala:303:29]
wire aFirst = gennum == 3'h0; // @[Fragmenter.scala:303:29, :304:29]
wire [2:0] aFragnum = aFirst ? ~(_aOrigOH1_T[5:3]) : gennum - 3'h1; // @[package.scala:243:{46,71,76}]
reg aToggle_r; // @[Fragmenter.scala:309:54] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_63 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE : UInt<1>[12]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
connect _source_ok_WIRE[7], _source_ok_T_27
connect _source_ok_WIRE[8], _source_ok_T_28
connect _source_ok_WIRE[9], _source_ok_T_29
connect _source_ok_WIRE[10], _source_ok_T_30
connect _source_ok_WIRE[11], _source_ok_T_31
node _source_ok_T_32 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[2])
node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[3])
node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[4])
node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[5])
node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[6])
node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[7])
node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[8])
node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[9])
node _source_ok_T_41 = or(_source_ok_T_40, _source_ok_WIRE[10])
node source_ok = or(_source_ok_T_41, _source_ok_WIRE[11])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_81 = eq(_T_80, UInt<1>(0h0))
node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_83 = cvt(_T_82)
node _T_84 = and(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = asSInt(_T_84)
node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = or(_T_81, _T_86)
node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_89 = eq(_T_88, UInt<1>(0h0))
node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<1>(0h0)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_89, _T_94)
node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_99 = cvt(_T_98)
node _T_100 = and(_T_99, asSInt(UInt<1>(0h0)))
node _T_101 = asSInt(_T_100)
node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = or(_T_97, _T_102)
node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_105 = eq(_T_104, UInt<1>(0h0))
node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_107 = cvt(_T_106)
node _T_108 = and(_T_107, asSInt(UInt<1>(0h0)))
node _T_109 = asSInt(_T_108)
node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = or(_T_105, _T_110)
node _T_112 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_113 = eq(_T_112, UInt<1>(0h0))
node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_115 = cvt(_T_114)
node _T_116 = and(_T_115, asSInt(UInt<1>(0h0)))
node _T_117 = asSInt(_T_116)
node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0)))
node _T_119 = or(_T_113, _T_118)
node _T_120 = and(_T_11, _T_24)
node _T_121 = and(_T_120, _T_37)
node _T_122 = and(_T_121, _T_50)
node _T_123 = and(_T_122, _T_63)
node _T_124 = and(_T_123, _T_71)
node _T_125 = and(_T_124, _T_79)
node _T_126 = and(_T_125, _T_87)
node _T_127 = and(_T_126, _T_95)
node _T_128 = and(_T_127, _T_103)
node _T_129 = and(_T_128, _T_111)
node _T_130 = and(_T_129, _T_119)
node _T_131 = asUInt(reset)
node _T_132 = eq(_T_131, UInt<1>(0h0))
when _T_132 :
node _T_133 = eq(_T_130, UInt<1>(0h0))
when _T_133 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_130, UInt<1>(0h1), "") : assert_1
node _T_134 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_134 :
node _T_135 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_136 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_137 = and(_T_135, _T_136)
node _T_138 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_139 = shr(io.in.a.bits.source, 2)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_142 = and(_T_140, _T_141)
node _T_143 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_144 = and(_T_142, _T_143)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_145 = shr(io.in.a.bits.source, 2)
node _T_146 = eq(_T_145, UInt<1>(0h1))
node _T_147 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_148 = and(_T_146, _T_147)
node _T_149 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_150 = and(_T_148, _T_149)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_151 = shr(io.in.a.bits.source, 2)
node _T_152 = eq(_T_151, UInt<2>(0h2))
node _T_153 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_154 = and(_T_152, _T_153)
node _T_155 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_156 = and(_T_154, _T_155)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_157 = shr(io.in.a.bits.source, 2)
node _T_158 = eq(_T_157, UInt<2>(0h3))
node _T_159 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_160 = and(_T_158, _T_159)
node _T_161 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_162 = and(_T_160, _T_161)
node _T_163 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_164 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_165 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_166 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_167 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_169 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_170 = or(_T_138, _T_144)
node _T_171 = or(_T_170, _T_150)
node _T_172 = or(_T_171, _T_156)
node _T_173 = or(_T_172, _T_162)
node _T_174 = or(_T_173, _T_163)
node _T_175 = or(_T_174, _T_164)
node _T_176 = or(_T_175, _T_165)
node _T_177 = or(_T_176, _T_166)
node _T_178 = or(_T_177, _T_167)
node _T_179 = or(_T_178, _T_168)
node _T_180 = or(_T_179, _T_169)
node _T_181 = and(_T_137, _T_180)
node _T_182 = or(UInt<1>(0h0), _T_181)
node _T_183 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_184 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_185 = cvt(_T_184)
node _T_186 = and(_T_185, asSInt(UInt<13>(0h1000)))
node _T_187 = asSInt(_T_186)
node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0)))
node _T_189 = and(_T_183, _T_188)
node _T_190 = or(UInt<1>(0h0), _T_189)
node _T_191 = and(_T_182, _T_190)
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_191, UInt<1>(0h1), "") : assert_2
node _T_195 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_196 = shr(io.in.a.bits.source, 2)
node _T_197 = eq(_T_196, UInt<1>(0h0))
node _T_198 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_199 = and(_T_197, _T_198)
node _T_200 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_201 = and(_T_199, _T_200)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_202 = shr(io.in.a.bits.source, 2)
node _T_203 = eq(_T_202, UInt<1>(0h1))
node _T_204 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_205 = and(_T_203, _T_204)
node _T_206 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_207 = and(_T_205, _T_206)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_208 = shr(io.in.a.bits.source, 2)
node _T_209 = eq(_T_208, UInt<2>(0h2))
node _T_210 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_211 = and(_T_209, _T_210)
node _T_212 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_213 = and(_T_211, _T_212)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_214 = shr(io.in.a.bits.source, 2)
node _T_215 = eq(_T_214, UInt<2>(0h3))
node _T_216 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_217 = and(_T_215, _T_216)
node _T_218 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_219 = and(_T_217, _T_218)
node _T_220 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_221 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_222 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_223 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_225 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_226 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE : UInt<1>[12]
connect _WIRE[0], _T_195
connect _WIRE[1], _T_201
connect _WIRE[2], _T_207
connect _WIRE[3], _T_213
connect _WIRE[4], _T_219
connect _WIRE[5], _T_220
connect _WIRE[6], _T_221
connect _WIRE[7], _T_222
connect _WIRE[8], _T_223
connect _WIRE[9], _T_224
connect _WIRE[10], _T_225
connect _WIRE[11], _T_226
node _T_227 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_228 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_229 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_230 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_231 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_232 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_233 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_234 = mux(_WIRE[5], _T_227, UInt<1>(0h0))
node _T_235 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_236 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_237 = mux(_WIRE[8], _T_228, UInt<1>(0h0))
node _T_238 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_239 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_240 = mux(_WIRE[11], UInt<1>(0h0), UInt<1>(0h0))
node _T_241 = or(_T_229, _T_230)
node _T_242 = or(_T_241, _T_231)
node _T_243 = or(_T_242, _T_232)
node _T_244 = or(_T_243, _T_233)
node _T_245 = or(_T_244, _T_234)
node _T_246 = or(_T_245, _T_235)
node _T_247 = or(_T_246, _T_236)
node _T_248 = or(_T_247, _T_237)
node _T_249 = or(_T_248, _T_238)
node _T_250 = or(_T_249, _T_239)
node _T_251 = or(_T_250, _T_240)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_251
node _T_252 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_253 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_254 = and(_T_252, _T_253)
node _T_255 = or(UInt<1>(0h0), _T_254)
node _T_256 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_257 = cvt(_T_256)
node _T_258 = and(_T_257, asSInt(UInt<13>(0h1000)))
node _T_259 = asSInt(_T_258)
node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0)))
node _T_261 = and(_T_255, _T_260)
node _T_262 = or(UInt<1>(0h0), _T_261)
node _T_263 = and(_WIRE_1, _T_262)
node _T_264 = asUInt(reset)
node _T_265 = eq(_T_264, UInt<1>(0h0))
when _T_265 :
node _T_266 = eq(_T_263, UInt<1>(0h0))
when _T_266 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_263, UInt<1>(0h1), "") : assert_3
node _T_267 = asUInt(reset)
node _T_268 = eq(_T_267, UInt<1>(0h0))
when _T_268 :
node _T_269 = eq(source_ok, UInt<1>(0h0))
when _T_269 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_270 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_271 = asUInt(reset)
node _T_272 = eq(_T_271, UInt<1>(0h0))
when _T_272 :
node _T_273 = eq(_T_270, UInt<1>(0h0))
when _T_273 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_270, UInt<1>(0h1), "") : assert_5
node _T_274 = asUInt(reset)
node _T_275 = eq(_T_274, UInt<1>(0h0))
when _T_275 :
node _T_276 = eq(is_aligned, UInt<1>(0h0))
when _T_276 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_277 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_278 = asUInt(reset)
node _T_279 = eq(_T_278, UInt<1>(0h0))
when _T_279 :
node _T_280 = eq(_T_277, UInt<1>(0h0))
when _T_280 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_277, UInt<1>(0h1), "") : assert_7
node _T_281 = not(io.in.a.bits.mask)
node _T_282 = eq(_T_281, UInt<1>(0h0))
node _T_283 = asUInt(reset)
node _T_284 = eq(_T_283, UInt<1>(0h0))
when _T_284 :
node _T_285 = eq(_T_282, UInt<1>(0h0))
when _T_285 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_282, UInt<1>(0h1), "") : assert_8
node _T_286 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_287 = asUInt(reset)
node _T_288 = eq(_T_287, UInt<1>(0h0))
when _T_288 :
node _T_289 = eq(_T_286, UInt<1>(0h0))
when _T_289 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_286, UInt<1>(0h1), "") : assert_9
node _T_290 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_290 :
node _T_291 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_292 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_293 = and(_T_291, _T_292)
node _T_294 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_295 = shr(io.in.a.bits.source, 2)
node _T_296 = eq(_T_295, UInt<1>(0h0))
node _T_297 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_298 = and(_T_296, _T_297)
node _T_299 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_300 = and(_T_298, _T_299)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_301 = shr(io.in.a.bits.source, 2)
node _T_302 = eq(_T_301, UInt<1>(0h1))
node _T_303 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_304 = and(_T_302, _T_303)
node _T_305 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_306 = and(_T_304, _T_305)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_307 = shr(io.in.a.bits.source, 2)
node _T_308 = eq(_T_307, UInt<2>(0h2))
node _T_309 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_310 = and(_T_308, _T_309)
node _T_311 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_312 = and(_T_310, _T_311)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_313 = shr(io.in.a.bits.source, 2)
node _T_314 = eq(_T_313, UInt<2>(0h3))
node _T_315 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_316 = and(_T_314, _T_315)
node _T_317 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_318 = and(_T_316, _T_317)
node _T_319 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_320 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_321 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_322 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_323 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_324 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_325 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_326 = or(_T_294, _T_300)
node _T_327 = or(_T_326, _T_306)
node _T_328 = or(_T_327, _T_312)
node _T_329 = or(_T_328, _T_318)
node _T_330 = or(_T_329, _T_319)
node _T_331 = or(_T_330, _T_320)
node _T_332 = or(_T_331, _T_321)
node _T_333 = or(_T_332, _T_322)
node _T_334 = or(_T_333, _T_323)
node _T_335 = or(_T_334, _T_324)
node _T_336 = or(_T_335, _T_325)
node _T_337 = and(_T_293, _T_336)
node _T_338 = or(UInt<1>(0h0), _T_337)
node _T_339 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_340 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_341 = cvt(_T_340)
node _T_342 = and(_T_341, asSInt(UInt<13>(0h1000)))
node _T_343 = asSInt(_T_342)
node _T_344 = eq(_T_343, asSInt(UInt<1>(0h0)))
node _T_345 = and(_T_339, _T_344)
node _T_346 = or(UInt<1>(0h0), _T_345)
node _T_347 = and(_T_338, _T_346)
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_347, UInt<1>(0h1), "") : assert_10
node _T_351 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_352 = shr(io.in.a.bits.source, 2)
node _T_353 = eq(_T_352, UInt<1>(0h0))
node _T_354 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_355 = and(_T_353, _T_354)
node _T_356 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_357 = and(_T_355, _T_356)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_358 = shr(io.in.a.bits.source, 2)
node _T_359 = eq(_T_358, UInt<1>(0h1))
node _T_360 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_361 = and(_T_359, _T_360)
node _T_362 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_363 = and(_T_361, _T_362)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_364 = shr(io.in.a.bits.source, 2)
node _T_365 = eq(_T_364, UInt<2>(0h2))
node _T_366 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_367 = and(_T_365, _T_366)
node _T_368 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_369 = and(_T_367, _T_368)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_370 = shr(io.in.a.bits.source, 2)
node _T_371 = eq(_T_370, UInt<2>(0h3))
node _T_372 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_373 = and(_T_371, _T_372)
node _T_374 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_375 = and(_T_373, _T_374)
node _T_376 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_377 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_378 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_379 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_380 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_381 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_382 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE_2 : UInt<1>[12]
connect _WIRE_2[0], _T_351
connect _WIRE_2[1], _T_357
connect _WIRE_2[2], _T_363
connect _WIRE_2[3], _T_369
connect _WIRE_2[4], _T_375
connect _WIRE_2[5], _T_376
connect _WIRE_2[6], _T_377
connect _WIRE_2[7], _T_378
connect _WIRE_2[8], _T_379
connect _WIRE_2[9], _T_380
connect _WIRE_2[10], _T_381
connect _WIRE_2[11], _T_382
node _T_383 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_384 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_385 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_386 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_387 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_388 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_389 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_390 = mux(_WIRE_2[5], _T_383, UInt<1>(0h0))
node _T_391 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_392 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_393 = mux(_WIRE_2[8], _T_384, UInt<1>(0h0))
node _T_394 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_395 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_396 = mux(_WIRE_2[11], UInt<1>(0h0), UInt<1>(0h0))
node _T_397 = or(_T_385, _T_386)
node _T_398 = or(_T_397, _T_387)
node _T_399 = or(_T_398, _T_388)
node _T_400 = or(_T_399, _T_389)
node _T_401 = or(_T_400, _T_390)
node _T_402 = or(_T_401, _T_391)
node _T_403 = or(_T_402, _T_392)
node _T_404 = or(_T_403, _T_393)
node _T_405 = or(_T_404, _T_394)
node _T_406 = or(_T_405, _T_395)
node _T_407 = or(_T_406, _T_396)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_407
node _T_408 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_409 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_410 = and(_T_408, _T_409)
node _T_411 = or(UInt<1>(0h0), _T_410)
node _T_412 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_413 = cvt(_T_412)
node _T_414 = and(_T_413, asSInt(UInt<13>(0h1000)))
node _T_415 = asSInt(_T_414)
node _T_416 = eq(_T_415, asSInt(UInt<1>(0h0)))
node _T_417 = and(_T_411, _T_416)
node _T_418 = or(UInt<1>(0h0), _T_417)
node _T_419 = and(_WIRE_3, _T_418)
node _T_420 = asUInt(reset)
node _T_421 = eq(_T_420, UInt<1>(0h0))
when _T_421 :
node _T_422 = eq(_T_419, UInt<1>(0h0))
when _T_422 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_419, UInt<1>(0h1), "") : assert_11
node _T_423 = asUInt(reset)
node _T_424 = eq(_T_423, UInt<1>(0h0))
when _T_424 :
node _T_425 = eq(source_ok, UInt<1>(0h0))
when _T_425 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_426 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_427 = asUInt(reset)
node _T_428 = eq(_T_427, UInt<1>(0h0))
when _T_428 :
node _T_429 = eq(_T_426, UInt<1>(0h0))
when _T_429 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_426, UInt<1>(0h1), "") : assert_13
node _T_430 = asUInt(reset)
node _T_431 = eq(_T_430, UInt<1>(0h0))
when _T_431 :
node _T_432 = eq(is_aligned, UInt<1>(0h0))
when _T_432 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_433 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_434 = asUInt(reset)
node _T_435 = eq(_T_434, UInt<1>(0h0))
when _T_435 :
node _T_436 = eq(_T_433, UInt<1>(0h0))
when _T_436 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_433, UInt<1>(0h1), "") : assert_15
node _T_437 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_438 = asUInt(reset)
node _T_439 = eq(_T_438, UInt<1>(0h0))
when _T_439 :
node _T_440 = eq(_T_437, UInt<1>(0h0))
when _T_440 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_437, UInt<1>(0h1), "") : assert_16
node _T_441 = not(io.in.a.bits.mask)
node _T_442 = eq(_T_441, UInt<1>(0h0))
node _T_443 = asUInt(reset)
node _T_444 = eq(_T_443, UInt<1>(0h0))
when _T_444 :
node _T_445 = eq(_T_442, UInt<1>(0h0))
when _T_445 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_442, UInt<1>(0h1), "") : assert_17
node _T_446 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_447 = asUInt(reset)
node _T_448 = eq(_T_447, UInt<1>(0h0))
when _T_448 :
node _T_449 = eq(_T_446, UInt<1>(0h0))
when _T_449 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_446, UInt<1>(0h1), "") : assert_18
node _T_450 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_450 :
node _T_451 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_452 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_453 = and(_T_451, _T_452)
node _T_454 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_455 = shr(io.in.a.bits.source, 2)
node _T_456 = eq(_T_455, UInt<1>(0h0))
node _T_457 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_458 = and(_T_456, _T_457)
node _T_459 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_460 = and(_T_458, _T_459)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_461 = shr(io.in.a.bits.source, 2)
node _T_462 = eq(_T_461, UInt<1>(0h1))
node _T_463 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_464 = and(_T_462, _T_463)
node _T_465 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_466 = and(_T_464, _T_465)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_467 = shr(io.in.a.bits.source, 2)
node _T_468 = eq(_T_467, UInt<2>(0h2))
node _T_469 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_470 = and(_T_468, _T_469)
node _T_471 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_472 = and(_T_470, _T_471)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_473 = shr(io.in.a.bits.source, 2)
node _T_474 = eq(_T_473, UInt<2>(0h3))
node _T_475 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_476 = and(_T_474, _T_475)
node _T_477 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_478 = and(_T_476, _T_477)
node _T_479 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_480 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_481 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_482 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_483 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_484 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_485 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_486 = or(_T_454, _T_460)
node _T_487 = or(_T_486, _T_466)
node _T_488 = or(_T_487, _T_472)
node _T_489 = or(_T_488, _T_478)
node _T_490 = or(_T_489, _T_479)
node _T_491 = or(_T_490, _T_480)
node _T_492 = or(_T_491, _T_481)
node _T_493 = or(_T_492, _T_482)
node _T_494 = or(_T_493, _T_483)
node _T_495 = or(_T_494, _T_484)
node _T_496 = or(_T_495, _T_485)
node _T_497 = and(_T_453, _T_496)
node _T_498 = or(UInt<1>(0h0), _T_497)
node _T_499 = asUInt(reset)
node _T_500 = eq(_T_499, UInt<1>(0h0))
when _T_500 :
node _T_501 = eq(_T_498, UInt<1>(0h0))
when _T_501 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_498, UInt<1>(0h1), "") : assert_19
node _T_502 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_503 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_504 = and(_T_502, _T_503)
node _T_505 = or(UInt<1>(0h0), _T_504)
node _T_506 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_507 = cvt(_T_506)
node _T_508 = and(_T_507, asSInt(UInt<13>(0h1000)))
node _T_509 = asSInt(_T_508)
node _T_510 = eq(_T_509, asSInt(UInt<1>(0h0)))
node _T_511 = and(_T_505, _T_510)
node _T_512 = or(UInt<1>(0h0), _T_511)
node _T_513 = asUInt(reset)
node _T_514 = eq(_T_513, UInt<1>(0h0))
when _T_514 :
node _T_515 = eq(_T_512, UInt<1>(0h0))
when _T_515 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_512, UInt<1>(0h1), "") : assert_20
node _T_516 = asUInt(reset)
node _T_517 = eq(_T_516, UInt<1>(0h0))
when _T_517 :
node _T_518 = eq(source_ok, UInt<1>(0h0))
when _T_518 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_519 = asUInt(reset)
node _T_520 = eq(_T_519, UInt<1>(0h0))
when _T_520 :
node _T_521 = eq(is_aligned, UInt<1>(0h0))
when _T_521 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_522 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_523 = asUInt(reset)
node _T_524 = eq(_T_523, UInt<1>(0h0))
when _T_524 :
node _T_525 = eq(_T_522, UInt<1>(0h0))
when _T_525 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_522, UInt<1>(0h1), "") : assert_23
node _T_526 = eq(io.in.a.bits.mask, mask)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_526, UInt<1>(0h1), "") : assert_24
node _T_530 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_530, UInt<1>(0h1), "") : assert_25
node _T_534 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_534 :
node _T_535 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_536 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_537 = and(_T_535, _T_536)
node _T_538 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_539 = shr(io.in.a.bits.source, 2)
node _T_540 = eq(_T_539, UInt<1>(0h0))
node _T_541 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_542 = and(_T_540, _T_541)
node _T_543 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_544 = and(_T_542, _T_543)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_545 = shr(io.in.a.bits.source, 2)
node _T_546 = eq(_T_545, UInt<1>(0h1))
node _T_547 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_548 = and(_T_546, _T_547)
node _T_549 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_550 = and(_T_548, _T_549)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_551 = shr(io.in.a.bits.source, 2)
node _T_552 = eq(_T_551, UInt<2>(0h2))
node _T_553 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_554 = and(_T_552, _T_553)
node _T_555 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_556 = and(_T_554, _T_555)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_557 = shr(io.in.a.bits.source, 2)
node _T_558 = eq(_T_557, UInt<2>(0h3))
node _T_559 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_560 = and(_T_558, _T_559)
node _T_561 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_562 = and(_T_560, _T_561)
node _T_563 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_564 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_565 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_566 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_567 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_568 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_569 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_570 = or(_T_538, _T_544)
node _T_571 = or(_T_570, _T_550)
node _T_572 = or(_T_571, _T_556)
node _T_573 = or(_T_572, _T_562)
node _T_574 = or(_T_573, _T_563)
node _T_575 = or(_T_574, _T_564)
node _T_576 = or(_T_575, _T_565)
node _T_577 = or(_T_576, _T_566)
node _T_578 = or(_T_577, _T_567)
node _T_579 = or(_T_578, _T_568)
node _T_580 = or(_T_579, _T_569)
node _T_581 = and(_T_537, _T_580)
node _T_582 = or(UInt<1>(0h0), _T_581)
node _T_583 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_584 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_585 = and(_T_583, _T_584)
node _T_586 = or(UInt<1>(0h0), _T_585)
node _T_587 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_588 = cvt(_T_587)
node _T_589 = and(_T_588, asSInt(UInt<13>(0h1000)))
node _T_590 = asSInt(_T_589)
node _T_591 = eq(_T_590, asSInt(UInt<1>(0h0)))
node _T_592 = and(_T_586, _T_591)
node _T_593 = or(UInt<1>(0h0), _T_592)
node _T_594 = and(_T_582, _T_593)
node _T_595 = asUInt(reset)
node _T_596 = eq(_T_595, UInt<1>(0h0))
when _T_596 :
node _T_597 = eq(_T_594, UInt<1>(0h0))
when _T_597 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_594, UInt<1>(0h1), "") : assert_26
node _T_598 = asUInt(reset)
node _T_599 = eq(_T_598, UInt<1>(0h0))
when _T_599 :
node _T_600 = eq(source_ok, UInt<1>(0h0))
when _T_600 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_601 = asUInt(reset)
node _T_602 = eq(_T_601, UInt<1>(0h0))
when _T_602 :
node _T_603 = eq(is_aligned, UInt<1>(0h0))
when _T_603 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_604 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_605 = asUInt(reset)
node _T_606 = eq(_T_605, UInt<1>(0h0))
when _T_606 :
node _T_607 = eq(_T_604, UInt<1>(0h0))
when _T_607 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_604, UInt<1>(0h1), "") : assert_29
node _T_608 = eq(io.in.a.bits.mask, mask)
node _T_609 = asUInt(reset)
node _T_610 = eq(_T_609, UInt<1>(0h0))
when _T_610 :
node _T_611 = eq(_T_608, UInt<1>(0h0))
when _T_611 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_608, UInt<1>(0h1), "") : assert_30
node _T_612 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_612 :
node _T_613 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_614 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_615 = and(_T_613, _T_614)
node _T_616 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_617 = shr(io.in.a.bits.source, 2)
node _T_618 = eq(_T_617, UInt<1>(0h0))
node _T_619 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_620 = and(_T_618, _T_619)
node _T_621 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_622 = and(_T_620, _T_621)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_623 = shr(io.in.a.bits.source, 2)
node _T_624 = eq(_T_623, UInt<1>(0h1))
node _T_625 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_626 = and(_T_624, _T_625)
node _T_627 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_628 = and(_T_626, _T_627)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_629 = shr(io.in.a.bits.source, 2)
node _T_630 = eq(_T_629, UInt<2>(0h2))
node _T_631 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_632 = and(_T_630, _T_631)
node _T_633 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_634 = and(_T_632, _T_633)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_635 = shr(io.in.a.bits.source, 2)
node _T_636 = eq(_T_635, UInt<2>(0h3))
node _T_637 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_638 = and(_T_636, _T_637)
node _T_639 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_640 = and(_T_638, _T_639)
node _T_641 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_642 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_643 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_644 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_645 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_646 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_647 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_648 = or(_T_616, _T_622)
node _T_649 = or(_T_648, _T_628)
node _T_650 = or(_T_649, _T_634)
node _T_651 = or(_T_650, _T_640)
node _T_652 = or(_T_651, _T_641)
node _T_653 = or(_T_652, _T_642)
node _T_654 = or(_T_653, _T_643)
node _T_655 = or(_T_654, _T_644)
node _T_656 = or(_T_655, _T_645)
node _T_657 = or(_T_656, _T_646)
node _T_658 = or(_T_657, _T_647)
node _T_659 = and(_T_615, _T_658)
node _T_660 = or(UInt<1>(0h0), _T_659)
node _T_661 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_662 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_663 = and(_T_661, _T_662)
node _T_664 = or(UInt<1>(0h0), _T_663)
node _T_665 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_666 = cvt(_T_665)
node _T_667 = and(_T_666, asSInt(UInt<13>(0h1000)))
node _T_668 = asSInt(_T_667)
node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0)))
node _T_670 = and(_T_664, _T_669)
node _T_671 = or(UInt<1>(0h0), _T_670)
node _T_672 = and(_T_660, _T_671)
node _T_673 = asUInt(reset)
node _T_674 = eq(_T_673, UInt<1>(0h0))
when _T_674 :
node _T_675 = eq(_T_672, UInt<1>(0h0))
when _T_675 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_672, UInt<1>(0h1), "") : assert_31
node _T_676 = asUInt(reset)
node _T_677 = eq(_T_676, UInt<1>(0h0))
when _T_677 :
node _T_678 = eq(source_ok, UInt<1>(0h0))
when _T_678 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_679 = asUInt(reset)
node _T_680 = eq(_T_679, UInt<1>(0h0))
when _T_680 :
node _T_681 = eq(is_aligned, UInt<1>(0h0))
when _T_681 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_682 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_683 = asUInt(reset)
node _T_684 = eq(_T_683, UInt<1>(0h0))
when _T_684 :
node _T_685 = eq(_T_682, UInt<1>(0h0))
when _T_685 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_682, UInt<1>(0h1), "") : assert_34
node _T_686 = not(mask)
node _T_687 = and(io.in.a.bits.mask, _T_686)
node _T_688 = eq(_T_687, UInt<1>(0h0))
node _T_689 = asUInt(reset)
node _T_690 = eq(_T_689, UInt<1>(0h0))
when _T_690 :
node _T_691 = eq(_T_688, UInt<1>(0h0))
when _T_691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_688, UInt<1>(0h1), "") : assert_35
node _T_692 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_692 :
node _T_693 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_694 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_695 = and(_T_693, _T_694)
node _T_696 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_697 = shr(io.in.a.bits.source, 2)
node _T_698 = eq(_T_697, UInt<1>(0h0))
node _T_699 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_700 = and(_T_698, _T_699)
node _T_701 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_702 = and(_T_700, _T_701)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_703 = shr(io.in.a.bits.source, 2)
node _T_704 = eq(_T_703, UInt<1>(0h1))
node _T_705 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_706 = and(_T_704, _T_705)
node _T_707 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_708 = and(_T_706, _T_707)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_709 = shr(io.in.a.bits.source, 2)
node _T_710 = eq(_T_709, UInt<2>(0h2))
node _T_711 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_712 = and(_T_710, _T_711)
node _T_713 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_714 = and(_T_712, _T_713)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_715 = shr(io.in.a.bits.source, 2)
node _T_716 = eq(_T_715, UInt<2>(0h3))
node _T_717 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_718 = and(_T_716, _T_717)
node _T_719 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_720 = and(_T_718, _T_719)
node _T_721 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_722 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_723 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_724 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_725 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_726 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_727 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_728 = or(_T_696, _T_702)
node _T_729 = or(_T_728, _T_708)
node _T_730 = or(_T_729, _T_714)
node _T_731 = or(_T_730, _T_720)
node _T_732 = or(_T_731, _T_721)
node _T_733 = or(_T_732, _T_722)
node _T_734 = or(_T_733, _T_723)
node _T_735 = or(_T_734, _T_724)
node _T_736 = or(_T_735, _T_725)
node _T_737 = or(_T_736, _T_726)
node _T_738 = or(_T_737, _T_727)
node _T_739 = and(_T_695, _T_738)
node _T_740 = or(UInt<1>(0h0), _T_739)
node _T_741 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_742 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_743 = cvt(_T_742)
node _T_744 = and(_T_743, asSInt(UInt<13>(0h1000)))
node _T_745 = asSInt(_T_744)
node _T_746 = eq(_T_745, asSInt(UInt<1>(0h0)))
node _T_747 = and(_T_741, _T_746)
node _T_748 = or(UInt<1>(0h0), _T_747)
node _T_749 = and(_T_740, _T_748)
node _T_750 = asUInt(reset)
node _T_751 = eq(_T_750, UInt<1>(0h0))
when _T_751 :
node _T_752 = eq(_T_749, UInt<1>(0h0))
when _T_752 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_749, UInt<1>(0h1), "") : assert_36
node _T_753 = asUInt(reset)
node _T_754 = eq(_T_753, UInt<1>(0h0))
when _T_754 :
node _T_755 = eq(source_ok, UInt<1>(0h0))
when _T_755 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_756 = asUInt(reset)
node _T_757 = eq(_T_756, UInt<1>(0h0))
when _T_757 :
node _T_758 = eq(is_aligned, UInt<1>(0h0))
when _T_758 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_759 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_760 = asUInt(reset)
node _T_761 = eq(_T_760, UInt<1>(0h0))
when _T_761 :
node _T_762 = eq(_T_759, UInt<1>(0h0))
when _T_762 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_759, UInt<1>(0h1), "") : assert_39
node _T_763 = eq(io.in.a.bits.mask, mask)
node _T_764 = asUInt(reset)
node _T_765 = eq(_T_764, UInt<1>(0h0))
when _T_765 :
node _T_766 = eq(_T_763, UInt<1>(0h0))
when _T_766 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_763, UInt<1>(0h1), "") : assert_40
node _T_767 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_767 :
node _T_768 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_769 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_770 = and(_T_768, _T_769)
node _T_771 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_772 = shr(io.in.a.bits.source, 2)
node _T_773 = eq(_T_772, UInt<1>(0h0))
node _T_774 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_775 = and(_T_773, _T_774)
node _T_776 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_777 = and(_T_775, _T_776)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_778 = shr(io.in.a.bits.source, 2)
node _T_779 = eq(_T_778, UInt<1>(0h1))
node _T_780 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_781 = and(_T_779, _T_780)
node _T_782 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_783 = and(_T_781, _T_782)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_784 = shr(io.in.a.bits.source, 2)
node _T_785 = eq(_T_784, UInt<2>(0h2))
node _T_786 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_787 = and(_T_785, _T_786)
node _T_788 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_789 = and(_T_787, _T_788)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_790 = shr(io.in.a.bits.source, 2)
node _T_791 = eq(_T_790, UInt<2>(0h3))
node _T_792 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_793 = and(_T_791, _T_792)
node _T_794 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_795 = and(_T_793, _T_794)
node _T_796 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_797 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_798 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_799 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_800 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_801 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_802 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_803 = or(_T_771, _T_777)
node _T_804 = or(_T_803, _T_783)
node _T_805 = or(_T_804, _T_789)
node _T_806 = or(_T_805, _T_795)
node _T_807 = or(_T_806, _T_796)
node _T_808 = or(_T_807, _T_797)
node _T_809 = or(_T_808, _T_798)
node _T_810 = or(_T_809, _T_799)
node _T_811 = or(_T_810, _T_800)
node _T_812 = or(_T_811, _T_801)
node _T_813 = or(_T_812, _T_802)
node _T_814 = and(_T_770, _T_813)
node _T_815 = or(UInt<1>(0h0), _T_814)
node _T_816 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_817 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_818 = cvt(_T_817)
node _T_819 = and(_T_818, asSInt(UInt<13>(0h1000)))
node _T_820 = asSInt(_T_819)
node _T_821 = eq(_T_820, asSInt(UInt<1>(0h0)))
node _T_822 = and(_T_816, _T_821)
node _T_823 = or(UInt<1>(0h0), _T_822)
node _T_824 = and(_T_815, _T_823)
node _T_825 = asUInt(reset)
node _T_826 = eq(_T_825, UInt<1>(0h0))
when _T_826 :
node _T_827 = eq(_T_824, UInt<1>(0h0))
when _T_827 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_824, UInt<1>(0h1), "") : assert_41
node _T_828 = asUInt(reset)
node _T_829 = eq(_T_828, UInt<1>(0h0))
when _T_829 :
node _T_830 = eq(source_ok, UInt<1>(0h0))
when _T_830 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_831 = asUInt(reset)
node _T_832 = eq(_T_831, UInt<1>(0h0))
when _T_832 :
node _T_833 = eq(is_aligned, UInt<1>(0h0))
when _T_833 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_834 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_835 = asUInt(reset)
node _T_836 = eq(_T_835, UInt<1>(0h0))
when _T_836 :
node _T_837 = eq(_T_834, UInt<1>(0h0))
when _T_837 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_834, UInt<1>(0h1), "") : assert_44
node _T_838 = eq(io.in.a.bits.mask, mask)
node _T_839 = asUInt(reset)
node _T_840 = eq(_T_839, UInt<1>(0h0))
when _T_840 :
node _T_841 = eq(_T_838, UInt<1>(0h0))
when _T_841 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_838, UInt<1>(0h1), "") : assert_45
node _T_842 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_842 :
node _T_843 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_844 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_845 = and(_T_843, _T_844)
node _T_846 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_847 = shr(io.in.a.bits.source, 2)
node _T_848 = eq(_T_847, UInt<1>(0h0))
node _T_849 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_850 = and(_T_848, _T_849)
node _T_851 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_852 = and(_T_850, _T_851)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_853 = shr(io.in.a.bits.source, 2)
node _T_854 = eq(_T_853, UInt<1>(0h1))
node _T_855 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_856 = and(_T_854, _T_855)
node _T_857 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_858 = and(_T_856, _T_857)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_859 = shr(io.in.a.bits.source, 2)
node _T_860 = eq(_T_859, UInt<2>(0h2))
node _T_861 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_862 = and(_T_860, _T_861)
node _T_863 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_864 = and(_T_862, _T_863)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_865 = shr(io.in.a.bits.source, 2)
node _T_866 = eq(_T_865, UInt<2>(0h3))
node _T_867 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_868 = and(_T_866, _T_867)
node _T_869 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_870 = and(_T_868, _T_869)
node _T_871 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_872 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_873 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_874 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_875 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_876 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_877 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_878 = or(_T_846, _T_852)
node _T_879 = or(_T_878, _T_858)
node _T_880 = or(_T_879, _T_864)
node _T_881 = or(_T_880, _T_870)
node _T_882 = or(_T_881, _T_871)
node _T_883 = or(_T_882, _T_872)
node _T_884 = or(_T_883, _T_873)
node _T_885 = or(_T_884, _T_874)
node _T_886 = or(_T_885, _T_875)
node _T_887 = or(_T_886, _T_876)
node _T_888 = or(_T_887, _T_877)
node _T_889 = and(_T_845, _T_888)
node _T_890 = or(UInt<1>(0h0), _T_889)
node _T_891 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_892 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_893 = cvt(_T_892)
node _T_894 = and(_T_893, asSInt(UInt<13>(0h1000)))
node _T_895 = asSInt(_T_894)
node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0)))
node _T_897 = and(_T_891, _T_896)
node _T_898 = or(UInt<1>(0h0), _T_897)
node _T_899 = and(_T_890, _T_898)
node _T_900 = asUInt(reset)
node _T_901 = eq(_T_900, UInt<1>(0h0))
when _T_901 :
node _T_902 = eq(_T_899, UInt<1>(0h0))
when _T_902 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_899, UInt<1>(0h1), "") : assert_46
node _T_903 = asUInt(reset)
node _T_904 = eq(_T_903, UInt<1>(0h0))
when _T_904 :
node _T_905 = eq(source_ok, UInt<1>(0h0))
when _T_905 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_906 = asUInt(reset)
node _T_907 = eq(_T_906, UInt<1>(0h0))
when _T_907 :
node _T_908 = eq(is_aligned, UInt<1>(0h0))
when _T_908 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_909 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_910 = asUInt(reset)
node _T_911 = eq(_T_910, UInt<1>(0h0))
when _T_911 :
node _T_912 = eq(_T_909, UInt<1>(0h0))
when _T_912 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_909, UInt<1>(0h1), "") : assert_49
node _T_913 = eq(io.in.a.bits.mask, mask)
node _T_914 = asUInt(reset)
node _T_915 = eq(_T_914, UInt<1>(0h0))
when _T_915 :
node _T_916 = eq(_T_913, UInt<1>(0h0))
when _T_916 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_913, UInt<1>(0h1), "") : assert_50
node _T_917 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_918 = asUInt(reset)
node _T_919 = eq(_T_918, UInt<1>(0h0))
when _T_919 :
node _T_920 = eq(_T_917, UInt<1>(0h0))
when _T_920 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_917, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_921 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_922 = asUInt(reset)
node _T_923 = eq(_T_922, UInt<1>(0h0))
when _T_923 :
node _T_924 = eq(_T_921, UInt<1>(0h0))
when _T_924 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_921, UInt<1>(0h1), "") : assert_52
node _source_ok_T_42 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_43 = shr(io.in.d.bits.source, 2)
node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h0))
node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45)
node _source_ok_T_47 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_49 = shr(io.in.d.bits.source, 2)
node _source_ok_T_50 = eq(_source_ok_T_49, UInt<1>(0h1))
node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51)
node _source_ok_T_53 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_55 = shr(io.in.d.bits.source, 2)
node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h2))
node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57)
node _source_ok_T_59 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_61 = shr(io.in.d.bits.source, 2)
node _source_ok_T_62 = eq(_source_ok_T_61, UInt<2>(0h3))
node _source_ok_T_63 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63)
node _source_ok_T_65 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65)
node _source_ok_T_67 = eq(io.in.d.bits.source, UInt<6>(0h24))
node _source_ok_T_68 = eq(io.in.d.bits.source, UInt<6>(0h25))
node _source_ok_T_69 = eq(io.in.d.bits.source, UInt<6>(0h26))
node _source_ok_T_70 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_T_71 = eq(io.in.d.bits.source, UInt<6>(0h21))
node _source_ok_T_72 = eq(io.in.d.bits.source, UInt<6>(0h22))
node _source_ok_T_73 = eq(io.in.d.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE_1 : UInt<1>[12]
connect _source_ok_WIRE_1[0], _source_ok_T_42
connect _source_ok_WIRE_1[1], _source_ok_T_48
connect _source_ok_WIRE_1[2], _source_ok_T_54
connect _source_ok_WIRE_1[3], _source_ok_T_60
connect _source_ok_WIRE_1[4], _source_ok_T_66
connect _source_ok_WIRE_1[5], _source_ok_T_67
connect _source_ok_WIRE_1[6], _source_ok_T_68
connect _source_ok_WIRE_1[7], _source_ok_T_69
connect _source_ok_WIRE_1[8], _source_ok_T_70
connect _source_ok_WIRE_1[9], _source_ok_T_71
connect _source_ok_WIRE_1[10], _source_ok_T_72
connect _source_ok_WIRE_1[11], _source_ok_T_73
node _source_ok_T_74 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE_1[2])
node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE_1[3])
node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE_1[4])
node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE_1[5])
node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE_1[6])
node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE_1[7])
node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE_1[8])
node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE_1[9])
node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE_1[10])
node source_ok_1 = or(_source_ok_T_83, _source_ok_WIRE_1[11])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_925 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_925 :
node _T_926 = asUInt(reset)
node _T_927 = eq(_T_926, UInt<1>(0h0))
when _T_927 :
node _T_928 = eq(source_ok_1, UInt<1>(0h0))
when _T_928 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_929 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_930 = asUInt(reset)
node _T_931 = eq(_T_930, UInt<1>(0h0))
when _T_931 :
node _T_932 = eq(_T_929, UInt<1>(0h0))
when _T_932 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_929, UInt<1>(0h1), "") : assert_54
node _T_933 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_934 = asUInt(reset)
node _T_935 = eq(_T_934, UInt<1>(0h0))
when _T_935 :
node _T_936 = eq(_T_933, UInt<1>(0h0))
when _T_936 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_933, UInt<1>(0h1), "") : assert_55
node _T_937 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_938 = asUInt(reset)
node _T_939 = eq(_T_938, UInt<1>(0h0))
when _T_939 :
node _T_940 = eq(_T_937, UInt<1>(0h0))
when _T_940 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_937, UInt<1>(0h1), "") : assert_56
node _T_941 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_942 = asUInt(reset)
node _T_943 = eq(_T_942, UInt<1>(0h0))
when _T_943 :
node _T_944 = eq(_T_941, UInt<1>(0h0))
when _T_944 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_941, UInt<1>(0h1), "") : assert_57
node _T_945 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_945 :
node _T_946 = asUInt(reset)
node _T_947 = eq(_T_946, UInt<1>(0h0))
when _T_947 :
node _T_948 = eq(source_ok_1, UInt<1>(0h0))
when _T_948 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_949 = asUInt(reset)
node _T_950 = eq(_T_949, UInt<1>(0h0))
when _T_950 :
node _T_951 = eq(sink_ok, UInt<1>(0h0))
when _T_951 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_952 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_953 = asUInt(reset)
node _T_954 = eq(_T_953, UInt<1>(0h0))
when _T_954 :
node _T_955 = eq(_T_952, UInt<1>(0h0))
when _T_955 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_952, UInt<1>(0h1), "") : assert_60
node _T_956 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_957 = asUInt(reset)
node _T_958 = eq(_T_957, UInt<1>(0h0))
when _T_958 :
node _T_959 = eq(_T_956, UInt<1>(0h0))
when _T_959 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_956, UInt<1>(0h1), "") : assert_61
node _T_960 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_961 = asUInt(reset)
node _T_962 = eq(_T_961, UInt<1>(0h0))
when _T_962 :
node _T_963 = eq(_T_960, UInt<1>(0h0))
when _T_963 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_960, UInt<1>(0h1), "") : assert_62
node _T_964 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_965 = asUInt(reset)
node _T_966 = eq(_T_965, UInt<1>(0h0))
when _T_966 :
node _T_967 = eq(_T_964, UInt<1>(0h0))
when _T_967 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_964, UInt<1>(0h1), "") : assert_63
node _T_968 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_969 = or(UInt<1>(0h0), _T_968)
node _T_970 = asUInt(reset)
node _T_971 = eq(_T_970, UInt<1>(0h0))
when _T_971 :
node _T_972 = eq(_T_969, UInt<1>(0h0))
when _T_972 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_969, UInt<1>(0h1), "") : assert_64
node _T_973 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_973 :
node _T_974 = asUInt(reset)
node _T_975 = eq(_T_974, UInt<1>(0h0))
when _T_975 :
node _T_976 = eq(source_ok_1, UInt<1>(0h0))
when _T_976 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_977 = asUInt(reset)
node _T_978 = eq(_T_977, UInt<1>(0h0))
when _T_978 :
node _T_979 = eq(sink_ok, UInt<1>(0h0))
when _T_979 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_980 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_981 = asUInt(reset)
node _T_982 = eq(_T_981, UInt<1>(0h0))
when _T_982 :
node _T_983 = eq(_T_980, UInt<1>(0h0))
when _T_983 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_980, UInt<1>(0h1), "") : assert_67
node _T_984 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_985 = asUInt(reset)
node _T_986 = eq(_T_985, UInt<1>(0h0))
when _T_986 :
node _T_987 = eq(_T_984, UInt<1>(0h0))
when _T_987 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_984, UInt<1>(0h1), "") : assert_68
node _T_988 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_989 = asUInt(reset)
node _T_990 = eq(_T_989, UInt<1>(0h0))
when _T_990 :
node _T_991 = eq(_T_988, UInt<1>(0h0))
when _T_991 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_988, UInt<1>(0h1), "") : assert_69
node _T_992 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_993 = or(_T_992, io.in.d.bits.corrupt)
node _T_994 = asUInt(reset)
node _T_995 = eq(_T_994, UInt<1>(0h0))
when _T_995 :
node _T_996 = eq(_T_993, UInt<1>(0h0))
when _T_996 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_993, UInt<1>(0h1), "") : assert_70
node _T_997 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_998 = or(UInt<1>(0h0), _T_997)
node _T_999 = asUInt(reset)
node _T_1000 = eq(_T_999, UInt<1>(0h0))
when _T_1000 :
node _T_1001 = eq(_T_998, UInt<1>(0h0))
when _T_1001 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_998, UInt<1>(0h1), "") : assert_71
node _T_1002 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1002 :
node _T_1003 = asUInt(reset)
node _T_1004 = eq(_T_1003, UInt<1>(0h0))
when _T_1004 :
node _T_1005 = eq(source_ok_1, UInt<1>(0h0))
when _T_1005 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1006 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1007 = asUInt(reset)
node _T_1008 = eq(_T_1007, UInt<1>(0h0))
when _T_1008 :
node _T_1009 = eq(_T_1006, UInt<1>(0h0))
when _T_1009 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1006, UInt<1>(0h1), "") : assert_73
node _T_1010 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1011 = asUInt(reset)
node _T_1012 = eq(_T_1011, UInt<1>(0h0))
when _T_1012 :
node _T_1013 = eq(_T_1010, UInt<1>(0h0))
when _T_1013 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1010, UInt<1>(0h1), "") : assert_74
node _T_1014 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1015 = or(UInt<1>(0h0), _T_1014)
node _T_1016 = asUInt(reset)
node _T_1017 = eq(_T_1016, UInt<1>(0h0))
when _T_1017 :
node _T_1018 = eq(_T_1015, UInt<1>(0h0))
when _T_1018 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1015, UInt<1>(0h1), "") : assert_75
node _T_1019 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1019 :
node _T_1020 = asUInt(reset)
node _T_1021 = eq(_T_1020, UInt<1>(0h0))
when _T_1021 :
node _T_1022 = eq(source_ok_1, UInt<1>(0h0))
when _T_1022 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1023 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1024 = asUInt(reset)
node _T_1025 = eq(_T_1024, UInt<1>(0h0))
when _T_1025 :
node _T_1026 = eq(_T_1023, UInt<1>(0h0))
when _T_1026 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1023, UInt<1>(0h1), "") : assert_77
node _T_1027 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1028 = or(_T_1027, io.in.d.bits.corrupt)
node _T_1029 = asUInt(reset)
node _T_1030 = eq(_T_1029, UInt<1>(0h0))
when _T_1030 :
node _T_1031 = eq(_T_1028, UInt<1>(0h0))
when _T_1031 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1028, UInt<1>(0h1), "") : assert_78
node _T_1032 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1033 = or(UInt<1>(0h0), _T_1032)
node _T_1034 = asUInt(reset)
node _T_1035 = eq(_T_1034, UInt<1>(0h0))
when _T_1035 :
node _T_1036 = eq(_T_1033, UInt<1>(0h0))
when _T_1036 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1033, UInt<1>(0h1), "") : assert_79
node _T_1037 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1037 :
node _T_1038 = asUInt(reset)
node _T_1039 = eq(_T_1038, UInt<1>(0h0))
when _T_1039 :
node _T_1040 = eq(source_ok_1, UInt<1>(0h0))
when _T_1040 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1041 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1042 = asUInt(reset)
node _T_1043 = eq(_T_1042, UInt<1>(0h0))
when _T_1043 :
node _T_1044 = eq(_T_1041, UInt<1>(0h0))
when _T_1044 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1041, UInt<1>(0h1), "") : assert_81
node _T_1045 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1046 = asUInt(reset)
node _T_1047 = eq(_T_1046, UInt<1>(0h0))
when _T_1047 :
node _T_1048 = eq(_T_1045, UInt<1>(0h0))
when _T_1048 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1045, UInt<1>(0h1), "") : assert_82
node _T_1049 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1050 = or(UInt<1>(0h0), _T_1049)
node _T_1051 = asUInt(reset)
node _T_1052 = eq(_T_1051, UInt<1>(0h0))
when _T_1052 :
node _T_1053 = eq(_T_1050, UInt<1>(0h0))
when _T_1053 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1050, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<21>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1054 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1055 = asUInt(reset)
node _T_1056 = eq(_T_1055, UInt<1>(0h0))
when _T_1056 :
node _T_1057 = eq(_T_1054, UInt<1>(0h0))
when _T_1057 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1054, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<21>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1058 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1059 = asUInt(reset)
node _T_1060 = eq(_T_1059, UInt<1>(0h0))
when _T_1060 :
node _T_1061 = eq(_T_1058, UInt<1>(0h0))
when _T_1061 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1058, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1062 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1063 = asUInt(reset)
node _T_1064 = eq(_T_1063, UInt<1>(0h0))
when _T_1064 :
node _T_1065 = eq(_T_1062, UInt<1>(0h0))
when _T_1065 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1062, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1066 = eq(a_first, UInt<1>(0h0))
node _T_1067 = and(io.in.a.valid, _T_1066)
when _T_1067 :
node _T_1068 = eq(io.in.a.bits.opcode, opcode)
node _T_1069 = asUInt(reset)
node _T_1070 = eq(_T_1069, UInt<1>(0h0))
when _T_1070 :
node _T_1071 = eq(_T_1068, UInt<1>(0h0))
when _T_1071 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1068, UInt<1>(0h1), "") : assert_87
node _T_1072 = eq(io.in.a.bits.param, param)
node _T_1073 = asUInt(reset)
node _T_1074 = eq(_T_1073, UInt<1>(0h0))
when _T_1074 :
node _T_1075 = eq(_T_1072, UInt<1>(0h0))
when _T_1075 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1072, UInt<1>(0h1), "") : assert_88
node _T_1076 = eq(io.in.a.bits.size, size)
node _T_1077 = asUInt(reset)
node _T_1078 = eq(_T_1077, UInt<1>(0h0))
when _T_1078 :
node _T_1079 = eq(_T_1076, UInt<1>(0h0))
when _T_1079 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1076, UInt<1>(0h1), "") : assert_89
node _T_1080 = eq(io.in.a.bits.source, source)
node _T_1081 = asUInt(reset)
node _T_1082 = eq(_T_1081, UInt<1>(0h0))
when _T_1082 :
node _T_1083 = eq(_T_1080, UInt<1>(0h0))
when _T_1083 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1080, UInt<1>(0h1), "") : assert_90
node _T_1084 = eq(io.in.a.bits.address, address)
node _T_1085 = asUInt(reset)
node _T_1086 = eq(_T_1085, UInt<1>(0h0))
when _T_1086 :
node _T_1087 = eq(_T_1084, UInt<1>(0h0))
when _T_1087 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1084, UInt<1>(0h1), "") : assert_91
node _T_1088 = and(io.in.a.ready, io.in.a.valid)
node _T_1089 = and(_T_1088, a_first)
when _T_1089 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1090 = eq(d_first, UInt<1>(0h0))
node _T_1091 = and(io.in.d.valid, _T_1090)
when _T_1091 :
node _T_1092 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1093 = asUInt(reset)
node _T_1094 = eq(_T_1093, UInt<1>(0h0))
when _T_1094 :
node _T_1095 = eq(_T_1092, UInt<1>(0h0))
when _T_1095 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1092, UInt<1>(0h1), "") : assert_92
node _T_1096 = eq(io.in.d.bits.param, param_1)
node _T_1097 = asUInt(reset)
node _T_1098 = eq(_T_1097, UInt<1>(0h0))
when _T_1098 :
node _T_1099 = eq(_T_1096, UInt<1>(0h0))
when _T_1099 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1096, UInt<1>(0h1), "") : assert_93
node _T_1100 = eq(io.in.d.bits.size, size_1)
node _T_1101 = asUInt(reset)
node _T_1102 = eq(_T_1101, UInt<1>(0h0))
when _T_1102 :
node _T_1103 = eq(_T_1100, UInt<1>(0h0))
when _T_1103 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1100, UInt<1>(0h1), "") : assert_94
node _T_1104 = eq(io.in.d.bits.source, source_1)
node _T_1105 = asUInt(reset)
node _T_1106 = eq(_T_1105, UInt<1>(0h0))
when _T_1106 :
node _T_1107 = eq(_T_1104, UInt<1>(0h0))
when _T_1107 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1104, UInt<1>(0h1), "") : assert_95
node _T_1108 = eq(io.in.d.bits.sink, sink)
node _T_1109 = asUInt(reset)
node _T_1110 = eq(_T_1109, UInt<1>(0h0))
when _T_1110 :
node _T_1111 = eq(_T_1108, UInt<1>(0h0))
when _T_1111 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1108, UInt<1>(0h1), "") : assert_96
node _T_1112 = eq(io.in.d.bits.denied, denied)
node _T_1113 = asUInt(reset)
node _T_1114 = eq(_T_1113, UInt<1>(0h0))
when _T_1114 :
node _T_1115 = eq(_T_1112, UInt<1>(0h0))
when _T_1115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1112, UInt<1>(0h1), "") : assert_97
node _T_1116 = and(io.in.d.ready, io.in.d.valid)
node _T_1117 = and(_T_1116, d_first)
when _T_1117 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<65>
connect a_set, UInt<65>(0h0)
wire a_set_wo_ready : UInt<65>
connect a_set_wo_ready, UInt<65>(0h0)
wire a_opcodes_set : UInt<260>
connect a_opcodes_set, UInt<260>(0h0)
wire a_sizes_set : UInt<260>
connect a_sizes_set, UInt<260>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1118 = and(io.in.a.valid, a_first_1)
node _T_1119 = and(_T_1118, UInt<1>(0h1))
when _T_1119 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1120 = and(io.in.a.ready, io.in.a.valid)
node _T_1121 = and(_T_1120, a_first_1)
node _T_1122 = and(_T_1121, UInt<1>(0h1))
when _T_1122 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1123 = dshr(inflight, io.in.a.bits.source)
node _T_1124 = bits(_T_1123, 0, 0)
node _T_1125 = eq(_T_1124, UInt<1>(0h0))
node _T_1126 = asUInt(reset)
node _T_1127 = eq(_T_1126, UInt<1>(0h0))
when _T_1127 :
node _T_1128 = eq(_T_1125, UInt<1>(0h0))
when _T_1128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1125, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<65>
connect d_clr, UInt<65>(0h0)
wire d_clr_wo_ready : UInt<65>
connect d_clr_wo_ready, UInt<65>(0h0)
wire d_opcodes_clr : UInt<260>
connect d_opcodes_clr, UInt<260>(0h0)
wire d_sizes_clr : UInt<260>
connect d_sizes_clr, UInt<260>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1129 = and(io.in.d.valid, d_first_1)
node _T_1130 = and(_T_1129, UInt<1>(0h1))
node _T_1131 = eq(d_release_ack, UInt<1>(0h0))
node _T_1132 = and(_T_1130, _T_1131)
when _T_1132 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1133 = and(io.in.d.ready, io.in.d.valid)
node _T_1134 = and(_T_1133, d_first_1)
node _T_1135 = and(_T_1134, UInt<1>(0h1))
node _T_1136 = eq(d_release_ack, UInt<1>(0h0))
node _T_1137 = and(_T_1135, _T_1136)
when _T_1137 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1138 = and(io.in.d.valid, d_first_1)
node _T_1139 = and(_T_1138, UInt<1>(0h1))
node _T_1140 = eq(d_release_ack, UInt<1>(0h0))
node _T_1141 = and(_T_1139, _T_1140)
when _T_1141 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1142 = dshr(inflight, io.in.d.bits.source)
node _T_1143 = bits(_T_1142, 0, 0)
node _T_1144 = or(_T_1143, same_cycle_resp)
node _T_1145 = asUInt(reset)
node _T_1146 = eq(_T_1145, UInt<1>(0h0))
when _T_1146 :
node _T_1147 = eq(_T_1144, UInt<1>(0h0))
when _T_1147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1144, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1148 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1149 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1150 = or(_T_1148, _T_1149)
node _T_1151 = asUInt(reset)
node _T_1152 = eq(_T_1151, UInt<1>(0h0))
when _T_1152 :
node _T_1153 = eq(_T_1150, UInt<1>(0h0))
when _T_1153 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1150, UInt<1>(0h1), "") : assert_100
node _T_1154 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1155 = asUInt(reset)
node _T_1156 = eq(_T_1155, UInt<1>(0h0))
when _T_1156 :
node _T_1157 = eq(_T_1154, UInt<1>(0h0))
when _T_1157 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1154, UInt<1>(0h1), "") : assert_101
else :
node _T_1158 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1159 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1160 = or(_T_1158, _T_1159)
node _T_1161 = asUInt(reset)
node _T_1162 = eq(_T_1161, UInt<1>(0h0))
when _T_1162 :
node _T_1163 = eq(_T_1160, UInt<1>(0h0))
when _T_1163 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1160, UInt<1>(0h1), "") : assert_102
node _T_1164 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1165 = asUInt(reset)
node _T_1166 = eq(_T_1165, UInt<1>(0h0))
when _T_1166 :
node _T_1167 = eq(_T_1164, UInt<1>(0h0))
when _T_1167 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1164, UInt<1>(0h1), "") : assert_103
node _T_1168 = and(io.in.d.valid, d_first_1)
node _T_1169 = and(_T_1168, a_first_1)
node _T_1170 = and(_T_1169, io.in.a.valid)
node _T_1171 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1172 = and(_T_1170, _T_1171)
node _T_1173 = eq(d_release_ack, UInt<1>(0h0))
node _T_1174 = and(_T_1172, _T_1173)
when _T_1174 :
node _T_1175 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1176 = or(_T_1175, io.in.a.ready)
node _T_1177 = asUInt(reset)
node _T_1178 = eq(_T_1177, UInt<1>(0h0))
when _T_1178 :
node _T_1179 = eq(_T_1176, UInt<1>(0h0))
when _T_1179 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1176, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_130
node _T_1180 = orr(inflight)
node _T_1181 = eq(_T_1180, UInt<1>(0h0))
node _T_1182 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1183 = or(_T_1181, _T_1182)
node _T_1184 = lt(watchdog, plusarg_reader.out)
node _T_1185 = or(_T_1183, _T_1184)
node _T_1186 = asUInt(reset)
node _T_1187 = eq(_T_1186, UInt<1>(0h0))
when _T_1187 :
node _T_1188 = eq(_T_1185, UInt<1>(0h0))
when _T_1188 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1185, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1189 = and(io.in.a.ready, io.in.a.valid)
node _T_1190 = and(io.in.d.ready, io.in.d.valid)
node _T_1191 = or(_T_1189, _T_1190)
when _T_1191 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<21>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<65>
connect c_set, UInt<65>(0h0)
wire c_set_wo_ready : UInt<65>
connect c_set_wo_ready, UInt<65>(0h0)
wire c_opcodes_set : UInt<260>
connect c_opcodes_set, UInt<260>(0h0)
wire c_sizes_set : UInt<260>
connect c_sizes_set, UInt<260>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<21>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1192 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<21>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1193 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1194 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1195 = and(_T_1193, _T_1194)
node _T_1196 = and(_T_1192, _T_1195)
when _T_1196 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<21>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1197 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1198 = and(_T_1197, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<21>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1199 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1200 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1201 = and(_T_1199, _T_1200)
node _T_1202 = and(_T_1198, _T_1201)
when _T_1202 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<21>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1203 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1204 = bits(_T_1203, 0, 0)
node _T_1205 = eq(_T_1204, UInt<1>(0h0))
node _T_1206 = asUInt(reset)
node _T_1207 = eq(_T_1206, UInt<1>(0h0))
when _T_1207 :
node _T_1208 = eq(_T_1205, UInt<1>(0h0))
when _T_1208 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1205, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<65>
connect d_clr_1, UInt<65>(0h0)
wire d_clr_wo_ready_1 : UInt<65>
connect d_clr_wo_ready_1, UInt<65>(0h0)
wire d_opcodes_clr_1 : UInt<260>
connect d_opcodes_clr_1, UInt<260>(0h0)
wire d_sizes_clr_1 : UInt<260>
connect d_sizes_clr_1, UInt<260>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1209 = and(io.in.d.valid, d_first_2)
node _T_1210 = and(_T_1209, UInt<1>(0h1))
node _T_1211 = and(_T_1210, d_release_ack_1)
when _T_1211 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1212 = and(io.in.d.ready, io.in.d.valid)
node _T_1213 = and(_T_1212, d_first_2)
node _T_1214 = and(_T_1213, UInt<1>(0h1))
node _T_1215 = and(_T_1214, d_release_ack_1)
when _T_1215 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1216 = and(io.in.d.valid, d_first_2)
node _T_1217 = and(_T_1216, UInt<1>(0h1))
node _T_1218 = and(_T_1217, d_release_ack_1)
when _T_1218 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1219 = dshr(inflight_1, io.in.d.bits.source)
node _T_1220 = bits(_T_1219, 0, 0)
node _T_1221 = or(_T_1220, same_cycle_resp_1)
node _T_1222 = asUInt(reset)
node _T_1223 = eq(_T_1222, UInt<1>(0h0))
when _T_1223 :
node _T_1224 = eq(_T_1221, UInt<1>(0h0))
when _T_1224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_1221, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<21>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1225 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1226 = asUInt(reset)
node _T_1227 = eq(_T_1226, UInt<1>(0h0))
when _T_1227 :
node _T_1228 = eq(_T_1225, UInt<1>(0h0))
when _T_1228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1225, UInt<1>(0h1), "") : assert_108
else :
node _T_1229 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1230 = asUInt(reset)
node _T_1231 = eq(_T_1230, UInt<1>(0h0))
when _T_1231 :
node _T_1232 = eq(_T_1229, UInt<1>(0h0))
when _T_1232 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1229, UInt<1>(0h1), "") : assert_109
node _T_1233 = and(io.in.d.valid, d_first_2)
node _T_1234 = and(_T_1233, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<21>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1235 = and(_T_1234, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<21>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1236 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1237 = and(_T_1235, _T_1236)
node _T_1238 = and(_T_1237, d_release_ack_1)
node _T_1239 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1240 = and(_T_1238, _T_1239)
when _T_1240 :
node _T_1241 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<21>(0h0)
connect _WIRE_26.bits.source, UInt<7>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1242 = or(_T_1241, _WIRE_27.ready)
node _T_1243 = asUInt(reset)
node _T_1244 = eq(_T_1243, UInt<1>(0h0))
when _T_1244 :
node _T_1245 = eq(_T_1242, UInt<1>(0h0))
when _T_1245 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1242, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_131
node _T_1246 = orr(inflight_1)
node _T_1247 = eq(_T_1246, UInt<1>(0h0))
node _T_1248 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1249 = or(_T_1247, _T_1248)
node _T_1250 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1251 = or(_T_1249, _T_1250)
node _T_1252 = asUInt(reset)
node _T_1253 = eq(_T_1252, UInt<1>(0h0))
when _T_1253 :
node _T_1254 = eq(_T_1251, UInt<1>(0h0))
when _T_1254 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1251, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<21>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1255 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1256 = and(io.in.d.ready, io.in.d.valid)
node _T_1257 = or(_T_1255, _T_1256)
when _T_1257 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_63( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h25; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31]
wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h26; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31]
wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31]
wire _source_ok_T_29 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31]
wire _source_ok_T_30 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_11 = _source_ok_T_31; // @[Parameters.scala:1138:31]
wire _source_ok_T_32 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_34 = _source_ok_T_33 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_39 = _source_ok_T_38 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_41 = _source_ok_T_40 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_41 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_42 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_42; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_43 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_61 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_44 = _source_ok_T_43 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_48; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_50 = _source_ok_T_49 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_54; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_56 = _source_ok_T_55 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_60; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_62 = _source_ok_T_61 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_66; // @[Parameters.scala:1138:31]
wire _source_ok_T_67 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_67; // @[Parameters.scala:1138:31]
wire _source_ok_T_68 = io_in_d_bits_source_0 == 7'h25; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_68; // @[Parameters.scala:1138:31]
wire _source_ok_T_69 = io_in_d_bits_source_0 == 7'h26; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_69; // @[Parameters.scala:1138:31]
wire _source_ok_T_70 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_70; // @[Parameters.scala:1138:31]
wire _source_ok_T_71 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_71; // @[Parameters.scala:1138:31]
wire _source_ok_T_72 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_72; // @[Parameters.scala:1138:31]
wire _source_ok_T_73 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_11 = _source_ok_T_73; // @[Parameters.scala:1138:31]
wire _source_ok_T_74 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_75 = _source_ok_T_74 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_78 = _source_ok_T_77 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_79 = _source_ok_T_78 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_80 = _source_ok_T_79 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_81 = _source_ok_T_80 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_82 = _source_ok_T_81 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_83 = _source_ok_T_82 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_83 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1189 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1189; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1189; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [20:0] address; // @[Monitor.scala:391:22]
wire _T_1257 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1257; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1257; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1257; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [259:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1122 = _T_1189 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1122 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1122 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1122 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1122 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1122 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1168 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1168 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1137 = _T_1257 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1137 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1137 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1137 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1233 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1233 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1215 = _T_1257 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1215 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1215 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1215 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e5_s11_5 :
output io : { flip op : UInt<2>, flip a : UInt<17>, flip b : UInt<17>, flip c : UInt<17>, mulAddA : UInt<11>, mulAddB : UInt<11>, mulAddC : UInt<22>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<7>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<4>, highAlignedSigC : UInt<13>, bit0AlignedSigC : UInt<1>}}
node rawA_exp = bits(io.a, 15, 10)
node _rawA_isZero_T = bits(rawA_exp, 5, 3)
node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0))
node _rawA_isSpecial_T = bits(rawA_exp, 5, 4)
node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3))
wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>}
node _rawA_out_isNaN_T = bits(rawA_exp, 3, 3)
node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T)
connect rawA.isNaN, _rawA_out_isNaN_T_1
node _rawA_out_isInf_T = bits(rawA_exp, 3, 3)
node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0))
node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1)
connect rawA.isInf, _rawA_out_isInf_T_2
connect rawA.isZero, rawA_isZero
node _rawA_out_sign_T = bits(io.a, 16, 16)
connect rawA.sign, _rawA_out_sign_T
node _rawA_out_sExp_T = cvt(rawA_exp)
connect rawA.sExp, _rawA_out_sExp_T
node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0))
node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T)
node _rawA_out_sig_T_2 = bits(io.a, 9, 0)
node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2)
connect rawA.sig, _rawA_out_sig_T_3
node rawB_exp = bits(io.b, 15, 10)
node _rawB_isZero_T = bits(rawB_exp, 5, 3)
node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0))
node _rawB_isSpecial_T = bits(rawB_exp, 5, 4)
node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3))
wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>}
node _rawB_out_isNaN_T = bits(rawB_exp, 3, 3)
node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T)
connect rawB.isNaN, _rawB_out_isNaN_T_1
node _rawB_out_isInf_T = bits(rawB_exp, 3, 3)
node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0))
node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1)
connect rawB.isInf, _rawB_out_isInf_T_2
connect rawB.isZero, rawB_isZero
node _rawB_out_sign_T = bits(io.b, 16, 16)
connect rawB.sign, _rawB_out_sign_T
node _rawB_out_sExp_T = cvt(rawB_exp)
connect rawB.sExp, _rawB_out_sExp_T
node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0))
node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T)
node _rawB_out_sig_T_2 = bits(io.b, 9, 0)
node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2)
connect rawB.sig, _rawB_out_sig_T_3
node rawC_exp = bits(io.c, 15, 10)
node _rawC_isZero_T = bits(rawC_exp, 5, 3)
node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0))
node _rawC_isSpecial_T = bits(rawC_exp, 5, 4)
node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3))
wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>}
node _rawC_out_isNaN_T = bits(rawC_exp, 3, 3)
node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T)
connect rawC.isNaN, _rawC_out_isNaN_T_1
node _rawC_out_isInf_T = bits(rawC_exp, 3, 3)
node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0))
node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1)
connect rawC.isInf, _rawC_out_isInf_T_2
connect rawC.isZero, rawC_isZero
node _rawC_out_sign_T = bits(io.c, 16, 16)
connect rawC.sign, _rawC_out_sign_T
node _rawC_out_sExp_T = cvt(rawC_exp)
connect rawC.sExp, _rawC_out_sExp_T
node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0))
node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T)
node _rawC_out_sig_T_2 = bits(io.c, 9, 0)
node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2)
connect rawC.sig, _rawC_out_sig_T_3
node _signProd_T = xor(rawA.sign, rawB.sign)
node _signProd_T_1 = bits(io.op, 1, 1)
node signProd = xor(_signProd_T, _signProd_T_1)
node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp)
node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<6>(0h2e)))
node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1)
node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2)
node _doSubMags_T = xor(signProd, rawC.sign)
node _doSubMags_T_1 = bits(io.op, 0, 0)
node doSubMags = xor(_doSubMags_T, _doSubMags_T_1)
node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp)
node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1)
node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1)
node posNatCAlignDist = bits(sNatCAlignDist, 6, 0)
node _isMinCAlign_T = or(rawA.isZero, rawB.isZero)
node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0)))
node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1)
node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0))
node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<4>(0hb))
node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1)
node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2)
node _CAlignDist_T = lt(posNatCAlignDist, UInt<6>(0h23))
node _CAlignDist_T_1 = bits(posNatCAlignDist, 5, 0)
node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<6>(0h23))
node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2)
node _mainAlignedSigC_T = not(rawC.sig)
node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig)
node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<27>(0h7ffffff), UInt<27>(0h0))
node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2)
node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3)
node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist)
node _reduced4CExtra_T = shl(rawC.sig, 0)
wire reduced4CExtra_reducedVec : UInt<1>[3]
node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0)
node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T)
connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1
node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4)
node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T)
connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1
node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8)
node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T)
connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1
node reduced4CExtra_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1])
node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_reducedVec[0])
node _reduced4CExtra_T_2 = shr(CAlignDist, 2)
node reduced4CExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _reduced4CExtra_T_2)
node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 9, 8)
node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 0, 0)
node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_3, 1, 1)
node _reduced4CExtra_T_6 = cat(_reduced4CExtra_T_4, _reduced4CExtra_T_5)
node _reduced4CExtra_T_7 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_6)
node reduced4CExtra = orr(_reduced4CExtra_T_7)
node _alignedSigC_T = shr(mainAlignedSigC, 3)
node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0)
node _alignedSigC_T_2 = andr(_alignedSigC_T_1)
node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0))
node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3)
node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0)
node _alignedSigC_T_6 = orr(_alignedSigC_T_5)
node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra)
node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7)
node alignedSigC_hi = asUInt(_alignedSigC_T)
node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8)
connect io.mulAddA, rawA.sig
connect io.mulAddB, rawB.sig
node _io_mulAddC_T = bits(alignedSigC, 22, 1)
connect io.mulAddC, _io_mulAddC_T
node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 9, 9)
node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1)
node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 9, 9)
node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4)
node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5)
node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 9, 9)
node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8)
node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9)
connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10
node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN)
connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T
connect io.toPostMul.isInfA, rawA.isInf
connect io.toPostMul.isZeroA, rawA.isZero
connect io.toPostMul.isInfB, rawB.isInf
connect io.toPostMul.isZeroB, rawB.isZero
connect io.toPostMul.signProd, signProd
connect io.toPostMul.isNaNC, rawC.isNaN
connect io.toPostMul.isInfC, rawC.isInf
connect io.toPostMul.isZeroC, rawC.isZero
node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<5>(0hb)))
node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1)
node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1)
node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2)
connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3
connect io.toPostMul.doSubMags, doSubMags
connect io.toPostMul.CIsDominant, CIsDominant
node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 3, 0)
connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T
node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 35, 23)
connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T
node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0)
connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T | module MulAddRecFNToRaw_preMul_e5_s11_5( // @[MulAddRecFN.scala:71:7]
input [1:0] io_op, // @[MulAddRecFN.scala:74:16]
input [16:0] io_a, // @[MulAddRecFN.scala:74:16]
input [16:0] io_b, // @[MulAddRecFN.scala:74:16]
input [16:0] io_c, // @[MulAddRecFN.scala:74:16]
output [10:0] io_mulAddA, // @[MulAddRecFN.scala:74:16]
output [10:0] io_mulAddB, // @[MulAddRecFN.scala:74:16]
output [21:0] io_mulAddC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16]
output [6:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16]
output [3:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16]
output [12:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16]
);
wire [1:0] io_op_0 = io_op; // @[MulAddRecFN.scala:71:7]
wire [16:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7]
wire [16:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7]
wire [16:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7]
wire [21:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30]
wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58]
wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42]
wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire signProd; // @[MulAddRecFN.scala:97:42]
wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire doSubMags; // @[MulAddRecFN.scala:102:42]
wire CIsDominant; // @[MulAddRecFN.scala:110:23]
wire [3:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47]
wire [12:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20]
wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48]
wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
wire [6:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
wire [3:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
wire [12:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire [10:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
wire [10:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
wire [21:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
wire [5:0] rawA_exp = io_a_0[15:10]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawA_isZero_T = rawA_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawA_isSpecial_T = rawA_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [6:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [11:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [6:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_isNaN_T = rawA_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawA_out_isInf_T = rawA_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawA_out_sign_T = io_a_0[16]; // @[rawFloatFromRecFN.scala:59:25]
assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [9:0] _rawA_out_sig_T_2 = io_a_0[9:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [5:0] rawB_exp = io_b_0[15:10]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawB_isZero_T = rawB_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawB_isSpecial_T = rawB_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [6:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [11:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [6:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_isNaN_T = rawB_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawB_out_isInf_T = rawB_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawB_out_sign_T = io_b_0[16]; // @[rawFloatFromRecFN.scala:59:25]
assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [9:0] _rawB_out_sig_T_2 = io_b_0[9:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [5:0] rawC_exp = io_c_0[15:10]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawC_isZero_T = rawC_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawC_isSpecial_T = rawC_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [6:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [11:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [6:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] _reduced4CExtra_T = rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isNaN_T = rawC_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawC_out_isInf_T = rawC_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawC_out_sign_T = io_c_0[16]; // @[rawFloatFromRecFN.scala:59:25]
assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [9:0] _rawC_out_sig_T_2 = io_c_0[9:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _signProd_T_1 = io_op_0[1]; // @[MulAddRecFN.scala:71:7, :97:49]
assign signProd = _signProd_T ^ _signProd_T_1; // @[MulAddRecFN.scala:97:{30,42,49}]
assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42]
wire [7:0] _sExpAlignedProd_T = {rawA_sExp[6], rawA_sExp} + {rawB_sExp[6], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[7], _sExpAlignedProd_T} - 9'h12; // @[MulAddRecFN.scala:100:{19,32}]
wire [7:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[7:0]; // @[MulAddRecFN.scala:100:32]
wire [7:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32]
wire _doSubMags_T = signProd ^ rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _doSubMags_T_1 = io_op_0[0]; // @[MulAddRecFN.scala:71:7, :102:49]
assign doSubMags = _doSubMags_T ^ _doSubMags_T_1; // @[MulAddRecFN.scala:102:{30,42,49}]
assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42]
wire [8:0] _GEN = {sExpAlignedProd[7], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42]
wire [8:0] _sNatCAlignDist_T = _GEN - {{2{rawC_sExp[6]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[7:0]; // @[MulAddRecFN.scala:106:42]
wire [7:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42]
wire [6:0] posNatCAlignDist = sNatCAlignDist[6:0]; // @[MulAddRecFN.scala:106:42, :107:42]
wire _isMinCAlign_T = rawA_isZero | rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 8'sh0; // @[MulAddRecFN.scala:106:42, :108:69]
wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}]
wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _CIsDominant_T_1 = posNatCAlignDist < 7'hC; // @[MulAddRecFN.scala:107:42, :110:60]
wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}]
assign CIsDominant = _CIsDominant_T & _CIsDominant_T_2; // @[MulAddRecFN.scala:110:{9,23,39}]
assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23]
wire _CAlignDist_T = posNatCAlignDist < 7'h23; // @[MulAddRecFN.scala:107:42, :114:34]
wire [5:0] _CAlignDist_T_1 = posNatCAlignDist[5:0]; // @[MulAddRecFN.scala:107:42, :115:33]
wire [5:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 6'h23; // @[MulAddRecFN.scala:114:{16,34}, :115:33]
wire [5:0] CAlignDist = isMinCAlign ? 6'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16]
wire [11:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [26:0] _mainAlignedSigC_T_2 = {27{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53]
wire [38:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}]
wire [38:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}]
wire [38:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}]
wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:123:57]
wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30]
wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_0_T_1 = |_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_1_T_1 = |_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:123:15]
assign _reduced4CExtra_reducedVec_2_T_1 = |_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:123:{15,57}]
assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] reduced4CExtra_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [3:0] _reduced4CExtra_T_2 = CAlignDist[5:2]; // @[MulAddRecFN.scala:112:12, :124:28]
wire [16:0] reduced4CExtra_shift = $signed(17'sh10000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56]
wire [1:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[9:8]; // @[primitives.scala:76:56, :78:22]
wire _reduced4CExtra_T_4 = _reduced4CExtra_T_3[0]; // @[primitives.scala:77:20, :78:22]
wire _reduced4CExtra_T_5 = _reduced4CExtra_T_3[1]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _reduced4CExtra_T_6 = {_reduced4CExtra_T_4, _reduced4CExtra_T_5}; // @[primitives.scala:77:20]
wire [2:0] _reduced4CExtra_T_7 = {1'h0, _reduced4CExtra_T_1[1:0] & _reduced4CExtra_T_6}; // @[primitives.scala:77:20, :124:20]
wire reduced4CExtra = |_reduced4CExtra_T_7; // @[MulAddRecFN.scala:122:68, :130:11]
wire [35:0] _alignedSigC_T = mainAlignedSigC[38:3]; // @[MulAddRecFN.scala:120:100, :132:28]
wire [35:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}]
wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32]
wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32]
wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}]
wire _alignedSigC_T_3 = ~reduced4CExtra; // @[MulAddRecFN.scala:130:11, :134:47]
wire _alignedSigC_T_4 = _alignedSigC_T_2 & _alignedSigC_T_3; // @[MulAddRecFN.scala:134:{39,44,47}]
wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}]
wire _alignedSigC_T_7 = _alignedSigC_T_6 | reduced4CExtra; // @[MulAddRecFN.scala:130:11, :135:{39,44}]
wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44]
wire [36:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16]
assign io_mulAddA_0 = rawA_sig[10:0]; // @[rawFloatFromRecFN.scala:55:23]
assign io_mulAddB_0 = rawB_sig[10:0]; // @[rawFloatFromRecFN.scala:55:23]
assign _io_mulAddC_T = alignedSigC[22:1]; // @[MulAddRecFN.scala:132:12, :143:30]
assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30]
wire _io_toPostMul_isSigNaNAny_T = rawA_sig[9]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[9]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 | _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46]
wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[9]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23]
assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6 | _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46]
assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58]
assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN | rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42]
wire [8:0] _io_toPostMul_sExpSum_T = _GEN - 9'hB; // @[MulAddRecFN.scala:106:42, :158:53]
wire [7:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[7:0]; // @[MulAddRecFN.scala:158:53]
wire [7:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53]
wire [7:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[6], rawC_sExp} : _io_toPostMul_sExpSum_T_2; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[6:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12]
assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[3:0]; // @[MulAddRecFN.scala:112:12, :161:47]
assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47]
assign _io_toPostMul_highAlignedSigC_T = alignedSigC[35:23]; // @[MulAddRecFN.scala:132:12, :163:20]
assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20]
assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48]
assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48]
assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Tile_138 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_394
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_138( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_394 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_60 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_124
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_60( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_124 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_55 :
input clock : Clock
input reset : Reset
output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}}
regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff)
reg value_reg : { symbol : UInt<10>}, clock
connect io.output_prev.key, key_reg
connect io.output_prev.value, value_reg
connect io.output_nxt.key, key_reg
connect io.output_nxt.value, value_reg
connect io.cur_output_keyval.key, key_reg
connect io.cur_output_keyval.value, value_reg
when io.cmd.valid :
node _T = eq(UInt<1>(0h0), io.cmd.bits)
when _T :
connect key_reg, io.input_nxt.key
connect value_reg, io.input_nxt.value
else :
node _T_1 = eq(UInt<1>(0h1), io.cmd.bits)
when _T_1 :
when io.insert_here :
connect key_reg, io.cur_input_keyval.key
connect value_reg, io.cur_input_keyval.value
else :
node _T_2 = geq(key_reg, io.cur_input_keyval.key)
when _T_2 :
connect key_reg, io.input_prev.key
connect value_reg, io.input_prev.value
else :
skip | module PriorityQueueStage_55( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToIN_e8_s24_i8_1 :
input clock : Clock
input reset : Reset
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip signedOut : UInt<1>, out : UInt<8>, intExceptionFlags : UInt<3>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node magGeOne = bits(rawIn.sExp, 8, 8)
node posExp = bits(rawIn.sExp, 7, 0)
node _magJustBelowOne_T = eq(magGeOne, UInt<1>(0h0))
node _magJustBelowOne_T_1 = andr(posExp)
node magJustBelowOne = and(_magJustBelowOne_T, _magJustBelowOne_T_1)
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _shiftedSig_T = bits(rawIn.sig, 22, 0)
node _shiftedSig_T_1 = cat(magGeOne, _shiftedSig_T)
node _shiftedSig_T_2 = bits(rawIn.sExp, 2, 0)
node _shiftedSig_T_3 = mux(magGeOne, _shiftedSig_T_2, UInt<1>(0h0))
node shiftedSig = dshl(_shiftedSig_T_1, _shiftedSig_T_3)
node _alignedSig_T = shr(shiftedSig, 22)
node _alignedSig_T_1 = bits(shiftedSig, 21, 0)
node _alignedSig_T_2 = orr(_alignedSig_T_1)
node alignedSig = cat(_alignedSig_T, _alignedSig_T_2)
node _unroundedInt_T = shr(alignedSig, 2)
node unroundedInt = or(UInt<8>(0h0), _unroundedInt_T)
node _common_inexact_T = bits(alignedSig, 1, 0)
node _common_inexact_T_1 = orr(_common_inexact_T)
node _common_inexact_T_2 = eq(rawIn.isZero, UInt<1>(0h0))
node common_inexact = mux(magGeOne, _common_inexact_T_1, _common_inexact_T_2)
node _roundIncr_near_even_T = bits(alignedSig, 2, 1)
node _roundIncr_near_even_T_1 = andr(_roundIncr_near_even_T)
node _roundIncr_near_even_T_2 = bits(alignedSig, 1, 0)
node _roundIncr_near_even_T_3 = andr(_roundIncr_near_even_T_2)
node _roundIncr_near_even_T_4 = or(_roundIncr_near_even_T_1, _roundIncr_near_even_T_3)
node _roundIncr_near_even_T_5 = and(magGeOne, _roundIncr_near_even_T_4)
node _roundIncr_near_even_T_6 = bits(alignedSig, 1, 0)
node _roundIncr_near_even_T_7 = orr(_roundIncr_near_even_T_6)
node _roundIncr_near_even_T_8 = and(magJustBelowOne, _roundIncr_near_even_T_7)
node roundIncr_near_even = or(_roundIncr_near_even_T_5, _roundIncr_near_even_T_8)
node _roundIncr_near_maxMag_T = bits(alignedSig, 1, 1)
node _roundIncr_near_maxMag_T_1 = and(magGeOne, _roundIncr_near_maxMag_T)
node roundIncr_near_maxMag = or(_roundIncr_near_maxMag_T_1, magJustBelowOne)
node _roundIncr_T = and(roundingMode_near_even, roundIncr_near_even)
node _roundIncr_T_1 = and(roundingMode_near_maxMag, roundIncr_near_maxMag)
node _roundIncr_T_2 = or(_roundIncr_T, _roundIncr_T_1)
node _roundIncr_T_3 = or(roundingMode_min, roundingMode_odd)
node _roundIncr_T_4 = and(rawIn.sign, common_inexact)
node _roundIncr_T_5 = and(_roundIncr_T_3, _roundIncr_T_4)
node _roundIncr_T_6 = or(_roundIncr_T_2, _roundIncr_T_5)
node _roundIncr_T_7 = eq(rawIn.sign, UInt<1>(0h0))
node _roundIncr_T_8 = and(_roundIncr_T_7, common_inexact)
node _roundIncr_T_9 = and(roundingMode_max, _roundIncr_T_8)
node roundIncr = or(_roundIncr_T_6, _roundIncr_T_9)
node _complUnroundedInt_T = not(unroundedInt)
node complUnroundedInt = mux(rawIn.sign, _complUnroundedInt_T, unroundedInt)
node _roundedInt_T = xor(roundIncr, rawIn.sign)
node _roundedInt_T_1 = add(complUnroundedInt, UInt<1>(0h1))
node _roundedInt_T_2 = tail(_roundedInt_T_1, 1)
node _roundedInt_T_3 = mux(_roundedInt_T, _roundedInt_T_2, complUnroundedInt)
node _roundedInt_T_4 = and(roundingMode_odd, common_inexact)
node roundedInt = or(_roundedInt_T_3, _roundedInt_T_4)
node magGeOne_atOverflowEdge = eq(posExp, UInt<3>(0h7))
node _roundCarryBut2_T = bits(unroundedInt, 5, 0)
node _roundCarryBut2_T_1 = andr(_roundCarryBut2_T)
node roundCarryBut2 = and(_roundCarryBut2_T_1, roundIncr)
node _common_overflow_T = geq(posExp, UInt<4>(0h8))
node _common_overflow_T_1 = bits(unroundedInt, 6, 0)
node _common_overflow_T_2 = orr(_common_overflow_T_1)
node _common_overflow_T_3 = or(_common_overflow_T_2, roundIncr)
node _common_overflow_T_4 = and(magGeOne_atOverflowEdge, _common_overflow_T_3)
node _common_overflow_T_5 = eq(posExp, UInt<3>(0h6))
node _common_overflow_T_6 = and(_common_overflow_T_5, roundCarryBut2)
node _common_overflow_T_7 = or(magGeOne_atOverflowEdge, _common_overflow_T_6)
node _common_overflow_T_8 = mux(rawIn.sign, _common_overflow_T_4, _common_overflow_T_7)
node _common_overflow_T_9 = bits(unroundedInt, 6, 6)
node _common_overflow_T_10 = and(magGeOne_atOverflowEdge, _common_overflow_T_9)
node _common_overflow_T_11 = and(_common_overflow_T_10, roundCarryBut2)
node _common_overflow_T_12 = or(rawIn.sign, _common_overflow_T_11)
node _common_overflow_T_13 = mux(io.signedOut, _common_overflow_T_8, _common_overflow_T_12)
node _common_overflow_T_14 = or(_common_overflow_T, _common_overflow_T_13)
node _common_overflow_T_15 = eq(io.signedOut, UInt<1>(0h0))
node _common_overflow_T_16 = and(_common_overflow_T_15, rawIn.sign)
node _common_overflow_T_17 = and(_common_overflow_T_16, roundIncr)
node common_overflow = mux(magGeOne, _common_overflow_T_14, _common_overflow_T_17)
node invalidExc = or(rawIn.isNaN, rawIn.isInf)
node _overflow_T = eq(invalidExc, UInt<1>(0h0))
node overflow = and(_overflow_T, common_overflow)
node _inexact_T = eq(invalidExc, UInt<1>(0h0))
node _inexact_T_1 = eq(common_overflow, UInt<1>(0h0))
node _inexact_T_2 = and(_inexact_T, _inexact_T_1)
node inexact = and(_inexact_T_2, common_inexact)
node _excSign_T = eq(rawIn.isNaN, UInt<1>(0h0))
node excSign = and(_excSign_T, rawIn.sign)
node _excOut_T = eq(io.signedOut, excSign)
node _excOut_T_1 = mux(_excOut_T, UInt<8>(0h80), UInt<1>(0h0))
node _excOut_T_2 = eq(excSign, UInt<1>(0h0))
node _excOut_T_3 = mux(_excOut_T_2, UInt<7>(0h7f), UInt<1>(0h0))
node excOut = or(_excOut_T_1, _excOut_T_3)
node _io_out_T = or(invalidExc, common_overflow)
node _io_out_T_1 = mux(_io_out_T, excOut, roundedInt)
connect io.out, _io_out_T_1
node _io_intExceptionFlags_T = cat(invalidExc, overflow)
node _io_intExceptionFlags_T_1 = cat(_io_intExceptionFlags_T, inexact)
connect io.intExceptionFlags, _io_intExceptionFlags_T_1 | module RecFNToIN_e8_s24_i8_1( // @[RecFNToIN.scala:46:7]
input clock, // @[RecFNToIN.scala:46:7]
input reset, // @[RecFNToIN.scala:46:7]
input [32:0] io_in, // @[RecFNToIN.scala:49:16]
output [7:0] io_out, // @[RecFNToIN.scala:49:16]
output [2:0] io_intExceptionFlags // @[RecFNToIN.scala:49:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToIN.scala:46:7]
wire roundingMode_minMag = 1'h0; // @[RecFNToIN.scala:68:53]
wire roundingMode_min = 1'h0; // @[RecFNToIN.scala:69:53]
wire roundingMode_max = 1'h0; // @[RecFNToIN.scala:70:53]
wire roundingMode_near_maxMag = 1'h0; // @[RecFNToIN.scala:71:53]
wire roundingMode_odd = 1'h0; // @[RecFNToIN.scala:72:53]
wire _roundIncr_T_1 = 1'h0; // @[RecFNToIN.scala:99:35]
wire _roundIncr_T_3 = 1'h0; // @[RecFNToIN.scala:100:28]
wire _roundIncr_T_5 = 1'h0; // @[RecFNToIN.scala:100:49]
wire _roundIncr_T_9 = 1'h0; // @[RecFNToIN.scala:102:27]
wire _roundedInt_T_4 = 1'h0; // @[RecFNToIN.scala:108:31]
wire _common_overflow_T_15 = 1'h0; // @[RecFNToIN.scala:128:13]
wire _common_overflow_T_16 = 1'h0; // @[RecFNToIN.scala:128:27]
wire _common_overflow_T_17 = 1'h0; // @[RecFNToIN.scala:128:41]
wire io_signedOut = 1'h1; // @[RecFNToIN.scala:46:7]
wire roundingMode_near_even = 1'h1; // @[RecFNToIN.scala:67:53]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToIN.scala:46:7]
wire [7:0] _io_out_T_1; // @[RecFNToIN.scala:145:18]
wire [2:0] _io_intExceptionFlags_T_1; // @[RecFNToIN.scala:146:52]
wire [7:0] io_out_0; // @[RecFNToIN.scala:46:7]
wire [2:0] io_intExceptionFlags_0; // @[RecFNToIN.scala:46:7]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire magGeOne = rawIn_sExp[8]; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] posExp = rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire _magJustBelowOne_T = ~magGeOne; // @[RecFNToIN.scala:61:30, :63:27]
wire _magJustBelowOne_T_1 = &posExp; // @[RecFNToIN.scala:62:28, :63:47]
wire magJustBelowOne = _magJustBelowOne_T & _magJustBelowOne_T_1; // @[RecFNToIN.scala:63:{27,37,47}]
wire [22:0] _shiftedSig_T = rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _shiftedSig_T_1 = {magGeOne, _shiftedSig_T}; // @[RecFNToIN.scala:61:30, :83:{19,31}]
wire [2:0] _shiftedSig_T_2 = rawIn_sExp[2:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [2:0] _shiftedSig_T_3 = magGeOne ? _shiftedSig_T_2 : 3'h0; // @[RecFNToIN.scala:61:30, :84:16, :85:27]
wire [30:0] shiftedSig = {7'h0, _shiftedSig_T_1} << _shiftedSig_T_3; // @[RecFNToIN.scala:83:{19,49}, :84:16]
wire [8:0] _alignedSig_T = shiftedSig[30:22]; // @[RecFNToIN.scala:83:49, :89:20]
wire [21:0] _alignedSig_T_1 = shiftedSig[21:0]; // @[RecFNToIN.scala:83:49, :89:51]
wire _alignedSig_T_2 = |_alignedSig_T_1; // @[RecFNToIN.scala:89:{51,69}]
wire [9:0] alignedSig = {_alignedSig_T, _alignedSig_T_2}; // @[RecFNToIN.scala:89:{20,38,69}]
wire [7:0] _unroundedInt_T = alignedSig[9:2]; // @[RecFNToIN.scala:89:38, :90:52]
wire [7:0] unroundedInt = _unroundedInt_T; // @[RecFNToIN.scala:90:{40,52}]
wire [1:0] _common_inexact_T = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50]
wire [1:0] _roundIncr_near_even_T_2 = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50, :94:64]
wire [1:0] _roundIncr_near_even_T_6 = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50, :95:39]
wire _common_inexact_T_1 = |_common_inexact_T; // @[RecFNToIN.scala:92:{50,57}]
wire _common_inexact_T_2 = ~rawIn_isZero_0; // @[rawFloatFromRecFN.scala:55:23]
wire common_inexact = magGeOne ? _common_inexact_T_1 : _common_inexact_T_2; // @[RecFNToIN.scala:61:30, :92:{29,57,62}]
wire [1:0] _roundIncr_near_even_T = alignedSig[2:1]; // @[RecFNToIN.scala:89:38, :94:39]
wire _roundIncr_near_even_T_1 = &_roundIncr_near_even_T; // @[RecFNToIN.scala:94:{39,46}]
wire _roundIncr_near_even_T_3 = &_roundIncr_near_even_T_2; // @[RecFNToIN.scala:94:{64,71}]
wire _roundIncr_near_even_T_4 = _roundIncr_near_even_T_1 | _roundIncr_near_even_T_3; // @[RecFNToIN.scala:94:{46,51,71}]
wire _roundIncr_near_even_T_5 = magGeOne & _roundIncr_near_even_T_4; // @[RecFNToIN.scala:61:30, :94:{25,51}]
wire _roundIncr_near_even_T_7 = |_roundIncr_near_even_T_6; // @[RecFNToIN.scala:95:{39,46}]
wire _roundIncr_near_even_T_8 = magJustBelowOne & _roundIncr_near_even_T_7; // @[RecFNToIN.scala:63:37, :95:{26,46}]
wire roundIncr_near_even = _roundIncr_near_even_T_5 | _roundIncr_near_even_T_8; // @[RecFNToIN.scala:94:{25,78}, :95:26]
wire _roundIncr_T = roundIncr_near_even; // @[RecFNToIN.scala:94:78, :98:35]
wire _roundIncr_near_maxMag_T = alignedSig[1]; // @[RecFNToIN.scala:89:38, :96:56]
wire _roundIncr_near_maxMag_T_1 = magGeOne & _roundIncr_near_maxMag_T; // @[RecFNToIN.scala:61:30, :96:{43,56}]
wire roundIncr_near_maxMag = _roundIncr_near_maxMag_T_1 | magJustBelowOne; // @[RecFNToIN.scala:63:37, :96:{43,61}]
wire _roundIncr_T_2 = _roundIncr_T; // @[RecFNToIN.scala:98:{35,61}]
wire _roundIncr_T_6 = _roundIncr_T_2; // @[RecFNToIN.scala:98:61, :99:61]
wire _roundIncr_T_4 = rawIn_sign & common_inexact; // @[rawFloatFromRecFN.scala:55:23]
wire roundIncr = _roundIncr_T_6; // @[RecFNToIN.scala:99:61, :101:46]
wire _roundIncr_T_7 = ~rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _roundIncr_T_8 = _roundIncr_T_7 & common_inexact; // @[RecFNToIN.scala:92:29, :102:{31,43}]
wire [7:0] _complUnroundedInt_T = ~unroundedInt; // @[RecFNToIN.scala:90:40, :103:45]
wire [7:0] complUnroundedInt = rawIn_sign ? _complUnroundedInt_T : unroundedInt; // @[rawFloatFromRecFN.scala:55:23]
wire _roundedInt_T = roundIncr ^ rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _roundedInt_T_1 = {1'h0, complUnroundedInt} + 9'h1; // @[RecFNToIN.scala:103:32, :106:31]
wire [7:0] _roundedInt_T_2 = _roundedInt_T_1[7:0]; // @[RecFNToIN.scala:106:31]
wire [7:0] _roundedInt_T_3 = _roundedInt_T ? _roundedInt_T_2 : complUnroundedInt; // @[RecFNToIN.scala:103:32, :105:{12,23}, :106:31]
wire [7:0] roundedInt = _roundedInt_T_3; // @[RecFNToIN.scala:105:12, :108:11]
wire magGeOne_atOverflowEdge = posExp == 8'h7; // @[RecFNToIN.scala:62:28, :110:43]
wire [5:0] _roundCarryBut2_T = unroundedInt[5:0]; // @[RecFNToIN.scala:90:40, :113:38]
wire _roundCarryBut2_T_1 = &_roundCarryBut2_T; // @[RecFNToIN.scala:113:{38,56}]
wire roundCarryBut2 = _roundCarryBut2_T_1 & roundIncr; // @[RecFNToIN.scala:101:46, :113:{56,61}]
wire _common_overflow_T = |(posExp[7:3]); // @[RecFNToIN.scala:62:28, :116:21]
wire [6:0] _common_overflow_T_1 = unroundedInt[6:0]; // @[RecFNToIN.scala:90:40, :120:42]
wire _common_overflow_T_2 = |_common_overflow_T_1; // @[RecFNToIN.scala:120:{42,60}]
wire _common_overflow_T_3 = _common_overflow_T_2 | roundIncr; // @[RecFNToIN.scala:101:46, :120:{60,64}]
wire _common_overflow_T_4 = magGeOne_atOverflowEdge & _common_overflow_T_3; // @[RecFNToIN.scala:110:43, :119:49, :120:64]
wire _common_overflow_T_5 = posExp == 8'h6; // @[RecFNToIN.scala:62:28, :122:38]
wire _common_overflow_T_6 = _common_overflow_T_5 & roundCarryBut2; // @[RecFNToIN.scala:113:61, :122:{38,60}]
wire _common_overflow_T_7 = magGeOne_atOverflowEdge | _common_overflow_T_6; // @[RecFNToIN.scala:110:43, :121:49, :122:60]
wire _common_overflow_T_8 = rawIn_sign ? _common_overflow_T_4 : _common_overflow_T_7; // @[rawFloatFromRecFN.scala:55:23]
wire _common_overflow_T_13 = _common_overflow_T_8; // @[RecFNToIN.scala:117:20, :118:24]
wire _common_overflow_T_9 = unroundedInt[6]; // @[RecFNToIN.scala:90:40, :126:42]
wire _common_overflow_T_10 = magGeOne_atOverflowEdge & _common_overflow_T_9; // @[RecFNToIN.scala:110:43, :125:50, :126:42]
wire _common_overflow_T_11 = _common_overflow_T_10 & roundCarryBut2; // @[RecFNToIN.scala:113:61, :125:50, :126:57]
wire _common_overflow_T_12 = rawIn_sign | _common_overflow_T_11; // @[rawFloatFromRecFN.scala:55:23]
wire _common_overflow_T_14 = _common_overflow_T | _common_overflow_T_13; // @[RecFNToIN.scala:116:{21,36}, :117:20]
wire common_overflow = magGeOne & _common_overflow_T_14; // @[RecFNToIN.scala:61:30, :115:12, :116:36]
wire invalidExc = rawIn_isNaN | rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire _overflow_T = ~invalidExc; // @[RecFNToIN.scala:133:34, :134:20]
wire overflow = _overflow_T & common_overflow; // @[RecFNToIN.scala:115:12, :134:{20,32}]
wire _inexact_T = ~invalidExc; // @[RecFNToIN.scala:133:34, :134:20, :135:20]
wire _inexact_T_1 = ~common_overflow; // @[RecFNToIN.scala:115:12, :135:35]
wire _inexact_T_2 = _inexact_T & _inexact_T_1; // @[RecFNToIN.scala:135:{20,32,35}]
wire inexact = _inexact_T_2 & common_inexact; // @[RecFNToIN.scala:92:29, :135:{32,52}]
wire _excSign_T = ~rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire excSign = _excSign_T & rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _excOut_T = excSign; // @[RecFNToIN.scala:137:32, :139:27]
wire [7:0] _excOut_T_1 = {_excOut_T, 7'h0}; // @[RecFNToIN.scala:139:{12,27}]
wire _excOut_T_2 = ~excSign; // @[RecFNToIN.scala:137:32, :143:13]
wire [6:0] _excOut_T_3 = {7{_excOut_T_2}}; // @[RecFNToIN.scala:143:{12,13}]
wire [7:0] excOut = {_excOut_T_1[7], _excOut_T_1[6:0] | _excOut_T_3}; // @[RecFNToIN.scala:139:12, :142:11, :143:12]
wire _io_out_T = invalidExc | common_overflow; // @[RecFNToIN.scala:115:12, :133:34, :145:30]
assign _io_out_T_1 = _io_out_T ? excOut : roundedInt; // @[RecFNToIN.scala:108:11, :142:11, :145:{18,30}]
assign io_out_0 = _io_out_T_1; // @[RecFNToIN.scala:46:7, :145:18]
wire [1:0] _io_intExceptionFlags_T = {invalidExc, overflow}; // @[RecFNToIN.scala:133:34, :134:32, :146:40]
assign _io_intExceptionFlags_T_1 = {_io_intExceptionFlags_T, inexact}; // @[RecFNToIN.scala:135:52, :146:{40,52}]
assign io_intExceptionFlags_0 = _io_intExceptionFlags_T_1; // @[RecFNToIN.scala:46:7, :146:52]
assign io_out = io_out_0; // @[RecFNToIN.scala:46:7]
assign io_intExceptionFlags = io_intExceptionFlags_0; // @[RecFNToIN.scala:46:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module INToRecFN_i64_e11_s53_7 :
output io : { flip signedIn : UInt<1>, flip in : UInt<64>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>}
node _intAsRawFloat_sign_T = bits(io.in, 63, 63)
node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T)
node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in)
node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1)
node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in)
node _intAsRawFloat_extAbsIn_T = cat(UInt<64>(0h0), intAsRawFloat_absIn)
node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 63, 0)
node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0)
node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1)
node _intAsRawFloat_adjustedNormDist_T_2 = bits(intAsRawFloat_extAbsIn, 2, 2)
node _intAsRawFloat_adjustedNormDist_T_3 = bits(intAsRawFloat_extAbsIn, 3, 3)
node _intAsRawFloat_adjustedNormDist_T_4 = bits(intAsRawFloat_extAbsIn, 4, 4)
node _intAsRawFloat_adjustedNormDist_T_5 = bits(intAsRawFloat_extAbsIn, 5, 5)
node _intAsRawFloat_adjustedNormDist_T_6 = bits(intAsRawFloat_extAbsIn, 6, 6)
node _intAsRawFloat_adjustedNormDist_T_7 = bits(intAsRawFloat_extAbsIn, 7, 7)
node _intAsRawFloat_adjustedNormDist_T_8 = bits(intAsRawFloat_extAbsIn, 8, 8)
node _intAsRawFloat_adjustedNormDist_T_9 = bits(intAsRawFloat_extAbsIn, 9, 9)
node _intAsRawFloat_adjustedNormDist_T_10 = bits(intAsRawFloat_extAbsIn, 10, 10)
node _intAsRawFloat_adjustedNormDist_T_11 = bits(intAsRawFloat_extAbsIn, 11, 11)
node _intAsRawFloat_adjustedNormDist_T_12 = bits(intAsRawFloat_extAbsIn, 12, 12)
node _intAsRawFloat_adjustedNormDist_T_13 = bits(intAsRawFloat_extAbsIn, 13, 13)
node _intAsRawFloat_adjustedNormDist_T_14 = bits(intAsRawFloat_extAbsIn, 14, 14)
node _intAsRawFloat_adjustedNormDist_T_15 = bits(intAsRawFloat_extAbsIn, 15, 15)
node _intAsRawFloat_adjustedNormDist_T_16 = bits(intAsRawFloat_extAbsIn, 16, 16)
node _intAsRawFloat_adjustedNormDist_T_17 = bits(intAsRawFloat_extAbsIn, 17, 17)
node _intAsRawFloat_adjustedNormDist_T_18 = bits(intAsRawFloat_extAbsIn, 18, 18)
node _intAsRawFloat_adjustedNormDist_T_19 = bits(intAsRawFloat_extAbsIn, 19, 19)
node _intAsRawFloat_adjustedNormDist_T_20 = bits(intAsRawFloat_extAbsIn, 20, 20)
node _intAsRawFloat_adjustedNormDist_T_21 = bits(intAsRawFloat_extAbsIn, 21, 21)
node _intAsRawFloat_adjustedNormDist_T_22 = bits(intAsRawFloat_extAbsIn, 22, 22)
node _intAsRawFloat_adjustedNormDist_T_23 = bits(intAsRawFloat_extAbsIn, 23, 23)
node _intAsRawFloat_adjustedNormDist_T_24 = bits(intAsRawFloat_extAbsIn, 24, 24)
node _intAsRawFloat_adjustedNormDist_T_25 = bits(intAsRawFloat_extAbsIn, 25, 25)
node _intAsRawFloat_adjustedNormDist_T_26 = bits(intAsRawFloat_extAbsIn, 26, 26)
node _intAsRawFloat_adjustedNormDist_T_27 = bits(intAsRawFloat_extAbsIn, 27, 27)
node _intAsRawFloat_adjustedNormDist_T_28 = bits(intAsRawFloat_extAbsIn, 28, 28)
node _intAsRawFloat_adjustedNormDist_T_29 = bits(intAsRawFloat_extAbsIn, 29, 29)
node _intAsRawFloat_adjustedNormDist_T_30 = bits(intAsRawFloat_extAbsIn, 30, 30)
node _intAsRawFloat_adjustedNormDist_T_31 = bits(intAsRawFloat_extAbsIn, 31, 31)
node _intAsRawFloat_adjustedNormDist_T_32 = bits(intAsRawFloat_extAbsIn, 32, 32)
node _intAsRawFloat_adjustedNormDist_T_33 = bits(intAsRawFloat_extAbsIn, 33, 33)
node _intAsRawFloat_adjustedNormDist_T_34 = bits(intAsRawFloat_extAbsIn, 34, 34)
node _intAsRawFloat_adjustedNormDist_T_35 = bits(intAsRawFloat_extAbsIn, 35, 35)
node _intAsRawFloat_adjustedNormDist_T_36 = bits(intAsRawFloat_extAbsIn, 36, 36)
node _intAsRawFloat_adjustedNormDist_T_37 = bits(intAsRawFloat_extAbsIn, 37, 37)
node _intAsRawFloat_adjustedNormDist_T_38 = bits(intAsRawFloat_extAbsIn, 38, 38)
node _intAsRawFloat_adjustedNormDist_T_39 = bits(intAsRawFloat_extAbsIn, 39, 39)
node _intAsRawFloat_adjustedNormDist_T_40 = bits(intAsRawFloat_extAbsIn, 40, 40)
node _intAsRawFloat_adjustedNormDist_T_41 = bits(intAsRawFloat_extAbsIn, 41, 41)
node _intAsRawFloat_adjustedNormDist_T_42 = bits(intAsRawFloat_extAbsIn, 42, 42)
node _intAsRawFloat_adjustedNormDist_T_43 = bits(intAsRawFloat_extAbsIn, 43, 43)
node _intAsRawFloat_adjustedNormDist_T_44 = bits(intAsRawFloat_extAbsIn, 44, 44)
node _intAsRawFloat_adjustedNormDist_T_45 = bits(intAsRawFloat_extAbsIn, 45, 45)
node _intAsRawFloat_adjustedNormDist_T_46 = bits(intAsRawFloat_extAbsIn, 46, 46)
node _intAsRawFloat_adjustedNormDist_T_47 = bits(intAsRawFloat_extAbsIn, 47, 47)
node _intAsRawFloat_adjustedNormDist_T_48 = bits(intAsRawFloat_extAbsIn, 48, 48)
node _intAsRawFloat_adjustedNormDist_T_49 = bits(intAsRawFloat_extAbsIn, 49, 49)
node _intAsRawFloat_adjustedNormDist_T_50 = bits(intAsRawFloat_extAbsIn, 50, 50)
node _intAsRawFloat_adjustedNormDist_T_51 = bits(intAsRawFloat_extAbsIn, 51, 51)
node _intAsRawFloat_adjustedNormDist_T_52 = bits(intAsRawFloat_extAbsIn, 52, 52)
node _intAsRawFloat_adjustedNormDist_T_53 = bits(intAsRawFloat_extAbsIn, 53, 53)
node _intAsRawFloat_adjustedNormDist_T_54 = bits(intAsRawFloat_extAbsIn, 54, 54)
node _intAsRawFloat_adjustedNormDist_T_55 = bits(intAsRawFloat_extAbsIn, 55, 55)
node _intAsRawFloat_adjustedNormDist_T_56 = bits(intAsRawFloat_extAbsIn, 56, 56)
node _intAsRawFloat_adjustedNormDist_T_57 = bits(intAsRawFloat_extAbsIn, 57, 57)
node _intAsRawFloat_adjustedNormDist_T_58 = bits(intAsRawFloat_extAbsIn, 58, 58)
node _intAsRawFloat_adjustedNormDist_T_59 = bits(intAsRawFloat_extAbsIn, 59, 59)
node _intAsRawFloat_adjustedNormDist_T_60 = bits(intAsRawFloat_extAbsIn, 60, 60)
node _intAsRawFloat_adjustedNormDist_T_61 = bits(intAsRawFloat_extAbsIn, 61, 61)
node _intAsRawFloat_adjustedNormDist_T_62 = bits(intAsRawFloat_extAbsIn, 62, 62)
node _intAsRawFloat_adjustedNormDist_T_63 = bits(intAsRawFloat_extAbsIn, 63, 63)
node _intAsRawFloat_adjustedNormDist_T_64 = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<6>(0h3e), UInt<6>(0h3f))
node _intAsRawFloat_adjustedNormDist_T_65 = mux(_intAsRawFloat_adjustedNormDist_T_2, UInt<6>(0h3d), _intAsRawFloat_adjustedNormDist_T_64)
node _intAsRawFloat_adjustedNormDist_T_66 = mux(_intAsRawFloat_adjustedNormDist_T_3, UInt<6>(0h3c), _intAsRawFloat_adjustedNormDist_T_65)
node _intAsRawFloat_adjustedNormDist_T_67 = mux(_intAsRawFloat_adjustedNormDist_T_4, UInt<6>(0h3b), _intAsRawFloat_adjustedNormDist_T_66)
node _intAsRawFloat_adjustedNormDist_T_68 = mux(_intAsRawFloat_adjustedNormDist_T_5, UInt<6>(0h3a), _intAsRawFloat_adjustedNormDist_T_67)
node _intAsRawFloat_adjustedNormDist_T_69 = mux(_intAsRawFloat_adjustedNormDist_T_6, UInt<6>(0h39), _intAsRawFloat_adjustedNormDist_T_68)
node _intAsRawFloat_adjustedNormDist_T_70 = mux(_intAsRawFloat_adjustedNormDist_T_7, UInt<6>(0h38), _intAsRawFloat_adjustedNormDist_T_69)
node _intAsRawFloat_adjustedNormDist_T_71 = mux(_intAsRawFloat_adjustedNormDist_T_8, UInt<6>(0h37), _intAsRawFloat_adjustedNormDist_T_70)
node _intAsRawFloat_adjustedNormDist_T_72 = mux(_intAsRawFloat_adjustedNormDist_T_9, UInt<6>(0h36), _intAsRawFloat_adjustedNormDist_T_71)
node _intAsRawFloat_adjustedNormDist_T_73 = mux(_intAsRawFloat_adjustedNormDist_T_10, UInt<6>(0h35), _intAsRawFloat_adjustedNormDist_T_72)
node _intAsRawFloat_adjustedNormDist_T_74 = mux(_intAsRawFloat_adjustedNormDist_T_11, UInt<6>(0h34), _intAsRawFloat_adjustedNormDist_T_73)
node _intAsRawFloat_adjustedNormDist_T_75 = mux(_intAsRawFloat_adjustedNormDist_T_12, UInt<6>(0h33), _intAsRawFloat_adjustedNormDist_T_74)
node _intAsRawFloat_adjustedNormDist_T_76 = mux(_intAsRawFloat_adjustedNormDist_T_13, UInt<6>(0h32), _intAsRawFloat_adjustedNormDist_T_75)
node _intAsRawFloat_adjustedNormDist_T_77 = mux(_intAsRawFloat_adjustedNormDist_T_14, UInt<6>(0h31), _intAsRawFloat_adjustedNormDist_T_76)
node _intAsRawFloat_adjustedNormDist_T_78 = mux(_intAsRawFloat_adjustedNormDist_T_15, UInt<6>(0h30), _intAsRawFloat_adjustedNormDist_T_77)
node _intAsRawFloat_adjustedNormDist_T_79 = mux(_intAsRawFloat_adjustedNormDist_T_16, UInt<6>(0h2f), _intAsRawFloat_adjustedNormDist_T_78)
node _intAsRawFloat_adjustedNormDist_T_80 = mux(_intAsRawFloat_adjustedNormDist_T_17, UInt<6>(0h2e), _intAsRawFloat_adjustedNormDist_T_79)
node _intAsRawFloat_adjustedNormDist_T_81 = mux(_intAsRawFloat_adjustedNormDist_T_18, UInt<6>(0h2d), _intAsRawFloat_adjustedNormDist_T_80)
node _intAsRawFloat_adjustedNormDist_T_82 = mux(_intAsRawFloat_adjustedNormDist_T_19, UInt<6>(0h2c), _intAsRawFloat_adjustedNormDist_T_81)
node _intAsRawFloat_adjustedNormDist_T_83 = mux(_intAsRawFloat_adjustedNormDist_T_20, UInt<6>(0h2b), _intAsRawFloat_adjustedNormDist_T_82)
node _intAsRawFloat_adjustedNormDist_T_84 = mux(_intAsRawFloat_adjustedNormDist_T_21, UInt<6>(0h2a), _intAsRawFloat_adjustedNormDist_T_83)
node _intAsRawFloat_adjustedNormDist_T_85 = mux(_intAsRawFloat_adjustedNormDist_T_22, UInt<6>(0h29), _intAsRawFloat_adjustedNormDist_T_84)
node _intAsRawFloat_adjustedNormDist_T_86 = mux(_intAsRawFloat_adjustedNormDist_T_23, UInt<6>(0h28), _intAsRawFloat_adjustedNormDist_T_85)
node _intAsRawFloat_adjustedNormDist_T_87 = mux(_intAsRawFloat_adjustedNormDist_T_24, UInt<6>(0h27), _intAsRawFloat_adjustedNormDist_T_86)
node _intAsRawFloat_adjustedNormDist_T_88 = mux(_intAsRawFloat_adjustedNormDist_T_25, UInt<6>(0h26), _intAsRawFloat_adjustedNormDist_T_87)
node _intAsRawFloat_adjustedNormDist_T_89 = mux(_intAsRawFloat_adjustedNormDist_T_26, UInt<6>(0h25), _intAsRawFloat_adjustedNormDist_T_88)
node _intAsRawFloat_adjustedNormDist_T_90 = mux(_intAsRawFloat_adjustedNormDist_T_27, UInt<6>(0h24), _intAsRawFloat_adjustedNormDist_T_89)
node _intAsRawFloat_adjustedNormDist_T_91 = mux(_intAsRawFloat_adjustedNormDist_T_28, UInt<6>(0h23), _intAsRawFloat_adjustedNormDist_T_90)
node _intAsRawFloat_adjustedNormDist_T_92 = mux(_intAsRawFloat_adjustedNormDist_T_29, UInt<6>(0h22), _intAsRawFloat_adjustedNormDist_T_91)
node _intAsRawFloat_adjustedNormDist_T_93 = mux(_intAsRawFloat_adjustedNormDist_T_30, UInt<6>(0h21), _intAsRawFloat_adjustedNormDist_T_92)
node _intAsRawFloat_adjustedNormDist_T_94 = mux(_intAsRawFloat_adjustedNormDist_T_31, UInt<6>(0h20), _intAsRawFloat_adjustedNormDist_T_93)
node _intAsRawFloat_adjustedNormDist_T_95 = mux(_intAsRawFloat_adjustedNormDist_T_32, UInt<5>(0h1f), _intAsRawFloat_adjustedNormDist_T_94)
node _intAsRawFloat_adjustedNormDist_T_96 = mux(_intAsRawFloat_adjustedNormDist_T_33, UInt<5>(0h1e), _intAsRawFloat_adjustedNormDist_T_95)
node _intAsRawFloat_adjustedNormDist_T_97 = mux(_intAsRawFloat_adjustedNormDist_T_34, UInt<5>(0h1d), _intAsRawFloat_adjustedNormDist_T_96)
node _intAsRawFloat_adjustedNormDist_T_98 = mux(_intAsRawFloat_adjustedNormDist_T_35, UInt<5>(0h1c), _intAsRawFloat_adjustedNormDist_T_97)
node _intAsRawFloat_adjustedNormDist_T_99 = mux(_intAsRawFloat_adjustedNormDist_T_36, UInt<5>(0h1b), _intAsRawFloat_adjustedNormDist_T_98)
node _intAsRawFloat_adjustedNormDist_T_100 = mux(_intAsRawFloat_adjustedNormDist_T_37, UInt<5>(0h1a), _intAsRawFloat_adjustedNormDist_T_99)
node _intAsRawFloat_adjustedNormDist_T_101 = mux(_intAsRawFloat_adjustedNormDist_T_38, UInt<5>(0h19), _intAsRawFloat_adjustedNormDist_T_100)
node _intAsRawFloat_adjustedNormDist_T_102 = mux(_intAsRawFloat_adjustedNormDist_T_39, UInt<5>(0h18), _intAsRawFloat_adjustedNormDist_T_101)
node _intAsRawFloat_adjustedNormDist_T_103 = mux(_intAsRawFloat_adjustedNormDist_T_40, UInt<5>(0h17), _intAsRawFloat_adjustedNormDist_T_102)
node _intAsRawFloat_adjustedNormDist_T_104 = mux(_intAsRawFloat_adjustedNormDist_T_41, UInt<5>(0h16), _intAsRawFloat_adjustedNormDist_T_103)
node _intAsRawFloat_adjustedNormDist_T_105 = mux(_intAsRawFloat_adjustedNormDist_T_42, UInt<5>(0h15), _intAsRawFloat_adjustedNormDist_T_104)
node _intAsRawFloat_adjustedNormDist_T_106 = mux(_intAsRawFloat_adjustedNormDist_T_43, UInt<5>(0h14), _intAsRawFloat_adjustedNormDist_T_105)
node _intAsRawFloat_adjustedNormDist_T_107 = mux(_intAsRawFloat_adjustedNormDist_T_44, UInt<5>(0h13), _intAsRawFloat_adjustedNormDist_T_106)
node _intAsRawFloat_adjustedNormDist_T_108 = mux(_intAsRawFloat_adjustedNormDist_T_45, UInt<5>(0h12), _intAsRawFloat_adjustedNormDist_T_107)
node _intAsRawFloat_adjustedNormDist_T_109 = mux(_intAsRawFloat_adjustedNormDist_T_46, UInt<5>(0h11), _intAsRawFloat_adjustedNormDist_T_108)
node _intAsRawFloat_adjustedNormDist_T_110 = mux(_intAsRawFloat_adjustedNormDist_T_47, UInt<5>(0h10), _intAsRawFloat_adjustedNormDist_T_109)
node _intAsRawFloat_adjustedNormDist_T_111 = mux(_intAsRawFloat_adjustedNormDist_T_48, UInt<4>(0hf), _intAsRawFloat_adjustedNormDist_T_110)
node _intAsRawFloat_adjustedNormDist_T_112 = mux(_intAsRawFloat_adjustedNormDist_T_49, UInt<4>(0he), _intAsRawFloat_adjustedNormDist_T_111)
node _intAsRawFloat_adjustedNormDist_T_113 = mux(_intAsRawFloat_adjustedNormDist_T_50, UInt<4>(0hd), _intAsRawFloat_adjustedNormDist_T_112)
node _intAsRawFloat_adjustedNormDist_T_114 = mux(_intAsRawFloat_adjustedNormDist_T_51, UInt<4>(0hc), _intAsRawFloat_adjustedNormDist_T_113)
node _intAsRawFloat_adjustedNormDist_T_115 = mux(_intAsRawFloat_adjustedNormDist_T_52, UInt<4>(0hb), _intAsRawFloat_adjustedNormDist_T_114)
node _intAsRawFloat_adjustedNormDist_T_116 = mux(_intAsRawFloat_adjustedNormDist_T_53, UInt<4>(0ha), _intAsRawFloat_adjustedNormDist_T_115)
node _intAsRawFloat_adjustedNormDist_T_117 = mux(_intAsRawFloat_adjustedNormDist_T_54, UInt<4>(0h9), _intAsRawFloat_adjustedNormDist_T_116)
node _intAsRawFloat_adjustedNormDist_T_118 = mux(_intAsRawFloat_adjustedNormDist_T_55, UInt<4>(0h8), _intAsRawFloat_adjustedNormDist_T_117)
node _intAsRawFloat_adjustedNormDist_T_119 = mux(_intAsRawFloat_adjustedNormDist_T_56, UInt<3>(0h7), _intAsRawFloat_adjustedNormDist_T_118)
node _intAsRawFloat_adjustedNormDist_T_120 = mux(_intAsRawFloat_adjustedNormDist_T_57, UInt<3>(0h6), _intAsRawFloat_adjustedNormDist_T_119)
node _intAsRawFloat_adjustedNormDist_T_121 = mux(_intAsRawFloat_adjustedNormDist_T_58, UInt<3>(0h5), _intAsRawFloat_adjustedNormDist_T_120)
node _intAsRawFloat_adjustedNormDist_T_122 = mux(_intAsRawFloat_adjustedNormDist_T_59, UInt<3>(0h4), _intAsRawFloat_adjustedNormDist_T_121)
node _intAsRawFloat_adjustedNormDist_T_123 = mux(_intAsRawFloat_adjustedNormDist_T_60, UInt<2>(0h3), _intAsRawFloat_adjustedNormDist_T_122)
node _intAsRawFloat_adjustedNormDist_T_124 = mux(_intAsRawFloat_adjustedNormDist_T_61, UInt<2>(0h2), _intAsRawFloat_adjustedNormDist_T_123)
node _intAsRawFloat_adjustedNormDist_T_125 = mux(_intAsRawFloat_adjustedNormDist_T_62, UInt<1>(0h1), _intAsRawFloat_adjustedNormDist_T_124)
node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_63, UInt<1>(0h0), _intAsRawFloat_adjustedNormDist_T_125)
node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist)
node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 63, 0)
wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<9>, sig : UInt<65>}
connect intAsRawFloat.isNaN, UInt<1>(0h0)
connect intAsRawFloat.isInf, UInt<1>(0h0)
node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 63, 63)
node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0))
connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1
connect intAsRawFloat.sign, intAsRawFloat_sign
node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 5, 0)
node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T)
node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1)
node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2)
connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3
connect intAsRawFloat.sig, intAsRawFloat_sig
inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie7_is64_oe11_os53_7
connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0)
connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig
connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp
connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign
connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero
connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf
connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN
connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundAnyRawFNToRecFN.io.out
connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags | module INToRecFN_i64_e11_s53_7( // @[INToRecFN.scala:43:7]
input io_signedIn, // @[INToRecFN.scala:46:16]
input [63:0] io_in, // @[INToRecFN.scala:46:16]
input [2:0] io_roundingMode, // @[INToRecFN.scala:46:16]
output [64:0] io_out, // @[INToRecFN.scala:46:16]
output [4:0] io_exceptionFlags // @[INToRecFN.scala:46:16]
);
wire io_signedIn_0 = io_signedIn; // @[INToRecFN.scala:43:7]
wire [63:0] io_in_0 = io_in; // @[INToRecFN.scala:43:7]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[INToRecFN.scala:43:7]
wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire io_detectTininess = 1'h1; // @[INToRecFN.scala:43:7]
wire [64:0] io_out_0; // @[INToRecFN.scala:43:7]
wire [4:0] io_exceptionFlags_0; // @[INToRecFN.scala:43:7]
wire _intAsRawFloat_sign_T = io_in_0[63]; // @[rawFloatFromIN.scala:51:34]
wire intAsRawFloat_sign = io_signedIn_0 & _intAsRawFloat_sign_T; // @[rawFloatFromIN.scala:51:{29,34}]
wire intAsRawFloat_sign_0 = intAsRawFloat_sign; // @[rawFloatFromIN.scala:51:29, :59:23]
wire [64:0] _intAsRawFloat_absIn_T = 65'h0 - {1'h0, io_in_0}; // @[rawFloatFromIN.scala:52:31]
wire [63:0] _intAsRawFloat_absIn_T_1 = _intAsRawFloat_absIn_T[63:0]; // @[rawFloatFromIN.scala:52:31]
wire [63:0] intAsRawFloat_absIn = intAsRawFloat_sign ? _intAsRawFloat_absIn_T_1 : io_in_0; // @[rawFloatFromIN.scala:51:29, :52:{24,31}]
wire [127:0] _intAsRawFloat_extAbsIn_T = {64'h0, intAsRawFloat_absIn}; // @[rawFloatFromIN.scala:52:24, :53:44]
wire [63:0] intAsRawFloat_extAbsIn = _intAsRawFloat_extAbsIn_T[63:0]; // @[rawFloatFromIN.scala:53:{44,53}]
wire _intAsRawFloat_adjustedNormDist_T = intAsRawFloat_extAbsIn[0]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_1 = intAsRawFloat_extAbsIn[1]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_2 = intAsRawFloat_extAbsIn[2]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_3 = intAsRawFloat_extAbsIn[3]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_4 = intAsRawFloat_extAbsIn[4]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_5 = intAsRawFloat_extAbsIn[5]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_6 = intAsRawFloat_extAbsIn[6]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_7 = intAsRawFloat_extAbsIn[7]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_8 = intAsRawFloat_extAbsIn[8]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_9 = intAsRawFloat_extAbsIn[9]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_10 = intAsRawFloat_extAbsIn[10]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_11 = intAsRawFloat_extAbsIn[11]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_12 = intAsRawFloat_extAbsIn[12]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_13 = intAsRawFloat_extAbsIn[13]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_14 = intAsRawFloat_extAbsIn[14]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_15 = intAsRawFloat_extAbsIn[15]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_16 = intAsRawFloat_extAbsIn[16]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_17 = intAsRawFloat_extAbsIn[17]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_18 = intAsRawFloat_extAbsIn[18]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_19 = intAsRawFloat_extAbsIn[19]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_20 = intAsRawFloat_extAbsIn[20]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_21 = intAsRawFloat_extAbsIn[21]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_22 = intAsRawFloat_extAbsIn[22]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_23 = intAsRawFloat_extAbsIn[23]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_24 = intAsRawFloat_extAbsIn[24]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_25 = intAsRawFloat_extAbsIn[25]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_26 = intAsRawFloat_extAbsIn[26]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_27 = intAsRawFloat_extAbsIn[27]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_28 = intAsRawFloat_extAbsIn[28]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_29 = intAsRawFloat_extAbsIn[29]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_30 = intAsRawFloat_extAbsIn[30]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_31 = intAsRawFloat_extAbsIn[31]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_32 = intAsRawFloat_extAbsIn[32]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_33 = intAsRawFloat_extAbsIn[33]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_34 = intAsRawFloat_extAbsIn[34]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_35 = intAsRawFloat_extAbsIn[35]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_36 = intAsRawFloat_extAbsIn[36]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_37 = intAsRawFloat_extAbsIn[37]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_38 = intAsRawFloat_extAbsIn[38]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_39 = intAsRawFloat_extAbsIn[39]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_40 = intAsRawFloat_extAbsIn[40]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_41 = intAsRawFloat_extAbsIn[41]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_42 = intAsRawFloat_extAbsIn[42]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_43 = intAsRawFloat_extAbsIn[43]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_44 = intAsRawFloat_extAbsIn[44]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_45 = intAsRawFloat_extAbsIn[45]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_46 = intAsRawFloat_extAbsIn[46]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_47 = intAsRawFloat_extAbsIn[47]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_48 = intAsRawFloat_extAbsIn[48]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_49 = intAsRawFloat_extAbsIn[49]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_50 = intAsRawFloat_extAbsIn[50]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_51 = intAsRawFloat_extAbsIn[51]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_52 = intAsRawFloat_extAbsIn[52]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_53 = intAsRawFloat_extAbsIn[53]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_54 = intAsRawFloat_extAbsIn[54]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_55 = intAsRawFloat_extAbsIn[55]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_56 = intAsRawFloat_extAbsIn[56]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_57 = intAsRawFloat_extAbsIn[57]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_58 = intAsRawFloat_extAbsIn[58]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_59 = intAsRawFloat_extAbsIn[59]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_60 = intAsRawFloat_extAbsIn[60]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_61 = intAsRawFloat_extAbsIn[61]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_62 = intAsRawFloat_extAbsIn[62]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_63 = intAsRawFloat_extAbsIn[63]; // @[rawFloatFromIN.scala:53:53]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_64 = {5'h1F, ~_intAsRawFloat_adjustedNormDist_T_1}; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_65 = _intAsRawFloat_adjustedNormDist_T_2 ? 6'h3D : _intAsRawFloat_adjustedNormDist_T_64; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_66 = _intAsRawFloat_adjustedNormDist_T_3 ? 6'h3C : _intAsRawFloat_adjustedNormDist_T_65; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_67 = _intAsRawFloat_adjustedNormDist_T_4 ? 6'h3B : _intAsRawFloat_adjustedNormDist_T_66; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_68 = _intAsRawFloat_adjustedNormDist_T_5 ? 6'h3A : _intAsRawFloat_adjustedNormDist_T_67; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_69 = _intAsRawFloat_adjustedNormDist_T_6 ? 6'h39 : _intAsRawFloat_adjustedNormDist_T_68; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_70 = _intAsRawFloat_adjustedNormDist_T_7 ? 6'h38 : _intAsRawFloat_adjustedNormDist_T_69; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_71 = _intAsRawFloat_adjustedNormDist_T_8 ? 6'h37 : _intAsRawFloat_adjustedNormDist_T_70; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_72 = _intAsRawFloat_adjustedNormDist_T_9 ? 6'h36 : _intAsRawFloat_adjustedNormDist_T_71; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_73 = _intAsRawFloat_adjustedNormDist_T_10 ? 6'h35 : _intAsRawFloat_adjustedNormDist_T_72; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_74 = _intAsRawFloat_adjustedNormDist_T_11 ? 6'h34 : _intAsRawFloat_adjustedNormDist_T_73; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_75 = _intAsRawFloat_adjustedNormDist_T_12 ? 6'h33 : _intAsRawFloat_adjustedNormDist_T_74; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_76 = _intAsRawFloat_adjustedNormDist_T_13 ? 6'h32 : _intAsRawFloat_adjustedNormDist_T_75; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_77 = _intAsRawFloat_adjustedNormDist_T_14 ? 6'h31 : _intAsRawFloat_adjustedNormDist_T_76; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_78 = _intAsRawFloat_adjustedNormDist_T_15 ? 6'h30 : _intAsRawFloat_adjustedNormDist_T_77; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_79 = _intAsRawFloat_adjustedNormDist_T_16 ? 6'h2F : _intAsRawFloat_adjustedNormDist_T_78; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_80 = _intAsRawFloat_adjustedNormDist_T_17 ? 6'h2E : _intAsRawFloat_adjustedNormDist_T_79; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_81 = _intAsRawFloat_adjustedNormDist_T_18 ? 6'h2D : _intAsRawFloat_adjustedNormDist_T_80; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_82 = _intAsRawFloat_adjustedNormDist_T_19 ? 6'h2C : _intAsRawFloat_adjustedNormDist_T_81; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_83 = _intAsRawFloat_adjustedNormDist_T_20 ? 6'h2B : _intAsRawFloat_adjustedNormDist_T_82; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_84 = _intAsRawFloat_adjustedNormDist_T_21 ? 6'h2A : _intAsRawFloat_adjustedNormDist_T_83; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_85 = _intAsRawFloat_adjustedNormDist_T_22 ? 6'h29 : _intAsRawFloat_adjustedNormDist_T_84; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_86 = _intAsRawFloat_adjustedNormDist_T_23 ? 6'h28 : _intAsRawFloat_adjustedNormDist_T_85; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_87 = _intAsRawFloat_adjustedNormDist_T_24 ? 6'h27 : _intAsRawFloat_adjustedNormDist_T_86; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_88 = _intAsRawFloat_adjustedNormDist_T_25 ? 6'h26 : _intAsRawFloat_adjustedNormDist_T_87; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_89 = _intAsRawFloat_adjustedNormDist_T_26 ? 6'h25 : _intAsRawFloat_adjustedNormDist_T_88; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_90 = _intAsRawFloat_adjustedNormDist_T_27 ? 6'h24 : _intAsRawFloat_adjustedNormDist_T_89; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_91 = _intAsRawFloat_adjustedNormDist_T_28 ? 6'h23 : _intAsRawFloat_adjustedNormDist_T_90; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_92 = _intAsRawFloat_adjustedNormDist_T_29 ? 6'h22 : _intAsRawFloat_adjustedNormDist_T_91; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_93 = _intAsRawFloat_adjustedNormDist_T_30 ? 6'h21 : _intAsRawFloat_adjustedNormDist_T_92; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_94 = _intAsRawFloat_adjustedNormDist_T_31 ? 6'h20 : _intAsRawFloat_adjustedNormDist_T_93; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_95 = _intAsRawFloat_adjustedNormDist_T_32 ? 6'h1F : _intAsRawFloat_adjustedNormDist_T_94; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_96 = _intAsRawFloat_adjustedNormDist_T_33 ? 6'h1E : _intAsRawFloat_adjustedNormDist_T_95; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_97 = _intAsRawFloat_adjustedNormDist_T_34 ? 6'h1D : _intAsRawFloat_adjustedNormDist_T_96; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_98 = _intAsRawFloat_adjustedNormDist_T_35 ? 6'h1C : _intAsRawFloat_adjustedNormDist_T_97; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_99 = _intAsRawFloat_adjustedNormDist_T_36 ? 6'h1B : _intAsRawFloat_adjustedNormDist_T_98; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_100 = _intAsRawFloat_adjustedNormDist_T_37 ? 6'h1A : _intAsRawFloat_adjustedNormDist_T_99; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_101 = _intAsRawFloat_adjustedNormDist_T_38 ? 6'h19 : _intAsRawFloat_adjustedNormDist_T_100; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_102 = _intAsRawFloat_adjustedNormDist_T_39 ? 6'h18 : _intAsRawFloat_adjustedNormDist_T_101; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_103 = _intAsRawFloat_adjustedNormDist_T_40 ? 6'h17 : _intAsRawFloat_adjustedNormDist_T_102; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_104 = _intAsRawFloat_adjustedNormDist_T_41 ? 6'h16 : _intAsRawFloat_adjustedNormDist_T_103; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_105 = _intAsRawFloat_adjustedNormDist_T_42 ? 6'h15 : _intAsRawFloat_adjustedNormDist_T_104; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_106 = _intAsRawFloat_adjustedNormDist_T_43 ? 6'h14 : _intAsRawFloat_adjustedNormDist_T_105; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_107 = _intAsRawFloat_adjustedNormDist_T_44 ? 6'h13 : _intAsRawFloat_adjustedNormDist_T_106; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_108 = _intAsRawFloat_adjustedNormDist_T_45 ? 6'h12 : _intAsRawFloat_adjustedNormDist_T_107; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_109 = _intAsRawFloat_adjustedNormDist_T_46 ? 6'h11 : _intAsRawFloat_adjustedNormDist_T_108; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_110 = _intAsRawFloat_adjustedNormDist_T_47 ? 6'h10 : _intAsRawFloat_adjustedNormDist_T_109; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_111 = _intAsRawFloat_adjustedNormDist_T_48 ? 6'hF : _intAsRawFloat_adjustedNormDist_T_110; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_112 = _intAsRawFloat_adjustedNormDist_T_49 ? 6'hE : _intAsRawFloat_adjustedNormDist_T_111; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_113 = _intAsRawFloat_adjustedNormDist_T_50 ? 6'hD : _intAsRawFloat_adjustedNormDist_T_112; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_114 = _intAsRawFloat_adjustedNormDist_T_51 ? 6'hC : _intAsRawFloat_adjustedNormDist_T_113; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_115 = _intAsRawFloat_adjustedNormDist_T_52 ? 6'hB : _intAsRawFloat_adjustedNormDist_T_114; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_116 = _intAsRawFloat_adjustedNormDist_T_53 ? 6'hA : _intAsRawFloat_adjustedNormDist_T_115; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_117 = _intAsRawFloat_adjustedNormDist_T_54 ? 6'h9 : _intAsRawFloat_adjustedNormDist_T_116; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_118 = _intAsRawFloat_adjustedNormDist_T_55 ? 6'h8 : _intAsRawFloat_adjustedNormDist_T_117; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_119 = _intAsRawFloat_adjustedNormDist_T_56 ? 6'h7 : _intAsRawFloat_adjustedNormDist_T_118; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_120 = _intAsRawFloat_adjustedNormDist_T_57 ? 6'h6 : _intAsRawFloat_adjustedNormDist_T_119; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_121 = _intAsRawFloat_adjustedNormDist_T_58 ? 6'h5 : _intAsRawFloat_adjustedNormDist_T_120; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_122 = _intAsRawFloat_adjustedNormDist_T_59 ? 6'h4 : _intAsRawFloat_adjustedNormDist_T_121; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_123 = _intAsRawFloat_adjustedNormDist_T_60 ? 6'h3 : _intAsRawFloat_adjustedNormDist_T_122; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_124 = _intAsRawFloat_adjustedNormDist_T_61 ? 6'h2 : _intAsRawFloat_adjustedNormDist_T_123; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_125 = _intAsRawFloat_adjustedNormDist_T_62 ? 6'h1 : _intAsRawFloat_adjustedNormDist_T_124; // @[Mux.scala:50:70]
wire [5:0] intAsRawFloat_adjustedNormDist = _intAsRawFloat_adjustedNormDist_T_63 ? 6'h0 : _intAsRawFloat_adjustedNormDist_T_125; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_out_sExp_T = intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70]
wire [126:0] _intAsRawFloat_sig_T = {63'h0, intAsRawFloat_extAbsIn} << intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70]
wire [63:0] intAsRawFloat_sig = _intAsRawFloat_sig_T[63:0]; // @[rawFloatFromIN.scala:56:{22,41}]
wire _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:62:23]
wire [8:0] _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:64:72]
wire intAsRawFloat_isZero; // @[rawFloatFromIN.scala:59:23]
wire [8:0] intAsRawFloat_sExp; // @[rawFloatFromIN.scala:59:23]
wire [64:0] intAsRawFloat_sig_0; // @[rawFloatFromIN.scala:59:23]
wire _intAsRawFloat_out_isZero_T = intAsRawFloat_sig[63]; // @[rawFloatFromIN.scala:56:41, :62:28]
assign _intAsRawFloat_out_isZero_T_1 = ~_intAsRawFloat_out_isZero_T; // @[rawFloatFromIN.scala:62:{23,28}]
assign intAsRawFloat_isZero = _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:59:23, :62:23]
wire [5:0] _intAsRawFloat_out_sExp_T_1 = ~_intAsRawFloat_out_sExp_T; // @[rawFloatFromIN.scala:64:{36,53}]
wire [7:0] _intAsRawFloat_out_sExp_T_2 = {2'h2, _intAsRawFloat_out_sExp_T_1}; // @[rawFloatFromIN.scala:64:{33,36}]
assign _intAsRawFloat_out_sExp_T_3 = {1'h0, _intAsRawFloat_out_sExp_T_2}; // @[rawFloatFromIN.scala:64:{33,72}]
assign intAsRawFloat_sExp = _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:59:23, :64:72]
assign intAsRawFloat_sig_0 = {1'h0, intAsRawFloat_sig}; // @[rawFloatFromIN.scala:56:41, :59:23, :65:20]
RoundAnyRawFNToRecFN_ie7_is64_oe11_os53_7 roundAnyRawFNToRecFN ( // @[INToRecFN.scala:60:15]
.io_in_isZero (intAsRawFloat_isZero), // @[rawFloatFromIN.scala:59:23]
.io_in_sign (intAsRawFloat_sign_0), // @[rawFloatFromIN.scala:59:23]
.io_in_sExp (intAsRawFloat_sExp), // @[rawFloatFromIN.scala:59:23]
.io_in_sig (intAsRawFloat_sig_0), // @[rawFloatFromIN.scala:59:23]
.io_roundingMode (io_roundingMode_0), // @[INToRecFN.scala:43:7]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[INToRecFN.scala:60:15]
assign io_out = io_out_0; // @[INToRecFN.scala:43:7]
assign io_exceptionFlags = io_exceptionFlags_0; // @[INToRecFN.scala:43:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_52 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<6>(0h22))
wire _source_ok_WIRE : UInt<1>[21]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
connect _source_ok_WIRE[7], _source_ok_T_27
connect _source_ok_WIRE[8], _source_ok_T_28
connect _source_ok_WIRE[9], _source_ok_T_29
connect _source_ok_WIRE[10], _source_ok_T_30
connect _source_ok_WIRE[11], _source_ok_T_31
connect _source_ok_WIRE[12], _source_ok_T_32
connect _source_ok_WIRE[13], _source_ok_T_33
connect _source_ok_WIRE[14], _source_ok_T_34
connect _source_ok_WIRE[15], _source_ok_T_35
connect _source_ok_WIRE[16], _source_ok_T_36
connect _source_ok_WIRE[17], _source_ok_T_37
connect _source_ok_WIRE[18], _source_ok_T_38
connect _source_ok_WIRE[19], _source_ok_T_39
connect _source_ok_WIRE[20], _source_ok_T_40
node _source_ok_T_41 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[2])
node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[3])
node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[4])
node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[5])
node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[6])
node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[7])
node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[8])
node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[9])
node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[10])
node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[11])
node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[12])
node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[13])
node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[14])
node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE[15])
node _source_ok_T_56 = or(_source_ok_T_55, _source_ok_WIRE[16])
node _source_ok_T_57 = or(_source_ok_T_56, _source_ok_WIRE[17])
node _source_ok_T_58 = or(_source_ok_T_57, _source_ok_WIRE[18])
node _source_ok_T_59 = or(_source_ok_T_58, _source_ok_WIRE[19])
node source_ok = or(_source_ok_T_59, _source_ok_WIRE[20])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_81 = eq(_T_80, UInt<1>(0h0))
node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_83 = cvt(_T_82)
node _T_84 = and(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = asSInt(_T_84)
node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = or(_T_81, _T_86)
node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_89 = eq(_T_88, UInt<1>(0h0))
node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<1>(0h0)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_89, _T_94)
node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_99 = cvt(_T_98)
node _T_100 = and(_T_99, asSInt(UInt<1>(0h0)))
node _T_101 = asSInt(_T_100)
node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = or(_T_97, _T_102)
node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_105 = eq(_T_104, UInt<1>(0h0))
node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_107 = cvt(_T_106)
node _T_108 = and(_T_107, asSInt(UInt<1>(0h0)))
node _T_109 = asSInt(_T_108)
node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = or(_T_105, _T_110)
node _T_112 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_113 = eq(_T_112, UInt<1>(0h0))
node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_115 = cvt(_T_114)
node _T_116 = and(_T_115, asSInt(UInt<1>(0h0)))
node _T_117 = asSInt(_T_116)
node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0)))
node _T_119 = or(_T_113, _T_118)
node _T_120 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_123 = cvt(_T_122)
node _T_124 = and(_T_123, asSInt(UInt<1>(0h0)))
node _T_125 = asSInt(_T_124)
node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0)))
node _T_127 = or(_T_121, _T_126)
node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_129 = eq(_T_128, UInt<1>(0h0))
node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_131 = cvt(_T_130)
node _T_132 = and(_T_131, asSInt(UInt<1>(0h0)))
node _T_133 = asSInt(_T_132)
node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0)))
node _T_135 = or(_T_129, _T_134)
node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_137 = eq(_T_136, UInt<1>(0h0))
node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_139 = cvt(_T_138)
node _T_140 = and(_T_139, asSInt(UInt<1>(0h0)))
node _T_141 = asSInt(_T_140)
node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0)))
node _T_143 = or(_T_137, _T_142)
node _T_144 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_145 = eq(_T_144, UInt<1>(0h0))
node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_147 = cvt(_T_146)
node _T_148 = and(_T_147, asSInt(UInt<1>(0h0)))
node _T_149 = asSInt(_T_148)
node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0)))
node _T_151 = or(_T_145, _T_150)
node _T_152 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_155 = cvt(_T_154)
node _T_156 = and(_T_155, asSInt(UInt<1>(0h0)))
node _T_157 = asSInt(_T_156)
node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0)))
node _T_159 = or(_T_153, _T_158)
node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_161 = eq(_T_160, UInt<1>(0h0))
node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_163 = cvt(_T_162)
node _T_164 = and(_T_163, asSInt(UInt<1>(0h0)))
node _T_165 = asSInt(_T_164)
node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0)))
node _T_167 = or(_T_161, _T_166)
node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_169 = eq(_T_168, UInt<1>(0h0))
node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_171 = cvt(_T_170)
node _T_172 = and(_T_171, asSInt(UInt<1>(0h0)))
node _T_173 = asSInt(_T_172)
node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0)))
node _T_175 = or(_T_169, _T_174)
node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_177 = eq(_T_176, UInt<1>(0h0))
node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_179 = cvt(_T_178)
node _T_180 = and(_T_179, asSInt(UInt<1>(0h0)))
node _T_181 = asSInt(_T_180)
node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0)))
node _T_183 = or(_T_177, _T_182)
node _T_184 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_185 = eq(_T_184, UInt<1>(0h0))
node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_187 = cvt(_T_186)
node _T_188 = and(_T_187, asSInt(UInt<1>(0h0)))
node _T_189 = asSInt(_T_188)
node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0)))
node _T_191 = or(_T_185, _T_190)
node _T_192 = and(_T_11, _T_24)
node _T_193 = and(_T_192, _T_37)
node _T_194 = and(_T_193, _T_50)
node _T_195 = and(_T_194, _T_63)
node _T_196 = and(_T_195, _T_71)
node _T_197 = and(_T_196, _T_79)
node _T_198 = and(_T_197, _T_87)
node _T_199 = and(_T_198, _T_95)
node _T_200 = and(_T_199, _T_103)
node _T_201 = and(_T_200, _T_111)
node _T_202 = and(_T_201, _T_119)
node _T_203 = and(_T_202, _T_127)
node _T_204 = and(_T_203, _T_135)
node _T_205 = and(_T_204, _T_143)
node _T_206 = and(_T_205, _T_151)
node _T_207 = and(_T_206, _T_159)
node _T_208 = and(_T_207, _T_167)
node _T_209 = and(_T_208, _T_175)
node _T_210 = and(_T_209, _T_183)
node _T_211 = and(_T_210, _T_191)
node _T_212 = asUInt(reset)
node _T_213 = eq(_T_212, UInt<1>(0h0))
when _T_213 :
node _T_214 = eq(_T_211, UInt<1>(0h0))
when _T_214 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_211, UInt<1>(0h1), "") : assert_1
node _T_215 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_215 :
node _T_216 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_217 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_218 = and(_T_216, _T_217)
node _T_219 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_220 = shr(io.in.a.bits.source, 2)
node _T_221 = eq(_T_220, UInt<1>(0h0))
node _T_222 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_223 = and(_T_221, _T_222)
node _T_224 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_225 = and(_T_223, _T_224)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_226 = shr(io.in.a.bits.source, 2)
node _T_227 = eq(_T_226, UInt<1>(0h1))
node _T_228 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_229 = and(_T_227, _T_228)
node _T_230 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_231 = and(_T_229, _T_230)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_232 = shr(io.in.a.bits.source, 2)
node _T_233 = eq(_T_232, UInt<2>(0h2))
node _T_234 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_235 = and(_T_233, _T_234)
node _T_236 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_237 = and(_T_235, _T_236)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_238 = shr(io.in.a.bits.source, 2)
node _T_239 = eq(_T_238, UInt<2>(0h3))
node _T_240 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_241 = and(_T_239, _T_240)
node _T_242 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_243 = and(_T_241, _T_242)
node _T_244 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_245 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_246 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_247 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_249 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_250 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_251 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_252 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_253 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_254 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_255 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_256 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_257 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_258 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_259 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_260 = or(_T_219, _T_225)
node _T_261 = or(_T_260, _T_231)
node _T_262 = or(_T_261, _T_237)
node _T_263 = or(_T_262, _T_243)
node _T_264 = or(_T_263, _T_244)
node _T_265 = or(_T_264, _T_245)
node _T_266 = or(_T_265, _T_246)
node _T_267 = or(_T_266, _T_247)
node _T_268 = or(_T_267, _T_248)
node _T_269 = or(_T_268, _T_249)
node _T_270 = or(_T_269, _T_250)
node _T_271 = or(_T_270, _T_251)
node _T_272 = or(_T_271, _T_252)
node _T_273 = or(_T_272, _T_253)
node _T_274 = or(_T_273, _T_254)
node _T_275 = or(_T_274, _T_255)
node _T_276 = or(_T_275, _T_256)
node _T_277 = or(_T_276, _T_257)
node _T_278 = or(_T_277, _T_258)
node _T_279 = or(_T_278, _T_259)
node _T_280 = and(_T_218, _T_279)
node _T_281 = or(UInt<1>(0h0), _T_280)
node _T_282 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_283 = or(UInt<1>(0h0), _T_282)
node _T_284 = xor(io.in.a.bits.address, UInt<28>(0h8000080))
node _T_285 = cvt(_T_284)
node _T_286 = and(_T_285, asSInt(UInt<17>(0h100c0)))
node _T_287 = asSInt(_T_286)
node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0)))
node _T_289 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_290 = cvt(_T_289)
node _T_291 = and(_T_290, asSInt(UInt<29>(0h100000c0)))
node _T_292 = asSInt(_T_291)
node _T_293 = eq(_T_292, asSInt(UInt<1>(0h0)))
node _T_294 = or(_T_288, _T_293)
node _T_295 = and(_T_283, _T_294)
node _T_296 = or(UInt<1>(0h0), _T_295)
node _T_297 = and(_T_281, _T_296)
node _T_298 = asUInt(reset)
node _T_299 = eq(_T_298, UInt<1>(0h0))
when _T_299 :
node _T_300 = eq(_T_297, UInt<1>(0h0))
when _T_300 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_297, UInt<1>(0h1), "") : assert_2
node _T_301 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_302 = shr(io.in.a.bits.source, 2)
node _T_303 = eq(_T_302, UInt<1>(0h0))
node _T_304 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_305 = and(_T_303, _T_304)
node _T_306 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_307 = and(_T_305, _T_306)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_308 = shr(io.in.a.bits.source, 2)
node _T_309 = eq(_T_308, UInt<1>(0h1))
node _T_310 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_311 = and(_T_309, _T_310)
node _T_312 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_313 = and(_T_311, _T_312)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_314 = shr(io.in.a.bits.source, 2)
node _T_315 = eq(_T_314, UInt<2>(0h2))
node _T_316 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_317 = and(_T_315, _T_316)
node _T_318 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_319 = and(_T_317, _T_318)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_320 = shr(io.in.a.bits.source, 2)
node _T_321 = eq(_T_320, UInt<2>(0h3))
node _T_322 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_323 = and(_T_321, _T_322)
node _T_324 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_325 = and(_T_323, _T_324)
node _T_326 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_330 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_331 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_332 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_333 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_334 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_335 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_336 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_337 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_338 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_339 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_340 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_341 = eq(io.in.a.bits.source, UInt<6>(0h22))
wire _WIRE : UInt<1>[21]
connect _WIRE[0], _T_301
connect _WIRE[1], _T_307
connect _WIRE[2], _T_313
connect _WIRE[3], _T_319
connect _WIRE[4], _T_325
connect _WIRE[5], _T_326
connect _WIRE[6], _T_327
connect _WIRE[7], _T_328
connect _WIRE[8], _T_329
connect _WIRE[9], _T_330
connect _WIRE[10], _T_331
connect _WIRE[11], _T_332
connect _WIRE[12], _T_333
connect _WIRE[13], _T_334
connect _WIRE[14], _T_335
connect _WIRE[15], _T_336
connect _WIRE[16], _T_337
connect _WIRE[17], _T_338
connect _WIRE[18], _T_339
connect _WIRE[19], _T_340
connect _WIRE[20], _T_341
node _T_342 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_343 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_344 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_345 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_346 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_347 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_348 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_349 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_350 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_351 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_352 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_353 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_354 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_355 = mux(_WIRE[5], _T_342, UInt<1>(0h0))
node _T_356 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_357 = mux(_WIRE[7], _T_343, UInt<1>(0h0))
node _T_358 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_359 = mux(_WIRE[9], _T_344, UInt<1>(0h0))
node _T_360 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_361 = mux(_WIRE[11], _T_345, UInt<1>(0h0))
node _T_362 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_363 = mux(_WIRE[13], _T_346, UInt<1>(0h0))
node _T_364 = mux(_WIRE[14], UInt<1>(0h0), UInt<1>(0h0))
node _T_365 = mux(_WIRE[15], _T_347, UInt<1>(0h0))
node _T_366 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_367 = mux(_WIRE[17], _T_348, UInt<1>(0h0))
node _T_368 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0))
node _T_369 = mux(_WIRE[19], _T_349, UInt<1>(0h0))
node _T_370 = mux(_WIRE[20], UInt<1>(0h0), UInt<1>(0h0))
node _T_371 = or(_T_350, _T_351)
node _T_372 = or(_T_371, _T_352)
node _T_373 = or(_T_372, _T_353)
node _T_374 = or(_T_373, _T_354)
node _T_375 = or(_T_374, _T_355)
node _T_376 = or(_T_375, _T_356)
node _T_377 = or(_T_376, _T_357)
node _T_378 = or(_T_377, _T_358)
node _T_379 = or(_T_378, _T_359)
node _T_380 = or(_T_379, _T_360)
node _T_381 = or(_T_380, _T_361)
node _T_382 = or(_T_381, _T_362)
node _T_383 = or(_T_382, _T_363)
node _T_384 = or(_T_383, _T_364)
node _T_385 = or(_T_384, _T_365)
node _T_386 = or(_T_385, _T_366)
node _T_387 = or(_T_386, _T_367)
node _T_388 = or(_T_387, _T_368)
node _T_389 = or(_T_388, _T_369)
node _T_390 = or(_T_389, _T_370)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_390
node _T_391 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_392 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_393 = and(_T_391, _T_392)
node _T_394 = or(UInt<1>(0h0), _T_393)
node _T_395 = xor(io.in.a.bits.address, UInt<28>(0h8000080))
node _T_396 = cvt(_T_395)
node _T_397 = and(_T_396, asSInt(UInt<17>(0h100c0)))
node _T_398 = asSInt(_T_397)
node _T_399 = eq(_T_398, asSInt(UInt<1>(0h0)))
node _T_400 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_401 = cvt(_T_400)
node _T_402 = and(_T_401, asSInt(UInt<29>(0h100000c0)))
node _T_403 = asSInt(_T_402)
node _T_404 = eq(_T_403, asSInt(UInt<1>(0h0)))
node _T_405 = or(_T_399, _T_404)
node _T_406 = and(_T_394, _T_405)
node _T_407 = or(UInt<1>(0h0), _T_406)
node _T_408 = and(_WIRE_1, _T_407)
node _T_409 = asUInt(reset)
node _T_410 = eq(_T_409, UInt<1>(0h0))
when _T_410 :
node _T_411 = eq(_T_408, UInt<1>(0h0))
when _T_411 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_408, UInt<1>(0h1), "") : assert_3
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(source_ok, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_415 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_416 = asUInt(reset)
node _T_417 = eq(_T_416, UInt<1>(0h0))
when _T_417 :
node _T_418 = eq(_T_415, UInt<1>(0h0))
when _T_418 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_415, UInt<1>(0h1), "") : assert_5
node _T_419 = asUInt(reset)
node _T_420 = eq(_T_419, UInt<1>(0h0))
when _T_420 :
node _T_421 = eq(is_aligned, UInt<1>(0h0))
when _T_421 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_422 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_423 = asUInt(reset)
node _T_424 = eq(_T_423, UInt<1>(0h0))
when _T_424 :
node _T_425 = eq(_T_422, UInt<1>(0h0))
when _T_425 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_422, UInt<1>(0h1), "") : assert_7
node _T_426 = not(io.in.a.bits.mask)
node _T_427 = eq(_T_426, UInt<1>(0h0))
node _T_428 = asUInt(reset)
node _T_429 = eq(_T_428, UInt<1>(0h0))
when _T_429 :
node _T_430 = eq(_T_427, UInt<1>(0h0))
when _T_430 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_427, UInt<1>(0h1), "") : assert_8
node _T_431 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_432 = asUInt(reset)
node _T_433 = eq(_T_432, UInt<1>(0h0))
when _T_433 :
node _T_434 = eq(_T_431, UInt<1>(0h0))
when _T_434 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_431, UInt<1>(0h1), "") : assert_9
node _T_435 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_435 :
node _T_436 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_437 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_438 = and(_T_436, _T_437)
node _T_439 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_440 = shr(io.in.a.bits.source, 2)
node _T_441 = eq(_T_440, UInt<1>(0h0))
node _T_442 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_443 = and(_T_441, _T_442)
node _T_444 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_445 = and(_T_443, _T_444)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_446 = shr(io.in.a.bits.source, 2)
node _T_447 = eq(_T_446, UInt<1>(0h1))
node _T_448 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_449 = and(_T_447, _T_448)
node _T_450 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_451 = and(_T_449, _T_450)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_452 = shr(io.in.a.bits.source, 2)
node _T_453 = eq(_T_452, UInt<2>(0h2))
node _T_454 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_455 = and(_T_453, _T_454)
node _T_456 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_457 = and(_T_455, _T_456)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_458 = shr(io.in.a.bits.source, 2)
node _T_459 = eq(_T_458, UInt<2>(0h3))
node _T_460 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_461 = and(_T_459, _T_460)
node _T_462 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_463 = and(_T_461, _T_462)
node _T_464 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_465 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_466 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_467 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_468 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_469 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_470 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_471 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_472 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_473 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_474 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_475 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_476 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_477 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_478 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_479 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_480 = or(_T_439, _T_445)
node _T_481 = or(_T_480, _T_451)
node _T_482 = or(_T_481, _T_457)
node _T_483 = or(_T_482, _T_463)
node _T_484 = or(_T_483, _T_464)
node _T_485 = or(_T_484, _T_465)
node _T_486 = or(_T_485, _T_466)
node _T_487 = or(_T_486, _T_467)
node _T_488 = or(_T_487, _T_468)
node _T_489 = or(_T_488, _T_469)
node _T_490 = or(_T_489, _T_470)
node _T_491 = or(_T_490, _T_471)
node _T_492 = or(_T_491, _T_472)
node _T_493 = or(_T_492, _T_473)
node _T_494 = or(_T_493, _T_474)
node _T_495 = or(_T_494, _T_475)
node _T_496 = or(_T_495, _T_476)
node _T_497 = or(_T_496, _T_477)
node _T_498 = or(_T_497, _T_478)
node _T_499 = or(_T_498, _T_479)
node _T_500 = and(_T_438, _T_499)
node _T_501 = or(UInt<1>(0h0), _T_500)
node _T_502 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_503 = or(UInt<1>(0h0), _T_502)
node _T_504 = xor(io.in.a.bits.address, UInt<28>(0h8000080))
node _T_505 = cvt(_T_504)
node _T_506 = and(_T_505, asSInt(UInt<17>(0h100c0)))
node _T_507 = asSInt(_T_506)
node _T_508 = eq(_T_507, asSInt(UInt<1>(0h0)))
node _T_509 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_510 = cvt(_T_509)
node _T_511 = and(_T_510, asSInt(UInt<29>(0h100000c0)))
node _T_512 = asSInt(_T_511)
node _T_513 = eq(_T_512, asSInt(UInt<1>(0h0)))
node _T_514 = or(_T_508, _T_513)
node _T_515 = and(_T_503, _T_514)
node _T_516 = or(UInt<1>(0h0), _T_515)
node _T_517 = and(_T_501, _T_516)
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_517, UInt<1>(0h1), "") : assert_10
node _T_521 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_522 = shr(io.in.a.bits.source, 2)
node _T_523 = eq(_T_522, UInt<1>(0h0))
node _T_524 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_525 = and(_T_523, _T_524)
node _T_526 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_527 = and(_T_525, _T_526)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_528 = shr(io.in.a.bits.source, 2)
node _T_529 = eq(_T_528, UInt<1>(0h1))
node _T_530 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_531 = and(_T_529, _T_530)
node _T_532 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_533 = and(_T_531, _T_532)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_534 = shr(io.in.a.bits.source, 2)
node _T_535 = eq(_T_534, UInt<2>(0h2))
node _T_536 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_537 = and(_T_535, _T_536)
node _T_538 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_539 = and(_T_537, _T_538)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_540 = shr(io.in.a.bits.source, 2)
node _T_541 = eq(_T_540, UInt<2>(0h3))
node _T_542 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_543 = and(_T_541, _T_542)
node _T_544 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_545 = and(_T_543, _T_544)
node _T_546 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_547 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_548 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_549 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_550 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_551 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_552 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_553 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_554 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_555 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_556 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_557 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_558 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_559 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_560 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_561 = eq(io.in.a.bits.source, UInt<6>(0h22))
wire _WIRE_2 : UInt<1>[21]
connect _WIRE_2[0], _T_521
connect _WIRE_2[1], _T_527
connect _WIRE_2[2], _T_533
connect _WIRE_2[3], _T_539
connect _WIRE_2[4], _T_545
connect _WIRE_2[5], _T_546
connect _WIRE_2[6], _T_547
connect _WIRE_2[7], _T_548
connect _WIRE_2[8], _T_549
connect _WIRE_2[9], _T_550
connect _WIRE_2[10], _T_551
connect _WIRE_2[11], _T_552
connect _WIRE_2[12], _T_553
connect _WIRE_2[13], _T_554
connect _WIRE_2[14], _T_555
connect _WIRE_2[15], _T_556
connect _WIRE_2[16], _T_557
connect _WIRE_2[17], _T_558
connect _WIRE_2[18], _T_559
connect _WIRE_2[19], _T_560
connect _WIRE_2[20], _T_561
node _T_562 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_563 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_564 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_565 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_566 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_567 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_568 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_569 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_570 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_571 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_572 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_573 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_574 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_575 = mux(_WIRE_2[5], _T_562, UInt<1>(0h0))
node _T_576 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_577 = mux(_WIRE_2[7], _T_563, UInt<1>(0h0))
node _T_578 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_579 = mux(_WIRE_2[9], _T_564, UInt<1>(0h0))
node _T_580 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_581 = mux(_WIRE_2[11], _T_565, UInt<1>(0h0))
node _T_582 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_583 = mux(_WIRE_2[13], _T_566, UInt<1>(0h0))
node _T_584 = mux(_WIRE_2[14], UInt<1>(0h0), UInt<1>(0h0))
node _T_585 = mux(_WIRE_2[15], _T_567, UInt<1>(0h0))
node _T_586 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_587 = mux(_WIRE_2[17], _T_568, UInt<1>(0h0))
node _T_588 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0))
node _T_589 = mux(_WIRE_2[19], _T_569, UInt<1>(0h0))
node _T_590 = mux(_WIRE_2[20], UInt<1>(0h0), UInt<1>(0h0))
node _T_591 = or(_T_570, _T_571)
node _T_592 = or(_T_591, _T_572)
node _T_593 = or(_T_592, _T_573)
node _T_594 = or(_T_593, _T_574)
node _T_595 = or(_T_594, _T_575)
node _T_596 = or(_T_595, _T_576)
node _T_597 = or(_T_596, _T_577)
node _T_598 = or(_T_597, _T_578)
node _T_599 = or(_T_598, _T_579)
node _T_600 = or(_T_599, _T_580)
node _T_601 = or(_T_600, _T_581)
node _T_602 = or(_T_601, _T_582)
node _T_603 = or(_T_602, _T_583)
node _T_604 = or(_T_603, _T_584)
node _T_605 = or(_T_604, _T_585)
node _T_606 = or(_T_605, _T_586)
node _T_607 = or(_T_606, _T_587)
node _T_608 = or(_T_607, _T_588)
node _T_609 = or(_T_608, _T_589)
node _T_610 = or(_T_609, _T_590)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_610
node _T_611 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_612 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_613 = and(_T_611, _T_612)
node _T_614 = or(UInt<1>(0h0), _T_613)
node _T_615 = xor(io.in.a.bits.address, UInt<28>(0h8000080))
node _T_616 = cvt(_T_615)
node _T_617 = and(_T_616, asSInt(UInt<17>(0h100c0)))
node _T_618 = asSInt(_T_617)
node _T_619 = eq(_T_618, asSInt(UInt<1>(0h0)))
node _T_620 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_621 = cvt(_T_620)
node _T_622 = and(_T_621, asSInt(UInt<29>(0h100000c0)))
node _T_623 = asSInt(_T_622)
node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0)))
node _T_625 = or(_T_619, _T_624)
node _T_626 = and(_T_614, _T_625)
node _T_627 = or(UInt<1>(0h0), _T_626)
node _T_628 = and(_WIRE_3, _T_627)
node _T_629 = asUInt(reset)
node _T_630 = eq(_T_629, UInt<1>(0h0))
when _T_630 :
node _T_631 = eq(_T_628, UInt<1>(0h0))
when _T_631 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_628, UInt<1>(0h1), "") : assert_11
node _T_632 = asUInt(reset)
node _T_633 = eq(_T_632, UInt<1>(0h0))
when _T_633 :
node _T_634 = eq(source_ok, UInt<1>(0h0))
when _T_634 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_635 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_636 = asUInt(reset)
node _T_637 = eq(_T_636, UInt<1>(0h0))
when _T_637 :
node _T_638 = eq(_T_635, UInt<1>(0h0))
when _T_638 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_635, UInt<1>(0h1), "") : assert_13
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(is_aligned, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_642 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_643 = asUInt(reset)
node _T_644 = eq(_T_643, UInt<1>(0h0))
when _T_644 :
node _T_645 = eq(_T_642, UInt<1>(0h0))
when _T_645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_642, UInt<1>(0h1), "") : assert_15
node _T_646 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_647 = asUInt(reset)
node _T_648 = eq(_T_647, UInt<1>(0h0))
when _T_648 :
node _T_649 = eq(_T_646, UInt<1>(0h0))
when _T_649 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_646, UInt<1>(0h1), "") : assert_16
node _T_650 = not(io.in.a.bits.mask)
node _T_651 = eq(_T_650, UInt<1>(0h0))
node _T_652 = asUInt(reset)
node _T_653 = eq(_T_652, UInt<1>(0h0))
when _T_653 :
node _T_654 = eq(_T_651, UInt<1>(0h0))
when _T_654 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_651, UInt<1>(0h1), "") : assert_17
node _T_655 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_656 = asUInt(reset)
node _T_657 = eq(_T_656, UInt<1>(0h0))
when _T_657 :
node _T_658 = eq(_T_655, UInt<1>(0h0))
when _T_658 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_655, UInt<1>(0h1), "") : assert_18
node _T_659 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_659 :
node _T_660 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_661 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_662 = and(_T_660, _T_661)
node _T_663 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_664 = shr(io.in.a.bits.source, 2)
node _T_665 = eq(_T_664, UInt<1>(0h0))
node _T_666 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_667 = and(_T_665, _T_666)
node _T_668 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_669 = and(_T_667, _T_668)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_670 = shr(io.in.a.bits.source, 2)
node _T_671 = eq(_T_670, UInt<1>(0h1))
node _T_672 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_673 = and(_T_671, _T_672)
node _T_674 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_675 = and(_T_673, _T_674)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_676 = shr(io.in.a.bits.source, 2)
node _T_677 = eq(_T_676, UInt<2>(0h2))
node _T_678 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_679 = and(_T_677, _T_678)
node _T_680 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_681 = and(_T_679, _T_680)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_682 = shr(io.in.a.bits.source, 2)
node _T_683 = eq(_T_682, UInt<2>(0h3))
node _T_684 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_685 = and(_T_683, _T_684)
node _T_686 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_687 = and(_T_685, _T_686)
node _T_688 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_689 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_690 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_691 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_692 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_693 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_694 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_695 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_696 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_697 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_698 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_699 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_700 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_701 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_702 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_703 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_704 = or(_T_663, _T_669)
node _T_705 = or(_T_704, _T_675)
node _T_706 = or(_T_705, _T_681)
node _T_707 = or(_T_706, _T_687)
node _T_708 = or(_T_707, _T_688)
node _T_709 = or(_T_708, _T_689)
node _T_710 = or(_T_709, _T_690)
node _T_711 = or(_T_710, _T_691)
node _T_712 = or(_T_711, _T_692)
node _T_713 = or(_T_712, _T_693)
node _T_714 = or(_T_713, _T_694)
node _T_715 = or(_T_714, _T_695)
node _T_716 = or(_T_715, _T_696)
node _T_717 = or(_T_716, _T_697)
node _T_718 = or(_T_717, _T_698)
node _T_719 = or(_T_718, _T_699)
node _T_720 = or(_T_719, _T_700)
node _T_721 = or(_T_720, _T_701)
node _T_722 = or(_T_721, _T_702)
node _T_723 = or(_T_722, _T_703)
node _T_724 = and(_T_662, _T_723)
node _T_725 = or(UInt<1>(0h0), _T_724)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_725, UInt<1>(0h1), "") : assert_19
node _T_729 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_730 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_731 = and(_T_729, _T_730)
node _T_732 = or(UInt<1>(0h0), _T_731)
node _T_733 = xor(io.in.a.bits.address, UInt<28>(0h8000080))
node _T_734 = cvt(_T_733)
node _T_735 = and(_T_734, asSInt(UInt<17>(0h100c0)))
node _T_736 = asSInt(_T_735)
node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0)))
node _T_738 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_739 = cvt(_T_738)
node _T_740 = and(_T_739, asSInt(UInt<29>(0h100000c0)))
node _T_741 = asSInt(_T_740)
node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0)))
node _T_743 = or(_T_737, _T_742)
node _T_744 = and(_T_732, _T_743)
node _T_745 = or(UInt<1>(0h0), _T_744)
node _T_746 = asUInt(reset)
node _T_747 = eq(_T_746, UInt<1>(0h0))
when _T_747 :
node _T_748 = eq(_T_745, UInt<1>(0h0))
when _T_748 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_745, UInt<1>(0h1), "") : assert_20
node _T_749 = asUInt(reset)
node _T_750 = eq(_T_749, UInt<1>(0h0))
when _T_750 :
node _T_751 = eq(source_ok, UInt<1>(0h0))
when _T_751 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_752 = asUInt(reset)
node _T_753 = eq(_T_752, UInt<1>(0h0))
when _T_753 :
node _T_754 = eq(is_aligned, UInt<1>(0h0))
when _T_754 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_755 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_756 = asUInt(reset)
node _T_757 = eq(_T_756, UInt<1>(0h0))
when _T_757 :
node _T_758 = eq(_T_755, UInt<1>(0h0))
when _T_758 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_755, UInt<1>(0h1), "") : assert_23
node _T_759 = eq(io.in.a.bits.mask, mask)
node _T_760 = asUInt(reset)
node _T_761 = eq(_T_760, UInt<1>(0h0))
when _T_761 :
node _T_762 = eq(_T_759, UInt<1>(0h0))
when _T_762 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_759, UInt<1>(0h1), "") : assert_24
node _T_763 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_764 = asUInt(reset)
node _T_765 = eq(_T_764, UInt<1>(0h0))
when _T_765 :
node _T_766 = eq(_T_763, UInt<1>(0h0))
when _T_766 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_763, UInt<1>(0h1), "") : assert_25
node _T_767 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_767 :
node _T_768 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_769 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_770 = and(_T_768, _T_769)
node _T_771 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_772 = shr(io.in.a.bits.source, 2)
node _T_773 = eq(_T_772, UInt<1>(0h0))
node _T_774 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_775 = and(_T_773, _T_774)
node _T_776 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_777 = and(_T_775, _T_776)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_778 = shr(io.in.a.bits.source, 2)
node _T_779 = eq(_T_778, UInt<1>(0h1))
node _T_780 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_781 = and(_T_779, _T_780)
node _T_782 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_783 = and(_T_781, _T_782)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_784 = shr(io.in.a.bits.source, 2)
node _T_785 = eq(_T_784, UInt<2>(0h2))
node _T_786 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_787 = and(_T_785, _T_786)
node _T_788 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_789 = and(_T_787, _T_788)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_790 = shr(io.in.a.bits.source, 2)
node _T_791 = eq(_T_790, UInt<2>(0h3))
node _T_792 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_793 = and(_T_791, _T_792)
node _T_794 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_795 = and(_T_793, _T_794)
node _T_796 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_797 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_798 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_799 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_800 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_801 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_802 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_803 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_804 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_805 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_806 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_807 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_808 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_809 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_810 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_811 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_812 = or(_T_771, _T_777)
node _T_813 = or(_T_812, _T_783)
node _T_814 = or(_T_813, _T_789)
node _T_815 = or(_T_814, _T_795)
node _T_816 = or(_T_815, _T_796)
node _T_817 = or(_T_816, _T_797)
node _T_818 = or(_T_817, _T_798)
node _T_819 = or(_T_818, _T_799)
node _T_820 = or(_T_819, _T_800)
node _T_821 = or(_T_820, _T_801)
node _T_822 = or(_T_821, _T_802)
node _T_823 = or(_T_822, _T_803)
node _T_824 = or(_T_823, _T_804)
node _T_825 = or(_T_824, _T_805)
node _T_826 = or(_T_825, _T_806)
node _T_827 = or(_T_826, _T_807)
node _T_828 = or(_T_827, _T_808)
node _T_829 = or(_T_828, _T_809)
node _T_830 = or(_T_829, _T_810)
node _T_831 = or(_T_830, _T_811)
node _T_832 = and(_T_770, _T_831)
node _T_833 = or(UInt<1>(0h0), _T_832)
node _T_834 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_835 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_836 = and(_T_834, _T_835)
node _T_837 = or(UInt<1>(0h0), _T_836)
node _T_838 = xor(io.in.a.bits.address, UInt<28>(0h8000080))
node _T_839 = cvt(_T_838)
node _T_840 = and(_T_839, asSInt(UInt<17>(0h100c0)))
node _T_841 = asSInt(_T_840)
node _T_842 = eq(_T_841, asSInt(UInt<1>(0h0)))
node _T_843 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_844 = cvt(_T_843)
node _T_845 = and(_T_844, asSInt(UInt<29>(0h100000c0)))
node _T_846 = asSInt(_T_845)
node _T_847 = eq(_T_846, asSInt(UInt<1>(0h0)))
node _T_848 = or(_T_842, _T_847)
node _T_849 = and(_T_837, _T_848)
node _T_850 = or(UInt<1>(0h0), _T_849)
node _T_851 = and(_T_833, _T_850)
node _T_852 = asUInt(reset)
node _T_853 = eq(_T_852, UInt<1>(0h0))
when _T_853 :
node _T_854 = eq(_T_851, UInt<1>(0h0))
when _T_854 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_851, UInt<1>(0h1), "") : assert_26
node _T_855 = asUInt(reset)
node _T_856 = eq(_T_855, UInt<1>(0h0))
when _T_856 :
node _T_857 = eq(source_ok, UInt<1>(0h0))
when _T_857 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_858 = asUInt(reset)
node _T_859 = eq(_T_858, UInt<1>(0h0))
when _T_859 :
node _T_860 = eq(is_aligned, UInt<1>(0h0))
when _T_860 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_861 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_862 = asUInt(reset)
node _T_863 = eq(_T_862, UInt<1>(0h0))
when _T_863 :
node _T_864 = eq(_T_861, UInt<1>(0h0))
when _T_864 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_861, UInt<1>(0h1), "") : assert_29
node _T_865 = eq(io.in.a.bits.mask, mask)
node _T_866 = asUInt(reset)
node _T_867 = eq(_T_866, UInt<1>(0h0))
when _T_867 :
node _T_868 = eq(_T_865, UInt<1>(0h0))
when _T_868 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_865, UInt<1>(0h1), "") : assert_30
node _T_869 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_869 :
node _T_870 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_871 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_872 = and(_T_870, _T_871)
node _T_873 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_874 = shr(io.in.a.bits.source, 2)
node _T_875 = eq(_T_874, UInt<1>(0h0))
node _T_876 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_877 = and(_T_875, _T_876)
node _T_878 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_879 = and(_T_877, _T_878)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_880 = shr(io.in.a.bits.source, 2)
node _T_881 = eq(_T_880, UInt<1>(0h1))
node _T_882 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_883 = and(_T_881, _T_882)
node _T_884 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_885 = and(_T_883, _T_884)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_886 = shr(io.in.a.bits.source, 2)
node _T_887 = eq(_T_886, UInt<2>(0h2))
node _T_888 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_889 = and(_T_887, _T_888)
node _T_890 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_891 = and(_T_889, _T_890)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_892 = shr(io.in.a.bits.source, 2)
node _T_893 = eq(_T_892, UInt<2>(0h3))
node _T_894 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_895 = and(_T_893, _T_894)
node _T_896 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_897 = and(_T_895, _T_896)
node _T_898 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_899 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_900 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_901 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_902 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_903 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_904 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_905 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_906 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_907 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_908 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_909 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_910 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_911 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_912 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_913 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_914 = or(_T_873, _T_879)
node _T_915 = or(_T_914, _T_885)
node _T_916 = or(_T_915, _T_891)
node _T_917 = or(_T_916, _T_897)
node _T_918 = or(_T_917, _T_898)
node _T_919 = or(_T_918, _T_899)
node _T_920 = or(_T_919, _T_900)
node _T_921 = or(_T_920, _T_901)
node _T_922 = or(_T_921, _T_902)
node _T_923 = or(_T_922, _T_903)
node _T_924 = or(_T_923, _T_904)
node _T_925 = or(_T_924, _T_905)
node _T_926 = or(_T_925, _T_906)
node _T_927 = or(_T_926, _T_907)
node _T_928 = or(_T_927, _T_908)
node _T_929 = or(_T_928, _T_909)
node _T_930 = or(_T_929, _T_910)
node _T_931 = or(_T_930, _T_911)
node _T_932 = or(_T_931, _T_912)
node _T_933 = or(_T_932, _T_913)
node _T_934 = and(_T_872, _T_933)
node _T_935 = or(UInt<1>(0h0), _T_934)
node _T_936 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_937 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_938 = and(_T_936, _T_937)
node _T_939 = or(UInt<1>(0h0), _T_938)
node _T_940 = xor(io.in.a.bits.address, UInt<28>(0h8000080))
node _T_941 = cvt(_T_940)
node _T_942 = and(_T_941, asSInt(UInt<17>(0h100c0)))
node _T_943 = asSInt(_T_942)
node _T_944 = eq(_T_943, asSInt(UInt<1>(0h0)))
node _T_945 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_946 = cvt(_T_945)
node _T_947 = and(_T_946, asSInt(UInt<29>(0h100000c0)))
node _T_948 = asSInt(_T_947)
node _T_949 = eq(_T_948, asSInt(UInt<1>(0h0)))
node _T_950 = or(_T_944, _T_949)
node _T_951 = and(_T_939, _T_950)
node _T_952 = or(UInt<1>(0h0), _T_951)
node _T_953 = and(_T_935, _T_952)
node _T_954 = asUInt(reset)
node _T_955 = eq(_T_954, UInt<1>(0h0))
when _T_955 :
node _T_956 = eq(_T_953, UInt<1>(0h0))
when _T_956 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_953, UInt<1>(0h1), "") : assert_31
node _T_957 = asUInt(reset)
node _T_958 = eq(_T_957, UInt<1>(0h0))
when _T_958 :
node _T_959 = eq(source_ok, UInt<1>(0h0))
when _T_959 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_960 = asUInt(reset)
node _T_961 = eq(_T_960, UInt<1>(0h0))
when _T_961 :
node _T_962 = eq(is_aligned, UInt<1>(0h0))
when _T_962 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_963 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_964 = asUInt(reset)
node _T_965 = eq(_T_964, UInt<1>(0h0))
when _T_965 :
node _T_966 = eq(_T_963, UInt<1>(0h0))
when _T_966 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_963, UInt<1>(0h1), "") : assert_34
node _T_967 = not(mask)
node _T_968 = and(io.in.a.bits.mask, _T_967)
node _T_969 = eq(_T_968, UInt<1>(0h0))
node _T_970 = asUInt(reset)
node _T_971 = eq(_T_970, UInt<1>(0h0))
when _T_971 :
node _T_972 = eq(_T_969, UInt<1>(0h0))
when _T_972 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_969, UInt<1>(0h1), "") : assert_35
node _T_973 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_973 :
node _T_974 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_975 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_976 = and(_T_974, _T_975)
node _T_977 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_978 = shr(io.in.a.bits.source, 2)
node _T_979 = eq(_T_978, UInt<1>(0h0))
node _T_980 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_981 = and(_T_979, _T_980)
node _T_982 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_983 = and(_T_981, _T_982)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_984 = shr(io.in.a.bits.source, 2)
node _T_985 = eq(_T_984, UInt<1>(0h1))
node _T_986 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_987 = and(_T_985, _T_986)
node _T_988 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_989 = and(_T_987, _T_988)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_990 = shr(io.in.a.bits.source, 2)
node _T_991 = eq(_T_990, UInt<2>(0h2))
node _T_992 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_993 = and(_T_991, _T_992)
node _T_994 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_995 = and(_T_993, _T_994)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_996 = shr(io.in.a.bits.source, 2)
node _T_997 = eq(_T_996, UInt<2>(0h3))
node _T_998 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_999 = and(_T_997, _T_998)
node _T_1000 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_1001 = and(_T_999, _T_1000)
node _T_1002 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_1003 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_1004 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_1005 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_1006 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_1007 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_1008 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_1009 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_1010 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1011 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1012 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1013 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1014 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1015 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1016 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1017 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1018 = or(_T_977, _T_983)
node _T_1019 = or(_T_1018, _T_989)
node _T_1020 = or(_T_1019, _T_995)
node _T_1021 = or(_T_1020, _T_1001)
node _T_1022 = or(_T_1021, _T_1002)
node _T_1023 = or(_T_1022, _T_1003)
node _T_1024 = or(_T_1023, _T_1004)
node _T_1025 = or(_T_1024, _T_1005)
node _T_1026 = or(_T_1025, _T_1006)
node _T_1027 = or(_T_1026, _T_1007)
node _T_1028 = or(_T_1027, _T_1008)
node _T_1029 = or(_T_1028, _T_1009)
node _T_1030 = or(_T_1029, _T_1010)
node _T_1031 = or(_T_1030, _T_1011)
node _T_1032 = or(_T_1031, _T_1012)
node _T_1033 = or(_T_1032, _T_1013)
node _T_1034 = or(_T_1033, _T_1014)
node _T_1035 = or(_T_1034, _T_1015)
node _T_1036 = or(_T_1035, _T_1016)
node _T_1037 = or(_T_1036, _T_1017)
node _T_1038 = and(_T_976, _T_1037)
node _T_1039 = or(UInt<1>(0h0), _T_1038)
node _T_1040 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1041 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1042 = and(_T_1040, _T_1041)
node _T_1043 = or(UInt<1>(0h0), _T_1042)
node _T_1044 = xor(io.in.a.bits.address, UInt<28>(0h8000080))
node _T_1045 = cvt(_T_1044)
node _T_1046 = and(_T_1045, asSInt(UInt<17>(0h100c0)))
node _T_1047 = asSInt(_T_1046)
node _T_1048 = eq(_T_1047, asSInt(UInt<1>(0h0)))
node _T_1049 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_1050 = cvt(_T_1049)
node _T_1051 = and(_T_1050, asSInt(UInt<29>(0h100000c0)))
node _T_1052 = asSInt(_T_1051)
node _T_1053 = eq(_T_1052, asSInt(UInt<1>(0h0)))
node _T_1054 = or(_T_1048, _T_1053)
node _T_1055 = and(_T_1043, _T_1054)
node _T_1056 = or(UInt<1>(0h0), _T_1055)
node _T_1057 = and(_T_1039, _T_1056)
node _T_1058 = asUInt(reset)
node _T_1059 = eq(_T_1058, UInt<1>(0h0))
when _T_1059 :
node _T_1060 = eq(_T_1057, UInt<1>(0h0))
when _T_1060 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_1057, UInt<1>(0h1), "") : assert_36
node _T_1061 = asUInt(reset)
node _T_1062 = eq(_T_1061, UInt<1>(0h0))
when _T_1062 :
node _T_1063 = eq(source_ok, UInt<1>(0h0))
when _T_1063 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_1064 = asUInt(reset)
node _T_1065 = eq(_T_1064, UInt<1>(0h0))
when _T_1065 :
node _T_1066 = eq(is_aligned, UInt<1>(0h0))
when _T_1066 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_1067 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_1068 = asUInt(reset)
node _T_1069 = eq(_T_1068, UInt<1>(0h0))
when _T_1069 :
node _T_1070 = eq(_T_1067, UInt<1>(0h0))
when _T_1070 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_1067, UInt<1>(0h1), "") : assert_39
node _T_1071 = eq(io.in.a.bits.mask, mask)
node _T_1072 = asUInt(reset)
node _T_1073 = eq(_T_1072, UInt<1>(0h0))
when _T_1073 :
node _T_1074 = eq(_T_1071, UInt<1>(0h0))
when _T_1074 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_1071, UInt<1>(0h1), "") : assert_40
node _T_1075 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_1075 :
node _T_1076 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1077 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1078 = and(_T_1076, _T_1077)
node _T_1079 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_1080 = shr(io.in.a.bits.source, 2)
node _T_1081 = eq(_T_1080, UInt<1>(0h0))
node _T_1082 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_1083 = and(_T_1081, _T_1082)
node _T_1084 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_1085 = and(_T_1083, _T_1084)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_1086 = shr(io.in.a.bits.source, 2)
node _T_1087 = eq(_T_1086, UInt<1>(0h1))
node _T_1088 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_1089 = and(_T_1087, _T_1088)
node _T_1090 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_1091 = and(_T_1089, _T_1090)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_1092 = shr(io.in.a.bits.source, 2)
node _T_1093 = eq(_T_1092, UInt<2>(0h2))
node _T_1094 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_1095 = and(_T_1093, _T_1094)
node _T_1096 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_1097 = and(_T_1095, _T_1096)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_1098 = shr(io.in.a.bits.source, 2)
node _T_1099 = eq(_T_1098, UInt<2>(0h3))
node _T_1100 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_1101 = and(_T_1099, _T_1100)
node _T_1102 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_1103 = and(_T_1101, _T_1102)
node _T_1104 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_1105 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_1106 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_1107 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_1108 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_1109 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_1110 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_1111 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_1112 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1113 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1114 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1115 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1116 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1117 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1118 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1119 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1120 = or(_T_1079, _T_1085)
node _T_1121 = or(_T_1120, _T_1091)
node _T_1122 = or(_T_1121, _T_1097)
node _T_1123 = or(_T_1122, _T_1103)
node _T_1124 = or(_T_1123, _T_1104)
node _T_1125 = or(_T_1124, _T_1105)
node _T_1126 = or(_T_1125, _T_1106)
node _T_1127 = or(_T_1126, _T_1107)
node _T_1128 = or(_T_1127, _T_1108)
node _T_1129 = or(_T_1128, _T_1109)
node _T_1130 = or(_T_1129, _T_1110)
node _T_1131 = or(_T_1130, _T_1111)
node _T_1132 = or(_T_1131, _T_1112)
node _T_1133 = or(_T_1132, _T_1113)
node _T_1134 = or(_T_1133, _T_1114)
node _T_1135 = or(_T_1134, _T_1115)
node _T_1136 = or(_T_1135, _T_1116)
node _T_1137 = or(_T_1136, _T_1117)
node _T_1138 = or(_T_1137, _T_1118)
node _T_1139 = or(_T_1138, _T_1119)
node _T_1140 = and(_T_1078, _T_1139)
node _T_1141 = or(UInt<1>(0h0), _T_1140)
node _T_1142 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1143 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1144 = and(_T_1142, _T_1143)
node _T_1145 = or(UInt<1>(0h0), _T_1144)
node _T_1146 = xor(io.in.a.bits.address, UInt<28>(0h8000080))
node _T_1147 = cvt(_T_1146)
node _T_1148 = and(_T_1147, asSInt(UInt<17>(0h100c0)))
node _T_1149 = asSInt(_T_1148)
node _T_1150 = eq(_T_1149, asSInt(UInt<1>(0h0)))
node _T_1151 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_1152 = cvt(_T_1151)
node _T_1153 = and(_T_1152, asSInt(UInt<29>(0h100000c0)))
node _T_1154 = asSInt(_T_1153)
node _T_1155 = eq(_T_1154, asSInt(UInt<1>(0h0)))
node _T_1156 = or(_T_1150, _T_1155)
node _T_1157 = and(_T_1145, _T_1156)
node _T_1158 = or(UInt<1>(0h0), _T_1157)
node _T_1159 = and(_T_1141, _T_1158)
node _T_1160 = asUInt(reset)
node _T_1161 = eq(_T_1160, UInt<1>(0h0))
when _T_1161 :
node _T_1162 = eq(_T_1159, UInt<1>(0h0))
when _T_1162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1159, UInt<1>(0h1), "") : assert_41
node _T_1163 = asUInt(reset)
node _T_1164 = eq(_T_1163, UInt<1>(0h0))
when _T_1164 :
node _T_1165 = eq(source_ok, UInt<1>(0h0))
when _T_1165 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1166 = asUInt(reset)
node _T_1167 = eq(_T_1166, UInt<1>(0h0))
when _T_1167 :
node _T_1168 = eq(is_aligned, UInt<1>(0h0))
when _T_1168 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1169 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1170 = asUInt(reset)
node _T_1171 = eq(_T_1170, UInt<1>(0h0))
when _T_1171 :
node _T_1172 = eq(_T_1169, UInt<1>(0h0))
when _T_1172 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1169, UInt<1>(0h1), "") : assert_44
node _T_1173 = eq(io.in.a.bits.mask, mask)
node _T_1174 = asUInt(reset)
node _T_1175 = eq(_T_1174, UInt<1>(0h0))
when _T_1175 :
node _T_1176 = eq(_T_1173, UInt<1>(0h0))
when _T_1176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1173, UInt<1>(0h1), "") : assert_45
node _T_1177 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1177 :
node _T_1178 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1179 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1180 = and(_T_1178, _T_1179)
node _T_1181 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_1182 = shr(io.in.a.bits.source, 2)
node _T_1183 = eq(_T_1182, UInt<1>(0h0))
node _T_1184 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_1185 = and(_T_1183, _T_1184)
node _T_1186 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_1187 = and(_T_1185, _T_1186)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_1188 = shr(io.in.a.bits.source, 2)
node _T_1189 = eq(_T_1188, UInt<1>(0h1))
node _T_1190 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_1191 = and(_T_1189, _T_1190)
node _T_1192 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_1193 = and(_T_1191, _T_1192)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_1194 = shr(io.in.a.bits.source, 2)
node _T_1195 = eq(_T_1194, UInt<2>(0h2))
node _T_1196 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_1197 = and(_T_1195, _T_1196)
node _T_1198 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_1199 = and(_T_1197, _T_1198)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_1200 = shr(io.in.a.bits.source, 2)
node _T_1201 = eq(_T_1200, UInt<2>(0h3))
node _T_1202 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_1203 = and(_T_1201, _T_1202)
node _T_1204 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_1205 = and(_T_1203, _T_1204)
node _T_1206 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_1207 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_1208 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_1209 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_1210 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_1211 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_1212 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_1213 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_1214 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1215 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1216 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1217 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1218 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1219 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1220 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1221 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1222 = or(_T_1181, _T_1187)
node _T_1223 = or(_T_1222, _T_1193)
node _T_1224 = or(_T_1223, _T_1199)
node _T_1225 = or(_T_1224, _T_1205)
node _T_1226 = or(_T_1225, _T_1206)
node _T_1227 = or(_T_1226, _T_1207)
node _T_1228 = or(_T_1227, _T_1208)
node _T_1229 = or(_T_1228, _T_1209)
node _T_1230 = or(_T_1229, _T_1210)
node _T_1231 = or(_T_1230, _T_1211)
node _T_1232 = or(_T_1231, _T_1212)
node _T_1233 = or(_T_1232, _T_1213)
node _T_1234 = or(_T_1233, _T_1214)
node _T_1235 = or(_T_1234, _T_1215)
node _T_1236 = or(_T_1235, _T_1216)
node _T_1237 = or(_T_1236, _T_1217)
node _T_1238 = or(_T_1237, _T_1218)
node _T_1239 = or(_T_1238, _T_1219)
node _T_1240 = or(_T_1239, _T_1220)
node _T_1241 = or(_T_1240, _T_1221)
node _T_1242 = and(_T_1180, _T_1241)
node _T_1243 = or(UInt<1>(0h0), _T_1242)
node _T_1244 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1245 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1246 = and(_T_1244, _T_1245)
node _T_1247 = or(UInt<1>(0h0), _T_1246)
node _T_1248 = xor(io.in.a.bits.address, UInt<28>(0h8000080))
node _T_1249 = cvt(_T_1248)
node _T_1250 = and(_T_1249, asSInt(UInt<17>(0h100c0)))
node _T_1251 = asSInt(_T_1250)
node _T_1252 = eq(_T_1251, asSInt(UInt<1>(0h0)))
node _T_1253 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_1254 = cvt(_T_1253)
node _T_1255 = and(_T_1254, asSInt(UInt<29>(0h100000c0)))
node _T_1256 = asSInt(_T_1255)
node _T_1257 = eq(_T_1256, asSInt(UInt<1>(0h0)))
node _T_1258 = or(_T_1252, _T_1257)
node _T_1259 = and(_T_1247, _T_1258)
node _T_1260 = or(UInt<1>(0h0), _T_1259)
node _T_1261 = and(_T_1243, _T_1260)
node _T_1262 = asUInt(reset)
node _T_1263 = eq(_T_1262, UInt<1>(0h0))
when _T_1263 :
node _T_1264 = eq(_T_1261, UInt<1>(0h0))
when _T_1264 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1261, UInt<1>(0h1), "") : assert_46
node _T_1265 = asUInt(reset)
node _T_1266 = eq(_T_1265, UInt<1>(0h0))
when _T_1266 :
node _T_1267 = eq(source_ok, UInt<1>(0h0))
when _T_1267 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1268 = asUInt(reset)
node _T_1269 = eq(_T_1268, UInt<1>(0h0))
when _T_1269 :
node _T_1270 = eq(is_aligned, UInt<1>(0h0))
when _T_1270 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1271 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1272 = asUInt(reset)
node _T_1273 = eq(_T_1272, UInt<1>(0h0))
when _T_1273 :
node _T_1274 = eq(_T_1271, UInt<1>(0h0))
when _T_1274 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1271, UInt<1>(0h1), "") : assert_49
node _T_1275 = eq(io.in.a.bits.mask, mask)
node _T_1276 = asUInt(reset)
node _T_1277 = eq(_T_1276, UInt<1>(0h0))
when _T_1277 :
node _T_1278 = eq(_T_1275, UInt<1>(0h0))
when _T_1278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1275, UInt<1>(0h1), "") : assert_50
node _T_1279 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1280 = asUInt(reset)
node _T_1281 = eq(_T_1280, UInt<1>(0h0))
when _T_1281 :
node _T_1282 = eq(_T_1279, UInt<1>(0h0))
when _T_1282 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1279, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1283 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1284 = asUInt(reset)
node _T_1285 = eq(_T_1284, UInt<1>(0h0))
when _T_1285 :
node _T_1286 = eq(_T_1283, UInt<1>(0h0))
when _T_1286 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1283, UInt<1>(0h1), "") : assert_52
node _source_ok_T_60 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_61 = shr(io.in.d.bits.source, 2)
node _source_ok_T_62 = eq(_source_ok_T_61, UInt<1>(0h0))
node _source_ok_T_63 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63)
node _source_ok_T_65 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_67 = shr(io.in.d.bits.source, 2)
node _source_ok_T_68 = eq(_source_ok_T_67, UInt<1>(0h1))
node _source_ok_T_69 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69)
node _source_ok_T_71 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_73 = shr(io.in.d.bits.source, 2)
node _source_ok_T_74 = eq(_source_ok_T_73, UInt<2>(0h2))
node _source_ok_T_75 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75)
node _source_ok_T_77 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_78 = and(_source_ok_T_76, _source_ok_T_77)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_79 = shr(io.in.d.bits.source, 2)
node _source_ok_T_80 = eq(_source_ok_T_79, UInt<2>(0h3))
node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81)
node _source_ok_T_83 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83)
node _source_ok_T_85 = eq(io.in.d.bits.source, UInt<6>(0h3c))
node _source_ok_T_86 = eq(io.in.d.bits.source, UInt<6>(0h3e))
node _source_ok_T_87 = eq(io.in.d.bits.source, UInt<6>(0h38))
node _source_ok_T_88 = eq(io.in.d.bits.source, UInt<6>(0h3a))
node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<6>(0h34))
node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<6>(0h36))
node _source_ok_T_91 = eq(io.in.d.bits.source, UInt<6>(0h30))
node _source_ok_T_92 = eq(io.in.d.bits.source, UInt<6>(0h32))
node _source_ok_T_93 = eq(io.in.d.bits.source, UInt<6>(0h2c))
node _source_ok_T_94 = eq(io.in.d.bits.source, UInt<6>(0h2e))
node _source_ok_T_95 = eq(io.in.d.bits.source, UInt<6>(0h28))
node _source_ok_T_96 = eq(io.in.d.bits.source, UInt<6>(0h2a))
node _source_ok_T_97 = eq(io.in.d.bits.source, UInt<6>(0h24))
node _source_ok_T_98 = eq(io.in.d.bits.source, UInt<6>(0h26))
node _source_ok_T_99 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_T_100 = eq(io.in.d.bits.source, UInt<6>(0h22))
wire _source_ok_WIRE_1 : UInt<1>[21]
connect _source_ok_WIRE_1[0], _source_ok_T_60
connect _source_ok_WIRE_1[1], _source_ok_T_66
connect _source_ok_WIRE_1[2], _source_ok_T_72
connect _source_ok_WIRE_1[3], _source_ok_T_78
connect _source_ok_WIRE_1[4], _source_ok_T_84
connect _source_ok_WIRE_1[5], _source_ok_T_85
connect _source_ok_WIRE_1[6], _source_ok_T_86
connect _source_ok_WIRE_1[7], _source_ok_T_87
connect _source_ok_WIRE_1[8], _source_ok_T_88
connect _source_ok_WIRE_1[9], _source_ok_T_89
connect _source_ok_WIRE_1[10], _source_ok_T_90
connect _source_ok_WIRE_1[11], _source_ok_T_91
connect _source_ok_WIRE_1[12], _source_ok_T_92
connect _source_ok_WIRE_1[13], _source_ok_T_93
connect _source_ok_WIRE_1[14], _source_ok_T_94
connect _source_ok_WIRE_1[15], _source_ok_T_95
connect _source_ok_WIRE_1[16], _source_ok_T_96
connect _source_ok_WIRE_1[17], _source_ok_T_97
connect _source_ok_WIRE_1[18], _source_ok_T_98
connect _source_ok_WIRE_1[19], _source_ok_T_99
connect _source_ok_WIRE_1[20], _source_ok_T_100
node _source_ok_T_101 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_102 = or(_source_ok_T_101, _source_ok_WIRE_1[2])
node _source_ok_T_103 = or(_source_ok_T_102, _source_ok_WIRE_1[3])
node _source_ok_T_104 = or(_source_ok_T_103, _source_ok_WIRE_1[4])
node _source_ok_T_105 = or(_source_ok_T_104, _source_ok_WIRE_1[5])
node _source_ok_T_106 = or(_source_ok_T_105, _source_ok_WIRE_1[6])
node _source_ok_T_107 = or(_source_ok_T_106, _source_ok_WIRE_1[7])
node _source_ok_T_108 = or(_source_ok_T_107, _source_ok_WIRE_1[8])
node _source_ok_T_109 = or(_source_ok_T_108, _source_ok_WIRE_1[9])
node _source_ok_T_110 = or(_source_ok_T_109, _source_ok_WIRE_1[10])
node _source_ok_T_111 = or(_source_ok_T_110, _source_ok_WIRE_1[11])
node _source_ok_T_112 = or(_source_ok_T_111, _source_ok_WIRE_1[12])
node _source_ok_T_113 = or(_source_ok_T_112, _source_ok_WIRE_1[13])
node _source_ok_T_114 = or(_source_ok_T_113, _source_ok_WIRE_1[14])
node _source_ok_T_115 = or(_source_ok_T_114, _source_ok_WIRE_1[15])
node _source_ok_T_116 = or(_source_ok_T_115, _source_ok_WIRE_1[16])
node _source_ok_T_117 = or(_source_ok_T_116, _source_ok_WIRE_1[17])
node _source_ok_T_118 = or(_source_ok_T_117, _source_ok_WIRE_1[18])
node _source_ok_T_119 = or(_source_ok_T_118, _source_ok_WIRE_1[19])
node source_ok_1 = or(_source_ok_T_119, _source_ok_WIRE_1[20])
node sink_ok = lt(io.in.d.bits.sink, UInt<3>(0h7))
node _T_1287 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1287 :
node _T_1288 = asUInt(reset)
node _T_1289 = eq(_T_1288, UInt<1>(0h0))
when _T_1289 :
node _T_1290 = eq(source_ok_1, UInt<1>(0h0))
when _T_1290 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1291 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1292 = asUInt(reset)
node _T_1293 = eq(_T_1292, UInt<1>(0h0))
when _T_1293 :
node _T_1294 = eq(_T_1291, UInt<1>(0h0))
when _T_1294 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1291, UInt<1>(0h1), "") : assert_54
node _T_1295 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1296 = asUInt(reset)
node _T_1297 = eq(_T_1296, UInt<1>(0h0))
when _T_1297 :
node _T_1298 = eq(_T_1295, UInt<1>(0h0))
when _T_1298 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1295, UInt<1>(0h1), "") : assert_55
node _T_1299 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1300 = asUInt(reset)
node _T_1301 = eq(_T_1300, UInt<1>(0h0))
when _T_1301 :
node _T_1302 = eq(_T_1299, UInt<1>(0h0))
when _T_1302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1299, UInt<1>(0h1), "") : assert_56
node _T_1303 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1304 = asUInt(reset)
node _T_1305 = eq(_T_1304, UInt<1>(0h0))
when _T_1305 :
node _T_1306 = eq(_T_1303, UInt<1>(0h0))
when _T_1306 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1303, UInt<1>(0h1), "") : assert_57
node _T_1307 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1307 :
node _T_1308 = asUInt(reset)
node _T_1309 = eq(_T_1308, UInt<1>(0h0))
when _T_1309 :
node _T_1310 = eq(source_ok_1, UInt<1>(0h0))
when _T_1310 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1311 = asUInt(reset)
node _T_1312 = eq(_T_1311, UInt<1>(0h0))
when _T_1312 :
node _T_1313 = eq(sink_ok, UInt<1>(0h0))
when _T_1313 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1314 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1315 = asUInt(reset)
node _T_1316 = eq(_T_1315, UInt<1>(0h0))
when _T_1316 :
node _T_1317 = eq(_T_1314, UInt<1>(0h0))
when _T_1317 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1314, UInt<1>(0h1), "") : assert_60
node _T_1318 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1319 = asUInt(reset)
node _T_1320 = eq(_T_1319, UInt<1>(0h0))
when _T_1320 :
node _T_1321 = eq(_T_1318, UInt<1>(0h0))
when _T_1321 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1318, UInt<1>(0h1), "") : assert_61
node _T_1322 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1323 = asUInt(reset)
node _T_1324 = eq(_T_1323, UInt<1>(0h0))
when _T_1324 :
node _T_1325 = eq(_T_1322, UInt<1>(0h0))
when _T_1325 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1322, UInt<1>(0h1), "") : assert_62
node _T_1326 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1327 = asUInt(reset)
node _T_1328 = eq(_T_1327, UInt<1>(0h0))
when _T_1328 :
node _T_1329 = eq(_T_1326, UInt<1>(0h0))
when _T_1329 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1326, UInt<1>(0h1), "") : assert_63
node _T_1330 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1331 = or(UInt<1>(0h1), _T_1330)
node _T_1332 = asUInt(reset)
node _T_1333 = eq(_T_1332, UInt<1>(0h0))
when _T_1333 :
node _T_1334 = eq(_T_1331, UInt<1>(0h0))
when _T_1334 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1331, UInt<1>(0h1), "") : assert_64
node _T_1335 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1335 :
node _T_1336 = asUInt(reset)
node _T_1337 = eq(_T_1336, UInt<1>(0h0))
when _T_1337 :
node _T_1338 = eq(source_ok_1, UInt<1>(0h0))
when _T_1338 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1339 = asUInt(reset)
node _T_1340 = eq(_T_1339, UInt<1>(0h0))
when _T_1340 :
node _T_1341 = eq(sink_ok, UInt<1>(0h0))
when _T_1341 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1342 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1343 = asUInt(reset)
node _T_1344 = eq(_T_1343, UInt<1>(0h0))
when _T_1344 :
node _T_1345 = eq(_T_1342, UInt<1>(0h0))
when _T_1345 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1342, UInt<1>(0h1), "") : assert_67
node _T_1346 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1347 = asUInt(reset)
node _T_1348 = eq(_T_1347, UInt<1>(0h0))
when _T_1348 :
node _T_1349 = eq(_T_1346, UInt<1>(0h0))
when _T_1349 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1346, UInt<1>(0h1), "") : assert_68
node _T_1350 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1351 = asUInt(reset)
node _T_1352 = eq(_T_1351, UInt<1>(0h0))
when _T_1352 :
node _T_1353 = eq(_T_1350, UInt<1>(0h0))
when _T_1353 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1350, UInt<1>(0h1), "") : assert_69
node _T_1354 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1355 = or(_T_1354, io.in.d.bits.corrupt)
node _T_1356 = asUInt(reset)
node _T_1357 = eq(_T_1356, UInt<1>(0h0))
when _T_1357 :
node _T_1358 = eq(_T_1355, UInt<1>(0h0))
when _T_1358 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1355, UInt<1>(0h1), "") : assert_70
node _T_1359 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1360 = or(UInt<1>(0h1), _T_1359)
node _T_1361 = asUInt(reset)
node _T_1362 = eq(_T_1361, UInt<1>(0h0))
when _T_1362 :
node _T_1363 = eq(_T_1360, UInt<1>(0h0))
when _T_1363 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1360, UInt<1>(0h1), "") : assert_71
node _T_1364 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1364 :
node _T_1365 = asUInt(reset)
node _T_1366 = eq(_T_1365, UInt<1>(0h0))
when _T_1366 :
node _T_1367 = eq(source_ok_1, UInt<1>(0h0))
when _T_1367 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1368 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1369 = asUInt(reset)
node _T_1370 = eq(_T_1369, UInt<1>(0h0))
when _T_1370 :
node _T_1371 = eq(_T_1368, UInt<1>(0h0))
when _T_1371 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1368, UInt<1>(0h1), "") : assert_73
node _T_1372 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1373 = asUInt(reset)
node _T_1374 = eq(_T_1373, UInt<1>(0h0))
when _T_1374 :
node _T_1375 = eq(_T_1372, UInt<1>(0h0))
when _T_1375 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1372, UInt<1>(0h1), "") : assert_74
node _T_1376 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1377 = or(UInt<1>(0h1), _T_1376)
node _T_1378 = asUInt(reset)
node _T_1379 = eq(_T_1378, UInt<1>(0h0))
when _T_1379 :
node _T_1380 = eq(_T_1377, UInt<1>(0h0))
when _T_1380 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1377, UInt<1>(0h1), "") : assert_75
node _T_1381 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1381 :
node _T_1382 = asUInt(reset)
node _T_1383 = eq(_T_1382, UInt<1>(0h0))
when _T_1383 :
node _T_1384 = eq(source_ok_1, UInt<1>(0h0))
when _T_1384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1385 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1386 = asUInt(reset)
node _T_1387 = eq(_T_1386, UInt<1>(0h0))
when _T_1387 :
node _T_1388 = eq(_T_1385, UInt<1>(0h0))
when _T_1388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1385, UInt<1>(0h1), "") : assert_77
node _T_1389 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1390 = or(_T_1389, io.in.d.bits.corrupt)
node _T_1391 = asUInt(reset)
node _T_1392 = eq(_T_1391, UInt<1>(0h0))
when _T_1392 :
node _T_1393 = eq(_T_1390, UInt<1>(0h0))
when _T_1393 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1390, UInt<1>(0h1), "") : assert_78
node _T_1394 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1395 = or(UInt<1>(0h1), _T_1394)
node _T_1396 = asUInt(reset)
node _T_1397 = eq(_T_1396, UInt<1>(0h0))
when _T_1397 :
node _T_1398 = eq(_T_1395, UInt<1>(0h0))
when _T_1398 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1395, UInt<1>(0h1), "") : assert_79
node _T_1399 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1399 :
node _T_1400 = asUInt(reset)
node _T_1401 = eq(_T_1400, UInt<1>(0h0))
when _T_1401 :
node _T_1402 = eq(source_ok_1, UInt<1>(0h0))
when _T_1402 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1403 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1404 = asUInt(reset)
node _T_1405 = eq(_T_1404, UInt<1>(0h0))
when _T_1405 :
node _T_1406 = eq(_T_1403, UInt<1>(0h0))
when _T_1406 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1403, UInt<1>(0h1), "") : assert_81
node _T_1407 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1408 = asUInt(reset)
node _T_1409 = eq(_T_1408, UInt<1>(0h0))
when _T_1409 :
node _T_1410 = eq(_T_1407, UInt<1>(0h0))
when _T_1410 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1407, UInt<1>(0h1), "") : assert_82
node _T_1411 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1412 = or(UInt<1>(0h1), _T_1411)
node _T_1413 = asUInt(reset)
node _T_1414 = eq(_T_1413, UInt<1>(0h0))
when _T_1414 :
node _T_1415 = eq(_T_1412, UInt<1>(0h0))
when _T_1415 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1412, UInt<1>(0h1), "") : assert_83
when io.in.b.valid :
node _T_1416 = leq(io.in.b.bits.opcode, UInt<3>(0h6))
node _T_1417 = asUInt(reset)
node _T_1418 = eq(_T_1417, UInt<1>(0h0))
when _T_1418 :
node _T_1419 = eq(_T_1416, UInt<1>(0h0))
when _T_1419 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1416, UInt<1>(0h1), "") : assert_84
node _T_1420 = eq(io.in.b.bits.source, UInt<5>(0h10))
node _T_1421 = eq(_T_1420, UInt<1>(0h0))
node _T_1422 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1423 = cvt(_T_1422)
node _T_1424 = and(_T_1423, asSInt(UInt<1>(0h0)))
node _T_1425 = asSInt(_T_1424)
node _T_1426 = eq(_T_1425, asSInt(UInt<1>(0h0)))
node _T_1427 = or(_T_1421, _T_1426)
node _uncommonBits_T_44 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_1428 = shr(io.in.b.bits.source, 2)
node _T_1429 = eq(_T_1428, UInt<1>(0h0))
node _T_1430 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_1431 = and(_T_1429, _T_1430)
node _T_1432 = leq(uncommonBits_44, UInt<2>(0h3))
node _T_1433 = and(_T_1431, _T_1432)
node _T_1434 = eq(_T_1433, UInt<1>(0h0))
node _T_1435 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1436 = cvt(_T_1435)
node _T_1437 = and(_T_1436, asSInt(UInt<1>(0h0)))
node _T_1438 = asSInt(_T_1437)
node _T_1439 = eq(_T_1438, asSInt(UInt<1>(0h0)))
node _T_1440 = or(_T_1434, _T_1439)
node _uncommonBits_T_45 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_1441 = shr(io.in.b.bits.source, 2)
node _T_1442 = eq(_T_1441, UInt<1>(0h1))
node _T_1443 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_1444 = and(_T_1442, _T_1443)
node _T_1445 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_1446 = and(_T_1444, _T_1445)
node _T_1447 = eq(_T_1446, UInt<1>(0h0))
node _T_1448 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1449 = cvt(_T_1448)
node _T_1450 = and(_T_1449, asSInt(UInt<1>(0h0)))
node _T_1451 = asSInt(_T_1450)
node _T_1452 = eq(_T_1451, asSInt(UInt<1>(0h0)))
node _T_1453 = or(_T_1447, _T_1452)
node _uncommonBits_T_46 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0)
node _T_1454 = shr(io.in.b.bits.source, 2)
node _T_1455 = eq(_T_1454, UInt<2>(0h2))
node _T_1456 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_1457 = and(_T_1455, _T_1456)
node _T_1458 = leq(uncommonBits_46, UInt<2>(0h3))
node _T_1459 = and(_T_1457, _T_1458)
node _T_1460 = eq(_T_1459, UInt<1>(0h0))
node _T_1461 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1462 = cvt(_T_1461)
node _T_1463 = and(_T_1462, asSInt(UInt<1>(0h0)))
node _T_1464 = asSInt(_T_1463)
node _T_1465 = eq(_T_1464, asSInt(UInt<1>(0h0)))
node _T_1466 = or(_T_1460, _T_1465)
node _uncommonBits_T_47 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0)
node _T_1467 = shr(io.in.b.bits.source, 2)
node _T_1468 = eq(_T_1467, UInt<2>(0h3))
node _T_1469 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_1470 = and(_T_1468, _T_1469)
node _T_1471 = leq(uncommonBits_47, UInt<2>(0h3))
node _T_1472 = and(_T_1470, _T_1471)
node _T_1473 = eq(_T_1472, UInt<1>(0h0))
node _T_1474 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1475 = cvt(_T_1474)
node _T_1476 = and(_T_1475, asSInt(UInt<1>(0h0)))
node _T_1477 = asSInt(_T_1476)
node _T_1478 = eq(_T_1477, asSInt(UInt<1>(0h0)))
node _T_1479 = or(_T_1473, _T_1478)
node _T_1480 = eq(io.in.b.bits.source, UInt<6>(0h3c))
node _T_1481 = eq(_T_1480, UInt<1>(0h0))
node _T_1482 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1483 = cvt(_T_1482)
node _T_1484 = and(_T_1483, asSInt(UInt<1>(0h0)))
node _T_1485 = asSInt(_T_1484)
node _T_1486 = eq(_T_1485, asSInt(UInt<1>(0h0)))
node _T_1487 = or(_T_1481, _T_1486)
node _T_1488 = eq(io.in.b.bits.source, UInt<6>(0h3e))
node _T_1489 = eq(_T_1488, UInt<1>(0h0))
node _T_1490 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1491 = cvt(_T_1490)
node _T_1492 = and(_T_1491, asSInt(UInt<1>(0h0)))
node _T_1493 = asSInt(_T_1492)
node _T_1494 = eq(_T_1493, asSInt(UInt<1>(0h0)))
node _T_1495 = or(_T_1489, _T_1494)
node _T_1496 = eq(io.in.b.bits.source, UInt<6>(0h38))
node _T_1497 = eq(_T_1496, UInt<1>(0h0))
node _T_1498 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1499 = cvt(_T_1498)
node _T_1500 = and(_T_1499, asSInt(UInt<1>(0h0)))
node _T_1501 = asSInt(_T_1500)
node _T_1502 = eq(_T_1501, asSInt(UInt<1>(0h0)))
node _T_1503 = or(_T_1497, _T_1502)
node _T_1504 = eq(io.in.b.bits.source, UInt<6>(0h3a))
node _T_1505 = eq(_T_1504, UInt<1>(0h0))
node _T_1506 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1507 = cvt(_T_1506)
node _T_1508 = and(_T_1507, asSInt(UInt<1>(0h0)))
node _T_1509 = asSInt(_T_1508)
node _T_1510 = eq(_T_1509, asSInt(UInt<1>(0h0)))
node _T_1511 = or(_T_1505, _T_1510)
node _T_1512 = eq(io.in.b.bits.source, UInt<6>(0h34))
node _T_1513 = eq(_T_1512, UInt<1>(0h0))
node _T_1514 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1515 = cvt(_T_1514)
node _T_1516 = and(_T_1515, asSInt(UInt<1>(0h0)))
node _T_1517 = asSInt(_T_1516)
node _T_1518 = eq(_T_1517, asSInt(UInt<1>(0h0)))
node _T_1519 = or(_T_1513, _T_1518)
node _T_1520 = eq(io.in.b.bits.source, UInt<6>(0h36))
node _T_1521 = eq(_T_1520, UInt<1>(0h0))
node _T_1522 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1523 = cvt(_T_1522)
node _T_1524 = and(_T_1523, asSInt(UInt<1>(0h0)))
node _T_1525 = asSInt(_T_1524)
node _T_1526 = eq(_T_1525, asSInt(UInt<1>(0h0)))
node _T_1527 = or(_T_1521, _T_1526)
node _T_1528 = eq(io.in.b.bits.source, UInt<6>(0h30))
node _T_1529 = eq(_T_1528, UInt<1>(0h0))
node _T_1530 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1531 = cvt(_T_1530)
node _T_1532 = and(_T_1531, asSInt(UInt<1>(0h0)))
node _T_1533 = asSInt(_T_1532)
node _T_1534 = eq(_T_1533, asSInt(UInt<1>(0h0)))
node _T_1535 = or(_T_1529, _T_1534)
node _T_1536 = eq(io.in.b.bits.source, UInt<6>(0h32))
node _T_1537 = eq(_T_1536, UInt<1>(0h0))
node _T_1538 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1539 = cvt(_T_1538)
node _T_1540 = and(_T_1539, asSInt(UInt<1>(0h0)))
node _T_1541 = asSInt(_T_1540)
node _T_1542 = eq(_T_1541, asSInt(UInt<1>(0h0)))
node _T_1543 = or(_T_1537, _T_1542)
node _T_1544 = eq(io.in.b.bits.source, UInt<6>(0h2c))
node _T_1545 = eq(_T_1544, UInt<1>(0h0))
node _T_1546 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1547 = cvt(_T_1546)
node _T_1548 = and(_T_1547, asSInt(UInt<1>(0h0)))
node _T_1549 = asSInt(_T_1548)
node _T_1550 = eq(_T_1549, asSInt(UInt<1>(0h0)))
node _T_1551 = or(_T_1545, _T_1550)
node _T_1552 = eq(io.in.b.bits.source, UInt<6>(0h2e))
node _T_1553 = eq(_T_1552, UInt<1>(0h0))
node _T_1554 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1555 = cvt(_T_1554)
node _T_1556 = and(_T_1555, asSInt(UInt<1>(0h0)))
node _T_1557 = asSInt(_T_1556)
node _T_1558 = eq(_T_1557, asSInt(UInt<1>(0h0)))
node _T_1559 = or(_T_1553, _T_1558)
node _T_1560 = eq(io.in.b.bits.source, UInt<6>(0h28))
node _T_1561 = eq(_T_1560, UInt<1>(0h0))
node _T_1562 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1563 = cvt(_T_1562)
node _T_1564 = and(_T_1563, asSInt(UInt<1>(0h0)))
node _T_1565 = asSInt(_T_1564)
node _T_1566 = eq(_T_1565, asSInt(UInt<1>(0h0)))
node _T_1567 = or(_T_1561, _T_1566)
node _T_1568 = eq(io.in.b.bits.source, UInt<6>(0h2a))
node _T_1569 = eq(_T_1568, UInt<1>(0h0))
node _T_1570 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1571 = cvt(_T_1570)
node _T_1572 = and(_T_1571, asSInt(UInt<1>(0h0)))
node _T_1573 = asSInt(_T_1572)
node _T_1574 = eq(_T_1573, asSInt(UInt<1>(0h0)))
node _T_1575 = or(_T_1569, _T_1574)
node _T_1576 = eq(io.in.b.bits.source, UInt<6>(0h24))
node _T_1577 = eq(_T_1576, UInt<1>(0h0))
node _T_1578 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1579 = cvt(_T_1578)
node _T_1580 = and(_T_1579, asSInt(UInt<1>(0h0)))
node _T_1581 = asSInt(_T_1580)
node _T_1582 = eq(_T_1581, asSInt(UInt<1>(0h0)))
node _T_1583 = or(_T_1577, _T_1582)
node _T_1584 = eq(io.in.b.bits.source, UInt<6>(0h26))
node _T_1585 = eq(_T_1584, UInt<1>(0h0))
node _T_1586 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1587 = cvt(_T_1586)
node _T_1588 = and(_T_1587, asSInt(UInt<1>(0h0)))
node _T_1589 = asSInt(_T_1588)
node _T_1590 = eq(_T_1589, asSInt(UInt<1>(0h0)))
node _T_1591 = or(_T_1585, _T_1590)
node _T_1592 = eq(io.in.b.bits.source, UInt<6>(0h20))
node _T_1593 = eq(_T_1592, UInt<1>(0h0))
node _T_1594 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1595 = cvt(_T_1594)
node _T_1596 = and(_T_1595, asSInt(UInt<1>(0h0)))
node _T_1597 = asSInt(_T_1596)
node _T_1598 = eq(_T_1597, asSInt(UInt<1>(0h0)))
node _T_1599 = or(_T_1593, _T_1598)
node _T_1600 = eq(io.in.b.bits.source, UInt<6>(0h22))
node _T_1601 = eq(_T_1600, UInt<1>(0h0))
node _T_1602 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1603 = cvt(_T_1602)
node _T_1604 = and(_T_1603, asSInt(UInt<1>(0h0)))
node _T_1605 = asSInt(_T_1604)
node _T_1606 = eq(_T_1605, asSInt(UInt<1>(0h0)))
node _T_1607 = or(_T_1601, _T_1606)
node _T_1608 = and(_T_1427, _T_1440)
node _T_1609 = and(_T_1608, _T_1453)
node _T_1610 = and(_T_1609, _T_1466)
node _T_1611 = and(_T_1610, _T_1479)
node _T_1612 = and(_T_1611, _T_1487)
node _T_1613 = and(_T_1612, _T_1495)
node _T_1614 = and(_T_1613, _T_1503)
node _T_1615 = and(_T_1614, _T_1511)
node _T_1616 = and(_T_1615, _T_1519)
node _T_1617 = and(_T_1616, _T_1527)
node _T_1618 = and(_T_1617, _T_1535)
node _T_1619 = and(_T_1618, _T_1543)
node _T_1620 = and(_T_1619, _T_1551)
node _T_1621 = and(_T_1620, _T_1559)
node _T_1622 = and(_T_1621, _T_1567)
node _T_1623 = and(_T_1622, _T_1575)
node _T_1624 = and(_T_1623, _T_1583)
node _T_1625 = and(_T_1624, _T_1591)
node _T_1626 = and(_T_1625, _T_1599)
node _T_1627 = and(_T_1626, _T_1607)
node _T_1628 = asUInt(reset)
node _T_1629 = eq(_T_1628, UInt<1>(0h0))
when _T_1629 :
node _T_1630 = eq(_T_1627, UInt<1>(0h0))
when _T_1630 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1627, UInt<1>(0h1), "") : assert_85
node _address_ok_T = xor(io.in.b.bits.address, UInt<28>(0h8000080))
node _address_ok_T_1 = cvt(_address_ok_T)
node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<17>(0h100c0)))
node _address_ok_T_3 = asSInt(_address_ok_T_2)
node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0)))
node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<32>(0h80000080))
node _address_ok_T_6 = cvt(_address_ok_T_5)
node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<29>(0h100000c0)))
node _address_ok_T_8 = asSInt(_address_ok_T_7)
node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE : UInt<1>[2]
connect _address_ok_WIRE[0], _address_ok_T_4
connect _address_ok_WIRE[1], _address_ok_T_9
node address_ok = or(_address_ok_WIRE[0], _address_ok_WIRE[1])
node _is_aligned_mask_T_2 = dshl(UInt<6>(0h3f), io.in.b.bits.size)
node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 5, 0)
node is_aligned_mask_1 = not(_is_aligned_mask_T_3)
node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1)
node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0))
node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0)
node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1)
node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0)
node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1))
node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3))
node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2)
node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2)
node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0))
node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1)
node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1)
node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2)
node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1)
node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1)
node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3)
node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1)
node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1)
node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0))
node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1)
node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4)
node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1)
node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5)
node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1)
node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6)
node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1)
node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7)
node mask_size_1 = bits(mask_sizeOH_1, 0, 0)
node mask_bit_1 = bits(io.in.b.bits.address, 0, 0)
node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0))
node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1)
node _mask_acc_T_8 = and(mask_size_1, mask_eq_8)
node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8)
node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1)
node _mask_acc_T_9 = and(mask_size_1, mask_eq_9)
node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9)
node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1)
node _mask_acc_T_10 = and(mask_size_1, mask_eq_10)
node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10)
node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1)
node _mask_acc_T_11 = and(mask_size_1, mask_eq_11)
node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11)
node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1)
node _mask_acc_T_12 = and(mask_size_1, mask_eq_12)
node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12)
node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1)
node _mask_acc_T_13 = and(mask_size_1, mask_eq_13)
node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13)
node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1)
node _mask_acc_T_14 = and(mask_size_1, mask_eq_14)
node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14)
node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1)
node _mask_acc_T_15 = and(mask_size_1, mask_eq_15)
node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15)
node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8)
node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10)
node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1)
node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12)
node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14)
node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1)
node mask_1 = cat(mask_hi_1, mask_lo_1)
node _legal_source_T = eq(io.in.b.bits.source, UInt<5>(0h10))
node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<2>(0h0))
node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 1, 0)
node _legal_source_T_1 = shr(io.in.b.bits.source, 2)
node _legal_source_T_2 = eq(_legal_source_T_1, UInt<1>(0h0))
node _legal_source_T_3 = leq(UInt<1>(0h0), legal_source_uncommonBits)
node _legal_source_T_4 = and(_legal_source_T_2, _legal_source_T_3)
node _legal_source_T_5 = leq(legal_source_uncommonBits, UInt<2>(0h3))
node _legal_source_T_6 = and(_legal_source_T_4, _legal_source_T_5)
node _legal_source_uncommonBits_T_1 = or(io.in.b.bits.source, UInt<2>(0h0))
node legal_source_uncommonBits_1 = bits(_legal_source_uncommonBits_T_1, 1, 0)
node _legal_source_T_7 = shr(io.in.b.bits.source, 2)
node _legal_source_T_8 = eq(_legal_source_T_7, UInt<1>(0h1))
node _legal_source_T_9 = leq(UInt<1>(0h0), legal_source_uncommonBits_1)
node _legal_source_T_10 = and(_legal_source_T_8, _legal_source_T_9)
node _legal_source_T_11 = leq(legal_source_uncommonBits_1, UInt<2>(0h3))
node _legal_source_T_12 = and(_legal_source_T_10, _legal_source_T_11)
node _legal_source_uncommonBits_T_2 = or(io.in.b.bits.source, UInt<2>(0h0))
node legal_source_uncommonBits_2 = bits(_legal_source_uncommonBits_T_2, 1, 0)
node _legal_source_T_13 = shr(io.in.b.bits.source, 2)
node _legal_source_T_14 = eq(_legal_source_T_13, UInt<2>(0h2))
node _legal_source_T_15 = leq(UInt<1>(0h0), legal_source_uncommonBits_2)
node _legal_source_T_16 = and(_legal_source_T_14, _legal_source_T_15)
node _legal_source_T_17 = leq(legal_source_uncommonBits_2, UInt<2>(0h3))
node _legal_source_T_18 = and(_legal_source_T_16, _legal_source_T_17)
node _legal_source_uncommonBits_T_3 = or(io.in.b.bits.source, UInt<2>(0h0))
node legal_source_uncommonBits_3 = bits(_legal_source_uncommonBits_T_3, 1, 0)
node _legal_source_T_19 = shr(io.in.b.bits.source, 2)
node _legal_source_T_20 = eq(_legal_source_T_19, UInt<2>(0h3))
node _legal_source_T_21 = leq(UInt<1>(0h0), legal_source_uncommonBits_3)
node _legal_source_T_22 = and(_legal_source_T_20, _legal_source_T_21)
node _legal_source_T_23 = leq(legal_source_uncommonBits_3, UInt<2>(0h3))
node _legal_source_T_24 = and(_legal_source_T_22, _legal_source_T_23)
node _legal_source_T_25 = eq(io.in.b.bits.source, UInt<6>(0h3c))
node _legal_source_T_26 = eq(io.in.b.bits.source, UInt<6>(0h3e))
node _legal_source_T_27 = eq(io.in.b.bits.source, UInt<6>(0h38))
node _legal_source_T_28 = eq(io.in.b.bits.source, UInt<6>(0h3a))
node _legal_source_T_29 = eq(io.in.b.bits.source, UInt<6>(0h34))
node _legal_source_T_30 = eq(io.in.b.bits.source, UInt<6>(0h36))
node _legal_source_T_31 = eq(io.in.b.bits.source, UInt<6>(0h30))
node _legal_source_T_32 = eq(io.in.b.bits.source, UInt<6>(0h32))
node _legal_source_T_33 = eq(io.in.b.bits.source, UInt<6>(0h2c))
node _legal_source_T_34 = eq(io.in.b.bits.source, UInt<6>(0h2e))
node _legal_source_T_35 = eq(io.in.b.bits.source, UInt<6>(0h28))
node _legal_source_T_36 = eq(io.in.b.bits.source, UInt<6>(0h2a))
node _legal_source_T_37 = eq(io.in.b.bits.source, UInt<6>(0h24))
node _legal_source_T_38 = eq(io.in.b.bits.source, UInt<6>(0h26))
node _legal_source_T_39 = eq(io.in.b.bits.source, UInt<6>(0h20))
node _legal_source_T_40 = eq(io.in.b.bits.source, UInt<6>(0h22))
wire _legal_source_WIRE : UInt<1>[21]
connect _legal_source_WIRE[0], _legal_source_T
connect _legal_source_WIRE[1], _legal_source_T_6
connect _legal_source_WIRE[2], _legal_source_T_12
connect _legal_source_WIRE[3], _legal_source_T_18
connect _legal_source_WIRE[4], _legal_source_T_24
connect _legal_source_WIRE[5], _legal_source_T_25
connect _legal_source_WIRE[6], _legal_source_T_26
connect _legal_source_WIRE[7], _legal_source_T_27
connect _legal_source_WIRE[8], _legal_source_T_28
connect _legal_source_WIRE[9], _legal_source_T_29
connect _legal_source_WIRE[10], _legal_source_T_30
connect _legal_source_WIRE[11], _legal_source_T_31
connect _legal_source_WIRE[12], _legal_source_T_32
connect _legal_source_WIRE[13], _legal_source_T_33
connect _legal_source_WIRE[14], _legal_source_T_34
connect _legal_source_WIRE[15], _legal_source_T_35
connect _legal_source_WIRE[16], _legal_source_T_36
connect _legal_source_WIRE[17], _legal_source_T_37
connect _legal_source_WIRE[18], _legal_source_T_38
connect _legal_source_WIRE[19], _legal_source_T_39
connect _legal_source_WIRE[20], _legal_source_T_40
node _legal_source_T_41 = mux(_legal_source_WIRE[0], UInt<5>(0h10), UInt<1>(0h0))
node _legal_source_T_42 = mux(_legal_source_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _legal_source_T_43 = mux(_legal_source_WIRE[2], UInt<3>(0h4), UInt<1>(0h0))
node _legal_source_T_44 = mux(_legal_source_WIRE[3], UInt<4>(0h8), UInt<1>(0h0))
node _legal_source_T_45 = mux(_legal_source_WIRE[4], UInt<4>(0hc), UInt<1>(0h0))
node _legal_source_T_46 = mux(_legal_source_WIRE[5], UInt<6>(0h3c), UInt<1>(0h0))
node _legal_source_T_47 = mux(_legal_source_WIRE[6], UInt<6>(0h3e), UInt<1>(0h0))
node _legal_source_T_48 = mux(_legal_source_WIRE[7], UInt<6>(0h38), UInt<1>(0h0))
node _legal_source_T_49 = mux(_legal_source_WIRE[8], UInt<6>(0h3a), UInt<1>(0h0))
node _legal_source_T_50 = mux(_legal_source_WIRE[9], UInt<6>(0h34), UInt<1>(0h0))
node _legal_source_T_51 = mux(_legal_source_WIRE[10], UInt<6>(0h36), UInt<1>(0h0))
node _legal_source_T_52 = mux(_legal_source_WIRE[11], UInt<6>(0h30), UInt<1>(0h0))
node _legal_source_T_53 = mux(_legal_source_WIRE[12], UInt<6>(0h32), UInt<1>(0h0))
node _legal_source_T_54 = mux(_legal_source_WIRE[13], UInt<6>(0h2c), UInt<1>(0h0))
node _legal_source_T_55 = mux(_legal_source_WIRE[14], UInt<6>(0h2e), UInt<1>(0h0))
node _legal_source_T_56 = mux(_legal_source_WIRE[15], UInt<6>(0h28), UInt<1>(0h0))
node _legal_source_T_57 = mux(_legal_source_WIRE[16], UInt<6>(0h2a), UInt<1>(0h0))
node _legal_source_T_58 = mux(_legal_source_WIRE[17], UInt<6>(0h24), UInt<1>(0h0))
node _legal_source_T_59 = mux(_legal_source_WIRE[18], UInt<6>(0h26), UInt<1>(0h0))
node _legal_source_T_60 = mux(_legal_source_WIRE[19], UInt<6>(0h20), UInt<1>(0h0))
node _legal_source_T_61 = mux(_legal_source_WIRE[20], UInt<6>(0h22), UInt<1>(0h0))
node _legal_source_T_62 = or(_legal_source_T_41, _legal_source_T_42)
node _legal_source_T_63 = or(_legal_source_T_62, _legal_source_T_43)
node _legal_source_T_64 = or(_legal_source_T_63, _legal_source_T_44)
node _legal_source_T_65 = or(_legal_source_T_64, _legal_source_T_45)
node _legal_source_T_66 = or(_legal_source_T_65, _legal_source_T_46)
node _legal_source_T_67 = or(_legal_source_T_66, _legal_source_T_47)
node _legal_source_T_68 = or(_legal_source_T_67, _legal_source_T_48)
node _legal_source_T_69 = or(_legal_source_T_68, _legal_source_T_49)
node _legal_source_T_70 = or(_legal_source_T_69, _legal_source_T_50)
node _legal_source_T_71 = or(_legal_source_T_70, _legal_source_T_51)
node _legal_source_T_72 = or(_legal_source_T_71, _legal_source_T_52)
node _legal_source_T_73 = or(_legal_source_T_72, _legal_source_T_53)
node _legal_source_T_74 = or(_legal_source_T_73, _legal_source_T_54)
node _legal_source_T_75 = or(_legal_source_T_74, _legal_source_T_55)
node _legal_source_T_76 = or(_legal_source_T_75, _legal_source_T_56)
node _legal_source_T_77 = or(_legal_source_T_76, _legal_source_T_57)
node _legal_source_T_78 = or(_legal_source_T_77, _legal_source_T_58)
node _legal_source_T_79 = or(_legal_source_T_78, _legal_source_T_59)
node _legal_source_T_80 = or(_legal_source_T_79, _legal_source_T_60)
node _legal_source_T_81 = or(_legal_source_T_80, _legal_source_T_61)
wire _legal_source_WIRE_1 : UInt<6>
connect _legal_source_WIRE_1, _legal_source_T_81
node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source)
node _T_1631 = eq(io.in.b.bits.opcode, UInt<3>(0h6))
when _T_1631 :
node _T_1632 = eq(io.in.b.bits.source, UInt<5>(0h10))
node _uncommonBits_T_48 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0)
node _T_1633 = shr(io.in.b.bits.source, 2)
node _T_1634 = eq(_T_1633, UInt<1>(0h0))
node _T_1635 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_1636 = and(_T_1634, _T_1635)
node _T_1637 = leq(uncommonBits_48, UInt<2>(0h3))
node _T_1638 = and(_T_1636, _T_1637)
node _uncommonBits_T_49 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0)
node _T_1639 = shr(io.in.b.bits.source, 2)
node _T_1640 = eq(_T_1639, UInt<1>(0h1))
node _T_1641 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_1642 = and(_T_1640, _T_1641)
node _T_1643 = leq(uncommonBits_49, UInt<2>(0h3))
node _T_1644 = and(_T_1642, _T_1643)
node _uncommonBits_T_50 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_1645 = shr(io.in.b.bits.source, 2)
node _T_1646 = eq(_T_1645, UInt<2>(0h2))
node _T_1647 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_1648 = and(_T_1646, _T_1647)
node _T_1649 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_1650 = and(_T_1648, _T_1649)
node _uncommonBits_T_51 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_1651 = shr(io.in.b.bits.source, 2)
node _T_1652 = eq(_T_1651, UInt<2>(0h3))
node _T_1653 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_1654 = and(_T_1652, _T_1653)
node _T_1655 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_1656 = and(_T_1654, _T_1655)
node _T_1657 = eq(io.in.b.bits.source, UInt<6>(0h3c))
node _T_1658 = eq(io.in.b.bits.source, UInt<6>(0h3e))
node _T_1659 = eq(io.in.b.bits.source, UInt<6>(0h38))
node _T_1660 = eq(io.in.b.bits.source, UInt<6>(0h3a))
node _T_1661 = eq(io.in.b.bits.source, UInt<6>(0h34))
node _T_1662 = eq(io.in.b.bits.source, UInt<6>(0h36))
node _T_1663 = eq(io.in.b.bits.source, UInt<6>(0h30))
node _T_1664 = eq(io.in.b.bits.source, UInt<6>(0h32))
node _T_1665 = eq(io.in.b.bits.source, UInt<6>(0h2c))
node _T_1666 = eq(io.in.b.bits.source, UInt<6>(0h2e))
node _T_1667 = eq(io.in.b.bits.source, UInt<6>(0h28))
node _T_1668 = eq(io.in.b.bits.source, UInt<6>(0h2a))
node _T_1669 = eq(io.in.b.bits.source, UInt<6>(0h24))
node _T_1670 = eq(io.in.b.bits.source, UInt<6>(0h26))
node _T_1671 = eq(io.in.b.bits.source, UInt<6>(0h20))
node _T_1672 = eq(io.in.b.bits.source, UInt<6>(0h22))
wire _WIRE_4 : UInt<1>[21]
connect _WIRE_4[0], _T_1632
connect _WIRE_4[1], _T_1638
connect _WIRE_4[2], _T_1644
connect _WIRE_4[3], _T_1650
connect _WIRE_4[4], _T_1656
connect _WIRE_4[5], _T_1657
connect _WIRE_4[6], _T_1658
connect _WIRE_4[7], _T_1659
connect _WIRE_4[8], _T_1660
connect _WIRE_4[9], _T_1661
connect _WIRE_4[10], _T_1662
connect _WIRE_4[11], _T_1663
connect _WIRE_4[12], _T_1664
connect _WIRE_4[13], _T_1665
connect _WIRE_4[14], _T_1666
connect _WIRE_4[15], _T_1667
connect _WIRE_4[16], _T_1668
connect _WIRE_4[17], _T_1669
connect _WIRE_4[18], _T_1670
connect _WIRE_4[19], _T_1671
connect _WIRE_4[20], _T_1672
node _T_1673 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_1674 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_1675 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_1676 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_1677 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_1678 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_1679 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_1680 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_1681 = mux(_WIRE_4[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_1682 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_1683 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_1684 = mux(_WIRE_4[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_1685 = mux(_WIRE_4[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_1686 = mux(_WIRE_4[5], _T_1673, UInt<1>(0h0))
node _T_1687 = mux(_WIRE_4[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_1688 = mux(_WIRE_4[7], _T_1674, UInt<1>(0h0))
node _T_1689 = mux(_WIRE_4[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_1690 = mux(_WIRE_4[9], _T_1675, UInt<1>(0h0))
node _T_1691 = mux(_WIRE_4[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_1692 = mux(_WIRE_4[11], _T_1676, UInt<1>(0h0))
node _T_1693 = mux(_WIRE_4[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_1694 = mux(_WIRE_4[13], _T_1677, UInt<1>(0h0))
node _T_1695 = mux(_WIRE_4[14], UInt<1>(0h0), UInt<1>(0h0))
node _T_1696 = mux(_WIRE_4[15], _T_1678, UInt<1>(0h0))
node _T_1697 = mux(_WIRE_4[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_1698 = mux(_WIRE_4[17], _T_1679, UInt<1>(0h0))
node _T_1699 = mux(_WIRE_4[18], UInt<1>(0h0), UInt<1>(0h0))
node _T_1700 = mux(_WIRE_4[19], _T_1680, UInt<1>(0h0))
node _T_1701 = mux(_WIRE_4[20], UInt<1>(0h0), UInt<1>(0h0))
node _T_1702 = or(_T_1681, _T_1682)
node _T_1703 = or(_T_1702, _T_1683)
node _T_1704 = or(_T_1703, _T_1684)
node _T_1705 = or(_T_1704, _T_1685)
node _T_1706 = or(_T_1705, _T_1686)
node _T_1707 = or(_T_1706, _T_1687)
node _T_1708 = or(_T_1707, _T_1688)
node _T_1709 = or(_T_1708, _T_1689)
node _T_1710 = or(_T_1709, _T_1690)
node _T_1711 = or(_T_1710, _T_1691)
node _T_1712 = or(_T_1711, _T_1692)
node _T_1713 = or(_T_1712, _T_1693)
node _T_1714 = or(_T_1713, _T_1694)
node _T_1715 = or(_T_1714, _T_1695)
node _T_1716 = or(_T_1715, _T_1696)
node _T_1717 = or(_T_1716, _T_1697)
node _T_1718 = or(_T_1717, _T_1698)
node _T_1719 = or(_T_1718, _T_1699)
node _T_1720 = or(_T_1719, _T_1700)
node _T_1721 = or(_T_1720, _T_1701)
wire _WIRE_5 : UInt<1>
connect _WIRE_5, _T_1721
node _T_1722 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1723 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1724 = and(_T_1722, _T_1723)
node _T_1725 = or(UInt<1>(0h0), _T_1724)
node _T_1726 = xor(io.in.b.bits.address, UInt<28>(0h8000080))
node _T_1727 = cvt(_T_1726)
node _T_1728 = and(_T_1727, asSInt(UInt<17>(0h100c0)))
node _T_1729 = asSInt(_T_1728)
node _T_1730 = eq(_T_1729, asSInt(UInt<1>(0h0)))
node _T_1731 = xor(io.in.b.bits.address, UInt<32>(0h80000080))
node _T_1732 = cvt(_T_1731)
node _T_1733 = and(_T_1732, asSInt(UInt<29>(0h100000c0)))
node _T_1734 = asSInt(_T_1733)
node _T_1735 = eq(_T_1734, asSInt(UInt<1>(0h0)))
node _T_1736 = or(_T_1730, _T_1735)
node _T_1737 = and(_T_1725, _T_1736)
node _T_1738 = or(UInt<1>(0h0), _T_1737)
node _T_1739 = and(_WIRE_5, _T_1738)
node _T_1740 = asUInt(reset)
node _T_1741 = eq(_T_1740, UInt<1>(0h0))
when _T_1741 :
node _T_1742 = eq(_T_1739, UInt<1>(0h0))
when _T_1742 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86
assert(clock, _T_1739, UInt<1>(0h1), "") : assert_86
node _T_1743 = asUInt(reset)
node _T_1744 = eq(_T_1743, UInt<1>(0h0))
when _T_1744 :
node _T_1745 = eq(address_ok, UInt<1>(0h0))
when _T_1745 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87
assert(clock, address_ok, UInt<1>(0h1), "") : assert_87
node _T_1746 = asUInt(reset)
node _T_1747 = eq(_T_1746, UInt<1>(0h0))
when _T_1747 :
node _T_1748 = eq(legal_source, UInt<1>(0h0))
when _T_1748 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88
assert(clock, legal_source, UInt<1>(0h1), "") : assert_88
node _T_1749 = asUInt(reset)
node _T_1750 = eq(_T_1749, UInt<1>(0h0))
when _T_1750 :
node _T_1751 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1751 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89
node _T_1752 = leq(io.in.b.bits.param, UInt<2>(0h2))
node _T_1753 = asUInt(reset)
node _T_1754 = eq(_T_1753, UInt<1>(0h0))
when _T_1754 :
node _T_1755 = eq(_T_1752, UInt<1>(0h0))
when _T_1755 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90
assert(clock, _T_1752, UInt<1>(0h1), "") : assert_90
node _T_1756 = eq(io.in.b.bits.mask, mask_1)
node _T_1757 = asUInt(reset)
node _T_1758 = eq(_T_1757, UInt<1>(0h0))
when _T_1758 :
node _T_1759 = eq(_T_1756, UInt<1>(0h0))
when _T_1759 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91
assert(clock, _T_1756, UInt<1>(0h1), "") : assert_91
node _T_1760 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1761 = asUInt(reset)
node _T_1762 = eq(_T_1761, UInt<1>(0h0))
when _T_1762 :
node _T_1763 = eq(_T_1760, UInt<1>(0h0))
when _T_1763 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1760, UInt<1>(0h1), "") : assert_92
node _T_1764 = eq(io.in.b.bits.opcode, UInt<3>(0h4))
when _T_1764 :
node _T_1765 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1766 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1767 = and(_T_1765, _T_1766)
node _T_1768 = or(UInt<1>(0h0), _T_1767)
node _T_1769 = xor(io.in.b.bits.address, UInt<28>(0h8000080))
node _T_1770 = cvt(_T_1769)
node _T_1771 = and(_T_1770, asSInt(UInt<17>(0h100c0)))
node _T_1772 = asSInt(_T_1771)
node _T_1773 = eq(_T_1772, asSInt(UInt<1>(0h0)))
node _T_1774 = xor(io.in.b.bits.address, UInt<32>(0h80000080))
node _T_1775 = cvt(_T_1774)
node _T_1776 = and(_T_1775, asSInt(UInt<29>(0h100000c0)))
node _T_1777 = asSInt(_T_1776)
node _T_1778 = eq(_T_1777, asSInt(UInt<1>(0h0)))
node _T_1779 = or(_T_1773, _T_1778)
node _T_1780 = and(_T_1768, _T_1779)
node _T_1781 = or(UInt<1>(0h0), _T_1780)
node _T_1782 = and(UInt<1>(0h0), _T_1781)
node _T_1783 = asUInt(reset)
node _T_1784 = eq(_T_1783, UInt<1>(0h0))
when _T_1784 :
node _T_1785 = eq(_T_1782, UInt<1>(0h0))
when _T_1785 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93
assert(clock, _T_1782, UInt<1>(0h1), "") : assert_93
node _T_1786 = asUInt(reset)
node _T_1787 = eq(_T_1786, UInt<1>(0h0))
when _T_1787 :
node _T_1788 = eq(address_ok, UInt<1>(0h0))
when _T_1788 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94
assert(clock, address_ok, UInt<1>(0h1), "") : assert_94
node _T_1789 = asUInt(reset)
node _T_1790 = eq(_T_1789, UInt<1>(0h0))
when _T_1790 :
node _T_1791 = eq(legal_source, UInt<1>(0h0))
when _T_1791 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95
assert(clock, legal_source, UInt<1>(0h1), "") : assert_95
node _T_1792 = asUInt(reset)
node _T_1793 = eq(_T_1792, UInt<1>(0h0))
when _T_1793 :
node _T_1794 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1794 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96
node _T_1795 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1796 = asUInt(reset)
node _T_1797 = eq(_T_1796, UInt<1>(0h0))
when _T_1797 :
node _T_1798 = eq(_T_1795, UInt<1>(0h0))
when _T_1798 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97
assert(clock, _T_1795, UInt<1>(0h1), "") : assert_97
node _T_1799 = eq(io.in.b.bits.mask, mask_1)
node _T_1800 = asUInt(reset)
node _T_1801 = eq(_T_1800, UInt<1>(0h0))
when _T_1801 :
node _T_1802 = eq(_T_1799, UInt<1>(0h0))
when _T_1802 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1799, UInt<1>(0h1), "") : assert_98
node _T_1803 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1804 = asUInt(reset)
node _T_1805 = eq(_T_1804, UInt<1>(0h0))
when _T_1805 :
node _T_1806 = eq(_T_1803, UInt<1>(0h0))
when _T_1806 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99
assert(clock, _T_1803, UInt<1>(0h1), "") : assert_99
node _T_1807 = eq(io.in.b.bits.opcode, UInt<1>(0h0))
when _T_1807 :
node _T_1808 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1809 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1810 = and(_T_1808, _T_1809)
node _T_1811 = or(UInt<1>(0h0), _T_1810)
node _T_1812 = xor(io.in.b.bits.address, UInt<28>(0h8000080))
node _T_1813 = cvt(_T_1812)
node _T_1814 = and(_T_1813, asSInt(UInt<17>(0h100c0)))
node _T_1815 = asSInt(_T_1814)
node _T_1816 = eq(_T_1815, asSInt(UInt<1>(0h0)))
node _T_1817 = xor(io.in.b.bits.address, UInt<32>(0h80000080))
node _T_1818 = cvt(_T_1817)
node _T_1819 = and(_T_1818, asSInt(UInt<29>(0h100000c0)))
node _T_1820 = asSInt(_T_1819)
node _T_1821 = eq(_T_1820, asSInt(UInt<1>(0h0)))
node _T_1822 = or(_T_1816, _T_1821)
node _T_1823 = and(_T_1811, _T_1822)
node _T_1824 = or(UInt<1>(0h0), _T_1823)
node _T_1825 = and(UInt<1>(0h0), _T_1824)
node _T_1826 = asUInt(reset)
node _T_1827 = eq(_T_1826, UInt<1>(0h0))
when _T_1827 :
node _T_1828 = eq(_T_1825, UInt<1>(0h0))
when _T_1828 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100
assert(clock, _T_1825, UInt<1>(0h1), "") : assert_100
node _T_1829 = asUInt(reset)
node _T_1830 = eq(_T_1829, UInt<1>(0h0))
when _T_1830 :
node _T_1831 = eq(address_ok, UInt<1>(0h0))
when _T_1831 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101
assert(clock, address_ok, UInt<1>(0h1), "") : assert_101
node _T_1832 = asUInt(reset)
node _T_1833 = eq(_T_1832, UInt<1>(0h0))
when _T_1833 :
node _T_1834 = eq(legal_source, UInt<1>(0h0))
when _T_1834 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102
assert(clock, legal_source, UInt<1>(0h1), "") : assert_102
node _T_1835 = asUInt(reset)
node _T_1836 = eq(_T_1835, UInt<1>(0h0))
when _T_1836 :
node _T_1837 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1837 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103
node _T_1838 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1839 = asUInt(reset)
node _T_1840 = eq(_T_1839, UInt<1>(0h0))
when _T_1840 :
node _T_1841 = eq(_T_1838, UInt<1>(0h0))
when _T_1841 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104
assert(clock, _T_1838, UInt<1>(0h1), "") : assert_104
node _T_1842 = eq(io.in.b.bits.mask, mask_1)
node _T_1843 = asUInt(reset)
node _T_1844 = eq(_T_1843, UInt<1>(0h0))
when _T_1844 :
node _T_1845 = eq(_T_1842, UInt<1>(0h0))
when _T_1845 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1842, UInt<1>(0h1), "") : assert_105
node _T_1846 = eq(io.in.b.bits.opcode, UInt<1>(0h1))
when _T_1846 :
node _T_1847 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1848 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1849 = and(_T_1847, _T_1848)
node _T_1850 = or(UInt<1>(0h0), _T_1849)
node _T_1851 = xor(io.in.b.bits.address, UInt<28>(0h8000080))
node _T_1852 = cvt(_T_1851)
node _T_1853 = and(_T_1852, asSInt(UInt<17>(0h100c0)))
node _T_1854 = asSInt(_T_1853)
node _T_1855 = eq(_T_1854, asSInt(UInt<1>(0h0)))
node _T_1856 = xor(io.in.b.bits.address, UInt<32>(0h80000080))
node _T_1857 = cvt(_T_1856)
node _T_1858 = and(_T_1857, asSInt(UInt<29>(0h100000c0)))
node _T_1859 = asSInt(_T_1858)
node _T_1860 = eq(_T_1859, asSInt(UInt<1>(0h0)))
node _T_1861 = or(_T_1855, _T_1860)
node _T_1862 = and(_T_1850, _T_1861)
node _T_1863 = or(UInt<1>(0h0), _T_1862)
node _T_1864 = and(UInt<1>(0h0), _T_1863)
node _T_1865 = asUInt(reset)
node _T_1866 = eq(_T_1865, UInt<1>(0h0))
when _T_1866 :
node _T_1867 = eq(_T_1864, UInt<1>(0h0))
when _T_1867 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1864, UInt<1>(0h1), "") : assert_106
node _T_1868 = asUInt(reset)
node _T_1869 = eq(_T_1868, UInt<1>(0h0))
when _T_1869 :
node _T_1870 = eq(address_ok, UInt<1>(0h0))
when _T_1870 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, address_ok, UInt<1>(0h1), "") : assert_107
node _T_1871 = asUInt(reset)
node _T_1872 = eq(_T_1871, UInt<1>(0h0))
when _T_1872 :
node _T_1873 = eq(legal_source, UInt<1>(0h0))
when _T_1873 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108
assert(clock, legal_source, UInt<1>(0h1), "") : assert_108
node _T_1874 = asUInt(reset)
node _T_1875 = eq(_T_1874, UInt<1>(0h0))
when _T_1875 :
node _T_1876 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1876 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109
node _T_1877 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1878 = asUInt(reset)
node _T_1879 = eq(_T_1878, UInt<1>(0h0))
when _T_1879 :
node _T_1880 = eq(_T_1877, UInt<1>(0h0))
when _T_1880 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110
assert(clock, _T_1877, UInt<1>(0h1), "") : assert_110
node _T_1881 = not(mask_1)
node _T_1882 = and(io.in.b.bits.mask, _T_1881)
node _T_1883 = eq(_T_1882, UInt<1>(0h0))
node _T_1884 = asUInt(reset)
node _T_1885 = eq(_T_1884, UInt<1>(0h0))
when _T_1885 :
node _T_1886 = eq(_T_1883, UInt<1>(0h0))
when _T_1886 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1883, UInt<1>(0h1), "") : assert_111
node _T_1887 = eq(io.in.b.bits.opcode, UInt<2>(0h2))
when _T_1887 :
node _T_1888 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1889 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1890 = and(_T_1888, _T_1889)
node _T_1891 = or(UInt<1>(0h0), _T_1890)
node _T_1892 = xor(io.in.b.bits.address, UInt<28>(0h8000080))
node _T_1893 = cvt(_T_1892)
node _T_1894 = and(_T_1893, asSInt(UInt<17>(0h100c0)))
node _T_1895 = asSInt(_T_1894)
node _T_1896 = eq(_T_1895, asSInt(UInt<1>(0h0)))
node _T_1897 = xor(io.in.b.bits.address, UInt<32>(0h80000080))
node _T_1898 = cvt(_T_1897)
node _T_1899 = and(_T_1898, asSInt(UInt<29>(0h100000c0)))
node _T_1900 = asSInt(_T_1899)
node _T_1901 = eq(_T_1900, asSInt(UInt<1>(0h0)))
node _T_1902 = or(_T_1896, _T_1901)
node _T_1903 = and(_T_1891, _T_1902)
node _T_1904 = or(UInt<1>(0h0), _T_1903)
node _T_1905 = and(UInt<1>(0h0), _T_1904)
node _T_1906 = asUInt(reset)
node _T_1907 = eq(_T_1906, UInt<1>(0h0))
when _T_1907 :
node _T_1908 = eq(_T_1905, UInt<1>(0h0))
when _T_1908 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112
assert(clock, _T_1905, UInt<1>(0h1), "") : assert_112
node _T_1909 = asUInt(reset)
node _T_1910 = eq(_T_1909, UInt<1>(0h0))
when _T_1910 :
node _T_1911 = eq(address_ok, UInt<1>(0h0))
when _T_1911 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, address_ok, UInt<1>(0h1), "") : assert_113
node _T_1912 = asUInt(reset)
node _T_1913 = eq(_T_1912, UInt<1>(0h0))
when _T_1913 :
node _T_1914 = eq(legal_source, UInt<1>(0h0))
when _T_1914 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114
assert(clock, legal_source, UInt<1>(0h1), "") : assert_114
node _T_1915 = asUInt(reset)
node _T_1916 = eq(_T_1915, UInt<1>(0h0))
when _T_1916 :
node _T_1917 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1917 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115
node _T_1918 = leq(io.in.b.bits.param, UInt<3>(0h4))
node _T_1919 = asUInt(reset)
node _T_1920 = eq(_T_1919, UInt<1>(0h0))
when _T_1920 :
node _T_1921 = eq(_T_1918, UInt<1>(0h0))
when _T_1921 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116
assert(clock, _T_1918, UInt<1>(0h1), "") : assert_116
node _T_1922 = eq(io.in.b.bits.mask, mask_1)
node _T_1923 = asUInt(reset)
node _T_1924 = eq(_T_1923, UInt<1>(0h0))
when _T_1924 :
node _T_1925 = eq(_T_1922, UInt<1>(0h0))
when _T_1925 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117
assert(clock, _T_1922, UInt<1>(0h1), "") : assert_117
node _T_1926 = eq(io.in.b.bits.opcode, UInt<2>(0h3))
when _T_1926 :
node _T_1927 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1928 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1929 = and(_T_1927, _T_1928)
node _T_1930 = or(UInt<1>(0h0), _T_1929)
node _T_1931 = xor(io.in.b.bits.address, UInt<28>(0h8000080))
node _T_1932 = cvt(_T_1931)
node _T_1933 = and(_T_1932, asSInt(UInt<17>(0h100c0)))
node _T_1934 = asSInt(_T_1933)
node _T_1935 = eq(_T_1934, asSInt(UInt<1>(0h0)))
node _T_1936 = xor(io.in.b.bits.address, UInt<32>(0h80000080))
node _T_1937 = cvt(_T_1936)
node _T_1938 = and(_T_1937, asSInt(UInt<29>(0h100000c0)))
node _T_1939 = asSInt(_T_1938)
node _T_1940 = eq(_T_1939, asSInt(UInt<1>(0h0)))
node _T_1941 = or(_T_1935, _T_1940)
node _T_1942 = and(_T_1930, _T_1941)
node _T_1943 = or(UInt<1>(0h0), _T_1942)
node _T_1944 = and(UInt<1>(0h0), _T_1943)
node _T_1945 = asUInt(reset)
node _T_1946 = eq(_T_1945, UInt<1>(0h0))
when _T_1946 :
node _T_1947 = eq(_T_1944, UInt<1>(0h0))
when _T_1947 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118
assert(clock, _T_1944, UInt<1>(0h1), "") : assert_118
node _T_1948 = asUInt(reset)
node _T_1949 = eq(_T_1948, UInt<1>(0h0))
when _T_1949 :
node _T_1950 = eq(address_ok, UInt<1>(0h0))
when _T_1950 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119
assert(clock, address_ok, UInt<1>(0h1), "") : assert_119
node _T_1951 = asUInt(reset)
node _T_1952 = eq(_T_1951, UInt<1>(0h0))
when _T_1952 :
node _T_1953 = eq(legal_source, UInt<1>(0h0))
when _T_1953 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120
assert(clock, legal_source, UInt<1>(0h1), "") : assert_120
node _T_1954 = asUInt(reset)
node _T_1955 = eq(_T_1954, UInt<1>(0h0))
when _T_1955 :
node _T_1956 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1956 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121
node _T_1957 = leq(io.in.b.bits.param, UInt<3>(0h3))
node _T_1958 = asUInt(reset)
node _T_1959 = eq(_T_1958, UInt<1>(0h0))
when _T_1959 :
node _T_1960 = eq(_T_1957, UInt<1>(0h0))
when _T_1960 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122
assert(clock, _T_1957, UInt<1>(0h1), "") : assert_122
node _T_1961 = eq(io.in.b.bits.mask, mask_1)
node _T_1962 = asUInt(reset)
node _T_1963 = eq(_T_1962, UInt<1>(0h0))
when _T_1963 :
node _T_1964 = eq(_T_1961, UInt<1>(0h0))
when _T_1964 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123
assert(clock, _T_1961, UInt<1>(0h1), "") : assert_123
node _T_1965 = eq(io.in.b.bits.opcode, UInt<3>(0h5))
when _T_1965 :
node _T_1966 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1967 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1968 = and(_T_1966, _T_1967)
node _T_1969 = or(UInt<1>(0h0), _T_1968)
node _T_1970 = xor(io.in.b.bits.address, UInt<28>(0h8000080))
node _T_1971 = cvt(_T_1970)
node _T_1972 = and(_T_1971, asSInt(UInt<17>(0h100c0)))
node _T_1973 = asSInt(_T_1972)
node _T_1974 = eq(_T_1973, asSInt(UInt<1>(0h0)))
node _T_1975 = xor(io.in.b.bits.address, UInt<32>(0h80000080))
node _T_1976 = cvt(_T_1975)
node _T_1977 = and(_T_1976, asSInt(UInt<29>(0h100000c0)))
node _T_1978 = asSInt(_T_1977)
node _T_1979 = eq(_T_1978, asSInt(UInt<1>(0h0)))
node _T_1980 = or(_T_1974, _T_1979)
node _T_1981 = and(_T_1969, _T_1980)
node _T_1982 = or(UInt<1>(0h0), _T_1981)
node _T_1983 = and(UInt<1>(0h0), _T_1982)
node _T_1984 = asUInt(reset)
node _T_1985 = eq(_T_1984, UInt<1>(0h0))
when _T_1985 :
node _T_1986 = eq(_T_1983, UInt<1>(0h0))
when _T_1986 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124
assert(clock, _T_1983, UInt<1>(0h1), "") : assert_124
node _T_1987 = asUInt(reset)
node _T_1988 = eq(_T_1987, UInt<1>(0h0))
when _T_1988 :
node _T_1989 = eq(address_ok, UInt<1>(0h0))
when _T_1989 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125
assert(clock, address_ok, UInt<1>(0h1), "") : assert_125
node _T_1990 = asUInt(reset)
node _T_1991 = eq(_T_1990, UInt<1>(0h0))
when _T_1991 :
node _T_1992 = eq(legal_source, UInt<1>(0h0))
when _T_1992 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126
assert(clock, legal_source, UInt<1>(0h1), "") : assert_126
node _T_1993 = asUInt(reset)
node _T_1994 = eq(_T_1993, UInt<1>(0h0))
when _T_1994 :
node _T_1995 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1995 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127
node _T_1996 = eq(io.in.b.bits.mask, mask_1)
node _T_1997 = asUInt(reset)
node _T_1998 = eq(_T_1997, UInt<1>(0h0))
when _T_1998 :
node _T_1999 = eq(_T_1996, UInt<1>(0h0))
when _T_1999 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128
assert(clock, _T_1996, UInt<1>(0h1), "") : assert_128
node _T_2000 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_2001 = asUInt(reset)
node _T_2002 = eq(_T_2001, UInt<1>(0h0))
when _T_2002 :
node _T_2003 = eq(_T_2000, UInt<1>(0h0))
when _T_2003 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129
assert(clock, _T_2000, UInt<1>(0h1), "") : assert_129
when io.in.c.valid :
node _T_2004 = leq(io.in.c.bits.opcode, UInt<3>(0h7))
node _T_2005 = asUInt(reset)
node _T_2006 = eq(_T_2005, UInt<1>(0h0))
when _T_2006 :
node _T_2007 = eq(_T_2004, UInt<1>(0h0))
when _T_2007 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130
assert(clock, _T_2004, UInt<1>(0h1), "") : assert_130
node _source_ok_T_120 = eq(io.in.c.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_8 = or(io.in.c.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_121 = shr(io.in.c.bits.source, 2)
node _source_ok_T_122 = eq(_source_ok_T_121, UInt<1>(0h0))
node _source_ok_T_123 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_124 = and(_source_ok_T_122, _source_ok_T_123)
node _source_ok_T_125 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_126 = and(_source_ok_T_124, _source_ok_T_125)
node _source_ok_uncommonBits_T_9 = or(io.in.c.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0)
node _source_ok_T_127 = shr(io.in.c.bits.source, 2)
node _source_ok_T_128 = eq(_source_ok_T_127, UInt<1>(0h1))
node _source_ok_T_129 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_130 = and(_source_ok_T_128, _source_ok_T_129)
node _source_ok_T_131 = leq(source_ok_uncommonBits_9, UInt<2>(0h3))
node _source_ok_T_132 = and(_source_ok_T_130, _source_ok_T_131)
node _source_ok_uncommonBits_T_10 = or(io.in.c.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0)
node _source_ok_T_133 = shr(io.in.c.bits.source, 2)
node _source_ok_T_134 = eq(_source_ok_T_133, UInt<2>(0h2))
node _source_ok_T_135 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_136 = and(_source_ok_T_134, _source_ok_T_135)
node _source_ok_T_137 = leq(source_ok_uncommonBits_10, UInt<2>(0h3))
node _source_ok_T_138 = and(_source_ok_T_136, _source_ok_T_137)
node _source_ok_uncommonBits_T_11 = or(io.in.c.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 1, 0)
node _source_ok_T_139 = shr(io.in.c.bits.source, 2)
node _source_ok_T_140 = eq(_source_ok_T_139, UInt<2>(0h3))
node _source_ok_T_141 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_142 = and(_source_ok_T_140, _source_ok_T_141)
node _source_ok_T_143 = leq(source_ok_uncommonBits_11, UInt<2>(0h3))
node _source_ok_T_144 = and(_source_ok_T_142, _source_ok_T_143)
node _source_ok_T_145 = eq(io.in.c.bits.source, UInt<6>(0h3c))
node _source_ok_T_146 = eq(io.in.c.bits.source, UInt<6>(0h3e))
node _source_ok_T_147 = eq(io.in.c.bits.source, UInt<6>(0h38))
node _source_ok_T_148 = eq(io.in.c.bits.source, UInt<6>(0h3a))
node _source_ok_T_149 = eq(io.in.c.bits.source, UInt<6>(0h34))
node _source_ok_T_150 = eq(io.in.c.bits.source, UInt<6>(0h36))
node _source_ok_T_151 = eq(io.in.c.bits.source, UInt<6>(0h30))
node _source_ok_T_152 = eq(io.in.c.bits.source, UInt<6>(0h32))
node _source_ok_T_153 = eq(io.in.c.bits.source, UInt<6>(0h2c))
node _source_ok_T_154 = eq(io.in.c.bits.source, UInt<6>(0h2e))
node _source_ok_T_155 = eq(io.in.c.bits.source, UInt<6>(0h28))
node _source_ok_T_156 = eq(io.in.c.bits.source, UInt<6>(0h2a))
node _source_ok_T_157 = eq(io.in.c.bits.source, UInt<6>(0h24))
node _source_ok_T_158 = eq(io.in.c.bits.source, UInt<6>(0h26))
node _source_ok_T_159 = eq(io.in.c.bits.source, UInt<6>(0h20))
node _source_ok_T_160 = eq(io.in.c.bits.source, UInt<6>(0h22))
wire _source_ok_WIRE_2 : UInt<1>[21]
connect _source_ok_WIRE_2[0], _source_ok_T_120
connect _source_ok_WIRE_2[1], _source_ok_T_126
connect _source_ok_WIRE_2[2], _source_ok_T_132
connect _source_ok_WIRE_2[3], _source_ok_T_138
connect _source_ok_WIRE_2[4], _source_ok_T_144
connect _source_ok_WIRE_2[5], _source_ok_T_145
connect _source_ok_WIRE_2[6], _source_ok_T_146
connect _source_ok_WIRE_2[7], _source_ok_T_147
connect _source_ok_WIRE_2[8], _source_ok_T_148
connect _source_ok_WIRE_2[9], _source_ok_T_149
connect _source_ok_WIRE_2[10], _source_ok_T_150
connect _source_ok_WIRE_2[11], _source_ok_T_151
connect _source_ok_WIRE_2[12], _source_ok_T_152
connect _source_ok_WIRE_2[13], _source_ok_T_153
connect _source_ok_WIRE_2[14], _source_ok_T_154
connect _source_ok_WIRE_2[15], _source_ok_T_155
connect _source_ok_WIRE_2[16], _source_ok_T_156
connect _source_ok_WIRE_2[17], _source_ok_T_157
connect _source_ok_WIRE_2[18], _source_ok_T_158
connect _source_ok_WIRE_2[19], _source_ok_T_159
connect _source_ok_WIRE_2[20], _source_ok_T_160
node _source_ok_T_161 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1])
node _source_ok_T_162 = or(_source_ok_T_161, _source_ok_WIRE_2[2])
node _source_ok_T_163 = or(_source_ok_T_162, _source_ok_WIRE_2[3])
node _source_ok_T_164 = or(_source_ok_T_163, _source_ok_WIRE_2[4])
node _source_ok_T_165 = or(_source_ok_T_164, _source_ok_WIRE_2[5])
node _source_ok_T_166 = or(_source_ok_T_165, _source_ok_WIRE_2[6])
node _source_ok_T_167 = or(_source_ok_T_166, _source_ok_WIRE_2[7])
node _source_ok_T_168 = or(_source_ok_T_167, _source_ok_WIRE_2[8])
node _source_ok_T_169 = or(_source_ok_T_168, _source_ok_WIRE_2[9])
node _source_ok_T_170 = or(_source_ok_T_169, _source_ok_WIRE_2[10])
node _source_ok_T_171 = or(_source_ok_T_170, _source_ok_WIRE_2[11])
node _source_ok_T_172 = or(_source_ok_T_171, _source_ok_WIRE_2[12])
node _source_ok_T_173 = or(_source_ok_T_172, _source_ok_WIRE_2[13])
node _source_ok_T_174 = or(_source_ok_T_173, _source_ok_WIRE_2[14])
node _source_ok_T_175 = or(_source_ok_T_174, _source_ok_WIRE_2[15])
node _source_ok_T_176 = or(_source_ok_T_175, _source_ok_WIRE_2[16])
node _source_ok_T_177 = or(_source_ok_T_176, _source_ok_WIRE_2[17])
node _source_ok_T_178 = or(_source_ok_T_177, _source_ok_WIRE_2[18])
node _source_ok_T_179 = or(_source_ok_T_178, _source_ok_WIRE_2[19])
node source_ok_2 = or(_source_ok_T_179, _source_ok_WIRE_2[20])
node _is_aligned_mask_T_4 = dshl(UInt<6>(0h3f), io.in.c.bits.size)
node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 5, 0)
node is_aligned_mask_2 = not(_is_aligned_mask_T_5)
node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2)
node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0))
node _address_ok_T_10 = xor(io.in.c.bits.address, UInt<28>(0h8000080))
node _address_ok_T_11 = cvt(_address_ok_T_10)
node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<17>(0h100c0)))
node _address_ok_T_13 = asSInt(_address_ok_T_12)
node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0)))
node _address_ok_T_15 = xor(io.in.c.bits.address, UInt<32>(0h80000080))
node _address_ok_T_16 = cvt(_address_ok_T_15)
node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<29>(0h100000c0)))
node _address_ok_T_18 = asSInt(_address_ok_T_17)
node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE_1 : UInt<1>[2]
connect _address_ok_WIRE_1[0], _address_ok_T_14
connect _address_ok_WIRE_1[1], _address_ok_T_19
node address_ok_1 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1])
node _T_2008 = eq(io.in.c.bits.source, UInt<5>(0h10))
node _T_2009 = eq(_T_2008, UInt<1>(0h0))
node _T_2010 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2011 = cvt(_T_2010)
node _T_2012 = and(_T_2011, asSInt(UInt<1>(0h0)))
node _T_2013 = asSInt(_T_2012)
node _T_2014 = eq(_T_2013, asSInt(UInt<1>(0h0)))
node _T_2015 = or(_T_2009, _T_2014)
node _uncommonBits_T_52 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0)
node _T_2016 = shr(io.in.c.bits.source, 2)
node _T_2017 = eq(_T_2016, UInt<1>(0h0))
node _T_2018 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_2019 = and(_T_2017, _T_2018)
node _T_2020 = leq(uncommonBits_52, UInt<2>(0h3))
node _T_2021 = and(_T_2019, _T_2020)
node _T_2022 = eq(_T_2021, UInt<1>(0h0))
node _T_2023 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2024 = cvt(_T_2023)
node _T_2025 = and(_T_2024, asSInt(UInt<1>(0h0)))
node _T_2026 = asSInt(_T_2025)
node _T_2027 = eq(_T_2026, asSInt(UInt<1>(0h0)))
node _T_2028 = or(_T_2022, _T_2027)
node _uncommonBits_T_53 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0)
node _T_2029 = shr(io.in.c.bits.source, 2)
node _T_2030 = eq(_T_2029, UInt<1>(0h1))
node _T_2031 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_2032 = and(_T_2030, _T_2031)
node _T_2033 = leq(uncommonBits_53, UInt<2>(0h3))
node _T_2034 = and(_T_2032, _T_2033)
node _T_2035 = eq(_T_2034, UInt<1>(0h0))
node _T_2036 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2037 = cvt(_T_2036)
node _T_2038 = and(_T_2037, asSInt(UInt<1>(0h0)))
node _T_2039 = asSInt(_T_2038)
node _T_2040 = eq(_T_2039, asSInt(UInt<1>(0h0)))
node _T_2041 = or(_T_2035, _T_2040)
node _uncommonBits_T_54 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0)
node _T_2042 = shr(io.in.c.bits.source, 2)
node _T_2043 = eq(_T_2042, UInt<2>(0h2))
node _T_2044 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_2045 = and(_T_2043, _T_2044)
node _T_2046 = leq(uncommonBits_54, UInt<2>(0h3))
node _T_2047 = and(_T_2045, _T_2046)
node _T_2048 = eq(_T_2047, UInt<1>(0h0))
node _T_2049 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2050 = cvt(_T_2049)
node _T_2051 = and(_T_2050, asSInt(UInt<1>(0h0)))
node _T_2052 = asSInt(_T_2051)
node _T_2053 = eq(_T_2052, asSInt(UInt<1>(0h0)))
node _T_2054 = or(_T_2048, _T_2053)
node _uncommonBits_T_55 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0)
node _T_2055 = shr(io.in.c.bits.source, 2)
node _T_2056 = eq(_T_2055, UInt<2>(0h3))
node _T_2057 = leq(UInt<1>(0h0), uncommonBits_55)
node _T_2058 = and(_T_2056, _T_2057)
node _T_2059 = leq(uncommonBits_55, UInt<2>(0h3))
node _T_2060 = and(_T_2058, _T_2059)
node _T_2061 = eq(_T_2060, UInt<1>(0h0))
node _T_2062 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2063 = cvt(_T_2062)
node _T_2064 = and(_T_2063, asSInt(UInt<1>(0h0)))
node _T_2065 = asSInt(_T_2064)
node _T_2066 = eq(_T_2065, asSInt(UInt<1>(0h0)))
node _T_2067 = or(_T_2061, _T_2066)
node _T_2068 = eq(io.in.c.bits.source, UInt<6>(0h3c))
node _T_2069 = eq(_T_2068, UInt<1>(0h0))
node _T_2070 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2071 = cvt(_T_2070)
node _T_2072 = and(_T_2071, asSInt(UInt<1>(0h0)))
node _T_2073 = asSInt(_T_2072)
node _T_2074 = eq(_T_2073, asSInt(UInt<1>(0h0)))
node _T_2075 = or(_T_2069, _T_2074)
node _T_2076 = eq(io.in.c.bits.source, UInt<6>(0h3e))
node _T_2077 = eq(_T_2076, UInt<1>(0h0))
node _T_2078 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2079 = cvt(_T_2078)
node _T_2080 = and(_T_2079, asSInt(UInt<1>(0h0)))
node _T_2081 = asSInt(_T_2080)
node _T_2082 = eq(_T_2081, asSInt(UInt<1>(0h0)))
node _T_2083 = or(_T_2077, _T_2082)
node _T_2084 = eq(io.in.c.bits.source, UInt<6>(0h38))
node _T_2085 = eq(_T_2084, UInt<1>(0h0))
node _T_2086 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2087 = cvt(_T_2086)
node _T_2088 = and(_T_2087, asSInt(UInt<1>(0h0)))
node _T_2089 = asSInt(_T_2088)
node _T_2090 = eq(_T_2089, asSInt(UInt<1>(0h0)))
node _T_2091 = or(_T_2085, _T_2090)
node _T_2092 = eq(io.in.c.bits.source, UInt<6>(0h3a))
node _T_2093 = eq(_T_2092, UInt<1>(0h0))
node _T_2094 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2095 = cvt(_T_2094)
node _T_2096 = and(_T_2095, asSInt(UInt<1>(0h0)))
node _T_2097 = asSInt(_T_2096)
node _T_2098 = eq(_T_2097, asSInt(UInt<1>(0h0)))
node _T_2099 = or(_T_2093, _T_2098)
node _T_2100 = eq(io.in.c.bits.source, UInt<6>(0h34))
node _T_2101 = eq(_T_2100, UInt<1>(0h0))
node _T_2102 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2103 = cvt(_T_2102)
node _T_2104 = and(_T_2103, asSInt(UInt<1>(0h0)))
node _T_2105 = asSInt(_T_2104)
node _T_2106 = eq(_T_2105, asSInt(UInt<1>(0h0)))
node _T_2107 = or(_T_2101, _T_2106)
node _T_2108 = eq(io.in.c.bits.source, UInt<6>(0h36))
node _T_2109 = eq(_T_2108, UInt<1>(0h0))
node _T_2110 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2111 = cvt(_T_2110)
node _T_2112 = and(_T_2111, asSInt(UInt<1>(0h0)))
node _T_2113 = asSInt(_T_2112)
node _T_2114 = eq(_T_2113, asSInt(UInt<1>(0h0)))
node _T_2115 = or(_T_2109, _T_2114)
node _T_2116 = eq(io.in.c.bits.source, UInt<6>(0h30))
node _T_2117 = eq(_T_2116, UInt<1>(0h0))
node _T_2118 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2119 = cvt(_T_2118)
node _T_2120 = and(_T_2119, asSInt(UInt<1>(0h0)))
node _T_2121 = asSInt(_T_2120)
node _T_2122 = eq(_T_2121, asSInt(UInt<1>(0h0)))
node _T_2123 = or(_T_2117, _T_2122)
node _T_2124 = eq(io.in.c.bits.source, UInt<6>(0h32))
node _T_2125 = eq(_T_2124, UInt<1>(0h0))
node _T_2126 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2127 = cvt(_T_2126)
node _T_2128 = and(_T_2127, asSInt(UInt<1>(0h0)))
node _T_2129 = asSInt(_T_2128)
node _T_2130 = eq(_T_2129, asSInt(UInt<1>(0h0)))
node _T_2131 = or(_T_2125, _T_2130)
node _T_2132 = eq(io.in.c.bits.source, UInt<6>(0h2c))
node _T_2133 = eq(_T_2132, UInt<1>(0h0))
node _T_2134 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2135 = cvt(_T_2134)
node _T_2136 = and(_T_2135, asSInt(UInt<1>(0h0)))
node _T_2137 = asSInt(_T_2136)
node _T_2138 = eq(_T_2137, asSInt(UInt<1>(0h0)))
node _T_2139 = or(_T_2133, _T_2138)
node _T_2140 = eq(io.in.c.bits.source, UInt<6>(0h2e))
node _T_2141 = eq(_T_2140, UInt<1>(0h0))
node _T_2142 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2143 = cvt(_T_2142)
node _T_2144 = and(_T_2143, asSInt(UInt<1>(0h0)))
node _T_2145 = asSInt(_T_2144)
node _T_2146 = eq(_T_2145, asSInt(UInt<1>(0h0)))
node _T_2147 = or(_T_2141, _T_2146)
node _T_2148 = eq(io.in.c.bits.source, UInt<6>(0h28))
node _T_2149 = eq(_T_2148, UInt<1>(0h0))
node _T_2150 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2151 = cvt(_T_2150)
node _T_2152 = and(_T_2151, asSInt(UInt<1>(0h0)))
node _T_2153 = asSInt(_T_2152)
node _T_2154 = eq(_T_2153, asSInt(UInt<1>(0h0)))
node _T_2155 = or(_T_2149, _T_2154)
node _T_2156 = eq(io.in.c.bits.source, UInt<6>(0h2a))
node _T_2157 = eq(_T_2156, UInt<1>(0h0))
node _T_2158 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2159 = cvt(_T_2158)
node _T_2160 = and(_T_2159, asSInt(UInt<1>(0h0)))
node _T_2161 = asSInt(_T_2160)
node _T_2162 = eq(_T_2161, asSInt(UInt<1>(0h0)))
node _T_2163 = or(_T_2157, _T_2162)
node _T_2164 = eq(io.in.c.bits.source, UInt<6>(0h24))
node _T_2165 = eq(_T_2164, UInt<1>(0h0))
node _T_2166 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2167 = cvt(_T_2166)
node _T_2168 = and(_T_2167, asSInt(UInt<1>(0h0)))
node _T_2169 = asSInt(_T_2168)
node _T_2170 = eq(_T_2169, asSInt(UInt<1>(0h0)))
node _T_2171 = or(_T_2165, _T_2170)
node _T_2172 = eq(io.in.c.bits.source, UInt<6>(0h26))
node _T_2173 = eq(_T_2172, UInt<1>(0h0))
node _T_2174 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2175 = cvt(_T_2174)
node _T_2176 = and(_T_2175, asSInt(UInt<1>(0h0)))
node _T_2177 = asSInt(_T_2176)
node _T_2178 = eq(_T_2177, asSInt(UInt<1>(0h0)))
node _T_2179 = or(_T_2173, _T_2178)
node _T_2180 = eq(io.in.c.bits.source, UInt<6>(0h20))
node _T_2181 = eq(_T_2180, UInt<1>(0h0))
node _T_2182 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2183 = cvt(_T_2182)
node _T_2184 = and(_T_2183, asSInt(UInt<1>(0h0)))
node _T_2185 = asSInt(_T_2184)
node _T_2186 = eq(_T_2185, asSInt(UInt<1>(0h0)))
node _T_2187 = or(_T_2181, _T_2186)
node _T_2188 = eq(io.in.c.bits.source, UInt<6>(0h22))
node _T_2189 = eq(_T_2188, UInt<1>(0h0))
node _T_2190 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2191 = cvt(_T_2190)
node _T_2192 = and(_T_2191, asSInt(UInt<1>(0h0)))
node _T_2193 = asSInt(_T_2192)
node _T_2194 = eq(_T_2193, asSInt(UInt<1>(0h0)))
node _T_2195 = or(_T_2189, _T_2194)
node _T_2196 = and(_T_2015, _T_2028)
node _T_2197 = and(_T_2196, _T_2041)
node _T_2198 = and(_T_2197, _T_2054)
node _T_2199 = and(_T_2198, _T_2067)
node _T_2200 = and(_T_2199, _T_2075)
node _T_2201 = and(_T_2200, _T_2083)
node _T_2202 = and(_T_2201, _T_2091)
node _T_2203 = and(_T_2202, _T_2099)
node _T_2204 = and(_T_2203, _T_2107)
node _T_2205 = and(_T_2204, _T_2115)
node _T_2206 = and(_T_2205, _T_2123)
node _T_2207 = and(_T_2206, _T_2131)
node _T_2208 = and(_T_2207, _T_2139)
node _T_2209 = and(_T_2208, _T_2147)
node _T_2210 = and(_T_2209, _T_2155)
node _T_2211 = and(_T_2210, _T_2163)
node _T_2212 = and(_T_2211, _T_2171)
node _T_2213 = and(_T_2212, _T_2179)
node _T_2214 = and(_T_2213, _T_2187)
node _T_2215 = and(_T_2214, _T_2195)
node _T_2216 = asUInt(reset)
node _T_2217 = eq(_T_2216, UInt<1>(0h0))
when _T_2217 :
node _T_2218 = eq(_T_2215, UInt<1>(0h0))
when _T_2218 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131
assert(clock, _T_2215, UInt<1>(0h1), "") : assert_131
node _T_2219 = eq(io.in.c.bits.opcode, UInt<3>(0h4))
when _T_2219 :
node _T_2220 = asUInt(reset)
node _T_2221 = eq(_T_2220, UInt<1>(0h0))
when _T_2221 :
node _T_2222 = eq(address_ok_1, UInt<1>(0h0))
when _T_2222 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132
node _T_2223 = asUInt(reset)
node _T_2224 = eq(_T_2223, UInt<1>(0h0))
when _T_2224 :
node _T_2225 = eq(source_ok_2, UInt<1>(0h0))
when _T_2225 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133
node _T_2226 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_2227 = asUInt(reset)
node _T_2228 = eq(_T_2227, UInt<1>(0h0))
when _T_2228 :
node _T_2229 = eq(_T_2226, UInt<1>(0h0))
when _T_2229 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134
assert(clock, _T_2226, UInt<1>(0h1), "") : assert_134
node _T_2230 = asUInt(reset)
node _T_2231 = eq(_T_2230, UInt<1>(0h0))
when _T_2231 :
node _T_2232 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2232 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135
node _T_2233 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_2234 = asUInt(reset)
node _T_2235 = eq(_T_2234, UInt<1>(0h0))
when _T_2235 :
node _T_2236 = eq(_T_2233, UInt<1>(0h0))
when _T_2236 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136
assert(clock, _T_2233, UInt<1>(0h1), "") : assert_136
node _T_2237 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2238 = asUInt(reset)
node _T_2239 = eq(_T_2238, UInt<1>(0h0))
when _T_2239 :
node _T_2240 = eq(_T_2237, UInt<1>(0h0))
when _T_2240 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137
assert(clock, _T_2237, UInt<1>(0h1), "") : assert_137
node _T_2241 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
when _T_2241 :
node _T_2242 = asUInt(reset)
node _T_2243 = eq(_T_2242, UInt<1>(0h0))
when _T_2243 :
node _T_2244 = eq(address_ok_1, UInt<1>(0h0))
when _T_2244 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138
node _T_2245 = asUInt(reset)
node _T_2246 = eq(_T_2245, UInt<1>(0h0))
when _T_2246 :
node _T_2247 = eq(source_ok_2, UInt<1>(0h0))
when _T_2247 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139
node _T_2248 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_2249 = asUInt(reset)
node _T_2250 = eq(_T_2249, UInt<1>(0h0))
when _T_2250 :
node _T_2251 = eq(_T_2248, UInt<1>(0h0))
when _T_2251 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140
assert(clock, _T_2248, UInt<1>(0h1), "") : assert_140
node _T_2252 = asUInt(reset)
node _T_2253 = eq(_T_2252, UInt<1>(0h0))
when _T_2253 :
node _T_2254 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2254 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141
node _T_2255 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_2256 = asUInt(reset)
node _T_2257 = eq(_T_2256, UInt<1>(0h0))
when _T_2257 :
node _T_2258 = eq(_T_2255, UInt<1>(0h0))
when _T_2258 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142
assert(clock, _T_2255, UInt<1>(0h1), "") : assert_142
node _T_2259 = eq(io.in.c.bits.opcode, UInt<3>(0h6))
when _T_2259 :
node _T_2260 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2261 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2262 = and(_T_2260, _T_2261)
node _T_2263 = eq(io.in.c.bits.source, UInt<5>(0h10))
node _uncommonBits_T_56 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0)
node _T_2264 = shr(io.in.c.bits.source, 2)
node _T_2265 = eq(_T_2264, UInt<1>(0h0))
node _T_2266 = leq(UInt<1>(0h0), uncommonBits_56)
node _T_2267 = and(_T_2265, _T_2266)
node _T_2268 = leq(uncommonBits_56, UInt<2>(0h3))
node _T_2269 = and(_T_2267, _T_2268)
node _uncommonBits_T_57 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0)
node _T_2270 = shr(io.in.c.bits.source, 2)
node _T_2271 = eq(_T_2270, UInt<1>(0h1))
node _T_2272 = leq(UInt<1>(0h0), uncommonBits_57)
node _T_2273 = and(_T_2271, _T_2272)
node _T_2274 = leq(uncommonBits_57, UInt<2>(0h3))
node _T_2275 = and(_T_2273, _T_2274)
node _uncommonBits_T_58 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0)
node _T_2276 = shr(io.in.c.bits.source, 2)
node _T_2277 = eq(_T_2276, UInt<2>(0h2))
node _T_2278 = leq(UInt<1>(0h0), uncommonBits_58)
node _T_2279 = and(_T_2277, _T_2278)
node _T_2280 = leq(uncommonBits_58, UInt<2>(0h3))
node _T_2281 = and(_T_2279, _T_2280)
node _uncommonBits_T_59 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_59 = bits(_uncommonBits_T_59, 1, 0)
node _T_2282 = shr(io.in.c.bits.source, 2)
node _T_2283 = eq(_T_2282, UInt<2>(0h3))
node _T_2284 = leq(UInt<1>(0h0), uncommonBits_59)
node _T_2285 = and(_T_2283, _T_2284)
node _T_2286 = leq(uncommonBits_59, UInt<2>(0h3))
node _T_2287 = and(_T_2285, _T_2286)
node _T_2288 = eq(io.in.c.bits.source, UInt<6>(0h3c))
node _T_2289 = eq(io.in.c.bits.source, UInt<6>(0h3e))
node _T_2290 = eq(io.in.c.bits.source, UInt<6>(0h38))
node _T_2291 = eq(io.in.c.bits.source, UInt<6>(0h3a))
node _T_2292 = eq(io.in.c.bits.source, UInt<6>(0h34))
node _T_2293 = eq(io.in.c.bits.source, UInt<6>(0h36))
node _T_2294 = eq(io.in.c.bits.source, UInt<6>(0h30))
node _T_2295 = eq(io.in.c.bits.source, UInt<6>(0h32))
node _T_2296 = eq(io.in.c.bits.source, UInt<6>(0h2c))
node _T_2297 = eq(io.in.c.bits.source, UInt<6>(0h2e))
node _T_2298 = eq(io.in.c.bits.source, UInt<6>(0h28))
node _T_2299 = eq(io.in.c.bits.source, UInt<6>(0h2a))
node _T_2300 = eq(io.in.c.bits.source, UInt<6>(0h24))
node _T_2301 = eq(io.in.c.bits.source, UInt<6>(0h26))
node _T_2302 = eq(io.in.c.bits.source, UInt<6>(0h20))
node _T_2303 = eq(io.in.c.bits.source, UInt<6>(0h22))
node _T_2304 = or(_T_2263, _T_2269)
node _T_2305 = or(_T_2304, _T_2275)
node _T_2306 = or(_T_2305, _T_2281)
node _T_2307 = or(_T_2306, _T_2287)
node _T_2308 = or(_T_2307, _T_2288)
node _T_2309 = or(_T_2308, _T_2289)
node _T_2310 = or(_T_2309, _T_2290)
node _T_2311 = or(_T_2310, _T_2291)
node _T_2312 = or(_T_2311, _T_2292)
node _T_2313 = or(_T_2312, _T_2293)
node _T_2314 = or(_T_2313, _T_2294)
node _T_2315 = or(_T_2314, _T_2295)
node _T_2316 = or(_T_2315, _T_2296)
node _T_2317 = or(_T_2316, _T_2297)
node _T_2318 = or(_T_2317, _T_2298)
node _T_2319 = or(_T_2318, _T_2299)
node _T_2320 = or(_T_2319, _T_2300)
node _T_2321 = or(_T_2320, _T_2301)
node _T_2322 = or(_T_2321, _T_2302)
node _T_2323 = or(_T_2322, _T_2303)
node _T_2324 = and(_T_2262, _T_2323)
node _T_2325 = or(UInt<1>(0h0), _T_2324)
node _T_2326 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2327 = or(UInt<1>(0h0), _T_2326)
node _T_2328 = xor(io.in.c.bits.address, UInt<28>(0h8000080))
node _T_2329 = cvt(_T_2328)
node _T_2330 = and(_T_2329, asSInt(UInt<17>(0h100c0)))
node _T_2331 = asSInt(_T_2330)
node _T_2332 = eq(_T_2331, asSInt(UInt<1>(0h0)))
node _T_2333 = xor(io.in.c.bits.address, UInt<32>(0h80000080))
node _T_2334 = cvt(_T_2333)
node _T_2335 = and(_T_2334, asSInt(UInt<29>(0h100000c0)))
node _T_2336 = asSInt(_T_2335)
node _T_2337 = eq(_T_2336, asSInt(UInt<1>(0h0)))
node _T_2338 = or(_T_2332, _T_2337)
node _T_2339 = and(_T_2327, _T_2338)
node _T_2340 = or(UInt<1>(0h0), _T_2339)
node _T_2341 = and(_T_2325, _T_2340)
node _T_2342 = asUInt(reset)
node _T_2343 = eq(_T_2342, UInt<1>(0h0))
when _T_2343 :
node _T_2344 = eq(_T_2341, UInt<1>(0h0))
when _T_2344 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143
assert(clock, _T_2341, UInt<1>(0h1), "") : assert_143
node _T_2345 = eq(io.in.c.bits.source, UInt<5>(0h10))
node _uncommonBits_T_60 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0)
node _T_2346 = shr(io.in.c.bits.source, 2)
node _T_2347 = eq(_T_2346, UInt<1>(0h0))
node _T_2348 = leq(UInt<1>(0h0), uncommonBits_60)
node _T_2349 = and(_T_2347, _T_2348)
node _T_2350 = leq(uncommonBits_60, UInt<2>(0h3))
node _T_2351 = and(_T_2349, _T_2350)
node _uncommonBits_T_61 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0)
node _T_2352 = shr(io.in.c.bits.source, 2)
node _T_2353 = eq(_T_2352, UInt<1>(0h1))
node _T_2354 = leq(UInt<1>(0h0), uncommonBits_61)
node _T_2355 = and(_T_2353, _T_2354)
node _T_2356 = leq(uncommonBits_61, UInt<2>(0h3))
node _T_2357 = and(_T_2355, _T_2356)
node _uncommonBits_T_62 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0)
node _T_2358 = shr(io.in.c.bits.source, 2)
node _T_2359 = eq(_T_2358, UInt<2>(0h2))
node _T_2360 = leq(UInt<1>(0h0), uncommonBits_62)
node _T_2361 = and(_T_2359, _T_2360)
node _T_2362 = leq(uncommonBits_62, UInt<2>(0h3))
node _T_2363 = and(_T_2361, _T_2362)
node _uncommonBits_T_63 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0)
node _T_2364 = shr(io.in.c.bits.source, 2)
node _T_2365 = eq(_T_2364, UInt<2>(0h3))
node _T_2366 = leq(UInt<1>(0h0), uncommonBits_63)
node _T_2367 = and(_T_2365, _T_2366)
node _T_2368 = leq(uncommonBits_63, UInt<2>(0h3))
node _T_2369 = and(_T_2367, _T_2368)
node _T_2370 = eq(io.in.c.bits.source, UInt<6>(0h3c))
node _T_2371 = eq(io.in.c.bits.source, UInt<6>(0h3e))
node _T_2372 = eq(io.in.c.bits.source, UInt<6>(0h38))
node _T_2373 = eq(io.in.c.bits.source, UInt<6>(0h3a))
node _T_2374 = eq(io.in.c.bits.source, UInt<6>(0h34))
node _T_2375 = eq(io.in.c.bits.source, UInt<6>(0h36))
node _T_2376 = eq(io.in.c.bits.source, UInt<6>(0h30))
node _T_2377 = eq(io.in.c.bits.source, UInt<6>(0h32))
node _T_2378 = eq(io.in.c.bits.source, UInt<6>(0h2c))
node _T_2379 = eq(io.in.c.bits.source, UInt<6>(0h2e))
node _T_2380 = eq(io.in.c.bits.source, UInt<6>(0h28))
node _T_2381 = eq(io.in.c.bits.source, UInt<6>(0h2a))
node _T_2382 = eq(io.in.c.bits.source, UInt<6>(0h24))
node _T_2383 = eq(io.in.c.bits.source, UInt<6>(0h26))
node _T_2384 = eq(io.in.c.bits.source, UInt<6>(0h20))
node _T_2385 = eq(io.in.c.bits.source, UInt<6>(0h22))
wire _WIRE_6 : UInt<1>[21]
connect _WIRE_6[0], _T_2345
connect _WIRE_6[1], _T_2351
connect _WIRE_6[2], _T_2357
connect _WIRE_6[3], _T_2363
connect _WIRE_6[4], _T_2369
connect _WIRE_6[5], _T_2370
connect _WIRE_6[6], _T_2371
connect _WIRE_6[7], _T_2372
connect _WIRE_6[8], _T_2373
connect _WIRE_6[9], _T_2374
connect _WIRE_6[10], _T_2375
connect _WIRE_6[11], _T_2376
connect _WIRE_6[12], _T_2377
connect _WIRE_6[13], _T_2378
connect _WIRE_6[14], _T_2379
connect _WIRE_6[15], _T_2380
connect _WIRE_6[16], _T_2381
connect _WIRE_6[17], _T_2382
connect _WIRE_6[18], _T_2383
connect _WIRE_6[19], _T_2384
connect _WIRE_6[20], _T_2385
node _T_2386 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2387 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2388 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2389 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2390 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2391 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2392 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2393 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2394 = mux(_WIRE_6[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_2395 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_2396 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_2397 = mux(_WIRE_6[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_2398 = mux(_WIRE_6[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_2399 = mux(_WIRE_6[5], _T_2386, UInt<1>(0h0))
node _T_2400 = mux(_WIRE_6[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_2401 = mux(_WIRE_6[7], _T_2387, UInt<1>(0h0))
node _T_2402 = mux(_WIRE_6[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_2403 = mux(_WIRE_6[9], _T_2388, UInt<1>(0h0))
node _T_2404 = mux(_WIRE_6[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_2405 = mux(_WIRE_6[11], _T_2389, UInt<1>(0h0))
node _T_2406 = mux(_WIRE_6[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_2407 = mux(_WIRE_6[13], _T_2390, UInt<1>(0h0))
node _T_2408 = mux(_WIRE_6[14], UInt<1>(0h0), UInt<1>(0h0))
node _T_2409 = mux(_WIRE_6[15], _T_2391, UInt<1>(0h0))
node _T_2410 = mux(_WIRE_6[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_2411 = mux(_WIRE_6[17], _T_2392, UInt<1>(0h0))
node _T_2412 = mux(_WIRE_6[18], UInt<1>(0h0), UInt<1>(0h0))
node _T_2413 = mux(_WIRE_6[19], _T_2393, UInt<1>(0h0))
node _T_2414 = mux(_WIRE_6[20], UInt<1>(0h0), UInt<1>(0h0))
node _T_2415 = or(_T_2394, _T_2395)
node _T_2416 = or(_T_2415, _T_2396)
node _T_2417 = or(_T_2416, _T_2397)
node _T_2418 = or(_T_2417, _T_2398)
node _T_2419 = or(_T_2418, _T_2399)
node _T_2420 = or(_T_2419, _T_2400)
node _T_2421 = or(_T_2420, _T_2401)
node _T_2422 = or(_T_2421, _T_2402)
node _T_2423 = or(_T_2422, _T_2403)
node _T_2424 = or(_T_2423, _T_2404)
node _T_2425 = or(_T_2424, _T_2405)
node _T_2426 = or(_T_2425, _T_2406)
node _T_2427 = or(_T_2426, _T_2407)
node _T_2428 = or(_T_2427, _T_2408)
node _T_2429 = or(_T_2428, _T_2409)
node _T_2430 = or(_T_2429, _T_2410)
node _T_2431 = or(_T_2430, _T_2411)
node _T_2432 = or(_T_2431, _T_2412)
node _T_2433 = or(_T_2432, _T_2413)
node _T_2434 = or(_T_2433, _T_2414)
wire _WIRE_7 : UInt<1>
connect _WIRE_7, _T_2434
node _T_2435 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2436 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2437 = and(_T_2435, _T_2436)
node _T_2438 = or(UInt<1>(0h0), _T_2437)
node _T_2439 = xor(io.in.c.bits.address, UInt<28>(0h8000080))
node _T_2440 = cvt(_T_2439)
node _T_2441 = and(_T_2440, asSInt(UInt<17>(0h100c0)))
node _T_2442 = asSInt(_T_2441)
node _T_2443 = eq(_T_2442, asSInt(UInt<1>(0h0)))
node _T_2444 = xor(io.in.c.bits.address, UInt<32>(0h80000080))
node _T_2445 = cvt(_T_2444)
node _T_2446 = and(_T_2445, asSInt(UInt<29>(0h100000c0)))
node _T_2447 = asSInt(_T_2446)
node _T_2448 = eq(_T_2447, asSInt(UInt<1>(0h0)))
node _T_2449 = or(_T_2443, _T_2448)
node _T_2450 = and(_T_2438, _T_2449)
node _T_2451 = or(UInt<1>(0h0), _T_2450)
node _T_2452 = and(_WIRE_7, _T_2451)
node _T_2453 = asUInt(reset)
node _T_2454 = eq(_T_2453, UInt<1>(0h0))
when _T_2454 :
node _T_2455 = eq(_T_2452, UInt<1>(0h0))
when _T_2455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144
assert(clock, _T_2452, UInt<1>(0h1), "") : assert_144
node _T_2456 = asUInt(reset)
node _T_2457 = eq(_T_2456, UInt<1>(0h0))
when _T_2457 :
node _T_2458 = eq(source_ok_2, UInt<1>(0h0))
when _T_2458 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145
node _T_2459 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_2460 = asUInt(reset)
node _T_2461 = eq(_T_2460, UInt<1>(0h0))
when _T_2461 :
node _T_2462 = eq(_T_2459, UInt<1>(0h0))
when _T_2462 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146
assert(clock, _T_2459, UInt<1>(0h1), "") : assert_146
node _T_2463 = asUInt(reset)
node _T_2464 = eq(_T_2463, UInt<1>(0h0))
when _T_2464 :
node _T_2465 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2465 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147
node _T_2466 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_2467 = asUInt(reset)
node _T_2468 = eq(_T_2467, UInt<1>(0h0))
when _T_2468 :
node _T_2469 = eq(_T_2466, UInt<1>(0h0))
when _T_2469 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148
assert(clock, _T_2466, UInt<1>(0h1), "") : assert_148
node _T_2470 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2471 = asUInt(reset)
node _T_2472 = eq(_T_2471, UInt<1>(0h0))
when _T_2472 :
node _T_2473 = eq(_T_2470, UInt<1>(0h0))
when _T_2473 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149
assert(clock, _T_2470, UInt<1>(0h1), "") : assert_149
node _T_2474 = eq(io.in.c.bits.opcode, UInt<3>(0h7))
when _T_2474 :
node _T_2475 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2476 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2477 = and(_T_2475, _T_2476)
node _T_2478 = eq(io.in.c.bits.source, UInt<5>(0h10))
node _uncommonBits_T_64 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_64 = bits(_uncommonBits_T_64, 1, 0)
node _T_2479 = shr(io.in.c.bits.source, 2)
node _T_2480 = eq(_T_2479, UInt<1>(0h0))
node _T_2481 = leq(UInt<1>(0h0), uncommonBits_64)
node _T_2482 = and(_T_2480, _T_2481)
node _T_2483 = leq(uncommonBits_64, UInt<2>(0h3))
node _T_2484 = and(_T_2482, _T_2483)
node _uncommonBits_T_65 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0)
node _T_2485 = shr(io.in.c.bits.source, 2)
node _T_2486 = eq(_T_2485, UInt<1>(0h1))
node _T_2487 = leq(UInt<1>(0h0), uncommonBits_65)
node _T_2488 = and(_T_2486, _T_2487)
node _T_2489 = leq(uncommonBits_65, UInt<2>(0h3))
node _T_2490 = and(_T_2488, _T_2489)
node _uncommonBits_T_66 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0)
node _T_2491 = shr(io.in.c.bits.source, 2)
node _T_2492 = eq(_T_2491, UInt<2>(0h2))
node _T_2493 = leq(UInt<1>(0h0), uncommonBits_66)
node _T_2494 = and(_T_2492, _T_2493)
node _T_2495 = leq(uncommonBits_66, UInt<2>(0h3))
node _T_2496 = and(_T_2494, _T_2495)
node _uncommonBits_T_67 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_67 = bits(_uncommonBits_T_67, 1, 0)
node _T_2497 = shr(io.in.c.bits.source, 2)
node _T_2498 = eq(_T_2497, UInt<2>(0h3))
node _T_2499 = leq(UInt<1>(0h0), uncommonBits_67)
node _T_2500 = and(_T_2498, _T_2499)
node _T_2501 = leq(uncommonBits_67, UInt<2>(0h3))
node _T_2502 = and(_T_2500, _T_2501)
node _T_2503 = eq(io.in.c.bits.source, UInt<6>(0h3c))
node _T_2504 = eq(io.in.c.bits.source, UInt<6>(0h3e))
node _T_2505 = eq(io.in.c.bits.source, UInt<6>(0h38))
node _T_2506 = eq(io.in.c.bits.source, UInt<6>(0h3a))
node _T_2507 = eq(io.in.c.bits.source, UInt<6>(0h34))
node _T_2508 = eq(io.in.c.bits.source, UInt<6>(0h36))
node _T_2509 = eq(io.in.c.bits.source, UInt<6>(0h30))
node _T_2510 = eq(io.in.c.bits.source, UInt<6>(0h32))
node _T_2511 = eq(io.in.c.bits.source, UInt<6>(0h2c))
node _T_2512 = eq(io.in.c.bits.source, UInt<6>(0h2e))
node _T_2513 = eq(io.in.c.bits.source, UInt<6>(0h28))
node _T_2514 = eq(io.in.c.bits.source, UInt<6>(0h2a))
node _T_2515 = eq(io.in.c.bits.source, UInt<6>(0h24))
node _T_2516 = eq(io.in.c.bits.source, UInt<6>(0h26))
node _T_2517 = eq(io.in.c.bits.source, UInt<6>(0h20))
node _T_2518 = eq(io.in.c.bits.source, UInt<6>(0h22))
node _T_2519 = or(_T_2478, _T_2484)
node _T_2520 = or(_T_2519, _T_2490)
node _T_2521 = or(_T_2520, _T_2496)
node _T_2522 = or(_T_2521, _T_2502)
node _T_2523 = or(_T_2522, _T_2503)
node _T_2524 = or(_T_2523, _T_2504)
node _T_2525 = or(_T_2524, _T_2505)
node _T_2526 = or(_T_2525, _T_2506)
node _T_2527 = or(_T_2526, _T_2507)
node _T_2528 = or(_T_2527, _T_2508)
node _T_2529 = or(_T_2528, _T_2509)
node _T_2530 = or(_T_2529, _T_2510)
node _T_2531 = or(_T_2530, _T_2511)
node _T_2532 = or(_T_2531, _T_2512)
node _T_2533 = or(_T_2532, _T_2513)
node _T_2534 = or(_T_2533, _T_2514)
node _T_2535 = or(_T_2534, _T_2515)
node _T_2536 = or(_T_2535, _T_2516)
node _T_2537 = or(_T_2536, _T_2517)
node _T_2538 = or(_T_2537, _T_2518)
node _T_2539 = and(_T_2477, _T_2538)
node _T_2540 = or(UInt<1>(0h0), _T_2539)
node _T_2541 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2542 = or(UInt<1>(0h0), _T_2541)
node _T_2543 = xor(io.in.c.bits.address, UInt<28>(0h8000080))
node _T_2544 = cvt(_T_2543)
node _T_2545 = and(_T_2544, asSInt(UInt<17>(0h100c0)))
node _T_2546 = asSInt(_T_2545)
node _T_2547 = eq(_T_2546, asSInt(UInt<1>(0h0)))
node _T_2548 = xor(io.in.c.bits.address, UInt<32>(0h80000080))
node _T_2549 = cvt(_T_2548)
node _T_2550 = and(_T_2549, asSInt(UInt<29>(0h100000c0)))
node _T_2551 = asSInt(_T_2550)
node _T_2552 = eq(_T_2551, asSInt(UInt<1>(0h0)))
node _T_2553 = or(_T_2547, _T_2552)
node _T_2554 = and(_T_2542, _T_2553)
node _T_2555 = or(UInt<1>(0h0), _T_2554)
node _T_2556 = and(_T_2540, _T_2555)
node _T_2557 = asUInt(reset)
node _T_2558 = eq(_T_2557, UInt<1>(0h0))
when _T_2558 :
node _T_2559 = eq(_T_2556, UInt<1>(0h0))
when _T_2559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150
assert(clock, _T_2556, UInt<1>(0h1), "") : assert_150
node _T_2560 = eq(io.in.c.bits.source, UInt<5>(0h10))
node _uncommonBits_T_68 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_68 = bits(_uncommonBits_T_68, 1, 0)
node _T_2561 = shr(io.in.c.bits.source, 2)
node _T_2562 = eq(_T_2561, UInt<1>(0h0))
node _T_2563 = leq(UInt<1>(0h0), uncommonBits_68)
node _T_2564 = and(_T_2562, _T_2563)
node _T_2565 = leq(uncommonBits_68, UInt<2>(0h3))
node _T_2566 = and(_T_2564, _T_2565)
node _uncommonBits_T_69 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_69 = bits(_uncommonBits_T_69, 1, 0)
node _T_2567 = shr(io.in.c.bits.source, 2)
node _T_2568 = eq(_T_2567, UInt<1>(0h1))
node _T_2569 = leq(UInt<1>(0h0), uncommonBits_69)
node _T_2570 = and(_T_2568, _T_2569)
node _T_2571 = leq(uncommonBits_69, UInt<2>(0h3))
node _T_2572 = and(_T_2570, _T_2571)
node _uncommonBits_T_70 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0)
node _T_2573 = shr(io.in.c.bits.source, 2)
node _T_2574 = eq(_T_2573, UInt<2>(0h2))
node _T_2575 = leq(UInt<1>(0h0), uncommonBits_70)
node _T_2576 = and(_T_2574, _T_2575)
node _T_2577 = leq(uncommonBits_70, UInt<2>(0h3))
node _T_2578 = and(_T_2576, _T_2577)
node _uncommonBits_T_71 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0)
node _T_2579 = shr(io.in.c.bits.source, 2)
node _T_2580 = eq(_T_2579, UInt<2>(0h3))
node _T_2581 = leq(UInt<1>(0h0), uncommonBits_71)
node _T_2582 = and(_T_2580, _T_2581)
node _T_2583 = leq(uncommonBits_71, UInt<2>(0h3))
node _T_2584 = and(_T_2582, _T_2583)
node _T_2585 = eq(io.in.c.bits.source, UInt<6>(0h3c))
node _T_2586 = eq(io.in.c.bits.source, UInt<6>(0h3e))
node _T_2587 = eq(io.in.c.bits.source, UInt<6>(0h38))
node _T_2588 = eq(io.in.c.bits.source, UInt<6>(0h3a))
node _T_2589 = eq(io.in.c.bits.source, UInt<6>(0h34))
node _T_2590 = eq(io.in.c.bits.source, UInt<6>(0h36))
node _T_2591 = eq(io.in.c.bits.source, UInt<6>(0h30))
node _T_2592 = eq(io.in.c.bits.source, UInt<6>(0h32))
node _T_2593 = eq(io.in.c.bits.source, UInt<6>(0h2c))
node _T_2594 = eq(io.in.c.bits.source, UInt<6>(0h2e))
node _T_2595 = eq(io.in.c.bits.source, UInt<6>(0h28))
node _T_2596 = eq(io.in.c.bits.source, UInt<6>(0h2a))
node _T_2597 = eq(io.in.c.bits.source, UInt<6>(0h24))
node _T_2598 = eq(io.in.c.bits.source, UInt<6>(0h26))
node _T_2599 = eq(io.in.c.bits.source, UInt<6>(0h20))
node _T_2600 = eq(io.in.c.bits.source, UInt<6>(0h22))
wire _WIRE_8 : UInt<1>[21]
connect _WIRE_8[0], _T_2560
connect _WIRE_8[1], _T_2566
connect _WIRE_8[2], _T_2572
connect _WIRE_8[3], _T_2578
connect _WIRE_8[4], _T_2584
connect _WIRE_8[5], _T_2585
connect _WIRE_8[6], _T_2586
connect _WIRE_8[7], _T_2587
connect _WIRE_8[8], _T_2588
connect _WIRE_8[9], _T_2589
connect _WIRE_8[10], _T_2590
connect _WIRE_8[11], _T_2591
connect _WIRE_8[12], _T_2592
connect _WIRE_8[13], _T_2593
connect _WIRE_8[14], _T_2594
connect _WIRE_8[15], _T_2595
connect _WIRE_8[16], _T_2596
connect _WIRE_8[17], _T_2597
connect _WIRE_8[18], _T_2598
connect _WIRE_8[19], _T_2599
connect _WIRE_8[20], _T_2600
node _T_2601 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2602 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2603 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2604 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2605 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2606 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2607 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2608 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2609 = mux(_WIRE_8[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_2610 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_2611 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_2612 = mux(_WIRE_8[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_2613 = mux(_WIRE_8[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_2614 = mux(_WIRE_8[5], _T_2601, UInt<1>(0h0))
node _T_2615 = mux(_WIRE_8[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_2616 = mux(_WIRE_8[7], _T_2602, UInt<1>(0h0))
node _T_2617 = mux(_WIRE_8[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_2618 = mux(_WIRE_8[9], _T_2603, UInt<1>(0h0))
node _T_2619 = mux(_WIRE_8[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_2620 = mux(_WIRE_8[11], _T_2604, UInt<1>(0h0))
node _T_2621 = mux(_WIRE_8[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_2622 = mux(_WIRE_8[13], _T_2605, UInt<1>(0h0))
node _T_2623 = mux(_WIRE_8[14], UInt<1>(0h0), UInt<1>(0h0))
node _T_2624 = mux(_WIRE_8[15], _T_2606, UInt<1>(0h0))
node _T_2625 = mux(_WIRE_8[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_2626 = mux(_WIRE_8[17], _T_2607, UInt<1>(0h0))
node _T_2627 = mux(_WIRE_8[18], UInt<1>(0h0), UInt<1>(0h0))
node _T_2628 = mux(_WIRE_8[19], _T_2608, UInt<1>(0h0))
node _T_2629 = mux(_WIRE_8[20], UInt<1>(0h0), UInt<1>(0h0))
node _T_2630 = or(_T_2609, _T_2610)
node _T_2631 = or(_T_2630, _T_2611)
node _T_2632 = or(_T_2631, _T_2612)
node _T_2633 = or(_T_2632, _T_2613)
node _T_2634 = or(_T_2633, _T_2614)
node _T_2635 = or(_T_2634, _T_2615)
node _T_2636 = or(_T_2635, _T_2616)
node _T_2637 = or(_T_2636, _T_2617)
node _T_2638 = or(_T_2637, _T_2618)
node _T_2639 = or(_T_2638, _T_2619)
node _T_2640 = or(_T_2639, _T_2620)
node _T_2641 = or(_T_2640, _T_2621)
node _T_2642 = or(_T_2641, _T_2622)
node _T_2643 = or(_T_2642, _T_2623)
node _T_2644 = or(_T_2643, _T_2624)
node _T_2645 = or(_T_2644, _T_2625)
node _T_2646 = or(_T_2645, _T_2626)
node _T_2647 = or(_T_2646, _T_2627)
node _T_2648 = or(_T_2647, _T_2628)
node _T_2649 = or(_T_2648, _T_2629)
wire _WIRE_9 : UInt<1>
connect _WIRE_9, _T_2649
node _T_2650 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2651 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2652 = and(_T_2650, _T_2651)
node _T_2653 = or(UInt<1>(0h0), _T_2652)
node _T_2654 = xor(io.in.c.bits.address, UInt<28>(0h8000080))
node _T_2655 = cvt(_T_2654)
node _T_2656 = and(_T_2655, asSInt(UInt<17>(0h100c0)))
node _T_2657 = asSInt(_T_2656)
node _T_2658 = eq(_T_2657, asSInt(UInt<1>(0h0)))
node _T_2659 = xor(io.in.c.bits.address, UInt<32>(0h80000080))
node _T_2660 = cvt(_T_2659)
node _T_2661 = and(_T_2660, asSInt(UInt<29>(0h100000c0)))
node _T_2662 = asSInt(_T_2661)
node _T_2663 = eq(_T_2662, asSInt(UInt<1>(0h0)))
node _T_2664 = or(_T_2658, _T_2663)
node _T_2665 = and(_T_2653, _T_2664)
node _T_2666 = or(UInt<1>(0h0), _T_2665)
node _T_2667 = and(_WIRE_9, _T_2666)
node _T_2668 = asUInt(reset)
node _T_2669 = eq(_T_2668, UInt<1>(0h0))
when _T_2669 :
node _T_2670 = eq(_T_2667, UInt<1>(0h0))
when _T_2670 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151
assert(clock, _T_2667, UInt<1>(0h1), "") : assert_151
node _T_2671 = asUInt(reset)
node _T_2672 = eq(_T_2671, UInt<1>(0h0))
when _T_2672 :
node _T_2673 = eq(source_ok_2, UInt<1>(0h0))
when _T_2673 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152
node _T_2674 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_2675 = asUInt(reset)
node _T_2676 = eq(_T_2675, UInt<1>(0h0))
when _T_2676 :
node _T_2677 = eq(_T_2674, UInt<1>(0h0))
when _T_2677 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153
assert(clock, _T_2674, UInt<1>(0h1), "") : assert_153
node _T_2678 = asUInt(reset)
node _T_2679 = eq(_T_2678, UInt<1>(0h0))
when _T_2679 :
node _T_2680 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2680 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154
node _T_2681 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_2682 = asUInt(reset)
node _T_2683 = eq(_T_2682, UInt<1>(0h0))
when _T_2683 :
node _T_2684 = eq(_T_2681, UInt<1>(0h0))
when _T_2684 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155
assert(clock, _T_2681, UInt<1>(0h1), "") : assert_155
node _T_2685 = eq(io.in.c.bits.opcode, UInt<1>(0h0))
when _T_2685 :
node _T_2686 = asUInt(reset)
node _T_2687 = eq(_T_2686, UInt<1>(0h0))
when _T_2687 :
node _T_2688 = eq(address_ok_1, UInt<1>(0h0))
when _T_2688 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156
node _T_2689 = asUInt(reset)
node _T_2690 = eq(_T_2689, UInt<1>(0h0))
when _T_2690 :
node _T_2691 = eq(source_ok_2, UInt<1>(0h0))
when _T_2691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157
node _T_2692 = asUInt(reset)
node _T_2693 = eq(_T_2692, UInt<1>(0h0))
when _T_2693 :
node _T_2694 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2694 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158
node _T_2695 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2696 = asUInt(reset)
node _T_2697 = eq(_T_2696, UInt<1>(0h0))
when _T_2697 :
node _T_2698 = eq(_T_2695, UInt<1>(0h0))
when _T_2698 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159
assert(clock, _T_2695, UInt<1>(0h1), "") : assert_159
node _T_2699 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2700 = asUInt(reset)
node _T_2701 = eq(_T_2700, UInt<1>(0h0))
when _T_2701 :
node _T_2702 = eq(_T_2699, UInt<1>(0h0))
when _T_2702 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160
assert(clock, _T_2699, UInt<1>(0h1), "") : assert_160
node _T_2703 = eq(io.in.c.bits.opcode, UInt<1>(0h1))
when _T_2703 :
node _T_2704 = asUInt(reset)
node _T_2705 = eq(_T_2704, UInt<1>(0h0))
when _T_2705 :
node _T_2706 = eq(address_ok_1, UInt<1>(0h0))
when _T_2706 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161
node _T_2707 = asUInt(reset)
node _T_2708 = eq(_T_2707, UInt<1>(0h0))
when _T_2708 :
node _T_2709 = eq(source_ok_2, UInt<1>(0h0))
when _T_2709 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162
node _T_2710 = asUInt(reset)
node _T_2711 = eq(_T_2710, UInt<1>(0h0))
when _T_2711 :
node _T_2712 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2712 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163
node _T_2713 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2714 = asUInt(reset)
node _T_2715 = eq(_T_2714, UInt<1>(0h0))
when _T_2715 :
node _T_2716 = eq(_T_2713, UInt<1>(0h0))
when _T_2716 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164
assert(clock, _T_2713, UInt<1>(0h1), "") : assert_164
node _T_2717 = eq(io.in.c.bits.opcode, UInt<2>(0h2))
when _T_2717 :
node _T_2718 = asUInt(reset)
node _T_2719 = eq(_T_2718, UInt<1>(0h0))
when _T_2719 :
node _T_2720 = eq(address_ok_1, UInt<1>(0h0))
when _T_2720 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165
node _T_2721 = asUInt(reset)
node _T_2722 = eq(_T_2721, UInt<1>(0h0))
when _T_2722 :
node _T_2723 = eq(source_ok_2, UInt<1>(0h0))
when _T_2723 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166
node _T_2724 = asUInt(reset)
node _T_2725 = eq(_T_2724, UInt<1>(0h0))
when _T_2725 :
node _T_2726 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2726 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167
node _T_2727 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2728 = asUInt(reset)
node _T_2729 = eq(_T_2728, UInt<1>(0h0))
when _T_2729 :
node _T_2730 = eq(_T_2727, UInt<1>(0h0))
when _T_2730 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168
assert(clock, _T_2727, UInt<1>(0h1), "") : assert_168
node _T_2731 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2732 = asUInt(reset)
node _T_2733 = eq(_T_2732, UInt<1>(0h0))
when _T_2733 :
node _T_2734 = eq(_T_2731, UInt<1>(0h0))
when _T_2734 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169
assert(clock, _T_2731, UInt<1>(0h1), "") : assert_169
when io.in.e.valid :
node sink_ok_1 = lt(io.in.e.bits.sink, UInt<3>(0h7))
node _T_2735 = asUInt(reset)
node _T_2736 = eq(_T_2735, UInt<1>(0h0))
when _T_2736 :
node _T_2737 = eq(sink_ok_1, UInt<1>(0h0))
when _T_2737 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170
assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_2738 = eq(a_first, UInt<1>(0h0))
node _T_2739 = and(io.in.a.valid, _T_2738)
when _T_2739 :
node _T_2740 = eq(io.in.a.bits.opcode, opcode)
node _T_2741 = asUInt(reset)
node _T_2742 = eq(_T_2741, UInt<1>(0h0))
when _T_2742 :
node _T_2743 = eq(_T_2740, UInt<1>(0h0))
when _T_2743 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171
assert(clock, _T_2740, UInt<1>(0h1), "") : assert_171
node _T_2744 = eq(io.in.a.bits.param, param)
node _T_2745 = asUInt(reset)
node _T_2746 = eq(_T_2745, UInt<1>(0h0))
when _T_2746 :
node _T_2747 = eq(_T_2744, UInt<1>(0h0))
when _T_2747 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172
assert(clock, _T_2744, UInt<1>(0h1), "") : assert_172
node _T_2748 = eq(io.in.a.bits.size, size)
node _T_2749 = asUInt(reset)
node _T_2750 = eq(_T_2749, UInt<1>(0h0))
when _T_2750 :
node _T_2751 = eq(_T_2748, UInt<1>(0h0))
when _T_2751 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173
assert(clock, _T_2748, UInt<1>(0h1), "") : assert_173
node _T_2752 = eq(io.in.a.bits.source, source)
node _T_2753 = asUInt(reset)
node _T_2754 = eq(_T_2753, UInt<1>(0h0))
when _T_2754 :
node _T_2755 = eq(_T_2752, UInt<1>(0h0))
when _T_2755 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174
assert(clock, _T_2752, UInt<1>(0h1), "") : assert_174
node _T_2756 = eq(io.in.a.bits.address, address)
node _T_2757 = asUInt(reset)
node _T_2758 = eq(_T_2757, UInt<1>(0h0))
when _T_2758 :
node _T_2759 = eq(_T_2756, UInt<1>(0h0))
when _T_2759 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175
assert(clock, _T_2756, UInt<1>(0h1), "") : assert_175
node _T_2760 = and(io.in.a.ready, io.in.a.valid)
node _T_2761 = and(_T_2760, a_first)
when _T_2761 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_2762 = eq(d_first, UInt<1>(0h0))
node _T_2763 = and(io.in.d.valid, _T_2762)
when _T_2763 :
node _T_2764 = eq(io.in.d.bits.opcode, opcode_1)
node _T_2765 = asUInt(reset)
node _T_2766 = eq(_T_2765, UInt<1>(0h0))
when _T_2766 :
node _T_2767 = eq(_T_2764, UInt<1>(0h0))
when _T_2767 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176
assert(clock, _T_2764, UInt<1>(0h1), "") : assert_176
node _T_2768 = eq(io.in.d.bits.param, param_1)
node _T_2769 = asUInt(reset)
node _T_2770 = eq(_T_2769, UInt<1>(0h0))
when _T_2770 :
node _T_2771 = eq(_T_2768, UInt<1>(0h0))
when _T_2771 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177
assert(clock, _T_2768, UInt<1>(0h1), "") : assert_177
node _T_2772 = eq(io.in.d.bits.size, size_1)
node _T_2773 = asUInt(reset)
node _T_2774 = eq(_T_2773, UInt<1>(0h0))
when _T_2774 :
node _T_2775 = eq(_T_2772, UInt<1>(0h0))
when _T_2775 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178
assert(clock, _T_2772, UInt<1>(0h1), "") : assert_178
node _T_2776 = eq(io.in.d.bits.source, source_1)
node _T_2777 = asUInt(reset)
node _T_2778 = eq(_T_2777, UInt<1>(0h0))
when _T_2778 :
node _T_2779 = eq(_T_2776, UInt<1>(0h0))
when _T_2779 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179
assert(clock, _T_2776, UInt<1>(0h1), "") : assert_179
node _T_2780 = eq(io.in.d.bits.sink, sink)
node _T_2781 = asUInt(reset)
node _T_2782 = eq(_T_2781, UInt<1>(0h0))
when _T_2782 :
node _T_2783 = eq(_T_2780, UInt<1>(0h0))
when _T_2783 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180
assert(clock, _T_2780, UInt<1>(0h1), "") : assert_180
node _T_2784 = eq(io.in.d.bits.denied, denied)
node _T_2785 = asUInt(reset)
node _T_2786 = eq(_T_2785, UInt<1>(0h0))
when _T_2786 :
node _T_2787 = eq(_T_2784, UInt<1>(0h0))
when _T_2787 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181
assert(clock, _T_2784, UInt<1>(0h1), "") : assert_181
node _T_2788 = and(io.in.d.ready, io.in.d.valid)
node _T_2789 = and(_T_2788, d_first)
when _T_2789 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
node _b_first_T = and(io.in.b.ready, io.in.b.valid)
node _b_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.b.bits.size)
node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 5, 0)
node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1)
node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3)
node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2)
node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0))
node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0))
regreset b_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1))
node b_first_counter1 = tail(_b_first_counter1_T, 1)
node b_first = eq(b_first_counter, UInt<1>(0h0))
node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1))
node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0))
node b_first_last = or(_b_first_last_T, _b_first_last_T_1)
node b_first_done = and(b_first_last, _b_first_T)
node _b_first_count_T = not(b_first_counter1)
node b_first_count = and(b_first_beats1, _b_first_count_T)
when _b_first_T :
node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1)
connect b_first_counter, _b_first_counter_T
reg opcode_2 : UInt, clock
reg param_2 : UInt, clock
reg size_2 : UInt, clock
reg source_2 : UInt, clock
reg address_1 : UInt, clock
node _T_2790 = eq(b_first, UInt<1>(0h0))
node _T_2791 = and(io.in.b.valid, _T_2790)
when _T_2791 :
node _T_2792 = eq(io.in.b.bits.opcode, opcode_2)
node _T_2793 = asUInt(reset)
node _T_2794 = eq(_T_2793, UInt<1>(0h0))
when _T_2794 :
node _T_2795 = eq(_T_2792, UInt<1>(0h0))
when _T_2795 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182
assert(clock, _T_2792, UInt<1>(0h1), "") : assert_182
node _T_2796 = eq(io.in.b.bits.param, param_2)
node _T_2797 = asUInt(reset)
node _T_2798 = eq(_T_2797, UInt<1>(0h0))
when _T_2798 :
node _T_2799 = eq(_T_2796, UInt<1>(0h0))
when _T_2799 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183
assert(clock, _T_2796, UInt<1>(0h1), "") : assert_183
node _T_2800 = eq(io.in.b.bits.size, size_2)
node _T_2801 = asUInt(reset)
node _T_2802 = eq(_T_2801, UInt<1>(0h0))
when _T_2802 :
node _T_2803 = eq(_T_2800, UInt<1>(0h0))
when _T_2803 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184
assert(clock, _T_2800, UInt<1>(0h1), "") : assert_184
node _T_2804 = eq(io.in.b.bits.source, source_2)
node _T_2805 = asUInt(reset)
node _T_2806 = eq(_T_2805, UInt<1>(0h0))
when _T_2806 :
node _T_2807 = eq(_T_2804, UInt<1>(0h0))
when _T_2807 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185
assert(clock, _T_2804, UInt<1>(0h1), "") : assert_185
node _T_2808 = eq(io.in.b.bits.address, address_1)
node _T_2809 = asUInt(reset)
node _T_2810 = eq(_T_2809, UInt<1>(0h0))
when _T_2810 :
node _T_2811 = eq(_T_2808, UInt<1>(0h0))
when _T_2811 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186
assert(clock, _T_2808, UInt<1>(0h1), "") : assert_186
node _T_2812 = and(io.in.b.ready, io.in.b.valid)
node _T_2813 = and(_T_2812, b_first)
when _T_2813 :
connect opcode_2, io.in.b.bits.opcode
connect param_2, io.in.b.bits.param
connect size_2, io.in.b.bits.size
connect source_2, io.in.b.bits.source
connect address_1, io.in.b.bits.address
node _c_first_T = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.c.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
reg opcode_3 : UInt, clock
reg param_3 : UInt, clock
reg size_3 : UInt, clock
reg source_3 : UInt, clock
reg address_2 : UInt, clock
node _T_2814 = eq(c_first, UInt<1>(0h0))
node _T_2815 = and(io.in.c.valid, _T_2814)
when _T_2815 :
node _T_2816 = eq(io.in.c.bits.opcode, opcode_3)
node _T_2817 = asUInt(reset)
node _T_2818 = eq(_T_2817, UInt<1>(0h0))
when _T_2818 :
node _T_2819 = eq(_T_2816, UInt<1>(0h0))
when _T_2819 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187
assert(clock, _T_2816, UInt<1>(0h1), "") : assert_187
node _T_2820 = eq(io.in.c.bits.param, param_3)
node _T_2821 = asUInt(reset)
node _T_2822 = eq(_T_2821, UInt<1>(0h0))
when _T_2822 :
node _T_2823 = eq(_T_2820, UInt<1>(0h0))
when _T_2823 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188
assert(clock, _T_2820, UInt<1>(0h1), "") : assert_188
node _T_2824 = eq(io.in.c.bits.size, size_3)
node _T_2825 = asUInt(reset)
node _T_2826 = eq(_T_2825, UInt<1>(0h0))
when _T_2826 :
node _T_2827 = eq(_T_2824, UInt<1>(0h0))
when _T_2827 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189
assert(clock, _T_2824, UInt<1>(0h1), "") : assert_189
node _T_2828 = eq(io.in.c.bits.source, source_3)
node _T_2829 = asUInt(reset)
node _T_2830 = eq(_T_2829, UInt<1>(0h0))
when _T_2830 :
node _T_2831 = eq(_T_2828, UInt<1>(0h0))
when _T_2831 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190
assert(clock, _T_2828, UInt<1>(0h1), "") : assert_190
node _T_2832 = eq(io.in.c.bits.address, address_2)
node _T_2833 = asUInt(reset)
node _T_2834 = eq(_T_2833, UInt<1>(0h0))
when _T_2834 :
node _T_2835 = eq(_T_2832, UInt<1>(0h0))
when _T_2835 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191
assert(clock, _T_2832, UInt<1>(0h1), "") : assert_191
node _T_2836 = and(io.in.c.ready, io.in.c.valid)
node _T_2837 = and(_T_2836, c_first)
when _T_2837 :
connect opcode_3, io.in.c.bits.opcode
connect param_3, io.in.c.bits.param
connect size_3, io.in.c.bits.size
connect source_3, io.in.c.bits.source
connect address_2, io.in.c.bits.address
regreset inflight : UInt<63>, clock, reset, UInt<63>(0h0)
regreset inflight_opcodes : UInt<252>, clock, reset, UInt<252>(0h0)
regreset inflight_sizes : UInt<252>, clock, reset, UInt<252>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<63>
connect a_set, UInt<63>(0h0)
wire a_set_wo_ready : UInt<63>
connect a_set_wo_ready, UInt<63>(0h0)
wire a_opcodes_set : UInt<252>
connect a_opcodes_set, UInt<252>(0h0)
wire a_sizes_set : UInt<252>
connect a_sizes_set, UInt<252>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_2838 = and(io.in.a.valid, a_first_1)
node _T_2839 = and(_T_2838, UInt<1>(0h1))
when _T_2839 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_2840 = and(io.in.a.ready, io.in.a.valid)
node _T_2841 = and(_T_2840, a_first_1)
node _T_2842 = and(_T_2841, UInt<1>(0h1))
when _T_2842 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_2843 = dshr(inflight, io.in.a.bits.source)
node _T_2844 = bits(_T_2843, 0, 0)
node _T_2845 = eq(_T_2844, UInt<1>(0h0))
node _T_2846 = asUInt(reset)
node _T_2847 = eq(_T_2846, UInt<1>(0h0))
when _T_2847 :
node _T_2848 = eq(_T_2845, UInt<1>(0h0))
when _T_2848 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192
assert(clock, _T_2845, UInt<1>(0h1), "") : assert_192
wire d_clr : UInt<63>
connect d_clr, UInt<63>(0h0)
wire d_clr_wo_ready : UInt<63>
connect d_clr_wo_ready, UInt<63>(0h0)
wire d_opcodes_clr : UInt<252>
connect d_opcodes_clr, UInt<252>(0h0)
wire d_sizes_clr : UInt<252>
connect d_sizes_clr, UInt<252>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2849 = and(io.in.d.valid, d_first_1)
node _T_2850 = and(_T_2849, UInt<1>(0h1))
node _T_2851 = eq(d_release_ack, UInt<1>(0h0))
node _T_2852 = and(_T_2850, _T_2851)
when _T_2852 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_2853 = and(io.in.d.ready, io.in.d.valid)
node _T_2854 = and(_T_2853, d_first_1)
node _T_2855 = and(_T_2854, UInt<1>(0h1))
node _T_2856 = eq(d_release_ack, UInt<1>(0h0))
node _T_2857 = and(_T_2855, _T_2856)
when _T_2857 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_2858 = and(io.in.d.valid, d_first_1)
node _T_2859 = and(_T_2858, UInt<1>(0h1))
node _T_2860 = eq(d_release_ack, UInt<1>(0h0))
node _T_2861 = and(_T_2859, _T_2860)
when _T_2861 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_2862 = dshr(inflight, io.in.d.bits.source)
node _T_2863 = bits(_T_2862, 0, 0)
node _T_2864 = or(_T_2863, same_cycle_resp)
node _T_2865 = asUInt(reset)
node _T_2866 = eq(_T_2865, UInt<1>(0h0))
when _T_2866 :
node _T_2867 = eq(_T_2864, UInt<1>(0h0))
when _T_2867 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193
assert(clock, _T_2864, UInt<1>(0h1), "") : assert_193
when same_cycle_resp :
node _T_2868 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_2869 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_2870 = or(_T_2868, _T_2869)
node _T_2871 = asUInt(reset)
node _T_2872 = eq(_T_2871, UInt<1>(0h0))
when _T_2872 :
node _T_2873 = eq(_T_2870, UInt<1>(0h0))
when _T_2873 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194
assert(clock, _T_2870, UInt<1>(0h1), "") : assert_194
node _T_2874 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_2875 = asUInt(reset)
node _T_2876 = eq(_T_2875, UInt<1>(0h0))
when _T_2876 :
node _T_2877 = eq(_T_2874, UInt<1>(0h0))
when _T_2877 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195
assert(clock, _T_2874, UInt<1>(0h1), "") : assert_195
else :
node _T_2878 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_2879 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_2880 = or(_T_2878, _T_2879)
node _T_2881 = asUInt(reset)
node _T_2882 = eq(_T_2881, UInt<1>(0h0))
when _T_2882 :
node _T_2883 = eq(_T_2880, UInt<1>(0h0))
when _T_2883 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196
assert(clock, _T_2880, UInt<1>(0h1), "") : assert_196
node _T_2884 = eq(io.in.d.bits.size, a_size_lookup)
node _T_2885 = asUInt(reset)
node _T_2886 = eq(_T_2885, UInt<1>(0h0))
when _T_2886 :
node _T_2887 = eq(_T_2884, UInt<1>(0h0))
when _T_2887 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197
assert(clock, _T_2884, UInt<1>(0h1), "") : assert_197
node _T_2888 = and(io.in.d.valid, d_first_1)
node _T_2889 = and(_T_2888, a_first_1)
node _T_2890 = and(_T_2889, io.in.a.valid)
node _T_2891 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_2892 = and(_T_2890, _T_2891)
node _T_2893 = eq(d_release_ack, UInt<1>(0h0))
node _T_2894 = and(_T_2892, _T_2893)
when _T_2894 :
node _T_2895 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2896 = or(_T_2895, io.in.a.ready)
node _T_2897 = asUInt(reset)
node _T_2898 = eq(_T_2897, UInt<1>(0h0))
when _T_2898 :
node _T_2899 = eq(_T_2896, UInt<1>(0h0))
when _T_2899 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198
assert(clock, _T_2896, UInt<1>(0h1), "") : assert_198
node _T_2900 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_2901 = orr(a_set_wo_ready)
node _T_2902 = eq(_T_2901, UInt<1>(0h0))
node _T_2903 = or(_T_2900, _T_2902)
node _T_2904 = asUInt(reset)
node _T_2905 = eq(_T_2904, UInt<1>(0h0))
when _T_2905 :
node _T_2906 = eq(_T_2903, UInt<1>(0h0))
when _T_2906 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199
assert(clock, _T_2903, UInt<1>(0h1), "") : assert_199
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_167
node _T_2907 = orr(inflight)
node _T_2908 = eq(_T_2907, UInt<1>(0h0))
node _T_2909 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_2910 = or(_T_2908, _T_2909)
node _T_2911 = lt(watchdog, plusarg_reader.out)
node _T_2912 = or(_T_2910, _T_2911)
node _T_2913 = asUInt(reset)
node _T_2914 = eq(_T_2913, UInt<1>(0h0))
when _T_2914 :
node _T_2915 = eq(_T_2912, UInt<1>(0h0))
when _T_2915 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200
assert(clock, _T_2912, UInt<1>(0h1), "") : assert_200
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_2916 = and(io.in.a.ready, io.in.a.valid)
node _T_2917 = and(io.in.d.ready, io.in.d.valid)
node _T_2918 = or(_T_2916, _T_2917)
when _T_2918 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<63>, clock, reset, UInt<63>(0h0)
regreset inflight_opcodes_1 : UInt<252>, clock, reset, UInt<252>(0h0)
regreset inflight_sizes_1 : UInt<252>, clock, reset, UInt<252>(0h0)
node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.c.bits.size)
node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 5, 0)
node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4)
node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3)
node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0))
regreset c_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1))
node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1)
node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0))
node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1))
node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0))
node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3)
node c_first_done_1 = and(c_first_last_1, _c_first_T_1)
node _c_first_count_T_1 = not(c_first_counter1_1)
node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1)
when _c_first_T_1 :
node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1)
connect c_first_counter_1, _c_first_counter_T_1
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<63>
connect c_set, UInt<63>(0h0)
wire c_set_wo_ready : UInt<63>
connect c_set_wo_ready, UInt<63>(0h0)
wire c_opcodes_set : UInt<252>
connect c_opcodes_set, UInt<252>(0h0)
wire c_sizes_set : UInt<252>
connect c_sizes_set, UInt<252>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
node _T_2919 = and(io.in.c.valid, c_first_1)
node _T_2920 = bits(io.in.c.bits.opcode, 2, 2)
node _T_2921 = bits(io.in.c.bits.opcode, 1, 1)
node _T_2922 = and(_T_2920, _T_2921)
node _T_2923 = and(_T_2919, _T_2922)
when _T_2923 :
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
node _T_2924 = and(io.in.c.ready, io.in.c.valid)
node _T_2925 = and(_T_2924, c_first_1)
node _T_2926 = bits(io.in.c.bits.opcode, 2, 2)
node _T_2927 = bits(io.in.c.bits.opcode, 1, 1)
node _T_2928 = and(_T_2926, _T_2927)
node _T_2929 = and(_T_2925, _T_2928)
when _T_2929 :
node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set, _c_set_T
node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
node _T_2930 = dshr(inflight_1, io.in.c.bits.source)
node _T_2931 = bits(_T_2930, 0, 0)
node _T_2932 = eq(_T_2931, UInt<1>(0h0))
node _T_2933 = asUInt(reset)
node _T_2934 = eq(_T_2933, UInt<1>(0h0))
when _T_2934 :
node _T_2935 = eq(_T_2932, UInt<1>(0h0))
when _T_2935 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201
assert(clock, _T_2932, UInt<1>(0h1), "") : assert_201
node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4))
node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<63>
connect d_clr_1, UInt<63>(0h0)
wire d_clr_wo_ready_1 : UInt<63>
connect d_clr_wo_ready_1, UInt<63>(0h0)
wire d_opcodes_clr_1 : UInt<252>
connect d_opcodes_clr_1, UInt<252>(0h0)
wire d_sizes_clr_1 : UInt<252>
connect d_sizes_clr_1, UInt<252>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2936 = and(io.in.d.valid, d_first_2)
node _T_2937 = and(_T_2936, UInt<1>(0h1))
node _T_2938 = and(_T_2937, d_release_ack_1)
when _T_2938 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_2939 = and(io.in.d.ready, io.in.d.valid)
node _T_2940 = and(_T_2939, d_first_2)
node _T_2941 = and(_T_2940, UInt<1>(0h1))
node _T_2942 = and(_T_2941, d_release_ack_1)
when _T_2942 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_2943 = and(io.in.d.valid, d_first_2)
node _T_2944 = and(_T_2943, UInt<1>(0h1))
node _T_2945 = and(_T_2944, d_release_ack_1)
when _T_2945 :
node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1)
node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_2946 = dshr(inflight_1, io.in.d.bits.source)
node _T_2947 = bits(_T_2946, 0, 0)
node _T_2948 = or(_T_2947, same_cycle_resp_1)
node _T_2949 = asUInt(reset)
node _T_2950 = eq(_T_2949, UInt<1>(0h0))
when _T_2950 :
node _T_2951 = eq(_T_2948, UInt<1>(0h0))
when _T_2951 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202
assert(clock, _T_2948, UInt<1>(0h1), "") : assert_202
when same_cycle_resp_1 :
node _T_2952 = eq(io.in.d.bits.size, io.in.c.bits.size)
node _T_2953 = asUInt(reset)
node _T_2954 = eq(_T_2953, UInt<1>(0h0))
when _T_2954 :
node _T_2955 = eq(_T_2952, UInt<1>(0h0))
when _T_2955 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203
assert(clock, _T_2952, UInt<1>(0h1), "") : assert_203
else :
node _T_2956 = eq(io.in.d.bits.size, c_size_lookup)
node _T_2957 = asUInt(reset)
node _T_2958 = eq(_T_2957, UInt<1>(0h0))
when _T_2958 :
node _T_2959 = eq(_T_2956, UInt<1>(0h0))
when _T_2959 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204
assert(clock, _T_2956, UInt<1>(0h1), "") : assert_204
node _T_2960 = and(io.in.d.valid, d_first_2)
node _T_2961 = and(_T_2960, c_first_1)
node _T_2962 = and(_T_2961, io.in.c.valid)
node _T_2963 = eq(io.in.c.bits.source, io.in.d.bits.source)
node _T_2964 = and(_T_2962, _T_2963)
node _T_2965 = and(_T_2964, d_release_ack_1)
node _T_2966 = eq(c_probe_ack, UInt<1>(0h0))
node _T_2967 = and(_T_2965, _T_2966)
when _T_2967 :
node _T_2968 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2969 = or(_T_2968, io.in.c.ready)
node _T_2970 = asUInt(reset)
node _T_2971 = eq(_T_2970, UInt<1>(0h0))
when _T_2971 :
node _T_2972 = eq(_T_2969, UInt<1>(0h0))
when _T_2972 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205
assert(clock, _T_2969, UInt<1>(0h1), "") : assert_205
node _T_2973 = orr(c_set_wo_ready)
when _T_2973 :
node _T_2974 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_2975 = asUInt(reset)
node _T_2976 = eq(_T_2975, UInt<1>(0h0))
when _T_2976 :
node _T_2977 = eq(_T_2974, UInt<1>(0h0))
when _T_2977 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206
assert(clock, _T_2974, UInt<1>(0h1), "") : assert_206
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_168
node _T_2978 = orr(inflight_1)
node _T_2979 = eq(_T_2978, UInt<1>(0h0))
node _T_2980 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_2981 = or(_T_2979, _T_2980)
node _T_2982 = lt(watchdog_1, plusarg_reader_1.out)
node _T_2983 = or(_T_2981, _T_2982)
node _T_2984 = asUInt(reset)
node _T_2985 = eq(_T_2984, UInt<1>(0h0))
when _T_2985 :
node _T_2986 = eq(_T_2983, UInt<1>(0h0))
when _T_2986 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207
assert(clock, _T_2983, UInt<1>(0h1), "") : assert_207
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
node _T_2987 = and(io.in.c.ready, io.in.c.valid)
node _T_2988 = and(io.in.d.ready, io.in.d.valid)
node _T_2989 = or(_T_2987, _T_2988)
when _T_2989 :
connect watchdog_1, UInt<1>(0h0)
regreset inflight_2 : UInt<7>, clock, reset, UInt<7>(0h0)
node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0)
node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10)
node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3)
node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0))
regreset d_first_counter_3 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1))
node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1)
node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0))
node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1))
node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0))
node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7)
node d_first_done_3 = and(d_first_last_3, _d_first_T_3)
node _d_first_count_T_3 = not(d_first_counter1_3)
node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3)
when _d_first_T_3 :
node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3)
connect d_first_counter_3, _d_first_counter_T_3
wire d_set : UInt<7>
connect d_set, UInt<7>(0h0)
node _T_2990 = and(io.in.d.ready, io.in.d.valid)
node _T_2991 = and(_T_2990, d_first_3)
node _T_2992 = bits(io.in.d.bits.opcode, 2, 2)
node _T_2993 = bits(io.in.d.bits.opcode, 1, 1)
node _T_2994 = eq(_T_2993, UInt<1>(0h0))
node _T_2995 = and(_T_2992, _T_2994)
node _T_2996 = and(_T_2991, _T_2995)
when _T_2996 :
node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink)
connect d_set, _d_set_T
node _T_2997 = dshr(inflight_2, io.in.d.bits.sink)
node _T_2998 = bits(_T_2997, 0, 0)
node _T_2999 = eq(_T_2998, UInt<1>(0h0))
node _T_3000 = asUInt(reset)
node _T_3001 = eq(_T_3000, UInt<1>(0h0))
when _T_3001 :
node _T_3002 = eq(_T_2999, UInt<1>(0h0))
when _T_3002 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208
assert(clock, _T_2999, UInt<1>(0h1), "") : assert_208
wire e_clr : UInt<7>
connect e_clr, UInt<7>(0h0)
node _T_3003 = and(io.in.e.ready, io.in.e.valid)
node _T_3004 = and(_T_3003, UInt<1>(0h1))
node _T_3005 = and(_T_3004, UInt<1>(0h1))
when _T_3005 :
node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink)
connect e_clr, _e_clr_T
node _T_3006 = or(d_set, inflight_2)
node _T_3007 = dshr(_T_3006, io.in.e.bits.sink)
node _T_3008 = bits(_T_3007, 0, 0)
node _T_3009 = asUInt(reset)
node _T_3010 = eq(_T_3009, UInt<1>(0h0))
when _T_3010 :
node _T_3011 = eq(_T_3008, UInt<1>(0h0))
when _T_3011 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209
assert(clock, _T_3008, UInt<1>(0h1), "") : assert_209
node _inflight_T_6 = or(inflight_2, d_set)
node _inflight_T_7 = not(e_clr)
node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7)
connect inflight_2, _inflight_T_8
extmodule plusarg_reader_169 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_170 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor_52( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_b_ready, // @[Monitor.scala:20:14]
input io_in_b_valid, // @[Monitor.scala:20:14]
input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14]
input [5:0] io_in_b_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14]
input io_in_c_ready, // @[Monitor.scala:20:14]
input io_in_c_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_c_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14]
input io_in_c_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_e_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire [12:0] _GEN_0 = {10'h0, io_in_c_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [5:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [5:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [2:0] b_first_counter; // @[Edges.scala:229:27]
reg [1:0] param_2; // @[Monitor.scala:411:22]
reg [5:0] source_2; // @[Monitor.scala:413:22]
reg [31:0] address_1; // @[Monitor.scala:414:22]
wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35]
reg [2:0] c_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_3; // @[Monitor.scala:515:22]
reg [2:0] param_3; // @[Monitor.scala:516:22]
reg [2:0] size_3; // @[Monitor.scala:517:22]
reg [5:0] source_3; // @[Monitor.scala:518:22]
reg [31:0] address_2; // @[Monitor.scala:519:22]
reg [62:0] inflight; // @[Monitor.scala:614:27]
reg [251:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [251:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire [63:0] _GEN_1 = {58'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [63:0] _GEN_4 = {58'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [62:0] inflight_1; // @[Monitor.scala:726:35]
reg [251:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] c_first_counter_1; // @[Edges.scala:229:27]
wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}]
wire [63:0] _GEN_6 = {58'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
reg [6:0] inflight_2; // @[Monitor.scala:828:27]
reg [2:0] d_first_counter_3; // @[Edges.scala:229:27]
wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35]
wire [7:0] _d_set_T = 8'h1 << io_in_d_bits_sink; // @[OneHot.scala:58:35]
wire [6:0] d_set = _GEN_8 ? _d_set_T[6:0] : 7'h0; // @[OneHot.scala:58:35] |
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_79 :
input clock : Clock
input reset : Reset
output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[5], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<3>}
regreset slot_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg slot_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock
wire next_valid : UInt<1>
connect next_valid, slot_valid
wire next_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect next_uop_out, slot_uop
node _next_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _next_uop_out_br_mask_T_1 = and(slot_uop.br_mask, _next_uop_out_br_mask_T)
connect next_uop_out.br_mask, _next_uop_out_br_mask_T_1
wire next_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect next_uop, next_uop_out
node _killed_T = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask)
node _killed_T_1 = neq(_killed_T, UInt<1>(0h0))
node killed = or(_killed_T_1, io.kill)
connect io.valid, slot_valid
connect io.out_uop, next_uop
node _io_will_be_valid_T = eq(killed, UInt<1>(0h0))
node _io_will_be_valid_T_1 = and(next_valid, _io_will_be_valid_T)
connect io.will_be_valid, _io_will_be_valid_T_1
when io.kill :
connect slot_valid, UInt<1>(0h0)
else :
when io.in_uop.valid :
connect slot_valid, UInt<1>(0h1)
else :
when io.clear :
connect slot_valid, UInt<1>(0h0)
else :
node _slot_valid_T = eq(killed, UInt<1>(0h0))
node _slot_valid_T_1 = and(next_valid, _slot_valid_T)
connect slot_valid, _slot_valid_T_1
when io.in_uop.valid :
connect slot_uop, io.in_uop.bits
node _T = eq(slot_valid, UInt<1>(0h0))
node _T_1 = or(_T, io.clear)
node _T_2 = or(_T_1, io.kill)
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:79 assert (!slot_valid || io.clear || io.kill)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
else :
connect slot_uop, next_uop
connect next_uop.iw_p1_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p2_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p3_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p1_speculative_child, UInt<1>(0h0)
connect next_uop.iw_p2_speculative_child, UInt<1>(0h0)
wire rebusied_prs1 : UInt<1>
connect rebusied_prs1, UInt<1>(0h0)
wire rebusied_prs2 : UInt<1>
connect rebusied_prs2, UInt<1>(0h0)
node rebusied = or(rebusied_prs1, rebusied_prs2)
node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs1)
node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs2)
node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs3)
node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0)
node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1)
node prs1_wakeups_2 = and(io.wakeup_ports[2].valid, prs1_matches_2)
node prs1_wakeups_3 = and(io.wakeup_ports[3].valid, prs1_matches_3)
node prs1_wakeups_4 = and(io.wakeup_ports[4].valid, prs1_matches_4)
node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0)
node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1)
node prs2_wakeups_2 = and(io.wakeup_ports[2].valid, prs2_matches_2)
node prs2_wakeups_3 = and(io.wakeup_ports[3].valid, prs2_matches_3)
node prs2_wakeups_4 = and(io.wakeup_ports[4].valid, prs2_matches_4)
node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0)
node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1)
node prs3_wakeups_2 = and(io.wakeup_ports[2].valid, prs3_matches_2)
node prs3_wakeups_3 = and(io.wakeup_ports[3].valid, prs3_matches_3)
node prs3_wakeups_4 = and(io.wakeup_ports[4].valid, prs3_matches_4)
node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0)
node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1)
node prs1_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs1_matches_2)
node prs1_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs1_matches_3)
node prs1_rebusys_4 = and(io.wakeup_ports[4].bits.rebusy, prs1_matches_4)
node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0)
node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1)
node prs2_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs2_matches_2)
node prs2_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs2_matches_3)
node prs2_rebusys_4 = and(io.wakeup_ports[4].bits.rebusy, prs2_matches_4)
node _T_6 = or(prs1_wakeups_0, prs1_wakeups_1)
node _T_7 = or(_T_6, prs1_wakeups_2)
node _T_8 = or(_T_7, prs1_wakeups_3)
node _T_9 = or(_T_8, prs1_wakeups_4)
when _T_9 :
connect next_uop.prs1_busy, UInt<1>(0h0)
node _next_uop_iw_p1_speculative_child_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_4 = mux(prs1_wakeups_4, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_5 = or(_next_uop_iw_p1_speculative_child_T, _next_uop_iw_p1_speculative_child_T_1)
node _next_uop_iw_p1_speculative_child_T_6 = or(_next_uop_iw_p1_speculative_child_T_5, _next_uop_iw_p1_speculative_child_T_2)
node _next_uop_iw_p1_speculative_child_T_7 = or(_next_uop_iw_p1_speculative_child_T_6, _next_uop_iw_p1_speculative_child_T_3)
node _next_uop_iw_p1_speculative_child_T_8 = or(_next_uop_iw_p1_speculative_child_T_7, _next_uop_iw_p1_speculative_child_T_4)
wire _next_uop_iw_p1_speculative_child_WIRE : UInt<3>
connect _next_uop_iw_p1_speculative_child_WIRE, _next_uop_iw_p1_speculative_child_T_8
connect next_uop.iw_p1_speculative_child, _next_uop_iw_p1_speculative_child_WIRE
node _next_uop_iw_p1_bypass_hint_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_4 = mux(prs1_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_5 = or(_next_uop_iw_p1_bypass_hint_T, _next_uop_iw_p1_bypass_hint_T_1)
node _next_uop_iw_p1_bypass_hint_T_6 = or(_next_uop_iw_p1_bypass_hint_T_5, _next_uop_iw_p1_bypass_hint_T_2)
node _next_uop_iw_p1_bypass_hint_T_7 = or(_next_uop_iw_p1_bypass_hint_T_6, _next_uop_iw_p1_bypass_hint_T_3)
node _next_uop_iw_p1_bypass_hint_T_8 = or(_next_uop_iw_p1_bypass_hint_T_7, _next_uop_iw_p1_bypass_hint_T_4)
wire _next_uop_iw_p1_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p1_bypass_hint_WIRE, _next_uop_iw_p1_bypass_hint_T_8
connect next_uop.iw_p1_bypass_hint, _next_uop_iw_p1_bypass_hint_WIRE
node _T_10 = or(prs1_rebusys_0, prs1_rebusys_1)
node _T_11 = or(_T_10, prs1_rebusys_2)
node _T_12 = or(_T_11, prs1_rebusys_3)
node _T_13 = or(_T_12, prs1_rebusys_4)
node _T_14 = and(io.child_rebusys, slot_uop.iw_p1_speculative_child)
node _T_15 = neq(_T_14, UInt<1>(0h0))
node _T_16 = or(_T_13, _T_15)
node _T_17 = eq(slot_uop.lrs1_rtype, UInt<2>(0h0))
node _T_18 = and(_T_16, _T_17)
when _T_18 :
connect next_uop.prs1_busy, UInt<1>(0h1)
connect rebusied_prs1, UInt<1>(0h1)
node _T_19 = or(prs2_wakeups_0, prs2_wakeups_1)
node _T_20 = or(_T_19, prs2_wakeups_2)
node _T_21 = or(_T_20, prs2_wakeups_3)
node _T_22 = or(_T_21, prs2_wakeups_4)
when _T_22 :
connect next_uop.prs2_busy, UInt<1>(0h0)
node _next_uop_iw_p2_speculative_child_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_4 = mux(prs2_wakeups_4, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_5 = or(_next_uop_iw_p2_speculative_child_T, _next_uop_iw_p2_speculative_child_T_1)
node _next_uop_iw_p2_speculative_child_T_6 = or(_next_uop_iw_p2_speculative_child_T_5, _next_uop_iw_p2_speculative_child_T_2)
node _next_uop_iw_p2_speculative_child_T_7 = or(_next_uop_iw_p2_speculative_child_T_6, _next_uop_iw_p2_speculative_child_T_3)
node _next_uop_iw_p2_speculative_child_T_8 = or(_next_uop_iw_p2_speculative_child_T_7, _next_uop_iw_p2_speculative_child_T_4)
wire _next_uop_iw_p2_speculative_child_WIRE : UInt<3>
connect _next_uop_iw_p2_speculative_child_WIRE, _next_uop_iw_p2_speculative_child_T_8
connect next_uop.iw_p2_speculative_child, _next_uop_iw_p2_speculative_child_WIRE
node _next_uop_iw_p2_bypass_hint_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_4 = mux(prs2_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_5 = or(_next_uop_iw_p2_bypass_hint_T, _next_uop_iw_p2_bypass_hint_T_1)
node _next_uop_iw_p2_bypass_hint_T_6 = or(_next_uop_iw_p2_bypass_hint_T_5, _next_uop_iw_p2_bypass_hint_T_2)
node _next_uop_iw_p2_bypass_hint_T_7 = or(_next_uop_iw_p2_bypass_hint_T_6, _next_uop_iw_p2_bypass_hint_T_3)
node _next_uop_iw_p2_bypass_hint_T_8 = or(_next_uop_iw_p2_bypass_hint_T_7, _next_uop_iw_p2_bypass_hint_T_4)
wire _next_uop_iw_p2_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p2_bypass_hint_WIRE, _next_uop_iw_p2_bypass_hint_T_8
connect next_uop.iw_p2_bypass_hint, _next_uop_iw_p2_bypass_hint_WIRE
node _T_23 = or(prs2_rebusys_0, prs2_rebusys_1)
node _T_24 = or(_T_23, prs2_rebusys_2)
node _T_25 = or(_T_24, prs2_rebusys_3)
node _T_26 = or(_T_25, prs2_rebusys_4)
node _T_27 = and(io.child_rebusys, slot_uop.iw_p2_speculative_child)
node _T_28 = neq(_T_27, UInt<1>(0h0))
node _T_29 = or(_T_26, _T_28)
node _T_30 = eq(slot_uop.lrs2_rtype, UInt<2>(0h0))
node _T_31 = and(_T_29, _T_30)
when _T_31 :
connect next_uop.prs2_busy, UInt<1>(0h1)
connect rebusied_prs2, UInt<1>(0h1)
node _T_32 = or(prs3_wakeups_0, prs3_wakeups_1)
node _T_33 = or(_T_32, prs3_wakeups_2)
node _T_34 = or(_T_33, prs3_wakeups_3)
node _T_35 = or(_T_34, prs3_wakeups_4)
when _T_35 :
connect next_uop.prs3_busy, UInt<1>(0h0)
node _next_uop_iw_p3_bypass_hint_T = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_1 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_2 = mux(prs3_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_3 = mux(prs3_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_4 = mux(prs3_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_5 = or(_next_uop_iw_p3_bypass_hint_T, _next_uop_iw_p3_bypass_hint_T_1)
node _next_uop_iw_p3_bypass_hint_T_6 = or(_next_uop_iw_p3_bypass_hint_T_5, _next_uop_iw_p3_bypass_hint_T_2)
node _next_uop_iw_p3_bypass_hint_T_7 = or(_next_uop_iw_p3_bypass_hint_T_6, _next_uop_iw_p3_bypass_hint_T_3)
node _next_uop_iw_p3_bypass_hint_T_8 = or(_next_uop_iw_p3_bypass_hint_T_7, _next_uop_iw_p3_bypass_hint_T_4)
wire _next_uop_iw_p3_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p3_bypass_hint_WIRE, _next_uop_iw_p3_bypass_hint_T_8
connect next_uop.iw_p3_bypass_hint, _next_uop_iw_p3_bypass_hint_WIRE
node _T_36 = eq(io.pred_wakeup_port.bits, slot_uop.ppred)
node _T_37 = and(io.pred_wakeup_port.valid, _T_36)
when _T_37 :
connect next_uop.ppred_busy, UInt<1>(0h0)
node _iss_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0))
node _iss_ready_T_1 = eq(slot_uop.prs2_busy, UInt<1>(0h0))
node _iss_ready_T_2 = and(_iss_ready_T, _iss_ready_T_1)
node _iss_ready_T_3 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _iss_ready_T_4 = eq(_iss_ready_T_3, UInt<1>(0h0))
node _iss_ready_T_5 = and(_iss_ready_T_2, _iss_ready_T_4)
node _iss_ready_T_6 = and(slot_uop.prs3_busy, UInt<1>(0h0))
node _iss_ready_T_7 = eq(_iss_ready_T_6, UInt<1>(0h0))
node iss_ready = and(_iss_ready_T_5, _iss_ready_T_7)
node _agen_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0))
node _agen_ready_T_1 = and(slot_uop.fu_code[1], _agen_ready_T)
node _agen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _agen_ready_T_3 = eq(_agen_ready_T_2, UInt<1>(0h0))
node _agen_ready_T_4 = and(_agen_ready_T_1, _agen_ready_T_3)
node agen_ready = and(_agen_ready_T_4, UInt<1>(0h0))
node _dgen_ready_T = eq(slot_uop.prs2_busy, UInt<1>(0h0))
node _dgen_ready_T_1 = and(slot_uop.fu_code[2], _dgen_ready_T)
node _dgen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _dgen_ready_T_3 = eq(_dgen_ready_T_2, UInt<1>(0h0))
node _dgen_ready_T_4 = and(_dgen_ready_T_1, _dgen_ready_T_3)
node dgen_ready = and(_dgen_ready_T_4, UInt<1>(0h0))
node _io_request_T = eq(slot_uop.iw_issued, UInt<1>(0h0))
node _io_request_T_1 = and(slot_valid, _io_request_T)
node _io_request_T_2 = or(iss_ready, agen_ready)
node _io_request_T_3 = or(_io_request_T_2, dgen_ready)
node _io_request_T_4 = and(_io_request_T_1, _io_request_T_3)
connect io.request, _io_request_T_4
connect io.iss_uop, slot_uop
connect next_uop.iw_issued, UInt<1>(0h0)
connect next_uop.iw_issued_partial_agen, UInt<1>(0h0)
connect next_uop.iw_issued_partial_dgen, UInt<1>(0h0)
node _T_38 = eq(io.squash_grant, UInt<1>(0h0))
node _T_39 = and(io.grant, _T_38)
when _T_39 :
connect next_uop.iw_issued, UInt<1>(0h1)
node _T_40 = and(slot_valid, slot_uop.iw_issued)
when _T_40 :
connect next_valid, rebusied | module IssueSlot_79( // @[issue-slot.scala:49:7]
input clock, // @[issue-slot.scala:49:7]
input reset, // @[issue-slot.scala:49:7]
output io_valid, // @[issue-slot.scala:52:14]
output io_will_be_valid, // @[issue-slot.scala:52:14]
output io_request, // @[issue-slot.scala:52:14]
input io_grant, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_amo, // @[issue-slot.scala:52:14]
output io_iss_uop_is_eret, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_iss_uop_taken, // @[issue-slot.scala:52:14]
output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14]
output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_iss_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14]
output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_iss_uop_is_unique, // @[issue-slot.scala:52:14]
output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_in_uop_valid, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:52:14]
input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:52:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_out_uop_iw_issued, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_out_uop_is_fence, // @[issue-slot.scala:52:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_out_uop_is_amo, // @[issue-slot.scala:52:14]
output io_out_uop_is_eret, // @[issue-slot.scala:52:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_out_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_out_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_out_uop_taken, // @[issue-slot.scala:52:14]
output io_out_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_out_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_out_uop_is_unique, // @[issue-slot.scala:52:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_out_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14]
input io_kill, // @[issue-slot.scala:52:14]
input io_clear, // @[issue-slot.scala:52:14]
input io_squash_grant, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_4_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_4_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_4_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_4_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_4_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_4_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_4_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_4_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_pred_wakeup_port_valid, // @[issue-slot.scala:52:14]
input [4:0] io_pred_wakeup_port_bits, // @[issue-slot.scala:52:14]
input [2:0] io_child_rebusys // @[issue-slot.scala:52:14]
);
wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23]
wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7]
wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_4_bits_uop_inst_0 = io_wakeup_ports_4_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_4_bits_uop_debug_inst_0 = io_wakeup_ports_4_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_rvc_0 = io_wakeup_ports_4_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_4_bits_uop_debug_pc_0 = io_wakeup_ports_4_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_0_0 = io_wakeup_ports_4_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_1_0 = io_wakeup_ports_4_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_2_0 = io_wakeup_ports_4_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_3_0 = io_wakeup_ports_4_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_0_0 = io_wakeup_ports_4_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_1_0 = io_wakeup_ports_4_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_2_0 = io_wakeup_ports_4_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_3_0 = io_wakeup_ports_4_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_4_0 = io_wakeup_ports_4_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_5_0 = io_wakeup_ports_4_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_6_0 = io_wakeup_ports_4_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_7_0 = io_wakeup_ports_4_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_8_0 = io_wakeup_ports_4_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_9_0 = io_wakeup_ports_4_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_0 = io_wakeup_ports_4_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel_0 = io_wakeup_ports_4_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_4_bits_uop_br_mask_0 = io_wakeup_ports_4_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_4_bits_uop_br_tag_0 = io_wakeup_ports_4_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_4_bits_uop_br_type_0 = io_wakeup_ports_4_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sfb_0 = io_wakeup_ports_4_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_fence_0 = io_wakeup_ports_4_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_fencei_0 = io_wakeup_ports_4_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sfence_0 = io_wakeup_ports_4_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_amo_0 = io_wakeup_ports_4_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_eret_0 = io_wakeup_ports_4_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_4_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_rocc_0 = io_wakeup_ports_4_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_mov_0 = io_wakeup_ports_4_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ftq_idx_0 = io_wakeup_ports_4_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_edge_inst_0 = io_wakeup_ports_4_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_pc_lob_0 = io_wakeup_ports_4_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_taken_0 = io_wakeup_ports_4_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_imm_rename_0 = io_wakeup_ports_4_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_imm_sel_0 = io_wakeup_ports_4_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_pimm_0 = io_wakeup_ports_4_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_4_bits_uop_imm_packed_0 = io_wakeup_ports_4_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_op1_sel_0 = io_wakeup_ports_4_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_op2_sel_0 = io_wakeup_ports_4_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_rob_idx_0 = io_wakeup_ports_4_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ldq_idx_0 = io_wakeup_ports_4_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_stq_idx_0 = io_wakeup_ports_4_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_rxq_idx_0 = io_wakeup_ports_4_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_pdst_0 = io_wakeup_ports_4_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs1_0 = io_wakeup_ports_4_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs2_0 = io_wakeup_ports_4_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs3_0 = io_wakeup_ports_4_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ppred_0 = io_wakeup_ports_4_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs1_busy_0 = io_wakeup_ports_4_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs2_busy_0 = io_wakeup_ports_4_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs3_busy_0 = io_wakeup_ports_4_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_ppred_busy_0 = io_wakeup_ports_4_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_stale_pdst_0 = io_wakeup_ports_4_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_exception_0 = io_wakeup_ports_4_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_4_bits_uop_exc_cause_0 = io_wakeup_ports_4_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_mem_cmd_0 = io_wakeup_ports_4_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_mem_size_0 = io_wakeup_ports_4_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_mem_signed_0 = io_wakeup_ports_4_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_uses_ldq_0 = io_wakeup_ports_4_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_uses_stq_0 = io_wakeup_ports_4_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_unique_0 = io_wakeup_ports_4_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_flush_on_commit_0 = io_wakeup_ports_4_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_csr_cmd_0 = io_wakeup_ports_4_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_4_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_ldst_0 = io_wakeup_ports_4_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs1_0 = io_wakeup_ports_4_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs2_0 = io_wakeup_ports_4_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs3_0 = io_wakeup_ports_4_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_dst_rtype_0 = io_wakeup_ports_4_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype_0 = io_wakeup_ports_4_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype_0 = io_wakeup_ports_4_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_frs3_en_0 = io_wakeup_ports_4_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fcn_dw_0 = io_wakeup_ports_4_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_fcn_op_0 = io_wakeup_ports_4_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_val_0 = io_wakeup_ports_4_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_fp_rm_0 = io_wakeup_ports_4_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_typ_0 = io_wakeup_ports_4_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_4_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_bp_debug_if_0 = io_wakeup_ports_4_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_4_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc_0 = io_wakeup_ports_4_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc_0 = io_wakeup_ports_4_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid; // @[issue-slot.scala:49:7]
wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits; // @[issue-slot.scala:49:7]
wire [2:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23]
wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23]
wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28]
wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_4 = 1'h0; // @[issue-slot.scala:102:91]
wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_4 = 1'h0; // @[issue-slot.scala:103:91]
wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131]
wire agen_ready = 1'h0; // @[issue-slot.scala:137:114]
wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114]
wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7]
wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73]
wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110]
wire [2:0] io_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-slot.scala:49:7]
wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34]
wire _io_request_T_4; // @[issue-slot.scala:140:51]
wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28]
wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28]
wire next_uop_is_rvc; // @[issue-slot.scala:59:28]
wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_0; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_1; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_2; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_0; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_1; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_2; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_4; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_5; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_6; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_7; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_8; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_9; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28]
wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28]
wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28]
wire next_uop_is_sfb; // @[issue-slot.scala:59:28]
wire next_uop_is_fence; // @[issue-slot.scala:59:28]
wire next_uop_is_fencei; // @[issue-slot.scala:59:28]
wire next_uop_is_sfence; // @[issue-slot.scala:59:28]
wire next_uop_is_amo; // @[issue-slot.scala:59:28]
wire next_uop_is_eret; // @[issue-slot.scala:59:28]
wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28]
wire next_uop_is_rocc; // @[issue-slot.scala:59:28]
wire next_uop_is_mov; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28]
wire next_uop_edge_inst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28]
wire next_uop_taken; // @[issue-slot.scala:59:28]
wire next_uop_imm_rename; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28]
wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28]
wire next_uop_prs1_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs2_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs3_busy; // @[issue-slot.scala:59:28]
wire next_uop_ppred_busy; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28]
wire next_uop_exception; // @[issue-slot.scala:59:28]
wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28]
wire next_uop_mem_signed; // @[issue-slot.scala:59:28]
wire next_uop_uses_ldq; // @[issue-slot.scala:59:28]
wire next_uop_uses_stq; // @[issue-slot.scala:59:28]
wire next_uop_is_unique; // @[issue-slot.scala:59:28]
wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28]
wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28]
wire next_uop_frs3_en; // @[issue-slot.scala:59:28]
wire next_uop_fcn_dw; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28]
wire next_uop_fp_val; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28]
wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_valid_0; // @[issue-slot.scala:49:7]
wire io_will_be_valid_0; // @[issue-slot.scala:49:7]
wire io_request_0; // @[issue-slot.scala:49:7]
reg slot_valid; // @[issue-slot.scala:55:27]
assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23]
reg slot_uop_is_rvc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21]
wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23]
reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23]
reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23]
reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23]
reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23]
reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23]
reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23]
reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23]
reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23]
reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23]
reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23]
reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23]
reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23]
reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23]
reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23]
reg slot_uop_iw_issued; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23]
reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23]
reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23]
reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23]
reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23]
reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23]
reg slot_uop_is_sfb; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23]
reg slot_uop_is_fence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23]
reg slot_uop_is_fencei; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23]
reg slot_uop_is_sfence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23]
reg slot_uop_is_amo; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23]
reg slot_uop_is_eret; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23]
reg slot_uop_is_rocc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23]
reg slot_uop_is_mov; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23]
reg slot_uop_edge_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21]
assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23]
reg slot_uop_taken; // @[issue-slot.scala:56:21]
assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23]
reg slot_uop_imm_rename; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23]
reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23]
reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21]
assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21]
wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23]
reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23]
reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23]
reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23]
reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23]
reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23]
reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23]
wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88]
wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95]
wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23]
reg slot_uop_exception; // @[issue-slot.scala:56:21]
assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21]
assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21]
wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23]
reg slot_uop_mem_signed; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23]
reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23]
reg slot_uop_uses_stq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23]
reg slot_uop_is_unique; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21]
assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23]
reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23]
reg slot_uop_frs3_en; // @[issue-slot.scala:56:21]
assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23]
reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23]
reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23]
reg slot_uop_fp_val; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23]
reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23]
wire next_valid; // @[issue-slot.scala:58:28]
assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23]
assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23]
assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23]
assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23]
assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23]
assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23]
assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23]
assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23]
assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23]
assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23]
assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23]
assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23]
assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23]
assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23]
assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23]
assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23]
assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23]
assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23]
wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25]
assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23]
assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23]
assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23]
assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23]
assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23]
assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23]
assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23]
assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23]
assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23]
assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23]
assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23]
assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23]
assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23]
assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23]
assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23]
assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23]
assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23]
assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23]
assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23]
assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23]
assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23]
assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23]
assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23]
assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23]
assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23]
assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23]
assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23]
assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23]
assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23]
assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23]
assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23]
assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23]
assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23]
assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23]
assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23]
assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23]
assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23]
assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23]
assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23]
assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23]
assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23]
assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23]
assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23]
assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23]
assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23]
assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23]
assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23]
assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23]
assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23]
assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23]
assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23]
assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23]
assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23]
assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23]
assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23]
assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23]
assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23]
assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23]
assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23]
assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23]
assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23]
assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23]
assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23]
assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23]
assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23]
assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23]
assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23]
wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27]
assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}]
assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28]
wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51]
wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}]
wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59]
wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61]
assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}]
assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34]
wire _slot_valid_T = ~killed; // @[util.scala:61:61]
wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}] |
Generate the Verilog code corresponding to this FIRRTL code module ClockGroupResetSynchronizer :
output auto : { flip in : { member : { allClocks_mbus_0 : { clock : Clock, reset : Reset}, allClocks_tileClockGroup_rockettile_0 : { clock : Clock, reset : Reset}, allClocks_periphery : { clock : Clock, reset : Reset}, allClocks_uncore : { clock : Clock, reset : Reset}}}, out : { member : { allClocks_mbus_0 : { clock : Clock, reset : Reset}, allClocks_tileClockGroup_rockettile_0 : { clock : Clock, reset : Reset}, allClocks_periphery : { clock : Clock, reset : Reset}, allClocks_uncore : { clock : Clock, reset : Reset}}}}
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
wire nodeIn : { member : { allClocks_mbus_0 : { clock : Clock, reset : Reset}, allClocks_tileClockGroup_rockettile_0 : { clock : Clock, reset : Reset}, allClocks_periphery : { clock : Clock, reset : Reset}, allClocks_uncore : { clock : Clock, reset : Reset}}}
invalidate nodeIn.member.allClocks_uncore.reset
invalidate nodeIn.member.allClocks_uncore.clock
invalidate nodeIn.member.allClocks_periphery.reset
invalidate nodeIn.member.allClocks_periphery.clock
invalidate nodeIn.member.allClocks_tileClockGroup_rockettile_0.reset
invalidate nodeIn.member.allClocks_tileClockGroup_rockettile_0.clock
invalidate nodeIn.member.allClocks_mbus_0.reset
invalidate nodeIn.member.allClocks_mbus_0.clock
wire nodeOut : { member : { allClocks_mbus_0 : { clock : Clock, reset : Reset}, allClocks_tileClockGroup_rockettile_0 : { clock : Clock, reset : Reset}, allClocks_periphery : { clock : Clock, reset : Reset}, allClocks_uncore : { clock : Clock, reset : Reset}}}
invalidate nodeOut.member.allClocks_uncore.reset
invalidate nodeOut.member.allClocks_uncore.clock
invalidate nodeOut.member.allClocks_periphery.reset
invalidate nodeOut.member.allClocks_periphery.clock
invalidate nodeOut.member.allClocks_tileClockGroup_rockettile_0.reset
invalidate nodeOut.member.allClocks_tileClockGroup_rockettile_0.clock
invalidate nodeOut.member.allClocks_mbus_0.reset
invalidate nodeOut.member.allClocks_mbus_0.clock
connect auto.out, nodeOut
connect nodeIn, auto.in
connect nodeOut.member.allClocks_uncore.clock, nodeIn.member.allClocks_uncore.clock
node _nodeOut_member_allClocks_uncore_reset_T = asUInt(nodeIn.member.allClocks_uncore.reset)
inst nodeOut_member_allClocks_uncore_reset_catcher of ResetCatchAndSync_d3_2
connect nodeOut_member_allClocks_uncore_reset_catcher.clock, nodeIn.member.allClocks_uncore.clock
connect nodeOut_member_allClocks_uncore_reset_catcher.reset, _nodeOut_member_allClocks_uncore_reset_T
wire _nodeOut_member_allClocks_uncore_reset_catcher_io_psd_WIRE : { test_mode : UInt<1>, test_mode_reset : UInt<1>}
connect _nodeOut_member_allClocks_uncore_reset_catcher_io_psd_WIRE.test_mode_reset, UInt<1>(0h0)
connect _nodeOut_member_allClocks_uncore_reset_catcher_io_psd_WIRE.test_mode, UInt<1>(0h0)
wire _nodeOut_member_allClocks_uncore_reset_catcher_io_psd_WIRE_1 : { test_mode : UInt<1>, test_mode_reset : UInt<1>}
connect _nodeOut_member_allClocks_uncore_reset_catcher_io_psd_WIRE_1, _nodeOut_member_allClocks_uncore_reset_catcher_io_psd_WIRE
connect nodeOut_member_allClocks_uncore_reset_catcher.io.psd, _nodeOut_member_allClocks_uncore_reset_catcher_io_psd_WIRE_1
connect nodeOut.member.allClocks_uncore.reset, nodeOut_member_allClocks_uncore_reset_catcher.io.sync_reset
connect nodeOut.member.allClocks_periphery.clock, nodeIn.member.allClocks_periphery.clock
node _nodeOut_member_allClocks_periphery_reset_T = asUInt(nodeIn.member.allClocks_periphery.reset)
inst nodeOut_member_allClocks_periphery_reset_catcher of ResetCatchAndSync_d3_3
connect nodeOut_member_allClocks_periphery_reset_catcher.clock, nodeIn.member.allClocks_periphery.clock
connect nodeOut_member_allClocks_periphery_reset_catcher.reset, _nodeOut_member_allClocks_periphery_reset_T
wire _nodeOut_member_allClocks_periphery_reset_catcher_io_psd_WIRE : { test_mode : UInt<1>, test_mode_reset : UInt<1>}
connect _nodeOut_member_allClocks_periphery_reset_catcher_io_psd_WIRE.test_mode_reset, UInt<1>(0h0)
connect _nodeOut_member_allClocks_periphery_reset_catcher_io_psd_WIRE.test_mode, UInt<1>(0h0)
wire _nodeOut_member_allClocks_periphery_reset_catcher_io_psd_WIRE_1 : { test_mode : UInt<1>, test_mode_reset : UInt<1>}
connect _nodeOut_member_allClocks_periphery_reset_catcher_io_psd_WIRE_1, _nodeOut_member_allClocks_periphery_reset_catcher_io_psd_WIRE
connect nodeOut_member_allClocks_periphery_reset_catcher.io.psd, _nodeOut_member_allClocks_periphery_reset_catcher_io_psd_WIRE_1
connect nodeOut.member.allClocks_periphery.reset, nodeOut_member_allClocks_periphery_reset_catcher.io.sync_reset
connect nodeOut.member.allClocks_tileClockGroup_rockettile_0.clock, nodeIn.member.allClocks_tileClockGroup_rockettile_0.clock
node _nodeOut_member_allClocks_tileClockGroup_rockettile_0_reset_T = asUInt(nodeIn.member.allClocks_tileClockGroup_rockettile_0.reset)
inst nodeOut_member_allClocks_tileClockGroup_rockettile_0_reset_catcher of ResetCatchAndSync_d3_4
connect nodeOut_member_allClocks_tileClockGroup_rockettile_0_reset_catcher.clock, nodeIn.member.allClocks_tileClockGroup_rockettile_0.clock
connect nodeOut_member_allClocks_tileClockGroup_rockettile_0_reset_catcher.reset, _nodeOut_member_allClocks_tileClockGroup_rockettile_0_reset_T
wire _nodeOut_member_allClocks_tileClockGroup_rockettile_0_reset_catcher_io_psd_WIRE : { test_mode : UInt<1>, test_mode_reset : UInt<1>}
connect _nodeOut_member_allClocks_tileClockGroup_rockettile_0_reset_catcher_io_psd_WIRE.test_mode_reset, UInt<1>(0h0)
connect _nodeOut_member_allClocks_tileClockGroup_rockettile_0_reset_catcher_io_psd_WIRE.test_mode, UInt<1>(0h0)
wire _nodeOut_member_allClocks_tileClockGroup_rockettile_0_reset_catcher_io_psd_WIRE_1 : { test_mode : UInt<1>, test_mode_reset : UInt<1>}
connect _nodeOut_member_allClocks_tileClockGroup_rockettile_0_reset_catcher_io_psd_WIRE_1, _nodeOut_member_allClocks_tileClockGroup_rockettile_0_reset_catcher_io_psd_WIRE
connect nodeOut_member_allClocks_tileClockGroup_rockettile_0_reset_catcher.io.psd, _nodeOut_member_allClocks_tileClockGroup_rockettile_0_reset_catcher_io_psd_WIRE_1
connect nodeOut.member.allClocks_tileClockGroup_rockettile_0.reset, nodeOut_member_allClocks_tileClockGroup_rockettile_0_reset_catcher.io.sync_reset
connect nodeOut.member.allClocks_mbus_0.clock, nodeIn.member.allClocks_mbus_0.clock
node _nodeOut_member_allClocks_mbus_0_reset_T = asUInt(nodeIn.member.allClocks_mbus_0.reset)
inst nodeOut_member_allClocks_mbus_0_reset_catcher of ResetCatchAndSync_d3_5
connect nodeOut_member_allClocks_mbus_0_reset_catcher.clock, nodeIn.member.allClocks_mbus_0.clock
connect nodeOut_member_allClocks_mbus_0_reset_catcher.reset, _nodeOut_member_allClocks_mbus_0_reset_T
wire _nodeOut_member_allClocks_mbus_0_reset_catcher_io_psd_WIRE : { test_mode : UInt<1>, test_mode_reset : UInt<1>}
connect _nodeOut_member_allClocks_mbus_0_reset_catcher_io_psd_WIRE.test_mode_reset, UInt<1>(0h0)
connect _nodeOut_member_allClocks_mbus_0_reset_catcher_io_psd_WIRE.test_mode, UInt<1>(0h0)
wire _nodeOut_member_allClocks_mbus_0_reset_catcher_io_psd_WIRE_1 : { test_mode : UInt<1>, test_mode_reset : UInt<1>}
connect _nodeOut_member_allClocks_mbus_0_reset_catcher_io_psd_WIRE_1, _nodeOut_member_allClocks_mbus_0_reset_catcher_io_psd_WIRE
connect nodeOut_member_allClocks_mbus_0_reset_catcher.io.psd, _nodeOut_member_allClocks_mbus_0_reset_catcher_io_psd_WIRE_1
connect nodeOut.member.allClocks_mbus_0.reset, nodeOut_member_allClocks_mbus_0_reset_catcher.io.sync_reset
extmodule plusarg_reader_117 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_118 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module ClockGroupResetSynchronizer( // @[ResetSynchronizer.scala:35:9]
input auto_in_member_allClocks_mbus_0_clock, // @[LazyModuleImp.scala:107:25]
input auto_in_member_allClocks_mbus_0_reset, // @[LazyModuleImp.scala:107:25]
input auto_in_member_allClocks_tileClockGroup_rockettile_0_clock, // @[LazyModuleImp.scala:107:25]
input auto_in_member_allClocks_tileClockGroup_rockettile_0_reset, // @[LazyModuleImp.scala:107:25]
input auto_in_member_allClocks_periphery_clock, // @[LazyModuleImp.scala:107:25]
input auto_in_member_allClocks_periphery_reset, // @[LazyModuleImp.scala:107:25]
input auto_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25]
input auto_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25]
output auto_out_member_allClocks_mbus_0_clock, // @[LazyModuleImp.scala:107:25]
output auto_out_member_allClocks_mbus_0_reset, // @[LazyModuleImp.scala:107:25]
output auto_out_member_allClocks_tileClockGroup_rockettile_0_clock, // @[LazyModuleImp.scala:107:25]
output auto_out_member_allClocks_tileClockGroup_rockettile_0_reset, // @[LazyModuleImp.scala:107:25]
output auto_out_member_allClocks_periphery_clock, // @[LazyModuleImp.scala:107:25]
output auto_out_member_allClocks_periphery_reset, // @[LazyModuleImp.scala:107:25]
output auto_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25]
output auto_out_member_allClocks_uncore_reset // @[LazyModuleImp.scala:107:25]
);
wire auto_in_member_allClocks_mbus_0_clock_0 = auto_in_member_allClocks_mbus_0_clock; // @[ResetSynchronizer.scala:35:9]
wire auto_in_member_allClocks_mbus_0_reset_0 = auto_in_member_allClocks_mbus_0_reset; // @[ResetSynchronizer.scala:35:9]
wire auto_in_member_allClocks_tileClockGroup_rockettile_0_clock_0 = auto_in_member_allClocks_tileClockGroup_rockettile_0_clock; // @[ResetSynchronizer.scala:35:9]
wire auto_in_member_allClocks_tileClockGroup_rockettile_0_reset_0 = auto_in_member_allClocks_tileClockGroup_rockettile_0_reset; // @[ResetSynchronizer.scala:35:9]
wire auto_in_member_allClocks_periphery_clock_0 = auto_in_member_allClocks_periphery_clock; // @[ResetSynchronizer.scala:35:9]
wire auto_in_member_allClocks_periphery_reset_0 = auto_in_member_allClocks_periphery_reset; // @[ResetSynchronizer.scala:35:9]
wire auto_in_member_allClocks_uncore_clock_0 = auto_in_member_allClocks_uncore_clock; // @[ResetSynchronizer.scala:35:9]
wire auto_in_member_allClocks_uncore_reset_0 = auto_in_member_allClocks_uncore_reset; // @[ResetSynchronizer.scala:35:9]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire _nodeOut_member_allClocks_uncore_reset_catcher_io_psd_WIRE_test_mode = 1'h0; // @[ResetCatchAndSync.scala:41:63]
wire _nodeOut_member_allClocks_uncore_reset_catcher_io_psd_WIRE_test_mode_reset = 1'h0; // @[ResetCatchAndSync.scala:41:63]
wire _nodeOut_member_allClocks_uncore_reset_catcher_io_psd_WIRE_1_test_mode = 1'h0; // @[ResetCatchAndSync.scala:41:50]
wire _nodeOut_member_allClocks_uncore_reset_catcher_io_psd_WIRE_1_test_mode_reset = 1'h0; // @[ResetCatchAndSync.scala:41:50]
wire _nodeOut_member_allClocks_periphery_reset_catcher_io_psd_WIRE_test_mode = 1'h0; // @[ResetCatchAndSync.scala:41:63]
wire _nodeOut_member_allClocks_periphery_reset_catcher_io_psd_WIRE_test_mode_reset = 1'h0; // @[ResetCatchAndSync.scala:41:63]
wire _nodeOut_member_allClocks_periphery_reset_catcher_io_psd_WIRE_1_test_mode = 1'h0; // @[ResetCatchAndSync.scala:41:50]
wire _nodeOut_member_allClocks_periphery_reset_catcher_io_psd_WIRE_1_test_mode_reset = 1'h0; // @[ResetCatchAndSync.scala:41:50]
wire _nodeOut_member_allClocks_tileClockGroup_rockettile_0_reset_catcher_io_psd_WIRE_test_mode = 1'h0; // @[ResetCatchAndSync.scala:41:63]
wire _nodeOut_member_allClocks_tileClockGroup_rockettile_0_reset_catcher_io_psd_WIRE_test_mode_reset = 1'h0; // @[ResetCatchAndSync.scala:41:63]
wire _nodeOut_member_allClocks_tileClockGroup_rockettile_0_reset_catcher_io_psd_WIRE_1_test_mode = 1'h0; // @[ResetCatchAndSync.scala:41:50]
wire _nodeOut_member_allClocks_tileClockGroup_rockettile_0_reset_catcher_io_psd_WIRE_1_test_mode_reset = 1'h0; // @[ResetCatchAndSync.scala:41:50]
wire _nodeOut_member_allClocks_mbus_0_reset_catcher_io_psd_WIRE_test_mode = 1'h0; // @[ResetCatchAndSync.scala:41:63]
wire _nodeOut_member_allClocks_mbus_0_reset_catcher_io_psd_WIRE_test_mode_reset = 1'h0; // @[ResetCatchAndSync.scala:41:63]
wire _nodeOut_member_allClocks_mbus_0_reset_catcher_io_psd_WIRE_1_test_mode = 1'h0; // @[ResetCatchAndSync.scala:41:50]
wire _nodeOut_member_allClocks_mbus_0_reset_catcher_io_psd_WIRE_1_test_mode_reset = 1'h0; // @[ResetCatchAndSync.scala:41:50]
wire nodeIn_member_allClocks_mbus_0_clock = auto_in_member_allClocks_mbus_0_clock_0; // @[ResetSynchronizer.scala:35:9]
wire nodeIn_member_allClocks_mbus_0_reset = auto_in_member_allClocks_mbus_0_reset_0; // @[ResetSynchronizer.scala:35:9]
wire nodeIn_member_allClocks_tileClockGroup_rockettile_0_clock = auto_in_member_allClocks_tileClockGroup_rockettile_0_clock_0; // @[ResetSynchronizer.scala:35:9]
wire nodeIn_member_allClocks_tileClockGroup_rockettile_0_reset = auto_in_member_allClocks_tileClockGroup_rockettile_0_reset_0; // @[ResetSynchronizer.scala:35:9]
wire nodeIn_member_allClocks_periphery_clock = auto_in_member_allClocks_periphery_clock_0; // @[ResetSynchronizer.scala:35:9]
wire nodeIn_member_allClocks_periphery_reset = auto_in_member_allClocks_periphery_reset_0; // @[ResetSynchronizer.scala:35:9]
wire nodeIn_member_allClocks_uncore_clock = auto_in_member_allClocks_uncore_clock_0; // @[ResetSynchronizer.scala:35:9]
wire nodeIn_member_allClocks_uncore_reset = auto_in_member_allClocks_uncore_reset_0; // @[ResetSynchronizer.scala:35:9]
wire nodeOut_member_allClocks_mbus_0_clock; // @[MixedNode.scala:542:17]
wire nodeOut_member_allClocks_mbus_0_reset; // @[MixedNode.scala:542:17]
wire nodeOut_member_allClocks_tileClockGroup_rockettile_0_clock; // @[MixedNode.scala:542:17]
wire nodeOut_member_allClocks_tileClockGroup_rockettile_0_reset; // @[MixedNode.scala:542:17]
wire nodeOut_member_allClocks_periphery_clock; // @[MixedNode.scala:542:17]
wire nodeOut_member_allClocks_periphery_reset; // @[MixedNode.scala:542:17]
wire nodeOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17]
wire nodeOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17]
wire auto_out_member_allClocks_mbus_0_clock_0; // @[ResetSynchronizer.scala:35:9]
wire auto_out_member_allClocks_mbus_0_reset_0; // @[ResetSynchronizer.scala:35:9]
wire auto_out_member_allClocks_tileClockGroup_rockettile_0_clock_0; // @[ResetSynchronizer.scala:35:9]
wire auto_out_member_allClocks_tileClockGroup_rockettile_0_reset_0; // @[ResetSynchronizer.scala:35:9]
wire auto_out_member_allClocks_periphery_clock_0; // @[ResetSynchronizer.scala:35:9]
wire auto_out_member_allClocks_periphery_reset_0; // @[ResetSynchronizer.scala:35:9]
wire auto_out_member_allClocks_uncore_clock_0; // @[ResetSynchronizer.scala:35:9]
wire auto_out_member_allClocks_uncore_reset_0; // @[ResetSynchronizer.scala:35:9]
assign nodeOut_member_allClocks_mbus_0_clock = nodeIn_member_allClocks_mbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
wire _nodeOut_member_allClocks_mbus_0_reset_T = nodeIn_member_allClocks_mbus_0_reset; // @[ResetSynchronizer.scala:39:55]
assign nodeOut_member_allClocks_tileClockGroup_rockettile_0_clock = nodeIn_member_allClocks_tileClockGroup_rockettile_0_clock; // @[MixedNode.scala:542:17, :551:17]
wire _nodeOut_member_allClocks_tileClockGroup_rockettile_0_reset_T = nodeIn_member_allClocks_tileClockGroup_rockettile_0_reset; // @[ResetSynchronizer.scala:39:55]
assign nodeOut_member_allClocks_periphery_clock = nodeIn_member_allClocks_periphery_clock; // @[MixedNode.scala:542:17, :551:17]
wire _nodeOut_member_allClocks_periphery_reset_T = nodeIn_member_allClocks_periphery_reset; // @[ResetSynchronizer.scala:39:55]
assign nodeOut_member_allClocks_uncore_clock = nodeIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17]
wire _nodeOut_member_allClocks_uncore_reset_T = nodeIn_member_allClocks_uncore_reset; // @[ResetSynchronizer.scala:39:55]
assign auto_out_member_allClocks_mbus_0_clock_0 = nodeOut_member_allClocks_mbus_0_clock; // @[ResetSynchronizer.scala:35:9]
assign auto_out_member_allClocks_mbus_0_reset_0 = nodeOut_member_allClocks_mbus_0_reset; // @[ResetSynchronizer.scala:35:9]
assign auto_out_member_allClocks_tileClockGroup_rockettile_0_clock_0 = nodeOut_member_allClocks_tileClockGroup_rockettile_0_clock; // @[ResetSynchronizer.scala:35:9]
assign auto_out_member_allClocks_tileClockGroup_rockettile_0_reset_0 = nodeOut_member_allClocks_tileClockGroup_rockettile_0_reset; // @[ResetSynchronizer.scala:35:9]
assign auto_out_member_allClocks_periphery_clock_0 = nodeOut_member_allClocks_periphery_clock; // @[ResetSynchronizer.scala:35:9]
assign auto_out_member_allClocks_periphery_reset_0 = nodeOut_member_allClocks_periphery_reset; // @[ResetSynchronizer.scala:35:9]
assign auto_out_member_allClocks_uncore_clock_0 = nodeOut_member_allClocks_uncore_clock; // @[ResetSynchronizer.scala:35:9]
assign auto_out_member_allClocks_uncore_reset_0 = nodeOut_member_allClocks_uncore_reset; // @[ResetSynchronizer.scala:35:9]
ResetCatchAndSync_d3_2 nodeOut_member_allClocks_uncore_reset_catcher ( // @[ResetCatchAndSync.scala:39:28]
.clock (nodeIn_member_allClocks_uncore_clock), // @[MixedNode.scala:551:17]
.reset (_nodeOut_member_allClocks_uncore_reset_T), // @[ResetSynchronizer.scala:39:55]
.io_sync_reset (nodeOut_member_allClocks_uncore_reset)
); // @[ResetCatchAndSync.scala:39:28]
ResetCatchAndSync_d3_3 nodeOut_member_allClocks_periphery_reset_catcher ( // @[ResetCatchAndSync.scala:39:28]
.clock (nodeIn_member_allClocks_periphery_clock), // @[MixedNode.scala:551:17]
.reset (_nodeOut_member_allClocks_periphery_reset_T), // @[ResetSynchronizer.scala:39:55]
.io_sync_reset (nodeOut_member_allClocks_periphery_reset)
); // @[ResetCatchAndSync.scala:39:28]
ResetCatchAndSync_d3_4 nodeOut_member_allClocks_tileClockGroup_rockettile_0_reset_catcher ( // @[ResetCatchAndSync.scala:39:28]
.clock (nodeIn_member_allClocks_tileClockGroup_rockettile_0_clock), // @[MixedNode.scala:551:17]
.reset (_nodeOut_member_allClocks_tileClockGroup_rockettile_0_reset_T), // @[ResetSynchronizer.scala:39:55]
.io_sync_reset (nodeOut_member_allClocks_tileClockGroup_rockettile_0_reset)
); // @[ResetCatchAndSync.scala:39:28]
ResetCatchAndSync_d3_5 nodeOut_member_allClocks_mbus_0_reset_catcher ( // @[ResetCatchAndSync.scala:39:28]
.clock (nodeIn_member_allClocks_mbus_0_clock), // @[MixedNode.scala:551:17]
.reset (_nodeOut_member_allClocks_mbus_0_reset_T), // @[ResetSynchronizer.scala:39:55]
.io_sync_reset (nodeOut_member_allClocks_mbus_0_reset)
); // @[ResetCatchAndSync.scala:39:28]
assign auto_out_member_allClocks_mbus_0_clock = auto_out_member_allClocks_mbus_0_clock_0; // @[ResetSynchronizer.scala:35:9]
assign auto_out_member_allClocks_mbus_0_reset = auto_out_member_allClocks_mbus_0_reset_0; // @[ResetSynchronizer.scala:35:9]
assign auto_out_member_allClocks_tileClockGroup_rockettile_0_clock = auto_out_member_allClocks_tileClockGroup_rockettile_0_clock_0; // @[ResetSynchronizer.scala:35:9]
assign auto_out_member_allClocks_tileClockGroup_rockettile_0_reset = auto_out_member_allClocks_tileClockGroup_rockettile_0_reset_0; // @[ResetSynchronizer.scala:35:9]
assign auto_out_member_allClocks_periphery_clock = auto_out_member_allClocks_periphery_clock_0; // @[ResetSynchronizer.scala:35:9]
assign auto_out_member_allClocks_periphery_reset = auto_out_member_allClocks_periphery_reset_0; // @[ResetSynchronizer.scala:35:9]
assign auto_out_member_allClocks_uncore_clock = auto_out_member_allClocks_uncore_clock_0; // @[ResetSynchronizer.scala:35:9]
assign auto_out_member_allClocks_uncore_reset = auto_out_member_allClocks_uncore_reset_0; // @[ResetSynchronizer.scala:35:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module SerialRAM :
input clock : Clock
input reset : Reset
output auto : { }
output io : { ser : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}}, tsi : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<32>}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<32>}}, tsi2tl_state : UInt}
inst serdesser of TLSerdesser_SerialRAM
connect serdesser.clock, clock
connect serdesser.reset, reset
inst tsi2tl of TSIToTileLink
connect tsi2tl.clock, clock
connect tsi2tl.reset, reset
inst buffer of TLBuffer_a32d64s1k5z4u
connect buffer.clock, clock
connect buffer.reset, reset
connect buffer.auto.in, tsi2tl.auto.out
connect serdesser.auto.manager_in, buffer.auto.out
inst phy of DecoupledSerialPhy_1
connect phy.io.outer_clock, clock
connect phy.io.outer_reset, reset
connect phy.io.inner_clock, clock
connect phy.io.inner_reset, reset
connect io.ser.out.bits, phy.io.outer_ser.out.bits
connect io.ser.out.valid, phy.io.outer_ser.out.valid
connect phy.io.outer_ser.out.ready, io.ser.out.ready
connect phy.io.outer_ser.in, io.ser.in
connect phy.io.inner_ser[0], serdesser.io.ser[0]
connect phy.io.inner_ser[1], serdesser.io.ser[1]
connect phy.io.inner_ser[2], serdesser.io.ser[2]
connect phy.io.inner_ser[3], serdesser.io.ser[3]
connect phy.io.inner_ser[4], serdesser.io.ser[4]
connect io.tsi.out.bits, tsi2tl.io.tsi.out.bits
connect io.tsi.out.valid, tsi2tl.io.tsi.out.valid
connect tsi2tl.io.tsi.out.ready, io.tsi.out.ready
connect tsi2tl.io.tsi.in, io.tsi.in
connect io.tsi2tl_state, tsi2tl.io.state
extmodule SimTSI :
input clock : Clock
input reset : UInt<1>
input tsi : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<32>}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<32>}}
output exit : UInt<32>
defname = SimTSI
parameter CHIPID = 0 | module SerialRAM( // @[TSIHarness.scala:122:9]
input clock, // @[TSIHarness.scala:122:9]
input reset, // @[TSIHarness.scala:122:9]
output io_ser_in_ready, // @[TSIHarness.scala:123:16]
input io_ser_in_valid, // @[TSIHarness.scala:123:16]
input [31:0] io_ser_in_bits_phit, // @[TSIHarness.scala:123:16]
input io_ser_out_ready, // @[TSIHarness.scala:123:16]
output io_ser_out_valid, // @[TSIHarness.scala:123:16]
output [31:0] io_ser_out_bits_phit, // @[TSIHarness.scala:123:16]
output io_tsi_in_ready, // @[TSIHarness.scala:123:16]
input io_tsi_in_valid, // @[TSIHarness.scala:123:16]
input [31:0] io_tsi_in_bits, // @[TSIHarness.scala:123:16]
input io_tsi_out_ready, // @[TSIHarness.scala:123:16]
output io_tsi_out_valid, // @[TSIHarness.scala:123:16]
output [31:0] io_tsi_out_bits // @[TSIHarness.scala:123:16]
);
wire _phy_io_inner_ser_0_in_valid; // @[TSIHarness.scala:129:21]
wire [31:0] _phy_io_inner_ser_0_in_bits_flit; // @[TSIHarness.scala:129:21]
wire _phy_io_inner_ser_1_in_valid; // @[TSIHarness.scala:129:21]
wire [31:0] _phy_io_inner_ser_1_in_bits_flit; // @[TSIHarness.scala:129:21]
wire _phy_io_inner_ser_2_in_valid; // @[TSIHarness.scala:129:21]
wire [31:0] _phy_io_inner_ser_2_in_bits_flit; // @[TSIHarness.scala:129:21]
wire _phy_io_inner_ser_2_out_ready; // @[TSIHarness.scala:129:21]
wire _phy_io_inner_ser_3_in_valid; // @[TSIHarness.scala:129:21]
wire [31:0] _phy_io_inner_ser_3_in_bits_flit; // @[TSIHarness.scala:129:21]
wire _phy_io_inner_ser_4_in_valid; // @[TSIHarness.scala:129:21]
wire [31:0] _phy_io_inner_ser_4_in_bits_flit; // @[TSIHarness.scala:129:21]
wire _phy_io_inner_ser_4_out_ready; // @[TSIHarness.scala:129:21]
wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28]
wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28]
wire [63:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28]
wire _buffer_auto_out_a_valid; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_out_a_bits_opcode; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_out_a_bits_param; // @[Buffer.scala:75:28]
wire [3:0] _buffer_auto_out_a_bits_size; // @[Buffer.scala:75:28]
wire _buffer_auto_out_a_bits_source; // @[Buffer.scala:75:28]
wire [31:0] _buffer_auto_out_a_bits_address; // @[Buffer.scala:75:28]
wire [7:0] _buffer_auto_out_a_bits_mask; // @[Buffer.scala:75:28]
wire [63:0] _buffer_auto_out_a_bits_data; // @[Buffer.scala:75:28]
wire _buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:75:28]
wire _buffer_auto_out_d_ready; // @[Buffer.scala:75:28]
wire _tsi2tl_auto_out_a_valid; // @[TSIHarness.scala:76:28]
wire [2:0] _tsi2tl_auto_out_a_bits_opcode; // @[TSIHarness.scala:76:28]
wire [3:0] _tsi2tl_auto_out_a_bits_size; // @[TSIHarness.scala:76:28]
wire [31:0] _tsi2tl_auto_out_a_bits_address; // @[TSIHarness.scala:76:28]
wire [7:0] _tsi2tl_auto_out_a_bits_mask; // @[TSIHarness.scala:76:28]
wire [63:0] _tsi2tl_auto_out_a_bits_data; // @[TSIHarness.scala:76:28]
wire _tsi2tl_auto_out_d_ready; // @[TSIHarness.scala:76:28]
wire _serdesser_auto_manager_in_a_ready; // @[TSIHarness.scala:66:29]
wire _serdesser_auto_manager_in_d_valid; // @[TSIHarness.scala:66:29]
wire [2:0] _serdesser_auto_manager_in_d_bits_opcode; // @[TSIHarness.scala:66:29]
wire [1:0] _serdesser_auto_manager_in_d_bits_param; // @[TSIHarness.scala:66:29]
wire [3:0] _serdesser_auto_manager_in_d_bits_size; // @[TSIHarness.scala:66:29]
wire _serdesser_auto_manager_in_d_bits_source; // @[TSIHarness.scala:66:29]
wire [4:0] _serdesser_auto_manager_in_d_bits_sink; // @[TSIHarness.scala:66:29]
wire _serdesser_auto_manager_in_d_bits_denied; // @[TSIHarness.scala:66:29]
wire [63:0] _serdesser_auto_manager_in_d_bits_data; // @[TSIHarness.scala:66:29]
wire _serdesser_auto_manager_in_d_bits_corrupt; // @[TSIHarness.scala:66:29]
wire _serdesser_io_ser_0_in_ready; // @[TSIHarness.scala:66:29]
wire [31:0] _serdesser_io_ser_0_out_bits_flit; // @[TSIHarness.scala:66:29]
wire _serdesser_io_ser_1_in_ready; // @[TSIHarness.scala:66:29]
wire _serdesser_io_ser_2_in_ready; // @[TSIHarness.scala:66:29]
wire _serdesser_io_ser_2_out_valid; // @[TSIHarness.scala:66:29]
wire [31:0] _serdesser_io_ser_2_out_bits_flit; // @[TSIHarness.scala:66:29]
wire _serdesser_io_ser_3_in_ready; // @[TSIHarness.scala:66:29]
wire _serdesser_io_ser_4_in_ready; // @[TSIHarness.scala:66:29]
wire _serdesser_io_ser_4_out_valid; // @[TSIHarness.scala:66:29]
wire [31:0] _serdesser_io_ser_4_out_bits_flit; // @[TSIHarness.scala:66:29]
TLSerdesser_SerialRAM serdesser ( // @[TSIHarness.scala:66:29]
.clock (clock),
.reset (reset),
.auto_manager_in_a_ready (_serdesser_auto_manager_in_a_ready),
.auto_manager_in_a_valid (_buffer_auto_out_a_valid), // @[Buffer.scala:75:28]
.auto_manager_in_a_bits_opcode (_buffer_auto_out_a_bits_opcode), // @[Buffer.scala:75:28]
.auto_manager_in_a_bits_param (_buffer_auto_out_a_bits_param), // @[Buffer.scala:75:28]
.auto_manager_in_a_bits_size (_buffer_auto_out_a_bits_size), // @[Buffer.scala:75:28]
.auto_manager_in_a_bits_source (_buffer_auto_out_a_bits_source), // @[Buffer.scala:75:28]
.auto_manager_in_a_bits_address (_buffer_auto_out_a_bits_address), // @[Buffer.scala:75:28]
.auto_manager_in_a_bits_mask (_buffer_auto_out_a_bits_mask), // @[Buffer.scala:75:28]
.auto_manager_in_a_bits_data (_buffer_auto_out_a_bits_data), // @[Buffer.scala:75:28]
.auto_manager_in_a_bits_corrupt (_buffer_auto_out_a_bits_corrupt), // @[Buffer.scala:75:28]
.auto_manager_in_d_ready (_buffer_auto_out_d_ready), // @[Buffer.scala:75:28]
.auto_manager_in_d_valid (_serdesser_auto_manager_in_d_valid),
.auto_manager_in_d_bits_opcode (_serdesser_auto_manager_in_d_bits_opcode),
.auto_manager_in_d_bits_param (_serdesser_auto_manager_in_d_bits_param),
.auto_manager_in_d_bits_size (_serdesser_auto_manager_in_d_bits_size),
.auto_manager_in_d_bits_source (_serdesser_auto_manager_in_d_bits_source),
.auto_manager_in_d_bits_sink (_serdesser_auto_manager_in_d_bits_sink),
.auto_manager_in_d_bits_denied (_serdesser_auto_manager_in_d_bits_denied),
.auto_manager_in_d_bits_data (_serdesser_auto_manager_in_d_bits_data),
.auto_manager_in_d_bits_corrupt (_serdesser_auto_manager_in_d_bits_corrupt),
.io_ser_0_in_ready (_serdesser_io_ser_0_in_ready),
.io_ser_0_in_valid (_phy_io_inner_ser_0_in_valid), // @[TSIHarness.scala:129:21]
.io_ser_0_in_bits_flit (_phy_io_inner_ser_0_in_bits_flit), // @[TSIHarness.scala:129:21]
.io_ser_0_out_bits_flit (_serdesser_io_ser_0_out_bits_flit),
.io_ser_1_in_ready (_serdesser_io_ser_1_in_ready),
.io_ser_1_in_valid (_phy_io_inner_ser_1_in_valid), // @[TSIHarness.scala:129:21]
.io_ser_1_in_bits_flit (_phy_io_inner_ser_1_in_bits_flit), // @[TSIHarness.scala:129:21]
.io_ser_2_in_ready (_serdesser_io_ser_2_in_ready),
.io_ser_2_in_valid (_phy_io_inner_ser_2_in_valid), // @[TSIHarness.scala:129:21]
.io_ser_2_in_bits_flit (_phy_io_inner_ser_2_in_bits_flit), // @[TSIHarness.scala:129:21]
.io_ser_2_out_ready (_phy_io_inner_ser_2_out_ready), // @[TSIHarness.scala:129:21]
.io_ser_2_out_valid (_serdesser_io_ser_2_out_valid),
.io_ser_2_out_bits_flit (_serdesser_io_ser_2_out_bits_flit),
.io_ser_3_in_ready (_serdesser_io_ser_3_in_ready),
.io_ser_3_in_valid (_phy_io_inner_ser_3_in_valid), // @[TSIHarness.scala:129:21]
.io_ser_3_in_bits_flit (_phy_io_inner_ser_3_in_bits_flit), // @[TSIHarness.scala:129:21]
.io_ser_4_in_ready (_serdesser_io_ser_4_in_ready),
.io_ser_4_in_valid (_phy_io_inner_ser_4_in_valid), // @[TSIHarness.scala:129:21]
.io_ser_4_in_bits_flit (_phy_io_inner_ser_4_in_bits_flit), // @[TSIHarness.scala:129:21]
.io_ser_4_out_ready (_phy_io_inner_ser_4_out_ready), // @[TSIHarness.scala:129:21]
.io_ser_4_out_valid (_serdesser_io_ser_4_out_valid),
.io_ser_4_out_bits_flit (_serdesser_io_ser_4_out_bits_flit)
); // @[TSIHarness.scala:66:29]
TSIToTileLink tsi2tl ( // @[TSIHarness.scala:76:28]
.clock (clock),
.reset (reset),
.auto_out_a_ready (_buffer_auto_in_a_ready), // @[Buffer.scala:75:28]
.auto_out_a_valid (_tsi2tl_auto_out_a_valid),
.auto_out_a_bits_opcode (_tsi2tl_auto_out_a_bits_opcode),
.auto_out_a_bits_size (_tsi2tl_auto_out_a_bits_size),
.auto_out_a_bits_address (_tsi2tl_auto_out_a_bits_address),
.auto_out_a_bits_mask (_tsi2tl_auto_out_a_bits_mask),
.auto_out_a_bits_data (_tsi2tl_auto_out_a_bits_data),
.auto_out_d_ready (_tsi2tl_auto_out_d_ready),
.auto_out_d_valid (_buffer_auto_in_d_valid), // @[Buffer.scala:75:28]
.auto_out_d_bits_data (_buffer_auto_in_d_bits_data), // @[Buffer.scala:75:28]
.io_tsi_in_ready (io_tsi_in_ready),
.io_tsi_in_valid (io_tsi_in_valid),
.io_tsi_in_bits (io_tsi_in_bits),
.io_tsi_out_ready (io_tsi_out_ready),
.io_tsi_out_valid (io_tsi_out_valid),
.io_tsi_out_bits (io_tsi_out_bits)
); // @[TSIHarness.scala:76:28]
TLBuffer_a32d64s1k5z4u buffer ( // @[Buffer.scala:75:28]
.clock (clock),
.reset (reset),
.auto_in_a_ready (_buffer_auto_in_a_ready),
.auto_in_a_valid (_tsi2tl_auto_out_a_valid), // @[TSIHarness.scala:76:28]
.auto_in_a_bits_opcode (_tsi2tl_auto_out_a_bits_opcode), // @[TSIHarness.scala:76:28]
.auto_in_a_bits_size (_tsi2tl_auto_out_a_bits_size), // @[TSIHarness.scala:76:28]
.auto_in_a_bits_address (_tsi2tl_auto_out_a_bits_address), // @[TSIHarness.scala:76:28]
.auto_in_a_bits_mask (_tsi2tl_auto_out_a_bits_mask), // @[TSIHarness.scala:76:28]
.auto_in_a_bits_data (_tsi2tl_auto_out_a_bits_data), // @[TSIHarness.scala:76:28]
.auto_in_d_ready (_tsi2tl_auto_out_d_ready), // @[TSIHarness.scala:76:28]
.auto_in_d_valid (_buffer_auto_in_d_valid),
.auto_in_d_bits_data (_buffer_auto_in_d_bits_data),
.auto_out_a_ready (_serdesser_auto_manager_in_a_ready), // @[TSIHarness.scala:66:29]
.auto_out_a_valid (_buffer_auto_out_a_valid),
.auto_out_a_bits_opcode (_buffer_auto_out_a_bits_opcode),
.auto_out_a_bits_param (_buffer_auto_out_a_bits_param),
.auto_out_a_bits_size (_buffer_auto_out_a_bits_size),
.auto_out_a_bits_source (_buffer_auto_out_a_bits_source),
.auto_out_a_bits_address (_buffer_auto_out_a_bits_address),
.auto_out_a_bits_mask (_buffer_auto_out_a_bits_mask),
.auto_out_a_bits_data (_buffer_auto_out_a_bits_data),
.auto_out_a_bits_corrupt (_buffer_auto_out_a_bits_corrupt),
.auto_out_d_ready (_buffer_auto_out_d_ready),
.auto_out_d_valid (_serdesser_auto_manager_in_d_valid), // @[TSIHarness.scala:66:29]
.auto_out_d_bits_opcode (_serdesser_auto_manager_in_d_bits_opcode), // @[TSIHarness.scala:66:29]
.auto_out_d_bits_param (_serdesser_auto_manager_in_d_bits_param), // @[TSIHarness.scala:66:29]
.auto_out_d_bits_size (_serdesser_auto_manager_in_d_bits_size), // @[TSIHarness.scala:66:29]
.auto_out_d_bits_source (_serdesser_auto_manager_in_d_bits_source), // @[TSIHarness.scala:66:29]
.auto_out_d_bits_sink (_serdesser_auto_manager_in_d_bits_sink), // @[TSIHarness.scala:66:29]
.auto_out_d_bits_denied (_serdesser_auto_manager_in_d_bits_denied), // @[TSIHarness.scala:66:29]
.auto_out_d_bits_data (_serdesser_auto_manager_in_d_bits_data), // @[TSIHarness.scala:66:29]
.auto_out_d_bits_corrupt (_serdesser_auto_manager_in_d_bits_corrupt) // @[TSIHarness.scala:66:29]
); // @[Buffer.scala:75:28]
DecoupledSerialPhy phy ( // @[TSIHarness.scala:129:21]
.io_outer_clock (clock),
.io_outer_reset (reset),
.io_inner_clock (clock),
.io_inner_reset (reset),
.io_outer_ser_in_ready (io_ser_in_ready),
.io_outer_ser_in_valid (io_ser_in_valid),
.io_outer_ser_in_bits_phit (io_ser_in_bits_phit),
.io_outer_ser_out_ready (io_ser_out_ready),
.io_outer_ser_out_valid (io_ser_out_valid),
.io_outer_ser_out_bits_phit (io_ser_out_bits_phit),
.io_inner_ser_0_in_ready (_serdesser_io_ser_0_in_ready), // @[TSIHarness.scala:66:29]
.io_inner_ser_0_in_valid (_phy_io_inner_ser_0_in_valid),
.io_inner_ser_0_in_bits_flit (_phy_io_inner_ser_0_in_bits_flit),
.io_inner_ser_0_out_bits_flit (_serdesser_io_ser_0_out_bits_flit), // @[TSIHarness.scala:66:29]
.io_inner_ser_1_in_ready (_serdesser_io_ser_1_in_ready), // @[TSIHarness.scala:66:29]
.io_inner_ser_1_in_valid (_phy_io_inner_ser_1_in_valid),
.io_inner_ser_1_in_bits_flit (_phy_io_inner_ser_1_in_bits_flit),
.io_inner_ser_1_out_ready (/* unused */),
.io_inner_ser_1_out_valid (1'h0), // @[TSIHarness.scala:66:29, :76:28, :129:21]
.io_inner_ser_1_out_bits_flit (32'h0), // @[TSIHarness.scala:66:29, :129:21]
.io_inner_ser_2_in_ready (_serdesser_io_ser_2_in_ready), // @[TSIHarness.scala:66:29]
.io_inner_ser_2_in_valid (_phy_io_inner_ser_2_in_valid),
.io_inner_ser_2_in_bits_flit (_phy_io_inner_ser_2_in_bits_flit),
.io_inner_ser_2_out_ready (_phy_io_inner_ser_2_out_ready),
.io_inner_ser_2_out_valid (_serdesser_io_ser_2_out_valid), // @[TSIHarness.scala:66:29]
.io_inner_ser_2_out_bits_flit (_serdesser_io_ser_2_out_bits_flit), // @[TSIHarness.scala:66:29]
.io_inner_ser_3_in_ready (_serdesser_io_ser_3_in_ready), // @[TSIHarness.scala:66:29]
.io_inner_ser_3_in_valid (_phy_io_inner_ser_3_in_valid),
.io_inner_ser_3_in_bits_flit (_phy_io_inner_ser_3_in_bits_flit),
.io_inner_ser_3_out_ready (/* unused */),
.io_inner_ser_3_out_valid (1'h0), // @[TSIHarness.scala:66:29, :76:28, :129:21]
.io_inner_ser_3_out_bits_flit (32'h0), // @[TSIHarness.scala:66:29, :129:21]
.io_inner_ser_4_in_ready (_serdesser_io_ser_4_in_ready), // @[TSIHarness.scala:66:29]
.io_inner_ser_4_in_valid (_phy_io_inner_ser_4_in_valid),
.io_inner_ser_4_in_bits_flit (_phy_io_inner_ser_4_in_bits_flit),
.io_inner_ser_4_out_ready (_phy_io_inner_ser_4_out_ready),
.io_inner_ser_4_out_valid (_serdesser_io_ser_4_out_valid), // @[TSIHarness.scala:66:29]
.io_inner_ser_4_out_bits_flit (_serdesser_io_ser_4_out_bits_flit) // @[TSIHarness.scala:66:29]
); // @[TSIHarness.scala:129:21]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TileResetSetter :
input clock : Clock
input reset : Reset
output auto : { flip clock_in : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, clock_out : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire tlNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate tlNodeIn.d.bits.corrupt
invalidate tlNodeIn.d.bits.data
invalidate tlNodeIn.d.bits.denied
invalidate tlNodeIn.d.bits.sink
invalidate tlNodeIn.d.bits.source
invalidate tlNodeIn.d.bits.size
invalidate tlNodeIn.d.bits.param
invalidate tlNodeIn.d.bits.opcode
invalidate tlNodeIn.d.valid
invalidate tlNodeIn.d.ready
invalidate tlNodeIn.a.bits.corrupt
invalidate tlNodeIn.a.bits.data
invalidate tlNodeIn.a.bits.mask
invalidate tlNodeIn.a.bits.address
invalidate tlNodeIn.a.bits.source
invalidate tlNodeIn.a.bits.size
invalidate tlNodeIn.a.bits.param
invalidate tlNodeIn.a.bits.opcode
invalidate tlNodeIn.a.valid
invalidate tlNodeIn.a.ready
inst monitor of TLMonitor_119
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, tlNodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, tlNodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, tlNodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, tlNodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, tlNodeIn.d.bits.source
connect monitor.io.in.d.bits.size, tlNodeIn.d.bits.size
connect monitor.io.in.d.bits.param, tlNodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, tlNodeIn.d.bits.opcode
connect monitor.io.in.d.valid, tlNodeIn.d.valid
connect monitor.io.in.d.ready, tlNodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, tlNodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, tlNodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, tlNodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, tlNodeIn.a.bits.address
connect monitor.io.in.a.bits.source, tlNodeIn.a.bits.source
connect monitor.io.in.a.bits.size, tlNodeIn.a.bits.size
connect monitor.io.in.a.bits.param, tlNodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, tlNodeIn.a.bits.opcode
connect monitor.io.in.a.valid, tlNodeIn.a.valid
connect monitor.io.in.a.ready, tlNodeIn.a.ready
wire clockNodeOut : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}
invalidate clockNodeOut.member.allClocks_uncore.reset
invalidate clockNodeOut.member.allClocks_uncore.clock
wire clockNodeIn : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}
invalidate clockNodeIn.member.allClocks_uncore.reset
invalidate clockNodeIn.member.allClocks_uncore.clock
connect clockNodeOut, clockNodeIn
connect tlNodeIn, auto.tl_in
connect auto.clock_out, clockNodeOut
connect clockNodeIn, auto.clock_in
wire tile_async_resets : Reset[12]
node _tile_async_resets_0_T = asAsyncReset(UInt<1>(0h1))
connect tile_async_resets[0], _tile_async_resets_0_T
inst r_tile_resets_0 of AsyncResetRegVec_w1_i0_61
connect r_tile_resets_0.clock, clock
connect r_tile_resets_0.reset, tile_async_resets[0]
node _tile_async_resets_1_T = asAsyncReset(UInt<1>(0h1))
connect tile_async_resets[1], _tile_async_resets_1_T
inst r_tile_resets_1 of AsyncResetRegVec_w1_i0_62
connect r_tile_resets_1.clock, clock
connect r_tile_resets_1.reset, tile_async_resets[1]
node _tile_async_resets_2_T = asAsyncReset(UInt<1>(0h1))
connect tile_async_resets[2], _tile_async_resets_2_T
inst r_tile_resets_2 of AsyncResetRegVec_w1_i0_63
connect r_tile_resets_2.clock, clock
connect r_tile_resets_2.reset, tile_async_resets[2]
node _tile_async_resets_3_T = asAsyncReset(UInt<1>(0h1))
connect tile_async_resets[3], _tile_async_resets_3_T
inst r_tile_resets_3 of AsyncResetRegVec_w1_i0_64
connect r_tile_resets_3.clock, clock
connect r_tile_resets_3.reset, tile_async_resets[3]
node _tile_async_resets_4_T = asAsyncReset(UInt<1>(0h1))
connect tile_async_resets[4], _tile_async_resets_4_T
inst r_tile_resets_4 of AsyncResetRegVec_w1_i0_65
connect r_tile_resets_4.clock, clock
connect r_tile_resets_4.reset, tile_async_resets[4]
node _tile_async_resets_5_T = asAsyncReset(UInt<1>(0h1))
connect tile_async_resets[5], _tile_async_resets_5_T
inst r_tile_resets_5 of AsyncResetRegVec_w1_i0_66
connect r_tile_resets_5.clock, clock
connect r_tile_resets_5.reset, tile_async_resets[5]
node _tile_async_resets_6_T = asAsyncReset(UInt<1>(0h1))
connect tile_async_resets[6], _tile_async_resets_6_T
inst r_tile_resets_6 of AsyncResetRegVec_w1_i0_67
connect r_tile_resets_6.clock, clock
connect r_tile_resets_6.reset, tile_async_resets[6]
node _tile_async_resets_7_T = asAsyncReset(UInt<1>(0h1))
connect tile_async_resets[7], _tile_async_resets_7_T
inst r_tile_resets_7 of AsyncResetRegVec_w1_i0_68
connect r_tile_resets_7.clock, clock
connect r_tile_resets_7.reset, tile_async_resets[7]
node _tile_async_resets_8_T = asAsyncReset(UInt<1>(0h1))
connect tile_async_resets[8], _tile_async_resets_8_T
inst r_tile_resets_8 of AsyncResetRegVec_w1_i0_69
connect r_tile_resets_8.clock, clock
connect r_tile_resets_8.reset, tile_async_resets[8]
node _tile_async_resets_9_T = asAsyncReset(UInt<1>(0h1))
connect tile_async_resets[9], _tile_async_resets_9_T
inst r_tile_resets_9 of AsyncResetRegVec_w1_i0_70
connect r_tile_resets_9.clock, clock
connect r_tile_resets_9.reset, tile_async_resets[9]
node _tile_async_resets_10_T = asAsyncReset(UInt<1>(0h1))
connect tile_async_resets[10], _tile_async_resets_10_T
inst r_tile_resets_10 of AsyncResetRegVec_w1_i0_71
connect r_tile_resets_10.clock, clock
connect r_tile_resets_10.reset, tile_async_resets[10]
node _tile_async_resets_11_T = asAsyncReset(UInt<1>(0h1))
connect tile_async_resets[11], _tile_async_resets_11_T
inst r_tile_resets_11 of AsyncResetRegVec_w1_i0_72
connect r_tile_resets_11.clock, clock
connect r_tile_resets_11.reset, tile_async_resets[11]
wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}}
node _in_bits_read_T = eq(tlNodeIn.a.bits.opcode, UInt<3>(0h4))
connect in.bits.read, _in_bits_read_T
node _in_bits_index_T = shr(tlNodeIn.a.bits.address, 3)
connect in.bits.index, _in_bits_index_T
connect in.bits.data, tlNodeIn.a.bits.data
connect in.bits.mask, tlNodeIn.a.bits.mask
connect in.bits.extra.tlrr_extra.source, tlNodeIn.a.bits.source
connect in.bits.extra.tlrr_extra.size, tlNodeIn.a.bits.size
wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}}
wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}}
connect out_front.bits, in.bits
node out_maskMatch = not(UInt<9>(0h7))
node out_findex = and(out_front.bits.index, out_maskMatch)
node out_bindex = and(out_front.bits.index, out_maskMatch)
node _out_T = eq(out_findex, UInt<9>(0h0))
node _out_T_1 = eq(out_bindex, UInt<9>(0h0))
node _out_T_2 = eq(out_findex, UInt<9>(0h0))
node _out_T_3 = eq(out_bindex, UInt<9>(0h0))
node _out_T_4 = eq(out_findex, UInt<9>(0h0))
node _out_T_5 = eq(out_bindex, UInt<9>(0h0))
node _out_T_6 = eq(out_findex, UInt<9>(0h0))
node _out_T_7 = eq(out_bindex, UInt<9>(0h0))
node _out_T_8 = eq(out_findex, UInt<9>(0h0))
node _out_T_9 = eq(out_bindex, UInt<9>(0h0))
node _out_T_10 = eq(out_findex, UInt<9>(0h0))
node _out_T_11 = eq(out_bindex, UInt<9>(0h0))
wire out_rivalid : UInt<1>[12]
wire out_wivalid : UInt<1>[12]
wire out_roready : UInt<1>[12]
wire out_woready : UInt<1>[12]
node _out_frontMask_T = bits(out_front.bits.mask, 0, 0)
node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1)
node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2)
node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3)
node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4)
node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5)
node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6)
node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7)
node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0))
node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8)
node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10)
node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo)
node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12)
node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14)
node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo)
node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo)
node _out_backMask_T = bits(out_front.bits.mask, 0, 0)
node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1)
node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2)
node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3)
node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4)
node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5)
node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6)
node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7)
node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0))
node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8)
node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10)
node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo)
node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12)
node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14)
node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo)
node out_backMask = cat(out_backMask_hi, out_backMask_lo)
node _out_rimask_T = bits(out_frontMask, 0, 0)
node out_rimask = orr(_out_rimask_T)
node _out_wimask_T = bits(out_frontMask, 0, 0)
node out_wimask = andr(_out_wimask_T)
node _out_romask_T = bits(out_backMask, 0, 0)
node out_romask = orr(_out_romask_T)
node _out_womask_T = bits(out_backMask, 0, 0)
node out_womask = andr(_out_womask_T)
node out_f_rivalid = and(out_rivalid[0], out_rimask)
node out_f_roready = and(out_roready[0], out_romask)
node out_f_wivalid = and(out_wivalid[0], out_wimask)
node out_f_woready = and(out_woready[0], out_womask)
node _out_T_12 = bits(out_front.bits.data, 0, 0)
connect r_tile_resets_0.io.en, out_f_woready
connect r_tile_resets_0.io.d, _out_T_12
node _out_T_13 = eq(out_rimask, UInt<1>(0h0))
node _out_T_14 = eq(out_wimask, UInt<1>(0h0))
node _out_T_15 = eq(out_romask, UInt<1>(0h0))
node _out_T_16 = eq(out_womask, UInt<1>(0h0))
node _out_T_17 = or(r_tile_resets_0.io.q, UInt<1>(0h0))
node _out_T_18 = bits(_out_T_17, 0, 0)
node _out_rimask_T_1 = bits(out_frontMask, 32, 32)
node out_rimask_1 = orr(_out_rimask_T_1)
node _out_wimask_T_1 = bits(out_frontMask, 32, 32)
node out_wimask_1 = andr(_out_wimask_T_1)
node _out_romask_T_1 = bits(out_backMask, 32, 32)
node out_romask_1 = orr(_out_romask_T_1)
node _out_womask_T_1 = bits(out_backMask, 32, 32)
node out_womask_1 = andr(_out_womask_T_1)
node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1)
node out_f_roready_1 = and(out_roready[1], out_romask_1)
node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1)
node out_f_woready_1 = and(out_woready[1], out_womask_1)
node _out_T_19 = bits(out_front.bits.data, 32, 32)
connect r_tile_resets_1.io.en, out_f_woready_1
connect r_tile_resets_1.io.d, _out_T_19
node _out_T_20 = eq(out_rimask_1, UInt<1>(0h0))
node _out_T_21 = eq(out_wimask_1, UInt<1>(0h0))
node _out_T_22 = eq(out_romask_1, UInt<1>(0h0))
node _out_T_23 = eq(out_womask_1, UInt<1>(0h0))
node _out_prepend_T = or(_out_T_18, UInt<32>(0h0))
node out_prepend = cat(r_tile_resets_1.io.q, _out_prepend_T)
node _out_T_24 = or(out_prepend, UInt<33>(0h0))
node _out_T_25 = bits(_out_T_24, 32, 0)
node _out_rimask_T_2 = bits(out_frontMask, 0, 0)
node out_rimask_2 = orr(_out_rimask_T_2)
node _out_wimask_T_2 = bits(out_frontMask, 0, 0)
node out_wimask_2 = andr(_out_wimask_T_2)
node _out_romask_T_2 = bits(out_backMask, 0, 0)
node out_romask_2 = orr(_out_romask_T_2)
node _out_womask_T_2 = bits(out_backMask, 0, 0)
node out_womask_2 = andr(_out_womask_T_2)
node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2)
node out_f_roready_2 = and(out_roready[2], out_romask_2)
node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2)
node out_f_woready_2 = and(out_woready[2], out_womask_2)
node _out_T_26 = bits(out_front.bits.data, 0, 0)
connect r_tile_resets_10.io.en, out_f_woready_2
connect r_tile_resets_10.io.d, _out_T_26
node _out_T_27 = eq(out_rimask_2, UInt<1>(0h0))
node _out_T_28 = eq(out_wimask_2, UInt<1>(0h0))
node _out_T_29 = eq(out_romask_2, UInt<1>(0h0))
node _out_T_30 = eq(out_womask_2, UInt<1>(0h0))
node _out_T_31 = or(r_tile_resets_10.io.q, UInt<1>(0h0))
node _out_T_32 = bits(_out_T_31, 0, 0)
node _out_rimask_T_3 = bits(out_frontMask, 32, 32)
node out_rimask_3 = orr(_out_rimask_T_3)
node _out_wimask_T_3 = bits(out_frontMask, 32, 32)
node out_wimask_3 = andr(_out_wimask_T_3)
node _out_romask_T_3 = bits(out_backMask, 32, 32)
node out_romask_3 = orr(_out_romask_T_3)
node _out_womask_T_3 = bits(out_backMask, 32, 32)
node out_womask_3 = andr(_out_womask_T_3)
node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3)
node out_f_roready_3 = and(out_roready[3], out_romask_3)
node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3)
node out_f_woready_3 = and(out_woready[3], out_womask_3)
node _out_T_33 = bits(out_front.bits.data, 32, 32)
connect r_tile_resets_11.io.en, out_f_woready_3
connect r_tile_resets_11.io.d, _out_T_33
node _out_T_34 = eq(out_rimask_3, UInt<1>(0h0))
node _out_T_35 = eq(out_wimask_3, UInt<1>(0h0))
node _out_T_36 = eq(out_romask_3, UInt<1>(0h0))
node _out_T_37 = eq(out_womask_3, UInt<1>(0h0))
node _out_prepend_T_1 = or(_out_T_32, UInt<32>(0h0))
node out_prepend_1 = cat(r_tile_resets_11.io.q, _out_prepend_T_1)
node _out_T_38 = or(out_prepend_1, UInt<33>(0h0))
node _out_T_39 = bits(_out_T_38, 32, 0)
node _out_rimask_T_4 = bits(out_frontMask, 0, 0)
node out_rimask_4 = orr(_out_rimask_T_4)
node _out_wimask_T_4 = bits(out_frontMask, 0, 0)
node out_wimask_4 = andr(_out_wimask_T_4)
node _out_romask_T_4 = bits(out_backMask, 0, 0)
node out_romask_4 = orr(_out_romask_T_4)
node _out_womask_T_4 = bits(out_backMask, 0, 0)
node out_womask_4 = andr(_out_womask_T_4)
node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4)
node out_f_roready_4 = and(out_roready[4], out_romask_4)
node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4)
node out_f_woready_4 = and(out_woready[4], out_womask_4)
node _out_T_40 = bits(out_front.bits.data, 0, 0)
connect r_tile_resets_2.io.en, out_f_woready_4
connect r_tile_resets_2.io.d, _out_T_40
node _out_T_41 = eq(out_rimask_4, UInt<1>(0h0))
node _out_T_42 = eq(out_wimask_4, UInt<1>(0h0))
node _out_T_43 = eq(out_romask_4, UInt<1>(0h0))
node _out_T_44 = eq(out_womask_4, UInt<1>(0h0))
node _out_T_45 = or(r_tile_resets_2.io.q, UInt<1>(0h0))
node _out_T_46 = bits(_out_T_45, 0, 0)
node _out_rimask_T_5 = bits(out_frontMask, 32, 32)
node out_rimask_5 = orr(_out_rimask_T_5)
node _out_wimask_T_5 = bits(out_frontMask, 32, 32)
node out_wimask_5 = andr(_out_wimask_T_5)
node _out_romask_T_5 = bits(out_backMask, 32, 32)
node out_romask_5 = orr(_out_romask_T_5)
node _out_womask_T_5 = bits(out_backMask, 32, 32)
node out_womask_5 = andr(_out_womask_T_5)
node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5)
node out_f_roready_5 = and(out_roready[5], out_romask_5)
node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5)
node out_f_woready_5 = and(out_woready[5], out_womask_5)
node _out_T_47 = bits(out_front.bits.data, 32, 32)
connect r_tile_resets_3.io.en, out_f_woready_5
connect r_tile_resets_3.io.d, _out_T_47
node _out_T_48 = eq(out_rimask_5, UInt<1>(0h0))
node _out_T_49 = eq(out_wimask_5, UInt<1>(0h0))
node _out_T_50 = eq(out_romask_5, UInt<1>(0h0))
node _out_T_51 = eq(out_womask_5, UInt<1>(0h0))
node _out_prepend_T_2 = or(_out_T_46, UInt<32>(0h0))
node out_prepend_2 = cat(r_tile_resets_3.io.q, _out_prepend_T_2)
node _out_T_52 = or(out_prepend_2, UInt<33>(0h0))
node _out_T_53 = bits(_out_T_52, 32, 0)
node _out_rimask_T_6 = bits(out_frontMask, 0, 0)
node out_rimask_6 = orr(_out_rimask_T_6)
node _out_wimask_T_6 = bits(out_frontMask, 0, 0)
node out_wimask_6 = andr(_out_wimask_T_6)
node _out_romask_T_6 = bits(out_backMask, 0, 0)
node out_romask_6 = orr(_out_romask_T_6)
node _out_womask_T_6 = bits(out_backMask, 0, 0)
node out_womask_6 = andr(_out_womask_T_6)
node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6)
node out_f_roready_6 = and(out_roready[6], out_romask_6)
node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6)
node out_f_woready_6 = and(out_woready[6], out_womask_6)
node _out_T_54 = bits(out_front.bits.data, 0, 0)
connect r_tile_resets_4.io.en, out_f_woready_6
connect r_tile_resets_4.io.d, _out_T_54
node _out_T_55 = eq(out_rimask_6, UInt<1>(0h0))
node _out_T_56 = eq(out_wimask_6, UInt<1>(0h0))
node _out_T_57 = eq(out_romask_6, UInt<1>(0h0))
node _out_T_58 = eq(out_womask_6, UInt<1>(0h0))
node _out_T_59 = or(r_tile_resets_4.io.q, UInt<1>(0h0))
node _out_T_60 = bits(_out_T_59, 0, 0)
node _out_rimask_T_7 = bits(out_frontMask, 32, 32)
node out_rimask_7 = orr(_out_rimask_T_7)
node _out_wimask_T_7 = bits(out_frontMask, 32, 32)
node out_wimask_7 = andr(_out_wimask_T_7)
node _out_romask_T_7 = bits(out_backMask, 32, 32)
node out_romask_7 = orr(_out_romask_T_7)
node _out_womask_T_7 = bits(out_backMask, 32, 32)
node out_womask_7 = andr(_out_womask_T_7)
node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7)
node out_f_roready_7 = and(out_roready[7], out_romask_7)
node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7)
node out_f_woready_7 = and(out_woready[7], out_womask_7)
node _out_T_61 = bits(out_front.bits.data, 32, 32)
connect r_tile_resets_5.io.en, out_f_woready_7
connect r_tile_resets_5.io.d, _out_T_61
node _out_T_62 = eq(out_rimask_7, UInt<1>(0h0))
node _out_T_63 = eq(out_wimask_7, UInt<1>(0h0))
node _out_T_64 = eq(out_romask_7, UInt<1>(0h0))
node _out_T_65 = eq(out_womask_7, UInt<1>(0h0))
node _out_prepend_T_3 = or(_out_T_60, UInt<32>(0h0))
node out_prepend_3 = cat(r_tile_resets_5.io.q, _out_prepend_T_3)
node _out_T_66 = or(out_prepend_3, UInt<33>(0h0))
node _out_T_67 = bits(_out_T_66, 32, 0)
node _out_rimask_T_8 = bits(out_frontMask, 0, 0)
node out_rimask_8 = orr(_out_rimask_T_8)
node _out_wimask_T_8 = bits(out_frontMask, 0, 0)
node out_wimask_8 = andr(_out_wimask_T_8)
node _out_romask_T_8 = bits(out_backMask, 0, 0)
node out_romask_8 = orr(_out_romask_T_8)
node _out_womask_T_8 = bits(out_backMask, 0, 0)
node out_womask_8 = andr(_out_womask_T_8)
node out_f_rivalid_8 = and(out_rivalid[8], out_rimask_8)
node out_f_roready_8 = and(out_roready[8], out_romask_8)
node out_f_wivalid_8 = and(out_wivalid[8], out_wimask_8)
node out_f_woready_8 = and(out_woready[8], out_womask_8)
node _out_T_68 = bits(out_front.bits.data, 0, 0)
connect r_tile_resets_6.io.en, out_f_woready_8
connect r_tile_resets_6.io.d, _out_T_68
node _out_T_69 = eq(out_rimask_8, UInt<1>(0h0))
node _out_T_70 = eq(out_wimask_8, UInt<1>(0h0))
node _out_T_71 = eq(out_romask_8, UInt<1>(0h0))
node _out_T_72 = eq(out_womask_8, UInt<1>(0h0))
node _out_T_73 = or(r_tile_resets_6.io.q, UInt<1>(0h0))
node _out_T_74 = bits(_out_T_73, 0, 0)
node _out_rimask_T_9 = bits(out_frontMask, 32, 32)
node out_rimask_9 = orr(_out_rimask_T_9)
node _out_wimask_T_9 = bits(out_frontMask, 32, 32)
node out_wimask_9 = andr(_out_wimask_T_9)
node _out_romask_T_9 = bits(out_backMask, 32, 32)
node out_romask_9 = orr(_out_romask_T_9)
node _out_womask_T_9 = bits(out_backMask, 32, 32)
node out_womask_9 = andr(_out_womask_T_9)
node out_f_rivalid_9 = and(out_rivalid[9], out_rimask_9)
node out_f_roready_9 = and(out_roready[9], out_romask_9)
node out_f_wivalid_9 = and(out_wivalid[9], out_wimask_9)
node out_f_woready_9 = and(out_woready[9], out_womask_9)
node _out_T_75 = bits(out_front.bits.data, 32, 32)
connect r_tile_resets_7.io.en, out_f_woready_9
connect r_tile_resets_7.io.d, _out_T_75
node _out_T_76 = eq(out_rimask_9, UInt<1>(0h0))
node _out_T_77 = eq(out_wimask_9, UInt<1>(0h0))
node _out_T_78 = eq(out_romask_9, UInt<1>(0h0))
node _out_T_79 = eq(out_womask_9, UInt<1>(0h0))
node _out_prepend_T_4 = or(_out_T_74, UInt<32>(0h0))
node out_prepend_4 = cat(r_tile_resets_7.io.q, _out_prepend_T_4)
node _out_T_80 = or(out_prepend_4, UInt<33>(0h0))
node _out_T_81 = bits(_out_T_80, 32, 0)
node _out_rimask_T_10 = bits(out_frontMask, 0, 0)
node out_rimask_10 = orr(_out_rimask_T_10)
node _out_wimask_T_10 = bits(out_frontMask, 0, 0)
node out_wimask_10 = andr(_out_wimask_T_10)
node _out_romask_T_10 = bits(out_backMask, 0, 0)
node out_romask_10 = orr(_out_romask_T_10)
node _out_womask_T_10 = bits(out_backMask, 0, 0)
node out_womask_10 = andr(_out_womask_T_10)
node out_f_rivalid_10 = and(out_rivalid[10], out_rimask_10)
node out_f_roready_10 = and(out_roready[10], out_romask_10)
node out_f_wivalid_10 = and(out_wivalid[10], out_wimask_10)
node out_f_woready_10 = and(out_woready[10], out_womask_10)
node _out_T_82 = bits(out_front.bits.data, 0, 0)
connect r_tile_resets_8.io.en, out_f_woready_10
connect r_tile_resets_8.io.d, _out_T_82
node _out_T_83 = eq(out_rimask_10, UInt<1>(0h0))
node _out_T_84 = eq(out_wimask_10, UInt<1>(0h0))
node _out_T_85 = eq(out_romask_10, UInt<1>(0h0))
node _out_T_86 = eq(out_womask_10, UInt<1>(0h0))
node _out_T_87 = or(r_tile_resets_8.io.q, UInt<1>(0h0))
node _out_T_88 = bits(_out_T_87, 0, 0)
node _out_rimask_T_11 = bits(out_frontMask, 32, 32)
node out_rimask_11 = orr(_out_rimask_T_11)
node _out_wimask_T_11 = bits(out_frontMask, 32, 32)
node out_wimask_11 = andr(_out_wimask_T_11)
node _out_romask_T_11 = bits(out_backMask, 32, 32)
node out_romask_11 = orr(_out_romask_T_11)
node _out_womask_T_11 = bits(out_backMask, 32, 32)
node out_womask_11 = andr(_out_womask_T_11)
node out_f_rivalid_11 = and(out_rivalid[11], out_rimask_11)
node out_f_roready_11 = and(out_roready[11], out_romask_11)
node out_f_wivalid_11 = and(out_wivalid[11], out_wimask_11)
node out_f_woready_11 = and(out_woready[11], out_womask_11)
node _out_T_89 = bits(out_front.bits.data, 32, 32)
connect r_tile_resets_9.io.en, out_f_woready_11
connect r_tile_resets_9.io.d, _out_T_89
node _out_T_90 = eq(out_rimask_11, UInt<1>(0h0))
node _out_T_91 = eq(out_wimask_11, UInt<1>(0h0))
node _out_T_92 = eq(out_romask_11, UInt<1>(0h0))
node _out_T_93 = eq(out_womask_11, UInt<1>(0h0))
node _out_prepend_T_5 = or(_out_T_88, UInt<32>(0h0))
node out_prepend_5 = cat(r_tile_resets_9.io.q, _out_prepend_T_5)
node _out_T_94 = or(out_prepend_5, UInt<33>(0h0))
node _out_T_95 = bits(_out_T_94, 32, 0)
node _out_iindex_T = bits(out_front.bits.index, 0, 0)
node _out_iindex_T_1 = bits(out_front.bits.index, 1, 1)
node _out_iindex_T_2 = bits(out_front.bits.index, 2, 2)
node _out_iindex_T_3 = bits(out_front.bits.index, 3, 3)
node _out_iindex_T_4 = bits(out_front.bits.index, 4, 4)
node _out_iindex_T_5 = bits(out_front.bits.index, 5, 5)
node _out_iindex_T_6 = bits(out_front.bits.index, 6, 6)
node _out_iindex_T_7 = bits(out_front.bits.index, 7, 7)
node _out_iindex_T_8 = bits(out_front.bits.index, 8, 8)
node out_iindex_hi = cat(_out_iindex_T_2, _out_iindex_T_1)
node out_iindex = cat(out_iindex_hi, _out_iindex_T)
node _out_oindex_T = bits(out_front.bits.index, 0, 0)
node _out_oindex_T_1 = bits(out_front.bits.index, 1, 1)
node _out_oindex_T_2 = bits(out_front.bits.index, 2, 2)
node _out_oindex_T_3 = bits(out_front.bits.index, 3, 3)
node _out_oindex_T_4 = bits(out_front.bits.index, 4, 4)
node _out_oindex_T_5 = bits(out_front.bits.index, 5, 5)
node _out_oindex_T_6 = bits(out_front.bits.index, 6, 6)
node _out_oindex_T_7 = bits(out_front.bits.index, 7, 7)
node _out_oindex_T_8 = bits(out_front.bits.index, 8, 8)
node out_oindex_hi = cat(_out_oindex_T_2, _out_oindex_T_1)
node out_oindex = cat(out_oindex_hi, _out_oindex_T)
node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex)
node out_frontSel_0 = bits(_out_frontSel_T, 0, 0)
node out_frontSel_1 = bits(_out_frontSel_T, 1, 1)
node out_frontSel_2 = bits(_out_frontSel_T, 2, 2)
node out_frontSel_3 = bits(_out_frontSel_T, 3, 3)
node out_frontSel_4 = bits(_out_frontSel_T, 4, 4)
node out_frontSel_5 = bits(_out_frontSel_T, 5, 5)
node out_frontSel_6 = bits(_out_frontSel_T, 6, 6)
node out_frontSel_7 = bits(_out_frontSel_T, 7, 7)
node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex)
node out_backSel_0 = bits(_out_backSel_T, 0, 0)
node out_backSel_1 = bits(_out_backSel_T, 1, 1)
node out_backSel_2 = bits(_out_backSel_T, 2, 2)
node out_backSel_3 = bits(_out_backSel_T, 3, 3)
node out_backSel_4 = bits(_out_backSel_T, 4, 4)
node out_backSel_5 = bits(_out_backSel_T, 5, 5)
node out_backSel_6 = bits(_out_backSel_T, 6, 6)
node out_backSel_7 = bits(_out_backSel_T, 7, 7)
node _out_rifireMux_T = and(in.valid, out_front.ready)
node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read)
wire out_rifireMux_out : UInt<1>
node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0)
node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T)
connect out_rifireMux_out, UInt<1>(0h1)
connect out_rivalid[1], _out_rifireMux_T_3
connect out_rivalid[0], _out_rifireMux_T_3
node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0))
node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4)
wire out_rifireMux_out_1 : UInt<1>
node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1)
node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, _out_T_4)
connect out_rifireMux_out_1, UInt<1>(0h1)
connect out_rivalid[5], _out_rifireMux_T_7
connect out_rivalid[4], _out_rifireMux_T_7
node _out_rifireMux_T_8 = eq(_out_T_4, UInt<1>(0h0))
node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8)
wire out_rifireMux_out_2 : UInt<1>
node _out_rifireMux_T_10 = and(_out_rifireMux_T_1, out_frontSel_2)
node _out_rifireMux_T_11 = and(_out_rifireMux_T_10, _out_T_6)
connect out_rifireMux_out_2, UInt<1>(0h1)
connect out_rivalid[7], _out_rifireMux_T_11
connect out_rivalid[6], _out_rifireMux_T_11
node _out_rifireMux_T_12 = eq(_out_T_6, UInt<1>(0h0))
node _out_rifireMux_T_13 = or(out_rifireMux_out_2, _out_rifireMux_T_12)
wire out_rifireMux_out_3 : UInt<1>
node _out_rifireMux_T_14 = and(_out_rifireMux_T_1, out_frontSel_3)
node _out_rifireMux_T_15 = and(_out_rifireMux_T_14, _out_T_8)
connect out_rifireMux_out_3, UInt<1>(0h1)
connect out_rivalid[9], _out_rifireMux_T_15
connect out_rivalid[8], _out_rifireMux_T_15
node _out_rifireMux_T_16 = eq(_out_T_8, UInt<1>(0h0))
node _out_rifireMux_T_17 = or(out_rifireMux_out_3, _out_rifireMux_T_16)
wire out_rifireMux_out_4 : UInt<1>
node _out_rifireMux_T_18 = and(_out_rifireMux_T_1, out_frontSel_4)
node _out_rifireMux_T_19 = and(_out_rifireMux_T_18, _out_T_10)
connect out_rifireMux_out_4, UInt<1>(0h1)
connect out_rivalid[11], _out_rifireMux_T_19
connect out_rivalid[10], _out_rifireMux_T_19
node _out_rifireMux_T_20 = eq(_out_T_10, UInt<1>(0h0))
node _out_rifireMux_T_21 = or(out_rifireMux_out_4, _out_rifireMux_T_20)
wire out_rifireMux_out_5 : UInt<1>
node _out_rifireMux_T_22 = and(_out_rifireMux_T_1, out_frontSel_5)
node _out_rifireMux_T_23 = and(_out_rifireMux_T_22, _out_T_2)
connect out_rifireMux_out_5, UInt<1>(0h1)
connect out_rivalid[3], _out_rifireMux_T_23
connect out_rivalid[2], _out_rifireMux_T_23
node _out_rifireMux_T_24 = eq(_out_T_2, UInt<1>(0h0))
node _out_rifireMux_T_25 = or(out_rifireMux_out_5, _out_rifireMux_T_24)
wire out_rifireMux_out_6 : UInt<1>
node _out_rifireMux_T_26 = and(_out_rifireMux_T_1, out_frontSel_6)
node _out_rifireMux_T_27 = and(_out_rifireMux_T_26, UInt<1>(0h1))
connect out_rifireMux_out_6, UInt<1>(0h1)
node _out_rifireMux_T_28 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _out_rifireMux_T_29 = or(out_rifireMux_out_6, _out_rifireMux_T_28)
wire out_rifireMux_out_7 : UInt<1>
node _out_rifireMux_T_30 = and(_out_rifireMux_T_1, out_frontSel_7)
node _out_rifireMux_T_31 = and(_out_rifireMux_T_30, UInt<1>(0h1))
connect out_rifireMux_out_7, UInt<1>(0h1)
node _out_rifireMux_T_32 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _out_rifireMux_T_33 = or(out_rifireMux_out_7, _out_rifireMux_T_32)
node _out_rifireMux_T_34 = geq(out_iindex, UInt<4>(0h8))
wire _out_rifireMux_WIRE : UInt<1>[8]
connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5
connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9
connect _out_rifireMux_WIRE[2], _out_rifireMux_T_13
connect _out_rifireMux_WIRE[3], _out_rifireMux_T_17
connect _out_rifireMux_WIRE[4], _out_rifireMux_T_21
connect _out_rifireMux_WIRE[5], _out_rifireMux_T_25
connect _out_rifireMux_WIRE[6], _out_rifireMux_T_29
connect _out_rifireMux_WIRE[7], _out_rifireMux_T_33
node out_rifireMux = mux(_out_rifireMux_T_34, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex])
node _out_wifireMux_T = and(in.valid, out_front.ready)
node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0))
node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1)
wire out_wifireMux_out : UInt<1>
node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0)
node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T)
connect out_wifireMux_out, UInt<1>(0h1)
connect out_wivalid[1], _out_wifireMux_T_4
connect out_wivalid[0], _out_wifireMux_T_4
node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0))
node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5)
wire out_wifireMux_out_1 : UInt<1>
node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1)
node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, _out_T_4)
connect out_wifireMux_out_1, UInt<1>(0h1)
connect out_wivalid[5], _out_wifireMux_T_8
connect out_wivalid[4], _out_wifireMux_T_8
node _out_wifireMux_T_9 = eq(_out_T_4, UInt<1>(0h0))
node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9)
wire out_wifireMux_out_2 : UInt<1>
node _out_wifireMux_T_11 = and(_out_wifireMux_T_2, out_frontSel_2)
node _out_wifireMux_T_12 = and(_out_wifireMux_T_11, _out_T_6)
connect out_wifireMux_out_2, UInt<1>(0h1)
connect out_wivalid[7], _out_wifireMux_T_12
connect out_wivalid[6], _out_wifireMux_T_12
node _out_wifireMux_T_13 = eq(_out_T_6, UInt<1>(0h0))
node _out_wifireMux_T_14 = or(out_wifireMux_out_2, _out_wifireMux_T_13)
wire out_wifireMux_out_3 : UInt<1>
node _out_wifireMux_T_15 = and(_out_wifireMux_T_2, out_frontSel_3)
node _out_wifireMux_T_16 = and(_out_wifireMux_T_15, _out_T_8)
connect out_wifireMux_out_3, UInt<1>(0h1)
connect out_wivalid[9], _out_wifireMux_T_16
connect out_wivalid[8], _out_wifireMux_T_16
node _out_wifireMux_T_17 = eq(_out_T_8, UInt<1>(0h0))
node _out_wifireMux_T_18 = or(out_wifireMux_out_3, _out_wifireMux_T_17)
wire out_wifireMux_out_4 : UInt<1>
node _out_wifireMux_T_19 = and(_out_wifireMux_T_2, out_frontSel_4)
node _out_wifireMux_T_20 = and(_out_wifireMux_T_19, _out_T_10)
connect out_wifireMux_out_4, UInt<1>(0h1)
connect out_wivalid[11], _out_wifireMux_T_20
connect out_wivalid[10], _out_wifireMux_T_20
node _out_wifireMux_T_21 = eq(_out_T_10, UInt<1>(0h0))
node _out_wifireMux_T_22 = or(out_wifireMux_out_4, _out_wifireMux_T_21)
wire out_wifireMux_out_5 : UInt<1>
node _out_wifireMux_T_23 = and(_out_wifireMux_T_2, out_frontSel_5)
node _out_wifireMux_T_24 = and(_out_wifireMux_T_23, _out_T_2)
connect out_wifireMux_out_5, UInt<1>(0h1)
connect out_wivalid[3], _out_wifireMux_T_24
connect out_wivalid[2], _out_wifireMux_T_24
node _out_wifireMux_T_25 = eq(_out_T_2, UInt<1>(0h0))
node _out_wifireMux_T_26 = or(out_wifireMux_out_5, _out_wifireMux_T_25)
wire out_wifireMux_out_6 : UInt<1>
node _out_wifireMux_T_27 = and(_out_wifireMux_T_2, out_frontSel_6)
node _out_wifireMux_T_28 = and(_out_wifireMux_T_27, UInt<1>(0h1))
connect out_wifireMux_out_6, UInt<1>(0h1)
node _out_wifireMux_T_29 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _out_wifireMux_T_30 = or(out_wifireMux_out_6, _out_wifireMux_T_29)
wire out_wifireMux_out_7 : UInt<1>
node _out_wifireMux_T_31 = and(_out_wifireMux_T_2, out_frontSel_7)
node _out_wifireMux_T_32 = and(_out_wifireMux_T_31, UInt<1>(0h1))
connect out_wifireMux_out_7, UInt<1>(0h1)
node _out_wifireMux_T_33 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _out_wifireMux_T_34 = or(out_wifireMux_out_7, _out_wifireMux_T_33)
node _out_wifireMux_T_35 = geq(out_iindex, UInt<4>(0h8))
wire _out_wifireMux_WIRE : UInt<1>[8]
connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6
connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10
connect _out_wifireMux_WIRE[2], _out_wifireMux_T_14
connect _out_wifireMux_WIRE[3], _out_wifireMux_T_18
connect _out_wifireMux_WIRE[4], _out_wifireMux_T_22
connect _out_wifireMux_WIRE[5], _out_wifireMux_T_26
connect _out_wifireMux_WIRE[6], _out_wifireMux_T_30
connect _out_wifireMux_WIRE[7], _out_wifireMux_T_34
node out_wifireMux = mux(_out_wifireMux_T_35, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex])
node _out_rofireMux_T = and(out_front.valid, out.ready)
node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read)
wire out_rofireMux_out : UInt<1>
node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0)
node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1)
connect out_rofireMux_out, UInt<1>(0h1)
connect out_roready[1], _out_rofireMux_T_3
connect out_roready[0], _out_rofireMux_T_3
node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0))
node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4)
wire out_rofireMux_out_1 : UInt<1>
node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1)
node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, _out_T_5)
connect out_rofireMux_out_1, UInt<1>(0h1)
connect out_roready[5], _out_rofireMux_T_7
connect out_roready[4], _out_rofireMux_T_7
node _out_rofireMux_T_8 = eq(_out_T_5, UInt<1>(0h0))
node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8)
wire out_rofireMux_out_2 : UInt<1>
node _out_rofireMux_T_10 = and(_out_rofireMux_T_1, out_backSel_2)
node _out_rofireMux_T_11 = and(_out_rofireMux_T_10, _out_T_7)
connect out_rofireMux_out_2, UInt<1>(0h1)
connect out_roready[7], _out_rofireMux_T_11
connect out_roready[6], _out_rofireMux_T_11
node _out_rofireMux_T_12 = eq(_out_T_7, UInt<1>(0h0))
node _out_rofireMux_T_13 = or(out_rofireMux_out_2, _out_rofireMux_T_12)
wire out_rofireMux_out_3 : UInt<1>
node _out_rofireMux_T_14 = and(_out_rofireMux_T_1, out_backSel_3)
node _out_rofireMux_T_15 = and(_out_rofireMux_T_14, _out_T_9)
connect out_rofireMux_out_3, UInt<1>(0h1)
connect out_roready[9], _out_rofireMux_T_15
connect out_roready[8], _out_rofireMux_T_15
node _out_rofireMux_T_16 = eq(_out_T_9, UInt<1>(0h0))
node _out_rofireMux_T_17 = or(out_rofireMux_out_3, _out_rofireMux_T_16)
wire out_rofireMux_out_4 : UInt<1>
node _out_rofireMux_T_18 = and(_out_rofireMux_T_1, out_backSel_4)
node _out_rofireMux_T_19 = and(_out_rofireMux_T_18, _out_T_11)
connect out_rofireMux_out_4, UInt<1>(0h1)
connect out_roready[11], _out_rofireMux_T_19
connect out_roready[10], _out_rofireMux_T_19
node _out_rofireMux_T_20 = eq(_out_T_11, UInt<1>(0h0))
node _out_rofireMux_T_21 = or(out_rofireMux_out_4, _out_rofireMux_T_20)
wire out_rofireMux_out_5 : UInt<1>
node _out_rofireMux_T_22 = and(_out_rofireMux_T_1, out_backSel_5)
node _out_rofireMux_T_23 = and(_out_rofireMux_T_22, _out_T_3)
connect out_rofireMux_out_5, UInt<1>(0h1)
connect out_roready[3], _out_rofireMux_T_23
connect out_roready[2], _out_rofireMux_T_23
node _out_rofireMux_T_24 = eq(_out_T_3, UInt<1>(0h0))
node _out_rofireMux_T_25 = or(out_rofireMux_out_5, _out_rofireMux_T_24)
wire out_rofireMux_out_6 : UInt<1>
node _out_rofireMux_T_26 = and(_out_rofireMux_T_1, out_backSel_6)
node _out_rofireMux_T_27 = and(_out_rofireMux_T_26, UInt<1>(0h1))
connect out_rofireMux_out_6, UInt<1>(0h1)
node _out_rofireMux_T_28 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _out_rofireMux_T_29 = or(out_rofireMux_out_6, _out_rofireMux_T_28)
wire out_rofireMux_out_7 : UInt<1>
node _out_rofireMux_T_30 = and(_out_rofireMux_T_1, out_backSel_7)
node _out_rofireMux_T_31 = and(_out_rofireMux_T_30, UInt<1>(0h1))
connect out_rofireMux_out_7, UInt<1>(0h1)
node _out_rofireMux_T_32 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _out_rofireMux_T_33 = or(out_rofireMux_out_7, _out_rofireMux_T_32)
node _out_rofireMux_T_34 = geq(out_oindex, UInt<4>(0h8))
wire _out_rofireMux_WIRE : UInt<1>[8]
connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5
connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9
connect _out_rofireMux_WIRE[2], _out_rofireMux_T_13
connect _out_rofireMux_WIRE[3], _out_rofireMux_T_17
connect _out_rofireMux_WIRE[4], _out_rofireMux_T_21
connect _out_rofireMux_WIRE[5], _out_rofireMux_T_25
connect _out_rofireMux_WIRE[6], _out_rofireMux_T_29
connect _out_rofireMux_WIRE[7], _out_rofireMux_T_33
node out_rofireMux = mux(_out_rofireMux_T_34, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex])
node _out_wofireMux_T = and(out_front.valid, out.ready)
node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0))
node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1)
wire out_wofireMux_out : UInt<1>
node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0)
node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1)
connect out_wofireMux_out, UInt<1>(0h1)
connect out_woready[1], _out_wofireMux_T_4
connect out_woready[0], _out_wofireMux_T_4
node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0))
node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5)
wire out_wofireMux_out_1 : UInt<1>
node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1)
node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, _out_T_5)
connect out_wofireMux_out_1, UInt<1>(0h1)
connect out_woready[5], _out_wofireMux_T_8
connect out_woready[4], _out_wofireMux_T_8
node _out_wofireMux_T_9 = eq(_out_T_5, UInt<1>(0h0))
node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9)
wire out_wofireMux_out_2 : UInt<1>
node _out_wofireMux_T_11 = and(_out_wofireMux_T_2, out_backSel_2)
node _out_wofireMux_T_12 = and(_out_wofireMux_T_11, _out_T_7)
connect out_wofireMux_out_2, UInt<1>(0h1)
connect out_woready[7], _out_wofireMux_T_12
connect out_woready[6], _out_wofireMux_T_12
node _out_wofireMux_T_13 = eq(_out_T_7, UInt<1>(0h0))
node _out_wofireMux_T_14 = or(out_wofireMux_out_2, _out_wofireMux_T_13)
wire out_wofireMux_out_3 : UInt<1>
node _out_wofireMux_T_15 = and(_out_wofireMux_T_2, out_backSel_3)
node _out_wofireMux_T_16 = and(_out_wofireMux_T_15, _out_T_9)
connect out_wofireMux_out_3, UInt<1>(0h1)
connect out_woready[9], _out_wofireMux_T_16
connect out_woready[8], _out_wofireMux_T_16
node _out_wofireMux_T_17 = eq(_out_T_9, UInt<1>(0h0))
node _out_wofireMux_T_18 = or(out_wofireMux_out_3, _out_wofireMux_T_17)
wire out_wofireMux_out_4 : UInt<1>
node _out_wofireMux_T_19 = and(_out_wofireMux_T_2, out_backSel_4)
node _out_wofireMux_T_20 = and(_out_wofireMux_T_19, _out_T_11)
connect out_wofireMux_out_4, UInt<1>(0h1)
connect out_woready[11], _out_wofireMux_T_20
connect out_woready[10], _out_wofireMux_T_20
node _out_wofireMux_T_21 = eq(_out_T_11, UInt<1>(0h0))
node _out_wofireMux_T_22 = or(out_wofireMux_out_4, _out_wofireMux_T_21)
wire out_wofireMux_out_5 : UInt<1>
node _out_wofireMux_T_23 = and(_out_wofireMux_T_2, out_backSel_5)
node _out_wofireMux_T_24 = and(_out_wofireMux_T_23, _out_T_3)
connect out_wofireMux_out_5, UInt<1>(0h1)
connect out_woready[3], _out_wofireMux_T_24
connect out_woready[2], _out_wofireMux_T_24
node _out_wofireMux_T_25 = eq(_out_T_3, UInt<1>(0h0))
node _out_wofireMux_T_26 = or(out_wofireMux_out_5, _out_wofireMux_T_25)
wire out_wofireMux_out_6 : UInt<1>
node _out_wofireMux_T_27 = and(_out_wofireMux_T_2, out_backSel_6)
node _out_wofireMux_T_28 = and(_out_wofireMux_T_27, UInt<1>(0h1))
connect out_wofireMux_out_6, UInt<1>(0h1)
node _out_wofireMux_T_29 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _out_wofireMux_T_30 = or(out_wofireMux_out_6, _out_wofireMux_T_29)
wire out_wofireMux_out_7 : UInt<1>
node _out_wofireMux_T_31 = and(_out_wofireMux_T_2, out_backSel_7)
node _out_wofireMux_T_32 = and(_out_wofireMux_T_31, UInt<1>(0h1))
connect out_wofireMux_out_7, UInt<1>(0h1)
node _out_wofireMux_T_33 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _out_wofireMux_T_34 = or(out_wofireMux_out_7, _out_wofireMux_T_33)
node _out_wofireMux_T_35 = geq(out_oindex, UInt<4>(0h8))
wire _out_wofireMux_WIRE : UInt<1>[8]
connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6
connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10
connect _out_wofireMux_WIRE[2], _out_wofireMux_T_14
connect _out_wofireMux_WIRE[3], _out_wofireMux_T_18
connect _out_wofireMux_WIRE[4], _out_wofireMux_T_22
connect _out_wofireMux_WIRE[5], _out_wofireMux_T_26
connect _out_wofireMux_WIRE[6], _out_wofireMux_T_30
connect _out_wofireMux_WIRE[7], _out_wofireMux_T_34
node out_wofireMux = mux(_out_wofireMux_T_35, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex])
node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux)
node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux)
node _out_in_ready_T = and(out_front.ready, out_iready)
connect in.ready, _out_in_ready_T
node _out_front_valid_T = and(in.valid, out_iready)
connect out_front.valid, _out_front_valid_T
node _out_front_ready_T = and(out.ready, out_oready)
connect out_front.ready, _out_front_ready_T
node _out_out_valid_T = and(out_front.valid, out_oready)
connect out.valid, _out_out_valid_T
connect out.bits.read, out_front.bits.read
node _out_out_bits_data_T = geq(out_oindex, UInt<4>(0h8))
wire _out_out_bits_data_WIRE : UInt<1>[8]
connect _out_out_bits_data_WIRE[0], _out_T_1
connect _out_out_bits_data_WIRE[1], _out_T_5
connect _out_out_bits_data_WIRE[2], _out_T_7
connect _out_out_bits_data_WIRE[3], _out_T_9
connect _out_out_bits_data_WIRE[4], _out_T_11
connect _out_out_bits_data_WIRE[5], _out_T_3
connect _out_out_bits_data_WIRE[6], UInt<1>(0h1)
connect _out_out_bits_data_WIRE[7], UInt<1>(0h1)
node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex])
node _out_out_bits_data_T_2 = geq(out_oindex, UInt<4>(0h8))
wire _out_out_bits_data_WIRE_1 : UInt<33>[8]
connect _out_out_bits_data_WIRE_1[0], _out_T_25
connect _out_out_bits_data_WIRE_1[1], _out_T_53
connect _out_out_bits_data_WIRE_1[2], _out_T_67
connect _out_out_bits_data_WIRE_1[3], _out_T_81
connect _out_out_bits_data_WIRE_1[4], _out_T_95
connect _out_out_bits_data_WIRE_1[5], _out_T_39
connect _out_out_bits_data_WIRE_1[6], UInt<1>(0h0)
connect _out_out_bits_data_WIRE_1[7], UInt<1>(0h0)
node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex])
node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0))
connect out.bits.data, _out_out_bits_data_T_4
connect out.bits.extra, out_front.bits.extra
connect in.valid, tlNodeIn.a.valid
connect tlNodeIn.a.ready, in.ready
connect tlNodeIn.d.valid, out.valid
connect out.ready, tlNodeIn.d.ready
wire tlNodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect tlNodeIn_d_bits_d.opcode, UInt<1>(0h0)
connect tlNodeIn_d_bits_d.param, UInt<1>(0h0)
connect tlNodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size
connect tlNodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source
connect tlNodeIn_d_bits_d.sink, UInt<1>(0h0)
connect tlNodeIn_d_bits_d.denied, UInt<1>(0h0)
invalidate tlNodeIn_d_bits_d.data
connect tlNodeIn_d_bits_d.corrupt, UInt<1>(0h0)
connect tlNodeIn.d.bits.corrupt, tlNodeIn_d_bits_d.corrupt
connect tlNodeIn.d.bits.data, tlNodeIn_d_bits_d.data
connect tlNodeIn.d.bits.denied, tlNodeIn_d_bits_d.denied
connect tlNodeIn.d.bits.sink, tlNodeIn_d_bits_d.sink
connect tlNodeIn.d.bits.source, tlNodeIn_d_bits_d.source
connect tlNodeIn.d.bits.size, tlNodeIn_d_bits_d.size
connect tlNodeIn.d.bits.param, tlNodeIn_d_bits_d.param
connect tlNodeIn.d.bits.opcode, tlNodeIn_d_bits_d.opcode
connect tlNodeIn.d.bits.data, out.bits.data
node _tlNodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0))
connect tlNodeIn.d.bits.opcode, _tlNodeIn_d_bits_opcode_T
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<21>(0h0)
connect _WIRE.bits.source, UInt<12>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<21>(0h0)
connect _WIRE_2.bits.source, UInt<12>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
connect clockNodeOut.member.allClocks_uncore.clock, clockNodeIn.member.allClocks_uncore.clock
connect clockNodeOut.member.allClocks_uncore.reset, clockNodeIn.member.allClocks_uncore.reset
extmodule plusarg_reader_286 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_287 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TileResetSetter( // @[TileResetSetter.scala:26:25]
input clock, // @[TileResetSetter.scala:26:25]
input reset, // @[TileResetSetter.scala:26:25]
input auto_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25]
output auto_clock_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25]
output auto_clock_out_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [11:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [20:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [11:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_in_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire [2:0] tlNodeIn_d_bits_opcode = {2'h0, auto_tl_in_a_bits_opcode == 3'h4}; // @[RegisterRouter.scala:74:36, :105:19]
TLMonitor_119 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (auto_tl_in_d_ready),
.io_in_a_valid (auto_tl_in_a_valid),
.io_in_a_bits_opcode (auto_tl_in_a_bits_opcode),
.io_in_a_bits_param (auto_tl_in_a_bits_param),
.io_in_a_bits_size (auto_tl_in_a_bits_size),
.io_in_a_bits_source (auto_tl_in_a_bits_source),
.io_in_a_bits_address (auto_tl_in_a_bits_address),
.io_in_a_bits_mask (auto_tl_in_a_bits_mask),
.io_in_a_bits_corrupt (auto_tl_in_a_bits_corrupt),
.io_in_d_ready (auto_tl_in_d_ready),
.io_in_d_valid (auto_tl_in_a_valid),
.io_in_d_bits_opcode (tlNodeIn_d_bits_opcode), // @[RegisterRouter.scala:105:19]
.io_in_d_bits_size (auto_tl_in_a_bits_size),
.io_in_d_bits_source (auto_tl_in_a_bits_source)
); // @[Nodes.scala:27:25]
assign auto_clock_out_member_allClocks_uncore_clock = auto_clock_in_member_allClocks_uncore_clock; // @[TileResetSetter.scala:26:25]
assign auto_clock_out_member_allClocks_uncore_reset = auto_clock_in_member_allClocks_uncore_reset; // @[TileResetSetter.scala:26:25]
assign auto_tl_in_a_ready = auto_tl_in_d_ready; // @[TileResetSetter.scala:26:25]
assign auto_tl_in_d_valid = auto_tl_in_a_valid; // @[TileResetSetter.scala:26:25]
assign auto_tl_in_d_bits_opcode = tlNodeIn_d_bits_opcode; // @[RegisterRouter.scala:105:19]
assign auto_tl_in_d_bits_size = auto_tl_in_a_bits_size; // @[TileResetSetter.scala:26:25]
assign auto_tl_in_d_bits_source = auto_tl_in_a_bits_source; // @[TileResetSetter.scala:26:25]
assign auto_tl_in_d_bits_data = 64'h0; // @[TileResetSetter.scala:26:25]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e8_s24_109 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_109
connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc
connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc
connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig
connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp
connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign
connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero
connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf
connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN
connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundAnyRawFNToRecFN.io.out
connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags | module RoundRawFNToRecFN_e8_s24_109( // @[RoundAnyRawFNToRecFN.scala:295:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_109 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15]
.io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[RoundAnyRawFNToRecFN.scala:310:15]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_122 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_202
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_122( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_202 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_25 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE : UInt<1>[9]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
connect _source_ok_WIRE[7], _source_ok_T_27
connect _source_ok_WIRE[8], _source_ok_T_28
node _source_ok_T_29 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[2])
node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[3])
node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[4])
node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[5])
node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[6])
node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[7])
node source_ok = or(_source_ok_T_35, _source_ok_WIRE[8])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_81 = eq(_T_80, UInt<1>(0h0))
node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_83 = cvt(_T_82)
node _T_84 = and(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = asSInt(_T_84)
node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = or(_T_81, _T_86)
node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_89 = eq(_T_88, UInt<1>(0h0))
node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<1>(0h0)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_89, _T_94)
node _T_96 = and(_T_11, _T_24)
node _T_97 = and(_T_96, _T_37)
node _T_98 = and(_T_97, _T_50)
node _T_99 = and(_T_98, _T_63)
node _T_100 = and(_T_99, _T_71)
node _T_101 = and(_T_100, _T_79)
node _T_102 = and(_T_101, _T_87)
node _T_103 = and(_T_102, _T_95)
node _T_104 = asUInt(reset)
node _T_105 = eq(_T_104, UInt<1>(0h0))
when _T_105 :
node _T_106 = eq(_T_103, UInt<1>(0h0))
when _T_106 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_103, UInt<1>(0h1), "") : assert_1
node _T_107 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_107 :
node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_112 = shr(io.in.a.bits.source, 2)
node _T_113 = eq(_T_112, UInt<1>(0h0))
node _T_114 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_115 = and(_T_113, _T_114)
node _T_116 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_117 = and(_T_115, _T_116)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_118 = shr(io.in.a.bits.source, 2)
node _T_119 = eq(_T_118, UInt<1>(0h1))
node _T_120 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_121 = and(_T_119, _T_120)
node _T_122 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_123 = and(_T_121, _T_122)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_124 = shr(io.in.a.bits.source, 2)
node _T_125 = eq(_T_124, UInt<2>(0h2))
node _T_126 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_127 = and(_T_125, _T_126)
node _T_128 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_129 = and(_T_127, _T_128)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_130 = shr(io.in.a.bits.source, 2)
node _T_131 = eq(_T_130, UInt<2>(0h3))
node _T_132 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_133 = and(_T_131, _T_132)
node _T_134 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_135 = and(_T_133, _T_134)
node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_137 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_140 = or(_T_111, _T_117)
node _T_141 = or(_T_140, _T_123)
node _T_142 = or(_T_141, _T_129)
node _T_143 = or(_T_142, _T_135)
node _T_144 = or(_T_143, _T_136)
node _T_145 = or(_T_144, _T_137)
node _T_146 = or(_T_145, _T_138)
node _T_147 = or(_T_146, _T_139)
node _T_148 = and(_T_110, _T_147)
node _T_149 = or(UInt<1>(0h0), _T_148)
node _T_150 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_151 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_152 = cvt(_T_151)
node _T_153 = and(_T_152, asSInt(UInt<13>(0h1000)))
node _T_154 = asSInt(_T_153)
node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0)))
node _T_156 = and(_T_150, _T_155)
node _T_157 = or(UInt<1>(0h0), _T_156)
node _T_158 = and(_T_149, _T_157)
node _T_159 = asUInt(reset)
node _T_160 = eq(_T_159, UInt<1>(0h0))
when _T_160 :
node _T_161 = eq(_T_158, UInt<1>(0h0))
when _T_161 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_158, UInt<1>(0h1), "") : assert_2
node _T_162 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_163 = shr(io.in.a.bits.source, 2)
node _T_164 = eq(_T_163, UInt<1>(0h0))
node _T_165 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_166 = and(_T_164, _T_165)
node _T_167 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_168 = and(_T_166, _T_167)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_169 = shr(io.in.a.bits.source, 2)
node _T_170 = eq(_T_169, UInt<1>(0h1))
node _T_171 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_172 = and(_T_170, _T_171)
node _T_173 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_174 = and(_T_172, _T_173)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_175 = shr(io.in.a.bits.source, 2)
node _T_176 = eq(_T_175, UInt<2>(0h2))
node _T_177 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_178 = and(_T_176, _T_177)
node _T_179 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_180 = and(_T_178, _T_179)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_181 = shr(io.in.a.bits.source, 2)
node _T_182 = eq(_T_181, UInt<2>(0h3))
node _T_183 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_184 = and(_T_182, _T_183)
node _T_185 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_186 = and(_T_184, _T_185)
node _T_187 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_188 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_189 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_190 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE : UInt<1>[9]
connect _WIRE[0], _T_162
connect _WIRE[1], _T_168
connect _WIRE[2], _T_174
connect _WIRE[3], _T_180
connect _WIRE[4], _T_186
connect _WIRE[5], _T_187
connect _WIRE[6], _T_188
connect _WIRE[7], _T_189
connect _WIRE[8], _T_190
node _T_191 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_192 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_193 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_194 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_195 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_196 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_197 = mux(_WIRE[5], _T_191, UInt<1>(0h0))
node _T_198 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_199 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_200 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_201 = or(_T_192, _T_193)
node _T_202 = or(_T_201, _T_194)
node _T_203 = or(_T_202, _T_195)
node _T_204 = or(_T_203, _T_196)
node _T_205 = or(_T_204, _T_197)
node _T_206 = or(_T_205, _T_198)
node _T_207 = or(_T_206, _T_199)
node _T_208 = or(_T_207, _T_200)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_208
node _T_209 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_210 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_211 = and(_T_209, _T_210)
node _T_212 = or(UInt<1>(0h0), _T_211)
node _T_213 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_214 = cvt(_T_213)
node _T_215 = and(_T_214, asSInt(UInt<13>(0h1000)))
node _T_216 = asSInt(_T_215)
node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0)))
node _T_218 = and(_T_212, _T_217)
node _T_219 = or(UInt<1>(0h0), _T_218)
node _T_220 = and(_WIRE_1, _T_219)
node _T_221 = asUInt(reset)
node _T_222 = eq(_T_221, UInt<1>(0h0))
when _T_222 :
node _T_223 = eq(_T_220, UInt<1>(0h0))
when _T_223 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_220, UInt<1>(0h1), "") : assert_3
node _T_224 = asUInt(reset)
node _T_225 = eq(_T_224, UInt<1>(0h0))
when _T_225 :
node _T_226 = eq(source_ok, UInt<1>(0h0))
when _T_226 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_227 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_228 = asUInt(reset)
node _T_229 = eq(_T_228, UInt<1>(0h0))
when _T_229 :
node _T_230 = eq(_T_227, UInt<1>(0h0))
when _T_230 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_227, UInt<1>(0h1), "") : assert_5
node _T_231 = asUInt(reset)
node _T_232 = eq(_T_231, UInt<1>(0h0))
when _T_232 :
node _T_233 = eq(is_aligned, UInt<1>(0h0))
when _T_233 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_234 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_235 = asUInt(reset)
node _T_236 = eq(_T_235, UInt<1>(0h0))
when _T_236 :
node _T_237 = eq(_T_234, UInt<1>(0h0))
when _T_237 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_234, UInt<1>(0h1), "") : assert_7
node _T_238 = not(io.in.a.bits.mask)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_239, UInt<1>(0h1), "") : assert_8
node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_244 = asUInt(reset)
node _T_245 = eq(_T_244, UInt<1>(0h0))
when _T_245 :
node _T_246 = eq(_T_243, UInt<1>(0h0))
when _T_246 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_243, UInt<1>(0h1), "") : assert_9
node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_247 :
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_250 = and(_T_248, _T_249)
node _T_251 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_252 = shr(io.in.a.bits.source, 2)
node _T_253 = eq(_T_252, UInt<1>(0h0))
node _T_254 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_255 = and(_T_253, _T_254)
node _T_256 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_257 = and(_T_255, _T_256)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_258 = shr(io.in.a.bits.source, 2)
node _T_259 = eq(_T_258, UInt<1>(0h1))
node _T_260 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_261 = and(_T_259, _T_260)
node _T_262 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_263 = and(_T_261, _T_262)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_264 = shr(io.in.a.bits.source, 2)
node _T_265 = eq(_T_264, UInt<2>(0h2))
node _T_266 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_267 = and(_T_265, _T_266)
node _T_268 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_269 = and(_T_267, _T_268)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_270 = shr(io.in.a.bits.source, 2)
node _T_271 = eq(_T_270, UInt<2>(0h3))
node _T_272 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_273 = and(_T_271, _T_272)
node _T_274 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_275 = and(_T_273, _T_274)
node _T_276 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_277 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_278 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_279 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_280 = or(_T_251, _T_257)
node _T_281 = or(_T_280, _T_263)
node _T_282 = or(_T_281, _T_269)
node _T_283 = or(_T_282, _T_275)
node _T_284 = or(_T_283, _T_276)
node _T_285 = or(_T_284, _T_277)
node _T_286 = or(_T_285, _T_278)
node _T_287 = or(_T_286, _T_279)
node _T_288 = and(_T_250, _T_287)
node _T_289 = or(UInt<1>(0h0), _T_288)
node _T_290 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_291 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_292 = cvt(_T_291)
node _T_293 = and(_T_292, asSInt(UInt<13>(0h1000)))
node _T_294 = asSInt(_T_293)
node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0)))
node _T_296 = and(_T_290, _T_295)
node _T_297 = or(UInt<1>(0h0), _T_296)
node _T_298 = and(_T_289, _T_297)
node _T_299 = asUInt(reset)
node _T_300 = eq(_T_299, UInt<1>(0h0))
when _T_300 :
node _T_301 = eq(_T_298, UInt<1>(0h0))
when _T_301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_298, UInt<1>(0h1), "") : assert_10
node _T_302 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_303 = shr(io.in.a.bits.source, 2)
node _T_304 = eq(_T_303, UInt<1>(0h0))
node _T_305 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_306 = and(_T_304, _T_305)
node _T_307 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_308 = and(_T_306, _T_307)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_309 = shr(io.in.a.bits.source, 2)
node _T_310 = eq(_T_309, UInt<1>(0h1))
node _T_311 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_312 = and(_T_310, _T_311)
node _T_313 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_314 = and(_T_312, _T_313)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_315 = shr(io.in.a.bits.source, 2)
node _T_316 = eq(_T_315, UInt<2>(0h2))
node _T_317 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_318 = and(_T_316, _T_317)
node _T_319 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_321 = shr(io.in.a.bits.source, 2)
node _T_322 = eq(_T_321, UInt<2>(0h3))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_326 = and(_T_324, _T_325)
node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_330 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE_2 : UInt<1>[9]
connect _WIRE_2[0], _T_302
connect _WIRE_2[1], _T_308
connect _WIRE_2[2], _T_314
connect _WIRE_2[3], _T_320
connect _WIRE_2[4], _T_326
connect _WIRE_2[5], _T_327
connect _WIRE_2[6], _T_328
connect _WIRE_2[7], _T_329
connect _WIRE_2[8], _T_330
node _T_331 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_332 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_333 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_334 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_335 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_336 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_337 = mux(_WIRE_2[5], _T_331, UInt<1>(0h0))
node _T_338 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_339 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_340 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_341 = or(_T_332, _T_333)
node _T_342 = or(_T_341, _T_334)
node _T_343 = or(_T_342, _T_335)
node _T_344 = or(_T_343, _T_336)
node _T_345 = or(_T_344, _T_337)
node _T_346 = or(_T_345, _T_338)
node _T_347 = or(_T_346, _T_339)
node _T_348 = or(_T_347, _T_340)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_348
node _T_349 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_350 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_351 = and(_T_349, _T_350)
node _T_352 = or(UInt<1>(0h0), _T_351)
node _T_353 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_354 = cvt(_T_353)
node _T_355 = and(_T_354, asSInt(UInt<13>(0h1000)))
node _T_356 = asSInt(_T_355)
node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0)))
node _T_358 = and(_T_352, _T_357)
node _T_359 = or(UInt<1>(0h0), _T_358)
node _T_360 = and(_WIRE_3, _T_359)
node _T_361 = asUInt(reset)
node _T_362 = eq(_T_361, UInt<1>(0h0))
when _T_362 :
node _T_363 = eq(_T_360, UInt<1>(0h0))
when _T_363 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_360, UInt<1>(0h1), "") : assert_11
node _T_364 = asUInt(reset)
node _T_365 = eq(_T_364, UInt<1>(0h0))
when _T_365 :
node _T_366 = eq(source_ok, UInt<1>(0h0))
when _T_366 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_367 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_368 = asUInt(reset)
node _T_369 = eq(_T_368, UInt<1>(0h0))
when _T_369 :
node _T_370 = eq(_T_367, UInt<1>(0h0))
when _T_370 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_367, UInt<1>(0h1), "") : assert_13
node _T_371 = asUInt(reset)
node _T_372 = eq(_T_371, UInt<1>(0h0))
when _T_372 :
node _T_373 = eq(is_aligned, UInt<1>(0h0))
when _T_373 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_374 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_375 = asUInt(reset)
node _T_376 = eq(_T_375, UInt<1>(0h0))
when _T_376 :
node _T_377 = eq(_T_374, UInt<1>(0h0))
when _T_377 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_374, UInt<1>(0h1), "") : assert_15
node _T_378 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_T_378, UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_378, UInt<1>(0h1), "") : assert_16
node _T_382 = not(io.in.a.bits.mask)
node _T_383 = eq(_T_382, UInt<1>(0h0))
node _T_384 = asUInt(reset)
node _T_385 = eq(_T_384, UInt<1>(0h0))
when _T_385 :
node _T_386 = eq(_T_383, UInt<1>(0h0))
when _T_386 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_383, UInt<1>(0h1), "") : assert_17
node _T_387 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(_T_387, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_387, UInt<1>(0h1), "") : assert_18
node _T_391 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_391 :
node _T_392 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_393 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_394 = and(_T_392, _T_393)
node _T_395 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_396 = shr(io.in.a.bits.source, 2)
node _T_397 = eq(_T_396, UInt<1>(0h0))
node _T_398 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_399 = and(_T_397, _T_398)
node _T_400 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_401 = and(_T_399, _T_400)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_402 = shr(io.in.a.bits.source, 2)
node _T_403 = eq(_T_402, UInt<1>(0h1))
node _T_404 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_405 = and(_T_403, _T_404)
node _T_406 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_407 = and(_T_405, _T_406)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_408 = shr(io.in.a.bits.source, 2)
node _T_409 = eq(_T_408, UInt<2>(0h2))
node _T_410 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_411 = and(_T_409, _T_410)
node _T_412 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_413 = and(_T_411, _T_412)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_414 = shr(io.in.a.bits.source, 2)
node _T_415 = eq(_T_414, UInt<2>(0h3))
node _T_416 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_417 = and(_T_415, _T_416)
node _T_418 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_419 = and(_T_417, _T_418)
node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_423 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_424 = or(_T_395, _T_401)
node _T_425 = or(_T_424, _T_407)
node _T_426 = or(_T_425, _T_413)
node _T_427 = or(_T_426, _T_419)
node _T_428 = or(_T_427, _T_420)
node _T_429 = or(_T_428, _T_421)
node _T_430 = or(_T_429, _T_422)
node _T_431 = or(_T_430, _T_423)
node _T_432 = and(_T_394, _T_431)
node _T_433 = or(UInt<1>(0h0), _T_432)
node _T_434 = asUInt(reset)
node _T_435 = eq(_T_434, UInt<1>(0h0))
when _T_435 :
node _T_436 = eq(_T_433, UInt<1>(0h0))
when _T_436 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_433, UInt<1>(0h1), "") : assert_19
node _T_437 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_438 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_439 = and(_T_437, _T_438)
node _T_440 = or(UInt<1>(0h0), _T_439)
node _T_441 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_442 = cvt(_T_441)
node _T_443 = and(_T_442, asSInt(UInt<13>(0h1000)))
node _T_444 = asSInt(_T_443)
node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0)))
node _T_446 = and(_T_440, _T_445)
node _T_447 = or(UInt<1>(0h0), _T_446)
node _T_448 = asUInt(reset)
node _T_449 = eq(_T_448, UInt<1>(0h0))
when _T_449 :
node _T_450 = eq(_T_447, UInt<1>(0h0))
when _T_450 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_447, UInt<1>(0h1), "") : assert_20
node _T_451 = asUInt(reset)
node _T_452 = eq(_T_451, UInt<1>(0h0))
when _T_452 :
node _T_453 = eq(source_ok, UInt<1>(0h0))
when _T_453 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_454 = asUInt(reset)
node _T_455 = eq(_T_454, UInt<1>(0h0))
when _T_455 :
node _T_456 = eq(is_aligned, UInt<1>(0h0))
when _T_456 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_457 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_458 = asUInt(reset)
node _T_459 = eq(_T_458, UInt<1>(0h0))
when _T_459 :
node _T_460 = eq(_T_457, UInt<1>(0h0))
when _T_460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_457, UInt<1>(0h1), "") : assert_23
node _T_461 = eq(io.in.a.bits.mask, mask)
node _T_462 = asUInt(reset)
node _T_463 = eq(_T_462, UInt<1>(0h0))
when _T_463 :
node _T_464 = eq(_T_461, UInt<1>(0h0))
when _T_464 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_461, UInt<1>(0h1), "") : assert_24
node _T_465 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_466 = asUInt(reset)
node _T_467 = eq(_T_466, UInt<1>(0h0))
when _T_467 :
node _T_468 = eq(_T_465, UInt<1>(0h0))
when _T_468 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_465, UInt<1>(0h1), "") : assert_25
node _T_469 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_469 :
node _T_470 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_471 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_472 = and(_T_470, _T_471)
node _T_473 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_474 = shr(io.in.a.bits.source, 2)
node _T_475 = eq(_T_474, UInt<1>(0h0))
node _T_476 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_477 = and(_T_475, _T_476)
node _T_478 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_479 = and(_T_477, _T_478)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_480 = shr(io.in.a.bits.source, 2)
node _T_481 = eq(_T_480, UInt<1>(0h1))
node _T_482 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_483 = and(_T_481, _T_482)
node _T_484 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_485 = and(_T_483, _T_484)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_486 = shr(io.in.a.bits.source, 2)
node _T_487 = eq(_T_486, UInt<2>(0h2))
node _T_488 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_489 = and(_T_487, _T_488)
node _T_490 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_491 = and(_T_489, _T_490)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_492 = shr(io.in.a.bits.source, 2)
node _T_493 = eq(_T_492, UInt<2>(0h3))
node _T_494 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_495 = and(_T_493, _T_494)
node _T_496 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_497 = and(_T_495, _T_496)
node _T_498 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_499 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_500 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_501 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_502 = or(_T_473, _T_479)
node _T_503 = or(_T_502, _T_485)
node _T_504 = or(_T_503, _T_491)
node _T_505 = or(_T_504, _T_497)
node _T_506 = or(_T_505, _T_498)
node _T_507 = or(_T_506, _T_499)
node _T_508 = or(_T_507, _T_500)
node _T_509 = or(_T_508, _T_501)
node _T_510 = and(_T_472, _T_509)
node _T_511 = or(UInt<1>(0h0), _T_510)
node _T_512 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_513 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_514 = and(_T_512, _T_513)
node _T_515 = or(UInt<1>(0h0), _T_514)
node _T_516 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_517 = cvt(_T_516)
node _T_518 = and(_T_517, asSInt(UInt<13>(0h1000)))
node _T_519 = asSInt(_T_518)
node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0)))
node _T_521 = and(_T_515, _T_520)
node _T_522 = or(UInt<1>(0h0), _T_521)
node _T_523 = and(_T_511, _T_522)
node _T_524 = asUInt(reset)
node _T_525 = eq(_T_524, UInt<1>(0h0))
when _T_525 :
node _T_526 = eq(_T_523, UInt<1>(0h0))
when _T_526 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_523, UInt<1>(0h1), "") : assert_26
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(source_ok, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_530 = asUInt(reset)
node _T_531 = eq(_T_530, UInt<1>(0h0))
when _T_531 :
node _T_532 = eq(is_aligned, UInt<1>(0h0))
when _T_532 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_533 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_534 = asUInt(reset)
node _T_535 = eq(_T_534, UInt<1>(0h0))
when _T_535 :
node _T_536 = eq(_T_533, UInt<1>(0h0))
when _T_536 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_533, UInt<1>(0h1), "") : assert_29
node _T_537 = eq(io.in.a.bits.mask, mask)
node _T_538 = asUInt(reset)
node _T_539 = eq(_T_538, UInt<1>(0h0))
when _T_539 :
node _T_540 = eq(_T_537, UInt<1>(0h0))
when _T_540 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_537, UInt<1>(0h1), "") : assert_30
node _T_541 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_541 :
node _T_542 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_543 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_544 = and(_T_542, _T_543)
node _T_545 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_546 = shr(io.in.a.bits.source, 2)
node _T_547 = eq(_T_546, UInt<1>(0h0))
node _T_548 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_549 = and(_T_547, _T_548)
node _T_550 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_551 = and(_T_549, _T_550)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_552 = shr(io.in.a.bits.source, 2)
node _T_553 = eq(_T_552, UInt<1>(0h1))
node _T_554 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_555 = and(_T_553, _T_554)
node _T_556 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_557 = and(_T_555, _T_556)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_558 = shr(io.in.a.bits.source, 2)
node _T_559 = eq(_T_558, UInt<2>(0h2))
node _T_560 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_561 = and(_T_559, _T_560)
node _T_562 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_563 = and(_T_561, _T_562)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_564 = shr(io.in.a.bits.source, 2)
node _T_565 = eq(_T_564, UInt<2>(0h3))
node _T_566 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_567 = and(_T_565, _T_566)
node _T_568 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_569 = and(_T_567, _T_568)
node _T_570 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_571 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_572 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_573 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_574 = or(_T_545, _T_551)
node _T_575 = or(_T_574, _T_557)
node _T_576 = or(_T_575, _T_563)
node _T_577 = or(_T_576, _T_569)
node _T_578 = or(_T_577, _T_570)
node _T_579 = or(_T_578, _T_571)
node _T_580 = or(_T_579, _T_572)
node _T_581 = or(_T_580, _T_573)
node _T_582 = and(_T_544, _T_581)
node _T_583 = or(UInt<1>(0h0), _T_582)
node _T_584 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_585 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_586 = and(_T_584, _T_585)
node _T_587 = or(UInt<1>(0h0), _T_586)
node _T_588 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_589 = cvt(_T_588)
node _T_590 = and(_T_589, asSInt(UInt<13>(0h1000)))
node _T_591 = asSInt(_T_590)
node _T_592 = eq(_T_591, asSInt(UInt<1>(0h0)))
node _T_593 = and(_T_587, _T_592)
node _T_594 = or(UInt<1>(0h0), _T_593)
node _T_595 = and(_T_583, _T_594)
node _T_596 = asUInt(reset)
node _T_597 = eq(_T_596, UInt<1>(0h0))
when _T_597 :
node _T_598 = eq(_T_595, UInt<1>(0h0))
when _T_598 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_595, UInt<1>(0h1), "") : assert_31
node _T_599 = asUInt(reset)
node _T_600 = eq(_T_599, UInt<1>(0h0))
when _T_600 :
node _T_601 = eq(source_ok, UInt<1>(0h0))
when _T_601 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(is_aligned, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_605 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_606 = asUInt(reset)
node _T_607 = eq(_T_606, UInt<1>(0h0))
when _T_607 :
node _T_608 = eq(_T_605, UInt<1>(0h0))
when _T_608 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_605, UInt<1>(0h1), "") : assert_34
node _T_609 = not(mask)
node _T_610 = and(io.in.a.bits.mask, _T_609)
node _T_611 = eq(_T_610, UInt<1>(0h0))
node _T_612 = asUInt(reset)
node _T_613 = eq(_T_612, UInt<1>(0h0))
when _T_613 :
node _T_614 = eq(_T_611, UInt<1>(0h0))
when _T_614 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_611, UInt<1>(0h1), "") : assert_35
node _T_615 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_615 :
node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_618 = and(_T_616, _T_617)
node _T_619 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_620 = shr(io.in.a.bits.source, 2)
node _T_621 = eq(_T_620, UInt<1>(0h0))
node _T_622 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_623 = and(_T_621, _T_622)
node _T_624 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_625 = and(_T_623, _T_624)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_626 = shr(io.in.a.bits.source, 2)
node _T_627 = eq(_T_626, UInt<1>(0h1))
node _T_628 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_629 = and(_T_627, _T_628)
node _T_630 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_631 = and(_T_629, _T_630)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_632 = shr(io.in.a.bits.source, 2)
node _T_633 = eq(_T_632, UInt<2>(0h2))
node _T_634 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_635 = and(_T_633, _T_634)
node _T_636 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_637 = and(_T_635, _T_636)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_638 = shr(io.in.a.bits.source, 2)
node _T_639 = eq(_T_638, UInt<2>(0h3))
node _T_640 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_641 = and(_T_639, _T_640)
node _T_642 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_643 = and(_T_641, _T_642)
node _T_644 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_645 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_646 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_647 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_648 = or(_T_619, _T_625)
node _T_649 = or(_T_648, _T_631)
node _T_650 = or(_T_649, _T_637)
node _T_651 = or(_T_650, _T_643)
node _T_652 = or(_T_651, _T_644)
node _T_653 = or(_T_652, _T_645)
node _T_654 = or(_T_653, _T_646)
node _T_655 = or(_T_654, _T_647)
node _T_656 = and(_T_618, _T_655)
node _T_657 = or(UInt<1>(0h0), _T_656)
node _T_658 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_659 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_660 = cvt(_T_659)
node _T_661 = and(_T_660, asSInt(UInt<13>(0h1000)))
node _T_662 = asSInt(_T_661)
node _T_663 = eq(_T_662, asSInt(UInt<1>(0h0)))
node _T_664 = and(_T_658, _T_663)
node _T_665 = or(UInt<1>(0h0), _T_664)
node _T_666 = and(_T_657, _T_665)
node _T_667 = asUInt(reset)
node _T_668 = eq(_T_667, UInt<1>(0h0))
when _T_668 :
node _T_669 = eq(_T_666, UInt<1>(0h0))
when _T_669 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_666, UInt<1>(0h1), "") : assert_36
node _T_670 = asUInt(reset)
node _T_671 = eq(_T_670, UInt<1>(0h0))
when _T_671 :
node _T_672 = eq(source_ok, UInt<1>(0h0))
when _T_672 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_673 = asUInt(reset)
node _T_674 = eq(_T_673, UInt<1>(0h0))
when _T_674 :
node _T_675 = eq(is_aligned, UInt<1>(0h0))
when _T_675 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_676 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_677 = asUInt(reset)
node _T_678 = eq(_T_677, UInt<1>(0h0))
when _T_678 :
node _T_679 = eq(_T_676, UInt<1>(0h0))
when _T_679 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_676, UInt<1>(0h1), "") : assert_39
node _T_680 = eq(io.in.a.bits.mask, mask)
node _T_681 = asUInt(reset)
node _T_682 = eq(_T_681, UInt<1>(0h0))
when _T_682 :
node _T_683 = eq(_T_680, UInt<1>(0h0))
when _T_683 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_680, UInt<1>(0h1), "") : assert_40
node _T_684 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_684 :
node _T_685 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_686 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_687 = and(_T_685, _T_686)
node _T_688 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_689 = shr(io.in.a.bits.source, 2)
node _T_690 = eq(_T_689, UInt<1>(0h0))
node _T_691 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_692 = and(_T_690, _T_691)
node _T_693 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_694 = and(_T_692, _T_693)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_695 = shr(io.in.a.bits.source, 2)
node _T_696 = eq(_T_695, UInt<1>(0h1))
node _T_697 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_698 = and(_T_696, _T_697)
node _T_699 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_700 = and(_T_698, _T_699)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_701 = shr(io.in.a.bits.source, 2)
node _T_702 = eq(_T_701, UInt<2>(0h2))
node _T_703 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_704 = and(_T_702, _T_703)
node _T_705 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_706 = and(_T_704, _T_705)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_707 = shr(io.in.a.bits.source, 2)
node _T_708 = eq(_T_707, UInt<2>(0h3))
node _T_709 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_710 = and(_T_708, _T_709)
node _T_711 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_712 = and(_T_710, _T_711)
node _T_713 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_714 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_715 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_716 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_717 = or(_T_688, _T_694)
node _T_718 = or(_T_717, _T_700)
node _T_719 = or(_T_718, _T_706)
node _T_720 = or(_T_719, _T_712)
node _T_721 = or(_T_720, _T_713)
node _T_722 = or(_T_721, _T_714)
node _T_723 = or(_T_722, _T_715)
node _T_724 = or(_T_723, _T_716)
node _T_725 = and(_T_687, _T_724)
node _T_726 = or(UInt<1>(0h0), _T_725)
node _T_727 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_728 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_729 = cvt(_T_728)
node _T_730 = and(_T_729, asSInt(UInt<13>(0h1000)))
node _T_731 = asSInt(_T_730)
node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0)))
node _T_733 = and(_T_727, _T_732)
node _T_734 = or(UInt<1>(0h0), _T_733)
node _T_735 = and(_T_726, _T_734)
node _T_736 = asUInt(reset)
node _T_737 = eq(_T_736, UInt<1>(0h0))
when _T_737 :
node _T_738 = eq(_T_735, UInt<1>(0h0))
when _T_738 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_735, UInt<1>(0h1), "") : assert_41
node _T_739 = asUInt(reset)
node _T_740 = eq(_T_739, UInt<1>(0h0))
when _T_740 :
node _T_741 = eq(source_ok, UInt<1>(0h0))
when _T_741 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_742 = asUInt(reset)
node _T_743 = eq(_T_742, UInt<1>(0h0))
when _T_743 :
node _T_744 = eq(is_aligned, UInt<1>(0h0))
when _T_744 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_745 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_746 = asUInt(reset)
node _T_747 = eq(_T_746, UInt<1>(0h0))
when _T_747 :
node _T_748 = eq(_T_745, UInt<1>(0h0))
when _T_748 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_745, UInt<1>(0h1), "") : assert_44
node _T_749 = eq(io.in.a.bits.mask, mask)
node _T_750 = asUInt(reset)
node _T_751 = eq(_T_750, UInt<1>(0h0))
when _T_751 :
node _T_752 = eq(_T_749, UInt<1>(0h0))
when _T_752 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_749, UInt<1>(0h1), "") : assert_45
node _T_753 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_753 :
node _T_754 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_755 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_756 = and(_T_754, _T_755)
node _T_757 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_758 = shr(io.in.a.bits.source, 2)
node _T_759 = eq(_T_758, UInt<1>(0h0))
node _T_760 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_761 = and(_T_759, _T_760)
node _T_762 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_763 = and(_T_761, _T_762)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_764 = shr(io.in.a.bits.source, 2)
node _T_765 = eq(_T_764, UInt<1>(0h1))
node _T_766 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_767 = and(_T_765, _T_766)
node _T_768 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_769 = and(_T_767, _T_768)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_770 = shr(io.in.a.bits.source, 2)
node _T_771 = eq(_T_770, UInt<2>(0h2))
node _T_772 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_773 = and(_T_771, _T_772)
node _T_774 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_775 = and(_T_773, _T_774)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_776 = shr(io.in.a.bits.source, 2)
node _T_777 = eq(_T_776, UInt<2>(0h3))
node _T_778 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_779 = and(_T_777, _T_778)
node _T_780 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_781 = and(_T_779, _T_780)
node _T_782 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_783 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_784 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_785 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_786 = or(_T_757, _T_763)
node _T_787 = or(_T_786, _T_769)
node _T_788 = or(_T_787, _T_775)
node _T_789 = or(_T_788, _T_781)
node _T_790 = or(_T_789, _T_782)
node _T_791 = or(_T_790, _T_783)
node _T_792 = or(_T_791, _T_784)
node _T_793 = or(_T_792, _T_785)
node _T_794 = and(_T_756, _T_793)
node _T_795 = or(UInt<1>(0h0), _T_794)
node _T_796 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_797 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_798 = cvt(_T_797)
node _T_799 = and(_T_798, asSInt(UInt<13>(0h1000)))
node _T_800 = asSInt(_T_799)
node _T_801 = eq(_T_800, asSInt(UInt<1>(0h0)))
node _T_802 = and(_T_796, _T_801)
node _T_803 = or(UInt<1>(0h0), _T_802)
node _T_804 = and(_T_795, _T_803)
node _T_805 = asUInt(reset)
node _T_806 = eq(_T_805, UInt<1>(0h0))
when _T_806 :
node _T_807 = eq(_T_804, UInt<1>(0h0))
when _T_807 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_804, UInt<1>(0h1), "") : assert_46
node _T_808 = asUInt(reset)
node _T_809 = eq(_T_808, UInt<1>(0h0))
when _T_809 :
node _T_810 = eq(source_ok, UInt<1>(0h0))
when _T_810 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_811 = asUInt(reset)
node _T_812 = eq(_T_811, UInt<1>(0h0))
when _T_812 :
node _T_813 = eq(is_aligned, UInt<1>(0h0))
when _T_813 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_814 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_815 = asUInt(reset)
node _T_816 = eq(_T_815, UInt<1>(0h0))
when _T_816 :
node _T_817 = eq(_T_814, UInt<1>(0h0))
when _T_817 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_814, UInt<1>(0h1), "") : assert_49
node _T_818 = eq(io.in.a.bits.mask, mask)
node _T_819 = asUInt(reset)
node _T_820 = eq(_T_819, UInt<1>(0h0))
when _T_820 :
node _T_821 = eq(_T_818, UInt<1>(0h0))
when _T_821 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_818, UInt<1>(0h1), "") : assert_50
node _T_822 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_823 = asUInt(reset)
node _T_824 = eq(_T_823, UInt<1>(0h0))
when _T_824 :
node _T_825 = eq(_T_822, UInt<1>(0h0))
when _T_825 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_822, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_826 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_827 = asUInt(reset)
node _T_828 = eq(_T_827, UInt<1>(0h0))
when _T_828 :
node _T_829 = eq(_T_826, UInt<1>(0h0))
when _T_829 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_826, UInt<1>(0h1), "") : assert_52
node _source_ok_T_36 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_37 = shr(io.in.d.bits.source, 2)
node _source_ok_T_38 = eq(_source_ok_T_37, UInt<1>(0h0))
node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39)
node _source_ok_T_41 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_43 = shr(io.in.d.bits.source, 2)
node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h1))
node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45)
node _source_ok_T_47 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_49 = shr(io.in.d.bits.source, 2)
node _source_ok_T_50 = eq(_source_ok_T_49, UInt<2>(0h2))
node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51)
node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_55 = shr(io.in.d.bits.source, 2)
node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h3))
node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57)
node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59)
node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_T_62 = eq(io.in.d.bits.source, UInt<6>(0h21))
node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<6>(0h22))
node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE_1 : UInt<1>[9]
connect _source_ok_WIRE_1[0], _source_ok_T_36
connect _source_ok_WIRE_1[1], _source_ok_T_42
connect _source_ok_WIRE_1[2], _source_ok_T_48
connect _source_ok_WIRE_1[3], _source_ok_T_54
connect _source_ok_WIRE_1[4], _source_ok_T_60
connect _source_ok_WIRE_1[5], _source_ok_T_61
connect _source_ok_WIRE_1[6], _source_ok_T_62
connect _source_ok_WIRE_1[7], _source_ok_T_63
connect _source_ok_WIRE_1[8], _source_ok_T_64
node _source_ok_T_65 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[2])
node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[3])
node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE_1[4])
node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[5])
node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[6])
node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[7])
node source_ok_1 = or(_source_ok_T_71, _source_ok_WIRE_1[8])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_830 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_830 :
node _T_831 = asUInt(reset)
node _T_832 = eq(_T_831, UInt<1>(0h0))
when _T_832 :
node _T_833 = eq(source_ok_1, UInt<1>(0h0))
when _T_833 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_834 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_835 = asUInt(reset)
node _T_836 = eq(_T_835, UInt<1>(0h0))
when _T_836 :
node _T_837 = eq(_T_834, UInt<1>(0h0))
when _T_837 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_834, UInt<1>(0h1), "") : assert_54
node _T_838 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_839 = asUInt(reset)
node _T_840 = eq(_T_839, UInt<1>(0h0))
when _T_840 :
node _T_841 = eq(_T_838, UInt<1>(0h0))
when _T_841 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_838, UInt<1>(0h1), "") : assert_55
node _T_842 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_843 = asUInt(reset)
node _T_844 = eq(_T_843, UInt<1>(0h0))
when _T_844 :
node _T_845 = eq(_T_842, UInt<1>(0h0))
when _T_845 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_842, UInt<1>(0h1), "") : assert_56
node _T_846 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_847 = asUInt(reset)
node _T_848 = eq(_T_847, UInt<1>(0h0))
when _T_848 :
node _T_849 = eq(_T_846, UInt<1>(0h0))
when _T_849 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_846, UInt<1>(0h1), "") : assert_57
node _T_850 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_850 :
node _T_851 = asUInt(reset)
node _T_852 = eq(_T_851, UInt<1>(0h0))
when _T_852 :
node _T_853 = eq(source_ok_1, UInt<1>(0h0))
when _T_853 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_854 = asUInt(reset)
node _T_855 = eq(_T_854, UInt<1>(0h0))
when _T_855 :
node _T_856 = eq(sink_ok, UInt<1>(0h0))
when _T_856 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_857 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_858 = asUInt(reset)
node _T_859 = eq(_T_858, UInt<1>(0h0))
when _T_859 :
node _T_860 = eq(_T_857, UInt<1>(0h0))
when _T_860 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_857, UInt<1>(0h1), "") : assert_60
node _T_861 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_862 = asUInt(reset)
node _T_863 = eq(_T_862, UInt<1>(0h0))
when _T_863 :
node _T_864 = eq(_T_861, UInt<1>(0h0))
when _T_864 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_861, UInt<1>(0h1), "") : assert_61
node _T_865 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_866 = asUInt(reset)
node _T_867 = eq(_T_866, UInt<1>(0h0))
when _T_867 :
node _T_868 = eq(_T_865, UInt<1>(0h0))
when _T_868 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_865, UInt<1>(0h1), "") : assert_62
node _T_869 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_870 = asUInt(reset)
node _T_871 = eq(_T_870, UInt<1>(0h0))
when _T_871 :
node _T_872 = eq(_T_869, UInt<1>(0h0))
when _T_872 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_869, UInt<1>(0h1), "") : assert_63
node _T_873 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_874 = or(UInt<1>(0h0), _T_873)
node _T_875 = asUInt(reset)
node _T_876 = eq(_T_875, UInt<1>(0h0))
when _T_876 :
node _T_877 = eq(_T_874, UInt<1>(0h0))
when _T_877 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_874, UInt<1>(0h1), "") : assert_64
node _T_878 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_878 :
node _T_879 = asUInt(reset)
node _T_880 = eq(_T_879, UInt<1>(0h0))
when _T_880 :
node _T_881 = eq(source_ok_1, UInt<1>(0h0))
when _T_881 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_882 = asUInt(reset)
node _T_883 = eq(_T_882, UInt<1>(0h0))
when _T_883 :
node _T_884 = eq(sink_ok, UInt<1>(0h0))
when _T_884 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_885 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_886 = asUInt(reset)
node _T_887 = eq(_T_886, UInt<1>(0h0))
when _T_887 :
node _T_888 = eq(_T_885, UInt<1>(0h0))
when _T_888 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_885, UInt<1>(0h1), "") : assert_67
node _T_889 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_890 = asUInt(reset)
node _T_891 = eq(_T_890, UInt<1>(0h0))
when _T_891 :
node _T_892 = eq(_T_889, UInt<1>(0h0))
when _T_892 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_889, UInt<1>(0h1), "") : assert_68
node _T_893 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_894 = asUInt(reset)
node _T_895 = eq(_T_894, UInt<1>(0h0))
when _T_895 :
node _T_896 = eq(_T_893, UInt<1>(0h0))
when _T_896 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_893, UInt<1>(0h1), "") : assert_69
node _T_897 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_898 = or(_T_897, io.in.d.bits.corrupt)
node _T_899 = asUInt(reset)
node _T_900 = eq(_T_899, UInt<1>(0h0))
when _T_900 :
node _T_901 = eq(_T_898, UInt<1>(0h0))
when _T_901 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_898, UInt<1>(0h1), "") : assert_70
node _T_902 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_903 = or(UInt<1>(0h0), _T_902)
node _T_904 = asUInt(reset)
node _T_905 = eq(_T_904, UInt<1>(0h0))
when _T_905 :
node _T_906 = eq(_T_903, UInt<1>(0h0))
when _T_906 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_903, UInt<1>(0h1), "") : assert_71
node _T_907 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_907 :
node _T_908 = asUInt(reset)
node _T_909 = eq(_T_908, UInt<1>(0h0))
when _T_909 :
node _T_910 = eq(source_ok_1, UInt<1>(0h0))
when _T_910 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_911 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_912 = asUInt(reset)
node _T_913 = eq(_T_912, UInt<1>(0h0))
when _T_913 :
node _T_914 = eq(_T_911, UInt<1>(0h0))
when _T_914 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_911, UInt<1>(0h1), "") : assert_73
node _T_915 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_916 = asUInt(reset)
node _T_917 = eq(_T_916, UInt<1>(0h0))
when _T_917 :
node _T_918 = eq(_T_915, UInt<1>(0h0))
when _T_918 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_915, UInt<1>(0h1), "") : assert_74
node _T_919 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_920 = or(UInt<1>(0h0), _T_919)
node _T_921 = asUInt(reset)
node _T_922 = eq(_T_921, UInt<1>(0h0))
when _T_922 :
node _T_923 = eq(_T_920, UInt<1>(0h0))
when _T_923 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_920, UInt<1>(0h1), "") : assert_75
node _T_924 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_924 :
node _T_925 = asUInt(reset)
node _T_926 = eq(_T_925, UInt<1>(0h0))
when _T_926 :
node _T_927 = eq(source_ok_1, UInt<1>(0h0))
when _T_927 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_928 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_929 = asUInt(reset)
node _T_930 = eq(_T_929, UInt<1>(0h0))
when _T_930 :
node _T_931 = eq(_T_928, UInt<1>(0h0))
when _T_931 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_928, UInt<1>(0h1), "") : assert_77
node _T_932 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_933 = or(_T_932, io.in.d.bits.corrupt)
node _T_934 = asUInt(reset)
node _T_935 = eq(_T_934, UInt<1>(0h0))
when _T_935 :
node _T_936 = eq(_T_933, UInt<1>(0h0))
when _T_936 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_933, UInt<1>(0h1), "") : assert_78
node _T_937 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_938 = or(UInt<1>(0h0), _T_937)
node _T_939 = asUInt(reset)
node _T_940 = eq(_T_939, UInt<1>(0h0))
when _T_940 :
node _T_941 = eq(_T_938, UInt<1>(0h0))
when _T_941 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_938, UInt<1>(0h1), "") : assert_79
node _T_942 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_942 :
node _T_943 = asUInt(reset)
node _T_944 = eq(_T_943, UInt<1>(0h0))
when _T_944 :
node _T_945 = eq(source_ok_1, UInt<1>(0h0))
when _T_945 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_946 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_947 = asUInt(reset)
node _T_948 = eq(_T_947, UInt<1>(0h0))
when _T_948 :
node _T_949 = eq(_T_946, UInt<1>(0h0))
when _T_949 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_946, UInt<1>(0h1), "") : assert_81
node _T_950 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_951 = asUInt(reset)
node _T_952 = eq(_T_951, UInt<1>(0h0))
when _T_952 :
node _T_953 = eq(_T_950, UInt<1>(0h0))
when _T_953 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_950, UInt<1>(0h1), "") : assert_82
node _T_954 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_955 = or(UInt<1>(0h0), _T_954)
node _T_956 = asUInt(reset)
node _T_957 = eq(_T_956, UInt<1>(0h0))
when _T_957 :
node _T_958 = eq(_T_955, UInt<1>(0h0))
when _T_958 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_955, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<12>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_959 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_960 = asUInt(reset)
node _T_961 = eq(_T_960, UInt<1>(0h0))
when _T_961 :
node _T_962 = eq(_T_959, UInt<1>(0h0))
when _T_962 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_959, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<12>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_963 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_964 = asUInt(reset)
node _T_965 = eq(_T_964, UInt<1>(0h0))
when _T_965 :
node _T_966 = eq(_T_963, UInt<1>(0h0))
when _T_966 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_963, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_967 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_968 = asUInt(reset)
node _T_969 = eq(_T_968, UInt<1>(0h0))
when _T_969 :
node _T_970 = eq(_T_967, UInt<1>(0h0))
when _T_970 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_967, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_971 = eq(a_first, UInt<1>(0h0))
node _T_972 = and(io.in.a.valid, _T_971)
when _T_972 :
node _T_973 = eq(io.in.a.bits.opcode, opcode)
node _T_974 = asUInt(reset)
node _T_975 = eq(_T_974, UInt<1>(0h0))
when _T_975 :
node _T_976 = eq(_T_973, UInt<1>(0h0))
when _T_976 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_973, UInt<1>(0h1), "") : assert_87
node _T_977 = eq(io.in.a.bits.param, param)
node _T_978 = asUInt(reset)
node _T_979 = eq(_T_978, UInt<1>(0h0))
when _T_979 :
node _T_980 = eq(_T_977, UInt<1>(0h0))
when _T_980 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_977, UInt<1>(0h1), "") : assert_88
node _T_981 = eq(io.in.a.bits.size, size)
node _T_982 = asUInt(reset)
node _T_983 = eq(_T_982, UInt<1>(0h0))
when _T_983 :
node _T_984 = eq(_T_981, UInt<1>(0h0))
when _T_984 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_981, UInt<1>(0h1), "") : assert_89
node _T_985 = eq(io.in.a.bits.source, source)
node _T_986 = asUInt(reset)
node _T_987 = eq(_T_986, UInt<1>(0h0))
when _T_987 :
node _T_988 = eq(_T_985, UInt<1>(0h0))
when _T_988 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_985, UInt<1>(0h1), "") : assert_90
node _T_989 = eq(io.in.a.bits.address, address)
node _T_990 = asUInt(reset)
node _T_991 = eq(_T_990, UInt<1>(0h0))
when _T_991 :
node _T_992 = eq(_T_989, UInt<1>(0h0))
when _T_992 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_989, UInt<1>(0h1), "") : assert_91
node _T_993 = and(io.in.a.ready, io.in.a.valid)
node _T_994 = and(_T_993, a_first)
when _T_994 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_995 = eq(d_first, UInt<1>(0h0))
node _T_996 = and(io.in.d.valid, _T_995)
when _T_996 :
node _T_997 = eq(io.in.d.bits.opcode, opcode_1)
node _T_998 = asUInt(reset)
node _T_999 = eq(_T_998, UInt<1>(0h0))
when _T_999 :
node _T_1000 = eq(_T_997, UInt<1>(0h0))
when _T_1000 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_997, UInt<1>(0h1), "") : assert_92
node _T_1001 = eq(io.in.d.bits.param, param_1)
node _T_1002 = asUInt(reset)
node _T_1003 = eq(_T_1002, UInt<1>(0h0))
when _T_1003 :
node _T_1004 = eq(_T_1001, UInt<1>(0h0))
when _T_1004 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1001, UInt<1>(0h1), "") : assert_93
node _T_1005 = eq(io.in.d.bits.size, size_1)
node _T_1006 = asUInt(reset)
node _T_1007 = eq(_T_1006, UInt<1>(0h0))
when _T_1007 :
node _T_1008 = eq(_T_1005, UInt<1>(0h0))
when _T_1008 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1005, UInt<1>(0h1), "") : assert_94
node _T_1009 = eq(io.in.d.bits.source, source_1)
node _T_1010 = asUInt(reset)
node _T_1011 = eq(_T_1010, UInt<1>(0h0))
when _T_1011 :
node _T_1012 = eq(_T_1009, UInt<1>(0h0))
when _T_1012 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1009, UInt<1>(0h1), "") : assert_95
node _T_1013 = eq(io.in.d.bits.sink, sink)
node _T_1014 = asUInt(reset)
node _T_1015 = eq(_T_1014, UInt<1>(0h0))
when _T_1015 :
node _T_1016 = eq(_T_1013, UInt<1>(0h0))
when _T_1016 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1013, UInt<1>(0h1), "") : assert_96
node _T_1017 = eq(io.in.d.bits.denied, denied)
node _T_1018 = asUInt(reset)
node _T_1019 = eq(_T_1018, UInt<1>(0h0))
when _T_1019 :
node _T_1020 = eq(_T_1017, UInt<1>(0h0))
when _T_1020 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1017, UInt<1>(0h1), "") : assert_97
node _T_1021 = and(io.in.d.ready, io.in.d.valid)
node _T_1022 = and(_T_1021, d_first)
when _T_1022 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<65>
connect a_set, UInt<65>(0h0)
wire a_set_wo_ready : UInt<65>
connect a_set_wo_ready, UInt<65>(0h0)
wire a_opcodes_set : UInt<260>
connect a_opcodes_set, UInt<260>(0h0)
wire a_sizes_set : UInt<260>
connect a_sizes_set, UInt<260>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1023 = and(io.in.a.valid, a_first_1)
node _T_1024 = and(_T_1023, UInt<1>(0h1))
when _T_1024 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1025 = and(io.in.a.ready, io.in.a.valid)
node _T_1026 = and(_T_1025, a_first_1)
node _T_1027 = and(_T_1026, UInt<1>(0h1))
when _T_1027 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1028 = dshr(inflight, io.in.a.bits.source)
node _T_1029 = bits(_T_1028, 0, 0)
node _T_1030 = eq(_T_1029, UInt<1>(0h0))
node _T_1031 = asUInt(reset)
node _T_1032 = eq(_T_1031, UInt<1>(0h0))
when _T_1032 :
node _T_1033 = eq(_T_1030, UInt<1>(0h0))
when _T_1033 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1030, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<65>
connect d_clr, UInt<65>(0h0)
wire d_clr_wo_ready : UInt<65>
connect d_clr_wo_ready, UInt<65>(0h0)
wire d_opcodes_clr : UInt<260>
connect d_opcodes_clr, UInt<260>(0h0)
wire d_sizes_clr : UInt<260>
connect d_sizes_clr, UInt<260>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1034 = and(io.in.d.valid, d_first_1)
node _T_1035 = and(_T_1034, UInt<1>(0h1))
node _T_1036 = eq(d_release_ack, UInt<1>(0h0))
node _T_1037 = and(_T_1035, _T_1036)
when _T_1037 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1038 = and(io.in.d.ready, io.in.d.valid)
node _T_1039 = and(_T_1038, d_first_1)
node _T_1040 = and(_T_1039, UInt<1>(0h1))
node _T_1041 = eq(d_release_ack, UInt<1>(0h0))
node _T_1042 = and(_T_1040, _T_1041)
when _T_1042 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1043 = and(io.in.d.valid, d_first_1)
node _T_1044 = and(_T_1043, UInt<1>(0h1))
node _T_1045 = eq(d_release_ack, UInt<1>(0h0))
node _T_1046 = and(_T_1044, _T_1045)
when _T_1046 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1047 = dshr(inflight, io.in.d.bits.source)
node _T_1048 = bits(_T_1047, 0, 0)
node _T_1049 = or(_T_1048, same_cycle_resp)
node _T_1050 = asUInt(reset)
node _T_1051 = eq(_T_1050, UInt<1>(0h0))
when _T_1051 :
node _T_1052 = eq(_T_1049, UInt<1>(0h0))
when _T_1052 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1049, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1053 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1054 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1055 = or(_T_1053, _T_1054)
node _T_1056 = asUInt(reset)
node _T_1057 = eq(_T_1056, UInt<1>(0h0))
when _T_1057 :
node _T_1058 = eq(_T_1055, UInt<1>(0h0))
when _T_1058 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1055, UInt<1>(0h1), "") : assert_100
node _T_1059 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1060 = asUInt(reset)
node _T_1061 = eq(_T_1060, UInt<1>(0h0))
when _T_1061 :
node _T_1062 = eq(_T_1059, UInt<1>(0h0))
when _T_1062 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1059, UInt<1>(0h1), "") : assert_101
else :
node _T_1063 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1064 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1065 = or(_T_1063, _T_1064)
node _T_1066 = asUInt(reset)
node _T_1067 = eq(_T_1066, UInt<1>(0h0))
when _T_1067 :
node _T_1068 = eq(_T_1065, UInt<1>(0h0))
when _T_1068 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1065, UInt<1>(0h1), "") : assert_102
node _T_1069 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1070 = asUInt(reset)
node _T_1071 = eq(_T_1070, UInt<1>(0h0))
when _T_1071 :
node _T_1072 = eq(_T_1069, UInt<1>(0h0))
when _T_1072 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1069, UInt<1>(0h1), "") : assert_103
node _T_1073 = and(io.in.d.valid, d_first_1)
node _T_1074 = and(_T_1073, a_first_1)
node _T_1075 = and(_T_1074, io.in.a.valid)
node _T_1076 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1077 = and(_T_1075, _T_1076)
node _T_1078 = eq(d_release_ack, UInt<1>(0h0))
node _T_1079 = and(_T_1077, _T_1078)
when _T_1079 :
node _T_1080 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1081 = or(_T_1080, io.in.a.ready)
node _T_1082 = asUInt(reset)
node _T_1083 = eq(_T_1082, UInt<1>(0h0))
when _T_1083 :
node _T_1084 = eq(_T_1081, UInt<1>(0h0))
when _T_1084 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1081, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_50
node _T_1085 = orr(inflight)
node _T_1086 = eq(_T_1085, UInt<1>(0h0))
node _T_1087 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1088 = or(_T_1086, _T_1087)
node _T_1089 = lt(watchdog, plusarg_reader.out)
node _T_1090 = or(_T_1088, _T_1089)
node _T_1091 = asUInt(reset)
node _T_1092 = eq(_T_1091, UInt<1>(0h0))
when _T_1092 :
node _T_1093 = eq(_T_1090, UInt<1>(0h0))
when _T_1093 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1090, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1094 = and(io.in.a.ready, io.in.a.valid)
node _T_1095 = and(io.in.d.ready, io.in.d.valid)
node _T_1096 = or(_T_1094, _T_1095)
when _T_1096 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<12>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<12>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<65>
connect c_set, UInt<65>(0h0)
wire c_set_wo_ready : UInt<65>
connect c_set_wo_ready, UInt<65>(0h0)
wire c_opcodes_set : UInt<260>
connect c_opcodes_set, UInt<260>(0h0)
wire c_sizes_set : UInt<260>
connect c_sizes_set, UInt<260>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<12>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1097 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<12>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1098 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1099 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1100 = and(_T_1098, _T_1099)
node _T_1101 = and(_T_1097, _T_1100)
when _T_1101 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<12>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<12>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1102 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1103 = and(_T_1102, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<12>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1104 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1105 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1106 = and(_T_1104, _T_1105)
node _T_1107 = and(_T_1103, _T_1106)
when _T_1107 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<12>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<12>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<12>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<12>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<12>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<12>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1108 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1109 = bits(_T_1108, 0, 0)
node _T_1110 = eq(_T_1109, UInt<1>(0h0))
node _T_1111 = asUInt(reset)
node _T_1112 = eq(_T_1111, UInt<1>(0h0))
when _T_1112 :
node _T_1113 = eq(_T_1110, UInt<1>(0h0))
when _T_1113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1110, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<12>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<12>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<65>
connect d_clr_1, UInt<65>(0h0)
wire d_clr_wo_ready_1 : UInt<65>
connect d_clr_wo_ready_1, UInt<65>(0h0)
wire d_opcodes_clr_1 : UInt<260>
connect d_opcodes_clr_1, UInt<260>(0h0)
wire d_sizes_clr_1 : UInt<260>
connect d_sizes_clr_1, UInt<260>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1114 = and(io.in.d.valid, d_first_2)
node _T_1115 = and(_T_1114, UInt<1>(0h1))
node _T_1116 = and(_T_1115, d_release_ack_1)
when _T_1116 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1117 = and(io.in.d.ready, io.in.d.valid)
node _T_1118 = and(_T_1117, d_first_2)
node _T_1119 = and(_T_1118, UInt<1>(0h1))
node _T_1120 = and(_T_1119, d_release_ack_1)
when _T_1120 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1121 = and(io.in.d.valid, d_first_2)
node _T_1122 = and(_T_1121, UInt<1>(0h1))
node _T_1123 = and(_T_1122, d_release_ack_1)
when _T_1123 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<12>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<12>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<12>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1124 = dshr(inflight_1, io.in.d.bits.source)
node _T_1125 = bits(_T_1124, 0, 0)
node _T_1126 = or(_T_1125, same_cycle_resp_1)
node _T_1127 = asUInt(reset)
node _T_1128 = eq(_T_1127, UInt<1>(0h0))
when _T_1128 :
node _T_1129 = eq(_T_1126, UInt<1>(0h0))
when _T_1129 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_1126, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<12>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1130 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1131 = asUInt(reset)
node _T_1132 = eq(_T_1131, UInt<1>(0h0))
when _T_1132 :
node _T_1133 = eq(_T_1130, UInt<1>(0h0))
when _T_1133 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1130, UInt<1>(0h1), "") : assert_108
else :
node _T_1134 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1135 = asUInt(reset)
node _T_1136 = eq(_T_1135, UInt<1>(0h0))
when _T_1136 :
node _T_1137 = eq(_T_1134, UInt<1>(0h0))
when _T_1137 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1134, UInt<1>(0h1), "") : assert_109
node _T_1138 = and(io.in.d.valid, d_first_2)
node _T_1139 = and(_T_1138, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<12>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1140 = and(_T_1139, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<12>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1141 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1142 = and(_T_1140, _T_1141)
node _T_1143 = and(_T_1142, d_release_ack_1)
node _T_1144 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1145 = and(_T_1143, _T_1144)
when _T_1145 :
node _T_1146 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<12>(0h0)
connect _WIRE_26.bits.source, UInt<7>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1147 = or(_T_1146, _WIRE_27.ready)
node _T_1148 = asUInt(reset)
node _T_1149 = eq(_T_1148, UInt<1>(0h0))
when _T_1149 :
node _T_1150 = eq(_T_1147, UInt<1>(0h0))
when _T_1150 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1147, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_51
node _T_1151 = orr(inflight_1)
node _T_1152 = eq(_T_1151, UInt<1>(0h0))
node _T_1153 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1154 = or(_T_1152, _T_1153)
node _T_1155 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1156 = or(_T_1154, _T_1155)
node _T_1157 = asUInt(reset)
node _T_1158 = eq(_T_1157, UInt<1>(0h0))
when _T_1158 :
node _T_1159 = eq(_T_1156, UInt<1>(0h0))
when _T_1159 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1156, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<12>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1160 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1161 = and(io.in.d.ready, io.in.d.valid)
node _T_1162 = or(_T_1160, _T_1161)
when _T_1162 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_25( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [11:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_2 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE : UInt<1>[9]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
connect _source_ok_WIRE[7], _source_ok_T_27
connect _source_ok_WIRE[8], _source_ok_T_28
node _source_ok_T_29 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[2])
node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[3])
node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[4])
node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[5])
node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[6])
node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[7])
node source_ok = or(_source_ok_T_35, _source_ok_WIRE[8])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_81 = eq(_T_80, UInt<1>(0h0))
node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_83 = cvt(_T_82)
node _T_84 = and(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = asSInt(_T_84)
node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = or(_T_81, _T_86)
node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_89 = eq(_T_88, UInt<1>(0h0))
node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<1>(0h0)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_89, _T_94)
node _T_96 = and(_T_11, _T_24)
node _T_97 = and(_T_96, _T_37)
node _T_98 = and(_T_97, _T_50)
node _T_99 = and(_T_98, _T_63)
node _T_100 = and(_T_99, _T_71)
node _T_101 = and(_T_100, _T_79)
node _T_102 = and(_T_101, _T_87)
node _T_103 = and(_T_102, _T_95)
node _T_104 = asUInt(reset)
node _T_105 = eq(_T_104, UInt<1>(0h0))
when _T_105 :
node _T_106 = eq(_T_103, UInt<1>(0h0))
when _T_106 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_103, UInt<1>(0h1), "") : assert_1
node _T_107 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_107 :
node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_112 = shr(io.in.a.bits.source, 2)
node _T_113 = eq(_T_112, UInt<1>(0h0))
node _T_114 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_115 = and(_T_113, _T_114)
node _T_116 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_117 = and(_T_115, _T_116)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_118 = shr(io.in.a.bits.source, 2)
node _T_119 = eq(_T_118, UInt<1>(0h1))
node _T_120 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_121 = and(_T_119, _T_120)
node _T_122 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_123 = and(_T_121, _T_122)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_124 = shr(io.in.a.bits.source, 2)
node _T_125 = eq(_T_124, UInt<2>(0h2))
node _T_126 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_127 = and(_T_125, _T_126)
node _T_128 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_129 = and(_T_127, _T_128)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_130 = shr(io.in.a.bits.source, 2)
node _T_131 = eq(_T_130, UInt<2>(0h3))
node _T_132 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_133 = and(_T_131, _T_132)
node _T_134 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_135 = and(_T_133, _T_134)
node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_137 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_140 = or(_T_111, _T_117)
node _T_141 = or(_T_140, _T_123)
node _T_142 = or(_T_141, _T_129)
node _T_143 = or(_T_142, _T_135)
node _T_144 = or(_T_143, _T_136)
node _T_145 = or(_T_144, _T_137)
node _T_146 = or(_T_145, _T_138)
node _T_147 = or(_T_146, _T_139)
node _T_148 = and(_T_110, _T_147)
node _T_149 = or(UInt<1>(0h0), _T_148)
node _T_150 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_151 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_152 = cvt(_T_151)
node _T_153 = and(_T_152, asSInt(UInt<13>(0h1000)))
node _T_154 = asSInt(_T_153)
node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0)))
node _T_156 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_157 = cvt(_T_156)
node _T_158 = and(_T_157, asSInt(UInt<13>(0h1000)))
node _T_159 = asSInt(_T_158)
node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0)))
node _T_161 = or(_T_155, _T_160)
node _T_162 = and(_T_150, _T_161)
node _T_163 = or(UInt<1>(0h0), _T_162)
node _T_164 = and(_T_149, _T_163)
node _T_165 = asUInt(reset)
node _T_166 = eq(_T_165, UInt<1>(0h0))
when _T_166 :
node _T_167 = eq(_T_164, UInt<1>(0h0))
when _T_167 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_164, UInt<1>(0h1), "") : assert_2
node _T_168 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_169 = shr(io.in.a.bits.source, 2)
node _T_170 = eq(_T_169, UInt<1>(0h0))
node _T_171 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_172 = and(_T_170, _T_171)
node _T_173 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_174 = and(_T_172, _T_173)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_175 = shr(io.in.a.bits.source, 2)
node _T_176 = eq(_T_175, UInt<1>(0h1))
node _T_177 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_178 = and(_T_176, _T_177)
node _T_179 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_180 = and(_T_178, _T_179)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_181 = shr(io.in.a.bits.source, 2)
node _T_182 = eq(_T_181, UInt<2>(0h2))
node _T_183 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_184 = and(_T_182, _T_183)
node _T_185 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_186 = and(_T_184, _T_185)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_187 = shr(io.in.a.bits.source, 2)
node _T_188 = eq(_T_187, UInt<2>(0h3))
node _T_189 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_190 = and(_T_188, _T_189)
node _T_191 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_192 = and(_T_190, _T_191)
node _T_193 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_194 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_195 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_196 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE : UInt<1>[9]
connect _WIRE[0], _T_168
connect _WIRE[1], _T_174
connect _WIRE[2], _T_180
connect _WIRE[3], _T_186
connect _WIRE[4], _T_192
connect _WIRE[5], _T_193
connect _WIRE[6], _T_194
connect _WIRE[7], _T_195
connect _WIRE[8], _T_196
node _T_197 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_198 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_199 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_200 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_201 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_202 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_203 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_204 = mux(_WIRE[6], _T_197, UInt<1>(0h0))
node _T_205 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_206 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_207 = or(_T_198, _T_199)
node _T_208 = or(_T_207, _T_200)
node _T_209 = or(_T_208, _T_201)
node _T_210 = or(_T_209, _T_202)
node _T_211 = or(_T_210, _T_203)
node _T_212 = or(_T_211, _T_204)
node _T_213 = or(_T_212, _T_205)
node _T_214 = or(_T_213, _T_206)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_214
node _T_215 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_216 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_217 = and(_T_215, _T_216)
node _T_218 = or(UInt<1>(0h0), _T_217)
node _T_219 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_220 = cvt(_T_219)
node _T_221 = and(_T_220, asSInt(UInt<13>(0h1000)))
node _T_222 = asSInt(_T_221)
node _T_223 = eq(_T_222, asSInt(UInt<1>(0h0)))
node _T_224 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_225 = cvt(_T_224)
node _T_226 = and(_T_225, asSInt(UInt<13>(0h1000)))
node _T_227 = asSInt(_T_226)
node _T_228 = eq(_T_227, asSInt(UInt<1>(0h0)))
node _T_229 = or(_T_223, _T_228)
node _T_230 = and(_T_218, _T_229)
node _T_231 = or(UInt<1>(0h0), _T_230)
node _T_232 = and(_WIRE_1, _T_231)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_232, UInt<1>(0h1), "") : assert_3
node _T_236 = asUInt(reset)
node _T_237 = eq(_T_236, UInt<1>(0h0))
when _T_237 :
node _T_238 = eq(source_ok, UInt<1>(0h0))
when _T_238 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_239 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_239, UInt<1>(0h1), "") : assert_5
node _T_243 = asUInt(reset)
node _T_244 = eq(_T_243, UInt<1>(0h0))
when _T_244 :
node _T_245 = eq(is_aligned, UInt<1>(0h0))
when _T_245 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_246 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_247 = asUInt(reset)
node _T_248 = eq(_T_247, UInt<1>(0h0))
when _T_248 :
node _T_249 = eq(_T_246, UInt<1>(0h0))
when _T_249 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_246, UInt<1>(0h1), "") : assert_7
node _T_250 = not(io.in.a.bits.mask)
node _T_251 = eq(_T_250, UInt<1>(0h0))
node _T_252 = asUInt(reset)
node _T_253 = eq(_T_252, UInt<1>(0h0))
when _T_253 :
node _T_254 = eq(_T_251, UInt<1>(0h0))
when _T_254 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_251, UInt<1>(0h1), "") : assert_8
node _T_255 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_256 = asUInt(reset)
node _T_257 = eq(_T_256, UInt<1>(0h0))
when _T_257 :
node _T_258 = eq(_T_255, UInt<1>(0h0))
when _T_258 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_255, UInt<1>(0h1), "") : assert_9
node _T_259 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_259 :
node _T_260 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_261 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_262 = and(_T_260, _T_261)
node _T_263 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_264 = shr(io.in.a.bits.source, 2)
node _T_265 = eq(_T_264, UInt<1>(0h0))
node _T_266 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_267 = and(_T_265, _T_266)
node _T_268 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_269 = and(_T_267, _T_268)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_270 = shr(io.in.a.bits.source, 2)
node _T_271 = eq(_T_270, UInt<1>(0h1))
node _T_272 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_273 = and(_T_271, _T_272)
node _T_274 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_275 = and(_T_273, _T_274)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_276 = shr(io.in.a.bits.source, 2)
node _T_277 = eq(_T_276, UInt<2>(0h2))
node _T_278 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_279 = and(_T_277, _T_278)
node _T_280 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_281 = and(_T_279, _T_280)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_282 = shr(io.in.a.bits.source, 2)
node _T_283 = eq(_T_282, UInt<2>(0h3))
node _T_284 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_285 = and(_T_283, _T_284)
node _T_286 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_287 = and(_T_285, _T_286)
node _T_288 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_289 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_290 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_291 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_292 = or(_T_263, _T_269)
node _T_293 = or(_T_292, _T_275)
node _T_294 = or(_T_293, _T_281)
node _T_295 = or(_T_294, _T_287)
node _T_296 = or(_T_295, _T_288)
node _T_297 = or(_T_296, _T_289)
node _T_298 = or(_T_297, _T_290)
node _T_299 = or(_T_298, _T_291)
node _T_300 = and(_T_262, _T_299)
node _T_301 = or(UInt<1>(0h0), _T_300)
node _T_302 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_303 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_304 = cvt(_T_303)
node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000)))
node _T_306 = asSInt(_T_305)
node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0)))
node _T_308 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_309 = cvt(_T_308)
node _T_310 = and(_T_309, asSInt(UInt<13>(0h1000)))
node _T_311 = asSInt(_T_310)
node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0)))
node _T_313 = or(_T_307, _T_312)
node _T_314 = and(_T_302, _T_313)
node _T_315 = or(UInt<1>(0h0), _T_314)
node _T_316 = and(_T_301, _T_315)
node _T_317 = asUInt(reset)
node _T_318 = eq(_T_317, UInt<1>(0h0))
when _T_318 :
node _T_319 = eq(_T_316, UInt<1>(0h0))
when _T_319 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_316, UInt<1>(0h1), "") : assert_10
node _T_320 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_321 = shr(io.in.a.bits.source, 2)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_326 = and(_T_324, _T_325)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_327 = shr(io.in.a.bits.source, 2)
node _T_328 = eq(_T_327, UInt<1>(0h1))
node _T_329 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_330 = and(_T_328, _T_329)
node _T_331 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_332 = and(_T_330, _T_331)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_333 = shr(io.in.a.bits.source, 2)
node _T_334 = eq(_T_333, UInt<2>(0h2))
node _T_335 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_336 = and(_T_334, _T_335)
node _T_337 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_338 = and(_T_336, _T_337)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_339 = shr(io.in.a.bits.source, 2)
node _T_340 = eq(_T_339, UInt<2>(0h3))
node _T_341 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_342 = and(_T_340, _T_341)
node _T_343 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_344 = and(_T_342, _T_343)
node _T_345 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_346 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_347 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_348 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE_2 : UInt<1>[9]
connect _WIRE_2[0], _T_320
connect _WIRE_2[1], _T_326
connect _WIRE_2[2], _T_332
connect _WIRE_2[3], _T_338
connect _WIRE_2[4], _T_344
connect _WIRE_2[5], _T_345
connect _WIRE_2[6], _T_346
connect _WIRE_2[7], _T_347
connect _WIRE_2[8], _T_348
node _T_349 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_350 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_351 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_352 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_353 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_354 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_355 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_356 = mux(_WIRE_2[6], _T_349, UInt<1>(0h0))
node _T_357 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_358 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_359 = or(_T_350, _T_351)
node _T_360 = or(_T_359, _T_352)
node _T_361 = or(_T_360, _T_353)
node _T_362 = or(_T_361, _T_354)
node _T_363 = or(_T_362, _T_355)
node _T_364 = or(_T_363, _T_356)
node _T_365 = or(_T_364, _T_357)
node _T_366 = or(_T_365, _T_358)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_366
node _T_367 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_368 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_369 = and(_T_367, _T_368)
node _T_370 = or(UInt<1>(0h0), _T_369)
node _T_371 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_372 = cvt(_T_371)
node _T_373 = and(_T_372, asSInt(UInt<13>(0h1000)))
node _T_374 = asSInt(_T_373)
node _T_375 = eq(_T_374, asSInt(UInt<1>(0h0)))
node _T_376 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_377 = cvt(_T_376)
node _T_378 = and(_T_377, asSInt(UInt<13>(0h1000)))
node _T_379 = asSInt(_T_378)
node _T_380 = eq(_T_379, asSInt(UInt<1>(0h0)))
node _T_381 = or(_T_375, _T_380)
node _T_382 = and(_T_370, _T_381)
node _T_383 = or(UInt<1>(0h0), _T_382)
node _T_384 = and(_WIRE_3, _T_383)
node _T_385 = asUInt(reset)
node _T_386 = eq(_T_385, UInt<1>(0h0))
when _T_386 :
node _T_387 = eq(_T_384, UInt<1>(0h0))
when _T_387 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_384, UInt<1>(0h1), "") : assert_11
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(source_ok, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_391 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_392 = asUInt(reset)
node _T_393 = eq(_T_392, UInt<1>(0h0))
when _T_393 :
node _T_394 = eq(_T_391, UInt<1>(0h0))
when _T_394 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_391, UInt<1>(0h1), "") : assert_13
node _T_395 = asUInt(reset)
node _T_396 = eq(_T_395, UInt<1>(0h0))
when _T_396 :
node _T_397 = eq(is_aligned, UInt<1>(0h0))
when _T_397 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_398 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_399 = asUInt(reset)
node _T_400 = eq(_T_399, UInt<1>(0h0))
when _T_400 :
node _T_401 = eq(_T_398, UInt<1>(0h0))
when _T_401 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_398, UInt<1>(0h1), "") : assert_15
node _T_402 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_403 = asUInt(reset)
node _T_404 = eq(_T_403, UInt<1>(0h0))
when _T_404 :
node _T_405 = eq(_T_402, UInt<1>(0h0))
when _T_405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_402, UInt<1>(0h1), "") : assert_16
node _T_406 = not(io.in.a.bits.mask)
node _T_407 = eq(_T_406, UInt<1>(0h0))
node _T_408 = asUInt(reset)
node _T_409 = eq(_T_408, UInt<1>(0h0))
when _T_409 :
node _T_410 = eq(_T_407, UInt<1>(0h0))
when _T_410 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_407, UInt<1>(0h1), "") : assert_17
node _T_411 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_411, UInt<1>(0h1), "") : assert_18
node _T_415 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_415 :
node _T_416 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_417 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_418 = and(_T_416, _T_417)
node _T_419 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_420 = shr(io.in.a.bits.source, 2)
node _T_421 = eq(_T_420, UInt<1>(0h0))
node _T_422 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_423 = and(_T_421, _T_422)
node _T_424 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_425 = and(_T_423, _T_424)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_426 = shr(io.in.a.bits.source, 2)
node _T_427 = eq(_T_426, UInt<1>(0h1))
node _T_428 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_429 = and(_T_427, _T_428)
node _T_430 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_431 = and(_T_429, _T_430)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_432 = shr(io.in.a.bits.source, 2)
node _T_433 = eq(_T_432, UInt<2>(0h2))
node _T_434 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_435 = and(_T_433, _T_434)
node _T_436 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_437 = and(_T_435, _T_436)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_438 = shr(io.in.a.bits.source, 2)
node _T_439 = eq(_T_438, UInt<2>(0h3))
node _T_440 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_441 = and(_T_439, _T_440)
node _T_442 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_443 = and(_T_441, _T_442)
node _T_444 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_445 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_446 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_447 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_448 = or(_T_419, _T_425)
node _T_449 = or(_T_448, _T_431)
node _T_450 = or(_T_449, _T_437)
node _T_451 = or(_T_450, _T_443)
node _T_452 = or(_T_451, _T_444)
node _T_453 = or(_T_452, _T_445)
node _T_454 = or(_T_453, _T_446)
node _T_455 = or(_T_454, _T_447)
node _T_456 = and(_T_418, _T_455)
node _T_457 = or(UInt<1>(0h0), _T_456)
node _T_458 = asUInt(reset)
node _T_459 = eq(_T_458, UInt<1>(0h0))
when _T_459 :
node _T_460 = eq(_T_457, UInt<1>(0h0))
when _T_460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_457, UInt<1>(0h1), "") : assert_19
node _T_461 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_462 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_463 = and(_T_461, _T_462)
node _T_464 = or(UInt<1>(0h0), _T_463)
node _T_465 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_466 = cvt(_T_465)
node _T_467 = and(_T_466, asSInt(UInt<13>(0h1000)))
node _T_468 = asSInt(_T_467)
node _T_469 = eq(_T_468, asSInt(UInt<1>(0h0)))
node _T_470 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_471 = cvt(_T_470)
node _T_472 = and(_T_471, asSInt(UInt<13>(0h1000)))
node _T_473 = asSInt(_T_472)
node _T_474 = eq(_T_473, asSInt(UInt<1>(0h0)))
node _T_475 = or(_T_469, _T_474)
node _T_476 = and(_T_464, _T_475)
node _T_477 = or(UInt<1>(0h0), _T_476)
node _T_478 = asUInt(reset)
node _T_479 = eq(_T_478, UInt<1>(0h0))
when _T_479 :
node _T_480 = eq(_T_477, UInt<1>(0h0))
when _T_480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_477, UInt<1>(0h1), "") : assert_20
node _T_481 = asUInt(reset)
node _T_482 = eq(_T_481, UInt<1>(0h0))
when _T_482 :
node _T_483 = eq(source_ok, UInt<1>(0h0))
when _T_483 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_484 = asUInt(reset)
node _T_485 = eq(_T_484, UInt<1>(0h0))
when _T_485 :
node _T_486 = eq(is_aligned, UInt<1>(0h0))
when _T_486 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_487 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_488 = asUInt(reset)
node _T_489 = eq(_T_488, UInt<1>(0h0))
when _T_489 :
node _T_490 = eq(_T_487, UInt<1>(0h0))
when _T_490 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_487, UInt<1>(0h1), "") : assert_23
node _T_491 = eq(io.in.a.bits.mask, mask)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_491, UInt<1>(0h1), "") : assert_24
node _T_495 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_T_495, UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_495, UInt<1>(0h1), "") : assert_25
node _T_499 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_499 :
node _T_500 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_501 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_502 = and(_T_500, _T_501)
node _T_503 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_504 = shr(io.in.a.bits.source, 2)
node _T_505 = eq(_T_504, UInt<1>(0h0))
node _T_506 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_507 = and(_T_505, _T_506)
node _T_508 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_509 = and(_T_507, _T_508)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_510 = shr(io.in.a.bits.source, 2)
node _T_511 = eq(_T_510, UInt<1>(0h1))
node _T_512 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_513 = and(_T_511, _T_512)
node _T_514 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_515 = and(_T_513, _T_514)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_516 = shr(io.in.a.bits.source, 2)
node _T_517 = eq(_T_516, UInt<2>(0h2))
node _T_518 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_519 = and(_T_517, _T_518)
node _T_520 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_521 = and(_T_519, _T_520)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_522 = shr(io.in.a.bits.source, 2)
node _T_523 = eq(_T_522, UInt<2>(0h3))
node _T_524 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_525 = and(_T_523, _T_524)
node _T_526 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_527 = and(_T_525, _T_526)
node _T_528 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_529 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_530 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_531 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_532 = or(_T_503, _T_509)
node _T_533 = or(_T_532, _T_515)
node _T_534 = or(_T_533, _T_521)
node _T_535 = or(_T_534, _T_527)
node _T_536 = or(_T_535, _T_528)
node _T_537 = or(_T_536, _T_529)
node _T_538 = or(_T_537, _T_530)
node _T_539 = or(_T_538, _T_531)
node _T_540 = and(_T_502, _T_539)
node _T_541 = or(UInt<1>(0h0), _T_540)
node _T_542 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_543 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_544 = and(_T_542, _T_543)
node _T_545 = or(UInt<1>(0h0), _T_544)
node _T_546 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_547 = cvt(_T_546)
node _T_548 = and(_T_547, asSInt(UInt<13>(0h1000)))
node _T_549 = asSInt(_T_548)
node _T_550 = eq(_T_549, asSInt(UInt<1>(0h0)))
node _T_551 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_552 = cvt(_T_551)
node _T_553 = and(_T_552, asSInt(UInt<13>(0h1000)))
node _T_554 = asSInt(_T_553)
node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0)))
node _T_556 = or(_T_550, _T_555)
node _T_557 = and(_T_545, _T_556)
node _T_558 = or(UInt<1>(0h0), _T_557)
node _T_559 = and(_T_541, _T_558)
node _T_560 = asUInt(reset)
node _T_561 = eq(_T_560, UInt<1>(0h0))
when _T_561 :
node _T_562 = eq(_T_559, UInt<1>(0h0))
when _T_562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_559, UInt<1>(0h1), "") : assert_26
node _T_563 = asUInt(reset)
node _T_564 = eq(_T_563, UInt<1>(0h0))
when _T_564 :
node _T_565 = eq(source_ok, UInt<1>(0h0))
when _T_565 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_566 = asUInt(reset)
node _T_567 = eq(_T_566, UInt<1>(0h0))
when _T_567 :
node _T_568 = eq(is_aligned, UInt<1>(0h0))
when _T_568 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_569 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_569, UInt<1>(0h1), "") : assert_29
node _T_573 = eq(io.in.a.bits.mask, mask)
node _T_574 = asUInt(reset)
node _T_575 = eq(_T_574, UInt<1>(0h0))
when _T_575 :
node _T_576 = eq(_T_573, UInt<1>(0h0))
when _T_576 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_573, UInt<1>(0h1), "") : assert_30
node _T_577 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_577 :
node _T_578 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_579 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_580 = and(_T_578, _T_579)
node _T_581 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_582 = shr(io.in.a.bits.source, 2)
node _T_583 = eq(_T_582, UInt<1>(0h0))
node _T_584 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_585 = and(_T_583, _T_584)
node _T_586 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_587 = and(_T_585, _T_586)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_588 = shr(io.in.a.bits.source, 2)
node _T_589 = eq(_T_588, UInt<1>(0h1))
node _T_590 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_591 = and(_T_589, _T_590)
node _T_592 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_593 = and(_T_591, _T_592)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_594 = shr(io.in.a.bits.source, 2)
node _T_595 = eq(_T_594, UInt<2>(0h2))
node _T_596 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_597 = and(_T_595, _T_596)
node _T_598 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_599 = and(_T_597, _T_598)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_600 = shr(io.in.a.bits.source, 2)
node _T_601 = eq(_T_600, UInt<2>(0h3))
node _T_602 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_603 = and(_T_601, _T_602)
node _T_604 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_605 = and(_T_603, _T_604)
node _T_606 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_607 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_608 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_609 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_610 = or(_T_581, _T_587)
node _T_611 = or(_T_610, _T_593)
node _T_612 = or(_T_611, _T_599)
node _T_613 = or(_T_612, _T_605)
node _T_614 = or(_T_613, _T_606)
node _T_615 = or(_T_614, _T_607)
node _T_616 = or(_T_615, _T_608)
node _T_617 = or(_T_616, _T_609)
node _T_618 = and(_T_580, _T_617)
node _T_619 = or(UInt<1>(0h0), _T_618)
node _T_620 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_621 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_622 = and(_T_620, _T_621)
node _T_623 = or(UInt<1>(0h0), _T_622)
node _T_624 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_625 = cvt(_T_624)
node _T_626 = and(_T_625, asSInt(UInt<13>(0h1000)))
node _T_627 = asSInt(_T_626)
node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0)))
node _T_629 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_630 = cvt(_T_629)
node _T_631 = and(_T_630, asSInt(UInt<13>(0h1000)))
node _T_632 = asSInt(_T_631)
node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0)))
node _T_634 = or(_T_628, _T_633)
node _T_635 = and(_T_623, _T_634)
node _T_636 = or(UInt<1>(0h0), _T_635)
node _T_637 = and(_T_619, _T_636)
node _T_638 = asUInt(reset)
node _T_639 = eq(_T_638, UInt<1>(0h0))
when _T_639 :
node _T_640 = eq(_T_637, UInt<1>(0h0))
when _T_640 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_637, UInt<1>(0h1), "") : assert_31
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(source_ok, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_644 = asUInt(reset)
node _T_645 = eq(_T_644, UInt<1>(0h0))
when _T_645 :
node _T_646 = eq(is_aligned, UInt<1>(0h0))
when _T_646 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_647 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_648 = asUInt(reset)
node _T_649 = eq(_T_648, UInt<1>(0h0))
when _T_649 :
node _T_650 = eq(_T_647, UInt<1>(0h0))
when _T_650 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_647, UInt<1>(0h1), "") : assert_34
node _T_651 = not(mask)
node _T_652 = and(io.in.a.bits.mask, _T_651)
node _T_653 = eq(_T_652, UInt<1>(0h0))
node _T_654 = asUInt(reset)
node _T_655 = eq(_T_654, UInt<1>(0h0))
when _T_655 :
node _T_656 = eq(_T_653, UInt<1>(0h0))
when _T_656 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_653, UInt<1>(0h1), "") : assert_35
node _T_657 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_657 :
node _T_658 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_659 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_660 = and(_T_658, _T_659)
node _T_661 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_662 = shr(io.in.a.bits.source, 2)
node _T_663 = eq(_T_662, UInt<1>(0h0))
node _T_664 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_665 = and(_T_663, _T_664)
node _T_666 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_667 = and(_T_665, _T_666)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_668 = shr(io.in.a.bits.source, 2)
node _T_669 = eq(_T_668, UInt<1>(0h1))
node _T_670 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_671 = and(_T_669, _T_670)
node _T_672 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_673 = and(_T_671, _T_672)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_674 = shr(io.in.a.bits.source, 2)
node _T_675 = eq(_T_674, UInt<2>(0h2))
node _T_676 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_677 = and(_T_675, _T_676)
node _T_678 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_679 = and(_T_677, _T_678)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_680 = shr(io.in.a.bits.source, 2)
node _T_681 = eq(_T_680, UInt<2>(0h3))
node _T_682 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_683 = and(_T_681, _T_682)
node _T_684 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_685 = and(_T_683, _T_684)
node _T_686 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_687 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_688 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_689 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_690 = or(_T_661, _T_667)
node _T_691 = or(_T_690, _T_673)
node _T_692 = or(_T_691, _T_679)
node _T_693 = or(_T_692, _T_685)
node _T_694 = or(_T_693, _T_686)
node _T_695 = or(_T_694, _T_687)
node _T_696 = or(_T_695, _T_688)
node _T_697 = or(_T_696, _T_689)
node _T_698 = and(_T_660, _T_697)
node _T_699 = or(UInt<1>(0h0), _T_698)
node _T_700 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_701 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_702 = cvt(_T_701)
node _T_703 = and(_T_702, asSInt(UInt<13>(0h1000)))
node _T_704 = asSInt(_T_703)
node _T_705 = eq(_T_704, asSInt(UInt<1>(0h0)))
node _T_706 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_707 = cvt(_T_706)
node _T_708 = and(_T_707, asSInt(UInt<13>(0h1000)))
node _T_709 = asSInt(_T_708)
node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0)))
node _T_711 = or(_T_705, _T_710)
node _T_712 = and(_T_700, _T_711)
node _T_713 = or(UInt<1>(0h0), _T_712)
node _T_714 = and(_T_699, _T_713)
node _T_715 = asUInt(reset)
node _T_716 = eq(_T_715, UInt<1>(0h0))
when _T_716 :
node _T_717 = eq(_T_714, UInt<1>(0h0))
when _T_717 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_714, UInt<1>(0h1), "") : assert_36
node _T_718 = asUInt(reset)
node _T_719 = eq(_T_718, UInt<1>(0h0))
when _T_719 :
node _T_720 = eq(source_ok, UInt<1>(0h0))
when _T_720 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_721 = asUInt(reset)
node _T_722 = eq(_T_721, UInt<1>(0h0))
when _T_722 :
node _T_723 = eq(is_aligned, UInt<1>(0h0))
when _T_723 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_724 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_725 = asUInt(reset)
node _T_726 = eq(_T_725, UInt<1>(0h0))
when _T_726 :
node _T_727 = eq(_T_724, UInt<1>(0h0))
when _T_727 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_724, UInt<1>(0h1), "") : assert_39
node _T_728 = eq(io.in.a.bits.mask, mask)
node _T_729 = asUInt(reset)
node _T_730 = eq(_T_729, UInt<1>(0h0))
when _T_730 :
node _T_731 = eq(_T_728, UInt<1>(0h0))
when _T_731 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_728, UInt<1>(0h1), "") : assert_40
node _T_732 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_732 :
node _T_733 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_734 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_735 = and(_T_733, _T_734)
node _T_736 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_737 = shr(io.in.a.bits.source, 2)
node _T_738 = eq(_T_737, UInt<1>(0h0))
node _T_739 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_740 = and(_T_738, _T_739)
node _T_741 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_742 = and(_T_740, _T_741)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_743 = shr(io.in.a.bits.source, 2)
node _T_744 = eq(_T_743, UInt<1>(0h1))
node _T_745 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_746 = and(_T_744, _T_745)
node _T_747 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_748 = and(_T_746, _T_747)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_749 = shr(io.in.a.bits.source, 2)
node _T_750 = eq(_T_749, UInt<2>(0h2))
node _T_751 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_752 = and(_T_750, _T_751)
node _T_753 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_754 = and(_T_752, _T_753)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_755 = shr(io.in.a.bits.source, 2)
node _T_756 = eq(_T_755, UInt<2>(0h3))
node _T_757 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_758 = and(_T_756, _T_757)
node _T_759 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_760 = and(_T_758, _T_759)
node _T_761 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_762 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_763 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_764 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_765 = or(_T_736, _T_742)
node _T_766 = or(_T_765, _T_748)
node _T_767 = or(_T_766, _T_754)
node _T_768 = or(_T_767, _T_760)
node _T_769 = or(_T_768, _T_761)
node _T_770 = or(_T_769, _T_762)
node _T_771 = or(_T_770, _T_763)
node _T_772 = or(_T_771, _T_764)
node _T_773 = and(_T_735, _T_772)
node _T_774 = or(UInt<1>(0h0), _T_773)
node _T_775 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_776 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_777 = cvt(_T_776)
node _T_778 = and(_T_777, asSInt(UInt<13>(0h1000)))
node _T_779 = asSInt(_T_778)
node _T_780 = eq(_T_779, asSInt(UInt<1>(0h0)))
node _T_781 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_782 = cvt(_T_781)
node _T_783 = and(_T_782, asSInt(UInt<13>(0h1000)))
node _T_784 = asSInt(_T_783)
node _T_785 = eq(_T_784, asSInt(UInt<1>(0h0)))
node _T_786 = or(_T_780, _T_785)
node _T_787 = and(_T_775, _T_786)
node _T_788 = or(UInt<1>(0h0), _T_787)
node _T_789 = and(_T_774, _T_788)
node _T_790 = asUInt(reset)
node _T_791 = eq(_T_790, UInt<1>(0h0))
when _T_791 :
node _T_792 = eq(_T_789, UInt<1>(0h0))
when _T_792 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_789, UInt<1>(0h1), "") : assert_41
node _T_793 = asUInt(reset)
node _T_794 = eq(_T_793, UInt<1>(0h0))
when _T_794 :
node _T_795 = eq(source_ok, UInt<1>(0h0))
when _T_795 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_796 = asUInt(reset)
node _T_797 = eq(_T_796, UInt<1>(0h0))
when _T_797 :
node _T_798 = eq(is_aligned, UInt<1>(0h0))
when _T_798 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_799 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_800 = asUInt(reset)
node _T_801 = eq(_T_800, UInt<1>(0h0))
when _T_801 :
node _T_802 = eq(_T_799, UInt<1>(0h0))
when _T_802 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_799, UInt<1>(0h1), "") : assert_44
node _T_803 = eq(io.in.a.bits.mask, mask)
node _T_804 = asUInt(reset)
node _T_805 = eq(_T_804, UInt<1>(0h0))
when _T_805 :
node _T_806 = eq(_T_803, UInt<1>(0h0))
when _T_806 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_803, UInt<1>(0h1), "") : assert_45
node _T_807 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_807 :
node _T_808 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_809 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_810 = and(_T_808, _T_809)
node _T_811 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_812 = shr(io.in.a.bits.source, 2)
node _T_813 = eq(_T_812, UInt<1>(0h0))
node _T_814 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_815 = and(_T_813, _T_814)
node _T_816 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_817 = and(_T_815, _T_816)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_818 = shr(io.in.a.bits.source, 2)
node _T_819 = eq(_T_818, UInt<1>(0h1))
node _T_820 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_821 = and(_T_819, _T_820)
node _T_822 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_823 = and(_T_821, _T_822)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_824 = shr(io.in.a.bits.source, 2)
node _T_825 = eq(_T_824, UInt<2>(0h2))
node _T_826 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_827 = and(_T_825, _T_826)
node _T_828 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_829 = and(_T_827, _T_828)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_830 = shr(io.in.a.bits.source, 2)
node _T_831 = eq(_T_830, UInt<2>(0h3))
node _T_832 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_833 = and(_T_831, _T_832)
node _T_834 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_835 = and(_T_833, _T_834)
node _T_836 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_837 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_838 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_839 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_840 = or(_T_811, _T_817)
node _T_841 = or(_T_840, _T_823)
node _T_842 = or(_T_841, _T_829)
node _T_843 = or(_T_842, _T_835)
node _T_844 = or(_T_843, _T_836)
node _T_845 = or(_T_844, _T_837)
node _T_846 = or(_T_845, _T_838)
node _T_847 = or(_T_846, _T_839)
node _T_848 = and(_T_810, _T_847)
node _T_849 = or(UInt<1>(0h0), _T_848)
node _T_850 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_851 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_852 = cvt(_T_851)
node _T_853 = and(_T_852, asSInt(UInt<13>(0h1000)))
node _T_854 = asSInt(_T_853)
node _T_855 = eq(_T_854, asSInt(UInt<1>(0h0)))
node _T_856 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_857 = cvt(_T_856)
node _T_858 = and(_T_857, asSInt(UInt<13>(0h1000)))
node _T_859 = asSInt(_T_858)
node _T_860 = eq(_T_859, asSInt(UInt<1>(0h0)))
node _T_861 = or(_T_855, _T_860)
node _T_862 = and(_T_850, _T_861)
node _T_863 = or(UInt<1>(0h0), _T_862)
node _T_864 = and(_T_849, _T_863)
node _T_865 = asUInt(reset)
node _T_866 = eq(_T_865, UInt<1>(0h0))
when _T_866 :
node _T_867 = eq(_T_864, UInt<1>(0h0))
when _T_867 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_864, UInt<1>(0h1), "") : assert_46
node _T_868 = asUInt(reset)
node _T_869 = eq(_T_868, UInt<1>(0h0))
when _T_869 :
node _T_870 = eq(source_ok, UInt<1>(0h0))
when _T_870 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_871 = asUInt(reset)
node _T_872 = eq(_T_871, UInt<1>(0h0))
when _T_872 :
node _T_873 = eq(is_aligned, UInt<1>(0h0))
when _T_873 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_874 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_875 = asUInt(reset)
node _T_876 = eq(_T_875, UInt<1>(0h0))
when _T_876 :
node _T_877 = eq(_T_874, UInt<1>(0h0))
when _T_877 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_874, UInt<1>(0h1), "") : assert_49
node _T_878 = eq(io.in.a.bits.mask, mask)
node _T_879 = asUInt(reset)
node _T_880 = eq(_T_879, UInt<1>(0h0))
when _T_880 :
node _T_881 = eq(_T_878, UInt<1>(0h0))
when _T_881 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_878, UInt<1>(0h1), "") : assert_50
node _T_882 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_883 = asUInt(reset)
node _T_884 = eq(_T_883, UInt<1>(0h0))
when _T_884 :
node _T_885 = eq(_T_882, UInt<1>(0h0))
when _T_885 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_882, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_886 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_887 = asUInt(reset)
node _T_888 = eq(_T_887, UInt<1>(0h0))
when _T_888 :
node _T_889 = eq(_T_886, UInt<1>(0h0))
when _T_889 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_886, UInt<1>(0h1), "") : assert_52
node _source_ok_T_36 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_37 = shr(io.in.d.bits.source, 2)
node _source_ok_T_38 = eq(_source_ok_T_37, UInt<1>(0h0))
node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39)
node _source_ok_T_41 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_43 = shr(io.in.d.bits.source, 2)
node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h1))
node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45)
node _source_ok_T_47 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_49 = shr(io.in.d.bits.source, 2)
node _source_ok_T_50 = eq(_source_ok_T_49, UInt<2>(0h2))
node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51)
node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_55 = shr(io.in.d.bits.source, 2)
node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h3))
node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57)
node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59)
node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<6>(0h22))
node _source_ok_T_62 = eq(io.in.d.bits.source, UInt<6>(0h21))
node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE_1 : UInt<1>[9]
connect _source_ok_WIRE_1[0], _source_ok_T_36
connect _source_ok_WIRE_1[1], _source_ok_T_42
connect _source_ok_WIRE_1[2], _source_ok_T_48
connect _source_ok_WIRE_1[3], _source_ok_T_54
connect _source_ok_WIRE_1[4], _source_ok_T_60
connect _source_ok_WIRE_1[5], _source_ok_T_61
connect _source_ok_WIRE_1[6], _source_ok_T_62
connect _source_ok_WIRE_1[7], _source_ok_T_63
connect _source_ok_WIRE_1[8], _source_ok_T_64
node _source_ok_T_65 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[2])
node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[3])
node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE_1[4])
node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[5])
node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[6])
node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[7])
node source_ok_1 = or(_source_ok_T_71, _source_ok_WIRE_1[8])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_890 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_890 :
node _T_891 = asUInt(reset)
node _T_892 = eq(_T_891, UInt<1>(0h0))
when _T_892 :
node _T_893 = eq(source_ok_1, UInt<1>(0h0))
when _T_893 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_894 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_895 = asUInt(reset)
node _T_896 = eq(_T_895, UInt<1>(0h0))
when _T_896 :
node _T_897 = eq(_T_894, UInt<1>(0h0))
when _T_897 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_894, UInt<1>(0h1), "") : assert_54
node _T_898 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_899 = asUInt(reset)
node _T_900 = eq(_T_899, UInt<1>(0h0))
when _T_900 :
node _T_901 = eq(_T_898, UInt<1>(0h0))
when _T_901 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_898, UInt<1>(0h1), "") : assert_55
node _T_902 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_903 = asUInt(reset)
node _T_904 = eq(_T_903, UInt<1>(0h0))
when _T_904 :
node _T_905 = eq(_T_902, UInt<1>(0h0))
when _T_905 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_902, UInt<1>(0h1), "") : assert_56
node _T_906 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_907 = asUInt(reset)
node _T_908 = eq(_T_907, UInt<1>(0h0))
when _T_908 :
node _T_909 = eq(_T_906, UInt<1>(0h0))
when _T_909 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_906, UInt<1>(0h1), "") : assert_57
node _T_910 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_910 :
node _T_911 = asUInt(reset)
node _T_912 = eq(_T_911, UInt<1>(0h0))
when _T_912 :
node _T_913 = eq(source_ok_1, UInt<1>(0h0))
when _T_913 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_914 = asUInt(reset)
node _T_915 = eq(_T_914, UInt<1>(0h0))
when _T_915 :
node _T_916 = eq(sink_ok, UInt<1>(0h0))
when _T_916 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_917 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_918 = asUInt(reset)
node _T_919 = eq(_T_918, UInt<1>(0h0))
when _T_919 :
node _T_920 = eq(_T_917, UInt<1>(0h0))
when _T_920 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_917, UInt<1>(0h1), "") : assert_60
node _T_921 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_922 = asUInt(reset)
node _T_923 = eq(_T_922, UInt<1>(0h0))
when _T_923 :
node _T_924 = eq(_T_921, UInt<1>(0h0))
when _T_924 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_921, UInt<1>(0h1), "") : assert_61
node _T_925 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_926 = asUInt(reset)
node _T_927 = eq(_T_926, UInt<1>(0h0))
when _T_927 :
node _T_928 = eq(_T_925, UInt<1>(0h0))
when _T_928 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_925, UInt<1>(0h1), "") : assert_62
node _T_929 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_930 = asUInt(reset)
node _T_931 = eq(_T_930, UInt<1>(0h0))
when _T_931 :
node _T_932 = eq(_T_929, UInt<1>(0h0))
when _T_932 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_929, UInt<1>(0h1), "") : assert_63
node _T_933 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_934 = or(UInt<1>(0h0), _T_933)
node _T_935 = asUInt(reset)
node _T_936 = eq(_T_935, UInt<1>(0h0))
when _T_936 :
node _T_937 = eq(_T_934, UInt<1>(0h0))
when _T_937 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_934, UInt<1>(0h1), "") : assert_64
node _T_938 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_938 :
node _T_939 = asUInt(reset)
node _T_940 = eq(_T_939, UInt<1>(0h0))
when _T_940 :
node _T_941 = eq(source_ok_1, UInt<1>(0h0))
when _T_941 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_942 = asUInt(reset)
node _T_943 = eq(_T_942, UInt<1>(0h0))
when _T_943 :
node _T_944 = eq(sink_ok, UInt<1>(0h0))
when _T_944 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_945 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_946 = asUInt(reset)
node _T_947 = eq(_T_946, UInt<1>(0h0))
when _T_947 :
node _T_948 = eq(_T_945, UInt<1>(0h0))
when _T_948 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_945, UInt<1>(0h1), "") : assert_67
node _T_949 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_950 = asUInt(reset)
node _T_951 = eq(_T_950, UInt<1>(0h0))
when _T_951 :
node _T_952 = eq(_T_949, UInt<1>(0h0))
when _T_952 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_949, UInt<1>(0h1), "") : assert_68
node _T_953 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_954 = asUInt(reset)
node _T_955 = eq(_T_954, UInt<1>(0h0))
when _T_955 :
node _T_956 = eq(_T_953, UInt<1>(0h0))
when _T_956 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_953, UInt<1>(0h1), "") : assert_69
node _T_957 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_958 = or(_T_957, io.in.d.bits.corrupt)
node _T_959 = asUInt(reset)
node _T_960 = eq(_T_959, UInt<1>(0h0))
when _T_960 :
node _T_961 = eq(_T_958, UInt<1>(0h0))
when _T_961 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_958, UInt<1>(0h1), "") : assert_70
node _T_962 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_963 = or(UInt<1>(0h0), _T_962)
node _T_964 = asUInt(reset)
node _T_965 = eq(_T_964, UInt<1>(0h0))
when _T_965 :
node _T_966 = eq(_T_963, UInt<1>(0h0))
when _T_966 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_963, UInt<1>(0h1), "") : assert_71
node _T_967 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_967 :
node _T_968 = asUInt(reset)
node _T_969 = eq(_T_968, UInt<1>(0h0))
when _T_969 :
node _T_970 = eq(source_ok_1, UInt<1>(0h0))
when _T_970 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_971 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_972 = asUInt(reset)
node _T_973 = eq(_T_972, UInt<1>(0h0))
when _T_973 :
node _T_974 = eq(_T_971, UInt<1>(0h0))
when _T_974 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_971, UInt<1>(0h1), "") : assert_73
node _T_975 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_976 = asUInt(reset)
node _T_977 = eq(_T_976, UInt<1>(0h0))
when _T_977 :
node _T_978 = eq(_T_975, UInt<1>(0h0))
when _T_978 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_975, UInt<1>(0h1), "") : assert_74
node _T_979 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_980 = or(UInt<1>(0h0), _T_979)
node _T_981 = asUInt(reset)
node _T_982 = eq(_T_981, UInt<1>(0h0))
when _T_982 :
node _T_983 = eq(_T_980, UInt<1>(0h0))
when _T_983 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_980, UInt<1>(0h1), "") : assert_75
node _T_984 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_984 :
node _T_985 = asUInt(reset)
node _T_986 = eq(_T_985, UInt<1>(0h0))
when _T_986 :
node _T_987 = eq(source_ok_1, UInt<1>(0h0))
when _T_987 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_988 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_989 = asUInt(reset)
node _T_990 = eq(_T_989, UInt<1>(0h0))
when _T_990 :
node _T_991 = eq(_T_988, UInt<1>(0h0))
when _T_991 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_988, UInt<1>(0h1), "") : assert_77
node _T_992 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_993 = or(_T_992, io.in.d.bits.corrupt)
node _T_994 = asUInt(reset)
node _T_995 = eq(_T_994, UInt<1>(0h0))
when _T_995 :
node _T_996 = eq(_T_993, UInt<1>(0h0))
when _T_996 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_993, UInt<1>(0h1), "") : assert_78
node _T_997 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_998 = or(UInt<1>(0h0), _T_997)
node _T_999 = asUInt(reset)
node _T_1000 = eq(_T_999, UInt<1>(0h0))
when _T_1000 :
node _T_1001 = eq(_T_998, UInt<1>(0h0))
when _T_1001 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_998, UInt<1>(0h1), "") : assert_79
node _T_1002 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1002 :
node _T_1003 = asUInt(reset)
node _T_1004 = eq(_T_1003, UInt<1>(0h0))
when _T_1004 :
node _T_1005 = eq(source_ok_1, UInt<1>(0h0))
when _T_1005 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1006 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1007 = asUInt(reset)
node _T_1008 = eq(_T_1007, UInt<1>(0h0))
when _T_1008 :
node _T_1009 = eq(_T_1006, UInt<1>(0h0))
when _T_1009 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1006, UInt<1>(0h1), "") : assert_81
node _T_1010 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1011 = asUInt(reset)
node _T_1012 = eq(_T_1011, UInt<1>(0h0))
when _T_1012 :
node _T_1013 = eq(_T_1010, UInt<1>(0h0))
when _T_1013 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1010, UInt<1>(0h1), "") : assert_82
node _T_1014 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1015 = or(UInt<1>(0h0), _T_1014)
node _T_1016 = asUInt(reset)
node _T_1017 = eq(_T_1016, UInt<1>(0h0))
when _T_1017 :
node _T_1018 = eq(_T_1015, UInt<1>(0h0))
when _T_1018 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1015, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<29>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1019 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1020 = asUInt(reset)
node _T_1021 = eq(_T_1020, UInt<1>(0h0))
when _T_1021 :
node _T_1022 = eq(_T_1019, UInt<1>(0h0))
when _T_1022 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1019, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1023 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1024 = asUInt(reset)
node _T_1025 = eq(_T_1024, UInt<1>(0h0))
when _T_1025 :
node _T_1026 = eq(_T_1023, UInt<1>(0h0))
when _T_1026 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1023, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1027 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1028 = asUInt(reset)
node _T_1029 = eq(_T_1028, UInt<1>(0h0))
when _T_1029 :
node _T_1030 = eq(_T_1027, UInt<1>(0h0))
when _T_1030 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1027, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1031 = eq(a_first, UInt<1>(0h0))
node _T_1032 = and(io.in.a.valid, _T_1031)
when _T_1032 :
node _T_1033 = eq(io.in.a.bits.opcode, opcode)
node _T_1034 = asUInt(reset)
node _T_1035 = eq(_T_1034, UInt<1>(0h0))
when _T_1035 :
node _T_1036 = eq(_T_1033, UInt<1>(0h0))
when _T_1036 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1033, UInt<1>(0h1), "") : assert_87
node _T_1037 = eq(io.in.a.bits.param, param)
node _T_1038 = asUInt(reset)
node _T_1039 = eq(_T_1038, UInt<1>(0h0))
when _T_1039 :
node _T_1040 = eq(_T_1037, UInt<1>(0h0))
when _T_1040 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1037, UInt<1>(0h1), "") : assert_88
node _T_1041 = eq(io.in.a.bits.size, size)
node _T_1042 = asUInt(reset)
node _T_1043 = eq(_T_1042, UInt<1>(0h0))
when _T_1043 :
node _T_1044 = eq(_T_1041, UInt<1>(0h0))
when _T_1044 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1041, UInt<1>(0h1), "") : assert_89
node _T_1045 = eq(io.in.a.bits.source, source)
node _T_1046 = asUInt(reset)
node _T_1047 = eq(_T_1046, UInt<1>(0h0))
when _T_1047 :
node _T_1048 = eq(_T_1045, UInt<1>(0h0))
when _T_1048 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1045, UInt<1>(0h1), "") : assert_90
node _T_1049 = eq(io.in.a.bits.address, address)
node _T_1050 = asUInt(reset)
node _T_1051 = eq(_T_1050, UInt<1>(0h0))
when _T_1051 :
node _T_1052 = eq(_T_1049, UInt<1>(0h0))
when _T_1052 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1049, UInt<1>(0h1), "") : assert_91
node _T_1053 = and(io.in.a.ready, io.in.a.valid)
node _T_1054 = and(_T_1053, a_first)
when _T_1054 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1055 = eq(d_first, UInt<1>(0h0))
node _T_1056 = and(io.in.d.valid, _T_1055)
when _T_1056 :
node _T_1057 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1058 = asUInt(reset)
node _T_1059 = eq(_T_1058, UInt<1>(0h0))
when _T_1059 :
node _T_1060 = eq(_T_1057, UInt<1>(0h0))
when _T_1060 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1057, UInt<1>(0h1), "") : assert_92
node _T_1061 = eq(io.in.d.bits.param, param_1)
node _T_1062 = asUInt(reset)
node _T_1063 = eq(_T_1062, UInt<1>(0h0))
when _T_1063 :
node _T_1064 = eq(_T_1061, UInt<1>(0h0))
when _T_1064 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1061, UInt<1>(0h1), "") : assert_93
node _T_1065 = eq(io.in.d.bits.size, size_1)
node _T_1066 = asUInt(reset)
node _T_1067 = eq(_T_1066, UInt<1>(0h0))
when _T_1067 :
node _T_1068 = eq(_T_1065, UInt<1>(0h0))
when _T_1068 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1065, UInt<1>(0h1), "") : assert_94
node _T_1069 = eq(io.in.d.bits.source, source_1)
node _T_1070 = asUInt(reset)
node _T_1071 = eq(_T_1070, UInt<1>(0h0))
when _T_1071 :
node _T_1072 = eq(_T_1069, UInt<1>(0h0))
when _T_1072 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1069, UInt<1>(0h1), "") : assert_95
node _T_1073 = eq(io.in.d.bits.sink, sink)
node _T_1074 = asUInt(reset)
node _T_1075 = eq(_T_1074, UInt<1>(0h0))
when _T_1075 :
node _T_1076 = eq(_T_1073, UInt<1>(0h0))
when _T_1076 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1073, UInt<1>(0h1), "") : assert_96
node _T_1077 = eq(io.in.d.bits.denied, denied)
node _T_1078 = asUInt(reset)
node _T_1079 = eq(_T_1078, UInt<1>(0h0))
when _T_1079 :
node _T_1080 = eq(_T_1077, UInt<1>(0h0))
when _T_1080 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1077, UInt<1>(0h1), "") : assert_97
node _T_1081 = and(io.in.d.ready, io.in.d.valid)
node _T_1082 = and(_T_1081, d_first)
when _T_1082 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<65>
connect a_set, UInt<65>(0h0)
wire a_set_wo_ready : UInt<65>
connect a_set_wo_ready, UInt<65>(0h0)
wire a_opcodes_set : UInt<260>
connect a_opcodes_set, UInt<260>(0h0)
wire a_sizes_set : UInt<260>
connect a_sizes_set, UInt<260>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1083 = and(io.in.a.valid, a_first_1)
node _T_1084 = and(_T_1083, UInt<1>(0h1))
when _T_1084 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1085 = and(io.in.a.ready, io.in.a.valid)
node _T_1086 = and(_T_1085, a_first_1)
node _T_1087 = and(_T_1086, UInt<1>(0h1))
when _T_1087 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1088 = dshr(inflight, io.in.a.bits.source)
node _T_1089 = bits(_T_1088, 0, 0)
node _T_1090 = eq(_T_1089, UInt<1>(0h0))
node _T_1091 = asUInt(reset)
node _T_1092 = eq(_T_1091, UInt<1>(0h0))
when _T_1092 :
node _T_1093 = eq(_T_1090, UInt<1>(0h0))
when _T_1093 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1090, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<65>
connect d_clr, UInt<65>(0h0)
wire d_clr_wo_ready : UInt<65>
connect d_clr_wo_ready, UInt<65>(0h0)
wire d_opcodes_clr : UInt<260>
connect d_opcodes_clr, UInt<260>(0h0)
wire d_sizes_clr : UInt<260>
connect d_sizes_clr, UInt<260>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1094 = and(io.in.d.valid, d_first_1)
node _T_1095 = and(_T_1094, UInt<1>(0h1))
node _T_1096 = eq(d_release_ack, UInt<1>(0h0))
node _T_1097 = and(_T_1095, _T_1096)
when _T_1097 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1098 = and(io.in.d.ready, io.in.d.valid)
node _T_1099 = and(_T_1098, d_first_1)
node _T_1100 = and(_T_1099, UInt<1>(0h1))
node _T_1101 = eq(d_release_ack, UInt<1>(0h0))
node _T_1102 = and(_T_1100, _T_1101)
when _T_1102 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1103 = and(io.in.d.valid, d_first_1)
node _T_1104 = and(_T_1103, UInt<1>(0h1))
node _T_1105 = eq(d_release_ack, UInt<1>(0h0))
node _T_1106 = and(_T_1104, _T_1105)
when _T_1106 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1107 = dshr(inflight, io.in.d.bits.source)
node _T_1108 = bits(_T_1107, 0, 0)
node _T_1109 = or(_T_1108, same_cycle_resp)
node _T_1110 = asUInt(reset)
node _T_1111 = eq(_T_1110, UInt<1>(0h0))
when _T_1111 :
node _T_1112 = eq(_T_1109, UInt<1>(0h0))
when _T_1112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1109, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1113 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1114 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1115 = or(_T_1113, _T_1114)
node _T_1116 = asUInt(reset)
node _T_1117 = eq(_T_1116, UInt<1>(0h0))
when _T_1117 :
node _T_1118 = eq(_T_1115, UInt<1>(0h0))
when _T_1118 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1115, UInt<1>(0h1), "") : assert_100
node _T_1119 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1120 = asUInt(reset)
node _T_1121 = eq(_T_1120, UInt<1>(0h0))
when _T_1121 :
node _T_1122 = eq(_T_1119, UInt<1>(0h0))
when _T_1122 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1119, UInt<1>(0h1), "") : assert_101
else :
node _T_1123 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1124 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1125 = or(_T_1123, _T_1124)
node _T_1126 = asUInt(reset)
node _T_1127 = eq(_T_1126, UInt<1>(0h0))
when _T_1127 :
node _T_1128 = eq(_T_1125, UInt<1>(0h0))
when _T_1128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1125, UInt<1>(0h1), "") : assert_102
node _T_1129 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1130 = asUInt(reset)
node _T_1131 = eq(_T_1130, UInt<1>(0h0))
when _T_1131 :
node _T_1132 = eq(_T_1129, UInt<1>(0h0))
when _T_1132 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1129, UInt<1>(0h1), "") : assert_103
node _T_1133 = and(io.in.d.valid, d_first_1)
node _T_1134 = and(_T_1133, a_first_1)
node _T_1135 = and(_T_1134, io.in.a.valid)
node _T_1136 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1137 = and(_T_1135, _T_1136)
node _T_1138 = eq(d_release_ack, UInt<1>(0h0))
node _T_1139 = and(_T_1137, _T_1138)
when _T_1139 :
node _T_1140 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1141 = or(_T_1140, io.in.a.ready)
node _T_1142 = asUInt(reset)
node _T_1143 = eq(_T_1142, UInt<1>(0h0))
when _T_1143 :
node _T_1144 = eq(_T_1141, UInt<1>(0h0))
when _T_1144 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1141, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_4
node _T_1145 = orr(inflight)
node _T_1146 = eq(_T_1145, UInt<1>(0h0))
node _T_1147 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1148 = or(_T_1146, _T_1147)
node _T_1149 = lt(watchdog, plusarg_reader.out)
node _T_1150 = or(_T_1148, _T_1149)
node _T_1151 = asUInt(reset)
node _T_1152 = eq(_T_1151, UInt<1>(0h0))
when _T_1152 :
node _T_1153 = eq(_T_1150, UInt<1>(0h0))
when _T_1153 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1150, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1154 = and(io.in.a.ready, io.in.a.valid)
node _T_1155 = and(io.in.d.ready, io.in.d.valid)
node _T_1156 = or(_T_1154, _T_1155)
when _T_1156 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<29>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<65>
connect c_set, UInt<65>(0h0)
wire c_set_wo_ready : UInt<65>
connect c_set_wo_ready, UInt<65>(0h0)
wire c_opcodes_set : UInt<260>
connect c_opcodes_set, UInt<260>(0h0)
wire c_sizes_set : UInt<260>
connect c_sizes_set, UInt<260>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<29>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1157 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<29>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1158 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1159 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1160 = and(_T_1158, _T_1159)
node _T_1161 = and(_T_1157, _T_1160)
when _T_1161 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<29>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1162 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1163 = and(_T_1162, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<29>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1164 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1165 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1166 = and(_T_1164, _T_1165)
node _T_1167 = and(_T_1163, _T_1166)
when _T_1167 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<29>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1168 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1169 = bits(_T_1168, 0, 0)
node _T_1170 = eq(_T_1169, UInt<1>(0h0))
node _T_1171 = asUInt(reset)
node _T_1172 = eq(_T_1171, UInt<1>(0h0))
when _T_1172 :
node _T_1173 = eq(_T_1170, UInt<1>(0h0))
when _T_1173 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1170, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<65>
connect d_clr_1, UInt<65>(0h0)
wire d_clr_wo_ready_1 : UInt<65>
connect d_clr_wo_ready_1, UInt<65>(0h0)
wire d_opcodes_clr_1 : UInt<260>
connect d_opcodes_clr_1, UInt<260>(0h0)
wire d_sizes_clr_1 : UInt<260>
connect d_sizes_clr_1, UInt<260>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1174 = and(io.in.d.valid, d_first_2)
node _T_1175 = and(_T_1174, UInt<1>(0h1))
node _T_1176 = and(_T_1175, d_release_ack_1)
when _T_1176 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1177 = and(io.in.d.ready, io.in.d.valid)
node _T_1178 = and(_T_1177, d_first_2)
node _T_1179 = and(_T_1178, UInt<1>(0h1))
node _T_1180 = and(_T_1179, d_release_ack_1)
when _T_1180 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1181 = and(io.in.d.valid, d_first_2)
node _T_1182 = and(_T_1181, UInt<1>(0h1))
node _T_1183 = and(_T_1182, d_release_ack_1)
when _T_1183 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1184 = dshr(inflight_1, io.in.d.bits.source)
node _T_1185 = bits(_T_1184, 0, 0)
node _T_1186 = or(_T_1185, same_cycle_resp_1)
node _T_1187 = asUInt(reset)
node _T_1188 = eq(_T_1187, UInt<1>(0h0))
when _T_1188 :
node _T_1189 = eq(_T_1186, UInt<1>(0h0))
when _T_1189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_1186, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<29>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1190 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1191 = asUInt(reset)
node _T_1192 = eq(_T_1191, UInt<1>(0h0))
when _T_1192 :
node _T_1193 = eq(_T_1190, UInt<1>(0h0))
when _T_1193 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1190, UInt<1>(0h1), "") : assert_108
else :
node _T_1194 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1195 = asUInt(reset)
node _T_1196 = eq(_T_1195, UInt<1>(0h0))
when _T_1196 :
node _T_1197 = eq(_T_1194, UInt<1>(0h0))
when _T_1197 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1194, UInt<1>(0h1), "") : assert_109
node _T_1198 = and(io.in.d.valid, d_first_2)
node _T_1199 = and(_T_1198, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<29>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1200 = and(_T_1199, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<29>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1201 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1202 = and(_T_1200, _T_1201)
node _T_1203 = and(_T_1202, d_release_ack_1)
node _T_1204 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1205 = and(_T_1203, _T_1204)
when _T_1205 :
node _T_1206 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<29>(0h0)
connect _WIRE_26.bits.source, UInt<7>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1207 = or(_T_1206, _WIRE_27.ready)
node _T_1208 = asUInt(reset)
node _T_1209 = eq(_T_1208, UInt<1>(0h0))
when _T_1209 :
node _T_1210 = eq(_T_1207, UInt<1>(0h0))
when _T_1210 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1207, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_5
node _T_1211 = orr(inflight_1)
node _T_1212 = eq(_T_1211, UInt<1>(0h0))
node _T_1213 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1214 = or(_T_1212, _T_1213)
node _T_1215 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1216 = or(_T_1214, _T_1215)
node _T_1217 = asUInt(reset)
node _T_1218 = eq(_T_1217, UInt<1>(0h0))
when _T_1218 :
node _T_1219 = eq(_T_1216, UInt<1>(0h0))
when _T_1219 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1216, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<29>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1220 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1221 = and(io.in.d.ready, io.in.d.valid)
node _T_1222 = or(_T_1220, _T_1221)
when _T_1222 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_2( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31]
wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31]
wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31]
wire _source_ok_T_29 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_32 = _source_ok_T_31 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_34 = _source_ok_T_33 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_35 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_36 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_37 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_43 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_38 = _source_ok_T_37 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_42; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_44 = _source_ok_T_43 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_48; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_50 = _source_ok_T_49 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_54; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_56 = _source_ok_T_55 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_60; // @[Parameters.scala:1138:31]
wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_61; // @[Parameters.scala:1138:31]
wire _source_ok_T_62 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_62; // @[Parameters.scala:1138:31]
wire _source_ok_T_63 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_63; // @[Parameters.scala:1138:31]
wire _source_ok_T_64 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_64; // @[Parameters.scala:1138:31]
wire _source_ok_T_65 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_68 = _source_ok_T_67 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_69 = _source_ok_T_68 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_70 = _source_ok_T_69 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_71 = _source_ok_T_70 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_71 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1154 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1154; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1154; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_1222 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1222; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1222; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1222; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [259:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1087 = _T_1154 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1087 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1087 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1087 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1087 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1087 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1133 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1133 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1102 = _T_1222 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1102 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1102 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1102 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1198 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1198 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1180 = _T_1222 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1180 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1180 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1180 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module PE_372 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_116
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<32>, clock
reg c2 : SInt<32>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node c1_sign = bits(io.in_d, 19, 19)
node c1_lo_lo_hi = cat(c1_sign, c1_sign)
node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign)
node c1_lo_hi_hi = cat(c1_sign, c1_sign)
node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign)
node c1_lo = cat(c1_lo_hi, c1_lo_lo)
node c1_hi_lo_hi = cat(c1_sign, c1_sign)
node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign)
node c1_hi_hi_hi = cat(c1_sign, c1_sign)
node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign)
node c1_hi = cat(c1_hi_hi, c1_hi_lo)
node _c1_T = cat(c1_hi, c1_lo)
node c1_lo_1 = asUInt(io.in_d)
node _c1_T_1 = cat(_c1_T, c1_lo_1)
wire _c1_WIRE : SInt<32>
node _c1_T_2 = asSInt(_c1_T_1)
connect _c1_WIRE, _c1_T_2
connect c1, _c1_WIRE
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node c2_sign = bits(io.in_d, 19, 19)
node c2_lo_lo_hi = cat(c2_sign, c2_sign)
node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign)
node c2_lo_hi_hi = cat(c2_sign, c2_sign)
node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign)
node c2_lo = cat(c2_lo_hi, c2_lo_lo)
node c2_hi_lo_hi = cat(c2_sign, c2_sign)
node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign)
node c2_hi_hi_hi = cat(c2_sign, c2_sign)
node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign)
node c2_hi = cat(c2_hi_hi, c2_hi_lo)
node _c2_T = cat(c2_hi, c2_lo)
node c2_lo_1 = asUInt(io.in_d)
node _c2_T_1 = cat(_c2_T, c2_lo_1)
wire _c2_WIRE : SInt<32>
node _c2_T_2 = asSInt(_c2_T_1)
connect _c2_WIRE, _c2_T_2
connect c2, _c2_WIRE
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h1), _T_4)
node _T_6 = or(UInt<1>(0h0), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_372( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_116 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLSerdesser_serial_tl_0 :
input clock : Clock
input reset : Reset
output auto : { client_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<7>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
output io : { ser : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}}[5], debug : { ser_busy : UInt<1>, des_busy : UInt<1>}}
wire clientNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<7>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate clientNodeOut.d.bits.corrupt
invalidate clientNodeOut.d.bits.data
invalidate clientNodeOut.d.bits.denied
invalidate clientNodeOut.d.bits.sink
invalidate clientNodeOut.d.bits.source
invalidate clientNodeOut.d.bits.size
invalidate clientNodeOut.d.bits.param
invalidate clientNodeOut.d.bits.opcode
invalidate clientNodeOut.d.valid
invalidate clientNodeOut.d.ready
invalidate clientNodeOut.a.bits.corrupt
invalidate clientNodeOut.a.bits.data
invalidate clientNodeOut.a.bits.mask
invalidate clientNodeOut.a.bits.address
invalidate clientNodeOut.a.bits.source
invalidate clientNodeOut.a.bits.size
invalidate clientNodeOut.a.bits.param
invalidate clientNodeOut.a.bits.opcode
invalidate clientNodeOut.a.valid
invalidate clientNodeOut.a.ready
connect auto.client_out, clientNodeOut
wire manager_tl : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<8>, source : UInt<8>, address : UInt<64>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<8>, source : UInt<8>, address : UInt<64>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<8>, source : UInt<8>, address : UInt<64>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<8>, source : UInt<8>, sink : UInt<8>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<8>}}}
connect manager_tl.e.bits.sink, UInt<8>(0h0)
connect manager_tl.e.valid, UInt<1>(0h0)
connect manager_tl.e.ready, UInt<1>(0h0)
connect manager_tl.d.bits.corrupt, UInt<1>(0h0)
connect manager_tl.d.bits.data, UInt<64>(0h0)
connect manager_tl.d.bits.denied, UInt<1>(0h0)
connect manager_tl.d.bits.sink, UInt<8>(0h0)
connect manager_tl.d.bits.source, UInt<8>(0h0)
connect manager_tl.d.bits.size, UInt<8>(0h0)
connect manager_tl.d.bits.param, UInt<2>(0h0)
connect manager_tl.d.bits.opcode, UInt<3>(0h0)
connect manager_tl.d.valid, UInt<1>(0h0)
connect manager_tl.d.ready, UInt<1>(0h0)
connect manager_tl.c.bits.corrupt, UInt<1>(0h0)
connect manager_tl.c.bits.data, UInt<64>(0h0)
connect manager_tl.c.bits.address, UInt<64>(0h0)
connect manager_tl.c.bits.source, UInt<8>(0h0)
connect manager_tl.c.bits.size, UInt<8>(0h0)
connect manager_tl.c.bits.param, UInt<3>(0h0)
connect manager_tl.c.bits.opcode, UInt<3>(0h0)
connect manager_tl.c.valid, UInt<1>(0h0)
connect manager_tl.c.ready, UInt<1>(0h0)
connect manager_tl.b.bits.corrupt, UInt<1>(0h0)
connect manager_tl.b.bits.data, UInt<64>(0h0)
connect manager_tl.b.bits.mask, UInt<8>(0h0)
connect manager_tl.b.bits.address, UInt<64>(0h0)
connect manager_tl.b.bits.source, UInt<8>(0h0)
connect manager_tl.b.bits.size, UInt<8>(0h0)
connect manager_tl.b.bits.param, UInt<2>(0h0)
connect manager_tl.b.bits.opcode, UInt<3>(0h0)
connect manager_tl.b.valid, UInt<1>(0h0)
connect manager_tl.b.ready, UInt<1>(0h0)
connect manager_tl.a.bits.corrupt, UInt<1>(0h0)
connect manager_tl.a.bits.data, UInt<64>(0h0)
connect manager_tl.a.bits.mask, UInt<8>(0h0)
connect manager_tl.a.bits.address, UInt<64>(0h0)
connect manager_tl.a.bits.source, UInt<8>(0h0)
connect manager_tl.a.bits.size, UInt<8>(0h0)
connect manager_tl.a.bits.param, UInt<3>(0h0)
connect manager_tl.a.bits.opcode, UInt<3>(0h0)
connect manager_tl.a.valid, UInt<1>(0h0)
connect manager_tl.a.ready, UInt<1>(0h0)
inst out_channels_1_2 of TLDToBeat_serial_tl_0_a64d64s8k8z8c
connect out_channels_1_2.clock, clock
connect out_channels_1_2.reset, reset
wire _out_channels_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _out_channels_WIRE.bits.corrupt, UInt<1>(0h0)
connect _out_channels_WIRE.bits.data, UInt<64>(0h0)
connect _out_channels_WIRE.bits.mask, UInt<8>(0h0)
connect _out_channels_WIRE.bits.address, UInt<32>(0h0)
connect _out_channels_WIRE.bits.source, UInt<4>(0h0)
connect _out_channels_WIRE.bits.size, UInt<4>(0h0)
connect _out_channels_WIRE.bits.param, UInt<2>(0h0)
connect _out_channels_WIRE.bits.opcode, UInt<3>(0h0)
connect _out_channels_WIRE.valid, UInt<1>(0h0)
connect _out_channels_WIRE.ready, UInt<1>(0h0)
wire out_channels_3_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect out_channels_3_1.bits, _out_channels_WIRE.bits
connect out_channels_3_1.valid, _out_channels_WIRE.valid
connect out_channels_3_1.ready, _out_channels_WIRE.ready
inst out_channels_3_2 of TLBToBeat_serial_tl_0_a64d64s8k8z8c
connect out_channels_3_2.clock, clock
connect out_channels_3_2.reset, reset
connect io.ser[0].out.valid, UInt<1>(0h0)
connect io.ser[1].out.valid, UInt<1>(0h0)
connect io.ser[2].out.valid, UInt<1>(0h0)
connect io.ser[3].out.valid, UInt<1>(0h0)
connect io.ser[4].out.valid, UInt<1>(0h0)
invalidate io.ser[0].out.bits.flit
invalidate io.ser[1].out.bits.flit
invalidate io.ser[2].out.bits.flit
invalidate io.ser[3].out.bits.flit
invalidate io.ser[4].out.bits.flit
connect out_channels_1_2.io.protocol, clientNodeOut.d
inst ser_1 of GenericSerializer_TLBeatw67_f32
connect ser_1.clock, clock
connect ser_1.reset, reset
connect ser_1.io.in, out_channels_1_2.io.beat
connect io.ser[1].out.bits, ser_1.io.out.bits
connect io.ser[1].out.valid, ser_1.io.out.valid
connect ser_1.io.out.ready, io.ser[1].out.ready
connect out_channels_3_2.io.protocol, out_channels_3_1
inst ser_3 of GenericSerializer_TLBeatw87_f32
connect ser_3.clock, clock
connect ser_3.reset, reset
connect ser_3.io.in, out_channels_3_2.io.beat
connect io.ser[3].out.bits, ser_3.io.out.bits
connect io.ser[3].out.valid, ser_3.io.out.valid
connect ser_3.io.out.ready, io.ser[3].out.ready
node _io_debug_ser_busy_T = or(ser_1.io.busy, ser_3.io.busy)
connect io.debug.ser_busy, _io_debug_ser_busy_T
wire _in_channels_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<7>}}
connect _in_channels_WIRE.bits.sink, UInt<7>(0h0)
connect _in_channels_WIRE.valid, UInt<1>(0h0)
connect _in_channels_WIRE.ready, UInt<1>(0h0)
wire in_channels_0_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<7>}}
connect in_channels_0_1.bits, _in_channels_WIRE.bits
connect in_channels_0_1.valid, _in_channels_WIRE.valid
connect in_channels_0_1.ready, _in_channels_WIRE.ready
inst in_channels_0_2 of TLEFromBeat_serial_tl_0_a64d64s8k8z8c
connect in_channels_0_2.clock, clock
connect in_channels_0_2.reset, reset
inst in_channels_1_2 of TLDFromBeat_serial_tl_0_a64d64s8k8z8c
connect in_channels_1_2.clock, clock
connect in_channels_1_2.reset, reset
wire _in_channels_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _in_channels_WIRE_1.bits.corrupt, UInt<1>(0h0)
connect _in_channels_WIRE_1.bits.data, UInt<64>(0h0)
connect _in_channels_WIRE_1.bits.address, UInt<32>(0h0)
connect _in_channels_WIRE_1.bits.source, UInt<4>(0h0)
connect _in_channels_WIRE_1.bits.size, UInt<4>(0h0)
connect _in_channels_WIRE_1.bits.param, UInt<3>(0h0)
connect _in_channels_WIRE_1.bits.opcode, UInt<3>(0h0)
connect _in_channels_WIRE_1.valid, UInt<1>(0h0)
connect _in_channels_WIRE_1.ready, UInt<1>(0h0)
wire in_channels_2_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect in_channels_2_1.bits, _in_channels_WIRE_1.bits
connect in_channels_2_1.valid, _in_channels_WIRE_1.valid
connect in_channels_2_1.ready, _in_channels_WIRE_1.ready
inst in_channels_2_2 of TLCFromBeat_serial_tl_0_a64d64s8k8z8c
connect in_channels_2_2.clock, clock
connect in_channels_2_2.reset, reset
inst in_channels_3_2 of TLBFromBeat_serial_tl_0_a64d64s8k8z8c
connect in_channels_3_2.clock, clock
connect in_channels_3_2.reset, reset
inst in_channels_4_2 of TLAFromBeat_serial_tl_0_a64d64s8k8z8c
connect in_channels_4_2.clock, clock
connect in_channels_4_2.reset, reset
connect in_channels_0_1.bits, in_channels_0_2.io.protocol.bits
connect in_channels_0_1.valid, in_channels_0_2.io.protocol.valid
connect in_channels_0_2.io.protocol.ready, in_channels_0_1.ready
inst des_0 of GenericDeserializer_TLBeatw10_f32
connect des_0.clock, clock
connect des_0.reset, reset
connect des_0.io.in, io.ser[0].in
connect in_channels_0_2.io.beat, des_0.io.out
connect manager_tl.d.bits.corrupt, in_channels_1_2.io.protocol.bits.corrupt
connect manager_tl.d.bits.data, in_channels_1_2.io.protocol.bits.data
connect manager_tl.d.bits.denied, in_channels_1_2.io.protocol.bits.denied
connect manager_tl.d.bits.sink, in_channels_1_2.io.protocol.bits.sink
connect manager_tl.d.bits.source, in_channels_1_2.io.protocol.bits.source
connect manager_tl.d.bits.size, in_channels_1_2.io.protocol.bits.size
connect manager_tl.d.bits.param, in_channels_1_2.io.protocol.bits.param
connect manager_tl.d.bits.opcode, in_channels_1_2.io.protocol.bits.opcode
connect manager_tl.d.valid, in_channels_1_2.io.protocol.valid
connect in_channels_1_2.io.protocol.ready, manager_tl.d.ready
inst des_1 of GenericDeserializer_TLBeatw67_f32
connect des_1.clock, clock
connect des_1.reset, reset
connect des_1.io.in, io.ser[1].in
connect in_channels_1_2.io.beat, des_1.io.out
connect in_channels_2_1.bits, in_channels_2_2.io.protocol.bits
connect in_channels_2_1.valid, in_channels_2_2.io.protocol.valid
connect in_channels_2_2.io.protocol.ready, in_channels_2_1.ready
inst des_2 of GenericDeserializer_TLBeatw88_f32
connect des_2.clock, clock
connect des_2.reset, reset
connect des_2.io.in, io.ser[2].in
connect in_channels_2_2.io.beat, des_2.io.out
connect manager_tl.b.bits.corrupt, in_channels_3_2.io.protocol.bits.corrupt
connect manager_tl.b.bits.data, in_channels_3_2.io.protocol.bits.data
connect manager_tl.b.bits.mask, in_channels_3_2.io.protocol.bits.mask
connect manager_tl.b.bits.address, in_channels_3_2.io.protocol.bits.address
connect manager_tl.b.bits.source, in_channels_3_2.io.protocol.bits.source
connect manager_tl.b.bits.size, in_channels_3_2.io.protocol.bits.size
connect manager_tl.b.bits.param, in_channels_3_2.io.protocol.bits.param
connect manager_tl.b.bits.opcode, in_channels_3_2.io.protocol.bits.opcode
connect manager_tl.b.valid, in_channels_3_2.io.protocol.valid
connect in_channels_3_2.io.protocol.ready, manager_tl.b.ready
inst des_3 of GenericDeserializer_TLBeatw87_f32
connect des_3.clock, clock
connect des_3.reset, reset
connect des_3.io.in, io.ser[3].in
connect in_channels_3_2.io.beat, des_3.io.out
connect clientNodeOut.a.bits, in_channels_4_2.io.protocol.bits
connect clientNodeOut.a.valid, in_channels_4_2.io.protocol.valid
connect in_channels_4_2.io.protocol.ready, clientNodeOut.a.ready
inst des_4 of GenericDeserializer_TLBeatw88_f32_1
connect des_4.clock, clock
connect des_4.reset, reset
connect des_4.io.in, io.ser[4].in
connect in_channels_4_2.io.beat, des_4.io.out
node _io_debug_des_busy_T = or(des_0.io.busy, des_1.io.busy)
node _io_debug_des_busy_T_1 = or(_io_debug_des_busy_T, des_2.io.busy)
node _io_debug_des_busy_T_2 = or(_io_debug_des_busy_T_1, des_3.io.busy)
node _io_debug_des_busy_T_3 = or(_io_debug_des_busy_T_2, des_4.io.busy)
connect io.debug.des_busy, _io_debug_des_busy_T_3 | module TLSerdesser_serial_tl_0( // @[TLSerdes.scala:39:9]
input clock, // @[TLSerdes.scala:39:9]
input reset, // @[TLSerdes.scala:39:9]
input auto_client_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_client_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_client_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_client_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_client_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_client_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_client_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_client_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_client_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_client_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_client_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_client_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_client_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_client_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_client_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_client_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_client_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_client_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_client_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_client_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output io_ser_0_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_0_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_0_in_bits_flit, // @[TLSerdes.scala:40:16]
output io_ser_1_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_1_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_1_in_bits_flit, // @[TLSerdes.scala:40:16]
input io_ser_1_out_ready, // @[TLSerdes.scala:40:16]
output io_ser_1_out_valid, // @[TLSerdes.scala:40:16]
output [31:0] io_ser_1_out_bits_flit, // @[TLSerdes.scala:40:16]
output io_ser_2_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_2_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_2_in_bits_flit, // @[TLSerdes.scala:40:16]
output io_ser_3_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_3_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_3_in_bits_flit, // @[TLSerdes.scala:40:16]
input io_ser_3_out_ready, // @[TLSerdes.scala:40:16]
output io_ser_3_out_valid, // @[TLSerdes.scala:40:16]
output [31:0] io_ser_3_out_bits_flit, // @[TLSerdes.scala:40:16]
output io_ser_4_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_4_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_4_in_bits_flit, // @[TLSerdes.scala:40:16]
output io_debug_ser_busy, // @[TLSerdes.scala:40:16]
output io_debug_des_busy // @[TLSerdes.scala:40:16]
);
wire _des_4_io_out_valid; // @[TLSerdes.scala:86:23]
wire [85:0] _des_4_io_out_bits_payload; // @[TLSerdes.scala:86:23]
wire _des_4_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_4_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _des_4_io_busy; // @[TLSerdes.scala:86:23]
wire _des_3_io_out_valid; // @[TLSerdes.scala:86:23]
wire [84:0] _des_3_io_out_bits_payload; // @[TLSerdes.scala:86:23]
wire _des_3_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_3_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _des_3_io_busy; // @[TLSerdes.scala:86:23]
wire _des_2_io_out_valid; // @[TLSerdes.scala:86:23]
wire [85:0] _des_2_io_out_bits_payload; // @[TLSerdes.scala:86:23]
wire _des_2_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_2_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _des_2_io_busy; // @[TLSerdes.scala:86:23]
wire _des_1_io_out_valid; // @[TLSerdes.scala:86:23]
wire [64:0] _des_1_io_out_bits_payload; // @[TLSerdes.scala:86:23]
wire _des_1_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_1_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _des_0_io_out_valid; // @[TLSerdes.scala:86:23]
wire [7:0] _des_0_io_out_bits_payload; // @[TLSerdes.scala:86:23]
wire _des_0_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_0_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire [7:0] _in_channels_4_2_io_protocol_bits_size; // @[TLSerdes.scala:82:28]
wire [7:0] _in_channels_4_2_io_protocol_bits_source; // @[TLSerdes.scala:82:28]
wire [63:0] _in_channels_4_2_io_protocol_bits_address; // @[TLSerdes.scala:82:28]
wire _in_channels_4_2_io_beat_ready; // @[TLSerdes.scala:82:28]
wire _in_channels_3_2_io_beat_ready; // @[TLSerdes.scala:81:28]
wire [7:0] _in_channels_2_2_io_protocol_bits_size; // @[TLSerdes.scala:80:28]
wire [7:0] _in_channels_2_2_io_protocol_bits_source; // @[TLSerdes.scala:80:28]
wire [63:0] _in_channels_2_2_io_protocol_bits_address; // @[TLSerdes.scala:80:28]
wire _in_channels_2_2_io_beat_ready; // @[TLSerdes.scala:80:28]
wire _in_channels_1_2_io_beat_ready; // @[TLSerdes.scala:79:28]
wire [7:0] _in_channels_0_2_io_protocol_bits_sink; // @[TLSerdes.scala:78:28]
wire _in_channels_0_2_io_beat_ready; // @[TLSerdes.scala:78:28]
wire _ser_3_io_in_ready; // @[TLSerdes.scala:69:23]
wire _ser_3_io_busy; // @[TLSerdes.scala:69:23]
wire _ser_1_io_in_ready; // @[TLSerdes.scala:69:23]
wire _ser_1_io_busy; // @[TLSerdes.scala:69:23]
wire _out_channels_3_2_io_beat_bits_head; // @[TLSerdes.scala:62:50]
wire _out_channels_3_2_io_beat_bits_tail; // @[TLSerdes.scala:62:50]
wire _out_channels_1_2_io_beat_valid; // @[TLSerdes.scala:60:50]
wire [64:0] _out_channels_1_2_io_beat_bits_payload; // @[TLSerdes.scala:60:50]
wire _out_channels_1_2_io_beat_bits_head; // @[TLSerdes.scala:60:50]
wire _out_channels_1_2_io_beat_bits_tail; // @[TLSerdes.scala:60:50]
wire auto_client_out_a_ready_0 = auto_client_out_a_ready; // @[TLSerdes.scala:39:9]
wire auto_client_out_d_valid_0 = auto_client_out_d_valid; // @[TLSerdes.scala:39:9]
wire [2:0] auto_client_out_d_bits_opcode_0 = auto_client_out_d_bits_opcode; // @[TLSerdes.scala:39:9]
wire [1:0] auto_client_out_d_bits_param_0 = auto_client_out_d_bits_param; // @[TLSerdes.scala:39:9]
wire [3:0] auto_client_out_d_bits_size_0 = auto_client_out_d_bits_size; // @[TLSerdes.scala:39:9]
wire [3:0] auto_client_out_d_bits_source_0 = auto_client_out_d_bits_source; // @[TLSerdes.scala:39:9]
wire [6:0] auto_client_out_d_bits_sink_0 = auto_client_out_d_bits_sink; // @[TLSerdes.scala:39:9]
wire auto_client_out_d_bits_denied_0 = auto_client_out_d_bits_denied; // @[TLSerdes.scala:39:9]
wire [63:0] auto_client_out_d_bits_data_0 = auto_client_out_d_bits_data; // @[TLSerdes.scala:39:9]
wire auto_client_out_d_bits_corrupt_0 = auto_client_out_d_bits_corrupt; // @[TLSerdes.scala:39:9]
wire io_ser_0_in_valid_0 = io_ser_0_in_valid; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_0_in_bits_flit_0 = io_ser_0_in_bits_flit; // @[TLSerdes.scala:39:9]
wire io_ser_1_in_valid_0 = io_ser_1_in_valid; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_1_in_bits_flit_0 = io_ser_1_in_bits_flit; // @[TLSerdes.scala:39:9]
wire io_ser_1_out_ready_0 = io_ser_1_out_ready; // @[TLSerdes.scala:39:9]
wire io_ser_2_in_valid_0 = io_ser_2_in_valid; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_2_in_bits_flit_0 = io_ser_2_in_bits_flit; // @[TLSerdes.scala:39:9]
wire io_ser_3_in_valid_0 = io_ser_3_in_valid; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_3_in_bits_flit_0 = io_ser_3_in_bits_flit; // @[TLSerdes.scala:39:9]
wire io_ser_3_out_ready_0 = io_ser_3_out_ready; // @[TLSerdes.scala:39:9]
wire io_ser_4_in_valid_0 = io_ser_4_in_valid; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_4_in_bits_flit_0 = io_ser_4_in_bits_flit; // @[TLSerdes.scala:39:9]
wire [6:0] _in_channels_WIRE_bits_sink = 7'h0; // @[Bundles.scala:267:74]
wire [1:0] _out_channels_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] out_channels_3_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [7:0] manager_tl_a_bits_size = 8'h0; // @[TLSerdes.scala:47:72]
wire [7:0] manager_tl_a_bits_source = 8'h0; // @[TLSerdes.scala:47:72]
wire [7:0] manager_tl_a_bits_mask = 8'h0; // @[TLSerdes.scala:47:72]
wire [7:0] manager_tl_c_bits_size = 8'h0; // @[TLSerdes.scala:47:72]
wire [7:0] manager_tl_c_bits_source = 8'h0; // @[TLSerdes.scala:47:72]
wire [7:0] manager_tl_e_bits_sink = 8'h0; // @[TLSerdes.scala:47:72]
wire [7:0] _out_channels_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] out_channels_3_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [2:0] manager_tl_a_bits_opcode = 3'h0; // @[TLSerdes.scala:47:72]
wire [2:0] manager_tl_a_bits_param = 3'h0; // @[TLSerdes.scala:47:72]
wire [2:0] manager_tl_c_bits_opcode = 3'h0; // @[TLSerdes.scala:47:72]
wire [2:0] manager_tl_c_bits_param = 3'h0; // @[TLSerdes.scala:47:72]
wire [2:0] _out_channels_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] out_channels_3_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _in_channels_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _in_channels_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [3:0] _out_channels_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _out_channels_WIRE_bits_source = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] out_channels_3_1_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] out_channels_3_1_bits_source = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _in_channels_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _in_channels_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [63:0] manager_tl_a_bits_address = 64'h0; // @[TLSerdes.scala:47:72]
wire [63:0] manager_tl_a_bits_data = 64'h0; // @[TLSerdes.scala:47:72]
wire [63:0] manager_tl_c_bits_address = 64'h0; // @[TLSerdes.scala:47:72]
wire [63:0] manager_tl_c_bits_data = 64'h0; // @[TLSerdes.scala:47:72]
wire [63:0] _out_channels_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] out_channels_3_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _in_channels_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [31:0] io_ser_0_out_bits_flit = 32'h0; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_2_out_bits_flit = 32'h0; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_4_out_bits_flit = 32'h0; // @[TLSerdes.scala:39:9]
wire [31:0] _out_channels_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] out_channels_3_1_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _in_channels_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire io_ser_0_out_valid = 1'h0; // @[TLSerdes.scala:39:9]
wire io_ser_2_out_valid = 1'h0; // @[TLSerdes.scala:39:9]
wire io_ser_4_out_valid = 1'h0; // @[TLSerdes.scala:39:9]
wire manager_tl_a_ready = 1'h0; // @[TLSerdes.scala:47:72]
wire manager_tl_a_valid = 1'h0; // @[TLSerdes.scala:47:72]
wire manager_tl_a_bits_corrupt = 1'h0; // @[TLSerdes.scala:47:72]
wire manager_tl_b_ready = 1'h0; // @[TLSerdes.scala:47:72]
wire manager_tl_c_ready = 1'h0; // @[TLSerdes.scala:47:72]
wire manager_tl_c_valid = 1'h0; // @[TLSerdes.scala:47:72]
wire manager_tl_c_bits_corrupt = 1'h0; // @[TLSerdes.scala:47:72]
wire manager_tl_d_ready = 1'h0; // @[TLSerdes.scala:47:72]
wire manager_tl_e_ready = 1'h0; // @[TLSerdes.scala:47:72]
wire manager_tl_e_valid = 1'h0; // @[TLSerdes.scala:47:72]
wire _out_channels_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _out_channels_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _out_channels_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire out_channels_3_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire out_channels_3_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _in_channels_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _in_channels_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire in_channels_0_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _in_channels_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:74]
wire _in_channels_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:74]
wire _in_channels_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire in_channels_2_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire io_ser_0_out_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :62:50]
wire io_ser_2_out_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :62:50]
wire io_ser_4_out_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :62:50]
wire out_channels_3_1_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :62:50]
wire clientNodeOut_a_ready = auto_client_out_a_ready_0; // @[TLSerdes.scala:39:9]
wire clientNodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] clientNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] clientNodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] clientNodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] clientNodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] clientNodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] clientNodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] clientNodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire clientNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire clientNodeOut_d_ready; // @[MixedNode.scala:542:17]
wire clientNodeOut_d_valid = auto_client_out_d_valid_0; // @[TLSerdes.scala:39:9]
wire [2:0] clientNodeOut_d_bits_opcode = auto_client_out_d_bits_opcode_0; // @[TLSerdes.scala:39:9]
wire [1:0] clientNodeOut_d_bits_param = auto_client_out_d_bits_param_0; // @[TLSerdes.scala:39:9]
wire [3:0] clientNodeOut_d_bits_size = auto_client_out_d_bits_size_0; // @[TLSerdes.scala:39:9]
wire [3:0] clientNodeOut_d_bits_source = auto_client_out_d_bits_source_0; // @[TLSerdes.scala:39:9]
wire [6:0] clientNodeOut_d_bits_sink = auto_client_out_d_bits_sink_0; // @[TLSerdes.scala:39:9]
wire clientNodeOut_d_bits_denied = auto_client_out_d_bits_denied_0; // @[TLSerdes.scala:39:9]
wire [63:0] clientNodeOut_d_bits_data = auto_client_out_d_bits_data_0; // @[TLSerdes.scala:39:9]
wire clientNodeOut_d_bits_corrupt = auto_client_out_d_bits_corrupt_0; // @[TLSerdes.scala:39:9]
wire _io_debug_ser_busy_T; // @[package.scala:81:59]
wire _io_debug_des_busy_T_3; // @[package.scala:81:59]
wire [2:0] auto_client_out_a_bits_opcode_0; // @[TLSerdes.scala:39:9]
wire [2:0] auto_client_out_a_bits_param_0; // @[TLSerdes.scala:39:9]
wire [3:0] auto_client_out_a_bits_size_0; // @[TLSerdes.scala:39:9]
wire [3:0] auto_client_out_a_bits_source_0; // @[TLSerdes.scala:39:9]
wire [31:0] auto_client_out_a_bits_address_0; // @[TLSerdes.scala:39:9]
wire [7:0] auto_client_out_a_bits_mask_0; // @[TLSerdes.scala:39:9]
wire [63:0] auto_client_out_a_bits_data_0; // @[TLSerdes.scala:39:9]
wire auto_client_out_a_bits_corrupt_0; // @[TLSerdes.scala:39:9]
wire auto_client_out_a_valid_0; // @[TLSerdes.scala:39:9]
wire auto_client_out_d_ready_0; // @[TLSerdes.scala:39:9]
wire io_ser_0_in_ready_0; // @[TLSerdes.scala:39:9]
wire io_ser_1_in_ready_0; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_1_out_bits_flit_0; // @[TLSerdes.scala:39:9]
wire io_ser_1_out_valid_0; // @[TLSerdes.scala:39:9]
wire io_ser_2_in_ready_0; // @[TLSerdes.scala:39:9]
wire io_ser_3_in_ready_0; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_3_out_bits_flit_0; // @[TLSerdes.scala:39:9]
wire io_ser_3_out_valid_0; // @[TLSerdes.scala:39:9]
wire io_ser_4_in_ready_0; // @[TLSerdes.scala:39:9]
wire io_debug_ser_busy_0; // @[TLSerdes.scala:39:9]
wire io_debug_des_busy_0; // @[TLSerdes.scala:39:9]
assign auto_client_out_a_valid_0 = clientNodeOut_a_valid; // @[TLSerdes.scala:39:9]
assign auto_client_out_a_bits_opcode_0 = clientNodeOut_a_bits_opcode; // @[TLSerdes.scala:39:9]
assign auto_client_out_a_bits_param_0 = clientNodeOut_a_bits_param; // @[TLSerdes.scala:39:9]
assign auto_client_out_a_bits_size_0 = clientNodeOut_a_bits_size; // @[TLSerdes.scala:39:9]
assign auto_client_out_a_bits_source_0 = clientNodeOut_a_bits_source; // @[TLSerdes.scala:39:9]
assign auto_client_out_a_bits_address_0 = clientNodeOut_a_bits_address; // @[TLSerdes.scala:39:9]
assign auto_client_out_a_bits_mask_0 = clientNodeOut_a_bits_mask; // @[TLSerdes.scala:39:9]
assign auto_client_out_a_bits_data_0 = clientNodeOut_a_bits_data; // @[TLSerdes.scala:39:9]
assign auto_client_out_a_bits_corrupt_0 = clientNodeOut_a_bits_corrupt; // @[TLSerdes.scala:39:9]
assign auto_client_out_d_ready_0 = clientNodeOut_d_ready; // @[TLSerdes.scala:39:9]
wire [2:0] manager_tl_b_bits_opcode; // @[TLSerdes.scala:47:72]
wire [1:0] manager_tl_b_bits_param; // @[TLSerdes.scala:47:72]
wire [7:0] manager_tl_b_bits_size; // @[TLSerdes.scala:47:72]
wire [7:0] manager_tl_b_bits_source; // @[TLSerdes.scala:47:72]
wire [63:0] manager_tl_b_bits_address; // @[TLSerdes.scala:47:72]
wire [7:0] manager_tl_b_bits_mask; // @[TLSerdes.scala:47:72]
wire [63:0] manager_tl_b_bits_data; // @[TLSerdes.scala:47:72]
wire manager_tl_b_bits_corrupt; // @[TLSerdes.scala:47:72]
wire manager_tl_b_valid; // @[TLSerdes.scala:47:72]
wire [2:0] manager_tl_d_bits_opcode; // @[TLSerdes.scala:47:72]
wire [1:0] manager_tl_d_bits_param; // @[TLSerdes.scala:47:72]
wire [7:0] manager_tl_d_bits_size; // @[TLSerdes.scala:47:72]
wire [7:0] manager_tl_d_bits_source; // @[TLSerdes.scala:47:72]
wire [7:0] manager_tl_d_bits_sink; // @[TLSerdes.scala:47:72]
wire manager_tl_d_bits_denied; // @[TLSerdes.scala:47:72]
wire [63:0] manager_tl_d_bits_data; // @[TLSerdes.scala:47:72]
wire manager_tl_d_bits_corrupt; // @[TLSerdes.scala:47:72]
wire manager_tl_d_valid; // @[TLSerdes.scala:47:72]
assign _io_debug_ser_busy_T = _ser_1_io_busy | _ser_3_io_busy; // @[TLSerdes.scala:69:23]
assign io_debug_ser_busy_0 = _io_debug_ser_busy_T; // @[TLSerdes.scala:39:9]
wire [6:0] in_channels_0_1_bits_sink; // @[Bundles.scala:267:61]
wire in_channels_0_1_valid; // @[Bundles.scala:267:61]
wire [2:0] in_channels_2_1_bits_opcode; // @[Bundles.scala:265:61]
wire [2:0] in_channels_2_1_bits_param; // @[Bundles.scala:265:61]
wire [3:0] in_channels_2_1_bits_size; // @[Bundles.scala:265:61]
wire [3:0] in_channels_2_1_bits_source; // @[Bundles.scala:265:61]
wire [31:0] in_channels_2_1_bits_address; // @[Bundles.scala:265:61]
wire [63:0] in_channels_2_1_bits_data; // @[Bundles.scala:265:61]
wire in_channels_2_1_bits_corrupt; // @[Bundles.scala:265:61]
wire in_channels_2_1_valid; // @[Bundles.scala:265:61]
assign in_channels_0_1_bits_sink = _in_channels_0_2_io_protocol_bits_sink[6:0]; // @[TLSerdes.scala:78:28, :85:9]
assign in_channels_2_1_bits_size = _in_channels_2_2_io_protocol_bits_size[3:0]; // @[TLSerdes.scala:80:28, :85:9]
assign in_channels_2_1_bits_source = _in_channels_2_2_io_protocol_bits_source[3:0]; // @[TLSerdes.scala:80:28, :85:9]
assign in_channels_2_1_bits_address = _in_channels_2_2_io_protocol_bits_address[31:0]; // @[TLSerdes.scala:80:28, :85:9]
assign clientNodeOut_a_bits_size = _in_channels_4_2_io_protocol_bits_size[3:0]; // @[TLSerdes.scala:82:28, :85:9]
assign clientNodeOut_a_bits_source = _in_channels_4_2_io_protocol_bits_source[3:0]; // @[TLSerdes.scala:82:28, :85:9]
assign clientNodeOut_a_bits_address = _in_channels_4_2_io_protocol_bits_address[31:0]; // @[TLSerdes.scala:82:28, :85:9]
wire _io_debug_des_busy_T; // @[package.scala:81:59]
wire _io_debug_des_busy_T_1 = _io_debug_des_busy_T | _des_2_io_busy; // @[TLSerdes.scala:86:23]
wire _io_debug_des_busy_T_2 = _io_debug_des_busy_T_1 | _des_3_io_busy; // @[TLSerdes.scala:86:23]
assign _io_debug_des_busy_T_3 = _io_debug_des_busy_T_2 | _des_4_io_busy; // @[TLSerdes.scala:86:23]
assign io_debug_des_busy_0 = _io_debug_des_busy_T_3; // @[TLSerdes.scala:39:9]
TLDToBeat_serial_tl_0_a64d64s8k8z8c out_channels_1_2 ( // @[TLSerdes.scala:60:50]
.clock (clock),
.reset (reset),
.io_protocol_ready (clientNodeOut_d_ready),
.io_protocol_valid (clientNodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_protocol_bits_opcode (clientNodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_protocol_bits_param (clientNodeOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_protocol_bits_size ({4'h0, clientNodeOut_d_bits_size}), // @[TLSerdes.scala:68:21]
.io_protocol_bits_source ({4'h0, clientNodeOut_d_bits_source}), // @[TLSerdes.scala:68:21]
.io_protocol_bits_sink ({1'h0, clientNodeOut_d_bits_sink}), // @[TLSerdes.scala:68:21]
.io_protocol_bits_denied (clientNodeOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_protocol_bits_data (clientNodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_protocol_bits_corrupt (clientNodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_beat_ready (_ser_1_io_in_ready), // @[TLSerdes.scala:69:23]
.io_beat_valid (_out_channels_1_2_io_beat_valid),
.io_beat_bits_payload (_out_channels_1_2_io_beat_bits_payload),
.io_beat_bits_head (_out_channels_1_2_io_beat_bits_head),
.io_beat_bits_tail (_out_channels_1_2_io_beat_bits_tail)
); // @[TLSerdes.scala:60:50]
TLBToBeat_serial_tl_0_a64d64s8k8z8c out_channels_3_2 ( // @[TLSerdes.scala:62:50]
.clock (clock),
.reset (reset),
.io_beat_ready (_ser_3_io_in_ready), // @[TLSerdes.scala:69:23]
.io_beat_bits_head (_out_channels_3_2_io_beat_bits_head),
.io_beat_bits_tail (_out_channels_3_2_io_beat_bits_tail)
); // @[TLSerdes.scala:62:50]
GenericSerializer_TLBeatw67_f32 ser_1 ( // @[TLSerdes.scala:69:23]
.clock (clock),
.reset (reset),
.io_in_ready (_ser_1_io_in_ready),
.io_in_valid (_out_channels_1_2_io_beat_valid), // @[TLSerdes.scala:60:50]
.io_in_bits_payload (_out_channels_1_2_io_beat_bits_payload), // @[TLSerdes.scala:60:50]
.io_in_bits_head (_out_channels_1_2_io_beat_bits_head), // @[TLSerdes.scala:60:50]
.io_in_bits_tail (_out_channels_1_2_io_beat_bits_tail), // @[TLSerdes.scala:60:50]
.io_out_ready (io_ser_1_out_ready_0), // @[TLSerdes.scala:39:9]
.io_out_valid (io_ser_1_out_valid_0),
.io_out_bits_flit (io_ser_1_out_bits_flit_0),
.io_busy (_ser_1_io_busy)
); // @[TLSerdes.scala:69:23]
GenericSerializer_TLBeatw87_f32 ser_3 ( // @[TLSerdes.scala:69:23]
.clock (clock),
.reset (reset),
.io_in_ready (_ser_3_io_in_ready),
.io_in_bits_head (_out_channels_3_2_io_beat_bits_head), // @[TLSerdes.scala:62:50]
.io_in_bits_tail (_out_channels_3_2_io_beat_bits_tail), // @[TLSerdes.scala:62:50]
.io_out_ready (io_ser_3_out_ready_0), // @[TLSerdes.scala:39:9]
.io_out_valid (io_ser_3_out_valid_0),
.io_out_bits_flit (io_ser_3_out_bits_flit_0),
.io_busy (_ser_3_io_busy)
); // @[TLSerdes.scala:69:23]
TLEFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_0_2 ( // @[TLSerdes.scala:78:28]
.clock (clock),
.reset (reset),
.io_protocol_valid (in_channels_0_1_valid),
.io_protocol_bits_sink (_in_channels_0_2_io_protocol_bits_sink),
.io_beat_ready (_in_channels_0_2_io_beat_ready),
.io_beat_valid (_des_0_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_payload (_des_0_io_out_bits_payload), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_0_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_0_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:78:28]
TLDFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_1_2 ( // @[TLSerdes.scala:79:28]
.clock (clock),
.reset (reset),
.io_protocol_valid (manager_tl_d_valid),
.io_protocol_bits_opcode (manager_tl_d_bits_opcode),
.io_protocol_bits_param (manager_tl_d_bits_param),
.io_protocol_bits_size (manager_tl_d_bits_size),
.io_protocol_bits_source (manager_tl_d_bits_source),
.io_protocol_bits_sink (manager_tl_d_bits_sink),
.io_protocol_bits_denied (manager_tl_d_bits_denied),
.io_protocol_bits_data (manager_tl_d_bits_data),
.io_protocol_bits_corrupt (manager_tl_d_bits_corrupt),
.io_beat_ready (_in_channels_1_2_io_beat_ready),
.io_beat_valid (_des_1_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_payload (_des_1_io_out_bits_payload), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_1_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_1_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:79:28]
TLCFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_2_2 ( // @[TLSerdes.scala:80:28]
.clock (clock),
.reset (reset),
.io_protocol_valid (in_channels_2_1_valid),
.io_protocol_bits_opcode (in_channels_2_1_bits_opcode),
.io_protocol_bits_param (in_channels_2_1_bits_param),
.io_protocol_bits_size (_in_channels_2_2_io_protocol_bits_size),
.io_protocol_bits_source (_in_channels_2_2_io_protocol_bits_source),
.io_protocol_bits_address (_in_channels_2_2_io_protocol_bits_address),
.io_protocol_bits_data (in_channels_2_1_bits_data),
.io_protocol_bits_corrupt (in_channels_2_1_bits_corrupt),
.io_beat_ready (_in_channels_2_2_io_beat_ready),
.io_beat_valid (_des_2_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_payload (_des_2_io_out_bits_payload), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_2_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_2_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:80:28]
TLBFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_3_2 ( // @[TLSerdes.scala:81:28]
.clock (clock),
.reset (reset),
.io_protocol_valid (manager_tl_b_valid),
.io_protocol_bits_opcode (manager_tl_b_bits_opcode),
.io_protocol_bits_param (manager_tl_b_bits_param),
.io_protocol_bits_size (manager_tl_b_bits_size),
.io_protocol_bits_source (manager_tl_b_bits_source),
.io_protocol_bits_address (manager_tl_b_bits_address),
.io_protocol_bits_mask (manager_tl_b_bits_mask),
.io_protocol_bits_data (manager_tl_b_bits_data),
.io_protocol_bits_corrupt (manager_tl_b_bits_corrupt),
.io_beat_ready (_in_channels_3_2_io_beat_ready),
.io_beat_valid (_des_3_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_payload (_des_3_io_out_bits_payload), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_3_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_3_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:81:28]
TLAFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_4_2 ( // @[TLSerdes.scala:82:28]
.clock (clock),
.reset (reset),
.io_protocol_ready (clientNodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_protocol_valid (clientNodeOut_a_valid),
.io_protocol_bits_opcode (clientNodeOut_a_bits_opcode),
.io_protocol_bits_param (clientNodeOut_a_bits_param),
.io_protocol_bits_size (_in_channels_4_2_io_protocol_bits_size),
.io_protocol_bits_source (_in_channels_4_2_io_protocol_bits_source),
.io_protocol_bits_address (_in_channels_4_2_io_protocol_bits_address),
.io_protocol_bits_mask (clientNodeOut_a_bits_mask),
.io_protocol_bits_data (clientNodeOut_a_bits_data),
.io_protocol_bits_corrupt (clientNodeOut_a_bits_corrupt),
.io_beat_ready (_in_channels_4_2_io_beat_ready),
.io_beat_valid (_des_4_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_payload (_des_4_io_out_bits_payload), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_4_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_4_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:82:28]
GenericDeserializer_TLBeatw10_f32 des_0 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_0_in_ready_0),
.io_in_valid (io_ser_0_in_valid_0), // @[TLSerdes.scala:39:9]
.io_in_bits_flit (io_ser_0_in_bits_flit_0), // @[TLSerdes.scala:39:9]
.io_out_ready (_in_channels_0_2_io_beat_ready), // @[TLSerdes.scala:78:28]
.io_out_valid (_des_0_io_out_valid),
.io_out_bits_payload (_des_0_io_out_bits_payload),
.io_out_bits_head (_des_0_io_out_bits_head),
.io_out_bits_tail (_des_0_io_out_bits_tail)
); // @[TLSerdes.scala:86:23]
GenericDeserializer_TLBeatw67_f32 des_1 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_1_in_ready_0),
.io_in_valid (io_ser_1_in_valid_0), // @[TLSerdes.scala:39:9]
.io_in_bits_flit (io_ser_1_in_bits_flit_0), // @[TLSerdes.scala:39:9]
.io_out_ready (_in_channels_1_2_io_beat_ready), // @[TLSerdes.scala:79:28]
.io_out_valid (_des_1_io_out_valid),
.io_out_bits_payload (_des_1_io_out_bits_payload),
.io_out_bits_head (_des_1_io_out_bits_head),
.io_out_bits_tail (_des_1_io_out_bits_tail),
.io_busy (_io_debug_des_busy_T)
); // @[TLSerdes.scala:86:23]
GenericDeserializer_TLBeatw88_f32 des_2 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_2_in_ready_0),
.io_in_valid (io_ser_2_in_valid_0), // @[TLSerdes.scala:39:9]
.io_in_bits_flit (io_ser_2_in_bits_flit_0), // @[TLSerdes.scala:39:9]
.io_out_ready (_in_channels_2_2_io_beat_ready), // @[TLSerdes.scala:80:28]
.io_out_valid (_des_2_io_out_valid),
.io_out_bits_payload (_des_2_io_out_bits_payload),
.io_out_bits_head (_des_2_io_out_bits_head),
.io_out_bits_tail (_des_2_io_out_bits_tail),
.io_busy (_des_2_io_busy)
); // @[TLSerdes.scala:86:23]
GenericDeserializer_TLBeatw87_f32 des_3 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_3_in_ready_0),
.io_in_valid (io_ser_3_in_valid_0), // @[TLSerdes.scala:39:9]
.io_in_bits_flit (io_ser_3_in_bits_flit_0), // @[TLSerdes.scala:39:9]
.io_out_ready (_in_channels_3_2_io_beat_ready), // @[TLSerdes.scala:81:28]
.io_out_valid (_des_3_io_out_valid),
.io_out_bits_payload (_des_3_io_out_bits_payload),
.io_out_bits_head (_des_3_io_out_bits_head),
.io_out_bits_tail (_des_3_io_out_bits_tail),
.io_busy (_des_3_io_busy)
); // @[TLSerdes.scala:86:23]
GenericDeserializer_TLBeatw88_f32_1 des_4 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_4_in_ready_0),
.io_in_valid (io_ser_4_in_valid_0), // @[TLSerdes.scala:39:9]
.io_in_bits_flit (io_ser_4_in_bits_flit_0), // @[TLSerdes.scala:39:9]
.io_out_ready (_in_channels_4_2_io_beat_ready), // @[TLSerdes.scala:82:28]
.io_out_valid (_des_4_io_out_valid),
.io_out_bits_payload (_des_4_io_out_bits_payload),
.io_out_bits_head (_des_4_io_out_bits_head),
.io_out_bits_tail (_des_4_io_out_bits_tail),
.io_busy (_des_4_io_busy)
); // @[TLSerdes.scala:86:23]
assign auto_client_out_a_valid = auto_client_out_a_valid_0; // @[TLSerdes.scala:39:9]
assign auto_client_out_a_bits_opcode = auto_client_out_a_bits_opcode_0; // @[TLSerdes.scala:39:9]
assign auto_client_out_a_bits_param = auto_client_out_a_bits_param_0; // @[TLSerdes.scala:39:9]
assign auto_client_out_a_bits_size = auto_client_out_a_bits_size_0; // @[TLSerdes.scala:39:9]
assign auto_client_out_a_bits_source = auto_client_out_a_bits_source_0; // @[TLSerdes.scala:39:9]
assign auto_client_out_a_bits_address = auto_client_out_a_bits_address_0; // @[TLSerdes.scala:39:9]
assign auto_client_out_a_bits_mask = auto_client_out_a_bits_mask_0; // @[TLSerdes.scala:39:9]
assign auto_client_out_a_bits_data = auto_client_out_a_bits_data_0; // @[TLSerdes.scala:39:9]
assign auto_client_out_a_bits_corrupt = auto_client_out_a_bits_corrupt_0; // @[TLSerdes.scala:39:9]
assign auto_client_out_d_ready = auto_client_out_d_ready_0; // @[TLSerdes.scala:39:9]
assign io_ser_0_in_ready = io_ser_0_in_ready_0; // @[TLSerdes.scala:39:9]
assign io_ser_1_in_ready = io_ser_1_in_ready_0; // @[TLSerdes.scala:39:9]
assign io_ser_1_out_valid = io_ser_1_out_valid_0; // @[TLSerdes.scala:39:9]
assign io_ser_1_out_bits_flit = io_ser_1_out_bits_flit_0; // @[TLSerdes.scala:39:9]
assign io_ser_2_in_ready = io_ser_2_in_ready_0; // @[TLSerdes.scala:39:9]
assign io_ser_3_in_ready = io_ser_3_in_ready_0; // @[TLSerdes.scala:39:9]
assign io_ser_3_out_valid = io_ser_3_out_valid_0; // @[TLSerdes.scala:39:9]
assign io_ser_3_out_bits_flit = io_ser_3_out_bits_flit_0; // @[TLSerdes.scala:39:9]
assign io_ser_4_in_ready = io_ser_4_in_ready_0; // @[TLSerdes.scala:39:9]
assign io_debug_ser_busy = io_debug_ser_busy_0; // @[TLSerdes.scala:39:9]
assign io_debug_des_busy = io_debug_des_busy_0; // @[TLSerdes.scala:39:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module FullyPortedRF_3 :
input clock : Clock
input reset : Reset
output io : { flip arb_read_reqs : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<5>}[2], rrd_read_resps : UInt<1>[2], flip write_ports : { valid : UInt<1>, bits : { addr : UInt<7>, data : UInt<1>}}[1]}
connect io.arb_read_reqs[0].ready, UInt<1>(0h1)
connect io.arb_read_reqs[1].ready, UInt<1>(0h1)
cmem regfile : UInt<1> [32]
reg io_rrd_read_resps_0_REG : UInt, clock
connect io_rrd_read_resps_0_REG, io.arb_read_reqs[0].bits
node _io_rrd_read_resps_0_T = or(io_rrd_read_resps_0_REG, UInt<5>(0h0))
node _io_rrd_read_resps_0_T_1 = bits(_io_rrd_read_resps_0_T, 4, 0)
infer mport io_rrd_read_resps_0_MPORT = regfile[_io_rrd_read_resps_0_T_1], clock
connect io.rrd_read_resps[0], io_rrd_read_resps_0_MPORT
reg io_rrd_read_resps_1_REG : UInt, clock
connect io_rrd_read_resps_1_REG, io.arb_read_reqs[1].bits
node _io_rrd_read_resps_1_T = or(io_rrd_read_resps_1_REG, UInt<5>(0h0))
node _io_rrd_read_resps_1_T_1 = bits(_io_rrd_read_resps_1_T, 4, 0)
infer mport io_rrd_read_resps_1_MPORT = regfile[_io_rrd_read_resps_1_T_1], clock
connect io.rrd_read_resps[1], io_rrd_read_resps_1_MPORT
when io.write_ports[0].valid :
node _T = bits(io.write_ports[0].bits.addr, 4, 0)
infer mport MPORT = regfile[_T], clock
connect MPORT, io.write_ports[0].bits.data | module FullyPortedRF_3( // @[regfile.scala:186:7]
input clock, // @[regfile.scala:186:7]
input reset, // @[regfile.scala:186:7]
input io_arb_read_reqs_0_valid, // @[regfile.scala:31:14]
input [4:0] io_arb_read_reqs_0_bits, // @[regfile.scala:31:14]
input io_arb_read_reqs_1_valid, // @[regfile.scala:31:14]
input [4:0] io_arb_read_reqs_1_bits, // @[regfile.scala:31:14]
output io_rrd_read_resps_0, // @[regfile.scala:31:14]
output io_rrd_read_resps_1, // @[regfile.scala:31:14]
input io_write_ports_0_valid, // @[regfile.scala:31:14]
input [6:0] io_write_ports_0_bits_addr, // @[regfile.scala:31:14]
input io_write_ports_0_bits_data // @[regfile.scala:31:14]
);
wire io_arb_read_reqs_0_valid_0 = io_arb_read_reqs_0_valid; // @[regfile.scala:186:7]
wire [4:0] io_arb_read_reqs_0_bits_0 = io_arb_read_reqs_0_bits; // @[regfile.scala:186:7]
wire io_arb_read_reqs_1_valid_0 = io_arb_read_reqs_1_valid; // @[regfile.scala:186:7]
wire [4:0] io_arb_read_reqs_1_bits_0 = io_arb_read_reqs_1_bits; // @[regfile.scala:186:7]
wire io_write_ports_0_valid_0 = io_write_ports_0_valid; // @[regfile.scala:186:7]
wire [6:0] io_write_ports_0_bits_addr_0 = io_write_ports_0_bits_addr; // @[regfile.scala:186:7]
wire io_write_ports_0_bits_data_0 = io_write_ports_0_bits_data; // @[regfile.scala:186:7]
wire io_arb_read_reqs_0_ready = 1'h1; // @[regfile.scala:186:7]
wire io_arb_read_reqs_1_ready = 1'h1; // @[regfile.scala:186:7]
wire io_rrd_read_resps_0_0; // @[regfile.scala:186:7]
wire io_rrd_read_resps_1_0; // @[regfile.scala:186:7]
reg [4:0] io_rrd_read_resps_0_REG; // @[regfile.scala:206:75]
wire [4:0] _io_rrd_read_resps_0_T = io_rrd_read_resps_0_REG; // @[regfile.scala:206:{67,75}]
wire [4:0] _io_rrd_read_resps_0_T_1 = _io_rrd_read_resps_0_T; // @[regfile.scala:206:67]
reg [4:0] io_rrd_read_resps_1_REG; // @[regfile.scala:206:75]
wire [4:0] _io_rrd_read_resps_1_T = io_rrd_read_resps_1_REG; // @[regfile.scala:206:{67,75}]
wire [4:0] _io_rrd_read_resps_1_T_1 = _io_rrd_read_resps_1_T; // @[regfile.scala:206:67]
always @(posedge clock) begin // @[regfile.scala:186:7]
io_rrd_read_resps_0_REG <= io_arb_read_reqs_0_bits_0; // @[regfile.scala:186:7, :206:75]
io_rrd_read_resps_1_REG <= io_arb_read_reqs_1_bits_0; // @[regfile.scala:186:7, :206:75]
always @(posedge)
regfile_32x1 regfile_ext ( // @[regfile.scala:204:20]
.R0_addr (_io_rrd_read_resps_1_T_1), // @[regfile.scala:206:67]
.R0_en (1'h1), // @[regfile.scala:186:7]
.R0_clk (clock),
.R0_data (io_rrd_read_resps_1_0),
.R1_addr (_io_rrd_read_resps_0_T_1), // @[regfile.scala:206:67]
.R1_en (1'h1), // @[regfile.scala:186:7]
.R1_clk (clock),
.R1_data (io_rrd_read_resps_0_0),
.W0_addr (io_write_ports_0_bits_addr_0[4:0]), // @[regfile.scala:186:7, :208:53]
.W0_en (io_write_ports_0_valid_0), // @[regfile.scala:186:7]
.W0_clk (clock),
.W0_data (io_write_ports_0_bits_data_0) // @[regfile.scala:186:7]
); // @[regfile.scala:204:20]
assign io_rrd_read_resps_0 = io_rrd_read_resps_0_0; // @[regfile.scala:186:7]
assign io_rrd_read_resps_1 = io_rrd_read_resps_1_0; // @[regfile.scala:186:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_154 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_168
connect io_out_sink_extend.clock, clock
connect io_out_sink_extend.reset, reset
connect io_out_sink_extend.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_extend.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_154( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_168 io_out_sink_extend ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetRegVec_w1_i0_20 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>}
node _reg_T = asAsyncReset(reset)
regreset reg : UInt<1>, clock, _reg_T, UInt<1>(0h0)
when io.en :
connect reg, io.d
connect io.q, reg | module AsyncResetRegVec_w1_i0_20( // @[AsyncResetReg.scala:56:7]
input clock, // @[AsyncResetReg.scala:56:7]
input reset // @[AsyncResetReg.scala:56:7]
);
wire _reg_T = reset; // @[AsyncResetReg.scala:61:29]
wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14]
wire io_d = 1'h0; // @[AsyncResetReg.scala:56:7]
wire io_q = 1'h0; // @[AsyncResetReg.scala:56:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_17 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE : UInt<1>[9]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
connect _source_ok_WIRE[7], _source_ok_T_27
connect _source_ok_WIRE[8], _source_ok_T_28
node _source_ok_T_29 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[2])
node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[3])
node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[4])
node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[5])
node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[6])
node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[7])
node source_ok = or(_source_ok_T_35, _source_ok_WIRE[8])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_81 = eq(_T_80, UInt<1>(0h0))
node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_83 = cvt(_T_82)
node _T_84 = and(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = asSInt(_T_84)
node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = or(_T_81, _T_86)
node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_89 = eq(_T_88, UInt<1>(0h0))
node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<1>(0h0)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_89, _T_94)
node _T_96 = and(_T_11, _T_24)
node _T_97 = and(_T_96, _T_37)
node _T_98 = and(_T_97, _T_50)
node _T_99 = and(_T_98, _T_63)
node _T_100 = and(_T_99, _T_71)
node _T_101 = and(_T_100, _T_79)
node _T_102 = and(_T_101, _T_87)
node _T_103 = and(_T_102, _T_95)
node _T_104 = asUInt(reset)
node _T_105 = eq(_T_104, UInt<1>(0h0))
when _T_105 :
node _T_106 = eq(_T_103, UInt<1>(0h0))
when _T_106 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_103, UInt<1>(0h1), "") : assert_1
node _T_107 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_107 :
node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_112 = shr(io.in.a.bits.source, 2)
node _T_113 = eq(_T_112, UInt<1>(0h0))
node _T_114 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_115 = and(_T_113, _T_114)
node _T_116 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_117 = and(_T_115, _T_116)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_118 = shr(io.in.a.bits.source, 2)
node _T_119 = eq(_T_118, UInt<1>(0h1))
node _T_120 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_121 = and(_T_119, _T_120)
node _T_122 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_123 = and(_T_121, _T_122)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_124 = shr(io.in.a.bits.source, 2)
node _T_125 = eq(_T_124, UInt<2>(0h2))
node _T_126 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_127 = and(_T_125, _T_126)
node _T_128 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_129 = and(_T_127, _T_128)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_130 = shr(io.in.a.bits.source, 2)
node _T_131 = eq(_T_130, UInt<2>(0h3))
node _T_132 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_133 = and(_T_131, _T_132)
node _T_134 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_135 = and(_T_133, _T_134)
node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_137 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_140 = or(_T_111, _T_117)
node _T_141 = or(_T_140, _T_123)
node _T_142 = or(_T_141, _T_129)
node _T_143 = or(_T_142, _T_135)
node _T_144 = or(_T_143, _T_136)
node _T_145 = or(_T_144, _T_137)
node _T_146 = or(_T_145, _T_138)
node _T_147 = or(_T_146, _T_139)
node _T_148 = and(_T_110, _T_147)
node _T_149 = or(UInt<1>(0h0), _T_148)
node _T_150 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_151 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_152 = cvt(_T_151)
node _T_153 = and(_T_152, asSInt(UInt<14>(0h2000)))
node _T_154 = asSInt(_T_153)
node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0)))
node _T_156 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_157 = cvt(_T_156)
node _T_158 = and(_T_157, asSInt(UInt<13>(0h1000)))
node _T_159 = asSInt(_T_158)
node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0)))
node _T_161 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_162 = cvt(_T_161)
node _T_163 = and(_T_162, asSInt(UInt<17>(0h10000)))
node _T_164 = asSInt(_T_163)
node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0)))
node _T_166 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_167 = cvt(_T_166)
node _T_168 = and(_T_167, asSInt(UInt<18>(0h2f000)))
node _T_169 = asSInt(_T_168)
node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0)))
node _T_171 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_172 = cvt(_T_171)
node _T_173 = and(_T_172, asSInt(UInt<17>(0h10000)))
node _T_174 = asSInt(_T_173)
node _T_175 = eq(_T_174, asSInt(UInt<1>(0h0)))
node _T_176 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_177 = cvt(_T_176)
node _T_178 = and(_T_177, asSInt(UInt<13>(0h1000)))
node _T_179 = asSInt(_T_178)
node _T_180 = eq(_T_179, asSInt(UInt<1>(0h0)))
node _T_181 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_182 = cvt(_T_181)
node _T_183 = and(_T_182, asSInt(UInt<27>(0h4000000)))
node _T_184 = asSInt(_T_183)
node _T_185 = eq(_T_184, asSInt(UInt<1>(0h0)))
node _T_186 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_187 = cvt(_T_186)
node _T_188 = and(_T_187, asSInt(UInt<13>(0h1000)))
node _T_189 = asSInt(_T_188)
node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0)))
node _T_191 = or(_T_155, _T_160)
node _T_192 = or(_T_191, _T_165)
node _T_193 = or(_T_192, _T_170)
node _T_194 = or(_T_193, _T_175)
node _T_195 = or(_T_194, _T_180)
node _T_196 = or(_T_195, _T_185)
node _T_197 = or(_T_196, _T_190)
node _T_198 = and(_T_150, _T_197)
node _T_199 = or(UInt<1>(0h0), _T_198)
node _T_200 = and(_T_149, _T_199)
node _T_201 = asUInt(reset)
node _T_202 = eq(_T_201, UInt<1>(0h0))
when _T_202 :
node _T_203 = eq(_T_200, UInt<1>(0h0))
when _T_203 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_200, UInt<1>(0h1), "") : assert_2
node _T_204 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_205 = shr(io.in.a.bits.source, 2)
node _T_206 = eq(_T_205, UInt<1>(0h0))
node _T_207 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_208 = and(_T_206, _T_207)
node _T_209 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_210 = and(_T_208, _T_209)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_211 = shr(io.in.a.bits.source, 2)
node _T_212 = eq(_T_211, UInt<1>(0h1))
node _T_213 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_214 = and(_T_212, _T_213)
node _T_215 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_216 = and(_T_214, _T_215)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_217 = shr(io.in.a.bits.source, 2)
node _T_218 = eq(_T_217, UInt<2>(0h2))
node _T_219 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_220 = and(_T_218, _T_219)
node _T_221 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_222 = and(_T_220, _T_221)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_223 = shr(io.in.a.bits.source, 2)
node _T_224 = eq(_T_223, UInt<2>(0h3))
node _T_225 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_226 = and(_T_224, _T_225)
node _T_227 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_228 = and(_T_226, _T_227)
node _T_229 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_230 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_231 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_232 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE : UInt<1>[9]
connect _WIRE[0], _T_204
connect _WIRE[1], _T_210
connect _WIRE[2], _T_216
connect _WIRE[3], _T_222
connect _WIRE[4], _T_228
connect _WIRE[5], _T_229
connect _WIRE[6], _T_230
connect _WIRE[7], _T_231
connect _WIRE[8], _T_232
node _T_233 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_234 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_235 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_236 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_237 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_238 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_239 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_240 = mux(_WIRE[6], _T_233, UInt<1>(0h0))
node _T_241 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_242 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_243 = or(_T_234, _T_235)
node _T_244 = or(_T_243, _T_236)
node _T_245 = or(_T_244, _T_237)
node _T_246 = or(_T_245, _T_238)
node _T_247 = or(_T_246, _T_239)
node _T_248 = or(_T_247, _T_240)
node _T_249 = or(_T_248, _T_241)
node _T_250 = or(_T_249, _T_242)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_250
node _T_251 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_252 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_253 = and(_T_251, _T_252)
node _T_254 = or(UInt<1>(0h0), _T_253)
node _T_255 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_256 = cvt(_T_255)
node _T_257 = and(_T_256, asSInt(UInt<14>(0h2000)))
node _T_258 = asSInt(_T_257)
node _T_259 = eq(_T_258, asSInt(UInt<1>(0h0)))
node _T_260 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_261 = cvt(_T_260)
node _T_262 = and(_T_261, asSInt(UInt<13>(0h1000)))
node _T_263 = asSInt(_T_262)
node _T_264 = eq(_T_263, asSInt(UInt<1>(0h0)))
node _T_265 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_266 = cvt(_T_265)
node _T_267 = and(_T_266, asSInt(UInt<17>(0h10000)))
node _T_268 = asSInt(_T_267)
node _T_269 = eq(_T_268, asSInt(UInt<1>(0h0)))
node _T_270 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_271 = cvt(_T_270)
node _T_272 = and(_T_271, asSInt(UInt<18>(0h2f000)))
node _T_273 = asSInt(_T_272)
node _T_274 = eq(_T_273, asSInt(UInt<1>(0h0)))
node _T_275 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_276 = cvt(_T_275)
node _T_277 = and(_T_276, asSInt(UInt<17>(0h10000)))
node _T_278 = asSInt(_T_277)
node _T_279 = eq(_T_278, asSInt(UInt<1>(0h0)))
node _T_280 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_281 = cvt(_T_280)
node _T_282 = and(_T_281, asSInt(UInt<13>(0h1000)))
node _T_283 = asSInt(_T_282)
node _T_284 = eq(_T_283, asSInt(UInt<1>(0h0)))
node _T_285 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_286 = cvt(_T_285)
node _T_287 = and(_T_286, asSInt(UInt<27>(0h4000000)))
node _T_288 = asSInt(_T_287)
node _T_289 = eq(_T_288, asSInt(UInt<1>(0h0)))
node _T_290 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_291 = cvt(_T_290)
node _T_292 = and(_T_291, asSInt(UInt<13>(0h1000)))
node _T_293 = asSInt(_T_292)
node _T_294 = eq(_T_293, asSInt(UInt<1>(0h0)))
node _T_295 = or(_T_259, _T_264)
node _T_296 = or(_T_295, _T_269)
node _T_297 = or(_T_296, _T_274)
node _T_298 = or(_T_297, _T_279)
node _T_299 = or(_T_298, _T_284)
node _T_300 = or(_T_299, _T_289)
node _T_301 = or(_T_300, _T_294)
node _T_302 = and(_T_254, _T_301)
node _T_303 = or(UInt<1>(0h0), _T_302)
node _T_304 = and(_WIRE_1, _T_303)
node _T_305 = asUInt(reset)
node _T_306 = eq(_T_305, UInt<1>(0h0))
when _T_306 :
node _T_307 = eq(_T_304, UInt<1>(0h0))
when _T_307 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_304, UInt<1>(0h1), "") : assert_3
node _T_308 = asUInt(reset)
node _T_309 = eq(_T_308, UInt<1>(0h0))
when _T_309 :
node _T_310 = eq(source_ok, UInt<1>(0h0))
when _T_310 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_311 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_312 = asUInt(reset)
node _T_313 = eq(_T_312, UInt<1>(0h0))
when _T_313 :
node _T_314 = eq(_T_311, UInt<1>(0h0))
when _T_314 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_311, UInt<1>(0h1), "") : assert_5
node _T_315 = asUInt(reset)
node _T_316 = eq(_T_315, UInt<1>(0h0))
when _T_316 :
node _T_317 = eq(is_aligned, UInt<1>(0h0))
when _T_317 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_318 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_319 = asUInt(reset)
node _T_320 = eq(_T_319, UInt<1>(0h0))
when _T_320 :
node _T_321 = eq(_T_318, UInt<1>(0h0))
when _T_321 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_318, UInt<1>(0h1), "") : assert_7
node _T_322 = not(io.in.a.bits.mask)
node _T_323 = eq(_T_322, UInt<1>(0h0))
node _T_324 = asUInt(reset)
node _T_325 = eq(_T_324, UInt<1>(0h0))
when _T_325 :
node _T_326 = eq(_T_323, UInt<1>(0h0))
when _T_326 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_323, UInt<1>(0h1), "") : assert_8
node _T_327 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_328 = asUInt(reset)
node _T_329 = eq(_T_328, UInt<1>(0h0))
when _T_329 :
node _T_330 = eq(_T_327, UInt<1>(0h0))
when _T_330 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_327, UInt<1>(0h1), "") : assert_9
node _T_331 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_331 :
node _T_332 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_333 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_334 = and(_T_332, _T_333)
node _T_335 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_336 = shr(io.in.a.bits.source, 2)
node _T_337 = eq(_T_336, UInt<1>(0h0))
node _T_338 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_339 = and(_T_337, _T_338)
node _T_340 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_341 = and(_T_339, _T_340)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_342 = shr(io.in.a.bits.source, 2)
node _T_343 = eq(_T_342, UInt<1>(0h1))
node _T_344 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_345 = and(_T_343, _T_344)
node _T_346 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_347 = and(_T_345, _T_346)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_348 = shr(io.in.a.bits.source, 2)
node _T_349 = eq(_T_348, UInt<2>(0h2))
node _T_350 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_351 = and(_T_349, _T_350)
node _T_352 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_353 = and(_T_351, _T_352)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_354 = shr(io.in.a.bits.source, 2)
node _T_355 = eq(_T_354, UInt<2>(0h3))
node _T_356 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_357 = and(_T_355, _T_356)
node _T_358 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_359 = and(_T_357, _T_358)
node _T_360 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_361 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_362 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_363 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_364 = or(_T_335, _T_341)
node _T_365 = or(_T_364, _T_347)
node _T_366 = or(_T_365, _T_353)
node _T_367 = or(_T_366, _T_359)
node _T_368 = or(_T_367, _T_360)
node _T_369 = or(_T_368, _T_361)
node _T_370 = or(_T_369, _T_362)
node _T_371 = or(_T_370, _T_363)
node _T_372 = and(_T_334, _T_371)
node _T_373 = or(UInt<1>(0h0), _T_372)
node _T_374 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_375 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_376 = cvt(_T_375)
node _T_377 = and(_T_376, asSInt(UInt<14>(0h2000)))
node _T_378 = asSInt(_T_377)
node _T_379 = eq(_T_378, asSInt(UInt<1>(0h0)))
node _T_380 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_381 = cvt(_T_380)
node _T_382 = and(_T_381, asSInt(UInt<13>(0h1000)))
node _T_383 = asSInt(_T_382)
node _T_384 = eq(_T_383, asSInt(UInt<1>(0h0)))
node _T_385 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_386 = cvt(_T_385)
node _T_387 = and(_T_386, asSInt(UInt<17>(0h10000)))
node _T_388 = asSInt(_T_387)
node _T_389 = eq(_T_388, asSInt(UInt<1>(0h0)))
node _T_390 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_391 = cvt(_T_390)
node _T_392 = and(_T_391, asSInt(UInt<18>(0h2f000)))
node _T_393 = asSInt(_T_392)
node _T_394 = eq(_T_393, asSInt(UInt<1>(0h0)))
node _T_395 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_396 = cvt(_T_395)
node _T_397 = and(_T_396, asSInt(UInt<17>(0h10000)))
node _T_398 = asSInt(_T_397)
node _T_399 = eq(_T_398, asSInt(UInt<1>(0h0)))
node _T_400 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_401 = cvt(_T_400)
node _T_402 = and(_T_401, asSInt(UInt<13>(0h1000)))
node _T_403 = asSInt(_T_402)
node _T_404 = eq(_T_403, asSInt(UInt<1>(0h0)))
node _T_405 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_406 = cvt(_T_405)
node _T_407 = and(_T_406, asSInt(UInt<27>(0h4000000)))
node _T_408 = asSInt(_T_407)
node _T_409 = eq(_T_408, asSInt(UInt<1>(0h0)))
node _T_410 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_411 = cvt(_T_410)
node _T_412 = and(_T_411, asSInt(UInt<13>(0h1000)))
node _T_413 = asSInt(_T_412)
node _T_414 = eq(_T_413, asSInt(UInt<1>(0h0)))
node _T_415 = or(_T_379, _T_384)
node _T_416 = or(_T_415, _T_389)
node _T_417 = or(_T_416, _T_394)
node _T_418 = or(_T_417, _T_399)
node _T_419 = or(_T_418, _T_404)
node _T_420 = or(_T_419, _T_409)
node _T_421 = or(_T_420, _T_414)
node _T_422 = and(_T_374, _T_421)
node _T_423 = or(UInt<1>(0h0), _T_422)
node _T_424 = and(_T_373, _T_423)
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(_T_424, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_424, UInt<1>(0h1), "") : assert_10
node _T_428 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_429 = shr(io.in.a.bits.source, 2)
node _T_430 = eq(_T_429, UInt<1>(0h0))
node _T_431 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_432 = and(_T_430, _T_431)
node _T_433 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_434 = and(_T_432, _T_433)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_435 = shr(io.in.a.bits.source, 2)
node _T_436 = eq(_T_435, UInt<1>(0h1))
node _T_437 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_438 = and(_T_436, _T_437)
node _T_439 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_440 = and(_T_438, _T_439)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_441 = shr(io.in.a.bits.source, 2)
node _T_442 = eq(_T_441, UInt<2>(0h2))
node _T_443 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_444 = and(_T_442, _T_443)
node _T_445 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_446 = and(_T_444, _T_445)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_447 = shr(io.in.a.bits.source, 2)
node _T_448 = eq(_T_447, UInt<2>(0h3))
node _T_449 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_450 = and(_T_448, _T_449)
node _T_451 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_452 = and(_T_450, _T_451)
node _T_453 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_454 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_455 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_456 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE_2 : UInt<1>[9]
connect _WIRE_2[0], _T_428
connect _WIRE_2[1], _T_434
connect _WIRE_2[2], _T_440
connect _WIRE_2[3], _T_446
connect _WIRE_2[4], _T_452
connect _WIRE_2[5], _T_453
connect _WIRE_2[6], _T_454
connect _WIRE_2[7], _T_455
connect _WIRE_2[8], _T_456
node _T_457 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_458 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_459 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_460 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_461 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_462 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_463 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_464 = mux(_WIRE_2[6], _T_457, UInt<1>(0h0))
node _T_465 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_466 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_467 = or(_T_458, _T_459)
node _T_468 = or(_T_467, _T_460)
node _T_469 = or(_T_468, _T_461)
node _T_470 = or(_T_469, _T_462)
node _T_471 = or(_T_470, _T_463)
node _T_472 = or(_T_471, _T_464)
node _T_473 = or(_T_472, _T_465)
node _T_474 = or(_T_473, _T_466)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_474
node _T_475 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_476 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_477 = and(_T_475, _T_476)
node _T_478 = or(UInt<1>(0h0), _T_477)
node _T_479 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_480 = cvt(_T_479)
node _T_481 = and(_T_480, asSInt(UInt<14>(0h2000)))
node _T_482 = asSInt(_T_481)
node _T_483 = eq(_T_482, asSInt(UInt<1>(0h0)))
node _T_484 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_485 = cvt(_T_484)
node _T_486 = and(_T_485, asSInt(UInt<13>(0h1000)))
node _T_487 = asSInt(_T_486)
node _T_488 = eq(_T_487, asSInt(UInt<1>(0h0)))
node _T_489 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_490 = cvt(_T_489)
node _T_491 = and(_T_490, asSInt(UInt<17>(0h10000)))
node _T_492 = asSInt(_T_491)
node _T_493 = eq(_T_492, asSInt(UInt<1>(0h0)))
node _T_494 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_495 = cvt(_T_494)
node _T_496 = and(_T_495, asSInt(UInt<18>(0h2f000)))
node _T_497 = asSInt(_T_496)
node _T_498 = eq(_T_497, asSInt(UInt<1>(0h0)))
node _T_499 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_500 = cvt(_T_499)
node _T_501 = and(_T_500, asSInt(UInt<17>(0h10000)))
node _T_502 = asSInt(_T_501)
node _T_503 = eq(_T_502, asSInt(UInt<1>(0h0)))
node _T_504 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_505 = cvt(_T_504)
node _T_506 = and(_T_505, asSInt(UInt<13>(0h1000)))
node _T_507 = asSInt(_T_506)
node _T_508 = eq(_T_507, asSInt(UInt<1>(0h0)))
node _T_509 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_510 = cvt(_T_509)
node _T_511 = and(_T_510, asSInt(UInt<27>(0h4000000)))
node _T_512 = asSInt(_T_511)
node _T_513 = eq(_T_512, asSInt(UInt<1>(0h0)))
node _T_514 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_515 = cvt(_T_514)
node _T_516 = and(_T_515, asSInt(UInt<13>(0h1000)))
node _T_517 = asSInt(_T_516)
node _T_518 = eq(_T_517, asSInt(UInt<1>(0h0)))
node _T_519 = or(_T_483, _T_488)
node _T_520 = or(_T_519, _T_493)
node _T_521 = or(_T_520, _T_498)
node _T_522 = or(_T_521, _T_503)
node _T_523 = or(_T_522, _T_508)
node _T_524 = or(_T_523, _T_513)
node _T_525 = or(_T_524, _T_518)
node _T_526 = and(_T_478, _T_525)
node _T_527 = or(UInt<1>(0h0), _T_526)
node _T_528 = and(_WIRE_3, _T_527)
node _T_529 = asUInt(reset)
node _T_530 = eq(_T_529, UInt<1>(0h0))
when _T_530 :
node _T_531 = eq(_T_528, UInt<1>(0h0))
when _T_531 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_528, UInt<1>(0h1), "") : assert_11
node _T_532 = asUInt(reset)
node _T_533 = eq(_T_532, UInt<1>(0h0))
when _T_533 :
node _T_534 = eq(source_ok, UInt<1>(0h0))
when _T_534 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_535 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_536 = asUInt(reset)
node _T_537 = eq(_T_536, UInt<1>(0h0))
when _T_537 :
node _T_538 = eq(_T_535, UInt<1>(0h0))
when _T_538 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_535, UInt<1>(0h1), "") : assert_13
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(is_aligned, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_542 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_543 = asUInt(reset)
node _T_544 = eq(_T_543, UInt<1>(0h0))
when _T_544 :
node _T_545 = eq(_T_542, UInt<1>(0h0))
when _T_545 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_542, UInt<1>(0h1), "") : assert_15
node _T_546 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_547 = asUInt(reset)
node _T_548 = eq(_T_547, UInt<1>(0h0))
when _T_548 :
node _T_549 = eq(_T_546, UInt<1>(0h0))
when _T_549 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_546, UInt<1>(0h1), "") : assert_16
node _T_550 = not(io.in.a.bits.mask)
node _T_551 = eq(_T_550, UInt<1>(0h0))
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_551, UInt<1>(0h1), "") : assert_17
node _T_555 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_556 = asUInt(reset)
node _T_557 = eq(_T_556, UInt<1>(0h0))
when _T_557 :
node _T_558 = eq(_T_555, UInt<1>(0h0))
when _T_558 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_555, UInt<1>(0h1), "") : assert_18
node _T_559 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_559 :
node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_562 = and(_T_560, _T_561)
node _T_563 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_564 = shr(io.in.a.bits.source, 2)
node _T_565 = eq(_T_564, UInt<1>(0h0))
node _T_566 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_567 = and(_T_565, _T_566)
node _T_568 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_569 = and(_T_567, _T_568)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_570 = shr(io.in.a.bits.source, 2)
node _T_571 = eq(_T_570, UInt<1>(0h1))
node _T_572 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_573 = and(_T_571, _T_572)
node _T_574 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_575 = and(_T_573, _T_574)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_576 = shr(io.in.a.bits.source, 2)
node _T_577 = eq(_T_576, UInt<2>(0h2))
node _T_578 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_579 = and(_T_577, _T_578)
node _T_580 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_581 = and(_T_579, _T_580)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_582 = shr(io.in.a.bits.source, 2)
node _T_583 = eq(_T_582, UInt<2>(0h3))
node _T_584 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_585 = and(_T_583, _T_584)
node _T_586 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_587 = and(_T_585, _T_586)
node _T_588 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_589 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_590 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_591 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_592 = or(_T_563, _T_569)
node _T_593 = or(_T_592, _T_575)
node _T_594 = or(_T_593, _T_581)
node _T_595 = or(_T_594, _T_587)
node _T_596 = or(_T_595, _T_588)
node _T_597 = or(_T_596, _T_589)
node _T_598 = or(_T_597, _T_590)
node _T_599 = or(_T_598, _T_591)
node _T_600 = and(_T_562, _T_599)
node _T_601 = or(UInt<1>(0h0), _T_600)
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_601, UInt<1>(0h1), "") : assert_19
node _T_605 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_606 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_607 = and(_T_605, _T_606)
node _T_608 = or(UInt<1>(0h0), _T_607)
node _T_609 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_610 = cvt(_T_609)
node _T_611 = and(_T_610, asSInt(UInt<13>(0h1000)))
node _T_612 = asSInt(_T_611)
node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0)))
node _T_614 = and(_T_608, _T_613)
node _T_615 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_616 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_617 = and(_T_615, _T_616)
node _T_618 = or(UInt<1>(0h0), _T_617)
node _T_619 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_620 = cvt(_T_619)
node _T_621 = and(_T_620, asSInt(UInt<14>(0h2000)))
node _T_622 = asSInt(_T_621)
node _T_623 = eq(_T_622, asSInt(UInt<1>(0h0)))
node _T_624 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_625 = cvt(_T_624)
node _T_626 = and(_T_625, asSInt(UInt<17>(0h10000)))
node _T_627 = asSInt(_T_626)
node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0)))
node _T_629 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_630 = cvt(_T_629)
node _T_631 = and(_T_630, asSInt(UInt<18>(0h2f000)))
node _T_632 = asSInt(_T_631)
node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0)))
node _T_634 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_635 = cvt(_T_634)
node _T_636 = and(_T_635, asSInt(UInt<17>(0h10000)))
node _T_637 = asSInt(_T_636)
node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0)))
node _T_639 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_640 = cvt(_T_639)
node _T_641 = and(_T_640, asSInt(UInt<13>(0h1000)))
node _T_642 = asSInt(_T_641)
node _T_643 = eq(_T_642, asSInt(UInt<1>(0h0)))
node _T_644 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_645 = cvt(_T_644)
node _T_646 = and(_T_645, asSInt(UInt<27>(0h4000000)))
node _T_647 = asSInt(_T_646)
node _T_648 = eq(_T_647, asSInt(UInt<1>(0h0)))
node _T_649 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_650 = cvt(_T_649)
node _T_651 = and(_T_650, asSInt(UInt<13>(0h1000)))
node _T_652 = asSInt(_T_651)
node _T_653 = eq(_T_652, asSInt(UInt<1>(0h0)))
node _T_654 = or(_T_623, _T_628)
node _T_655 = or(_T_654, _T_633)
node _T_656 = or(_T_655, _T_638)
node _T_657 = or(_T_656, _T_643)
node _T_658 = or(_T_657, _T_648)
node _T_659 = or(_T_658, _T_653)
node _T_660 = and(_T_618, _T_659)
node _T_661 = or(UInt<1>(0h0), _T_614)
node _T_662 = or(_T_661, _T_660)
node _T_663 = asUInt(reset)
node _T_664 = eq(_T_663, UInt<1>(0h0))
when _T_664 :
node _T_665 = eq(_T_662, UInt<1>(0h0))
when _T_665 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_662, UInt<1>(0h1), "") : assert_20
node _T_666 = asUInt(reset)
node _T_667 = eq(_T_666, UInt<1>(0h0))
when _T_667 :
node _T_668 = eq(source_ok, UInt<1>(0h0))
when _T_668 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_669 = asUInt(reset)
node _T_670 = eq(_T_669, UInt<1>(0h0))
when _T_670 :
node _T_671 = eq(is_aligned, UInt<1>(0h0))
when _T_671 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_672 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_673 = asUInt(reset)
node _T_674 = eq(_T_673, UInt<1>(0h0))
when _T_674 :
node _T_675 = eq(_T_672, UInt<1>(0h0))
when _T_675 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_672, UInt<1>(0h1), "") : assert_23
node _T_676 = eq(io.in.a.bits.mask, mask)
node _T_677 = asUInt(reset)
node _T_678 = eq(_T_677, UInt<1>(0h0))
when _T_678 :
node _T_679 = eq(_T_676, UInt<1>(0h0))
when _T_679 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_676, UInt<1>(0h1), "") : assert_24
node _T_680 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_681 = asUInt(reset)
node _T_682 = eq(_T_681, UInt<1>(0h0))
when _T_682 :
node _T_683 = eq(_T_680, UInt<1>(0h0))
when _T_683 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_680, UInt<1>(0h1), "") : assert_25
node _T_684 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_684 :
node _T_685 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_686 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_687 = and(_T_685, _T_686)
node _T_688 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_689 = shr(io.in.a.bits.source, 2)
node _T_690 = eq(_T_689, UInt<1>(0h0))
node _T_691 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_692 = and(_T_690, _T_691)
node _T_693 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_694 = and(_T_692, _T_693)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_695 = shr(io.in.a.bits.source, 2)
node _T_696 = eq(_T_695, UInt<1>(0h1))
node _T_697 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_698 = and(_T_696, _T_697)
node _T_699 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_700 = and(_T_698, _T_699)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_701 = shr(io.in.a.bits.source, 2)
node _T_702 = eq(_T_701, UInt<2>(0h2))
node _T_703 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_704 = and(_T_702, _T_703)
node _T_705 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_706 = and(_T_704, _T_705)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_707 = shr(io.in.a.bits.source, 2)
node _T_708 = eq(_T_707, UInt<2>(0h3))
node _T_709 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_710 = and(_T_708, _T_709)
node _T_711 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_712 = and(_T_710, _T_711)
node _T_713 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_714 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_715 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_716 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_717 = or(_T_688, _T_694)
node _T_718 = or(_T_717, _T_700)
node _T_719 = or(_T_718, _T_706)
node _T_720 = or(_T_719, _T_712)
node _T_721 = or(_T_720, _T_713)
node _T_722 = or(_T_721, _T_714)
node _T_723 = or(_T_722, _T_715)
node _T_724 = or(_T_723, _T_716)
node _T_725 = and(_T_687, _T_724)
node _T_726 = or(UInt<1>(0h0), _T_725)
node _T_727 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_728 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_729 = and(_T_727, _T_728)
node _T_730 = or(UInt<1>(0h0), _T_729)
node _T_731 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_732 = cvt(_T_731)
node _T_733 = and(_T_732, asSInt(UInt<13>(0h1000)))
node _T_734 = asSInt(_T_733)
node _T_735 = eq(_T_734, asSInt(UInt<1>(0h0)))
node _T_736 = and(_T_730, _T_735)
node _T_737 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_738 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_739 = and(_T_737, _T_738)
node _T_740 = or(UInt<1>(0h0), _T_739)
node _T_741 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_742 = cvt(_T_741)
node _T_743 = and(_T_742, asSInt(UInt<14>(0h2000)))
node _T_744 = asSInt(_T_743)
node _T_745 = eq(_T_744, asSInt(UInt<1>(0h0)))
node _T_746 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_747 = cvt(_T_746)
node _T_748 = and(_T_747, asSInt(UInt<18>(0h2f000)))
node _T_749 = asSInt(_T_748)
node _T_750 = eq(_T_749, asSInt(UInt<1>(0h0)))
node _T_751 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_752 = cvt(_T_751)
node _T_753 = and(_T_752, asSInt(UInt<17>(0h10000)))
node _T_754 = asSInt(_T_753)
node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0)))
node _T_756 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_757 = cvt(_T_756)
node _T_758 = and(_T_757, asSInt(UInt<13>(0h1000)))
node _T_759 = asSInt(_T_758)
node _T_760 = eq(_T_759, asSInt(UInt<1>(0h0)))
node _T_761 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_762 = cvt(_T_761)
node _T_763 = and(_T_762, asSInt(UInt<27>(0h4000000)))
node _T_764 = asSInt(_T_763)
node _T_765 = eq(_T_764, asSInt(UInt<1>(0h0)))
node _T_766 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_767 = cvt(_T_766)
node _T_768 = and(_T_767, asSInt(UInt<13>(0h1000)))
node _T_769 = asSInt(_T_768)
node _T_770 = eq(_T_769, asSInt(UInt<1>(0h0)))
node _T_771 = or(_T_745, _T_750)
node _T_772 = or(_T_771, _T_755)
node _T_773 = or(_T_772, _T_760)
node _T_774 = or(_T_773, _T_765)
node _T_775 = or(_T_774, _T_770)
node _T_776 = and(_T_740, _T_775)
node _T_777 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_778 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_779 = cvt(_T_778)
node _T_780 = and(_T_779, asSInt(UInt<17>(0h10000)))
node _T_781 = asSInt(_T_780)
node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0)))
node _T_783 = and(_T_777, _T_782)
node _T_784 = or(UInt<1>(0h0), _T_736)
node _T_785 = or(_T_784, _T_776)
node _T_786 = or(_T_785, _T_783)
node _T_787 = and(_T_726, _T_786)
node _T_788 = asUInt(reset)
node _T_789 = eq(_T_788, UInt<1>(0h0))
when _T_789 :
node _T_790 = eq(_T_787, UInt<1>(0h0))
when _T_790 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_787, UInt<1>(0h1), "") : assert_26
node _T_791 = asUInt(reset)
node _T_792 = eq(_T_791, UInt<1>(0h0))
when _T_792 :
node _T_793 = eq(source_ok, UInt<1>(0h0))
when _T_793 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_794 = asUInt(reset)
node _T_795 = eq(_T_794, UInt<1>(0h0))
when _T_795 :
node _T_796 = eq(is_aligned, UInt<1>(0h0))
when _T_796 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_797 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_798 = asUInt(reset)
node _T_799 = eq(_T_798, UInt<1>(0h0))
when _T_799 :
node _T_800 = eq(_T_797, UInt<1>(0h0))
when _T_800 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_797, UInt<1>(0h1), "") : assert_29
node _T_801 = eq(io.in.a.bits.mask, mask)
node _T_802 = asUInt(reset)
node _T_803 = eq(_T_802, UInt<1>(0h0))
when _T_803 :
node _T_804 = eq(_T_801, UInt<1>(0h0))
when _T_804 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_801, UInt<1>(0h1), "") : assert_30
node _T_805 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_805 :
node _T_806 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_807 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_808 = and(_T_806, _T_807)
node _T_809 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_810 = shr(io.in.a.bits.source, 2)
node _T_811 = eq(_T_810, UInt<1>(0h0))
node _T_812 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_813 = and(_T_811, _T_812)
node _T_814 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_815 = and(_T_813, _T_814)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_816 = shr(io.in.a.bits.source, 2)
node _T_817 = eq(_T_816, UInt<1>(0h1))
node _T_818 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_819 = and(_T_817, _T_818)
node _T_820 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_821 = and(_T_819, _T_820)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_822 = shr(io.in.a.bits.source, 2)
node _T_823 = eq(_T_822, UInt<2>(0h2))
node _T_824 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_825 = and(_T_823, _T_824)
node _T_826 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_827 = and(_T_825, _T_826)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_828 = shr(io.in.a.bits.source, 2)
node _T_829 = eq(_T_828, UInt<2>(0h3))
node _T_830 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_831 = and(_T_829, _T_830)
node _T_832 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_833 = and(_T_831, _T_832)
node _T_834 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_835 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_836 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_837 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_838 = or(_T_809, _T_815)
node _T_839 = or(_T_838, _T_821)
node _T_840 = or(_T_839, _T_827)
node _T_841 = or(_T_840, _T_833)
node _T_842 = or(_T_841, _T_834)
node _T_843 = or(_T_842, _T_835)
node _T_844 = or(_T_843, _T_836)
node _T_845 = or(_T_844, _T_837)
node _T_846 = and(_T_808, _T_845)
node _T_847 = or(UInt<1>(0h0), _T_846)
node _T_848 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_849 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_850 = and(_T_848, _T_849)
node _T_851 = or(UInt<1>(0h0), _T_850)
node _T_852 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_853 = cvt(_T_852)
node _T_854 = and(_T_853, asSInt(UInt<13>(0h1000)))
node _T_855 = asSInt(_T_854)
node _T_856 = eq(_T_855, asSInt(UInt<1>(0h0)))
node _T_857 = and(_T_851, _T_856)
node _T_858 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_859 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_860 = and(_T_858, _T_859)
node _T_861 = or(UInt<1>(0h0), _T_860)
node _T_862 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_863 = cvt(_T_862)
node _T_864 = and(_T_863, asSInt(UInt<14>(0h2000)))
node _T_865 = asSInt(_T_864)
node _T_866 = eq(_T_865, asSInt(UInt<1>(0h0)))
node _T_867 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_868 = cvt(_T_867)
node _T_869 = and(_T_868, asSInt(UInt<18>(0h2f000)))
node _T_870 = asSInt(_T_869)
node _T_871 = eq(_T_870, asSInt(UInt<1>(0h0)))
node _T_872 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_873 = cvt(_T_872)
node _T_874 = and(_T_873, asSInt(UInt<17>(0h10000)))
node _T_875 = asSInt(_T_874)
node _T_876 = eq(_T_875, asSInt(UInt<1>(0h0)))
node _T_877 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_878 = cvt(_T_877)
node _T_879 = and(_T_878, asSInt(UInt<13>(0h1000)))
node _T_880 = asSInt(_T_879)
node _T_881 = eq(_T_880, asSInt(UInt<1>(0h0)))
node _T_882 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_883 = cvt(_T_882)
node _T_884 = and(_T_883, asSInt(UInt<27>(0h4000000)))
node _T_885 = asSInt(_T_884)
node _T_886 = eq(_T_885, asSInt(UInt<1>(0h0)))
node _T_887 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_888 = cvt(_T_887)
node _T_889 = and(_T_888, asSInt(UInt<13>(0h1000)))
node _T_890 = asSInt(_T_889)
node _T_891 = eq(_T_890, asSInt(UInt<1>(0h0)))
node _T_892 = or(_T_866, _T_871)
node _T_893 = or(_T_892, _T_876)
node _T_894 = or(_T_893, _T_881)
node _T_895 = or(_T_894, _T_886)
node _T_896 = or(_T_895, _T_891)
node _T_897 = and(_T_861, _T_896)
node _T_898 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_899 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_900 = cvt(_T_899)
node _T_901 = and(_T_900, asSInt(UInt<17>(0h10000)))
node _T_902 = asSInt(_T_901)
node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0)))
node _T_904 = and(_T_898, _T_903)
node _T_905 = or(UInt<1>(0h0), _T_857)
node _T_906 = or(_T_905, _T_897)
node _T_907 = or(_T_906, _T_904)
node _T_908 = and(_T_847, _T_907)
node _T_909 = asUInt(reset)
node _T_910 = eq(_T_909, UInt<1>(0h0))
when _T_910 :
node _T_911 = eq(_T_908, UInt<1>(0h0))
when _T_911 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_908, UInt<1>(0h1), "") : assert_31
node _T_912 = asUInt(reset)
node _T_913 = eq(_T_912, UInt<1>(0h0))
when _T_913 :
node _T_914 = eq(source_ok, UInt<1>(0h0))
when _T_914 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_915 = asUInt(reset)
node _T_916 = eq(_T_915, UInt<1>(0h0))
when _T_916 :
node _T_917 = eq(is_aligned, UInt<1>(0h0))
when _T_917 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_918 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_919 = asUInt(reset)
node _T_920 = eq(_T_919, UInt<1>(0h0))
when _T_920 :
node _T_921 = eq(_T_918, UInt<1>(0h0))
when _T_921 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_918, UInt<1>(0h1), "") : assert_34
node _T_922 = not(mask)
node _T_923 = and(io.in.a.bits.mask, _T_922)
node _T_924 = eq(_T_923, UInt<1>(0h0))
node _T_925 = asUInt(reset)
node _T_926 = eq(_T_925, UInt<1>(0h0))
when _T_926 :
node _T_927 = eq(_T_924, UInt<1>(0h0))
when _T_927 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_924, UInt<1>(0h1), "") : assert_35
node _T_928 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_928 :
node _T_929 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_930 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_931 = and(_T_929, _T_930)
node _T_932 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_933 = shr(io.in.a.bits.source, 2)
node _T_934 = eq(_T_933, UInt<1>(0h0))
node _T_935 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_936 = and(_T_934, _T_935)
node _T_937 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_938 = and(_T_936, _T_937)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_939 = shr(io.in.a.bits.source, 2)
node _T_940 = eq(_T_939, UInt<1>(0h1))
node _T_941 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_942 = and(_T_940, _T_941)
node _T_943 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_944 = and(_T_942, _T_943)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_945 = shr(io.in.a.bits.source, 2)
node _T_946 = eq(_T_945, UInt<2>(0h2))
node _T_947 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_948 = and(_T_946, _T_947)
node _T_949 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_950 = and(_T_948, _T_949)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_951 = shr(io.in.a.bits.source, 2)
node _T_952 = eq(_T_951, UInt<2>(0h3))
node _T_953 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_954 = and(_T_952, _T_953)
node _T_955 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_956 = and(_T_954, _T_955)
node _T_957 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_958 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_959 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_960 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_961 = or(_T_932, _T_938)
node _T_962 = or(_T_961, _T_944)
node _T_963 = or(_T_962, _T_950)
node _T_964 = or(_T_963, _T_956)
node _T_965 = or(_T_964, _T_957)
node _T_966 = or(_T_965, _T_958)
node _T_967 = or(_T_966, _T_959)
node _T_968 = or(_T_967, _T_960)
node _T_969 = and(_T_931, _T_968)
node _T_970 = or(UInt<1>(0h0), _T_969)
node _T_971 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_972 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_973 = and(_T_971, _T_972)
node _T_974 = or(UInt<1>(0h0), _T_973)
node _T_975 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_976 = cvt(_T_975)
node _T_977 = and(_T_976, asSInt(UInt<15>(0h5000)))
node _T_978 = asSInt(_T_977)
node _T_979 = eq(_T_978, asSInt(UInt<1>(0h0)))
node _T_980 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_981 = cvt(_T_980)
node _T_982 = and(_T_981, asSInt(UInt<13>(0h1000)))
node _T_983 = asSInt(_T_982)
node _T_984 = eq(_T_983, asSInt(UInt<1>(0h0)))
node _T_985 = or(_T_979, _T_984)
node _T_986 = and(_T_974, _T_985)
node _T_987 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_988 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_989 = cvt(_T_988)
node _T_990 = and(_T_989, asSInt(UInt<13>(0h1000)))
node _T_991 = asSInt(_T_990)
node _T_992 = eq(_T_991, asSInt(UInt<1>(0h0)))
node _T_993 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_994 = cvt(_T_993)
node _T_995 = and(_T_994, asSInt(UInt<17>(0h10000)))
node _T_996 = asSInt(_T_995)
node _T_997 = eq(_T_996, asSInt(UInt<1>(0h0)))
node _T_998 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_999 = cvt(_T_998)
node _T_1000 = and(_T_999, asSInt(UInt<18>(0h2f000)))
node _T_1001 = asSInt(_T_1000)
node _T_1002 = eq(_T_1001, asSInt(UInt<1>(0h0)))
node _T_1003 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1004 = cvt(_T_1003)
node _T_1005 = and(_T_1004, asSInt(UInt<17>(0h10000)))
node _T_1006 = asSInt(_T_1005)
node _T_1007 = eq(_T_1006, asSInt(UInt<1>(0h0)))
node _T_1008 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1009 = cvt(_T_1008)
node _T_1010 = and(_T_1009, asSInt(UInt<13>(0h1000)))
node _T_1011 = asSInt(_T_1010)
node _T_1012 = eq(_T_1011, asSInt(UInt<1>(0h0)))
node _T_1013 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1014 = cvt(_T_1013)
node _T_1015 = and(_T_1014, asSInt(UInt<27>(0h4000000)))
node _T_1016 = asSInt(_T_1015)
node _T_1017 = eq(_T_1016, asSInt(UInt<1>(0h0)))
node _T_1018 = or(_T_992, _T_997)
node _T_1019 = or(_T_1018, _T_1002)
node _T_1020 = or(_T_1019, _T_1007)
node _T_1021 = or(_T_1020, _T_1012)
node _T_1022 = or(_T_1021, _T_1017)
node _T_1023 = and(_T_987, _T_1022)
node _T_1024 = or(UInt<1>(0h0), _T_986)
node _T_1025 = or(_T_1024, _T_1023)
node _T_1026 = and(_T_970, _T_1025)
node _T_1027 = asUInt(reset)
node _T_1028 = eq(_T_1027, UInt<1>(0h0))
when _T_1028 :
node _T_1029 = eq(_T_1026, UInt<1>(0h0))
when _T_1029 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_1026, UInt<1>(0h1), "") : assert_36
node _T_1030 = asUInt(reset)
node _T_1031 = eq(_T_1030, UInt<1>(0h0))
when _T_1031 :
node _T_1032 = eq(source_ok, UInt<1>(0h0))
when _T_1032 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_1033 = asUInt(reset)
node _T_1034 = eq(_T_1033, UInt<1>(0h0))
when _T_1034 :
node _T_1035 = eq(is_aligned, UInt<1>(0h0))
when _T_1035 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_1036 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_1037 = asUInt(reset)
node _T_1038 = eq(_T_1037, UInt<1>(0h0))
when _T_1038 :
node _T_1039 = eq(_T_1036, UInt<1>(0h0))
when _T_1039 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_1036, UInt<1>(0h1), "") : assert_39
node _T_1040 = eq(io.in.a.bits.mask, mask)
node _T_1041 = asUInt(reset)
node _T_1042 = eq(_T_1041, UInt<1>(0h0))
when _T_1042 :
node _T_1043 = eq(_T_1040, UInt<1>(0h0))
when _T_1043 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_1040, UInt<1>(0h1), "") : assert_40
node _T_1044 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_1044 :
node _T_1045 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1046 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1047 = and(_T_1045, _T_1046)
node _T_1048 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_1049 = shr(io.in.a.bits.source, 2)
node _T_1050 = eq(_T_1049, UInt<1>(0h0))
node _T_1051 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_1052 = and(_T_1050, _T_1051)
node _T_1053 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_1054 = and(_T_1052, _T_1053)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_1055 = shr(io.in.a.bits.source, 2)
node _T_1056 = eq(_T_1055, UInt<1>(0h1))
node _T_1057 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_1058 = and(_T_1056, _T_1057)
node _T_1059 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_1060 = and(_T_1058, _T_1059)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_1061 = shr(io.in.a.bits.source, 2)
node _T_1062 = eq(_T_1061, UInt<2>(0h2))
node _T_1063 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_1064 = and(_T_1062, _T_1063)
node _T_1065 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_1066 = and(_T_1064, _T_1065)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_1067 = shr(io.in.a.bits.source, 2)
node _T_1068 = eq(_T_1067, UInt<2>(0h3))
node _T_1069 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_1070 = and(_T_1068, _T_1069)
node _T_1071 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_1072 = and(_T_1070, _T_1071)
node _T_1073 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1074 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1075 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1076 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1077 = or(_T_1048, _T_1054)
node _T_1078 = or(_T_1077, _T_1060)
node _T_1079 = or(_T_1078, _T_1066)
node _T_1080 = or(_T_1079, _T_1072)
node _T_1081 = or(_T_1080, _T_1073)
node _T_1082 = or(_T_1081, _T_1074)
node _T_1083 = or(_T_1082, _T_1075)
node _T_1084 = or(_T_1083, _T_1076)
node _T_1085 = and(_T_1047, _T_1084)
node _T_1086 = or(UInt<1>(0h0), _T_1085)
node _T_1087 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1088 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1089 = and(_T_1087, _T_1088)
node _T_1090 = or(UInt<1>(0h0), _T_1089)
node _T_1091 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_1092 = cvt(_T_1091)
node _T_1093 = and(_T_1092, asSInt(UInt<15>(0h5000)))
node _T_1094 = asSInt(_T_1093)
node _T_1095 = eq(_T_1094, asSInt(UInt<1>(0h0)))
node _T_1096 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1097 = cvt(_T_1096)
node _T_1098 = and(_T_1097, asSInt(UInt<13>(0h1000)))
node _T_1099 = asSInt(_T_1098)
node _T_1100 = eq(_T_1099, asSInt(UInt<1>(0h0)))
node _T_1101 = or(_T_1095, _T_1100)
node _T_1102 = and(_T_1090, _T_1101)
node _T_1103 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1104 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1105 = cvt(_T_1104)
node _T_1106 = and(_T_1105, asSInt(UInt<13>(0h1000)))
node _T_1107 = asSInt(_T_1106)
node _T_1108 = eq(_T_1107, asSInt(UInt<1>(0h0)))
node _T_1109 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1110 = cvt(_T_1109)
node _T_1111 = and(_T_1110, asSInt(UInt<17>(0h10000)))
node _T_1112 = asSInt(_T_1111)
node _T_1113 = eq(_T_1112, asSInt(UInt<1>(0h0)))
node _T_1114 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1115 = cvt(_T_1114)
node _T_1116 = and(_T_1115, asSInt(UInt<18>(0h2f000)))
node _T_1117 = asSInt(_T_1116)
node _T_1118 = eq(_T_1117, asSInt(UInt<1>(0h0)))
node _T_1119 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1120 = cvt(_T_1119)
node _T_1121 = and(_T_1120, asSInt(UInt<17>(0h10000)))
node _T_1122 = asSInt(_T_1121)
node _T_1123 = eq(_T_1122, asSInt(UInt<1>(0h0)))
node _T_1124 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1125 = cvt(_T_1124)
node _T_1126 = and(_T_1125, asSInt(UInt<13>(0h1000)))
node _T_1127 = asSInt(_T_1126)
node _T_1128 = eq(_T_1127, asSInt(UInt<1>(0h0)))
node _T_1129 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1130 = cvt(_T_1129)
node _T_1131 = and(_T_1130, asSInt(UInt<27>(0h4000000)))
node _T_1132 = asSInt(_T_1131)
node _T_1133 = eq(_T_1132, asSInt(UInt<1>(0h0)))
node _T_1134 = or(_T_1108, _T_1113)
node _T_1135 = or(_T_1134, _T_1118)
node _T_1136 = or(_T_1135, _T_1123)
node _T_1137 = or(_T_1136, _T_1128)
node _T_1138 = or(_T_1137, _T_1133)
node _T_1139 = and(_T_1103, _T_1138)
node _T_1140 = or(UInt<1>(0h0), _T_1102)
node _T_1141 = or(_T_1140, _T_1139)
node _T_1142 = and(_T_1086, _T_1141)
node _T_1143 = asUInt(reset)
node _T_1144 = eq(_T_1143, UInt<1>(0h0))
when _T_1144 :
node _T_1145 = eq(_T_1142, UInt<1>(0h0))
when _T_1145 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1142, UInt<1>(0h1), "") : assert_41
node _T_1146 = asUInt(reset)
node _T_1147 = eq(_T_1146, UInt<1>(0h0))
when _T_1147 :
node _T_1148 = eq(source_ok, UInt<1>(0h0))
when _T_1148 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1149 = asUInt(reset)
node _T_1150 = eq(_T_1149, UInt<1>(0h0))
when _T_1150 :
node _T_1151 = eq(is_aligned, UInt<1>(0h0))
when _T_1151 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1152 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1153 = asUInt(reset)
node _T_1154 = eq(_T_1153, UInt<1>(0h0))
when _T_1154 :
node _T_1155 = eq(_T_1152, UInt<1>(0h0))
when _T_1155 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1152, UInt<1>(0h1), "") : assert_44
node _T_1156 = eq(io.in.a.bits.mask, mask)
node _T_1157 = asUInt(reset)
node _T_1158 = eq(_T_1157, UInt<1>(0h0))
when _T_1158 :
node _T_1159 = eq(_T_1156, UInt<1>(0h0))
when _T_1159 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1156, UInt<1>(0h1), "") : assert_45
node _T_1160 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1160 :
node _T_1161 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1162 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1163 = and(_T_1161, _T_1162)
node _T_1164 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_1165 = shr(io.in.a.bits.source, 2)
node _T_1166 = eq(_T_1165, UInt<1>(0h0))
node _T_1167 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_1168 = and(_T_1166, _T_1167)
node _T_1169 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_1170 = and(_T_1168, _T_1169)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_1171 = shr(io.in.a.bits.source, 2)
node _T_1172 = eq(_T_1171, UInt<1>(0h1))
node _T_1173 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_1174 = and(_T_1172, _T_1173)
node _T_1175 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_1176 = and(_T_1174, _T_1175)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_1177 = shr(io.in.a.bits.source, 2)
node _T_1178 = eq(_T_1177, UInt<2>(0h2))
node _T_1179 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_1180 = and(_T_1178, _T_1179)
node _T_1181 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_1182 = and(_T_1180, _T_1181)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_1183 = shr(io.in.a.bits.source, 2)
node _T_1184 = eq(_T_1183, UInt<2>(0h3))
node _T_1185 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_1186 = and(_T_1184, _T_1185)
node _T_1187 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_1188 = and(_T_1186, _T_1187)
node _T_1189 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1190 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1191 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1192 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1193 = or(_T_1164, _T_1170)
node _T_1194 = or(_T_1193, _T_1176)
node _T_1195 = or(_T_1194, _T_1182)
node _T_1196 = or(_T_1195, _T_1188)
node _T_1197 = or(_T_1196, _T_1189)
node _T_1198 = or(_T_1197, _T_1190)
node _T_1199 = or(_T_1198, _T_1191)
node _T_1200 = or(_T_1199, _T_1192)
node _T_1201 = and(_T_1163, _T_1200)
node _T_1202 = or(UInt<1>(0h0), _T_1201)
node _T_1203 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1204 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1205 = and(_T_1203, _T_1204)
node _T_1206 = or(UInt<1>(0h0), _T_1205)
node _T_1207 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1208 = cvt(_T_1207)
node _T_1209 = and(_T_1208, asSInt(UInt<13>(0h1000)))
node _T_1210 = asSInt(_T_1209)
node _T_1211 = eq(_T_1210, asSInt(UInt<1>(0h0)))
node _T_1212 = and(_T_1206, _T_1211)
node _T_1213 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1214 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1215 = cvt(_T_1214)
node _T_1216 = and(_T_1215, asSInt(UInt<14>(0h2000)))
node _T_1217 = asSInt(_T_1216)
node _T_1218 = eq(_T_1217, asSInt(UInt<1>(0h0)))
node _T_1219 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1220 = cvt(_T_1219)
node _T_1221 = and(_T_1220, asSInt(UInt<17>(0h10000)))
node _T_1222 = asSInt(_T_1221)
node _T_1223 = eq(_T_1222, asSInt(UInt<1>(0h0)))
node _T_1224 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1225 = cvt(_T_1224)
node _T_1226 = and(_T_1225, asSInt(UInt<18>(0h2f000)))
node _T_1227 = asSInt(_T_1226)
node _T_1228 = eq(_T_1227, asSInt(UInt<1>(0h0)))
node _T_1229 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1230 = cvt(_T_1229)
node _T_1231 = and(_T_1230, asSInt(UInt<17>(0h10000)))
node _T_1232 = asSInt(_T_1231)
node _T_1233 = eq(_T_1232, asSInt(UInt<1>(0h0)))
node _T_1234 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1235 = cvt(_T_1234)
node _T_1236 = and(_T_1235, asSInt(UInt<13>(0h1000)))
node _T_1237 = asSInt(_T_1236)
node _T_1238 = eq(_T_1237, asSInt(UInt<1>(0h0)))
node _T_1239 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1240 = cvt(_T_1239)
node _T_1241 = and(_T_1240, asSInt(UInt<27>(0h4000000)))
node _T_1242 = asSInt(_T_1241)
node _T_1243 = eq(_T_1242, asSInt(UInt<1>(0h0)))
node _T_1244 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1245 = cvt(_T_1244)
node _T_1246 = and(_T_1245, asSInt(UInt<13>(0h1000)))
node _T_1247 = asSInt(_T_1246)
node _T_1248 = eq(_T_1247, asSInt(UInt<1>(0h0)))
node _T_1249 = or(_T_1218, _T_1223)
node _T_1250 = or(_T_1249, _T_1228)
node _T_1251 = or(_T_1250, _T_1233)
node _T_1252 = or(_T_1251, _T_1238)
node _T_1253 = or(_T_1252, _T_1243)
node _T_1254 = or(_T_1253, _T_1248)
node _T_1255 = and(_T_1213, _T_1254)
node _T_1256 = or(UInt<1>(0h0), _T_1212)
node _T_1257 = or(_T_1256, _T_1255)
node _T_1258 = and(_T_1202, _T_1257)
node _T_1259 = asUInt(reset)
node _T_1260 = eq(_T_1259, UInt<1>(0h0))
when _T_1260 :
node _T_1261 = eq(_T_1258, UInt<1>(0h0))
when _T_1261 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1258, UInt<1>(0h1), "") : assert_46
node _T_1262 = asUInt(reset)
node _T_1263 = eq(_T_1262, UInt<1>(0h0))
when _T_1263 :
node _T_1264 = eq(source_ok, UInt<1>(0h0))
when _T_1264 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1265 = asUInt(reset)
node _T_1266 = eq(_T_1265, UInt<1>(0h0))
when _T_1266 :
node _T_1267 = eq(is_aligned, UInt<1>(0h0))
when _T_1267 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1268 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1269 = asUInt(reset)
node _T_1270 = eq(_T_1269, UInt<1>(0h0))
when _T_1270 :
node _T_1271 = eq(_T_1268, UInt<1>(0h0))
when _T_1271 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1268, UInt<1>(0h1), "") : assert_49
node _T_1272 = eq(io.in.a.bits.mask, mask)
node _T_1273 = asUInt(reset)
node _T_1274 = eq(_T_1273, UInt<1>(0h0))
when _T_1274 :
node _T_1275 = eq(_T_1272, UInt<1>(0h0))
when _T_1275 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1272, UInt<1>(0h1), "") : assert_50
node _T_1276 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1277 = asUInt(reset)
node _T_1278 = eq(_T_1277, UInt<1>(0h0))
when _T_1278 :
node _T_1279 = eq(_T_1276, UInt<1>(0h0))
when _T_1279 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1276, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1280 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1281 = asUInt(reset)
node _T_1282 = eq(_T_1281, UInt<1>(0h0))
when _T_1282 :
node _T_1283 = eq(_T_1280, UInt<1>(0h0))
when _T_1283 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1280, UInt<1>(0h1), "") : assert_52
node _source_ok_T_36 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_37 = shr(io.in.d.bits.source, 2)
node _source_ok_T_38 = eq(_source_ok_T_37, UInt<1>(0h0))
node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39)
node _source_ok_T_41 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_43 = shr(io.in.d.bits.source, 2)
node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h1))
node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45)
node _source_ok_T_47 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_49 = shr(io.in.d.bits.source, 2)
node _source_ok_T_50 = eq(_source_ok_T_49, UInt<2>(0h2))
node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51)
node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_55 = shr(io.in.d.bits.source, 2)
node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h3))
node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57)
node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59)
node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<6>(0h22))
node _source_ok_T_62 = eq(io.in.d.bits.source, UInt<6>(0h21))
node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE_1 : UInt<1>[9]
connect _source_ok_WIRE_1[0], _source_ok_T_36
connect _source_ok_WIRE_1[1], _source_ok_T_42
connect _source_ok_WIRE_1[2], _source_ok_T_48
connect _source_ok_WIRE_1[3], _source_ok_T_54
connect _source_ok_WIRE_1[4], _source_ok_T_60
connect _source_ok_WIRE_1[5], _source_ok_T_61
connect _source_ok_WIRE_1[6], _source_ok_T_62
connect _source_ok_WIRE_1[7], _source_ok_T_63
connect _source_ok_WIRE_1[8], _source_ok_T_64
node _source_ok_T_65 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[2])
node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[3])
node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE_1[4])
node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[5])
node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[6])
node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[7])
node source_ok_1 = or(_source_ok_T_71, _source_ok_WIRE_1[8])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1284 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1284 :
node _T_1285 = asUInt(reset)
node _T_1286 = eq(_T_1285, UInt<1>(0h0))
when _T_1286 :
node _T_1287 = eq(source_ok_1, UInt<1>(0h0))
when _T_1287 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1288 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1289 = asUInt(reset)
node _T_1290 = eq(_T_1289, UInt<1>(0h0))
when _T_1290 :
node _T_1291 = eq(_T_1288, UInt<1>(0h0))
when _T_1291 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1288, UInt<1>(0h1), "") : assert_54
node _T_1292 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1293 = asUInt(reset)
node _T_1294 = eq(_T_1293, UInt<1>(0h0))
when _T_1294 :
node _T_1295 = eq(_T_1292, UInt<1>(0h0))
when _T_1295 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1292, UInt<1>(0h1), "") : assert_55
node _T_1296 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1297 = asUInt(reset)
node _T_1298 = eq(_T_1297, UInt<1>(0h0))
when _T_1298 :
node _T_1299 = eq(_T_1296, UInt<1>(0h0))
when _T_1299 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1296, UInt<1>(0h1), "") : assert_56
node _T_1300 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1301 = asUInt(reset)
node _T_1302 = eq(_T_1301, UInt<1>(0h0))
when _T_1302 :
node _T_1303 = eq(_T_1300, UInt<1>(0h0))
when _T_1303 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1300, UInt<1>(0h1), "") : assert_57
node _T_1304 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1304 :
node _T_1305 = asUInt(reset)
node _T_1306 = eq(_T_1305, UInt<1>(0h0))
when _T_1306 :
node _T_1307 = eq(source_ok_1, UInt<1>(0h0))
when _T_1307 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1308 = asUInt(reset)
node _T_1309 = eq(_T_1308, UInt<1>(0h0))
when _T_1309 :
node _T_1310 = eq(sink_ok, UInt<1>(0h0))
when _T_1310 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1311 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1312 = asUInt(reset)
node _T_1313 = eq(_T_1312, UInt<1>(0h0))
when _T_1313 :
node _T_1314 = eq(_T_1311, UInt<1>(0h0))
when _T_1314 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1311, UInt<1>(0h1), "") : assert_60
node _T_1315 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1316 = asUInt(reset)
node _T_1317 = eq(_T_1316, UInt<1>(0h0))
when _T_1317 :
node _T_1318 = eq(_T_1315, UInt<1>(0h0))
when _T_1318 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1315, UInt<1>(0h1), "") : assert_61
node _T_1319 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1320 = asUInt(reset)
node _T_1321 = eq(_T_1320, UInt<1>(0h0))
when _T_1321 :
node _T_1322 = eq(_T_1319, UInt<1>(0h0))
when _T_1322 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1319, UInt<1>(0h1), "") : assert_62
node _T_1323 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1324 = asUInt(reset)
node _T_1325 = eq(_T_1324, UInt<1>(0h0))
when _T_1325 :
node _T_1326 = eq(_T_1323, UInt<1>(0h0))
when _T_1326 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1323, UInt<1>(0h1), "") : assert_63
node _T_1327 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1328 = or(UInt<1>(0h1), _T_1327)
node _T_1329 = asUInt(reset)
node _T_1330 = eq(_T_1329, UInt<1>(0h0))
when _T_1330 :
node _T_1331 = eq(_T_1328, UInt<1>(0h0))
when _T_1331 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1328, UInt<1>(0h1), "") : assert_64
node _T_1332 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1332 :
node _T_1333 = asUInt(reset)
node _T_1334 = eq(_T_1333, UInt<1>(0h0))
when _T_1334 :
node _T_1335 = eq(source_ok_1, UInt<1>(0h0))
when _T_1335 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1336 = asUInt(reset)
node _T_1337 = eq(_T_1336, UInt<1>(0h0))
when _T_1337 :
node _T_1338 = eq(sink_ok, UInt<1>(0h0))
when _T_1338 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1339 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1340 = asUInt(reset)
node _T_1341 = eq(_T_1340, UInt<1>(0h0))
when _T_1341 :
node _T_1342 = eq(_T_1339, UInt<1>(0h0))
when _T_1342 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1339, UInt<1>(0h1), "") : assert_67
node _T_1343 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1344 = asUInt(reset)
node _T_1345 = eq(_T_1344, UInt<1>(0h0))
when _T_1345 :
node _T_1346 = eq(_T_1343, UInt<1>(0h0))
when _T_1346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1343, UInt<1>(0h1), "") : assert_68
node _T_1347 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1348 = asUInt(reset)
node _T_1349 = eq(_T_1348, UInt<1>(0h0))
when _T_1349 :
node _T_1350 = eq(_T_1347, UInt<1>(0h0))
when _T_1350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1347, UInt<1>(0h1), "") : assert_69
node _T_1351 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1352 = or(_T_1351, io.in.d.bits.corrupt)
node _T_1353 = asUInt(reset)
node _T_1354 = eq(_T_1353, UInt<1>(0h0))
when _T_1354 :
node _T_1355 = eq(_T_1352, UInt<1>(0h0))
when _T_1355 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1352, UInt<1>(0h1), "") : assert_70
node _T_1356 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1357 = or(UInt<1>(0h1), _T_1356)
node _T_1358 = asUInt(reset)
node _T_1359 = eq(_T_1358, UInt<1>(0h0))
when _T_1359 :
node _T_1360 = eq(_T_1357, UInt<1>(0h0))
when _T_1360 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1357, UInt<1>(0h1), "") : assert_71
node _T_1361 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1361 :
node _T_1362 = asUInt(reset)
node _T_1363 = eq(_T_1362, UInt<1>(0h0))
when _T_1363 :
node _T_1364 = eq(source_ok_1, UInt<1>(0h0))
when _T_1364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1365 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1366 = asUInt(reset)
node _T_1367 = eq(_T_1366, UInt<1>(0h0))
when _T_1367 :
node _T_1368 = eq(_T_1365, UInt<1>(0h0))
when _T_1368 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1365, UInt<1>(0h1), "") : assert_73
node _T_1369 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1370 = asUInt(reset)
node _T_1371 = eq(_T_1370, UInt<1>(0h0))
when _T_1371 :
node _T_1372 = eq(_T_1369, UInt<1>(0h0))
when _T_1372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1369, UInt<1>(0h1), "") : assert_74
node _T_1373 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1374 = or(UInt<1>(0h1), _T_1373)
node _T_1375 = asUInt(reset)
node _T_1376 = eq(_T_1375, UInt<1>(0h0))
when _T_1376 :
node _T_1377 = eq(_T_1374, UInt<1>(0h0))
when _T_1377 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1374, UInt<1>(0h1), "") : assert_75
node _T_1378 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1378 :
node _T_1379 = asUInt(reset)
node _T_1380 = eq(_T_1379, UInt<1>(0h0))
when _T_1380 :
node _T_1381 = eq(source_ok_1, UInt<1>(0h0))
when _T_1381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1382 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1383 = asUInt(reset)
node _T_1384 = eq(_T_1383, UInt<1>(0h0))
when _T_1384 :
node _T_1385 = eq(_T_1382, UInt<1>(0h0))
when _T_1385 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1382, UInt<1>(0h1), "") : assert_77
node _T_1386 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1387 = or(_T_1386, io.in.d.bits.corrupt)
node _T_1388 = asUInt(reset)
node _T_1389 = eq(_T_1388, UInt<1>(0h0))
when _T_1389 :
node _T_1390 = eq(_T_1387, UInt<1>(0h0))
when _T_1390 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1387, UInt<1>(0h1), "") : assert_78
node _T_1391 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1392 = or(UInt<1>(0h1), _T_1391)
node _T_1393 = asUInt(reset)
node _T_1394 = eq(_T_1393, UInt<1>(0h0))
when _T_1394 :
node _T_1395 = eq(_T_1392, UInt<1>(0h0))
when _T_1395 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1392, UInt<1>(0h1), "") : assert_79
node _T_1396 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1396 :
node _T_1397 = asUInt(reset)
node _T_1398 = eq(_T_1397, UInt<1>(0h0))
when _T_1398 :
node _T_1399 = eq(source_ok_1, UInt<1>(0h0))
when _T_1399 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1400 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1401 = asUInt(reset)
node _T_1402 = eq(_T_1401, UInt<1>(0h0))
when _T_1402 :
node _T_1403 = eq(_T_1400, UInt<1>(0h0))
when _T_1403 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1400, UInt<1>(0h1), "") : assert_81
node _T_1404 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1405 = asUInt(reset)
node _T_1406 = eq(_T_1405, UInt<1>(0h0))
when _T_1406 :
node _T_1407 = eq(_T_1404, UInt<1>(0h0))
when _T_1407 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1404, UInt<1>(0h1), "") : assert_82
node _T_1408 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1409 = or(UInt<1>(0h1), _T_1408)
node _T_1410 = asUInt(reset)
node _T_1411 = eq(_T_1410, UInt<1>(0h0))
when _T_1411 :
node _T_1412 = eq(_T_1409, UInt<1>(0h0))
when _T_1412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1409, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<29>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<4>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1413 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1414 = asUInt(reset)
node _T_1415 = eq(_T_1414, UInt<1>(0h0))
when _T_1415 :
node _T_1416 = eq(_T_1413, UInt<1>(0h0))
when _T_1416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1413, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1417 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1418 = asUInt(reset)
node _T_1419 = eq(_T_1418, UInt<1>(0h0))
when _T_1419 :
node _T_1420 = eq(_T_1417, UInt<1>(0h0))
when _T_1420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1417, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1421 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1422 = asUInt(reset)
node _T_1423 = eq(_T_1422, UInt<1>(0h0))
when _T_1423 :
node _T_1424 = eq(_T_1421, UInt<1>(0h0))
when _T_1424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1421, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1425 = eq(a_first, UInt<1>(0h0))
node _T_1426 = and(io.in.a.valid, _T_1425)
when _T_1426 :
node _T_1427 = eq(io.in.a.bits.opcode, opcode)
node _T_1428 = asUInt(reset)
node _T_1429 = eq(_T_1428, UInt<1>(0h0))
when _T_1429 :
node _T_1430 = eq(_T_1427, UInt<1>(0h0))
when _T_1430 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1427, UInt<1>(0h1), "") : assert_87
node _T_1431 = eq(io.in.a.bits.param, param)
node _T_1432 = asUInt(reset)
node _T_1433 = eq(_T_1432, UInt<1>(0h0))
when _T_1433 :
node _T_1434 = eq(_T_1431, UInt<1>(0h0))
when _T_1434 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1431, UInt<1>(0h1), "") : assert_88
node _T_1435 = eq(io.in.a.bits.size, size)
node _T_1436 = asUInt(reset)
node _T_1437 = eq(_T_1436, UInt<1>(0h0))
when _T_1437 :
node _T_1438 = eq(_T_1435, UInt<1>(0h0))
when _T_1438 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1435, UInt<1>(0h1), "") : assert_89
node _T_1439 = eq(io.in.a.bits.source, source)
node _T_1440 = asUInt(reset)
node _T_1441 = eq(_T_1440, UInt<1>(0h0))
when _T_1441 :
node _T_1442 = eq(_T_1439, UInt<1>(0h0))
when _T_1442 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1439, UInt<1>(0h1), "") : assert_90
node _T_1443 = eq(io.in.a.bits.address, address)
node _T_1444 = asUInt(reset)
node _T_1445 = eq(_T_1444, UInt<1>(0h0))
when _T_1445 :
node _T_1446 = eq(_T_1443, UInt<1>(0h0))
when _T_1446 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1443, UInt<1>(0h1), "") : assert_91
node _T_1447 = and(io.in.a.ready, io.in.a.valid)
node _T_1448 = and(_T_1447, a_first)
when _T_1448 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1449 = eq(d_first, UInt<1>(0h0))
node _T_1450 = and(io.in.d.valid, _T_1449)
when _T_1450 :
node _T_1451 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1452 = asUInt(reset)
node _T_1453 = eq(_T_1452, UInt<1>(0h0))
when _T_1453 :
node _T_1454 = eq(_T_1451, UInt<1>(0h0))
when _T_1454 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1451, UInt<1>(0h1), "") : assert_92
node _T_1455 = eq(io.in.d.bits.param, param_1)
node _T_1456 = asUInt(reset)
node _T_1457 = eq(_T_1456, UInt<1>(0h0))
when _T_1457 :
node _T_1458 = eq(_T_1455, UInt<1>(0h0))
when _T_1458 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1455, UInt<1>(0h1), "") : assert_93
node _T_1459 = eq(io.in.d.bits.size, size_1)
node _T_1460 = asUInt(reset)
node _T_1461 = eq(_T_1460, UInt<1>(0h0))
when _T_1461 :
node _T_1462 = eq(_T_1459, UInt<1>(0h0))
when _T_1462 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1459, UInt<1>(0h1), "") : assert_94
node _T_1463 = eq(io.in.d.bits.source, source_1)
node _T_1464 = asUInt(reset)
node _T_1465 = eq(_T_1464, UInt<1>(0h0))
when _T_1465 :
node _T_1466 = eq(_T_1463, UInt<1>(0h0))
when _T_1466 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1463, UInt<1>(0h1), "") : assert_95
node _T_1467 = eq(io.in.d.bits.sink, sink)
node _T_1468 = asUInt(reset)
node _T_1469 = eq(_T_1468, UInt<1>(0h0))
when _T_1469 :
node _T_1470 = eq(_T_1467, UInt<1>(0h0))
when _T_1470 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1467, UInt<1>(0h1), "") : assert_96
node _T_1471 = eq(io.in.d.bits.denied, denied)
node _T_1472 = asUInt(reset)
node _T_1473 = eq(_T_1472, UInt<1>(0h0))
when _T_1473 :
node _T_1474 = eq(_T_1471, UInt<1>(0h0))
when _T_1474 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1471, UInt<1>(0h1), "") : assert_97
node _T_1475 = and(io.in.d.ready, io.in.d.valid)
node _T_1476 = and(_T_1475, d_first)
when _T_1476 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes : UInt<520>, clock, reset, UInt<520>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<65>
connect a_set, UInt<65>(0h0)
wire a_set_wo_ready : UInt<65>
connect a_set_wo_ready, UInt<65>(0h0)
wire a_opcodes_set : UInt<260>
connect a_opcodes_set, UInt<260>(0h0)
wire a_sizes_set : UInt<520>
connect a_sizes_set, UInt<520>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1477 = and(io.in.a.valid, a_first_1)
node _T_1478 = and(_T_1477, UInt<1>(0h1))
when _T_1478 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1479 = and(io.in.a.ready, io.in.a.valid)
node _T_1480 = and(_T_1479, a_first_1)
node _T_1481 = and(_T_1480, UInt<1>(0h1))
when _T_1481 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1482 = dshr(inflight, io.in.a.bits.source)
node _T_1483 = bits(_T_1482, 0, 0)
node _T_1484 = eq(_T_1483, UInt<1>(0h0))
node _T_1485 = asUInt(reset)
node _T_1486 = eq(_T_1485, UInt<1>(0h0))
when _T_1486 :
node _T_1487 = eq(_T_1484, UInt<1>(0h0))
when _T_1487 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1484, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<65>
connect d_clr, UInt<65>(0h0)
wire d_clr_wo_ready : UInt<65>
connect d_clr_wo_ready, UInt<65>(0h0)
wire d_opcodes_clr : UInt<260>
connect d_opcodes_clr, UInt<260>(0h0)
wire d_sizes_clr : UInt<520>
connect d_sizes_clr, UInt<520>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1488 = and(io.in.d.valid, d_first_1)
node _T_1489 = and(_T_1488, UInt<1>(0h1))
node _T_1490 = eq(d_release_ack, UInt<1>(0h0))
node _T_1491 = and(_T_1489, _T_1490)
when _T_1491 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1492 = and(io.in.d.ready, io.in.d.valid)
node _T_1493 = and(_T_1492, d_first_1)
node _T_1494 = and(_T_1493, UInt<1>(0h1))
node _T_1495 = eq(d_release_ack, UInt<1>(0h0))
node _T_1496 = and(_T_1494, _T_1495)
when _T_1496 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1497 = and(io.in.d.valid, d_first_1)
node _T_1498 = and(_T_1497, UInt<1>(0h1))
node _T_1499 = eq(d_release_ack, UInt<1>(0h0))
node _T_1500 = and(_T_1498, _T_1499)
when _T_1500 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1501 = dshr(inflight, io.in.d.bits.source)
node _T_1502 = bits(_T_1501, 0, 0)
node _T_1503 = or(_T_1502, same_cycle_resp)
node _T_1504 = asUInt(reset)
node _T_1505 = eq(_T_1504, UInt<1>(0h0))
when _T_1505 :
node _T_1506 = eq(_T_1503, UInt<1>(0h0))
when _T_1506 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1503, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1507 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1508 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1509 = or(_T_1507, _T_1508)
node _T_1510 = asUInt(reset)
node _T_1511 = eq(_T_1510, UInt<1>(0h0))
when _T_1511 :
node _T_1512 = eq(_T_1509, UInt<1>(0h0))
when _T_1512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1509, UInt<1>(0h1), "") : assert_100
node _T_1513 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1514 = asUInt(reset)
node _T_1515 = eq(_T_1514, UInt<1>(0h0))
when _T_1515 :
node _T_1516 = eq(_T_1513, UInt<1>(0h0))
when _T_1516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1513, UInt<1>(0h1), "") : assert_101
else :
node _T_1517 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1518 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1519 = or(_T_1517, _T_1518)
node _T_1520 = asUInt(reset)
node _T_1521 = eq(_T_1520, UInt<1>(0h0))
when _T_1521 :
node _T_1522 = eq(_T_1519, UInt<1>(0h0))
when _T_1522 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1519, UInt<1>(0h1), "") : assert_102
node _T_1523 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1524 = asUInt(reset)
node _T_1525 = eq(_T_1524, UInt<1>(0h0))
when _T_1525 :
node _T_1526 = eq(_T_1523, UInt<1>(0h0))
when _T_1526 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1523, UInt<1>(0h1), "") : assert_103
node _T_1527 = and(io.in.d.valid, d_first_1)
node _T_1528 = and(_T_1527, a_first_1)
node _T_1529 = and(_T_1528, io.in.a.valid)
node _T_1530 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1531 = and(_T_1529, _T_1530)
node _T_1532 = eq(d_release_ack, UInt<1>(0h0))
node _T_1533 = and(_T_1531, _T_1532)
when _T_1533 :
node _T_1534 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1535 = or(_T_1534, io.in.a.ready)
node _T_1536 = asUInt(reset)
node _T_1537 = eq(_T_1536, UInt<1>(0h0))
when _T_1537 :
node _T_1538 = eq(_T_1535, UInt<1>(0h0))
when _T_1538 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1535, UInt<1>(0h1), "") : assert_104
node _T_1539 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1540 = orr(a_set_wo_ready)
node _T_1541 = eq(_T_1540, UInt<1>(0h0))
node _T_1542 = or(_T_1539, _T_1541)
node _T_1543 = asUInt(reset)
node _T_1544 = eq(_T_1543, UInt<1>(0h0))
when _T_1544 :
node _T_1545 = eq(_T_1542, UInt<1>(0h0))
when _T_1545 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1542, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_34
node _T_1546 = orr(inflight)
node _T_1547 = eq(_T_1546, UInt<1>(0h0))
node _T_1548 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1549 = or(_T_1547, _T_1548)
node _T_1550 = lt(watchdog, plusarg_reader.out)
node _T_1551 = or(_T_1549, _T_1550)
node _T_1552 = asUInt(reset)
node _T_1553 = eq(_T_1552, UInt<1>(0h0))
when _T_1553 :
node _T_1554 = eq(_T_1551, UInt<1>(0h0))
when _T_1554 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1551, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1555 = and(io.in.a.ready, io.in.a.valid)
node _T_1556 = and(io.in.d.ready, io.in.d.valid)
node _T_1557 = or(_T_1555, _T_1556)
when _T_1557 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes_1 : UInt<520>, clock, reset, UInt<520>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<29>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<65>
connect c_set, UInt<65>(0h0)
wire c_set_wo_ready : UInt<65>
connect c_set_wo_ready, UInt<65>(0h0)
wire c_opcodes_set : UInt<260>
connect c_opcodes_set, UInt<260>(0h0)
wire c_sizes_set : UInt<520>
connect c_sizes_set, UInt<520>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<29>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1558 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<29>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1559 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1560 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1561 = and(_T_1559, _T_1560)
node _T_1562 = and(_T_1558, _T_1561)
when _T_1562 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<29>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1563 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1564 = and(_T_1563, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<29>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1565 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1566 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1567 = and(_T_1565, _T_1566)
node _T_1568 = and(_T_1564, _T_1567)
when _T_1568 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<29>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1569 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1570 = bits(_T_1569, 0, 0)
node _T_1571 = eq(_T_1570, UInt<1>(0h0))
node _T_1572 = asUInt(reset)
node _T_1573 = eq(_T_1572, UInt<1>(0h0))
when _T_1573 :
node _T_1574 = eq(_T_1571, UInt<1>(0h0))
when _T_1574 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1571, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<65>
connect d_clr_1, UInt<65>(0h0)
wire d_clr_wo_ready_1 : UInt<65>
connect d_clr_wo_ready_1, UInt<65>(0h0)
wire d_opcodes_clr_1 : UInt<260>
connect d_opcodes_clr_1, UInt<260>(0h0)
wire d_sizes_clr_1 : UInt<520>
connect d_sizes_clr_1, UInt<520>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1575 = and(io.in.d.valid, d_first_2)
node _T_1576 = and(_T_1575, UInt<1>(0h1))
node _T_1577 = and(_T_1576, d_release_ack_1)
when _T_1577 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1578 = and(io.in.d.ready, io.in.d.valid)
node _T_1579 = and(_T_1578, d_first_2)
node _T_1580 = and(_T_1579, UInt<1>(0h1))
node _T_1581 = and(_T_1580, d_release_ack_1)
when _T_1581 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1582 = and(io.in.d.valid, d_first_2)
node _T_1583 = and(_T_1582, UInt<1>(0h1))
node _T_1584 = and(_T_1583, d_release_ack_1)
when _T_1584 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1585 = dshr(inflight_1, io.in.d.bits.source)
node _T_1586 = bits(_T_1585, 0, 0)
node _T_1587 = or(_T_1586, same_cycle_resp_1)
node _T_1588 = asUInt(reset)
node _T_1589 = eq(_T_1588, UInt<1>(0h0))
when _T_1589 :
node _T_1590 = eq(_T_1587, UInt<1>(0h0))
when _T_1590 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1587, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<29>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1591 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1592 = asUInt(reset)
node _T_1593 = eq(_T_1592, UInt<1>(0h0))
when _T_1593 :
node _T_1594 = eq(_T_1591, UInt<1>(0h0))
when _T_1594 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1591, UInt<1>(0h1), "") : assert_109
else :
node _T_1595 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1596 = asUInt(reset)
node _T_1597 = eq(_T_1596, UInt<1>(0h0))
when _T_1597 :
node _T_1598 = eq(_T_1595, UInt<1>(0h0))
when _T_1598 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1595, UInt<1>(0h1), "") : assert_110
node _T_1599 = and(io.in.d.valid, d_first_2)
node _T_1600 = and(_T_1599, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<29>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1601 = and(_T_1600, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<29>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1602 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1603 = and(_T_1601, _T_1602)
node _T_1604 = and(_T_1603, d_release_ack_1)
node _T_1605 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1606 = and(_T_1604, _T_1605)
when _T_1606 :
node _T_1607 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<29>(0h0)
connect _WIRE_26.bits.source, UInt<7>(0h0)
connect _WIRE_26.bits.size, UInt<4>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1608 = or(_T_1607, _WIRE_27.ready)
node _T_1609 = asUInt(reset)
node _T_1610 = eq(_T_1609, UInt<1>(0h0))
when _T_1610 :
node _T_1611 = eq(_T_1608, UInt<1>(0h0))
when _T_1611 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1608, UInt<1>(0h1), "") : assert_111
node _T_1612 = orr(c_set_wo_ready)
when _T_1612 :
node _T_1613 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1614 = asUInt(reset)
node _T_1615 = eq(_T_1614, UInt<1>(0h0))
when _T_1615 :
node _T_1616 = eq(_T_1613, UInt<1>(0h0))
when _T_1616 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1613, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_35
node _T_1617 = orr(inflight_1)
node _T_1618 = eq(_T_1617, UInt<1>(0h0))
node _T_1619 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1620 = or(_T_1618, _T_1619)
node _T_1621 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1622 = or(_T_1620, _T_1621)
node _T_1623 = asUInt(reset)
node _T_1624 = eq(_T_1623, UInt<1>(0h0))
when _T_1624 :
node _T_1625 = eq(_T_1622, UInt<1>(0h0))
when _T_1625 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1622, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<29>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<4>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1626 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1627 = and(io.in.d.ready, io.in.d.valid)
node _T_1628 = or(_T_1626, _T_1627)
when _T_1628 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_17( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [519:0] c_sizes_set = 520'h0; // @[Monitor.scala:741:34]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31]
wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31]
wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31]
wire _source_ok_T_29 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_32 = _source_ok_T_31 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_34 = _source_ok_T_33 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_35 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_36 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_37 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_43 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_38 = _source_ok_T_37 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_42; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_44 = _source_ok_T_43 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_48; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_50 = _source_ok_T_49 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_54; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_56 = _source_ok_T_55 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_60; // @[Parameters.scala:1138:31]
wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_61; // @[Parameters.scala:1138:31]
wire _source_ok_T_62 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_62; // @[Parameters.scala:1138:31]
wire _source_ok_T_63 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_63; // @[Parameters.scala:1138:31]
wire _source_ok_T_64 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_64; // @[Parameters.scala:1138:31]
wire _source_ok_T_65 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_68 = _source_ok_T_67 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_69 = _source_ok_T_68 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_70 = _source_ok_T_69 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_71 = _source_ok_T_70 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_71 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1555 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1555; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1555; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_1628 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1628; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1628; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1628; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [519:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [519:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [519:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [519:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [519:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[519:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1481 = _T_1555 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1481 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1481 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1481 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1481 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1481 ? _a_sizes_set_T_1[519:0] : 520'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [519:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1527 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1527 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1496 = _T_1628 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1496 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1496 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1496 ? _d_sizes_clr_T_5[519:0] : 520'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [519:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [519:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [519:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [519:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [519:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [519:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [519:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[519:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [519:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1599 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1599 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1581 = _T_1628 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1581 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1581 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1581 ? _d_sizes_clr_T_11[519:0] : 520'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [519:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [519:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_195 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node _io_out_T = shl(io.in, 0)
connect io.out, _io_out_T
node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22)
node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0))
node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RecFNToRecFN_195( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_197 :
input clock : Clock
input reset : Reset
output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}}
regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff)
reg value_reg : { symbol : UInt<10>}, clock
connect io.output_prev.key, key_reg
connect io.output_prev.value, value_reg
connect io.output_nxt.key, key_reg
connect io.output_nxt.value, value_reg
connect io.cur_output_keyval.key, key_reg
connect io.cur_output_keyval.value, value_reg
when io.cmd.valid :
node _T = eq(UInt<1>(0h0), io.cmd.bits)
when _T :
connect key_reg, io.input_nxt.key
connect value_reg, io.input_nxt.value
else :
node _T_1 = eq(UInt<1>(0h1), io.cmd.bits)
when _T_1 :
when io.insert_here :
connect key_reg, io.cur_input_keyval.key
connect value_reg, io.cur_input_keyval.value
else :
node _T_2 = geq(key_reg, io.cur_input_keyval.key)
when _T_2 :
connect key_reg, io.input_prev.key
connect value_reg, io.input_prev.value
else :
skip | module PriorityQueueStage_197( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PE_502 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_246
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<32>, clock
reg c2 : SInt<32>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node c1_sign = bits(io.in_d, 19, 19)
node c1_lo_lo_hi = cat(c1_sign, c1_sign)
node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign)
node c1_lo_hi_hi = cat(c1_sign, c1_sign)
node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign)
node c1_lo = cat(c1_lo_hi, c1_lo_lo)
node c1_hi_lo_hi = cat(c1_sign, c1_sign)
node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign)
node c1_hi_hi_hi = cat(c1_sign, c1_sign)
node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign)
node c1_hi = cat(c1_hi_hi, c1_hi_lo)
node _c1_T = cat(c1_hi, c1_lo)
node c1_lo_1 = asUInt(io.in_d)
node _c1_T_1 = cat(_c1_T, c1_lo_1)
wire _c1_WIRE : SInt<32>
node _c1_T_2 = asSInt(_c1_T_1)
connect _c1_WIRE, _c1_T_2
connect c1, _c1_WIRE
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node c2_sign = bits(io.in_d, 19, 19)
node c2_lo_lo_hi = cat(c2_sign, c2_sign)
node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign)
node c2_lo_hi_hi = cat(c2_sign, c2_sign)
node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign)
node c2_lo = cat(c2_lo_hi, c2_lo_lo)
node c2_hi_lo_hi = cat(c2_sign, c2_sign)
node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign)
node c2_hi_hi_hi = cat(c2_sign, c2_sign)
node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign)
node c2_hi = cat(c2_hi_hi, c2_hi_lo)
node _c2_T = cat(c2_hi, c2_lo)
node c2_lo_1 = asUInt(io.in_d)
node _c2_T_1 = cat(_c2_T, c2_lo_1)
wire _c2_WIRE : SInt<32>
node _c2_T_2 = asSInt(_c2_T_1)
connect _c2_WIRE, _c2_T_2
connect c2, _c2_WIRE
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h1), _T_4)
node _T_6 = or(UInt<1>(0h0), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_502( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_246 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s1k3z4c_3 :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeIn.e.bits.sink
invalidate nodeIn.e.valid
invalidate nodeIn.e.ready
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.c.bits.corrupt
invalidate nodeIn.c.bits.data
invalidate nodeIn.c.bits.address
invalidate nodeIn.c.bits.source
invalidate nodeIn.c.bits.size
invalidate nodeIn.c.bits.param
invalidate nodeIn.c.bits.opcode
invalidate nodeIn.c.valid
invalidate nodeIn.c.ready
invalidate nodeIn.b.bits.corrupt
invalidate nodeIn.b.bits.data
invalidate nodeIn.b.bits.mask
invalidate nodeIn.b.bits.address
invalidate nodeIn.b.bits.source
invalidate nodeIn.b.bits.size
invalidate nodeIn.b.bits.param
invalidate nodeIn.b.bits.opcode
invalidate nodeIn.b.valid
invalidate nodeIn.b.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_10
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink
connect monitor.io.in.e.valid, nodeIn.e.valid
connect monitor.io.in.e.ready, nodeIn.e.ready
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt
connect monitor.io.in.c.bits.data, nodeIn.c.bits.data
connect monitor.io.in.c.bits.address, nodeIn.c.bits.address
connect monitor.io.in.c.bits.source, nodeIn.c.bits.source
connect monitor.io.in.c.bits.size, nodeIn.c.bits.size
connect monitor.io.in.c.bits.param, nodeIn.c.bits.param
connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode
connect monitor.io.in.c.valid, nodeIn.c.valid
connect monitor.io.in.c.ready, nodeIn.c.ready
connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt
connect monitor.io.in.b.bits.data, nodeIn.b.bits.data
connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask
connect monitor.io.in.b.bits.address, nodeIn.b.bits.address
connect monitor.io.in.b.bits.source, nodeIn.b.bits.source
connect monitor.io.in.b.bits.size, nodeIn.b.bits.size
connect monitor.io.in.b.bits.param, nodeIn.b.bits.param
connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode
connect monitor.io.in.b.valid, nodeIn.b.valid
connect monitor.io.in.b.ready, nodeIn.b.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeOut.e.bits.sink
invalidate nodeOut.e.valid
invalidate nodeOut.e.ready
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.c.bits.corrupt
invalidate nodeOut.c.bits.data
invalidate nodeOut.c.bits.address
invalidate nodeOut.c.bits.source
invalidate nodeOut.c.bits.size
invalidate nodeOut.c.bits.param
invalidate nodeOut.c.bits.opcode
invalidate nodeOut.c.valid
invalidate nodeOut.c.ready
invalidate nodeOut.b.bits.corrupt
invalidate nodeOut.b.bits.data
invalidate nodeOut.b.bits.mask
invalidate nodeOut.b.bits.address
invalidate nodeOut.b.bits.source
invalidate nodeOut.b.bits.size
invalidate nodeOut.b.bits.param
invalidate nodeOut.b.bits.opcode
invalidate nodeOut.b.valid
invalidate nodeOut.b.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_a_q of Queue2_TLBundleA_a32d64s1k3z4c_3
connect nodeOut_a_q.clock, clock
connect nodeOut_a_q.reset, reset
connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid
connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt
connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data
connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask
connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address
connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source
connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size
connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param
connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode
connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready
connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits
connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid
connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready
inst nodeIn_d_q of Queue2_TLBundleD_a32d64s1k3z4c_3
connect nodeIn_d_q.clock, clock
connect nodeIn_d_q.reset, reset
connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid
connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt
connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data
connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied
connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink
connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source
connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size
connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param
connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode
connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready
connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits
connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid
connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready
inst nodeIn_b_q of Queue2_TLBundleB_a32d64s1k3z4c_3
connect nodeIn_b_q.clock, clock
connect nodeIn_b_q.reset, reset
connect nodeIn_b_q.io.enq.valid, nodeOut.b.valid
connect nodeIn_b_q.io.enq.bits.corrupt, nodeOut.b.bits.corrupt
connect nodeIn_b_q.io.enq.bits.data, nodeOut.b.bits.data
connect nodeIn_b_q.io.enq.bits.mask, nodeOut.b.bits.mask
connect nodeIn_b_q.io.enq.bits.address, nodeOut.b.bits.address
connect nodeIn_b_q.io.enq.bits.source, nodeOut.b.bits.source
connect nodeIn_b_q.io.enq.bits.size, nodeOut.b.bits.size
connect nodeIn_b_q.io.enq.bits.param, nodeOut.b.bits.param
connect nodeIn_b_q.io.enq.bits.opcode, nodeOut.b.bits.opcode
connect nodeOut.b.ready, nodeIn_b_q.io.enq.ready
connect nodeIn.b.bits, nodeIn_b_q.io.deq.bits
connect nodeIn.b.valid, nodeIn_b_q.io.deq.valid
connect nodeIn_b_q.io.deq.ready, nodeIn.b.ready
inst nodeOut_c_q of Queue2_TLBundleC_a32d64s1k3z4c_3
connect nodeOut_c_q.clock, clock
connect nodeOut_c_q.reset, reset
connect nodeOut_c_q.io.enq.valid, nodeIn.c.valid
connect nodeOut_c_q.io.enq.bits.corrupt, nodeIn.c.bits.corrupt
connect nodeOut_c_q.io.enq.bits.data, nodeIn.c.bits.data
connect nodeOut_c_q.io.enq.bits.address, nodeIn.c.bits.address
connect nodeOut_c_q.io.enq.bits.source, nodeIn.c.bits.source
connect nodeOut_c_q.io.enq.bits.size, nodeIn.c.bits.size
connect nodeOut_c_q.io.enq.bits.param, nodeIn.c.bits.param
connect nodeOut_c_q.io.enq.bits.opcode, nodeIn.c.bits.opcode
connect nodeIn.c.ready, nodeOut_c_q.io.enq.ready
connect nodeOut.c.bits, nodeOut_c_q.io.deq.bits
connect nodeOut.c.valid, nodeOut_c_q.io.deq.valid
connect nodeOut_c_q.io.deq.ready, nodeOut.c.ready
inst nodeOut_e_q of Queue2_TLBundleE_a32d64s1k3z4c_3
connect nodeOut_e_q.clock, clock
connect nodeOut_e_q.reset, reset
connect nodeOut_e_q.io.enq.valid, nodeIn.e.valid
connect nodeOut_e_q.io.enq.bits.sink, nodeIn.e.bits.sink
connect nodeIn.e.ready, nodeOut_e_q.io.enq.ready
connect nodeOut.e.bits, nodeOut_e_q.io.deq.bits
connect nodeOut.e.valid, nodeOut_e_q.io.deq.valid
connect nodeOut_e_q.io.deq.ready, nodeOut.e.ready | module TLBuffer_a32d64s1k3z4c_3( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input auto_out_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_e_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9]
wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9]
wire auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9]
wire [63:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9]
wire auto_in_c_bits_corrupt_0 = auto_in_c_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9]
wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9]
wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9]
wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9]
wire auto_out_b_bits_source_0 = auto_out_b_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9]
wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_out_e_ready_0 = auto_out_e_ready; // @[Buffer.scala:40:9]
wire auto_out_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeOut_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire [63:0] auto_out_b_bits_data = 64'h0; // @[Decoupled.scala:362:21]
wire [63:0] nodeOut_b_bits_data = 64'h0; // @[Decoupled.scala:362:21]
wire [7:0] auto_out_b_bits_mask = 8'hFF; // @[Decoupled.scala:362:21]
wire [7:0] nodeOut_b_bits_mask = 8'hFF; // @[Decoupled.scala:362:21]
wire [3:0] auto_out_b_bits_size = 4'h6; // @[Decoupled.scala:362:21]
wire [3:0] nodeOut_b_bits_size = 4'h6; // @[Decoupled.scala:362:21]
wire [2:0] auto_out_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire [2:0] nodeOut_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9]
wire nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_b_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_b_bits_size; // @[MixedNode.scala:551:17]
wire nodeIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_b_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_c_ready; // @[MixedNode.scala:551:17]
wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9]
wire nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_c_bits_corrupt = auto_in_c_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_e_ready; // @[MixedNode.scala:551:17]
wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_b_ready; // @[MixedNode.scala:542:17]
wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9]
wire nodeOut_b_bits_source = auto_out_b_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9]
wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeOut_e_ready = auto_out_e_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire auto_in_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_b_bits_size_0; // @[Buffer.scala:40:9]
wire auto_in_b_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_in_b_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_b_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_b_valid_0; // @[Buffer.scala:40:9]
wire auto_in_c_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_d_valid_0; // @[Buffer.scala:40:9]
wire auto_in_e_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_b_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9]
wire auto_out_c_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_c_valid_0; // @[Buffer.scala:40:9]
wire auto_out_d_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_out_e_valid_0; // @[Buffer.scala:40:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9]
assign auto_in_b_bits_opcode_0 = nodeIn_b_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9]
assign auto_in_b_bits_size_0 = nodeIn_b_bits_size; // @[Buffer.scala:40:9]
assign auto_in_b_bits_source_0 = nodeIn_b_bits_source; // @[Buffer.scala:40:9]
assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9]
assign auto_in_b_bits_mask_0 = nodeIn_b_bits_mask; // @[Buffer.scala:40:9]
assign auto_in_b_bits_data_0 = nodeIn_b_bits_data; // @[Buffer.scala:40:9]
assign auto_in_b_bits_corrupt_0 = nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_in_e_ready_0 = nodeIn_e_ready; // @[Buffer.scala:40:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9]
assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9]
assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9]
assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9]
assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9]
assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9]
assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9]
assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9]
assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9]
TLMonitor_10 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17]
.io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17]
.io_in_b_bits_opcode (nodeIn_b_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17]
.io_in_b_bits_size (nodeIn_b_bits_size), // @[MixedNode.scala:551:17]
.io_in_b_bits_source (nodeIn_b_bits_source), // @[MixedNode.scala:551:17]
.io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17]
.io_in_b_bits_mask (nodeIn_b_bits_mask), // @[MixedNode.scala:551:17]
.io_in_b_bits_data (nodeIn_b_bits_data), // @[MixedNode.scala:551:17]
.io_in_b_bits_corrupt (nodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17]
.io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17]
.io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17]
.io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17]
.io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17]
.io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17]
.io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17]
.io_in_c_bits_corrupt (nodeIn_c_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_e_ready (nodeIn_e_ready), // @[MixedNode.scala:551:17]
.io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17]
.io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a32d64s1k3z4c_3 nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a32d64s1k3z4c_3 nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17]
.io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleB_a32d64s1k3z4c_3 nodeIn_b_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_b_ready),
.io_enq_valid (nodeOut_b_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_b_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_b_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_address (nodeOut_b_bits_address), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_b_valid),
.io_deq_bits_opcode (nodeIn_b_bits_opcode),
.io_deq_bits_param (nodeIn_b_bits_param),
.io_deq_bits_size (nodeIn_b_bits_size),
.io_deq_bits_source (nodeIn_b_bits_source),
.io_deq_bits_address (nodeIn_b_bits_address),
.io_deq_bits_mask (nodeIn_b_bits_mask),
.io_deq_bits_data (nodeIn_b_bits_data),
.io_deq_bits_corrupt (nodeIn_b_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleC_a32d64s1k3z4c_3 nodeOut_c_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_c_ready),
.io_enq_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (nodeIn_c_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_c_valid),
.io_deq_bits_opcode (nodeOut_c_bits_opcode),
.io_deq_bits_param (nodeOut_c_bits_param),
.io_deq_bits_size (nodeOut_c_bits_size),
.io_deq_bits_source (nodeOut_c_bits_source),
.io_deq_bits_address (nodeOut_c_bits_address),
.io_deq_bits_data (nodeOut_c_bits_data),
.io_deq_bits_corrupt (nodeOut_c_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleE_a32d64s1k3z4c_3 nodeOut_e_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_e_ready),
.io_enq_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_e_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_e_valid),
.io_deq_bits_sink (nodeOut_e_bits_sink)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_opcode = auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_size = auto_in_b_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_source = auto_in_b_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_mask = auto_in_b_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_data = auto_in_b_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_corrupt = auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_in_e_ready = auto_in_e_ready_0; // @[Buffer.scala:40:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9]
assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9]
assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9]
assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s4k3z4u :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_12
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_a_q of Queue2_TLBundleA_a32d64s4k3z4u
connect nodeOut_a_q.clock, clock
connect nodeOut_a_q.reset, reset
connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid
connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt
connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data
connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask
connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address
connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source
connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size
connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param
connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode
connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready
connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits
connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid
connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready
inst nodeIn_d_q of Queue2_TLBundleD_a32d64s4k3z4u
connect nodeIn_d_q.clock, clock
connect nodeIn_d_q.reset, reset
connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid
connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt
connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data
connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied
connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink
connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source
connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size
connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param
connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode
connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready
connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits
connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid
connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<4>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<4>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_4.bits.sink, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<4>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<4>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_10.bits.sink, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0) | module TLBuffer_a32d64s4k3z4u( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [3:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_d_ready_0; // @[Buffer.scala:40:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
TLMonitor_12 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a32d64s4k3z4u nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a32d64s4k3z4u nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17]
.io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Queue1_RegMapperInput_i9_m8 :
input clock : Clock
input reset : Reset
output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}}, count : UInt<1>}
cmem ram : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}} [1]
wire enq_ptr_value : UInt
connect enq_ptr_value, UInt<1>(0h0)
wire deq_ptr_value : UInt
connect deq_ptr_value, UInt<1>(0h0)
regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0)
node ptr_match = eq(enq_ptr_value, deq_ptr_value)
node _empty_T = eq(maybe_full, UInt<1>(0h0))
node empty = and(ptr_match, _empty_T)
node full = and(ptr_match, maybe_full)
node _do_enq_T = and(io.enq.ready, io.enq.valid)
wire do_enq : UInt<1>
connect do_enq, _do_enq_T
node _do_deq_T = and(io.deq.ready, io.deq.valid)
wire do_deq : UInt<1>
connect do_deq, _do_deq_T
when do_enq :
wire _WIRE : UInt
connect _WIRE, UInt<1>(0h0)
infer mport MPORT = ram[_WIRE], clock
connect MPORT.extra, io.enq.bits.extra
connect MPORT.mask, io.enq.bits.mask
connect MPORT.data, io.enq.bits.data
connect MPORT.index, io.enq.bits.index
connect MPORT.read, io.enq.bits.read
when do_deq :
skip
node _T = neq(do_enq, do_deq)
when _T :
connect maybe_full, do_enq
when UInt<1>(0h0) :
connect enq_ptr_value, UInt<1>(0h0)
connect deq_ptr_value, UInt<1>(0h0)
connect maybe_full, UInt<1>(0h0)
node _io_deq_valid_T = eq(empty, UInt<1>(0h0))
connect io.deq.valid, _io_deq_valid_T
node _io_enq_ready_T = eq(full, UInt<1>(0h0))
connect io.enq.ready, _io_enq_ready_T
wire _io_deq_bits_WIRE : UInt
connect _io_deq_bits_WIRE, UInt<1>(0h0)
infer mport io_deq_bits_MPORT = ram[_io_deq_bits_WIRE], clock
connect io.deq.bits, io_deq_bits_MPORT
node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value)
node ptr_diff = tail(_ptr_diff_T, 1)
node _io_count_T = and(maybe_full, ptr_match)
node _io_count_T_1 = mux(_io_count_T, UInt<1>(0h1), UInt<1>(0h0))
node _io_count_T_2 = or(_io_count_T_1, ptr_diff)
connect io.count, _io_count_T_2 | module Queue1_RegMapperInput_i9_m8( // @[RegMapper.scala:71:32]
input clock, // @[RegMapper.scala:71:32]
input reset, // @[RegMapper.scala:71:32]
output io_enq_ready, // @[Decoupled.scala:255:14]
input io_enq_valid, // @[Decoupled.scala:255:14]
input io_enq_bits_read, // @[Decoupled.scala:255:14]
input [8:0] io_enq_bits_index, // @[Decoupled.scala:255:14]
input [63:0] io_enq_bits_data, // @[Decoupled.scala:255:14]
input [7:0] io_enq_bits_mask, // @[Decoupled.scala:255:14]
input [10:0] io_enq_bits_extra_tlrr_extra_source, // @[Decoupled.scala:255:14]
input [1:0] io_enq_bits_extra_tlrr_extra_size, // @[Decoupled.scala:255:14]
input io_deq_ready, // @[Decoupled.scala:255:14]
output io_deq_valid, // @[Decoupled.scala:255:14]
output io_deq_bits_read, // @[Decoupled.scala:255:14]
output [8:0] io_deq_bits_index, // @[Decoupled.scala:255:14]
output [63:0] io_deq_bits_data, // @[Decoupled.scala:255:14]
output [7:0] io_deq_bits_mask, // @[Decoupled.scala:255:14]
output [10:0] io_deq_bits_extra_tlrr_extra_source, // @[Decoupled.scala:255:14]
output [1:0] io_deq_bits_extra_tlrr_extra_size // @[Decoupled.scala:255:14]
);
wire io_enq_valid_0 = io_enq_valid; // @[RegMapper.scala:71:32]
wire io_enq_bits_read_0 = io_enq_bits_read; // @[RegMapper.scala:71:32]
wire [8:0] io_enq_bits_index_0 = io_enq_bits_index; // @[RegMapper.scala:71:32]
wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[RegMapper.scala:71:32]
wire [7:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[RegMapper.scala:71:32]
wire [10:0] io_enq_bits_extra_tlrr_extra_source_0 = io_enq_bits_extra_tlrr_extra_source; // @[RegMapper.scala:71:32]
wire [1:0] io_enq_bits_extra_tlrr_extra_size_0 = io_enq_bits_extra_tlrr_extra_size; // @[RegMapper.scala:71:32]
wire io_deq_ready_0 = io_deq_ready; // @[RegMapper.scala:71:32]
wire ptr_match = 1'h1; // @[Decoupled.scala:260:33]
wire [1:0] _ptr_diff_T = 2'h0; // @[Decoupled.scala:309:32]
wire enq_ptr_value = 1'h0; // @[Counter.scala:61:73]
wire deq_ptr_value = 1'h0; // @[Counter.scala:61:73]
wire _io_enq_ready_T; // @[Decoupled.scala:286:19]
wire _io_deq_bits_WIRE = 1'h0; // @[Decoupled.scala:293:23]
wire ptr_diff = 1'h0; // @[Decoupled.scala:309:32]
wire _io_deq_valid_T; // @[Decoupled.scala:285:19]
wire _io_count_T_2; // @[Decoupled.scala:312:62]
wire io_enq_ready_0; // @[RegMapper.scala:71:32]
wire [10:0] io_deq_bits_extra_tlrr_extra_source_0; // @[RegMapper.scala:71:32]
wire [1:0] io_deq_bits_extra_tlrr_extra_size_0; // @[RegMapper.scala:71:32]
wire io_deq_bits_read_0; // @[RegMapper.scala:71:32]
wire [8:0] io_deq_bits_index_0; // @[RegMapper.scala:71:32]
wire [63:0] io_deq_bits_data_0; // @[RegMapper.scala:71:32]
wire [7:0] io_deq_bits_mask_0; // @[RegMapper.scala:71:32]
wire io_deq_valid_0; // @[RegMapper.scala:71:32]
wire io_count; // @[RegMapper.scala:71:32]
reg [94:0] ram; // @[Decoupled.scala:256:91]
assign io_deq_bits_read_0 = ram[0]; // @[Decoupled.scala:256:91]
assign io_deq_bits_index_0 = ram[9:1]; // @[Decoupled.scala:256:91]
assign io_deq_bits_data_0 = ram[73:10]; // @[Decoupled.scala:256:91]
assign io_deq_bits_mask_0 = ram[81:74]; // @[Decoupled.scala:256:91]
assign io_deq_bits_extra_tlrr_extra_source_0 = ram[92:82]; // @[Decoupled.scala:256:91]
assign io_deq_bits_extra_tlrr_extra_size_0 = ram[94:93]; // @[Decoupled.scala:256:91]
reg maybe_full; // @[Decoupled.scala:259:27]
wire full = maybe_full; // @[Decoupled.scala:259:27, :262:24]
wire _io_count_T = maybe_full; // @[Decoupled.scala:259:27, :312:32]
wire _empty_T = ~maybe_full; // @[Decoupled.scala:259:27, :261:28]
wire empty = _empty_T; // @[Decoupled.scala:261:{25,28}]
wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35]
wire do_enq = _do_enq_T; // @[Decoupled.scala:51:35, :263:27]
wire _do_deq_T = io_deq_ready_0 & io_deq_valid_0; // @[Decoupled.scala:51:35]
wire do_deq = _do_deq_T; // @[Decoupled.scala:51:35, :264:27]
assign _io_deq_valid_T = ~empty; // @[Decoupled.scala:261:25, :285:19]
assign io_deq_valid_0 = _io_deq_valid_T; // @[Decoupled.scala:285:19]
assign _io_enq_ready_T = ~full; // @[Decoupled.scala:262:24, :286:19]
assign io_enq_ready_0 = _io_enq_ready_T; // @[Decoupled.scala:286:19]
wire _io_count_T_1 = _io_count_T; // @[Decoupled.scala:312:{20,32}]
assign _io_count_T_2 = _io_count_T_1; // @[Decoupled.scala:312:{20,62}]
assign io_count = _io_count_T_2; // @[Decoupled.scala:312:62]
always @(posedge clock) begin // @[RegMapper.scala:71:32]
if (do_enq) // @[Decoupled.scala:263:27]
ram <= {io_enq_bits_extra_tlrr_extra_size_0, io_enq_bits_extra_tlrr_extra_source_0, io_enq_bits_mask_0, io_enq_bits_data_0, io_enq_bits_index_0, io_enq_bits_read_0}; // @[Decoupled.scala:256:91]
if (reset) // @[RegMapper.scala:71:32]
maybe_full <= 1'h0; // @[Decoupled.scala:259:27]
else if (~(do_enq == do_deq)) // @[Decoupled.scala:259:27, :263:27, :264:27, :276:{15,27}, :277:16]
maybe_full <= do_enq; // @[Decoupled.scala:259:27, :263:27]
always @(posedge)
assign io_enq_ready = io_enq_ready_0; // @[RegMapper.scala:71:32]
assign io_deq_valid = io_deq_valid_0; // @[RegMapper.scala:71:32]
assign io_deq_bits_read = io_deq_bits_read_0; // @[RegMapper.scala:71:32]
assign io_deq_bits_index = io_deq_bits_index_0; // @[RegMapper.scala:71:32]
assign io_deq_bits_data = io_deq_bits_data_0; // @[RegMapper.scala:71:32]
assign io_deq_bits_mask = io_deq_bits_mask_0; // @[RegMapper.scala:71:32]
assign io_deq_bits_extra_tlrr_extra_source = io_deq_bits_extra_tlrr_extra_source_0; // @[RegMapper.scala:71:32]
assign io_deq_bits_extra_tlrr_extra_size = io_deq_bits_extra_tlrr_extra_size_0; // @[RegMapper.scala:71:32]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PMAChecker_3 :
input clock : Clock
input reset : Reset
output io : { flip paddr : UInt, resp : { cacheable : UInt<1>, r : UInt<1>, w : UInt<1>, pp : UInt<1>, al : UInt<1>, aa : UInt<1>, x : UInt<1>, eff : UInt<1>}}
node _legal_address_T = xor(io.paddr, UInt<1>(0h0))
node _legal_address_T_1 = cvt(_legal_address_T)
node _legal_address_T_2 = and(_legal_address_T_1, asSInt(UInt<13>(0h1000)))
node _legal_address_T_3 = asSInt(_legal_address_T_2)
node _legal_address_T_4 = eq(_legal_address_T_3, asSInt(UInt<1>(0h0)))
node _legal_address_T_5 = xor(io.paddr, UInt<13>(0h1000))
node _legal_address_T_6 = cvt(_legal_address_T_5)
node _legal_address_T_7 = and(_legal_address_T_6, asSInt(UInt<13>(0h1000)))
node _legal_address_T_8 = asSInt(_legal_address_T_7)
node _legal_address_T_9 = eq(_legal_address_T_8, asSInt(UInt<1>(0h0)))
node _legal_address_T_10 = xor(io.paddr, UInt<14>(0h3000))
node _legal_address_T_11 = cvt(_legal_address_T_10)
node _legal_address_T_12 = and(_legal_address_T_11, asSInt(UInt<13>(0h1000)))
node _legal_address_T_13 = asSInt(_legal_address_T_12)
node _legal_address_T_14 = eq(_legal_address_T_13, asSInt(UInt<1>(0h0)))
node _legal_address_T_15 = xor(io.paddr, UInt<17>(0h10000))
node _legal_address_T_16 = cvt(_legal_address_T_15)
node _legal_address_T_17 = and(_legal_address_T_16, asSInt(UInt<17>(0h10000)))
node _legal_address_T_18 = asSInt(_legal_address_T_17)
node _legal_address_T_19 = eq(_legal_address_T_18, asSInt(UInt<1>(0h0)))
node _legal_address_T_20 = xor(io.paddr, UInt<21>(0h100000))
node _legal_address_T_21 = cvt(_legal_address_T_20)
node _legal_address_T_22 = and(_legal_address_T_21, asSInt(UInt<13>(0h1000)))
node _legal_address_T_23 = asSInt(_legal_address_T_22)
node _legal_address_T_24 = eq(_legal_address_T_23, asSInt(UInt<1>(0h0)))
node _legal_address_T_25 = xor(io.paddr, UInt<21>(0h110000))
node _legal_address_T_26 = cvt(_legal_address_T_25)
node _legal_address_T_27 = and(_legal_address_T_26, asSInt(UInt<13>(0h1000)))
node _legal_address_T_28 = asSInt(_legal_address_T_27)
node _legal_address_T_29 = eq(_legal_address_T_28, asSInt(UInt<1>(0h0)))
node _legal_address_T_30 = xor(io.paddr, UInt<26>(0h2000000))
node _legal_address_T_31 = cvt(_legal_address_T_30)
node _legal_address_T_32 = and(_legal_address_T_31, asSInt(UInt<17>(0h10000)))
node _legal_address_T_33 = asSInt(_legal_address_T_32)
node _legal_address_T_34 = eq(_legal_address_T_33, asSInt(UInt<1>(0h0)))
node _legal_address_T_35 = xor(io.paddr, UInt<26>(0h2010000))
node _legal_address_T_36 = cvt(_legal_address_T_35)
node _legal_address_T_37 = and(_legal_address_T_36, asSInt(UInt<13>(0h1000)))
node _legal_address_T_38 = asSInt(_legal_address_T_37)
node _legal_address_T_39 = eq(_legal_address_T_38, asSInt(UInt<1>(0h0)))
node _legal_address_T_40 = xor(io.paddr, UInt<28>(0h8000000))
node _legal_address_T_41 = cvt(_legal_address_T_40)
node _legal_address_T_42 = and(_legal_address_T_41, asSInt(UInt<17>(0h10000)))
node _legal_address_T_43 = asSInt(_legal_address_T_42)
node _legal_address_T_44 = eq(_legal_address_T_43, asSInt(UInt<1>(0h0)))
node _legal_address_T_45 = xor(io.paddr, UInt<28>(0hc000000))
node _legal_address_T_46 = cvt(_legal_address_T_45)
node _legal_address_T_47 = and(_legal_address_T_46, asSInt(UInt<27>(0h4000000)))
node _legal_address_T_48 = asSInt(_legal_address_T_47)
node _legal_address_T_49 = eq(_legal_address_T_48, asSInt(UInt<1>(0h0)))
node _legal_address_T_50 = xor(io.paddr, UInt<29>(0h10020000))
node _legal_address_T_51 = cvt(_legal_address_T_50)
node _legal_address_T_52 = and(_legal_address_T_51, asSInt(UInt<13>(0h1000)))
node _legal_address_T_53 = asSInt(_legal_address_T_52)
node _legal_address_T_54 = eq(_legal_address_T_53, asSInt(UInt<1>(0h0)))
node _legal_address_T_55 = xor(io.paddr, UInt<32>(0h80000000))
node _legal_address_T_56 = cvt(_legal_address_T_55)
node _legal_address_T_57 = and(_legal_address_T_56, asSInt(UInt<29>(0h10000000)))
node _legal_address_T_58 = asSInt(_legal_address_T_57)
node _legal_address_T_59 = eq(_legal_address_T_58, asSInt(UInt<1>(0h0)))
wire _legal_address_WIRE : UInt<1>[12]
connect _legal_address_WIRE[0], _legal_address_T_4
connect _legal_address_WIRE[1], _legal_address_T_9
connect _legal_address_WIRE[2], _legal_address_T_14
connect _legal_address_WIRE[3], _legal_address_T_19
connect _legal_address_WIRE[4], _legal_address_T_24
connect _legal_address_WIRE[5], _legal_address_T_29
connect _legal_address_WIRE[6], _legal_address_T_34
connect _legal_address_WIRE[7], _legal_address_T_39
connect _legal_address_WIRE[8], _legal_address_T_44
connect _legal_address_WIRE[9], _legal_address_T_49
connect _legal_address_WIRE[10], _legal_address_T_54
connect _legal_address_WIRE[11], _legal_address_T_59
node _legal_address_T_60 = or(_legal_address_WIRE[0], _legal_address_WIRE[1])
node _legal_address_T_61 = or(_legal_address_T_60, _legal_address_WIRE[2])
node _legal_address_T_62 = or(_legal_address_T_61, _legal_address_WIRE[3])
node _legal_address_T_63 = or(_legal_address_T_62, _legal_address_WIRE[4])
node _legal_address_T_64 = or(_legal_address_T_63, _legal_address_WIRE[5])
node _legal_address_T_65 = or(_legal_address_T_64, _legal_address_WIRE[6])
node _legal_address_T_66 = or(_legal_address_T_65, _legal_address_WIRE[7])
node _legal_address_T_67 = or(_legal_address_T_66, _legal_address_WIRE[8])
node _legal_address_T_68 = or(_legal_address_T_67, _legal_address_WIRE[9])
node _legal_address_T_69 = or(_legal_address_T_68, _legal_address_WIRE[10])
node legal_address = or(_legal_address_T_69, _legal_address_WIRE[11])
node _io_resp_cacheable_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_cacheable_T_1 = cvt(_io_resp_cacheable_T)
node _io_resp_cacheable_T_2 = and(_io_resp_cacheable_T_1, asSInt(UInt<33>(0h8c000000)))
node _io_resp_cacheable_T_3 = asSInt(_io_resp_cacheable_T_2)
node _io_resp_cacheable_T_4 = eq(_io_resp_cacheable_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_5 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_cacheable_T_6 = cvt(_io_resp_cacheable_T_5)
node _io_resp_cacheable_T_7 = and(_io_resp_cacheable_T_6, asSInt(UInt<33>(0h8c011000)))
node _io_resp_cacheable_T_8 = asSInt(_io_resp_cacheable_T_7)
node _io_resp_cacheable_T_9 = eq(_io_resp_cacheable_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_10 = xor(io.paddr, UInt<28>(0hc000000))
node _io_resp_cacheable_T_11 = cvt(_io_resp_cacheable_T_10)
node _io_resp_cacheable_T_12 = and(_io_resp_cacheable_T_11, asSInt(UInt<33>(0h8c000000)))
node _io_resp_cacheable_T_13 = asSInt(_io_resp_cacheable_T_12)
node _io_resp_cacheable_T_14 = eq(_io_resp_cacheable_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_15 = or(_io_resp_cacheable_T_4, _io_resp_cacheable_T_9)
node _io_resp_cacheable_T_16 = or(_io_resp_cacheable_T_15, _io_resp_cacheable_T_14)
node _io_resp_cacheable_T_17 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_cacheable_T_18 = cvt(_io_resp_cacheable_T_17)
node _io_resp_cacheable_T_19 = and(_io_resp_cacheable_T_18, asSInt(UInt<33>(0h8c010000)))
node _io_resp_cacheable_T_20 = asSInt(_io_resp_cacheable_T_19)
node _io_resp_cacheable_T_21 = eq(_io_resp_cacheable_T_20, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_22 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_cacheable_T_23 = cvt(_io_resp_cacheable_T_22)
node _io_resp_cacheable_T_24 = and(_io_resp_cacheable_T_23, asSInt(UInt<33>(0h80000000)))
node _io_resp_cacheable_T_25 = asSInt(_io_resp_cacheable_T_24)
node _io_resp_cacheable_T_26 = eq(_io_resp_cacheable_T_25, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_27 = or(_io_resp_cacheable_T_21, _io_resp_cacheable_T_26)
node _io_resp_cacheable_T_28 = mux(_io_resp_cacheable_T_16, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_cacheable_T_29 = mux(_io_resp_cacheable_T_27, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_cacheable_T_30 = or(_io_resp_cacheable_T_28, _io_resp_cacheable_T_29)
wire _io_resp_cacheable_WIRE : UInt<1>
connect _io_resp_cacheable_WIRE, _io_resp_cacheable_T_30
node _io_resp_cacheable_T_31 = and(legal_address, _io_resp_cacheable_WIRE)
connect io.resp.cacheable, _io_resp_cacheable_T_31
node _io_resp_r_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_r_T_1 = cvt(_io_resp_r_T)
node _io_resp_r_T_2 = and(_io_resp_r_T_1, asSInt(UInt<1>(0h0)))
node _io_resp_r_T_3 = asSInt(_io_resp_r_T_2)
node _io_resp_r_T_4 = eq(_io_resp_r_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_r_T_5 = and(legal_address, UInt<1>(0h1))
connect io.resp.r, _io_resp_r_T_5
node _io_resp_w_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_w_T_1 = cvt(_io_resp_w_T)
node _io_resp_w_T_2 = and(_io_resp_w_T_1, asSInt(UInt<33>(0h98110000)))
node _io_resp_w_T_3 = asSInt(_io_resp_w_T_2)
node _io_resp_w_T_4 = eq(_io_resp_w_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_5 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_w_T_6 = cvt(_io_resp_w_T_5)
node _io_resp_w_T_7 = and(_io_resp_w_T_6, asSInt(UInt<33>(0h9a101000)))
node _io_resp_w_T_8 = asSInt(_io_resp_w_T_7)
node _io_resp_w_T_9 = eq(_io_resp_w_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_10 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_w_T_11 = cvt(_io_resp_w_T_10)
node _io_resp_w_T_12 = and(_io_resp_w_T_11, asSInt(UInt<33>(0h9a111000)))
node _io_resp_w_T_13 = asSInt(_io_resp_w_T_12)
node _io_resp_w_T_14 = eq(_io_resp_w_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_15 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_w_T_16 = cvt(_io_resp_w_T_15)
node _io_resp_w_T_17 = and(_io_resp_w_T_16, asSInt(UInt<33>(0h98000000)))
node _io_resp_w_T_18 = asSInt(_io_resp_w_T_17)
node _io_resp_w_T_19 = eq(_io_resp_w_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_20 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_w_T_21 = cvt(_io_resp_w_T_20)
node _io_resp_w_T_22 = and(_io_resp_w_T_21, asSInt(UInt<33>(0h9a110000)))
node _io_resp_w_T_23 = asSInt(_io_resp_w_T_22)
node _io_resp_w_T_24 = eq(_io_resp_w_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_25 = xor(io.paddr, UInt<29>(0h10000000))
node _io_resp_w_T_26 = cvt(_io_resp_w_T_25)
node _io_resp_w_T_27 = and(_io_resp_w_T_26, asSInt(UInt<33>(0h9a111000)))
node _io_resp_w_T_28 = asSInt(_io_resp_w_T_27)
node _io_resp_w_T_29 = eq(_io_resp_w_T_28, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_30 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_w_T_31 = cvt(_io_resp_w_T_30)
node _io_resp_w_T_32 = and(_io_resp_w_T_31, asSInt(UInt<33>(0h90000000)))
node _io_resp_w_T_33 = asSInt(_io_resp_w_T_32)
node _io_resp_w_T_34 = eq(_io_resp_w_T_33, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_35 = or(_io_resp_w_T_4, _io_resp_w_T_9)
node _io_resp_w_T_36 = or(_io_resp_w_T_35, _io_resp_w_T_14)
node _io_resp_w_T_37 = or(_io_resp_w_T_36, _io_resp_w_T_19)
node _io_resp_w_T_38 = or(_io_resp_w_T_37, _io_resp_w_T_24)
node _io_resp_w_T_39 = or(_io_resp_w_T_38, _io_resp_w_T_29)
node _io_resp_w_T_40 = or(_io_resp_w_T_39, _io_resp_w_T_34)
node _io_resp_w_T_41 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_w_T_42 = cvt(_io_resp_w_T_41)
node _io_resp_w_T_43 = and(_io_resp_w_T_42, asSInt(UInt<33>(0h9a110000)))
node _io_resp_w_T_44 = asSInt(_io_resp_w_T_43)
node _io_resp_w_T_45 = eq(_io_resp_w_T_44, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_46 = mux(_io_resp_w_T_40, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_w_T_47 = mux(_io_resp_w_T_45, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_w_T_48 = or(_io_resp_w_T_46, _io_resp_w_T_47)
wire _io_resp_w_WIRE : UInt<1>
connect _io_resp_w_WIRE, _io_resp_w_T_48
node _io_resp_w_T_49 = and(legal_address, _io_resp_w_WIRE)
connect io.resp.w, _io_resp_w_T_49
node _io_resp_pp_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_pp_T_1 = cvt(_io_resp_pp_T)
node _io_resp_pp_T_2 = and(_io_resp_pp_T_1, asSInt(UInt<33>(0h98110000)))
node _io_resp_pp_T_3 = asSInt(_io_resp_pp_T_2)
node _io_resp_pp_T_4 = eq(_io_resp_pp_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_5 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_pp_T_6 = cvt(_io_resp_pp_T_5)
node _io_resp_pp_T_7 = and(_io_resp_pp_T_6, asSInt(UInt<33>(0h9a101000)))
node _io_resp_pp_T_8 = asSInt(_io_resp_pp_T_7)
node _io_resp_pp_T_9 = eq(_io_resp_pp_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_10 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_pp_T_11 = cvt(_io_resp_pp_T_10)
node _io_resp_pp_T_12 = and(_io_resp_pp_T_11, asSInt(UInt<33>(0h9a111000)))
node _io_resp_pp_T_13 = asSInt(_io_resp_pp_T_12)
node _io_resp_pp_T_14 = eq(_io_resp_pp_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_15 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_pp_T_16 = cvt(_io_resp_pp_T_15)
node _io_resp_pp_T_17 = and(_io_resp_pp_T_16, asSInt(UInt<33>(0h98000000)))
node _io_resp_pp_T_18 = asSInt(_io_resp_pp_T_17)
node _io_resp_pp_T_19 = eq(_io_resp_pp_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_20 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_pp_T_21 = cvt(_io_resp_pp_T_20)
node _io_resp_pp_T_22 = and(_io_resp_pp_T_21, asSInt(UInt<33>(0h9a110000)))
node _io_resp_pp_T_23 = asSInt(_io_resp_pp_T_22)
node _io_resp_pp_T_24 = eq(_io_resp_pp_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_25 = xor(io.paddr, UInt<29>(0h10000000))
node _io_resp_pp_T_26 = cvt(_io_resp_pp_T_25)
node _io_resp_pp_T_27 = and(_io_resp_pp_T_26, asSInt(UInt<33>(0h9a111000)))
node _io_resp_pp_T_28 = asSInt(_io_resp_pp_T_27)
node _io_resp_pp_T_29 = eq(_io_resp_pp_T_28, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_30 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_pp_T_31 = cvt(_io_resp_pp_T_30)
node _io_resp_pp_T_32 = and(_io_resp_pp_T_31, asSInt(UInt<33>(0h90000000)))
node _io_resp_pp_T_33 = asSInt(_io_resp_pp_T_32)
node _io_resp_pp_T_34 = eq(_io_resp_pp_T_33, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_35 = or(_io_resp_pp_T_4, _io_resp_pp_T_9)
node _io_resp_pp_T_36 = or(_io_resp_pp_T_35, _io_resp_pp_T_14)
node _io_resp_pp_T_37 = or(_io_resp_pp_T_36, _io_resp_pp_T_19)
node _io_resp_pp_T_38 = or(_io_resp_pp_T_37, _io_resp_pp_T_24)
node _io_resp_pp_T_39 = or(_io_resp_pp_T_38, _io_resp_pp_T_29)
node _io_resp_pp_T_40 = or(_io_resp_pp_T_39, _io_resp_pp_T_34)
node _io_resp_pp_T_41 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_pp_T_42 = cvt(_io_resp_pp_T_41)
node _io_resp_pp_T_43 = and(_io_resp_pp_T_42, asSInt(UInt<33>(0h9a110000)))
node _io_resp_pp_T_44 = asSInt(_io_resp_pp_T_43)
node _io_resp_pp_T_45 = eq(_io_resp_pp_T_44, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_46 = mux(_io_resp_pp_T_40, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_pp_T_47 = mux(_io_resp_pp_T_45, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_pp_T_48 = or(_io_resp_pp_T_46, _io_resp_pp_T_47)
wire _io_resp_pp_WIRE : UInt<1>
connect _io_resp_pp_WIRE, _io_resp_pp_T_48
node _io_resp_pp_T_49 = and(legal_address, _io_resp_pp_WIRE)
connect io.resp.pp, _io_resp_pp_T_49
node _io_resp_al_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_al_T_1 = cvt(_io_resp_al_T)
node _io_resp_al_T_2 = and(_io_resp_al_T_1, asSInt(UInt<33>(0h98110000)))
node _io_resp_al_T_3 = asSInt(_io_resp_al_T_2)
node _io_resp_al_T_4 = eq(_io_resp_al_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_5 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_al_T_6 = cvt(_io_resp_al_T_5)
node _io_resp_al_T_7 = and(_io_resp_al_T_6, asSInt(UInt<33>(0h9a101000)))
node _io_resp_al_T_8 = asSInt(_io_resp_al_T_7)
node _io_resp_al_T_9 = eq(_io_resp_al_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_10 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_al_T_11 = cvt(_io_resp_al_T_10)
node _io_resp_al_T_12 = and(_io_resp_al_T_11, asSInt(UInt<33>(0h9a111000)))
node _io_resp_al_T_13 = asSInt(_io_resp_al_T_12)
node _io_resp_al_T_14 = eq(_io_resp_al_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_15 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_al_T_16 = cvt(_io_resp_al_T_15)
node _io_resp_al_T_17 = and(_io_resp_al_T_16, asSInt(UInt<33>(0h98000000)))
node _io_resp_al_T_18 = asSInt(_io_resp_al_T_17)
node _io_resp_al_T_19 = eq(_io_resp_al_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_20 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_al_T_21 = cvt(_io_resp_al_T_20)
node _io_resp_al_T_22 = and(_io_resp_al_T_21, asSInt(UInt<33>(0h9a110000)))
node _io_resp_al_T_23 = asSInt(_io_resp_al_T_22)
node _io_resp_al_T_24 = eq(_io_resp_al_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_25 = xor(io.paddr, UInt<29>(0h10000000))
node _io_resp_al_T_26 = cvt(_io_resp_al_T_25)
node _io_resp_al_T_27 = and(_io_resp_al_T_26, asSInt(UInt<33>(0h9a111000)))
node _io_resp_al_T_28 = asSInt(_io_resp_al_T_27)
node _io_resp_al_T_29 = eq(_io_resp_al_T_28, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_30 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_al_T_31 = cvt(_io_resp_al_T_30)
node _io_resp_al_T_32 = and(_io_resp_al_T_31, asSInt(UInt<33>(0h90000000)))
node _io_resp_al_T_33 = asSInt(_io_resp_al_T_32)
node _io_resp_al_T_34 = eq(_io_resp_al_T_33, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_35 = or(_io_resp_al_T_4, _io_resp_al_T_9)
node _io_resp_al_T_36 = or(_io_resp_al_T_35, _io_resp_al_T_14)
node _io_resp_al_T_37 = or(_io_resp_al_T_36, _io_resp_al_T_19)
node _io_resp_al_T_38 = or(_io_resp_al_T_37, _io_resp_al_T_24)
node _io_resp_al_T_39 = or(_io_resp_al_T_38, _io_resp_al_T_29)
node _io_resp_al_T_40 = or(_io_resp_al_T_39, _io_resp_al_T_34)
node _io_resp_al_T_41 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_al_T_42 = cvt(_io_resp_al_T_41)
node _io_resp_al_T_43 = and(_io_resp_al_T_42, asSInt(UInt<33>(0h9a110000)))
node _io_resp_al_T_44 = asSInt(_io_resp_al_T_43)
node _io_resp_al_T_45 = eq(_io_resp_al_T_44, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_46 = mux(_io_resp_al_T_40, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_al_T_47 = mux(_io_resp_al_T_45, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_al_T_48 = or(_io_resp_al_T_46, _io_resp_al_T_47)
wire _io_resp_al_WIRE : UInt<1>
connect _io_resp_al_WIRE, _io_resp_al_T_48
node _io_resp_al_T_49 = and(legal_address, _io_resp_al_WIRE)
connect io.resp.al, _io_resp_al_T_49
node _io_resp_aa_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_aa_T_1 = cvt(_io_resp_aa_T)
node _io_resp_aa_T_2 = and(_io_resp_aa_T_1, asSInt(UInt<33>(0h98110000)))
node _io_resp_aa_T_3 = asSInt(_io_resp_aa_T_2)
node _io_resp_aa_T_4 = eq(_io_resp_aa_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_5 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_aa_T_6 = cvt(_io_resp_aa_T_5)
node _io_resp_aa_T_7 = and(_io_resp_aa_T_6, asSInt(UInt<33>(0h9a101000)))
node _io_resp_aa_T_8 = asSInt(_io_resp_aa_T_7)
node _io_resp_aa_T_9 = eq(_io_resp_aa_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_10 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_aa_T_11 = cvt(_io_resp_aa_T_10)
node _io_resp_aa_T_12 = and(_io_resp_aa_T_11, asSInt(UInt<33>(0h9a111000)))
node _io_resp_aa_T_13 = asSInt(_io_resp_aa_T_12)
node _io_resp_aa_T_14 = eq(_io_resp_aa_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_15 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_aa_T_16 = cvt(_io_resp_aa_T_15)
node _io_resp_aa_T_17 = and(_io_resp_aa_T_16, asSInt(UInt<33>(0h98000000)))
node _io_resp_aa_T_18 = asSInt(_io_resp_aa_T_17)
node _io_resp_aa_T_19 = eq(_io_resp_aa_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_20 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_aa_T_21 = cvt(_io_resp_aa_T_20)
node _io_resp_aa_T_22 = and(_io_resp_aa_T_21, asSInt(UInt<33>(0h9a110000)))
node _io_resp_aa_T_23 = asSInt(_io_resp_aa_T_22)
node _io_resp_aa_T_24 = eq(_io_resp_aa_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_25 = xor(io.paddr, UInt<29>(0h10000000))
node _io_resp_aa_T_26 = cvt(_io_resp_aa_T_25)
node _io_resp_aa_T_27 = and(_io_resp_aa_T_26, asSInt(UInt<33>(0h9a111000)))
node _io_resp_aa_T_28 = asSInt(_io_resp_aa_T_27)
node _io_resp_aa_T_29 = eq(_io_resp_aa_T_28, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_30 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_aa_T_31 = cvt(_io_resp_aa_T_30)
node _io_resp_aa_T_32 = and(_io_resp_aa_T_31, asSInt(UInt<33>(0h90000000)))
node _io_resp_aa_T_33 = asSInt(_io_resp_aa_T_32)
node _io_resp_aa_T_34 = eq(_io_resp_aa_T_33, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_35 = or(_io_resp_aa_T_4, _io_resp_aa_T_9)
node _io_resp_aa_T_36 = or(_io_resp_aa_T_35, _io_resp_aa_T_14)
node _io_resp_aa_T_37 = or(_io_resp_aa_T_36, _io_resp_aa_T_19)
node _io_resp_aa_T_38 = or(_io_resp_aa_T_37, _io_resp_aa_T_24)
node _io_resp_aa_T_39 = or(_io_resp_aa_T_38, _io_resp_aa_T_29)
node _io_resp_aa_T_40 = or(_io_resp_aa_T_39, _io_resp_aa_T_34)
node _io_resp_aa_T_41 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_aa_T_42 = cvt(_io_resp_aa_T_41)
node _io_resp_aa_T_43 = and(_io_resp_aa_T_42, asSInt(UInt<33>(0h9a110000)))
node _io_resp_aa_T_44 = asSInt(_io_resp_aa_T_43)
node _io_resp_aa_T_45 = eq(_io_resp_aa_T_44, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_46 = mux(_io_resp_aa_T_40, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_aa_T_47 = mux(_io_resp_aa_T_45, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_aa_T_48 = or(_io_resp_aa_T_46, _io_resp_aa_T_47)
wire _io_resp_aa_WIRE : UInt<1>
connect _io_resp_aa_WIRE, _io_resp_aa_T_48
node _io_resp_aa_T_49 = and(legal_address, _io_resp_aa_WIRE)
connect io.resp.aa, _io_resp_aa_T_49
node _io_resp_x_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_x_T_1 = cvt(_io_resp_x_T)
node _io_resp_x_T_2 = and(_io_resp_x_T_1, asSInt(UInt<33>(0h9e113000)))
node _io_resp_x_T_3 = asSInt(_io_resp_x_T_2)
node _io_resp_x_T_4 = eq(_io_resp_x_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_5 = xor(io.paddr, UInt<14>(0h3000))
node _io_resp_x_T_6 = cvt(_io_resp_x_T_5)
node _io_resp_x_T_7 = and(_io_resp_x_T_6, asSInt(UInt<33>(0h9e113000)))
node _io_resp_x_T_8 = asSInt(_io_resp_x_T_7)
node _io_resp_x_T_9 = eq(_io_resp_x_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_10 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_x_T_11 = cvt(_io_resp_x_T_10)
node _io_resp_x_T_12 = and(_io_resp_x_T_11, asSInt(UInt<33>(0h9e110000)))
node _io_resp_x_T_13 = asSInt(_io_resp_x_T_12)
node _io_resp_x_T_14 = eq(_io_resp_x_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_15 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_x_T_16 = cvt(_io_resp_x_T_15)
node _io_resp_x_T_17 = and(_io_resp_x_T_16, asSInt(UInt<33>(0h9e110000)))
node _io_resp_x_T_18 = asSInt(_io_resp_x_T_17)
node _io_resp_x_T_19 = eq(_io_resp_x_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_20 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_x_T_21 = cvt(_io_resp_x_T_20)
node _io_resp_x_T_22 = and(_io_resp_x_T_21, asSInt(UInt<33>(0h90000000)))
node _io_resp_x_T_23 = asSInt(_io_resp_x_T_22)
node _io_resp_x_T_24 = eq(_io_resp_x_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_25 = or(_io_resp_x_T_4, _io_resp_x_T_9)
node _io_resp_x_T_26 = or(_io_resp_x_T_25, _io_resp_x_T_14)
node _io_resp_x_T_27 = or(_io_resp_x_T_26, _io_resp_x_T_19)
node _io_resp_x_T_28 = or(_io_resp_x_T_27, _io_resp_x_T_24)
node _io_resp_x_T_29 = xor(io.paddr, UInt<13>(0h1000))
node _io_resp_x_T_30 = cvt(_io_resp_x_T_29)
node _io_resp_x_T_31 = and(_io_resp_x_T_30, asSInt(UInt<33>(0h9e113000)))
node _io_resp_x_T_32 = asSInt(_io_resp_x_T_31)
node _io_resp_x_T_33 = eq(_io_resp_x_T_32, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_34 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_x_T_35 = cvt(_io_resp_x_T_34)
node _io_resp_x_T_36 = and(_io_resp_x_T_35, asSInt(UInt<33>(0h9e103000)))
node _io_resp_x_T_37 = asSInt(_io_resp_x_T_36)
node _io_resp_x_T_38 = eq(_io_resp_x_T_37, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_39 = xor(io.paddr, UInt<26>(0h2000000))
node _io_resp_x_T_40 = cvt(_io_resp_x_T_39)
node _io_resp_x_T_41 = and(_io_resp_x_T_40, asSInt(UInt<33>(0h9e110000)))
node _io_resp_x_T_42 = asSInt(_io_resp_x_T_41)
node _io_resp_x_T_43 = eq(_io_resp_x_T_42, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_44 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_x_T_45 = cvt(_io_resp_x_T_44)
node _io_resp_x_T_46 = and(_io_resp_x_T_45, asSInt(UInt<33>(0h9e113000)))
node _io_resp_x_T_47 = asSInt(_io_resp_x_T_46)
node _io_resp_x_T_48 = eq(_io_resp_x_T_47, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_49 = xor(io.paddr, UInt<28>(0hc000000))
node _io_resp_x_T_50 = cvt(_io_resp_x_T_49)
node _io_resp_x_T_51 = and(_io_resp_x_T_50, asSInt(UInt<33>(0h9c000000)))
node _io_resp_x_T_52 = asSInt(_io_resp_x_T_51)
node _io_resp_x_T_53 = eq(_io_resp_x_T_52, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_54 = xor(io.paddr, UInt<29>(0h10000000))
node _io_resp_x_T_55 = cvt(_io_resp_x_T_54)
node _io_resp_x_T_56 = and(_io_resp_x_T_55, asSInt(UInt<33>(0h9e113000)))
node _io_resp_x_T_57 = asSInt(_io_resp_x_T_56)
node _io_resp_x_T_58 = eq(_io_resp_x_T_57, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_59 = or(_io_resp_x_T_33, _io_resp_x_T_38)
node _io_resp_x_T_60 = or(_io_resp_x_T_59, _io_resp_x_T_43)
node _io_resp_x_T_61 = or(_io_resp_x_T_60, _io_resp_x_T_48)
node _io_resp_x_T_62 = or(_io_resp_x_T_61, _io_resp_x_T_53)
node _io_resp_x_T_63 = or(_io_resp_x_T_62, _io_resp_x_T_58)
node _io_resp_x_T_64 = mux(_io_resp_x_T_28, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_x_T_65 = mux(_io_resp_x_T_63, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_x_T_66 = or(_io_resp_x_T_64, _io_resp_x_T_65)
wire _io_resp_x_WIRE : UInt<1>
connect _io_resp_x_WIRE, _io_resp_x_T_66
node _io_resp_x_T_67 = and(legal_address, _io_resp_x_WIRE)
connect io.resp.x, _io_resp_x_T_67
node _io_resp_eff_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_eff_T_1 = cvt(_io_resp_eff_T)
node _io_resp_eff_T_2 = and(_io_resp_eff_T_1, asSInt(UInt<33>(0h9e112000)))
node _io_resp_eff_T_3 = asSInt(_io_resp_eff_T_2)
node _io_resp_eff_T_4 = eq(_io_resp_eff_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_5 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_eff_T_6 = cvt(_io_resp_eff_T_5)
node _io_resp_eff_T_7 = and(_io_resp_eff_T_6, asSInt(UInt<33>(0h9e103000)))
node _io_resp_eff_T_8 = asSInt(_io_resp_eff_T_7)
node _io_resp_eff_T_9 = eq(_io_resp_eff_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_10 = xor(io.paddr, UInt<26>(0h2000000))
node _io_resp_eff_T_11 = cvt(_io_resp_eff_T_10)
node _io_resp_eff_T_12 = and(_io_resp_eff_T_11, asSInt(UInt<33>(0h9e110000)))
node _io_resp_eff_T_13 = asSInt(_io_resp_eff_T_12)
node _io_resp_eff_T_14 = eq(_io_resp_eff_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_15 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_eff_T_16 = cvt(_io_resp_eff_T_15)
node _io_resp_eff_T_17 = and(_io_resp_eff_T_16, asSInt(UInt<33>(0h9e113000)))
node _io_resp_eff_T_18 = asSInt(_io_resp_eff_T_17)
node _io_resp_eff_T_19 = eq(_io_resp_eff_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_20 = xor(io.paddr, UInt<28>(0hc000000))
node _io_resp_eff_T_21 = cvt(_io_resp_eff_T_20)
node _io_resp_eff_T_22 = and(_io_resp_eff_T_21, asSInt(UInt<33>(0h9c000000)))
node _io_resp_eff_T_23 = asSInt(_io_resp_eff_T_22)
node _io_resp_eff_T_24 = eq(_io_resp_eff_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_25 = xor(io.paddr, UInt<29>(0h10000000))
node _io_resp_eff_T_26 = cvt(_io_resp_eff_T_25)
node _io_resp_eff_T_27 = and(_io_resp_eff_T_26, asSInt(UInt<33>(0h9e113000)))
node _io_resp_eff_T_28 = asSInt(_io_resp_eff_T_27)
node _io_resp_eff_T_29 = eq(_io_resp_eff_T_28, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_30 = or(_io_resp_eff_T_4, _io_resp_eff_T_9)
node _io_resp_eff_T_31 = or(_io_resp_eff_T_30, _io_resp_eff_T_14)
node _io_resp_eff_T_32 = or(_io_resp_eff_T_31, _io_resp_eff_T_19)
node _io_resp_eff_T_33 = or(_io_resp_eff_T_32, _io_resp_eff_T_24)
node _io_resp_eff_T_34 = or(_io_resp_eff_T_33, _io_resp_eff_T_29)
node _io_resp_eff_T_35 = xor(io.paddr, UInt<14>(0h3000))
node _io_resp_eff_T_36 = cvt(_io_resp_eff_T_35)
node _io_resp_eff_T_37 = and(_io_resp_eff_T_36, asSInt(UInt<33>(0h9e113000)))
node _io_resp_eff_T_38 = asSInt(_io_resp_eff_T_37)
node _io_resp_eff_T_39 = eq(_io_resp_eff_T_38, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_40 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_eff_T_41 = cvt(_io_resp_eff_T_40)
node _io_resp_eff_T_42 = and(_io_resp_eff_T_41, asSInt(UInt<33>(0h9e110000)))
node _io_resp_eff_T_43 = asSInt(_io_resp_eff_T_42)
node _io_resp_eff_T_44 = eq(_io_resp_eff_T_43, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_45 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_eff_T_46 = cvt(_io_resp_eff_T_45)
node _io_resp_eff_T_47 = and(_io_resp_eff_T_46, asSInt(UInt<33>(0h9e110000)))
node _io_resp_eff_T_48 = asSInt(_io_resp_eff_T_47)
node _io_resp_eff_T_49 = eq(_io_resp_eff_T_48, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_50 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_eff_T_51 = cvt(_io_resp_eff_T_50)
node _io_resp_eff_T_52 = and(_io_resp_eff_T_51, asSInt(UInt<33>(0h90000000)))
node _io_resp_eff_T_53 = asSInt(_io_resp_eff_T_52)
node _io_resp_eff_T_54 = eq(_io_resp_eff_T_53, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_55 = or(_io_resp_eff_T_39, _io_resp_eff_T_44)
node _io_resp_eff_T_56 = or(_io_resp_eff_T_55, _io_resp_eff_T_49)
node _io_resp_eff_T_57 = or(_io_resp_eff_T_56, _io_resp_eff_T_54)
node _io_resp_eff_T_58 = mux(_io_resp_eff_T_34, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_eff_T_59 = mux(_io_resp_eff_T_57, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_eff_T_60 = or(_io_resp_eff_T_58, _io_resp_eff_T_59)
wire _io_resp_eff_WIRE : UInt<1>
connect _io_resp_eff_WIRE, _io_resp_eff_T_60
node _io_resp_eff_T_61 = and(legal_address, _io_resp_eff_WIRE)
connect io.resp.eff, _io_resp_eff_T_61 | module PMAChecker_3( // @[PMA.scala:18:7]
input clock, // @[PMA.scala:18:7]
input reset, // @[PMA.scala:18:7]
input [39:0] io_paddr, // @[PMA.scala:19:14]
output io_resp_cacheable, // @[PMA.scala:19:14]
output io_resp_r, // @[PMA.scala:19:14]
output io_resp_w, // @[PMA.scala:19:14]
output io_resp_pp, // @[PMA.scala:19:14]
output io_resp_al, // @[PMA.scala:19:14]
output io_resp_aa, // @[PMA.scala:19:14]
output io_resp_x, // @[PMA.scala:19:14]
output io_resp_eff // @[PMA.scala:19:14]
);
wire [39:0] io_paddr_0 = io_paddr; // @[PMA.scala:18:7]
wire [40:0] _io_resp_r_T_2 = 41'h0; // @[Parameters.scala:137:46]
wire [40:0] _io_resp_r_T_3 = 41'h0; // @[Parameters.scala:137:46]
wire _io_resp_r_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire _io_resp_cacheable_T_28 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_w_T_47 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_pp_T_47 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_al_T_47 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_aa_T_47 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_x_T_65 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_eff_T_59 = 1'h0; // @[Mux.scala:30:73]
wire [39:0] _legal_address_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_cacheable_T = io_paddr_0; // @[PMA.scala:18:7]
wire _io_resp_cacheable_T_31; // @[PMA.scala:39:19]
wire [39:0] _io_resp_r_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_w_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_pp_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_al_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_aa_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_x_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_eff_T = io_paddr_0; // @[PMA.scala:18:7]
wire _io_resp_r_T_5; // @[PMA.scala:39:19]
wire _io_resp_w_T_49; // @[PMA.scala:39:19]
wire _io_resp_pp_T_49; // @[PMA.scala:39:19]
wire _io_resp_al_T_49; // @[PMA.scala:39:19]
wire _io_resp_aa_T_49; // @[PMA.scala:39:19]
wire _io_resp_x_T_67; // @[PMA.scala:39:19]
wire _io_resp_eff_T_61; // @[PMA.scala:39:19]
wire io_resp_cacheable_0; // @[PMA.scala:18:7]
wire io_resp_r_0; // @[PMA.scala:18:7]
wire io_resp_w_0; // @[PMA.scala:18:7]
wire io_resp_pp_0; // @[PMA.scala:18:7]
wire io_resp_al_0; // @[PMA.scala:18:7]
wire io_resp_aa_0; // @[PMA.scala:18:7]
wire io_resp_x_0; // @[PMA.scala:18:7]
wire io_resp_eff_0; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_1 = {1'h0, _legal_address_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_2 = _legal_address_T_1 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_3 = _legal_address_T_2; // @[Parameters.scala:137:46]
wire _legal_address_T_4 = _legal_address_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_0 = _legal_address_T_4; // @[Parameters.scala:612:40]
wire [39:0] _GEN = {io_paddr_0[39:13], io_paddr_0[12:0] ^ 13'h1000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_5; // @[Parameters.scala:137:31]
assign _legal_address_T_5 = _GEN; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_29; // @[Parameters.scala:137:31]
assign _io_resp_x_T_29 = _GEN; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_6 = {1'h0, _legal_address_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_7 = _legal_address_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_8 = _legal_address_T_7; // @[Parameters.scala:137:46]
wire _legal_address_T_9 = _legal_address_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_1 = _legal_address_T_9; // @[Parameters.scala:612:40]
wire [39:0] _GEN_0 = {io_paddr_0[39:14], io_paddr_0[13:0] ^ 14'h3000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_10; // @[Parameters.scala:137:31]
assign _legal_address_T_10 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_5; // @[Parameters.scala:137:31]
assign _io_resp_x_T_5 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_35; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_35 = _GEN_0; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_11 = {1'h0, _legal_address_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_12 = _legal_address_T_11 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_13 = _legal_address_T_12; // @[Parameters.scala:137:46]
wire _legal_address_T_14 = _legal_address_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_2 = _legal_address_T_14; // @[Parameters.scala:612:40]
wire [39:0] _GEN_1 = {io_paddr_0[39:17], io_paddr_0[16:0] ^ 17'h10000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_15; // @[Parameters.scala:137:31]
assign _legal_address_T_15 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_5; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_5 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_41; // @[Parameters.scala:137:31]
assign _io_resp_w_T_41 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_41; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_41 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_41; // @[Parameters.scala:137:31]
assign _io_resp_al_T_41 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_41; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_41 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_10; // @[Parameters.scala:137:31]
assign _io_resp_x_T_10 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_40; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_40 = _GEN_1; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_16 = {1'h0, _legal_address_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_17 = _legal_address_T_16 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_18 = _legal_address_T_17; // @[Parameters.scala:137:46]
wire _legal_address_T_19 = _legal_address_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_3 = _legal_address_T_19; // @[Parameters.scala:612:40]
wire [39:0] _GEN_2 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h100000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_20; // @[Parameters.scala:137:31]
assign _legal_address_T_20 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_5; // @[Parameters.scala:137:31]
assign _io_resp_w_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_5; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_5; // @[Parameters.scala:137:31]
assign _io_resp_al_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_5; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_34; // @[Parameters.scala:137:31]
assign _io_resp_x_T_34 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_5; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_21 = {1'h0, _legal_address_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_22 = _legal_address_T_21 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_23 = _legal_address_T_22; // @[Parameters.scala:137:46]
wire _legal_address_T_24 = _legal_address_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_4 = _legal_address_T_24; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_25 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h110000}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_26 = {1'h0, _legal_address_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_27 = _legal_address_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_28 = _legal_address_T_27; // @[Parameters.scala:137:46]
wire _legal_address_T_29 = _legal_address_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_5 = _legal_address_T_29; // @[Parameters.scala:612:40]
wire [39:0] _GEN_3 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_30; // @[Parameters.scala:137:31]
assign _legal_address_T_30 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_39; // @[Parameters.scala:137:31]
assign _io_resp_x_T_39 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_10; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_10 = _GEN_3; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_31 = {1'h0, _legal_address_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_32 = _legal_address_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_33 = _legal_address_T_32; // @[Parameters.scala:137:46]
wire _legal_address_T_34 = _legal_address_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_6 = _legal_address_T_34; // @[Parameters.scala:612:40]
wire [39:0] _GEN_4 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2010000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_35; // @[Parameters.scala:137:31]
assign _legal_address_T_35 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_10; // @[Parameters.scala:137:31]
assign _io_resp_w_T_10 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_10; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_10 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_10; // @[Parameters.scala:137:31]
assign _io_resp_al_T_10 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_10; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_10 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_44; // @[Parameters.scala:137:31]
assign _io_resp_x_T_44 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_15; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_15 = _GEN_4; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_36 = {1'h0, _legal_address_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_37 = _legal_address_T_36 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_38 = _legal_address_T_37; // @[Parameters.scala:137:46]
wire _legal_address_T_39 = _legal_address_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_7 = _legal_address_T_39; // @[Parameters.scala:612:40]
wire [39:0] _GEN_5 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'h8000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_40; // @[Parameters.scala:137:31]
assign _legal_address_T_40 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_17; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_17 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_15; // @[Parameters.scala:137:31]
assign _io_resp_w_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_20; // @[Parameters.scala:137:31]
assign _io_resp_w_T_20 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_15; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_20; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_20 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_15; // @[Parameters.scala:137:31]
assign _io_resp_al_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_20; // @[Parameters.scala:137:31]
assign _io_resp_al_T_20 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_15; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_20; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_20 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_15; // @[Parameters.scala:137:31]
assign _io_resp_x_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_45; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_45 = _GEN_5; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_41 = {1'h0, _legal_address_T_40}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_42 = _legal_address_T_41 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_43 = _legal_address_T_42; // @[Parameters.scala:137:46]
wire _legal_address_T_44 = _legal_address_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_8 = _legal_address_T_44; // @[Parameters.scala:612:40]
wire [39:0] _GEN_6 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'hC000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_45; // @[Parameters.scala:137:31]
assign _legal_address_T_45 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_10; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_10 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_49; // @[Parameters.scala:137:31]
assign _io_resp_x_T_49 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_20; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_20 = _GEN_6; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_46 = {1'h0, _legal_address_T_45}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_47 = _legal_address_T_46 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_48 = _legal_address_T_47; // @[Parameters.scala:137:46]
wire _legal_address_T_49 = _legal_address_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_9 = _legal_address_T_49; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_50 = {io_paddr_0[39:29], io_paddr_0[28:0] ^ 29'h10020000}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_51 = {1'h0, _legal_address_T_50}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_52 = _legal_address_T_51 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_53 = _legal_address_T_52; // @[Parameters.scala:137:46]
wire _legal_address_T_54 = _legal_address_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_10 = _legal_address_T_54; // @[Parameters.scala:612:40]
wire [39:0] _GEN_7 = {io_paddr_0[39:32], io_paddr_0[31:0] ^ 32'h80000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_55; // @[Parameters.scala:137:31]
assign _legal_address_T_55 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_22; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_22 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_30; // @[Parameters.scala:137:31]
assign _io_resp_w_T_30 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_30; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_30 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_30; // @[Parameters.scala:137:31]
assign _io_resp_al_T_30 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_30; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_30 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_20; // @[Parameters.scala:137:31]
assign _io_resp_x_T_20 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_50; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_50 = _GEN_7; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_56 = {1'h0, _legal_address_T_55}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_57 = _legal_address_T_56 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_58 = _legal_address_T_57; // @[Parameters.scala:137:46]
wire _legal_address_T_59 = _legal_address_T_58 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_11 = _legal_address_T_59; // @[Parameters.scala:612:40]
wire _legal_address_T_60 = _legal_address_WIRE_0 | _legal_address_WIRE_1; // @[Parameters.scala:612:40]
wire _legal_address_T_61 = _legal_address_T_60 | _legal_address_WIRE_2; // @[Parameters.scala:612:40]
wire _legal_address_T_62 = _legal_address_T_61 | _legal_address_WIRE_3; // @[Parameters.scala:612:40]
wire _legal_address_T_63 = _legal_address_T_62 | _legal_address_WIRE_4; // @[Parameters.scala:612:40]
wire _legal_address_T_64 = _legal_address_T_63 | _legal_address_WIRE_5; // @[Parameters.scala:612:40]
wire _legal_address_T_65 = _legal_address_T_64 | _legal_address_WIRE_6; // @[Parameters.scala:612:40]
wire _legal_address_T_66 = _legal_address_T_65 | _legal_address_WIRE_7; // @[Parameters.scala:612:40]
wire _legal_address_T_67 = _legal_address_T_66 | _legal_address_WIRE_8; // @[Parameters.scala:612:40]
wire _legal_address_T_68 = _legal_address_T_67 | _legal_address_WIRE_9; // @[Parameters.scala:612:40]
wire _legal_address_T_69 = _legal_address_T_68 | _legal_address_WIRE_10; // @[Parameters.scala:612:40]
wire legal_address = _legal_address_T_69 | _legal_address_WIRE_11; // @[Parameters.scala:612:40]
assign _io_resp_r_T_5 = legal_address; // @[PMA.scala:36:58, :39:19]
wire [40:0] _io_resp_cacheable_T_1 = {1'h0, _io_resp_cacheable_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_2 = _io_resp_cacheable_T_1 & 41'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_3 = _io_resp_cacheable_T_2; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_4 = _io_resp_cacheable_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_cacheable_T_6 = {1'h0, _io_resp_cacheable_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_7 = _io_resp_cacheable_T_6 & 41'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_8 = _io_resp_cacheable_T_7; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_9 = _io_resp_cacheable_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_cacheable_T_11 = {1'h0, _io_resp_cacheable_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_12 = _io_resp_cacheable_T_11 & 41'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_13 = _io_resp_cacheable_T_12; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_14 = _io_resp_cacheable_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_cacheable_T_15 = _io_resp_cacheable_T_4 | _io_resp_cacheable_T_9; // @[Parameters.scala:629:89]
wire _io_resp_cacheable_T_16 = _io_resp_cacheable_T_15 | _io_resp_cacheable_T_14; // @[Parameters.scala:629:89]
wire [40:0] _io_resp_cacheable_T_18 = {1'h0, _io_resp_cacheable_T_17}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_19 = _io_resp_cacheable_T_18 & 41'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_20 = _io_resp_cacheable_T_19; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_21 = _io_resp_cacheable_T_20 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_cacheable_T_23 = {1'h0, _io_resp_cacheable_T_22}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_24 = _io_resp_cacheable_T_23 & 41'h80000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_25 = _io_resp_cacheable_T_24; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_26 = _io_resp_cacheable_T_25 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_cacheable_T_27 = _io_resp_cacheable_T_21 | _io_resp_cacheable_T_26; // @[Parameters.scala:629:89]
wire _io_resp_cacheable_T_29 = _io_resp_cacheable_T_27; // @[Mux.scala:30:73]
wire _io_resp_cacheable_T_30 = _io_resp_cacheable_T_29; // @[Mux.scala:30:73]
wire _io_resp_cacheable_WIRE = _io_resp_cacheable_T_30; // @[Mux.scala:30:73]
assign _io_resp_cacheable_T_31 = legal_address & _io_resp_cacheable_WIRE; // @[Mux.scala:30:73]
assign io_resp_cacheable_0 = _io_resp_cacheable_T_31; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_r_T_1 = {1'h0, _io_resp_r_T}; // @[Parameters.scala:137:{31,41}]
assign io_resp_r_0 = _io_resp_r_T_5; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_w_T_1 = {1'h0, _io_resp_w_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_2 = _io_resp_w_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_3 = _io_resp_w_T_2; // @[Parameters.scala:137:46]
wire _io_resp_w_T_4 = _io_resp_w_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_6 = {1'h0, _io_resp_w_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_7 = _io_resp_w_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_8 = _io_resp_w_T_7; // @[Parameters.scala:137:46]
wire _io_resp_w_T_9 = _io_resp_w_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_11 = {1'h0, _io_resp_w_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_12 = _io_resp_w_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_13 = _io_resp_w_T_12; // @[Parameters.scala:137:46]
wire _io_resp_w_T_14 = _io_resp_w_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_16 = {1'h0, _io_resp_w_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_17 = _io_resp_w_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_18 = _io_resp_w_T_17; // @[Parameters.scala:137:46]
wire _io_resp_w_T_19 = _io_resp_w_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_21 = {1'h0, _io_resp_w_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_22 = _io_resp_w_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_23 = _io_resp_w_T_22; // @[Parameters.scala:137:46]
wire _io_resp_w_T_24 = _io_resp_w_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_8 = {io_paddr_0[39:29], io_paddr_0[28:0] ^ 29'h10000000}; // @[PMA.scala:18:7]
wire [39:0] _io_resp_w_T_25; // @[Parameters.scala:137:31]
assign _io_resp_w_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_25; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_25; // @[Parameters.scala:137:31]
assign _io_resp_al_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_25; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_54; // @[Parameters.scala:137:31]
assign _io_resp_x_T_54 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_25; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [40:0] _io_resp_w_T_26 = {1'h0, _io_resp_w_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_27 = _io_resp_w_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_28 = _io_resp_w_T_27; // @[Parameters.scala:137:46]
wire _io_resp_w_T_29 = _io_resp_w_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_31 = {1'h0, _io_resp_w_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_32 = _io_resp_w_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_33 = _io_resp_w_T_32; // @[Parameters.scala:137:46]
wire _io_resp_w_T_34 = _io_resp_w_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_w_T_35 = _io_resp_w_T_4 | _io_resp_w_T_9; // @[Parameters.scala:629:89]
wire _io_resp_w_T_36 = _io_resp_w_T_35 | _io_resp_w_T_14; // @[Parameters.scala:629:89]
wire _io_resp_w_T_37 = _io_resp_w_T_36 | _io_resp_w_T_19; // @[Parameters.scala:629:89]
wire _io_resp_w_T_38 = _io_resp_w_T_37 | _io_resp_w_T_24; // @[Parameters.scala:629:89]
wire _io_resp_w_T_39 = _io_resp_w_T_38 | _io_resp_w_T_29; // @[Parameters.scala:629:89]
wire _io_resp_w_T_40 = _io_resp_w_T_39 | _io_resp_w_T_34; // @[Parameters.scala:629:89]
wire _io_resp_w_T_46 = _io_resp_w_T_40; // @[Mux.scala:30:73]
wire [40:0] _io_resp_w_T_42 = {1'h0, _io_resp_w_T_41}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_43 = _io_resp_w_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_44 = _io_resp_w_T_43; // @[Parameters.scala:137:46]
wire _io_resp_w_T_45 = _io_resp_w_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_w_T_48 = _io_resp_w_T_46; // @[Mux.scala:30:73]
wire _io_resp_w_WIRE = _io_resp_w_T_48; // @[Mux.scala:30:73]
assign _io_resp_w_T_49 = legal_address & _io_resp_w_WIRE; // @[Mux.scala:30:73]
assign io_resp_w_0 = _io_resp_w_T_49; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_pp_T_1 = {1'h0, _io_resp_pp_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_2 = _io_resp_pp_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_3 = _io_resp_pp_T_2; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_4 = _io_resp_pp_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_6 = {1'h0, _io_resp_pp_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_7 = _io_resp_pp_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_8 = _io_resp_pp_T_7; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_9 = _io_resp_pp_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_11 = {1'h0, _io_resp_pp_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_12 = _io_resp_pp_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_13 = _io_resp_pp_T_12; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_14 = _io_resp_pp_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_16 = {1'h0, _io_resp_pp_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_17 = _io_resp_pp_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_18 = _io_resp_pp_T_17; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_19 = _io_resp_pp_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_21 = {1'h0, _io_resp_pp_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_22 = _io_resp_pp_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_23 = _io_resp_pp_T_22; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_24 = _io_resp_pp_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_26 = {1'h0, _io_resp_pp_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_27 = _io_resp_pp_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_28 = _io_resp_pp_T_27; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_29 = _io_resp_pp_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_31 = {1'h0, _io_resp_pp_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_32 = _io_resp_pp_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_33 = _io_resp_pp_T_32; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_34 = _io_resp_pp_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_pp_T_35 = _io_resp_pp_T_4 | _io_resp_pp_T_9; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_36 = _io_resp_pp_T_35 | _io_resp_pp_T_14; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_37 = _io_resp_pp_T_36 | _io_resp_pp_T_19; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_38 = _io_resp_pp_T_37 | _io_resp_pp_T_24; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_39 = _io_resp_pp_T_38 | _io_resp_pp_T_29; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_40 = _io_resp_pp_T_39 | _io_resp_pp_T_34; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_46 = _io_resp_pp_T_40; // @[Mux.scala:30:73]
wire [40:0] _io_resp_pp_T_42 = {1'h0, _io_resp_pp_T_41}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_43 = _io_resp_pp_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_44 = _io_resp_pp_T_43; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_45 = _io_resp_pp_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_pp_T_48 = _io_resp_pp_T_46; // @[Mux.scala:30:73]
wire _io_resp_pp_WIRE = _io_resp_pp_T_48; // @[Mux.scala:30:73]
assign _io_resp_pp_T_49 = legal_address & _io_resp_pp_WIRE; // @[Mux.scala:30:73]
assign io_resp_pp_0 = _io_resp_pp_T_49; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_al_T_1 = {1'h0, _io_resp_al_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_2 = _io_resp_al_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_3 = _io_resp_al_T_2; // @[Parameters.scala:137:46]
wire _io_resp_al_T_4 = _io_resp_al_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_6 = {1'h0, _io_resp_al_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_7 = _io_resp_al_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_8 = _io_resp_al_T_7; // @[Parameters.scala:137:46]
wire _io_resp_al_T_9 = _io_resp_al_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_11 = {1'h0, _io_resp_al_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_12 = _io_resp_al_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_13 = _io_resp_al_T_12; // @[Parameters.scala:137:46]
wire _io_resp_al_T_14 = _io_resp_al_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_16 = {1'h0, _io_resp_al_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_17 = _io_resp_al_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_18 = _io_resp_al_T_17; // @[Parameters.scala:137:46]
wire _io_resp_al_T_19 = _io_resp_al_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_21 = {1'h0, _io_resp_al_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_22 = _io_resp_al_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_23 = _io_resp_al_T_22; // @[Parameters.scala:137:46]
wire _io_resp_al_T_24 = _io_resp_al_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_26 = {1'h0, _io_resp_al_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_27 = _io_resp_al_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_28 = _io_resp_al_T_27; // @[Parameters.scala:137:46]
wire _io_resp_al_T_29 = _io_resp_al_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_31 = {1'h0, _io_resp_al_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_32 = _io_resp_al_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_33 = _io_resp_al_T_32; // @[Parameters.scala:137:46]
wire _io_resp_al_T_34 = _io_resp_al_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_al_T_35 = _io_resp_al_T_4 | _io_resp_al_T_9; // @[Parameters.scala:629:89]
wire _io_resp_al_T_36 = _io_resp_al_T_35 | _io_resp_al_T_14; // @[Parameters.scala:629:89]
wire _io_resp_al_T_37 = _io_resp_al_T_36 | _io_resp_al_T_19; // @[Parameters.scala:629:89]
wire _io_resp_al_T_38 = _io_resp_al_T_37 | _io_resp_al_T_24; // @[Parameters.scala:629:89]
wire _io_resp_al_T_39 = _io_resp_al_T_38 | _io_resp_al_T_29; // @[Parameters.scala:629:89]
wire _io_resp_al_T_40 = _io_resp_al_T_39 | _io_resp_al_T_34; // @[Parameters.scala:629:89]
wire _io_resp_al_T_46 = _io_resp_al_T_40; // @[Mux.scala:30:73]
wire [40:0] _io_resp_al_T_42 = {1'h0, _io_resp_al_T_41}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_43 = _io_resp_al_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_44 = _io_resp_al_T_43; // @[Parameters.scala:137:46]
wire _io_resp_al_T_45 = _io_resp_al_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_al_T_48 = _io_resp_al_T_46; // @[Mux.scala:30:73]
wire _io_resp_al_WIRE = _io_resp_al_T_48; // @[Mux.scala:30:73]
assign _io_resp_al_T_49 = legal_address & _io_resp_al_WIRE; // @[Mux.scala:30:73]
assign io_resp_al_0 = _io_resp_al_T_49; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_aa_T_1 = {1'h0, _io_resp_aa_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_2 = _io_resp_aa_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_3 = _io_resp_aa_T_2; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_4 = _io_resp_aa_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_6 = {1'h0, _io_resp_aa_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_7 = _io_resp_aa_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_8 = _io_resp_aa_T_7; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_9 = _io_resp_aa_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_11 = {1'h0, _io_resp_aa_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_12 = _io_resp_aa_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_13 = _io_resp_aa_T_12; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_14 = _io_resp_aa_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_16 = {1'h0, _io_resp_aa_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_17 = _io_resp_aa_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_18 = _io_resp_aa_T_17; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_19 = _io_resp_aa_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_21 = {1'h0, _io_resp_aa_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_22 = _io_resp_aa_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_23 = _io_resp_aa_T_22; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_24 = _io_resp_aa_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_26 = {1'h0, _io_resp_aa_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_27 = _io_resp_aa_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_28 = _io_resp_aa_T_27; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_29 = _io_resp_aa_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_31 = {1'h0, _io_resp_aa_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_32 = _io_resp_aa_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_33 = _io_resp_aa_T_32; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_34 = _io_resp_aa_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_aa_T_35 = _io_resp_aa_T_4 | _io_resp_aa_T_9; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_36 = _io_resp_aa_T_35 | _io_resp_aa_T_14; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_37 = _io_resp_aa_T_36 | _io_resp_aa_T_19; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_38 = _io_resp_aa_T_37 | _io_resp_aa_T_24; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_39 = _io_resp_aa_T_38 | _io_resp_aa_T_29; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_40 = _io_resp_aa_T_39 | _io_resp_aa_T_34; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_46 = _io_resp_aa_T_40; // @[Mux.scala:30:73]
wire [40:0] _io_resp_aa_T_42 = {1'h0, _io_resp_aa_T_41}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_43 = _io_resp_aa_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_44 = _io_resp_aa_T_43; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_45 = _io_resp_aa_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_aa_T_48 = _io_resp_aa_T_46; // @[Mux.scala:30:73]
wire _io_resp_aa_WIRE = _io_resp_aa_T_48; // @[Mux.scala:30:73]
assign _io_resp_aa_T_49 = legal_address & _io_resp_aa_WIRE; // @[Mux.scala:30:73]
assign io_resp_aa_0 = _io_resp_aa_T_49; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_x_T_1 = {1'h0, _io_resp_x_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_2 = _io_resp_x_T_1 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_3 = _io_resp_x_T_2; // @[Parameters.scala:137:46]
wire _io_resp_x_T_4 = _io_resp_x_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_6 = {1'h0, _io_resp_x_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_7 = _io_resp_x_T_6 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_8 = _io_resp_x_T_7; // @[Parameters.scala:137:46]
wire _io_resp_x_T_9 = _io_resp_x_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_11 = {1'h0, _io_resp_x_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_12 = _io_resp_x_T_11 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_13 = _io_resp_x_T_12; // @[Parameters.scala:137:46]
wire _io_resp_x_T_14 = _io_resp_x_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_16 = {1'h0, _io_resp_x_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_17 = _io_resp_x_T_16 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_18 = _io_resp_x_T_17; // @[Parameters.scala:137:46]
wire _io_resp_x_T_19 = _io_resp_x_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_21 = {1'h0, _io_resp_x_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_22 = _io_resp_x_T_21 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_23 = _io_resp_x_T_22; // @[Parameters.scala:137:46]
wire _io_resp_x_T_24 = _io_resp_x_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_x_T_25 = _io_resp_x_T_4 | _io_resp_x_T_9; // @[Parameters.scala:629:89]
wire _io_resp_x_T_26 = _io_resp_x_T_25 | _io_resp_x_T_14; // @[Parameters.scala:629:89]
wire _io_resp_x_T_27 = _io_resp_x_T_26 | _io_resp_x_T_19; // @[Parameters.scala:629:89]
wire _io_resp_x_T_28 = _io_resp_x_T_27 | _io_resp_x_T_24; // @[Parameters.scala:629:89]
wire _io_resp_x_T_64 = _io_resp_x_T_28; // @[Mux.scala:30:73]
wire [40:0] _io_resp_x_T_30 = {1'h0, _io_resp_x_T_29}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_31 = _io_resp_x_T_30 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_32 = _io_resp_x_T_31; // @[Parameters.scala:137:46]
wire _io_resp_x_T_33 = _io_resp_x_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_35 = {1'h0, _io_resp_x_T_34}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_36 = _io_resp_x_T_35 & 41'h9E103000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_37 = _io_resp_x_T_36; // @[Parameters.scala:137:46]
wire _io_resp_x_T_38 = _io_resp_x_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_40 = {1'h0, _io_resp_x_T_39}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_41 = _io_resp_x_T_40 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_42 = _io_resp_x_T_41; // @[Parameters.scala:137:46]
wire _io_resp_x_T_43 = _io_resp_x_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_45 = {1'h0, _io_resp_x_T_44}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_46 = _io_resp_x_T_45 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_47 = _io_resp_x_T_46; // @[Parameters.scala:137:46]
wire _io_resp_x_T_48 = _io_resp_x_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_50 = {1'h0, _io_resp_x_T_49}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_51 = _io_resp_x_T_50 & 41'h9C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_52 = _io_resp_x_T_51; // @[Parameters.scala:137:46]
wire _io_resp_x_T_53 = _io_resp_x_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_55 = {1'h0, _io_resp_x_T_54}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_56 = _io_resp_x_T_55 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_57 = _io_resp_x_T_56; // @[Parameters.scala:137:46]
wire _io_resp_x_T_58 = _io_resp_x_T_57 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_x_T_59 = _io_resp_x_T_33 | _io_resp_x_T_38; // @[Parameters.scala:629:89]
wire _io_resp_x_T_60 = _io_resp_x_T_59 | _io_resp_x_T_43; // @[Parameters.scala:629:89]
wire _io_resp_x_T_61 = _io_resp_x_T_60 | _io_resp_x_T_48; // @[Parameters.scala:629:89]
wire _io_resp_x_T_62 = _io_resp_x_T_61 | _io_resp_x_T_53; // @[Parameters.scala:629:89]
wire _io_resp_x_T_63 = _io_resp_x_T_62 | _io_resp_x_T_58; // @[Parameters.scala:629:89]
wire _io_resp_x_T_66 = _io_resp_x_T_64; // @[Mux.scala:30:73]
wire _io_resp_x_WIRE = _io_resp_x_T_66; // @[Mux.scala:30:73]
assign _io_resp_x_T_67 = legal_address & _io_resp_x_WIRE; // @[Mux.scala:30:73]
assign io_resp_x_0 = _io_resp_x_T_67; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_eff_T_1 = {1'h0, _io_resp_eff_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_2 = _io_resp_eff_T_1 & 41'h9E112000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_3 = _io_resp_eff_T_2; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_4 = _io_resp_eff_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_6 = {1'h0, _io_resp_eff_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_7 = _io_resp_eff_T_6 & 41'h9E103000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_8 = _io_resp_eff_T_7; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_9 = _io_resp_eff_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_11 = {1'h0, _io_resp_eff_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_12 = _io_resp_eff_T_11 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_13 = _io_resp_eff_T_12; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_14 = _io_resp_eff_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_16 = {1'h0, _io_resp_eff_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_17 = _io_resp_eff_T_16 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_18 = _io_resp_eff_T_17; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_19 = _io_resp_eff_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_21 = {1'h0, _io_resp_eff_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_22 = _io_resp_eff_T_21 & 41'h9C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_23 = _io_resp_eff_T_22; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_24 = _io_resp_eff_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_26 = {1'h0, _io_resp_eff_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_27 = _io_resp_eff_T_26 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_28 = _io_resp_eff_T_27; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_29 = _io_resp_eff_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_eff_T_30 = _io_resp_eff_T_4 | _io_resp_eff_T_9; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_31 = _io_resp_eff_T_30 | _io_resp_eff_T_14; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_32 = _io_resp_eff_T_31 | _io_resp_eff_T_19; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_33 = _io_resp_eff_T_32 | _io_resp_eff_T_24; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_34 = _io_resp_eff_T_33 | _io_resp_eff_T_29; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_58 = _io_resp_eff_T_34; // @[Mux.scala:30:73]
wire [40:0] _io_resp_eff_T_36 = {1'h0, _io_resp_eff_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_37 = _io_resp_eff_T_36 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_38 = _io_resp_eff_T_37; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_39 = _io_resp_eff_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_41 = {1'h0, _io_resp_eff_T_40}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_42 = _io_resp_eff_T_41 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_43 = _io_resp_eff_T_42; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_44 = _io_resp_eff_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_46 = {1'h0, _io_resp_eff_T_45}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_47 = _io_resp_eff_T_46 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_48 = _io_resp_eff_T_47; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_49 = _io_resp_eff_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_51 = {1'h0, _io_resp_eff_T_50}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_52 = _io_resp_eff_T_51 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_53 = _io_resp_eff_T_52; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_54 = _io_resp_eff_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_eff_T_55 = _io_resp_eff_T_39 | _io_resp_eff_T_44; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_56 = _io_resp_eff_T_55 | _io_resp_eff_T_49; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_57 = _io_resp_eff_T_56 | _io_resp_eff_T_54; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_60 = _io_resp_eff_T_58; // @[Mux.scala:30:73]
wire _io_resp_eff_WIRE = _io_resp_eff_T_60; // @[Mux.scala:30:73]
assign _io_resp_eff_T_61 = legal_address & _io_resp_eff_WIRE; // @[Mux.scala:30:73]
assign io_resp_eff_0 = _io_resp_eff_T_61; // @[PMA.scala:18:7, :39:19]
assign io_resp_cacheable = io_resp_cacheable_0; // @[PMA.scala:18:7]
assign io_resp_r = io_resp_r_0; // @[PMA.scala:18:7]
assign io_resp_w = io_resp_w_0; // @[PMA.scala:18:7]
assign io_resp_pp = io_resp_pp_0; // @[PMA.scala:18:7]
assign io_resp_al = io_resp_al_0; // @[PMA.scala:18:7]
assign io_resp_aa = io_resp_aa_0; // @[PMA.scala:18:7]
assign io_resp_x = io_resp_x_0; // @[PMA.scala:18:7]
assign io_resp_eff = io_resp_eff_0; // @[PMA.scala:18:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_263 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_280
connect io_out_source_valid.clock, clock
connect io_out_source_valid.reset, reset
connect io_out_source_valid.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_valid.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_263( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_280 io_out_source_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLWriteQueue :
input clock : Clock
input reset : Reset
output auto : { flip mem_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, stream_out : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<0>, keep : UInt<0>, last : UInt<1>, id : UInt<0>, dest : UInt<0>, user : UInt<0>}}}
wire streamNodeOut : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<0>, keep : UInt<0>, last : UInt<1>, id : UInt<0>, dest : UInt<0>, user : UInt<0>}}
invalidate streamNodeOut.bits.user
invalidate streamNodeOut.bits.dest
invalidate streamNodeOut.bits.id
invalidate streamNodeOut.bits.last
invalidate streamNodeOut.bits.keep
invalidate streamNodeOut.bits.strb
invalidate streamNodeOut.bits.data
invalidate streamNodeOut.valid
invalidate streamNodeOut.ready
wire memIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate memIn.d.bits.corrupt
invalidate memIn.d.bits.data
invalidate memIn.d.bits.denied
invalidate memIn.d.bits.sink
invalidate memIn.d.bits.source
invalidate memIn.d.bits.size
invalidate memIn.d.bits.param
invalidate memIn.d.bits.opcode
invalidate memIn.d.valid
invalidate memIn.d.ready
invalidate memIn.a.bits.corrupt
invalidate memIn.a.bits.data
invalidate memIn.a.bits.mask
invalidate memIn.a.bits.address
invalidate memIn.a.bits.source
invalidate memIn.a.bits.size
invalidate memIn.a.bits.param
invalidate memIn.a.bits.opcode
invalidate memIn.a.valid
invalidate memIn.a.ready
inst monitor of TLMonitor_56
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, memIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, memIn.d.bits.data
connect monitor.io.in.d.bits.denied, memIn.d.bits.denied
connect monitor.io.in.d.bits.sink, memIn.d.bits.sink
connect monitor.io.in.d.bits.source, memIn.d.bits.source
connect monitor.io.in.d.bits.size, memIn.d.bits.size
connect monitor.io.in.d.bits.param, memIn.d.bits.param
connect monitor.io.in.d.bits.opcode, memIn.d.bits.opcode
connect monitor.io.in.d.valid, memIn.d.valid
connect monitor.io.in.d.ready, memIn.d.ready
connect monitor.io.in.a.bits.corrupt, memIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, memIn.a.bits.data
connect monitor.io.in.a.bits.mask, memIn.a.bits.mask
connect monitor.io.in.a.bits.address, memIn.a.bits.address
connect monitor.io.in.a.bits.source, memIn.a.bits.source
connect monitor.io.in.a.bits.size, memIn.a.bits.size
connect monitor.io.in.a.bits.param, memIn.a.bits.param
connect monitor.io.in.a.bits.opcode, memIn.a.bits.opcode
connect monitor.io.in.a.valid, memIn.a.valid
connect monitor.io.in.a.ready, memIn.a.ready
connect auto.stream_out, streamNodeOut
connect memIn, auto.mem_in
inst queue of Queue8_UInt64
connect queue.clock, clock
connect queue.reset, reset
connect streamNodeOut.valid, queue.io.deq.valid
connect streamNodeOut.bits.data, queue.io.deq.bits
connect streamNodeOut.bits.last, UInt<1>(0h0)
connect queue.io.deq.ready, streamNodeOut.ready
wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<5>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}}
node _in_bits_read_T = eq(memIn.a.bits.opcode, UInt<3>(0h4))
connect in.bits.read, _in_bits_read_T
node _in_bits_index_T = shr(memIn.a.bits.address, 3)
connect in.bits.index, _in_bits_index_T
connect in.bits.data, memIn.a.bits.data
connect in.bits.mask, memIn.a.bits.mask
connect in.bits.extra.tlrr_extra.source, memIn.a.bits.source
connect in.bits.extra.tlrr_extra.size, memIn.a.bits.size
wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}}
wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<5>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}}
connect out_front.bits, in.bits
node out_maskMatch = not(UInt<5>(0h1))
node out_findex = and(out_front.bits.index, out_maskMatch)
node out_bindex = and(out_front.bits.index, out_maskMatch)
node _out_T = eq(out_findex, UInt<5>(0h0))
node _out_T_1 = eq(out_bindex, UInt<5>(0h0))
node _out_T_2 = eq(out_findex, UInt<5>(0h0))
node _out_T_3 = eq(out_bindex, UInt<5>(0h0))
wire out_rivalid : UInt<1>[2]
wire out_wivalid : UInt<1>[2]
wire out_roready : UInt<1>[2]
wire out_woready : UInt<1>[2]
node _out_frontMask_T = bits(out_front.bits.mask, 0, 0)
node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1)
node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2)
node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3)
node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4)
node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5)
node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6)
node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7)
node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0))
node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8)
node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10)
node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo)
node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12)
node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14)
node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo)
node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo)
node _out_backMask_T = bits(out_front.bits.mask, 0, 0)
node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1)
node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2)
node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3)
node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4)
node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5)
node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6)
node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7)
node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0))
node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8)
node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10)
node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo)
node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12)
node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14)
node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo)
node out_backMask = cat(out_backMask_hi, out_backMask_lo)
node _out_rimask_T = bits(out_frontMask, 63, 0)
node out_rimask = orr(_out_rimask_T)
node _out_wimask_T = bits(out_frontMask, 63, 0)
node out_wimask = andr(_out_wimask_T)
node _out_romask_T = bits(out_backMask, 63, 0)
node out_romask = orr(_out_romask_T)
node _out_womask_T = bits(out_backMask, 63, 0)
node out_womask = andr(_out_womask_T)
node out_f_rivalid = and(out_rivalid[0], out_rimask)
node out_f_roready = and(out_roready[0], out_romask)
node out_f_wivalid = and(out_wivalid[0], out_wimask)
node out_f_woready = and(out_woready[0], out_womask)
node _out_T_4 = bits(out_front.bits.data, 63, 0)
connect queue.io.enq.valid, out_f_woready
connect queue.io.enq.bits, _out_T_4
node _out_T_5 = eq(out_rimask, UInt<1>(0h0))
node _out_T_6 = eq(out_wimask, UInt<1>(0h0))
node _out_T_7 = eq(out_romask, UInt<1>(0h0))
node _out_T_8 = eq(out_womask, UInt<1>(0h0))
node _out_T_9 = or(queue.io.enq.ready, _out_T_8)
node _out_T_10 = or(UInt<1>(0h0), UInt<64>(0h0))
node _out_T_11 = bits(_out_T_10, 63, 0)
node _out_rimask_T_1 = bits(out_frontMask, 63, 0)
node out_rimask_1 = orr(_out_rimask_T_1)
node _out_wimask_T_1 = bits(out_frontMask, 63, 0)
node out_wimask_1 = andr(_out_wimask_T_1)
node _out_romask_T_1 = bits(out_backMask, 63, 0)
node out_romask_1 = orr(_out_romask_T_1)
node _out_womask_T_1 = bits(out_backMask, 63, 0)
node out_womask_1 = andr(_out_womask_T_1)
node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1)
node out_f_roready_1 = and(out_roready[1], out_romask_1)
node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1)
node out_f_woready_1 = and(out_woready[1], out_womask_1)
node _out_T_12 = bits(out_front.bits.data, 63, 0)
node _out_T_13 = eq(out_rimask_1, UInt<1>(0h0))
node _out_T_14 = eq(out_wimask_1, UInt<1>(0h0))
node _out_T_15 = eq(out_romask_1, UInt<1>(0h0))
node _out_T_16 = eq(out_womask_1, UInt<1>(0h0))
node _out_T_17 = or(queue.io.count, UInt<64>(0h0))
node _out_T_18 = bits(_out_T_17, 63, 0)
node out_iindex = bits(out_front.bits.index, 0, 0)
node _out_iindex_T = bits(out_front.bits.index, 1, 1)
node _out_iindex_T_1 = bits(out_front.bits.index, 2, 2)
node _out_iindex_T_2 = bits(out_front.bits.index, 3, 3)
node _out_iindex_T_3 = bits(out_front.bits.index, 4, 4)
node out_oindex = bits(out_front.bits.index, 0, 0)
node _out_oindex_T = bits(out_front.bits.index, 1, 1)
node _out_oindex_T_1 = bits(out_front.bits.index, 2, 2)
node _out_oindex_T_2 = bits(out_front.bits.index, 3, 3)
node _out_oindex_T_3 = bits(out_front.bits.index, 4, 4)
node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex)
node out_frontSel_0 = bits(_out_frontSel_T, 0, 0)
node out_frontSel_1 = bits(_out_frontSel_T, 1, 1)
node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex)
node out_backSel_0 = bits(_out_backSel_T, 0, 0)
node out_backSel_1 = bits(_out_backSel_T, 1, 1)
node _out_rifireMux_T = and(in.valid, out_front.ready)
node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read)
wire out_rifireMux_out : UInt<1>
node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0)
node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T)
connect out_rifireMux_out, UInt<1>(0h1)
connect out_rivalid[0], _out_rifireMux_T_3
node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0))
node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4)
wire out_rifireMux_out_1 : UInt<1>
node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1)
node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, _out_T_2)
connect out_rifireMux_out_1, UInt<1>(0h1)
connect out_rivalid[1], _out_rifireMux_T_7
node _out_rifireMux_T_8 = eq(_out_T_2, UInt<1>(0h0))
node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8)
node _out_rifireMux_T_10 = geq(out_iindex, UInt<2>(0h2))
wire _out_rifireMux_WIRE : UInt<1>[2]
connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5
connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9
node out_rifireMux = mux(_out_rifireMux_T_10, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex])
node _out_wifireMux_T = and(in.valid, out_front.ready)
node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0))
node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1)
wire out_wifireMux_out : UInt<1>
node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0)
node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T)
connect out_wifireMux_out, UInt<1>(0h1)
connect out_wivalid[0], _out_wifireMux_T_4
node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0))
node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5)
wire out_wifireMux_out_1 : UInt<1>
node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1)
node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, _out_T_2)
connect out_wifireMux_out_1, UInt<1>(0h1)
connect out_wivalid[1], _out_wifireMux_T_8
node _out_wifireMux_T_9 = eq(_out_T_2, UInt<1>(0h0))
node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9)
node _out_wifireMux_T_11 = geq(out_iindex, UInt<2>(0h2))
wire _out_wifireMux_WIRE : UInt<1>[2]
connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6
connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10
node out_wifireMux = mux(_out_wifireMux_T_11, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex])
node _out_rofireMux_T = and(out_front.valid, out.ready)
node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read)
wire out_rofireMux_out : UInt<1>
node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0)
node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1)
connect out_rofireMux_out, UInt<1>(0h1)
connect out_roready[0], _out_rofireMux_T_3
node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0))
node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4)
wire out_rofireMux_out_1 : UInt<1>
node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1)
node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, _out_T_3)
connect out_rofireMux_out_1, UInt<1>(0h1)
connect out_roready[1], _out_rofireMux_T_7
node _out_rofireMux_T_8 = eq(_out_T_3, UInt<1>(0h0))
node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8)
node _out_rofireMux_T_10 = geq(out_oindex, UInt<2>(0h2))
wire _out_rofireMux_WIRE : UInt<1>[2]
connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5
connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9
node out_rofireMux = mux(_out_rofireMux_T_10, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex])
node _out_wofireMux_T = and(out_front.valid, out.ready)
node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0))
node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1)
wire out_wofireMux_out : UInt<1>
node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0)
node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1)
node out_wofireMux_all = and(_out_wofireMux_T_4, _out_T_9)
connect out_wofireMux_out, _out_T_9
connect out_woready[0], _out_wofireMux_T_4
node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0))
node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5)
wire out_wofireMux_out_1 : UInt<1>
node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1)
node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, _out_T_3)
connect out_wofireMux_out_1, UInt<1>(0h1)
connect out_woready[1], _out_wofireMux_T_8
node _out_wofireMux_T_9 = eq(_out_T_3, UInt<1>(0h0))
node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9)
node _out_wofireMux_T_11 = geq(out_oindex, UInt<2>(0h2))
wire _out_wofireMux_WIRE : UInt<1>[2]
connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6
connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10
node out_wofireMux = mux(_out_wofireMux_T_11, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex])
node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux)
node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux)
node _out_in_ready_T = and(out_front.ready, out_iready)
connect in.ready, _out_in_ready_T
node _out_front_valid_T = and(in.valid, out_iready)
connect out_front.valid, _out_front_valid_T
node _out_front_ready_T = and(out.ready, out_oready)
connect out_front.ready, _out_front_ready_T
node _out_out_valid_T = and(out_front.valid, out_oready)
connect out.valid, _out_out_valid_T
connect out.bits.read, out_front.bits.read
node _out_out_bits_data_T = geq(out_oindex, UInt<2>(0h2))
wire _out_out_bits_data_WIRE : UInt<1>[2]
connect _out_out_bits_data_WIRE[0], _out_T_1
connect _out_out_bits_data_WIRE[1], _out_T_3
node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex])
node _out_out_bits_data_T_2 = geq(out_oindex, UInt<2>(0h2))
wire _out_out_bits_data_WIRE_1 : UInt<64>[2]
connect _out_out_bits_data_WIRE_1[0], _out_T_11
connect _out_out_bits_data_WIRE_1[1], _out_T_18
node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex])
node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0))
connect out.bits.data, _out_out_bits_data_T_4
connect out.bits.extra, out_front.bits.extra
connect in.valid, memIn.a.valid
connect memIn.a.ready, in.ready
connect memIn.d.valid, out.valid
connect out.ready, memIn.d.ready
wire memIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect memIn_d_bits_d.opcode, UInt<1>(0h0)
connect memIn_d_bits_d.param, UInt<1>(0h0)
connect memIn_d_bits_d.size, out.bits.extra.tlrr_extra.size
connect memIn_d_bits_d.source, out.bits.extra.tlrr_extra.source
connect memIn_d_bits_d.sink, UInt<1>(0h0)
connect memIn_d_bits_d.denied, UInt<1>(0h0)
invalidate memIn_d_bits_d.data
connect memIn_d_bits_d.corrupt, UInt<1>(0h0)
connect memIn.d.bits.corrupt, memIn_d_bits_d.corrupt
connect memIn.d.bits.data, memIn_d_bits_d.data
connect memIn.d.bits.denied, memIn_d_bits_d.denied
connect memIn.d.bits.sink, memIn_d_bits_d.sink
connect memIn.d.bits.source, memIn_d_bits_d.source
connect memIn.d.bits.size, memIn_d_bits_d.size
connect memIn.d.bits.param, memIn_d_bits_d.param
connect memIn.d.bits.opcode, memIn_d_bits_d.opcode
connect memIn.d.bits.data, out.bits.data
node _memIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0))
connect memIn.d.bits.opcode, _memIn_d_bits_opcode_T
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<14>(0h0)
connect _WIRE.bits.source, UInt<11>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<14>(0h0)
connect _WIRE_2.bits.source, UInt<11>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1) | module TLWriteQueue( // @[DspBlocks.scala:29:25]
input clock, // @[DspBlocks.scala:29:25]
input reset, // @[DspBlocks.scala:29:25]
output auto_mem_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_mem_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_mem_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_mem_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_mem_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_mem_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [13:0] auto_mem_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_mem_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_mem_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_mem_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_mem_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_mem_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_mem_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_mem_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_mem_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_mem_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_stream_out_ready, // @[LazyModuleImp.scala:107:25]
output auto_stream_out_valid, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_stream_out_bits_data // @[LazyModuleImp.scala:107:25]
);
wire _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24]
wire out_backSel_0; // @[RegisterRouter.scala:87:24]
wire _queue_io_enq_ready; // @[DspBlocks.scala:37:23]
wire [3:0] _queue_io_count; // @[DspBlocks.scala:37:23]
wire in_bits_read = auto_mem_in_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36]
wire _out_T_3 = auto_mem_in_a_bits_address[7:4] == 4'h0; // @[RegisterRouter.scala:75:19, :87:24]
wire [63:0] out_backMask = {{8{auto_mem_in_a_bits_mask[7]}}, {8{auto_mem_in_a_bits_mask[6]}}, {8{auto_mem_in_a_bits_mask[5]}}, {8{auto_mem_in_a_bits_mask[4]}}, {8{auto_mem_in_a_bits_mask[3]}}, {8{auto_mem_in_a_bits_mask[2]}}, {8{auto_mem_in_a_bits_mask[1]}}, {8{auto_mem_in_a_bits_mask[0]}}}; // @[RegisterRouter.scala:87:24]
assign out_backSel_0 = ~(auto_mem_in_a_bits_address[3]); // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1 = ~in_bits_read; // @[RegisterRouter.scala:74:36, :87:24]
wire out_oready = in_bits_read | auto_mem_in_a_bits_address[3] | (|{_queue_io_enq_ready | ~(&out_backMask), auto_mem_in_a_bits_address[7:4]}); // @[MuxLiteral.scala:49:10]
wire out_front_ready = auto_mem_in_d_ready & out_oready; // @[MuxLiteral.scala:49:10]
wire out_valid = auto_mem_in_a_valid & out_oready; // @[MuxLiteral.scala:49:10]
wire [2:0] memIn_d_bits_opcode = {2'h0, in_bits_read}; // @[RegisterRouter.scala:74:36, :105:19]
TLMonitor_56 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (out_front_ready), // @[RegisterRouter.scala:87:24]
.io_in_a_valid (auto_mem_in_a_valid),
.io_in_a_bits_opcode (auto_mem_in_a_bits_opcode),
.io_in_a_bits_param (auto_mem_in_a_bits_param),
.io_in_a_bits_size (auto_mem_in_a_bits_size),
.io_in_a_bits_source (auto_mem_in_a_bits_source),
.io_in_a_bits_address (auto_mem_in_a_bits_address),
.io_in_a_bits_mask (auto_mem_in_a_bits_mask),
.io_in_a_bits_corrupt (auto_mem_in_a_bits_corrupt),
.io_in_d_ready (auto_mem_in_d_ready),
.io_in_d_valid (out_valid), // @[RegisterRouter.scala:87:24]
.io_in_d_bits_opcode (memIn_d_bits_opcode), // @[RegisterRouter.scala:105:19]
.io_in_d_bits_size (auto_mem_in_a_bits_size),
.io_in_d_bits_source (auto_mem_in_a_bits_source)
); // @[Nodes.scala:27:25]
Queue8_UInt64 queue ( // @[DspBlocks.scala:37:23]
.clock (clock),
.reset (reset),
.io_enq_ready (_queue_io_enq_ready),
.io_enq_valid (auto_mem_in_a_valid & auto_mem_in_d_ready & _out_wofireMux_T_1 & out_backSel_0 & _out_T_3 & (&out_backMask)), // @[RegisterRouter.scala:87:24]
.io_enq_bits (auto_mem_in_a_bits_data),
.io_deq_ready (auto_stream_out_ready),
.io_deq_valid (auto_stream_out_valid),
.io_deq_bits (auto_stream_out_bits_data),
.io_count (_queue_io_count)
); // @[DspBlocks.scala:37:23]
assign auto_mem_in_a_ready = out_front_ready; // @[RegisterRouter.scala:87:24]
assign auto_mem_in_d_valid = out_valid; // @[RegisterRouter.scala:87:24]
assign auto_mem_in_d_bits_opcode = memIn_d_bits_opcode; // @[RegisterRouter.scala:105:19]
assign auto_mem_in_d_bits_size = auto_mem_in_a_bits_size; // @[DspBlocks.scala:29:25]
assign auto_mem_in_d_bits_source = auto_mem_in_a_bits_source; // @[DspBlocks.scala:29:25]
assign auto_mem_in_d_bits_data = _out_T_3 & auto_mem_in_a_bits_address[3] ? {60'h0, _queue_io_count} : 64'h0; // @[MuxLiteral.scala:49:10]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_5 :
input clock : Clock
input reset : Reset
output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[2], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}}
wire next_state : UInt
wire next_uopc : UInt
wire next_lrs1_rtype : UInt
wire next_lrs2_rtype : UInt
regreset state : UInt<2>, clock, reset, UInt<2>(0h0)
regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0)
connect p1_poisoned, UInt<1>(0h0)
connect p2_poisoned, UInt<1>(0h0)
node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned)
node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned)
wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate slot_uop_uop.debug_tsrc
invalidate slot_uop_uop.debug_fsrc
invalidate slot_uop_uop.bp_xcpt_if
invalidate slot_uop_uop.bp_debug_if
invalidate slot_uop_uop.xcpt_ma_if
invalidate slot_uop_uop.xcpt_ae_if
invalidate slot_uop_uop.xcpt_pf_if
invalidate slot_uop_uop.fp_single
invalidate slot_uop_uop.fp_val
invalidate slot_uop_uop.frs3_en
invalidate slot_uop_uop.lrs2_rtype
invalidate slot_uop_uop.lrs1_rtype
invalidate slot_uop_uop.dst_rtype
invalidate slot_uop_uop.ldst_val
invalidate slot_uop_uop.lrs3
invalidate slot_uop_uop.lrs2
invalidate slot_uop_uop.lrs1
invalidate slot_uop_uop.ldst
invalidate slot_uop_uop.ldst_is_rs1
invalidate slot_uop_uop.flush_on_commit
invalidate slot_uop_uop.is_unique
invalidate slot_uop_uop.is_sys_pc2epc
invalidate slot_uop_uop.uses_stq
invalidate slot_uop_uop.uses_ldq
invalidate slot_uop_uop.is_amo
invalidate slot_uop_uop.is_fencei
invalidate slot_uop_uop.is_fence
invalidate slot_uop_uop.mem_signed
invalidate slot_uop_uop.mem_size
invalidate slot_uop_uop.mem_cmd
invalidate slot_uop_uop.bypassable
invalidate slot_uop_uop.exc_cause
invalidate slot_uop_uop.exception
invalidate slot_uop_uop.stale_pdst
invalidate slot_uop_uop.ppred_busy
invalidate slot_uop_uop.prs3_busy
invalidate slot_uop_uop.prs2_busy
invalidate slot_uop_uop.prs1_busy
invalidate slot_uop_uop.ppred
invalidate slot_uop_uop.prs3
invalidate slot_uop_uop.prs2
invalidate slot_uop_uop.prs1
invalidate slot_uop_uop.pdst
invalidate slot_uop_uop.rxq_idx
invalidate slot_uop_uop.stq_idx
invalidate slot_uop_uop.ldq_idx
invalidate slot_uop_uop.rob_idx
invalidate slot_uop_uop.csr_addr
invalidate slot_uop_uop.imm_packed
invalidate slot_uop_uop.taken
invalidate slot_uop_uop.pc_lob
invalidate slot_uop_uop.edge_inst
invalidate slot_uop_uop.ftq_idx
invalidate slot_uop_uop.br_tag
invalidate slot_uop_uop.br_mask
invalidate slot_uop_uop.is_sfb
invalidate slot_uop_uop.is_jal
invalidate slot_uop_uop.is_jalr
invalidate slot_uop_uop.is_br
invalidate slot_uop_uop.iw_p2_poisoned
invalidate slot_uop_uop.iw_p1_poisoned
invalidate slot_uop_uop.iw_state
invalidate slot_uop_uop.ctrl.is_std
invalidate slot_uop_uop.ctrl.is_sta
invalidate slot_uop_uop.ctrl.is_load
invalidate slot_uop_uop.ctrl.csr_cmd
invalidate slot_uop_uop.ctrl.fcn_dw
invalidate slot_uop_uop.ctrl.op_fcn
invalidate slot_uop_uop.ctrl.imm_sel
invalidate slot_uop_uop.ctrl.op2_sel
invalidate slot_uop_uop.ctrl.op1_sel
invalidate slot_uop_uop.ctrl.br_type
invalidate slot_uop_uop.fu_code
invalidate slot_uop_uop.iq_type
invalidate slot_uop_uop.debug_pc
invalidate slot_uop_uop.is_rvc
invalidate slot_uop_uop.debug_inst
invalidate slot_uop_uop.inst
invalidate slot_uop_uop.uopc
connect slot_uop_uop.uopc, UInt<7>(0h0)
connect slot_uop_uop.bypassable, UInt<1>(0h0)
connect slot_uop_uop.fp_val, UInt<1>(0h0)
connect slot_uop_uop.uses_stq, UInt<1>(0h0)
connect slot_uop_uop.uses_ldq, UInt<1>(0h0)
connect slot_uop_uop.pdst, UInt<1>(0h0)
connect slot_uop_uop.dst_rtype, UInt<2>(0h2)
wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate slot_uop_cs.is_std
invalidate slot_uop_cs.is_sta
invalidate slot_uop_cs.is_load
invalidate slot_uop_cs.csr_cmd
invalidate slot_uop_cs.fcn_dw
invalidate slot_uop_cs.op_fcn
invalidate slot_uop_cs.imm_sel
invalidate slot_uop_cs.op2_sel
invalidate slot_uop_cs.op1_sel
invalidate slot_uop_cs.br_type
connect slot_uop_cs.br_type, UInt<4>(0h0)
connect slot_uop_cs.csr_cmd, UInt<3>(0h0)
connect slot_uop_cs.is_load, UInt<1>(0h0)
connect slot_uop_cs.is_sta, UInt<1>(0h0)
connect slot_uop_cs.is_std, UInt<1>(0h0)
connect slot_uop_uop.ctrl, slot_uop_cs
regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop
node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop)
when io.kill :
connect state, UInt<2>(0h0)
else :
when io.in_uop.valid :
connect state, io.in_uop.bits.iw_state
else :
when io.clear :
connect state, UInt<2>(0h0)
else :
connect state, next_state
connect next_state, state
connect next_uopc, slot_uop.uopc
connect next_lrs1_rtype, slot_uop.lrs1_rtype
connect next_lrs2_rtype, slot_uop.lrs2_rtype
when io.kill :
connect next_state, UInt<2>(0h0)
else :
node _T = eq(state, UInt<2>(0h1))
node _T_1 = and(io.grant, _T)
node _T_2 = eq(state, UInt<2>(0h2))
node _T_3 = and(io.grant, _T_2)
node _T_4 = and(_T_3, p1)
node _T_5 = and(_T_4, p2)
node _T_6 = and(_T_5, ppred)
node _T_7 = or(_T_1, _T_6)
when _T_7 :
node _T_8 = or(p1_poisoned, p2_poisoned)
node _T_9 = and(io.ldspec_miss, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
connect next_state, UInt<2>(0h0)
else :
node _T_11 = eq(state, UInt<2>(0h2))
node _T_12 = and(io.grant, _T_11)
when _T_12 :
node _T_13 = or(p1_poisoned, p2_poisoned)
node _T_14 = and(io.ldspec_miss, _T_13)
node _T_15 = eq(_T_14, UInt<1>(0h0))
when _T_15 :
connect next_state, UInt<2>(0h1)
when p1 :
connect slot_uop.uopc, UInt<7>(0h3)
connect next_uopc, UInt<7>(0h3)
connect slot_uop.lrs1_rtype, UInt<2>(0h2)
connect next_lrs1_rtype, UInt<2>(0h2)
else :
connect slot_uop.lrs2_rtype, UInt<2>(0h2)
connect next_lrs2_rtype, UInt<2>(0h2)
when io.in_uop.valid :
connect slot_uop, io.in_uop.bits
node _T_16 = eq(state, UInt<2>(0h0))
node _T_17 = or(_T_16, io.clear)
node _T_18 = or(_T_17, io.kill)
node _T_19 = asUInt(reset)
node _T_20 = eq(_T_19, UInt<1>(0h0))
when _T_20 :
node _T_21 = eq(_T_18, UInt<1>(0h0))
when _T_21 :
printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf
assert(clock, _T_18, UInt<1>(0h1), "") : assert
wire next_p1 : UInt<1>
connect next_p1, p1
wire next_p2 : UInt<1>
connect next_p2, p2
wire next_p3 : UInt<1>
connect next_p3, p3
wire next_ppred : UInt<1>
connect next_ppred, ppred
when io.in_uop.valid :
node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0))
connect p1, _p1_T
node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0))
connect p2, _p2_T
node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0))
connect p3, _p3_T
node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0))
connect ppred, _ppred_T
node _T_22 = and(io.ldspec_miss, next_p1_poisoned)
when _T_22 :
node _T_23 = neq(next_uop.prs1, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1
assert(clock, _T_23, UInt<1>(0h1), "") : assert_1
connect p1, UInt<1>(0h0)
node _T_27 = and(io.ldspec_miss, next_p2_poisoned)
when _T_27 :
node _T_28 = neq(next_uop.prs2, UInt<1>(0h0))
node _T_29 = asUInt(reset)
node _T_30 = eq(_T_29, UInt<1>(0h0))
when _T_30 :
node _T_31 = eq(_T_28, UInt<1>(0h0))
when _T_31 :
printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2
assert(clock, _T_28, UInt<1>(0h1), "") : assert_2
connect p2, UInt<1>(0h0)
node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1)
node _T_33 = and(io.wakeup_ports[0].valid, _T_32)
when _T_33 :
connect p1, UInt<1>(0h1)
node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2)
node _T_35 = and(io.wakeup_ports[0].valid, _T_34)
when _T_35 :
connect p2, UInt<1>(0h1)
node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3)
node _T_37 = and(io.wakeup_ports[0].valid, _T_36)
when _T_37 :
connect p3, UInt<1>(0h1)
node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1)
node _T_39 = and(io.wakeup_ports[1].valid, _T_38)
when _T_39 :
connect p1, UInt<1>(0h1)
node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2)
node _T_41 = and(io.wakeup_ports[1].valid, _T_40)
when _T_41 :
connect p2, UInt<1>(0h1)
node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3)
node _T_43 = and(io.wakeup_ports[1].valid, _T_42)
when _T_43 :
connect p3, UInt<1>(0h1)
node _T_44 = eq(io.pred_wakeup_port.bits, next_uop.ppred)
node _T_45 = and(io.pred_wakeup_port.valid, _T_44)
when _T_45 :
connect ppred, UInt<1>(0h1)
node _T_46 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0))
node _T_47 = and(io.spec_ld_wakeup[0].valid, _T_46)
node _T_48 = eq(_T_47, UInt<1>(0h0))
node _T_49 = asUInt(reset)
node _T_50 = eq(_T_49, UInt<1>(0h0))
when _T_50 :
node _T_51 = eq(_T_48, UInt<1>(0h0))
when _T_51 :
printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3
assert(clock, _T_48, UInt<1>(0h1), "") : assert_3
node _T_52 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1)
node _T_53 = and(io.spec_ld_wakeup[0].valid, _T_52)
node _T_54 = eq(next_uop.lrs1_rtype, UInt<2>(0h0))
node _T_55 = and(_T_53, _T_54)
when _T_55 :
connect p1, UInt<1>(0h1)
connect p1_poisoned, UInt<1>(0h1)
node _T_56 = eq(next_p1_poisoned, UInt<1>(0h0))
node _T_57 = asUInt(reset)
node _T_58 = eq(_T_57, UInt<1>(0h0))
when _T_58 :
node _T_59 = eq(_T_56, UInt<1>(0h0))
when _T_59 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4
assert(clock, _T_56, UInt<1>(0h1), "") : assert_4
node _T_60 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2)
node _T_61 = and(io.spec_ld_wakeup[0].valid, _T_60)
node _T_62 = eq(next_uop.lrs2_rtype, UInt<2>(0h0))
node _T_63 = and(_T_61, _T_62)
when _T_63 :
connect p2, UInt<1>(0h1)
connect p2_poisoned, UInt<1>(0h1)
node _T_64 = eq(next_p2_poisoned, UInt<1>(0h0))
node _T_65 = asUInt(reset)
node _T_66 = eq(_T_65, UInt<1>(0h0))
when _T_66 :
node _T_67 = eq(_T_64, UInt<1>(0h0))
when _T_67 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5
assert(clock, _T_64, UInt<1>(0h1), "") : assert_5
node _next_br_mask_T = not(io.brupdate.b1.resolve_mask)
node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T)
node _T_68 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask)
node _T_69 = neq(_T_68, UInt<1>(0h0))
when _T_69 :
connect next_state, UInt<2>(0h0)
node _T_70 = eq(io.in_uop.valid, UInt<1>(0h0))
when _T_70 :
connect slot_uop.br_mask, next_br_mask
node _io_request_T = neq(state, UInt<2>(0h0))
node _io_request_T_1 = and(_io_request_T, p1)
node _io_request_T_2 = and(_io_request_T_1, p2)
node _io_request_T_3 = and(_io_request_T_2, p3)
node _io_request_T_4 = and(_io_request_T_3, ppred)
node _io_request_T_5 = eq(io.kill, UInt<1>(0h0))
node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5)
connect io.request, _io_request_T_6
node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal)
node high_priority = or(_high_priority_T, slot_uop.is_jalr)
node _io_request_hp_T = and(io.request, high_priority)
connect io.request_hp, _io_request_hp_T
node _T_71 = eq(state, UInt<2>(0h1))
when _T_71 :
node _io_request_T_7 = and(p1, p2)
node _io_request_T_8 = and(_io_request_T_7, p3)
node _io_request_T_9 = and(_io_request_T_8, ppred)
node _io_request_T_10 = eq(io.kill, UInt<1>(0h0))
node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10)
connect io.request, _io_request_T_11
else :
node _T_72 = eq(state, UInt<2>(0h2))
when _T_72 :
node _io_request_T_12 = or(p1, p2)
node _io_request_T_13 = and(_io_request_T_12, ppred)
node _io_request_T_14 = eq(io.kill, UInt<1>(0h0))
node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14)
connect io.request, _io_request_T_15
else :
connect io.request, UInt<1>(0h0)
node _io_valid_T = neq(state, UInt<2>(0h0))
connect io.valid, _io_valid_T
connect io.uop, slot_uop
connect io.uop.iw_p1_poisoned, p1_poisoned
connect io.uop.iw_p2_poisoned, p2_poisoned
node _may_vacate_T = eq(state, UInt<2>(0h1))
node _may_vacate_T_1 = eq(state, UInt<2>(0h2))
node _may_vacate_T_2 = and(_may_vacate_T_1, p1)
node _may_vacate_T_3 = and(_may_vacate_T_2, p2)
node _may_vacate_T_4 = and(_may_vacate_T_3, ppred)
node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4)
node may_vacate = and(io.grant, _may_vacate_T_5)
node _squash_grant_T = or(p1_poisoned, p2_poisoned)
node squash_grant = and(io.ldspec_miss, _squash_grant_T)
node _io_will_be_valid_T = neq(state, UInt<2>(0h0))
node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0))
node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1)
node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0))
node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3)
connect io.will_be_valid, _io_will_be_valid_T_4
connect io.out_uop, slot_uop
connect io.out_uop.iw_state, next_state
connect io.out_uop.uopc, next_uopc
connect io.out_uop.lrs1_rtype, next_lrs1_rtype
connect io.out_uop.lrs2_rtype, next_lrs2_rtype
connect io.out_uop.br_mask, next_br_mask
node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0))
connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T
node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0))
connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T
node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0))
connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T
node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0))
connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T
connect io.out_uop.iw_p1_poisoned, p1_poisoned
connect io.out_uop.iw_p2_poisoned, p2_poisoned
node _T_73 = eq(state, UInt<2>(0h2))
when _T_73 :
node _T_74 = and(p1, p2)
node _T_75 = and(_T_74, ppred)
when _T_75 :
skip
else :
node _T_76 = and(p1, ppred)
when _T_76 :
connect io.uop.uopc, slot_uop.uopc
connect io.uop.lrs2_rtype, UInt<2>(0h2)
else :
node _T_77 = and(p2, ppred)
when _T_77 :
connect io.uop.uopc, UInt<7>(0h3)
connect io.uop.lrs1_rtype, UInt<2>(0h2)
connect io.debug.p1, p1
connect io.debug.p2, p2
connect io.debug.p3, p3
connect io.debug.ppred, ppred
connect io.debug.state, state | module IssueSlot_5( // @[issue-slot.scala:69:7]
input clock, // @[issue-slot.scala:69:7]
input reset, // @[issue-slot.scala:69:7]
output io_valid, // @[issue-slot.scala:73:14]
output io_will_be_valid, // @[issue-slot.scala:73:14]
output io_request, // @[issue-slot.scala:73:14]
output io_request_hp, // @[issue-slot.scala:73:14]
input io_grant, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_valid, // @[issue-slot.scala:73:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14]
input io_kill, // @[issue-slot.scala:73:14]
input io_clear, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14]
input io_in_uop_valid, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:73:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:73:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14]
output io_out_uop_is_br, // @[issue-slot.scala:73:14]
output io_out_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_out_uop_is_jal, // @[issue-slot.scala:73:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_out_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_out_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_out_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_out_uop_is_fence, // @[issue-slot.scala:73:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_out_uop_is_amo, // @[issue-slot.scala:73:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_out_uop_is_unique, // @[issue-slot.scala:73:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_out_uop_fp_val, // @[issue-slot.scala:73:14]
output io_out_uop_fp_single, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14]
output io_uop_is_br, // @[issue-slot.scala:73:14]
output io_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_uop_is_jal, // @[issue-slot.scala:73:14]
output io_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14]
output io_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14]
output io_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_uop_is_fence, // @[issue-slot.scala:73:14]
output io_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_uop_is_amo, // @[issue-slot.scala:73:14]
output io_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_uop_is_unique, // @[issue-slot.scala:73:14]
output io_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14]
output io_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_uop_fp_val, // @[issue-slot.scala:73:14]
output io_uop_fp_single, // @[issue-slot.scala:73:14]
output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output io_debug_p1, // @[issue-slot.scala:73:14]
output io_debug_p2, // @[issue-slot.scala:73:14]
output io_debug_p3, // @[issue-slot.scala:73:14]
output io_debug_ppred, // @[issue-slot.scala:73:14]
output [1:0] io_debug_state // @[issue-slot.scala:73:14]
);
wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_ldspec_miss = 1'h0; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7]
wire io_spec_ld_wakeup_0_valid = 1'h0; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire next_p1_poisoned = 1'h0; // @[issue-slot.scala:99:29]
wire next_p2_poisoned = 1'h0; // @[issue-slot.scala:100:29]
wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire _squash_grant_T = 1'h0; // @[issue-slot.scala:261:53]
wire squash_grant = 1'h0; // @[issue-slot.scala:261:37]
wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7]
wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [6:0] io_spec_ld_wakeup_0_bits = 7'h0; // @[issue-slot.scala:69:7]
wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire _io_will_be_valid_T_1 = 1'h1; // @[issue-slot.scala:262:51]
wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire _io_valid_T; // @[issue-slot.scala:79:24]
wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32]
wire _io_request_hp_T; // @[issue-slot.scala:243:31]
wire [6:0] next_uopc; // @[issue-slot.scala:82:29]
wire [1:0] next_state; // @[issue-slot.scala:81:29]
wire [15:0] next_br_mask; // @[util.scala:85:25]
wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28]
wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28]
wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28]
wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28]
wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29]
wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29]
wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire io_debug_p1_0; // @[issue-slot.scala:69:7]
wire io_debug_p2_0; // @[issue-slot.scala:69:7]
wire io_debug_p3_0; // @[issue-slot.scala:69:7]
wire io_debug_ppred_0; // @[issue-slot.scala:69:7]
wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7]
wire io_valid_0; // @[issue-slot.scala:69:7]
wire io_will_be_valid_0; // @[issue-slot.scala:69:7]
wire io_request_0; // @[issue-slot.scala:69:7]
wire io_request_hp_0; // @[issue-slot.scala:69:7]
assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29]
assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29]
assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29]
assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29]
reg [1:0] state; // @[issue-slot.scala:86:22]
assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22]
reg p1; // @[issue-slot.scala:87:22]
assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22]
wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25]
reg p2; // @[issue-slot.scala:88:22]
assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22]
wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25]
reg p3; // @[issue-slot.scala:89:22]
assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22]
wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25]
reg ppred; // @[issue-slot.scala:90:22]
assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22]
wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28]
reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_rvc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25]
assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25]
assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25]
assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_is_br; // @[issue-slot.scala:102:25]
assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jalr; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jal; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sfb; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25]
assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25]
assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_edge_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25]
assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_taken; // @[issue-slot.scala:102:25]
assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25]
assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25]
assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25]
assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25]
assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25]
assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25]
assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25]
assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_exception; // @[issue-slot.scala:102:25]
assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25]
assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bypassable; // @[issue-slot.scala:102:25]
assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_mem_signed; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fence; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fencei; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_amo; // @[issue-slot.scala:102:25]
assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_stq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_unique; // @[issue-slot.scala:102:25]
assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25]
assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_val; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25]
assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25]
reg slot_uop_frs3_en; // @[issue-slot.scala:102:25]
assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_val; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_single; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p1_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p2_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25]
wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}]
wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25]
wire _GEN = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51]
wire _GEN_0 = _GEN | ~(_T_12 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17, :143:23]
assign next_uopc = _GEN_0 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51]
assign next_lrs1_rtype = _GEN_0 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51]
wire _GEN_1 = _GEN | ~_T_12 | p1; // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17]
assign next_lrs2_rtype = _GEN_1 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] |
Generate the Verilog code corresponding to this FIRRTL code module TLNoC_router_5ClockSinkDomain :
output auto : { routers_debug_out : { va_stall : UInt[3], sa_stall : UInt[3]}, routers_egress_nodes_out_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, routers_egress_nodes_out_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, routers_egress_nodes_out_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, flip routers_ingress_nodes_in_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip routers_ingress_nodes_in_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, routers_source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}, flip routers_dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}, flip clock_in : { clock : Clock, reset : Reset}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst routers of Router_5
connect routers.clock, childClock
connect routers.reset, childReset
wire clockNodeIn : { clock : Clock, reset : Reset}
invalidate clockNodeIn.reset
invalidate clockNodeIn.clock
connect clockNodeIn, auto.clock_in
connect routers.auto.dest_nodes_in, auto.routers_dest_nodes_in
connect routers.auto.source_nodes_out.vc_free, auto.routers_source_nodes_out.vc_free
connect routers.auto.source_nodes_out.credit_return, auto.routers_source_nodes_out.credit_return
connect auto.routers_source_nodes_out.flit, routers.auto.source_nodes_out.flit
connect routers.auto.ingress_nodes_in_0, auto.routers_ingress_nodes_in_0
connect routers.auto.ingress_nodes_in_1, auto.routers_ingress_nodes_in_1
connect auto.routers_egress_nodes_out_0.flit.bits, routers.auto.egress_nodes_out_0.flit.bits
connect auto.routers_egress_nodes_out_0.flit.valid, routers.auto.egress_nodes_out_0.flit.valid
connect routers.auto.egress_nodes_out_0.flit.ready, auto.routers_egress_nodes_out_0.flit.ready
connect auto.routers_egress_nodes_out_1.flit.bits, routers.auto.egress_nodes_out_1.flit.bits
connect auto.routers_egress_nodes_out_1.flit.valid, routers.auto.egress_nodes_out_1.flit.valid
connect routers.auto.egress_nodes_out_1.flit.ready, auto.routers_egress_nodes_out_1.flit.ready
connect auto.routers_egress_nodes_out_2.flit.bits, routers.auto.egress_nodes_out_2.flit.bits
connect auto.routers_egress_nodes_out_2.flit.valid, routers.auto.egress_nodes_out_2.flit.valid
connect routers.auto.egress_nodes_out_2.flit.ready, auto.routers_egress_nodes_out_2.flit.ready
connect auto.routers_debug_out, routers.auto.debug_out
connect childClock, clockNodeIn.clock
connect childReset, clockNodeIn.reset
connect clock, clockNodeIn.clock
connect reset, clockNodeIn.reset | module TLNoC_router_5ClockSinkDomain( // @[ClockDomain.scala:14:9]
output [3:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_2_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_2_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_2_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_egress_nodes_out_2_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_routers_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_routers_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_routers_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_routers_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_routers_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_routers_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_routers_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_routers_dest_nodes_in_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
Router_5 routers ( // @[NoC.scala:67:22]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0),
.auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1),
.auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2),
.auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0),
.auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1),
.auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2),
.auto_egress_nodes_out_2_flit_valid (auto_routers_egress_nodes_out_2_flit_valid),
.auto_egress_nodes_out_2_flit_bits_head (auto_routers_egress_nodes_out_2_flit_bits_head),
.auto_egress_nodes_out_2_flit_bits_tail (auto_routers_egress_nodes_out_2_flit_bits_tail),
.auto_egress_nodes_out_2_flit_bits_payload (auto_routers_egress_nodes_out_2_flit_bits_payload),
.auto_egress_nodes_out_1_flit_ready (auto_routers_egress_nodes_out_1_flit_ready),
.auto_egress_nodes_out_1_flit_valid (auto_routers_egress_nodes_out_1_flit_valid),
.auto_egress_nodes_out_1_flit_bits_head (auto_routers_egress_nodes_out_1_flit_bits_head),
.auto_egress_nodes_out_1_flit_bits_tail (auto_routers_egress_nodes_out_1_flit_bits_tail),
.auto_egress_nodes_out_1_flit_bits_payload (auto_routers_egress_nodes_out_1_flit_bits_payload),
.auto_egress_nodes_out_0_flit_ready (auto_routers_egress_nodes_out_0_flit_ready),
.auto_egress_nodes_out_0_flit_valid (auto_routers_egress_nodes_out_0_flit_valid),
.auto_egress_nodes_out_0_flit_bits_head (auto_routers_egress_nodes_out_0_flit_bits_head),
.auto_egress_nodes_out_0_flit_bits_tail (auto_routers_egress_nodes_out_0_flit_bits_tail),
.auto_egress_nodes_out_0_flit_bits_payload (auto_routers_egress_nodes_out_0_flit_bits_payload),
.auto_ingress_nodes_in_1_flit_ready (auto_routers_ingress_nodes_in_1_flit_ready),
.auto_ingress_nodes_in_1_flit_valid (auto_routers_ingress_nodes_in_1_flit_valid),
.auto_ingress_nodes_in_1_flit_bits_head (auto_routers_ingress_nodes_in_1_flit_bits_head),
.auto_ingress_nodes_in_1_flit_bits_tail (auto_routers_ingress_nodes_in_1_flit_bits_tail),
.auto_ingress_nodes_in_1_flit_bits_payload (auto_routers_ingress_nodes_in_1_flit_bits_payload),
.auto_ingress_nodes_in_1_flit_bits_egress_id (auto_routers_ingress_nodes_in_1_flit_bits_egress_id),
.auto_ingress_nodes_in_0_flit_ready (auto_routers_ingress_nodes_in_0_flit_ready),
.auto_ingress_nodes_in_0_flit_valid (auto_routers_ingress_nodes_in_0_flit_valid),
.auto_ingress_nodes_in_0_flit_bits_head (auto_routers_ingress_nodes_in_0_flit_bits_head),
.auto_ingress_nodes_in_0_flit_bits_tail (auto_routers_ingress_nodes_in_0_flit_bits_tail),
.auto_ingress_nodes_in_0_flit_bits_payload (auto_routers_ingress_nodes_in_0_flit_bits_payload),
.auto_ingress_nodes_in_0_flit_bits_egress_id (auto_routers_ingress_nodes_in_0_flit_bits_egress_id),
.auto_source_nodes_out_flit_0_valid (auto_routers_source_nodes_out_flit_0_valid),
.auto_source_nodes_out_flit_0_bits_head (auto_routers_source_nodes_out_flit_0_bits_head),
.auto_source_nodes_out_flit_0_bits_tail (auto_routers_source_nodes_out_flit_0_bits_tail),
.auto_source_nodes_out_flit_0_bits_payload (auto_routers_source_nodes_out_flit_0_bits_payload),
.auto_source_nodes_out_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_credit_return (auto_routers_source_nodes_out_credit_return),
.auto_source_nodes_out_vc_free (auto_routers_source_nodes_out_vc_free),
.auto_dest_nodes_in_flit_0_valid (auto_routers_dest_nodes_in_flit_0_valid),
.auto_dest_nodes_in_flit_0_bits_head (auto_routers_dest_nodes_in_flit_0_bits_head),
.auto_dest_nodes_in_flit_0_bits_tail (auto_routers_dest_nodes_in_flit_0_bits_tail),
.auto_dest_nodes_in_flit_0_bits_payload (auto_routers_dest_nodes_in_flit_0_bits_payload),
.auto_dest_nodes_in_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_credit_return (auto_routers_dest_nodes_in_credit_return),
.auto_dest_nodes_in_vc_free (auto_routers_dest_nodes_in_vc_free)
); // @[NoC.scala:67:22]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module OutputUnit_14 :
input clock : Clock
input reset : Reset
output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}}[1], credit_available : UInt<1>[4], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}}[4], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}}[4], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[4], out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<4>, flip vc_free : UInt<4>}}
reg states : { `3` : { occupied : UInt<1>, c : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}}, `2` : { occupied : UInt<1>, c : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}}, `1` : { occupied : UInt<1>, c : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}}, `0` : { occupied : UInt<1>, c : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}}}, clock
connect io.channel_status[0].occupied, states.`0`.occupied
connect io.channel_status[0].flow, states.`0`.flow
connect io.channel_status[1].occupied, states.`1`.occupied
connect io.channel_status[1].flow, states.`1`.flow
connect io.channel_status[2].occupied, states.`2`.occupied
connect io.channel_status[2].flow, states.`2`.flow
connect io.channel_status[3].occupied, states.`3`.occupied
connect io.channel_status[3].flow, states.`3`.flow
connect io.out.flit, io.in
node _T = bits(io.out.vc_free, 0, 0)
when _T :
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(states.`0`.occupied, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at OutputUnit.scala:75 assert(s.occupied)\n") : printf
assert(clock, states.`0`.occupied, UInt<1>(0h1), "") : assert
connect states.`0`.occupied, UInt<1>(0h0)
node _T_4 = bits(io.out.vc_free, 1, 1)
when _T_4 :
node _T_5 = asUInt(reset)
node _T_6 = eq(_T_5, UInt<1>(0h0))
when _T_6 :
node _T_7 = eq(states.`1`.occupied, UInt<1>(0h0))
when _T_7 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at OutputUnit.scala:75 assert(s.occupied)\n") : printf_1
assert(clock, states.`1`.occupied, UInt<1>(0h1), "") : assert_1
connect states.`1`.occupied, UInt<1>(0h0)
node _T_8 = bits(io.out.vc_free, 2, 2)
when _T_8 :
node _T_9 = asUInt(reset)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
node _T_11 = eq(states.`2`.occupied, UInt<1>(0h0))
when _T_11 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at OutputUnit.scala:75 assert(s.occupied)\n") : printf_2
assert(clock, states.`2`.occupied, UInt<1>(0h1), "") : assert_2
connect states.`2`.occupied, UInt<1>(0h0)
node _T_12 = bits(io.out.vc_free, 3, 3)
when _T_12 :
node _T_13 = asUInt(reset)
node _T_14 = eq(_T_13, UInt<1>(0h0))
when _T_14 :
node _T_15 = eq(states.`3`.occupied, UInt<1>(0h0))
when _T_15 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at OutputUnit.scala:75 assert(s.occupied)\n") : printf_3
assert(clock, states.`3`.occupied, UInt<1>(0h1), "") : assert_3
connect states.`3`.occupied, UInt<1>(0h0)
when io.allocs[0].alloc :
connect states.`0`.occupied, UInt<1>(0h1)
connect states.`0`.flow, io.allocs[0].flow
when io.allocs[1].alloc :
connect states.`1`.occupied, UInt<1>(0h1)
connect states.`1`.flow, io.allocs[1].flow
when io.allocs[2].alloc :
connect states.`2`.occupied, UInt<1>(0h1)
connect states.`2`.flow, io.allocs[2].flow
when io.allocs[3].alloc :
connect states.`3`.occupied, UInt<1>(0h1)
connect states.`3`.flow, io.allocs[3].flow
node _io_credit_available_0_T = neq(states.`0`.c, UInt<1>(0h0))
connect io.credit_available[0], _io_credit_available_0_T
node _io_credit_available_1_T = neq(states.`1`.c, UInt<1>(0h0))
connect io.credit_available[1], _io_credit_available_1_T
node _io_credit_available_2_T = neq(states.`2`.c, UInt<1>(0h0))
connect io.credit_available[2], _io_credit_available_2_T
node _io_credit_available_3_T = neq(states.`3`.c, UInt<1>(0h0))
connect io.credit_available[3], _io_credit_available_3_T
node free = bits(io.out.credit_return, 0, 0)
node _states_0_c_T = add(states.`0`.c, free)
node _states_0_c_T_1 = sub(_states_0_c_T, io.credit_alloc[0].alloc)
node _states_0_c_T_2 = tail(_states_0_c_T_1, 1)
connect states.`0`.c, _states_0_c_T_2
node free_1 = bits(io.out.credit_return, 1, 1)
node _states_1_c_T = add(states.`1`.c, free_1)
node _states_1_c_T_1 = sub(_states_1_c_T, io.credit_alloc[1].alloc)
node _states_1_c_T_2 = tail(_states_1_c_T_1, 1)
connect states.`1`.c, _states_1_c_T_2
node free_2 = bits(io.out.credit_return, 2, 2)
node _states_2_c_T = add(states.`2`.c, free_2)
node _states_2_c_T_1 = sub(_states_2_c_T, io.credit_alloc[2].alloc)
node _states_2_c_T_2 = tail(_states_2_c_T_1, 1)
connect states.`2`.c, _states_2_c_T_2
node free_3 = bits(io.out.credit_return, 3, 3)
node _states_3_c_T = add(states.`3`.c, free_3)
node _states_3_c_T_1 = sub(_states_3_c_T, io.credit_alloc[3].alloc)
node _states_3_c_T_2 = tail(_states_3_c_T_1, 1)
connect states.`3`.c, _states_3_c_T_2
node _T_16 = asUInt(reset)
when _T_16 :
connect states.`0`.occupied, UInt<1>(0h0)
connect states.`1`.occupied, UInt<1>(0h0)
connect states.`2`.occupied, UInt<1>(0h0)
connect states.`3`.occupied, UInt<1>(0h0)
connect states.`0`.c, UInt<1>(0h1)
connect states.`1`.c, UInt<1>(0h1)
connect states.`2`.c, UInt<1>(0h1)
connect states.`3`.c, UInt<1>(0h1) | module OutputUnit_14( // @[OutputUnit.scala:52:7]
input clock, // @[OutputUnit.scala:52:7]
input reset, // @[OutputUnit.scala:52:7]
input io_in_0_valid, // @[OutputUnit.scala:58:14]
input io_in_0_bits_head, // @[OutputUnit.scala:58:14]
input io_in_0_bits_tail, // @[OutputUnit.scala:58:14]
input [36:0] io_in_0_bits_payload, // @[OutputUnit.scala:58:14]
input io_in_0_bits_flow_vnet_id, // @[OutputUnit.scala:58:14]
input [3:0] io_in_0_bits_flow_ingress_node, // @[OutputUnit.scala:58:14]
input io_in_0_bits_flow_ingress_node_id, // @[OutputUnit.scala:58:14]
input [3:0] io_in_0_bits_flow_egress_node, // @[OutputUnit.scala:58:14]
input io_in_0_bits_flow_egress_node_id, // @[OutputUnit.scala:58:14]
input [1:0] io_in_0_bits_virt_channel_id, // @[OutputUnit.scala:58:14]
output io_credit_available_0, // @[OutputUnit.scala:58:14]
output io_credit_available_1, // @[OutputUnit.scala:58:14]
output io_credit_available_2, // @[OutputUnit.scala:58:14]
output io_credit_available_3, // @[OutputUnit.scala:58:14]
output io_channel_status_0_occupied, // @[OutputUnit.scala:58:14]
output io_channel_status_1_occupied, // @[OutputUnit.scala:58:14]
output io_channel_status_2_occupied, // @[OutputUnit.scala:58:14]
output io_channel_status_3_occupied, // @[OutputUnit.scala:58:14]
input io_allocs_0_alloc, // @[OutputUnit.scala:58:14]
input io_allocs_1_alloc, // @[OutputUnit.scala:58:14]
input io_allocs_2_alloc, // @[OutputUnit.scala:58:14]
input io_allocs_3_alloc, // @[OutputUnit.scala:58:14]
input io_credit_alloc_0_alloc, // @[OutputUnit.scala:58:14]
input io_credit_alloc_1_alloc, // @[OutputUnit.scala:58:14]
input io_credit_alloc_2_alloc, // @[OutputUnit.scala:58:14]
input io_credit_alloc_3_alloc, // @[OutputUnit.scala:58:14]
output io_out_flit_0_valid, // @[OutputUnit.scala:58:14]
output io_out_flit_0_bits_head, // @[OutputUnit.scala:58:14]
output io_out_flit_0_bits_tail, // @[OutputUnit.scala:58:14]
output [36:0] io_out_flit_0_bits_payload, // @[OutputUnit.scala:58:14]
output io_out_flit_0_bits_flow_vnet_id, // @[OutputUnit.scala:58:14]
output [3:0] io_out_flit_0_bits_flow_ingress_node, // @[OutputUnit.scala:58:14]
output io_out_flit_0_bits_flow_ingress_node_id, // @[OutputUnit.scala:58:14]
output [3:0] io_out_flit_0_bits_flow_egress_node, // @[OutputUnit.scala:58:14]
output io_out_flit_0_bits_flow_egress_node_id, // @[OutputUnit.scala:58:14]
output [1:0] io_out_flit_0_bits_virt_channel_id, // @[OutputUnit.scala:58:14]
input [3:0] io_out_credit_return, // @[OutputUnit.scala:58:14]
input [3:0] io_out_vc_free // @[OutputUnit.scala:58:14]
);
reg states_3_occupied; // @[OutputUnit.scala:66:19]
reg states_3_c; // @[OutputUnit.scala:66:19]
reg states_2_occupied; // @[OutputUnit.scala:66:19]
reg states_2_c; // @[OutputUnit.scala:66:19]
reg states_1_occupied; // @[OutputUnit.scala:66:19]
reg states_1_c; // @[OutputUnit.scala:66:19]
reg states_0_occupied; // @[OutputUnit.scala:66:19]
reg states_0_c; // @[OutputUnit.scala:66:19] |
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a14d64s8k1z4u :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_28
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_a_q of Queue2_TLBundleA_a14d64s8k1z4u
connect nodeOut_a_q.clock, clock
connect nodeOut_a_q.reset, reset
connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid
connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt
connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data
connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask
connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address
connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source
connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size
connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param
connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode
connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready
connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits
connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid
connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready
inst nodeIn_d_q of Queue2_TLBundleD_a14d64s8k1z4u
connect nodeIn_d_q.clock, clock
connect nodeIn_d_q.reset, reset
connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid
connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt
connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data
connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied
connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink
connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source
connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size
connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param
connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode
connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready
connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits
connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid
connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<14>(0h0)
connect _WIRE.bits.source, UInt<8>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<14>(0h0)
connect _WIRE_2.bits.source, UInt<8>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<14>(0h0)
connect _WIRE_6.bits.source, UInt<8>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<14>(0h0)
connect _WIRE_8.bits.source, UInt<8>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_10.bits.sink, UInt<1>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0) | module TLBuffer_a14d64s8k1z4u( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [13:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [13:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [7:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [13:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [7:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire [63:0] auto_out_d_bits_data = 64'h0; // @[Decoupled.scala:362:21]
wire [63:0] nodeOut_d_bits_data = 64'h0; // @[Decoupled.scala:362:21]
wire auto_out_d_bits_denied = 1'h1; // @[Decoupled.scala:362:21]
wire nodeOut_d_bits_denied = 1'h1; // @[Decoupled.scala:362:21]
wire auto_out_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21]
wire nodeOut_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21]
wire [1:0] auto_out_d_bits_param = 2'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire [1:0] nodeOut_d_bits_param = 2'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9]
wire [7:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9]
wire [13:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [13:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire [7:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
wire [7:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
wire [7:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
wire [13:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_d_ready_0; // @[Buffer.scala:40:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
TLMonitor_28 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a14d64s8k1z4u nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a14d64s8k1z4u nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module NoC :
input clock : Clock
input reset : Reset
output auto : { }
output io : { ingress : { flip `36` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `35` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `34` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `33` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `32` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `31` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `30` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `29` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `28` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `27` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `26` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `25` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `24` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `23` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `22` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `21` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `20` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `19` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `18` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `17` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `16` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `15` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `14` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `13` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `12` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `11` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `10` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `9` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `8` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `7` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `6` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `5` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `4` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `3` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `2` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `1` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `0` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}}, egress : { `32` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `31` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `30` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `29` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `28` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `27` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `26` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `25` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `24` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `23` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `22` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `21` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `20` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `19` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `18` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `17` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `16` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `15` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `14` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `13` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `12` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `11` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `10` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `9` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `8` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `7` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `6` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `5` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `4` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `3` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `2` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `1` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `0` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}}, flip router_clocks : { clock : Clock, reset : Reset}[32]}
inst router_sink_domain of TLNoC_router_0ClockSinkDomain
inst router_sink_domain_1 of TLNoC_router_1ClockSinkDomain
inst router_sink_domain_2 of TLNoC_router_2ClockSinkDomain
inst router_sink_domain_3 of TLNoC_router_3ClockSinkDomain
inst router_sink_domain_4 of TLNoC_router_4ClockSinkDomain
inst router_sink_domain_5 of TLNoC_router_5ClockSinkDomain
inst router_sink_domain_6 of TLNoC_router_6ClockSinkDomain
inst router_sink_domain_7 of TLNoC_router_7ClockSinkDomain
inst router_sink_domain_8 of TLNoC_router_8ClockSinkDomain
inst router_sink_domain_9 of TLNoC_router_9ClockSinkDomain
inst router_sink_domain_10 of TLNoC_router_10ClockSinkDomain
inst router_sink_domain_11 of TLNoC_router_11ClockSinkDomain
inst router_sink_domain_12 of TLNoC_router_12ClockSinkDomain
inst router_sink_domain_13 of TLNoC_router_13ClockSinkDomain
inst router_sink_domain_14 of TLNoC_router_14ClockSinkDomain
inst router_sink_domain_15 of TLNoC_router_15ClockSinkDomain
inst router_sink_domain_16 of TLNoC_router_16ClockSinkDomain
inst router_sink_domain_17 of TLNoC_router_17ClockSinkDomain
inst router_sink_domain_18 of TLNoC_router_18ClockSinkDomain
inst router_sink_domain_19 of TLNoC_router_19ClockSinkDomain
inst router_sink_domain_20 of TLNoC_router_20ClockSinkDomain
inst router_sink_domain_21 of TLNoC_router_21ClockSinkDomain
inst router_sink_domain_22 of TLNoC_router_22ClockSinkDomain
inst router_sink_domain_23 of TLNoC_router_23ClockSinkDomain
inst router_sink_domain_24 of TLNoC_router_24ClockSinkDomain
inst router_sink_domain_25 of TLNoC_router_25ClockSinkDomain
inst router_sink_domain_26 of TLNoC_router_26ClockSinkDomain
inst router_sink_domain_27 of TLNoC_router_27ClockSinkDomain
inst router_sink_domain_28 of TLNoC_router_28ClockSinkDomain
inst router_sink_domain_29 of TLNoC_router_29ClockSinkDomain
inst router_sink_domain_30 of TLNoC_router_30ClockSinkDomain
inst router_sink_domain_31 of TLNoC_router_31ClockSinkDomain
wire clockSourceNodesOut : { clock : Clock, reset : Reset}
invalidate clockSourceNodesOut.reset
invalidate clockSourceNodesOut.clock
wire clockSourceNodesOut_1 : { clock : Clock, reset : Reset}
invalidate clockSourceNodesOut_1.reset
invalidate clockSourceNodesOut_1.clock
wire clockSourceNodesOut_2 : { clock : Clock, reset : Reset}
invalidate clockSourceNodesOut_2.reset
invalidate clockSourceNodesOut_2.clock
wire clockSourceNodesOut_3 : { clock : Clock, reset : Reset}
invalidate clockSourceNodesOut_3.reset
invalidate clockSourceNodesOut_3.clock
wire clockSourceNodesOut_4 : { clock : Clock, reset : Reset}
invalidate clockSourceNodesOut_4.reset
invalidate clockSourceNodesOut_4.clock
wire clockSourceNodesOut_5 : { clock : Clock, reset : Reset}
invalidate clockSourceNodesOut_5.reset
invalidate clockSourceNodesOut_5.clock
wire clockSourceNodesOut_6 : { clock : Clock, reset : Reset}
invalidate clockSourceNodesOut_6.reset
invalidate clockSourceNodesOut_6.clock
wire clockSourceNodesOut_7 : { clock : Clock, reset : Reset}
invalidate clockSourceNodesOut_7.reset
invalidate clockSourceNodesOut_7.clock
wire clockSourceNodesOut_8 : { clock : Clock, reset : Reset}
invalidate clockSourceNodesOut_8.reset
invalidate clockSourceNodesOut_8.clock
wire clockSourceNodesOut_9 : { clock : Clock, reset : Reset}
invalidate clockSourceNodesOut_9.reset
invalidate clockSourceNodesOut_9.clock
wire clockSourceNodesOut_10 : { clock : Clock, reset : Reset}
invalidate clockSourceNodesOut_10.reset
invalidate clockSourceNodesOut_10.clock
wire clockSourceNodesOut_11 : { clock : Clock, reset : Reset}
invalidate clockSourceNodesOut_11.reset
invalidate clockSourceNodesOut_11.clock
wire clockSourceNodesOut_12 : { clock : Clock, reset : Reset}
invalidate clockSourceNodesOut_12.reset
invalidate clockSourceNodesOut_12.clock
wire clockSourceNodesOut_13 : { clock : Clock, reset : Reset}
invalidate clockSourceNodesOut_13.reset
invalidate clockSourceNodesOut_13.clock
wire clockSourceNodesOut_14 : { clock : Clock, reset : Reset}
invalidate clockSourceNodesOut_14.reset
invalidate clockSourceNodesOut_14.clock
wire clockSourceNodesOut_15 : { clock : Clock, reset : Reset}
invalidate clockSourceNodesOut_15.reset
invalidate clockSourceNodesOut_15.clock
wire clockSourceNodesOut_16 : { clock : Clock, reset : Reset}
invalidate clockSourceNodesOut_16.reset
invalidate clockSourceNodesOut_16.clock
wire clockSourceNodesOut_17 : { clock : Clock, reset : Reset}
invalidate clockSourceNodesOut_17.reset
invalidate clockSourceNodesOut_17.clock
wire clockSourceNodesOut_18 : { clock : Clock, reset : Reset}
invalidate clockSourceNodesOut_18.reset
invalidate clockSourceNodesOut_18.clock
wire clockSourceNodesOut_19 : { clock : Clock, reset : Reset}
invalidate clockSourceNodesOut_19.reset
invalidate clockSourceNodesOut_19.clock
wire clockSourceNodesOut_20 : { clock : Clock, reset : Reset}
invalidate clockSourceNodesOut_20.reset
invalidate clockSourceNodesOut_20.clock
wire clockSourceNodesOut_21 : { clock : Clock, reset : Reset}
invalidate clockSourceNodesOut_21.reset
invalidate clockSourceNodesOut_21.clock
wire clockSourceNodesOut_22 : { clock : Clock, reset : Reset}
invalidate clockSourceNodesOut_22.reset
invalidate clockSourceNodesOut_22.clock
wire clockSourceNodesOut_23 : { clock : Clock, reset : Reset}
invalidate clockSourceNodesOut_23.reset
invalidate clockSourceNodesOut_23.clock
wire clockSourceNodesOut_24 : { clock : Clock, reset : Reset}
invalidate clockSourceNodesOut_24.reset
invalidate clockSourceNodesOut_24.clock
wire clockSourceNodesOut_25 : { clock : Clock, reset : Reset}
invalidate clockSourceNodesOut_25.reset
invalidate clockSourceNodesOut_25.clock
wire clockSourceNodesOut_26 : { clock : Clock, reset : Reset}
invalidate clockSourceNodesOut_26.reset
invalidate clockSourceNodesOut_26.clock
wire clockSourceNodesOut_27 : { clock : Clock, reset : Reset}
invalidate clockSourceNodesOut_27.reset
invalidate clockSourceNodesOut_27.clock
wire clockSourceNodesOut_28 : { clock : Clock, reset : Reset}
invalidate clockSourceNodesOut_28.reset
invalidate clockSourceNodesOut_28.clock
wire clockSourceNodesOut_29 : { clock : Clock, reset : Reset}
invalidate clockSourceNodesOut_29.reset
invalidate clockSourceNodesOut_29.clock
wire clockSourceNodesOut_30 : { clock : Clock, reset : Reset}
invalidate clockSourceNodesOut_30.reset
invalidate clockSourceNodesOut_30.clock
wire clockSourceNodesOut_31 : { clock : Clock, reset : Reset}
invalidate clockSourceNodesOut_31.reset
invalidate clockSourceNodesOut_31.clock
wire ingressNodesOut : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut.flit.bits.egress_id
invalidate ingressNodesOut.flit.bits.payload
invalidate ingressNodesOut.flit.bits.tail
invalidate ingressNodesOut.flit.bits.head
invalidate ingressNodesOut.flit.valid
invalidate ingressNodesOut.flit.ready
wire ingressNodesOut_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut_1.flit.bits.egress_id
invalidate ingressNodesOut_1.flit.bits.payload
invalidate ingressNodesOut_1.flit.bits.tail
invalidate ingressNodesOut_1.flit.bits.head
invalidate ingressNodesOut_1.flit.valid
invalidate ingressNodesOut_1.flit.ready
wire ingressNodesOut_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut_2.flit.bits.egress_id
invalidate ingressNodesOut_2.flit.bits.payload
invalidate ingressNodesOut_2.flit.bits.tail
invalidate ingressNodesOut_2.flit.bits.head
invalidate ingressNodesOut_2.flit.valid
invalidate ingressNodesOut_2.flit.ready
wire ingressNodesOut_3 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut_3.flit.bits.egress_id
invalidate ingressNodesOut_3.flit.bits.payload
invalidate ingressNodesOut_3.flit.bits.tail
invalidate ingressNodesOut_3.flit.bits.head
invalidate ingressNodesOut_3.flit.valid
invalidate ingressNodesOut_3.flit.ready
wire ingressNodesOut_4 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut_4.flit.bits.egress_id
invalidate ingressNodesOut_4.flit.bits.payload
invalidate ingressNodesOut_4.flit.bits.tail
invalidate ingressNodesOut_4.flit.bits.head
invalidate ingressNodesOut_4.flit.valid
invalidate ingressNodesOut_4.flit.ready
wire ingressNodesOut_5 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut_5.flit.bits.egress_id
invalidate ingressNodesOut_5.flit.bits.payload
invalidate ingressNodesOut_5.flit.bits.tail
invalidate ingressNodesOut_5.flit.bits.head
invalidate ingressNodesOut_5.flit.valid
invalidate ingressNodesOut_5.flit.ready
wire ingressNodesOut_6 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut_6.flit.bits.egress_id
invalidate ingressNodesOut_6.flit.bits.payload
invalidate ingressNodesOut_6.flit.bits.tail
invalidate ingressNodesOut_6.flit.bits.head
invalidate ingressNodesOut_6.flit.valid
invalidate ingressNodesOut_6.flit.ready
wire ingressNodesOut_7 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut_7.flit.bits.egress_id
invalidate ingressNodesOut_7.flit.bits.payload
invalidate ingressNodesOut_7.flit.bits.tail
invalidate ingressNodesOut_7.flit.bits.head
invalidate ingressNodesOut_7.flit.valid
invalidate ingressNodesOut_7.flit.ready
wire ingressNodesOut_8 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut_8.flit.bits.egress_id
invalidate ingressNodesOut_8.flit.bits.payload
invalidate ingressNodesOut_8.flit.bits.tail
invalidate ingressNodesOut_8.flit.bits.head
invalidate ingressNodesOut_8.flit.valid
invalidate ingressNodesOut_8.flit.ready
wire ingressNodesOut_9 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut_9.flit.bits.egress_id
invalidate ingressNodesOut_9.flit.bits.payload
invalidate ingressNodesOut_9.flit.bits.tail
invalidate ingressNodesOut_9.flit.bits.head
invalidate ingressNodesOut_9.flit.valid
invalidate ingressNodesOut_9.flit.ready
wire ingressNodesOut_10 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut_10.flit.bits.egress_id
invalidate ingressNodesOut_10.flit.bits.payload
invalidate ingressNodesOut_10.flit.bits.tail
invalidate ingressNodesOut_10.flit.bits.head
invalidate ingressNodesOut_10.flit.valid
invalidate ingressNodesOut_10.flit.ready
wire ingressNodesOut_11 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut_11.flit.bits.egress_id
invalidate ingressNodesOut_11.flit.bits.payload
invalidate ingressNodesOut_11.flit.bits.tail
invalidate ingressNodesOut_11.flit.bits.head
invalidate ingressNodesOut_11.flit.valid
invalidate ingressNodesOut_11.flit.ready
wire ingressNodesOut_12 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut_12.flit.bits.egress_id
invalidate ingressNodesOut_12.flit.bits.payload
invalidate ingressNodesOut_12.flit.bits.tail
invalidate ingressNodesOut_12.flit.bits.head
invalidate ingressNodesOut_12.flit.valid
invalidate ingressNodesOut_12.flit.ready
wire ingressNodesOut_13 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut_13.flit.bits.egress_id
invalidate ingressNodesOut_13.flit.bits.payload
invalidate ingressNodesOut_13.flit.bits.tail
invalidate ingressNodesOut_13.flit.bits.head
invalidate ingressNodesOut_13.flit.valid
invalidate ingressNodesOut_13.flit.ready
wire ingressNodesOut_14 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut_14.flit.bits.egress_id
invalidate ingressNodesOut_14.flit.bits.payload
invalidate ingressNodesOut_14.flit.bits.tail
invalidate ingressNodesOut_14.flit.bits.head
invalidate ingressNodesOut_14.flit.valid
invalidate ingressNodesOut_14.flit.ready
wire ingressNodesOut_15 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut_15.flit.bits.egress_id
invalidate ingressNodesOut_15.flit.bits.payload
invalidate ingressNodesOut_15.flit.bits.tail
invalidate ingressNodesOut_15.flit.bits.head
invalidate ingressNodesOut_15.flit.valid
invalidate ingressNodesOut_15.flit.ready
wire ingressNodesOut_16 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut_16.flit.bits.egress_id
invalidate ingressNodesOut_16.flit.bits.payload
invalidate ingressNodesOut_16.flit.bits.tail
invalidate ingressNodesOut_16.flit.bits.head
invalidate ingressNodesOut_16.flit.valid
invalidate ingressNodesOut_16.flit.ready
wire ingressNodesOut_17 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut_17.flit.bits.egress_id
invalidate ingressNodesOut_17.flit.bits.payload
invalidate ingressNodesOut_17.flit.bits.tail
invalidate ingressNodesOut_17.flit.bits.head
invalidate ingressNodesOut_17.flit.valid
invalidate ingressNodesOut_17.flit.ready
wire ingressNodesOut_18 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut_18.flit.bits.egress_id
invalidate ingressNodesOut_18.flit.bits.payload
invalidate ingressNodesOut_18.flit.bits.tail
invalidate ingressNodesOut_18.flit.bits.head
invalidate ingressNodesOut_18.flit.valid
invalidate ingressNodesOut_18.flit.ready
wire ingressNodesOut_19 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut_19.flit.bits.egress_id
invalidate ingressNodesOut_19.flit.bits.payload
invalidate ingressNodesOut_19.flit.bits.tail
invalidate ingressNodesOut_19.flit.bits.head
invalidate ingressNodesOut_19.flit.valid
invalidate ingressNodesOut_19.flit.ready
wire ingressNodesOut_20 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut_20.flit.bits.egress_id
invalidate ingressNodesOut_20.flit.bits.payload
invalidate ingressNodesOut_20.flit.bits.tail
invalidate ingressNodesOut_20.flit.bits.head
invalidate ingressNodesOut_20.flit.valid
invalidate ingressNodesOut_20.flit.ready
wire ingressNodesOut_21 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut_21.flit.bits.egress_id
invalidate ingressNodesOut_21.flit.bits.payload
invalidate ingressNodesOut_21.flit.bits.tail
invalidate ingressNodesOut_21.flit.bits.head
invalidate ingressNodesOut_21.flit.valid
invalidate ingressNodesOut_21.flit.ready
wire ingressNodesOut_22 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut_22.flit.bits.egress_id
invalidate ingressNodesOut_22.flit.bits.payload
invalidate ingressNodesOut_22.flit.bits.tail
invalidate ingressNodesOut_22.flit.bits.head
invalidate ingressNodesOut_22.flit.valid
invalidate ingressNodesOut_22.flit.ready
wire ingressNodesOut_23 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut_23.flit.bits.egress_id
invalidate ingressNodesOut_23.flit.bits.payload
invalidate ingressNodesOut_23.flit.bits.tail
invalidate ingressNodesOut_23.flit.bits.head
invalidate ingressNodesOut_23.flit.valid
invalidate ingressNodesOut_23.flit.ready
wire ingressNodesOut_24 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut_24.flit.bits.egress_id
invalidate ingressNodesOut_24.flit.bits.payload
invalidate ingressNodesOut_24.flit.bits.tail
invalidate ingressNodesOut_24.flit.bits.head
invalidate ingressNodesOut_24.flit.valid
invalidate ingressNodesOut_24.flit.ready
wire ingressNodesOut_25 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut_25.flit.bits.egress_id
invalidate ingressNodesOut_25.flit.bits.payload
invalidate ingressNodesOut_25.flit.bits.tail
invalidate ingressNodesOut_25.flit.bits.head
invalidate ingressNodesOut_25.flit.valid
invalidate ingressNodesOut_25.flit.ready
wire ingressNodesOut_26 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut_26.flit.bits.egress_id
invalidate ingressNodesOut_26.flit.bits.payload
invalidate ingressNodesOut_26.flit.bits.tail
invalidate ingressNodesOut_26.flit.bits.head
invalidate ingressNodesOut_26.flit.valid
invalidate ingressNodesOut_26.flit.ready
wire ingressNodesOut_27 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut_27.flit.bits.egress_id
invalidate ingressNodesOut_27.flit.bits.payload
invalidate ingressNodesOut_27.flit.bits.tail
invalidate ingressNodesOut_27.flit.bits.head
invalidate ingressNodesOut_27.flit.valid
invalidate ingressNodesOut_27.flit.ready
wire ingressNodesOut_28 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut_28.flit.bits.egress_id
invalidate ingressNodesOut_28.flit.bits.payload
invalidate ingressNodesOut_28.flit.bits.tail
invalidate ingressNodesOut_28.flit.bits.head
invalidate ingressNodesOut_28.flit.valid
invalidate ingressNodesOut_28.flit.ready
wire ingressNodesOut_29 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut_29.flit.bits.egress_id
invalidate ingressNodesOut_29.flit.bits.payload
invalidate ingressNodesOut_29.flit.bits.tail
invalidate ingressNodesOut_29.flit.bits.head
invalidate ingressNodesOut_29.flit.valid
invalidate ingressNodesOut_29.flit.ready
wire ingressNodesOut_30 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut_30.flit.bits.egress_id
invalidate ingressNodesOut_30.flit.bits.payload
invalidate ingressNodesOut_30.flit.bits.tail
invalidate ingressNodesOut_30.flit.bits.head
invalidate ingressNodesOut_30.flit.valid
invalidate ingressNodesOut_30.flit.ready
wire ingressNodesOut_31 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut_31.flit.bits.egress_id
invalidate ingressNodesOut_31.flit.bits.payload
invalidate ingressNodesOut_31.flit.bits.tail
invalidate ingressNodesOut_31.flit.bits.head
invalidate ingressNodesOut_31.flit.valid
invalidate ingressNodesOut_31.flit.ready
wire ingressNodesOut_32 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut_32.flit.bits.egress_id
invalidate ingressNodesOut_32.flit.bits.payload
invalidate ingressNodesOut_32.flit.bits.tail
invalidate ingressNodesOut_32.flit.bits.head
invalidate ingressNodesOut_32.flit.valid
invalidate ingressNodesOut_32.flit.ready
wire ingressNodesOut_33 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut_33.flit.bits.egress_id
invalidate ingressNodesOut_33.flit.bits.payload
invalidate ingressNodesOut_33.flit.bits.tail
invalidate ingressNodesOut_33.flit.bits.head
invalidate ingressNodesOut_33.flit.valid
invalidate ingressNodesOut_33.flit.ready
wire ingressNodesOut_34 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut_34.flit.bits.egress_id
invalidate ingressNodesOut_34.flit.bits.payload
invalidate ingressNodesOut_34.flit.bits.tail
invalidate ingressNodesOut_34.flit.bits.head
invalidate ingressNodesOut_34.flit.valid
invalidate ingressNodesOut_34.flit.ready
wire ingressNodesOut_35 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut_35.flit.bits.egress_id
invalidate ingressNodesOut_35.flit.bits.payload
invalidate ingressNodesOut_35.flit.bits.tail
invalidate ingressNodesOut_35.flit.bits.head
invalidate ingressNodesOut_35.flit.valid
invalidate ingressNodesOut_35.flit.ready
wire ingressNodesOut_36 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesOut_36.flit.bits.egress_id
invalidate ingressNodesOut_36.flit.bits.payload
invalidate ingressNodesOut_36.flit.bits.tail
invalidate ingressNodesOut_36.flit.bits.head
invalidate ingressNodesOut_36.flit.valid
invalidate ingressNodesOut_36.flit.ready
wire egressNodesIn : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesIn.flit.bits.ingress_id
invalidate egressNodesIn.flit.bits.payload
invalidate egressNodesIn.flit.bits.tail
invalidate egressNodesIn.flit.bits.head
invalidate egressNodesIn.flit.valid
invalidate egressNodesIn.flit.ready
wire egressNodesIn_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesIn_1.flit.bits.ingress_id
invalidate egressNodesIn_1.flit.bits.payload
invalidate egressNodesIn_1.flit.bits.tail
invalidate egressNodesIn_1.flit.bits.head
invalidate egressNodesIn_1.flit.valid
invalidate egressNodesIn_1.flit.ready
wire egressNodesIn_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesIn_2.flit.bits.ingress_id
invalidate egressNodesIn_2.flit.bits.payload
invalidate egressNodesIn_2.flit.bits.tail
invalidate egressNodesIn_2.flit.bits.head
invalidate egressNodesIn_2.flit.valid
invalidate egressNodesIn_2.flit.ready
wire egressNodesIn_3 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesIn_3.flit.bits.ingress_id
invalidate egressNodesIn_3.flit.bits.payload
invalidate egressNodesIn_3.flit.bits.tail
invalidate egressNodesIn_3.flit.bits.head
invalidate egressNodesIn_3.flit.valid
invalidate egressNodesIn_3.flit.ready
wire egressNodesIn_4 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesIn_4.flit.bits.ingress_id
invalidate egressNodesIn_4.flit.bits.payload
invalidate egressNodesIn_4.flit.bits.tail
invalidate egressNodesIn_4.flit.bits.head
invalidate egressNodesIn_4.flit.valid
invalidate egressNodesIn_4.flit.ready
wire egressNodesIn_5 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesIn_5.flit.bits.ingress_id
invalidate egressNodesIn_5.flit.bits.payload
invalidate egressNodesIn_5.flit.bits.tail
invalidate egressNodesIn_5.flit.bits.head
invalidate egressNodesIn_5.flit.valid
invalidate egressNodesIn_5.flit.ready
wire egressNodesIn_6 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesIn_6.flit.bits.ingress_id
invalidate egressNodesIn_6.flit.bits.payload
invalidate egressNodesIn_6.flit.bits.tail
invalidate egressNodesIn_6.flit.bits.head
invalidate egressNodesIn_6.flit.valid
invalidate egressNodesIn_6.flit.ready
wire egressNodesIn_7 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesIn_7.flit.bits.ingress_id
invalidate egressNodesIn_7.flit.bits.payload
invalidate egressNodesIn_7.flit.bits.tail
invalidate egressNodesIn_7.flit.bits.head
invalidate egressNodesIn_7.flit.valid
invalidate egressNodesIn_7.flit.ready
wire egressNodesIn_8 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesIn_8.flit.bits.ingress_id
invalidate egressNodesIn_8.flit.bits.payload
invalidate egressNodesIn_8.flit.bits.tail
invalidate egressNodesIn_8.flit.bits.head
invalidate egressNodesIn_8.flit.valid
invalidate egressNodesIn_8.flit.ready
wire egressNodesIn_9 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesIn_9.flit.bits.ingress_id
invalidate egressNodesIn_9.flit.bits.payload
invalidate egressNodesIn_9.flit.bits.tail
invalidate egressNodesIn_9.flit.bits.head
invalidate egressNodesIn_9.flit.valid
invalidate egressNodesIn_9.flit.ready
wire egressNodesIn_10 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesIn_10.flit.bits.ingress_id
invalidate egressNodesIn_10.flit.bits.payload
invalidate egressNodesIn_10.flit.bits.tail
invalidate egressNodesIn_10.flit.bits.head
invalidate egressNodesIn_10.flit.valid
invalidate egressNodesIn_10.flit.ready
wire egressNodesIn_11 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesIn_11.flit.bits.ingress_id
invalidate egressNodesIn_11.flit.bits.payload
invalidate egressNodesIn_11.flit.bits.tail
invalidate egressNodesIn_11.flit.bits.head
invalidate egressNodesIn_11.flit.valid
invalidate egressNodesIn_11.flit.ready
wire egressNodesIn_12 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesIn_12.flit.bits.ingress_id
invalidate egressNodesIn_12.flit.bits.payload
invalidate egressNodesIn_12.flit.bits.tail
invalidate egressNodesIn_12.flit.bits.head
invalidate egressNodesIn_12.flit.valid
invalidate egressNodesIn_12.flit.ready
wire egressNodesIn_13 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesIn_13.flit.bits.ingress_id
invalidate egressNodesIn_13.flit.bits.payload
invalidate egressNodesIn_13.flit.bits.tail
invalidate egressNodesIn_13.flit.bits.head
invalidate egressNodesIn_13.flit.valid
invalidate egressNodesIn_13.flit.ready
wire egressNodesIn_14 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesIn_14.flit.bits.ingress_id
invalidate egressNodesIn_14.flit.bits.payload
invalidate egressNodesIn_14.flit.bits.tail
invalidate egressNodesIn_14.flit.bits.head
invalidate egressNodesIn_14.flit.valid
invalidate egressNodesIn_14.flit.ready
wire egressNodesIn_15 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesIn_15.flit.bits.ingress_id
invalidate egressNodesIn_15.flit.bits.payload
invalidate egressNodesIn_15.flit.bits.tail
invalidate egressNodesIn_15.flit.bits.head
invalidate egressNodesIn_15.flit.valid
invalidate egressNodesIn_15.flit.ready
wire egressNodesIn_16 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesIn_16.flit.bits.ingress_id
invalidate egressNodesIn_16.flit.bits.payload
invalidate egressNodesIn_16.flit.bits.tail
invalidate egressNodesIn_16.flit.bits.head
invalidate egressNodesIn_16.flit.valid
invalidate egressNodesIn_16.flit.ready
wire egressNodesIn_17 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesIn_17.flit.bits.ingress_id
invalidate egressNodesIn_17.flit.bits.payload
invalidate egressNodesIn_17.flit.bits.tail
invalidate egressNodesIn_17.flit.bits.head
invalidate egressNodesIn_17.flit.valid
invalidate egressNodesIn_17.flit.ready
wire egressNodesIn_18 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesIn_18.flit.bits.ingress_id
invalidate egressNodesIn_18.flit.bits.payload
invalidate egressNodesIn_18.flit.bits.tail
invalidate egressNodesIn_18.flit.bits.head
invalidate egressNodesIn_18.flit.valid
invalidate egressNodesIn_18.flit.ready
wire egressNodesIn_19 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesIn_19.flit.bits.ingress_id
invalidate egressNodesIn_19.flit.bits.payload
invalidate egressNodesIn_19.flit.bits.tail
invalidate egressNodesIn_19.flit.bits.head
invalidate egressNodesIn_19.flit.valid
invalidate egressNodesIn_19.flit.ready
wire egressNodesIn_20 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesIn_20.flit.bits.ingress_id
invalidate egressNodesIn_20.flit.bits.payload
invalidate egressNodesIn_20.flit.bits.tail
invalidate egressNodesIn_20.flit.bits.head
invalidate egressNodesIn_20.flit.valid
invalidate egressNodesIn_20.flit.ready
wire egressNodesIn_21 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesIn_21.flit.bits.ingress_id
invalidate egressNodesIn_21.flit.bits.payload
invalidate egressNodesIn_21.flit.bits.tail
invalidate egressNodesIn_21.flit.bits.head
invalidate egressNodesIn_21.flit.valid
invalidate egressNodesIn_21.flit.ready
wire egressNodesIn_22 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesIn_22.flit.bits.ingress_id
invalidate egressNodesIn_22.flit.bits.payload
invalidate egressNodesIn_22.flit.bits.tail
invalidate egressNodesIn_22.flit.bits.head
invalidate egressNodesIn_22.flit.valid
invalidate egressNodesIn_22.flit.ready
wire egressNodesIn_23 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesIn_23.flit.bits.ingress_id
invalidate egressNodesIn_23.flit.bits.payload
invalidate egressNodesIn_23.flit.bits.tail
invalidate egressNodesIn_23.flit.bits.head
invalidate egressNodesIn_23.flit.valid
invalidate egressNodesIn_23.flit.ready
wire egressNodesIn_24 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesIn_24.flit.bits.ingress_id
invalidate egressNodesIn_24.flit.bits.payload
invalidate egressNodesIn_24.flit.bits.tail
invalidate egressNodesIn_24.flit.bits.head
invalidate egressNodesIn_24.flit.valid
invalidate egressNodesIn_24.flit.ready
wire egressNodesIn_25 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesIn_25.flit.bits.ingress_id
invalidate egressNodesIn_25.flit.bits.payload
invalidate egressNodesIn_25.flit.bits.tail
invalidate egressNodesIn_25.flit.bits.head
invalidate egressNodesIn_25.flit.valid
invalidate egressNodesIn_25.flit.ready
wire egressNodesIn_26 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesIn_26.flit.bits.ingress_id
invalidate egressNodesIn_26.flit.bits.payload
invalidate egressNodesIn_26.flit.bits.tail
invalidate egressNodesIn_26.flit.bits.head
invalidate egressNodesIn_26.flit.valid
invalidate egressNodesIn_26.flit.ready
wire egressNodesIn_27 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesIn_27.flit.bits.ingress_id
invalidate egressNodesIn_27.flit.bits.payload
invalidate egressNodesIn_27.flit.bits.tail
invalidate egressNodesIn_27.flit.bits.head
invalidate egressNodesIn_27.flit.valid
invalidate egressNodesIn_27.flit.ready
wire egressNodesIn_28 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesIn_28.flit.bits.ingress_id
invalidate egressNodesIn_28.flit.bits.payload
invalidate egressNodesIn_28.flit.bits.tail
invalidate egressNodesIn_28.flit.bits.head
invalidate egressNodesIn_28.flit.valid
invalidate egressNodesIn_28.flit.ready
wire egressNodesIn_29 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesIn_29.flit.bits.ingress_id
invalidate egressNodesIn_29.flit.bits.payload
invalidate egressNodesIn_29.flit.bits.tail
invalidate egressNodesIn_29.flit.bits.head
invalidate egressNodesIn_29.flit.valid
invalidate egressNodesIn_29.flit.ready
wire egressNodesIn_30 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesIn_30.flit.bits.ingress_id
invalidate egressNodesIn_30.flit.bits.payload
invalidate egressNodesIn_30.flit.bits.tail
invalidate egressNodesIn_30.flit.bits.head
invalidate egressNodesIn_30.flit.valid
invalidate egressNodesIn_30.flit.ready
wire egressNodesIn_31 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesIn_31.flit.bits.ingress_id
invalidate egressNodesIn_31.flit.bits.payload
invalidate egressNodesIn_31.flit.bits.tail
invalidate egressNodesIn_31.flit.bits.head
invalidate egressNodesIn_31.flit.valid
invalidate egressNodesIn_31.flit.ready
wire egressNodesIn_32 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesIn_32.flit.bits.ingress_id
invalidate egressNodesIn_32.flit.bits.payload
invalidate egressNodesIn_32.flit.bits.tail
invalidate egressNodesIn_32.flit.bits.head
invalidate egressNodesIn_32.flit.valid
invalidate egressNodesIn_32.flit.ready
wire sinkIn : { va_stall : UInt[4], sa_stall : UInt[4]}
invalidate sinkIn.sa_stall[0]
invalidate sinkIn.sa_stall[1]
invalidate sinkIn.sa_stall[2]
invalidate sinkIn.sa_stall[3]
invalidate sinkIn.va_stall[0]
invalidate sinkIn.va_stall[1]
invalidate sinkIn.va_stall[2]
invalidate sinkIn.va_stall[3]
wire sinkIn_1 : { va_stall : UInt[4], sa_stall : UInt[4]}
invalidate sinkIn_1.sa_stall[0]
invalidate sinkIn_1.sa_stall[1]
invalidate sinkIn_1.sa_stall[2]
invalidate sinkIn_1.sa_stall[3]
invalidate sinkIn_1.va_stall[0]
invalidate sinkIn_1.va_stall[1]
invalidate sinkIn_1.va_stall[2]
invalidate sinkIn_1.va_stall[3]
wire sinkIn_2 : { va_stall : UInt[4], sa_stall : UInt[4]}
invalidate sinkIn_2.sa_stall[0]
invalidate sinkIn_2.sa_stall[1]
invalidate sinkIn_2.sa_stall[2]
invalidate sinkIn_2.sa_stall[3]
invalidate sinkIn_2.va_stall[0]
invalidate sinkIn_2.va_stall[1]
invalidate sinkIn_2.va_stall[2]
invalidate sinkIn_2.va_stall[3]
wire sinkIn_3 : { va_stall : UInt[3], sa_stall : UInt[3]}
invalidate sinkIn_3.sa_stall[0]
invalidate sinkIn_3.sa_stall[1]
invalidate sinkIn_3.sa_stall[2]
invalidate sinkIn_3.va_stall[0]
invalidate sinkIn_3.va_stall[1]
invalidate sinkIn_3.va_stall[2]
wire sinkIn_4 : { va_stall : UInt[4], sa_stall : UInt[4]}
invalidate sinkIn_4.sa_stall[0]
invalidate sinkIn_4.sa_stall[1]
invalidate sinkIn_4.sa_stall[2]
invalidate sinkIn_4.sa_stall[3]
invalidate sinkIn_4.va_stall[0]
invalidate sinkIn_4.va_stall[1]
invalidate sinkIn_4.va_stall[2]
invalidate sinkIn_4.va_stall[3]
wire sinkIn_5 : { va_stall : UInt[3], sa_stall : UInt[3]}
invalidate sinkIn_5.sa_stall[0]
invalidate sinkIn_5.sa_stall[1]
invalidate sinkIn_5.sa_stall[2]
invalidate sinkIn_5.va_stall[0]
invalidate sinkIn_5.va_stall[1]
invalidate sinkIn_5.va_stall[2]
wire sinkIn_6 : { va_stall : UInt[3], sa_stall : UInt[3]}
invalidate sinkIn_6.sa_stall[0]
invalidate sinkIn_6.sa_stall[1]
invalidate sinkIn_6.sa_stall[2]
invalidate sinkIn_6.va_stall[0]
invalidate sinkIn_6.va_stall[1]
invalidate sinkIn_6.va_stall[2]
wire sinkIn_7 : { va_stall : UInt[4], sa_stall : UInt[4]}
invalidate sinkIn_7.sa_stall[0]
invalidate sinkIn_7.sa_stall[1]
invalidate sinkIn_7.sa_stall[2]
invalidate sinkIn_7.sa_stall[3]
invalidate sinkIn_7.va_stall[0]
invalidate sinkIn_7.va_stall[1]
invalidate sinkIn_7.va_stall[2]
invalidate sinkIn_7.va_stall[3]
wire sinkIn_8 : { va_stall : UInt[4], sa_stall : UInt[4]}
invalidate sinkIn_8.sa_stall[0]
invalidate sinkIn_8.sa_stall[1]
invalidate sinkIn_8.sa_stall[2]
invalidate sinkIn_8.sa_stall[3]
invalidate sinkIn_8.va_stall[0]
invalidate sinkIn_8.va_stall[1]
invalidate sinkIn_8.va_stall[2]
invalidate sinkIn_8.va_stall[3]
wire sinkIn_9 : { va_stall : UInt[3], sa_stall : UInt[3]}
invalidate sinkIn_9.sa_stall[0]
invalidate sinkIn_9.sa_stall[1]
invalidate sinkIn_9.sa_stall[2]
invalidate sinkIn_9.va_stall[0]
invalidate sinkIn_9.va_stall[1]
invalidate sinkIn_9.va_stall[2]
wire sinkIn_10 : { va_stall : UInt[3], sa_stall : UInt[3]}
invalidate sinkIn_10.sa_stall[0]
invalidate sinkIn_10.sa_stall[1]
invalidate sinkIn_10.sa_stall[2]
invalidate sinkIn_10.va_stall[0]
invalidate sinkIn_10.va_stall[1]
invalidate sinkIn_10.va_stall[2]
wire sinkIn_11 : { va_stall : UInt[4], sa_stall : UInt[4]}
invalidate sinkIn_11.sa_stall[0]
invalidate sinkIn_11.sa_stall[1]
invalidate sinkIn_11.sa_stall[2]
invalidate sinkIn_11.sa_stall[3]
invalidate sinkIn_11.va_stall[0]
invalidate sinkIn_11.va_stall[1]
invalidate sinkIn_11.va_stall[2]
invalidate sinkIn_11.va_stall[3]
wire sinkIn_12 : { va_stall : UInt[4], sa_stall : UInt[4]}
invalidate sinkIn_12.sa_stall[0]
invalidate sinkIn_12.sa_stall[1]
invalidate sinkIn_12.sa_stall[2]
invalidate sinkIn_12.sa_stall[3]
invalidate sinkIn_12.va_stall[0]
invalidate sinkIn_12.va_stall[1]
invalidate sinkIn_12.va_stall[2]
invalidate sinkIn_12.va_stall[3]
wire sinkIn_13 : { va_stall : UInt[4], sa_stall : UInt[4]}
invalidate sinkIn_13.sa_stall[0]
invalidate sinkIn_13.sa_stall[1]
invalidate sinkIn_13.sa_stall[2]
invalidate sinkIn_13.sa_stall[3]
invalidate sinkIn_13.va_stall[0]
invalidate sinkIn_13.va_stall[1]
invalidate sinkIn_13.va_stall[2]
invalidate sinkIn_13.va_stall[3]
wire sinkIn_14 : { va_stall : UInt[3], sa_stall : UInt[3]}
invalidate sinkIn_14.sa_stall[0]
invalidate sinkIn_14.sa_stall[1]
invalidate sinkIn_14.sa_stall[2]
invalidate sinkIn_14.va_stall[0]
invalidate sinkIn_14.va_stall[1]
invalidate sinkIn_14.va_stall[2]
wire sinkIn_15 : { va_stall : UInt[4], sa_stall : UInt[4]}
invalidate sinkIn_15.sa_stall[0]
invalidate sinkIn_15.sa_stall[1]
invalidate sinkIn_15.sa_stall[2]
invalidate sinkIn_15.sa_stall[3]
invalidate sinkIn_15.va_stall[0]
invalidate sinkIn_15.va_stall[1]
invalidate sinkIn_15.va_stall[2]
invalidate sinkIn_15.va_stall[3]
wire sinkIn_16 : { va_stall : UInt[4], sa_stall : UInt[4]}
invalidate sinkIn_16.sa_stall[0]
invalidate sinkIn_16.sa_stall[1]
invalidate sinkIn_16.sa_stall[2]
invalidate sinkIn_16.sa_stall[3]
invalidate sinkIn_16.va_stall[0]
invalidate sinkIn_16.va_stall[1]
invalidate sinkIn_16.va_stall[2]
invalidate sinkIn_16.va_stall[3]
wire sinkIn_17 : { va_stall : UInt[3], sa_stall : UInt[3]}
invalidate sinkIn_17.sa_stall[0]
invalidate sinkIn_17.sa_stall[1]
invalidate sinkIn_17.sa_stall[2]
invalidate sinkIn_17.va_stall[0]
invalidate sinkIn_17.va_stall[1]
invalidate sinkIn_17.va_stall[2]
wire sinkIn_18 : { va_stall : UInt[4], sa_stall : UInt[4]}
invalidate sinkIn_18.sa_stall[0]
invalidate sinkIn_18.sa_stall[1]
invalidate sinkIn_18.sa_stall[2]
invalidate sinkIn_18.sa_stall[3]
invalidate sinkIn_18.va_stall[0]
invalidate sinkIn_18.va_stall[1]
invalidate sinkIn_18.va_stall[2]
invalidate sinkIn_18.va_stall[3]
wire sinkIn_19 : { va_stall : UInt[5], sa_stall : UInt[5]}
invalidate sinkIn_19.sa_stall[0]
invalidate sinkIn_19.sa_stall[1]
invalidate sinkIn_19.sa_stall[2]
invalidate sinkIn_19.sa_stall[3]
invalidate sinkIn_19.sa_stall[4]
invalidate sinkIn_19.va_stall[0]
invalidate sinkIn_19.va_stall[1]
invalidate sinkIn_19.va_stall[2]
invalidate sinkIn_19.va_stall[3]
invalidate sinkIn_19.va_stall[4]
wire sinkIn_20 : { va_stall : UInt[5], sa_stall : UInt[5]}
invalidate sinkIn_20.sa_stall[0]
invalidate sinkIn_20.sa_stall[1]
invalidate sinkIn_20.sa_stall[2]
invalidate sinkIn_20.sa_stall[3]
invalidate sinkIn_20.sa_stall[4]
invalidate sinkIn_20.va_stall[0]
invalidate sinkIn_20.va_stall[1]
invalidate sinkIn_20.va_stall[2]
invalidate sinkIn_20.va_stall[3]
invalidate sinkIn_20.va_stall[4]
wire sinkIn_21 : { va_stall : UInt[4], sa_stall : UInt[4]}
invalidate sinkIn_21.sa_stall[0]
invalidate sinkIn_21.sa_stall[1]
invalidate sinkIn_21.sa_stall[2]
invalidate sinkIn_21.sa_stall[3]
invalidate sinkIn_21.va_stall[0]
invalidate sinkIn_21.va_stall[1]
invalidate sinkIn_21.va_stall[2]
invalidate sinkIn_21.va_stall[3]
wire sinkIn_22 : { va_stall : UInt[3], sa_stall : UInt[3]}
invalidate sinkIn_22.sa_stall[0]
invalidate sinkIn_22.sa_stall[1]
invalidate sinkIn_22.sa_stall[2]
invalidate sinkIn_22.va_stall[0]
invalidate sinkIn_22.va_stall[1]
invalidate sinkIn_22.va_stall[2]
wire sinkIn_23 : { va_stall : UInt[5], sa_stall : UInt[5]}
invalidate sinkIn_23.sa_stall[0]
invalidate sinkIn_23.sa_stall[1]
invalidate sinkIn_23.sa_stall[2]
invalidate sinkIn_23.sa_stall[3]
invalidate sinkIn_23.sa_stall[4]
invalidate sinkIn_23.va_stall[0]
invalidate sinkIn_23.va_stall[1]
invalidate sinkIn_23.va_stall[2]
invalidate sinkIn_23.va_stall[3]
invalidate sinkIn_23.va_stall[4]
wire sinkIn_24 : { va_stall : UInt[5], sa_stall : UInt[5]}
invalidate sinkIn_24.sa_stall[0]
invalidate sinkIn_24.sa_stall[1]
invalidate sinkIn_24.sa_stall[2]
invalidate sinkIn_24.sa_stall[3]
invalidate sinkIn_24.sa_stall[4]
invalidate sinkIn_24.va_stall[0]
invalidate sinkIn_24.va_stall[1]
invalidate sinkIn_24.va_stall[2]
invalidate sinkIn_24.va_stall[3]
invalidate sinkIn_24.va_stall[4]
wire sinkIn_25 : { va_stall : UInt[4], sa_stall : UInt[4]}
invalidate sinkIn_25.sa_stall[0]
invalidate sinkIn_25.sa_stall[1]
invalidate sinkIn_25.sa_stall[2]
invalidate sinkIn_25.sa_stall[3]
invalidate sinkIn_25.va_stall[0]
invalidate sinkIn_25.va_stall[1]
invalidate sinkIn_25.va_stall[2]
invalidate sinkIn_25.va_stall[3]
wire sinkIn_26 : { va_stall : UInt[3], sa_stall : UInt[3]}
invalidate sinkIn_26.sa_stall[0]
invalidate sinkIn_26.sa_stall[1]
invalidate sinkIn_26.sa_stall[2]
invalidate sinkIn_26.va_stall[0]
invalidate sinkIn_26.va_stall[1]
invalidate sinkIn_26.va_stall[2]
wire sinkIn_27 : { va_stall : UInt[4], sa_stall : UInt[4]}
invalidate sinkIn_27.sa_stall[0]
invalidate sinkIn_27.sa_stall[1]
invalidate sinkIn_27.sa_stall[2]
invalidate sinkIn_27.sa_stall[3]
invalidate sinkIn_27.va_stall[0]
invalidate sinkIn_27.va_stall[1]
invalidate sinkIn_27.va_stall[2]
invalidate sinkIn_27.va_stall[3]
wire sinkIn_28 : { va_stall : UInt[2], sa_stall : UInt[2]}
invalidate sinkIn_28.sa_stall[0]
invalidate sinkIn_28.sa_stall[1]
invalidate sinkIn_28.va_stall[0]
invalidate sinkIn_28.va_stall[1]
connect router_sink_domain.auto.clock_in, clockSourceNodesOut
connect router_sink_domain_1.auto.clock_in, clockSourceNodesOut_1
connect router_sink_domain_2.auto.clock_in, clockSourceNodesOut_2
connect router_sink_domain_3.auto.clock_in, clockSourceNodesOut_3
connect router_sink_domain_4.auto.clock_in, clockSourceNodesOut_4
connect router_sink_domain_5.auto.clock_in, clockSourceNodesOut_5
connect router_sink_domain_6.auto.clock_in, clockSourceNodesOut_6
connect router_sink_domain_7.auto.clock_in, clockSourceNodesOut_7
connect router_sink_domain_8.auto.clock_in, clockSourceNodesOut_8
connect router_sink_domain_9.auto.clock_in, clockSourceNodesOut_9
connect router_sink_domain_10.auto.clock_in, clockSourceNodesOut_10
connect router_sink_domain_11.auto.clock_in, clockSourceNodesOut_11
connect router_sink_domain_12.auto.clock_in, clockSourceNodesOut_12
connect router_sink_domain_13.auto.clock_in, clockSourceNodesOut_13
connect router_sink_domain_14.auto.clock_in, clockSourceNodesOut_14
connect router_sink_domain_15.auto.clock_in, clockSourceNodesOut_15
connect router_sink_domain_16.auto.clock_in, clockSourceNodesOut_16
connect router_sink_domain_17.auto.clock_in, clockSourceNodesOut_17
connect router_sink_domain_18.auto.clock_in, clockSourceNodesOut_18
connect router_sink_domain_19.auto.clock_in, clockSourceNodesOut_19
connect router_sink_domain_20.auto.clock_in, clockSourceNodesOut_20
connect router_sink_domain_21.auto.clock_in, clockSourceNodesOut_21
connect router_sink_domain_22.auto.clock_in, clockSourceNodesOut_22
connect router_sink_domain_23.auto.clock_in, clockSourceNodesOut_23
connect router_sink_domain_24.auto.clock_in, clockSourceNodesOut_24
connect router_sink_domain_25.auto.clock_in, clockSourceNodesOut_25
connect router_sink_domain_26.auto.clock_in, clockSourceNodesOut_26
connect router_sink_domain_27.auto.clock_in, clockSourceNodesOut_27
connect router_sink_domain_28.auto.clock_in, clockSourceNodesOut_28
connect router_sink_domain_29.auto.clock_in, clockSourceNodesOut_29
connect router_sink_domain_30.auto.clock_in, clockSourceNodesOut_30
connect router_sink_domain_31.auto.clock_in, clockSourceNodesOut_31
connect router_sink_domain_16.auto.routers_dest_nodes_in_0, router_sink_domain.auto.routers_source_nodes_out
connect egressNodesIn.flit.bits, router_sink_domain.auto.routers_egress_nodes_out_0.flit.bits
connect egressNodesIn.flit.valid, router_sink_domain.auto.routers_egress_nodes_out_0.flit.valid
connect router_sink_domain.auto.routers_egress_nodes_out_0.flit.ready, egressNodesIn.flit.ready
connect egressNodesIn_1.flit.bits, router_sink_domain.auto.routers_egress_nodes_out_1.flit.bits
connect egressNodesIn_1.flit.valid, router_sink_domain.auto.routers_egress_nodes_out_1.flit.valid
connect router_sink_domain.auto.routers_egress_nodes_out_1.flit.ready, egressNodesIn_1.flit.ready
connect sinkIn, router_sink_domain.auto.routers_debug_out
connect router_sink_domain_17.auto.routers_dest_nodes_in_0, router_sink_domain_1.auto.routers_source_nodes_out
connect egressNodesIn_2.flit.bits, router_sink_domain_1.auto.routers_egress_nodes_out_0.flit.bits
connect egressNodesIn_2.flit.valid, router_sink_domain_1.auto.routers_egress_nodes_out_0.flit.valid
connect router_sink_domain_1.auto.routers_egress_nodes_out_0.flit.ready, egressNodesIn_2.flit.ready
connect egressNodesIn_3.flit.bits, router_sink_domain_1.auto.routers_egress_nodes_out_1.flit.bits
connect egressNodesIn_3.flit.valid, router_sink_domain_1.auto.routers_egress_nodes_out_1.flit.valid
connect router_sink_domain_1.auto.routers_egress_nodes_out_1.flit.ready, egressNodesIn_3.flit.ready
connect sinkIn_1, router_sink_domain_1.auto.routers_debug_out
connect router_sink_domain_18.auto.routers_dest_nodes_in_0, router_sink_domain_2.auto.routers_source_nodes_out
connect egressNodesIn_4.flit.bits, router_sink_domain_2.auto.routers_egress_nodes_out_0.flit.bits
connect egressNodesIn_4.flit.valid, router_sink_domain_2.auto.routers_egress_nodes_out_0.flit.valid
connect router_sink_domain_2.auto.routers_egress_nodes_out_0.flit.ready, egressNodesIn_4.flit.ready
connect egressNodesIn_5.flit.bits, router_sink_domain_2.auto.routers_egress_nodes_out_1.flit.bits
connect egressNodesIn_5.flit.valid, router_sink_domain_2.auto.routers_egress_nodes_out_1.flit.valid
connect router_sink_domain_2.auto.routers_egress_nodes_out_1.flit.ready, egressNodesIn_5.flit.ready
connect sinkIn_2, router_sink_domain_2.auto.routers_debug_out
connect router_sink_domain_19.auto.routers_dest_nodes_in_0, router_sink_domain_3.auto.routers_source_nodes_out
connect egressNodesIn_18.flit.bits, router_sink_domain_3.auto.routers_egress_nodes_out_0.flit.bits
connect egressNodesIn_18.flit.valid, router_sink_domain_3.auto.routers_egress_nodes_out_0.flit.valid
connect router_sink_domain_3.auto.routers_egress_nodes_out_0.flit.ready, egressNodesIn_18.flit.ready
connect egressNodesIn_19.flit.bits, router_sink_domain_3.auto.routers_egress_nodes_out_1.flit.bits
connect egressNodesIn_19.flit.valid, router_sink_domain_3.auto.routers_egress_nodes_out_1.flit.valid
connect router_sink_domain_3.auto.routers_egress_nodes_out_1.flit.ready, egressNodesIn_19.flit.ready
connect egressNodesIn_20.flit.bits, router_sink_domain_3.auto.routers_egress_nodes_out_2.flit.bits
connect egressNodesIn_20.flit.valid, router_sink_domain_3.auto.routers_egress_nodes_out_2.flit.valid
connect router_sink_domain_3.auto.routers_egress_nodes_out_2.flit.ready, egressNodesIn_20.flit.ready
connect sinkIn_3, router_sink_domain_3.auto.routers_debug_out
connect router_sink_domain_20.auto.routers_dest_nodes_in_0, router_sink_domain_4.auto.routers_source_nodes_out
connect egressNodesIn_6.flit.bits, router_sink_domain_4.auto.routers_egress_nodes_out_0.flit.bits
connect egressNodesIn_6.flit.valid, router_sink_domain_4.auto.routers_egress_nodes_out_0.flit.valid
connect router_sink_domain_4.auto.routers_egress_nodes_out_0.flit.ready, egressNodesIn_6.flit.ready
connect egressNodesIn_7.flit.bits, router_sink_domain_4.auto.routers_egress_nodes_out_1.flit.bits
connect egressNodesIn_7.flit.valid, router_sink_domain_4.auto.routers_egress_nodes_out_1.flit.valid
connect router_sink_domain_4.auto.routers_egress_nodes_out_1.flit.ready, egressNodesIn_7.flit.ready
connect sinkIn_4, router_sink_domain_4.auto.routers_debug_out
connect router_sink_domain_21.auto.routers_dest_nodes_in_0, router_sink_domain_5.auto.routers_source_nodes_out
connect egressNodesIn_21.flit.bits, router_sink_domain_5.auto.routers_egress_nodes_out_0.flit.bits
connect egressNodesIn_21.flit.valid, router_sink_domain_5.auto.routers_egress_nodes_out_0.flit.valid
connect router_sink_domain_5.auto.routers_egress_nodes_out_0.flit.ready, egressNodesIn_21.flit.ready
connect egressNodesIn_22.flit.bits, router_sink_domain_5.auto.routers_egress_nodes_out_1.flit.bits
connect egressNodesIn_22.flit.valid, router_sink_domain_5.auto.routers_egress_nodes_out_1.flit.valid
connect router_sink_domain_5.auto.routers_egress_nodes_out_1.flit.ready, egressNodesIn_22.flit.ready
connect egressNodesIn_23.flit.bits, router_sink_domain_5.auto.routers_egress_nodes_out_2.flit.bits
connect egressNodesIn_23.flit.valid, router_sink_domain_5.auto.routers_egress_nodes_out_2.flit.valid
connect router_sink_domain_5.auto.routers_egress_nodes_out_2.flit.ready, egressNodesIn_23.flit.ready
connect sinkIn_5, router_sink_domain_5.auto.routers_debug_out
connect router_sink_domain_22.auto.routers_dest_nodes_in_0, router_sink_domain_6.auto.routers_source_nodes_out
connect egressNodesIn_24.flit.bits, router_sink_domain_6.auto.routers_egress_nodes_out_0.flit.bits
connect egressNodesIn_24.flit.valid, router_sink_domain_6.auto.routers_egress_nodes_out_0.flit.valid
connect router_sink_domain_6.auto.routers_egress_nodes_out_0.flit.ready, egressNodesIn_24.flit.ready
connect egressNodesIn_25.flit.bits, router_sink_domain_6.auto.routers_egress_nodes_out_1.flit.bits
connect egressNodesIn_25.flit.valid, router_sink_domain_6.auto.routers_egress_nodes_out_1.flit.valid
connect router_sink_domain_6.auto.routers_egress_nodes_out_1.flit.ready, egressNodesIn_25.flit.ready
connect egressNodesIn_26.flit.bits, router_sink_domain_6.auto.routers_egress_nodes_out_2.flit.bits
connect egressNodesIn_26.flit.valid, router_sink_domain_6.auto.routers_egress_nodes_out_2.flit.valid
connect router_sink_domain_6.auto.routers_egress_nodes_out_2.flit.ready, egressNodesIn_26.flit.ready
connect sinkIn_6, router_sink_domain_6.auto.routers_debug_out
connect router_sink_domain_23.auto.routers_dest_nodes_in_0, router_sink_domain_7.auto.routers_source_nodes_out
connect egressNodesIn_8.flit.bits, router_sink_domain_7.auto.routers_egress_nodes_out_0.flit.bits
connect egressNodesIn_8.flit.valid, router_sink_domain_7.auto.routers_egress_nodes_out_0.flit.valid
connect router_sink_domain_7.auto.routers_egress_nodes_out_0.flit.ready, egressNodesIn_8.flit.ready
connect egressNodesIn_9.flit.bits, router_sink_domain_7.auto.routers_egress_nodes_out_1.flit.bits
connect egressNodesIn_9.flit.valid, router_sink_domain_7.auto.routers_egress_nodes_out_1.flit.valid
connect router_sink_domain_7.auto.routers_egress_nodes_out_1.flit.ready, egressNodesIn_9.flit.ready
connect sinkIn_7, router_sink_domain_7.auto.routers_debug_out
connect router_sink_domain_24.auto.routers_dest_nodes_in_0, router_sink_domain_8.auto.routers_source_nodes_out
connect egressNodesIn_10.flit.bits, router_sink_domain_8.auto.routers_egress_nodes_out_0.flit.bits
connect egressNodesIn_10.flit.valid, router_sink_domain_8.auto.routers_egress_nodes_out_0.flit.valid
connect router_sink_domain_8.auto.routers_egress_nodes_out_0.flit.ready, egressNodesIn_10.flit.ready
connect egressNodesIn_11.flit.bits, router_sink_domain_8.auto.routers_egress_nodes_out_1.flit.bits
connect egressNodesIn_11.flit.valid, router_sink_domain_8.auto.routers_egress_nodes_out_1.flit.valid
connect router_sink_domain_8.auto.routers_egress_nodes_out_1.flit.ready, egressNodesIn_11.flit.ready
connect sinkIn_8, router_sink_domain_8.auto.routers_debug_out
connect router_sink_domain_25.auto.routers_dest_nodes_in_0, router_sink_domain_9.auto.routers_source_nodes_out
connect egressNodesIn_27.flit.bits, router_sink_domain_9.auto.routers_egress_nodes_out_0.flit.bits
connect egressNodesIn_27.flit.valid, router_sink_domain_9.auto.routers_egress_nodes_out_0.flit.valid
connect router_sink_domain_9.auto.routers_egress_nodes_out_0.flit.ready, egressNodesIn_27.flit.ready
connect egressNodesIn_28.flit.bits, router_sink_domain_9.auto.routers_egress_nodes_out_1.flit.bits
connect egressNodesIn_28.flit.valid, router_sink_domain_9.auto.routers_egress_nodes_out_1.flit.valid
connect router_sink_domain_9.auto.routers_egress_nodes_out_1.flit.ready, egressNodesIn_28.flit.ready
connect egressNodesIn_29.flit.bits, router_sink_domain_9.auto.routers_egress_nodes_out_2.flit.bits
connect egressNodesIn_29.flit.valid, router_sink_domain_9.auto.routers_egress_nodes_out_2.flit.valid
connect router_sink_domain_9.auto.routers_egress_nodes_out_2.flit.ready, egressNodesIn_29.flit.ready
connect sinkIn_9, router_sink_domain_9.auto.routers_debug_out
connect router_sink_domain_26.auto.routers_dest_nodes_in_0, router_sink_domain_10.auto.routers_source_nodes_out
connect egressNodesIn_30.flit.bits, router_sink_domain_10.auto.routers_egress_nodes_out_0.flit.bits
connect egressNodesIn_30.flit.valid, router_sink_domain_10.auto.routers_egress_nodes_out_0.flit.valid
connect router_sink_domain_10.auto.routers_egress_nodes_out_0.flit.ready, egressNodesIn_30.flit.ready
connect egressNodesIn_31.flit.bits, router_sink_domain_10.auto.routers_egress_nodes_out_1.flit.bits
connect egressNodesIn_31.flit.valid, router_sink_domain_10.auto.routers_egress_nodes_out_1.flit.valid
connect router_sink_domain_10.auto.routers_egress_nodes_out_1.flit.ready, egressNodesIn_31.flit.ready
connect egressNodesIn_32.flit.bits, router_sink_domain_10.auto.routers_egress_nodes_out_2.flit.bits
connect egressNodesIn_32.flit.valid, router_sink_domain_10.auto.routers_egress_nodes_out_2.flit.valid
connect router_sink_domain_10.auto.routers_egress_nodes_out_2.flit.ready, egressNodesIn_32.flit.ready
connect sinkIn_10, router_sink_domain_10.auto.routers_debug_out
connect router_sink_domain_27.auto.routers_dest_nodes_in_0, router_sink_domain_11.auto.routers_source_nodes_out
connect egressNodesIn_12.flit.bits, router_sink_domain_11.auto.routers_egress_nodes_out_0.flit.bits
connect egressNodesIn_12.flit.valid, router_sink_domain_11.auto.routers_egress_nodes_out_0.flit.valid
connect router_sink_domain_11.auto.routers_egress_nodes_out_0.flit.ready, egressNodesIn_12.flit.ready
connect egressNodesIn_13.flit.bits, router_sink_domain_11.auto.routers_egress_nodes_out_1.flit.bits
connect egressNodesIn_13.flit.valid, router_sink_domain_11.auto.routers_egress_nodes_out_1.flit.valid
connect router_sink_domain_11.auto.routers_egress_nodes_out_1.flit.ready, egressNodesIn_13.flit.ready
connect sinkIn_11, router_sink_domain_11.auto.routers_debug_out
connect router_sink_domain_29.auto.routers_dest_nodes_in_0, router_sink_domain_13.auto.routers_source_nodes_out
connect egressNodesIn_14.flit.bits, router_sink_domain_13.auto.routers_egress_nodes_out_0.flit.bits
connect egressNodesIn_14.flit.valid, router_sink_domain_13.auto.routers_egress_nodes_out_0.flit.valid
connect router_sink_domain_13.auto.routers_egress_nodes_out_0.flit.ready, egressNodesIn_14.flit.ready
connect egressNodesIn_15.flit.bits, router_sink_domain_13.auto.routers_egress_nodes_out_1.flit.bits
connect egressNodesIn_15.flit.valid, router_sink_domain_13.auto.routers_egress_nodes_out_1.flit.valid
connect router_sink_domain_13.auto.routers_egress_nodes_out_1.flit.ready, egressNodesIn_15.flit.ready
connect sinkIn_12, router_sink_domain_13.auto.routers_debug_out
connect router_sink_domain_30.auto.routers_dest_nodes_in_0, router_sink_domain_14.auto.routers_source_nodes_out
connect egressNodesIn_16.flit.bits, router_sink_domain_14.auto.routers_egress_nodes_out_0.flit.bits
connect egressNodesIn_16.flit.valid, router_sink_domain_14.auto.routers_egress_nodes_out_0.flit.valid
connect router_sink_domain_14.auto.routers_egress_nodes_out_0.flit.ready, egressNodesIn_16.flit.ready
connect egressNodesIn_17.flit.bits, router_sink_domain_14.auto.routers_egress_nodes_out_1.flit.bits
connect egressNodesIn_17.flit.valid, router_sink_domain_14.auto.routers_egress_nodes_out_1.flit.valid
connect router_sink_domain_14.auto.routers_egress_nodes_out_1.flit.ready, egressNodesIn_17.flit.ready
connect sinkIn_13, router_sink_domain_14.auto.routers_debug_out
connect router_sink_domain.auto.routers_dest_nodes_in, router_sink_domain_16.auto.routers_source_nodes_out_0
connect router_sink_domain_17.auto.routers_dest_nodes_in_1, router_sink_domain_16.auto.routers_source_nodes_out_1
connect router_sink_domain_20.auto.routers_dest_nodes_in_1, router_sink_domain_16.auto.routers_source_nodes_out_2
connect sinkIn_14, router_sink_domain_16.auto.routers_debug_out
connect router_sink_domain_1.auto.routers_dest_nodes_in, router_sink_domain_17.auto.routers_source_nodes_out_0
connect router_sink_domain_16.auto.routers_dest_nodes_in_1, router_sink_domain_17.auto.routers_source_nodes_out_1
connect router_sink_domain_18.auto.routers_dest_nodes_in_1, router_sink_domain_17.auto.routers_source_nodes_out_2
connect router_sink_domain_21.auto.routers_dest_nodes_in_1, router_sink_domain_17.auto.routers_source_nodes_out_3
connect sinkIn_15, router_sink_domain_17.auto.routers_debug_out
connect router_sink_domain_2.auto.routers_dest_nodes_in, router_sink_domain_18.auto.routers_source_nodes_out_0
connect router_sink_domain_17.auto.routers_dest_nodes_in_2, router_sink_domain_18.auto.routers_source_nodes_out_1
connect router_sink_domain_19.auto.routers_dest_nodes_in_1, router_sink_domain_18.auto.routers_source_nodes_out_2
connect router_sink_domain_22.auto.routers_dest_nodes_in_1, router_sink_domain_18.auto.routers_source_nodes_out_3
connect sinkIn_16, router_sink_domain_18.auto.routers_debug_out
connect router_sink_domain_3.auto.routers_dest_nodes_in, router_sink_domain_19.auto.routers_source_nodes_out_0
connect router_sink_domain_18.auto.routers_dest_nodes_in_2, router_sink_domain_19.auto.routers_source_nodes_out_1
connect router_sink_domain_23.auto.routers_dest_nodes_in_1, router_sink_domain_19.auto.routers_source_nodes_out_2
connect sinkIn_17, router_sink_domain_19.auto.routers_debug_out
connect router_sink_domain_4.auto.routers_dest_nodes_in, router_sink_domain_20.auto.routers_source_nodes_out_0
connect router_sink_domain_16.auto.routers_dest_nodes_in_2, router_sink_domain_20.auto.routers_source_nodes_out_1
connect router_sink_domain_21.auto.routers_dest_nodes_in_2, router_sink_domain_20.auto.routers_source_nodes_out_2
connect router_sink_domain_24.auto.routers_dest_nodes_in_1, router_sink_domain_20.auto.routers_source_nodes_out_3
connect sinkIn_18, router_sink_domain_20.auto.routers_debug_out
connect router_sink_domain_5.auto.routers_dest_nodes_in, router_sink_domain_21.auto.routers_source_nodes_out_0
connect router_sink_domain_17.auto.routers_dest_nodes_in_3, router_sink_domain_21.auto.routers_source_nodes_out_1
connect router_sink_domain_20.auto.routers_dest_nodes_in_2, router_sink_domain_21.auto.routers_source_nodes_out_2
connect router_sink_domain_22.auto.routers_dest_nodes_in_2, router_sink_domain_21.auto.routers_source_nodes_out_3
connect router_sink_domain_25.auto.routers_dest_nodes_in_1, router_sink_domain_21.auto.routers_source_nodes_out_4
connect sinkIn_19, router_sink_domain_21.auto.routers_debug_out
connect router_sink_domain_6.auto.routers_dest_nodes_in, router_sink_domain_22.auto.routers_source_nodes_out_0
connect router_sink_domain_18.auto.routers_dest_nodes_in_3, router_sink_domain_22.auto.routers_source_nodes_out_1
connect router_sink_domain_21.auto.routers_dest_nodes_in_3, router_sink_domain_22.auto.routers_source_nodes_out_2
connect router_sink_domain_23.auto.routers_dest_nodes_in_2, router_sink_domain_22.auto.routers_source_nodes_out_3
connect router_sink_domain_26.auto.routers_dest_nodes_in_1, router_sink_domain_22.auto.routers_source_nodes_out_4
connect sinkIn_20, router_sink_domain_22.auto.routers_debug_out
connect router_sink_domain_7.auto.routers_dest_nodes_in, router_sink_domain_23.auto.routers_source_nodes_out_0
connect router_sink_domain_19.auto.routers_dest_nodes_in_2, router_sink_domain_23.auto.routers_source_nodes_out_1
connect router_sink_domain_22.auto.routers_dest_nodes_in_3, router_sink_domain_23.auto.routers_source_nodes_out_2
connect router_sink_domain_27.auto.routers_dest_nodes_in_1, router_sink_domain_23.auto.routers_source_nodes_out_3
connect sinkIn_21, router_sink_domain_23.auto.routers_debug_out
connect router_sink_domain_8.auto.routers_dest_nodes_in, router_sink_domain_24.auto.routers_source_nodes_out_0
connect router_sink_domain_20.auto.routers_dest_nodes_in_3, router_sink_domain_24.auto.routers_source_nodes_out_1
connect router_sink_domain_25.auto.routers_dest_nodes_in_2, router_sink_domain_24.auto.routers_source_nodes_out_2
connect sinkIn_22, router_sink_domain_24.auto.routers_debug_out
connect router_sink_domain_9.auto.routers_dest_nodes_in, router_sink_domain_25.auto.routers_source_nodes_out_0
connect router_sink_domain_21.auto.routers_dest_nodes_in_4, router_sink_domain_25.auto.routers_source_nodes_out_1
connect router_sink_domain_24.auto.routers_dest_nodes_in_2, router_sink_domain_25.auto.routers_source_nodes_out_2
connect router_sink_domain_26.auto.routers_dest_nodes_in_2, router_sink_domain_25.auto.routers_source_nodes_out_3
connect router_sink_domain_29.auto.routers_dest_nodes_in_1, router_sink_domain_25.auto.routers_source_nodes_out_4
connect sinkIn_23, router_sink_domain_25.auto.routers_debug_out
connect router_sink_domain_10.auto.routers_dest_nodes_in, router_sink_domain_26.auto.routers_source_nodes_out_0
connect router_sink_domain_22.auto.routers_dest_nodes_in_4, router_sink_domain_26.auto.routers_source_nodes_out_1
connect router_sink_domain_25.auto.routers_dest_nodes_in_3, router_sink_domain_26.auto.routers_source_nodes_out_2
connect router_sink_domain_27.auto.routers_dest_nodes_in_2, router_sink_domain_26.auto.routers_source_nodes_out_3
connect router_sink_domain_30.auto.routers_dest_nodes_in_1, router_sink_domain_26.auto.routers_source_nodes_out_4
connect sinkIn_24, router_sink_domain_26.auto.routers_debug_out
connect router_sink_domain_11.auto.routers_dest_nodes_in, router_sink_domain_27.auto.routers_source_nodes_out_0
connect router_sink_domain_23.auto.routers_dest_nodes_in_3, router_sink_domain_27.auto.routers_source_nodes_out_1
connect router_sink_domain_26.auto.routers_dest_nodes_in_3, router_sink_domain_27.auto.routers_source_nodes_out_2
connect router_sink_domain_31.auto.routers_dest_nodes_in_0, router_sink_domain_27.auto.routers_source_nodes_out_3
connect sinkIn_25, router_sink_domain_27.auto.routers_debug_out
connect router_sink_domain_13.auto.routers_dest_nodes_in, router_sink_domain_29.auto.routers_source_nodes_out_0
connect router_sink_domain_25.auto.routers_dest_nodes_in_4, router_sink_domain_29.auto.routers_source_nodes_out_1
connect router_sink_domain_30.auto.routers_dest_nodes_in_2, router_sink_domain_29.auto.routers_source_nodes_out_2
connect sinkIn_26, router_sink_domain_29.auto.routers_debug_out
connect router_sink_domain_14.auto.routers_dest_nodes_in, router_sink_domain_30.auto.routers_source_nodes_out_0
connect router_sink_domain_26.auto.routers_dest_nodes_in_4, router_sink_domain_30.auto.routers_source_nodes_out_1
connect router_sink_domain_29.auto.routers_dest_nodes_in_2, router_sink_domain_30.auto.routers_source_nodes_out_2
connect router_sink_domain_31.auto.routers_dest_nodes_in_1, router_sink_domain_30.auto.routers_source_nodes_out_3
connect sinkIn_27, router_sink_domain_30.auto.routers_debug_out
connect router_sink_domain_27.auto.routers_dest_nodes_in_3, router_sink_domain_31.auto.routers_source_nodes_out_0
connect router_sink_domain_30.auto.routers_dest_nodes_in_3, router_sink_domain_31.auto.routers_source_nodes_out_1
connect sinkIn_28, router_sink_domain_31.auto.routers_debug_out
connect router_sink_domain.auto.routers_ingress_nodes_in_0, ingressNodesOut
connect router_sink_domain.auto.routers_ingress_nodes_in_1, ingressNodesOut_1
connect router_sink_domain.auto.routers_ingress_nodes_in_2, ingressNodesOut_2
connect router_sink_domain_1.auto.routers_ingress_nodes_in_0, ingressNodesOut_3
connect router_sink_domain_1.auto.routers_ingress_nodes_in_1, ingressNodesOut_4
connect router_sink_domain_1.auto.routers_ingress_nodes_in_2, ingressNodesOut_5
connect router_sink_domain_2.auto.routers_ingress_nodes_in_0, ingressNodesOut_6
connect router_sink_domain_2.auto.routers_ingress_nodes_in_1, ingressNodesOut_7
connect router_sink_domain_2.auto.routers_ingress_nodes_in_2, ingressNodesOut_8
connect router_sink_domain_4.auto.routers_ingress_nodes_in_0, ingressNodesOut_9
connect router_sink_domain_4.auto.routers_ingress_nodes_in_1, ingressNodesOut_10
connect router_sink_domain_4.auto.routers_ingress_nodes_in_2, ingressNodesOut_11
connect router_sink_domain_7.auto.routers_ingress_nodes_in_0, ingressNodesOut_12
connect router_sink_domain_7.auto.routers_ingress_nodes_in_1, ingressNodesOut_13
connect router_sink_domain_7.auto.routers_ingress_nodes_in_2, ingressNodesOut_14
connect router_sink_domain_8.auto.routers_ingress_nodes_in_0, ingressNodesOut_15
connect router_sink_domain_8.auto.routers_ingress_nodes_in_1, ingressNodesOut_16
connect router_sink_domain_8.auto.routers_ingress_nodes_in_2, ingressNodesOut_17
connect router_sink_domain_11.auto.routers_ingress_nodes_in_0, ingressNodesOut_18
connect router_sink_domain_11.auto.routers_ingress_nodes_in_1, ingressNodesOut_19
connect router_sink_domain_11.auto.routers_ingress_nodes_in_2, ingressNodesOut_20
connect router_sink_domain_13.auto.routers_ingress_nodes_in_0, ingressNodesOut_21
connect router_sink_domain_13.auto.routers_ingress_nodes_in_1, ingressNodesOut_22
connect router_sink_domain_13.auto.routers_ingress_nodes_in_2, ingressNodesOut_23
connect router_sink_domain_14.auto.routers_ingress_nodes_in_0, ingressNodesOut_24
connect router_sink_domain_14.auto.routers_ingress_nodes_in_1, ingressNodesOut_25
connect router_sink_domain_14.auto.routers_ingress_nodes_in_2, ingressNodesOut_26
connect router_sink_domain_3.auto.routers_ingress_nodes_in_0, ingressNodesOut_27
connect router_sink_domain_3.auto.routers_ingress_nodes_in_1, ingressNodesOut_28
connect router_sink_domain_5.auto.routers_ingress_nodes_in_0, ingressNodesOut_29
connect router_sink_domain_5.auto.routers_ingress_nodes_in_1, ingressNodesOut_30
connect router_sink_domain_6.auto.routers_ingress_nodes_in_0, ingressNodesOut_31
connect router_sink_domain_6.auto.routers_ingress_nodes_in_1, ingressNodesOut_32
connect router_sink_domain_9.auto.routers_ingress_nodes_in_0, ingressNodesOut_33
connect router_sink_domain_9.auto.routers_ingress_nodes_in_1, ingressNodesOut_34
connect router_sink_domain_10.auto.routers_ingress_nodes_in_0, ingressNodesOut_35
connect router_sink_domain_10.auto.routers_ingress_nodes_in_1, ingressNodesOut_36
connect ingressNodesOut, io.ingress.`0`
connect ingressNodesOut_1, io.ingress.`1`
connect ingressNodesOut_2, io.ingress.`2`
connect ingressNodesOut_3, io.ingress.`3`
connect ingressNodesOut_4, io.ingress.`4`
connect ingressNodesOut_5, io.ingress.`5`
connect ingressNodesOut_6, io.ingress.`6`
connect ingressNodesOut_7, io.ingress.`7`
connect ingressNodesOut_8, io.ingress.`8`
connect ingressNodesOut_9, io.ingress.`9`
connect ingressNodesOut_10, io.ingress.`10`
connect ingressNodesOut_11, io.ingress.`11`
connect ingressNodesOut_12, io.ingress.`12`
connect ingressNodesOut_13, io.ingress.`13`
connect ingressNodesOut_14, io.ingress.`14`
connect ingressNodesOut_15, io.ingress.`15`
connect ingressNodesOut_16, io.ingress.`16`
connect ingressNodesOut_17, io.ingress.`17`
connect ingressNodesOut_18, io.ingress.`18`
connect ingressNodesOut_19, io.ingress.`19`
connect ingressNodesOut_20, io.ingress.`20`
connect ingressNodesOut_21, io.ingress.`21`
connect ingressNodesOut_22, io.ingress.`22`
connect ingressNodesOut_23, io.ingress.`23`
connect ingressNodesOut_24, io.ingress.`24`
connect ingressNodesOut_25, io.ingress.`25`
connect ingressNodesOut_26, io.ingress.`26`
connect ingressNodesOut_27, io.ingress.`27`
connect ingressNodesOut_28, io.ingress.`28`
connect ingressNodesOut_29, io.ingress.`29`
connect ingressNodesOut_30, io.ingress.`30`
connect ingressNodesOut_31, io.ingress.`31`
connect ingressNodesOut_32, io.ingress.`32`
connect ingressNodesOut_33, io.ingress.`33`
connect ingressNodesOut_34, io.ingress.`34`
connect ingressNodesOut_35, io.ingress.`35`
connect ingressNodesOut_36, io.ingress.`36`
connect io.egress.`0`, egressNodesIn
connect io.egress.`1`, egressNodesIn_1
connect io.egress.`2`, egressNodesIn_2
connect io.egress.`3`, egressNodesIn_3
connect io.egress.`4`, egressNodesIn_4
connect io.egress.`5`, egressNodesIn_5
connect io.egress.`6`, egressNodesIn_6
connect io.egress.`7`, egressNodesIn_7
connect io.egress.`8`, egressNodesIn_8
connect io.egress.`9`, egressNodesIn_9
connect io.egress.`10`, egressNodesIn_10
connect io.egress.`11`, egressNodesIn_11
connect io.egress.`12`, egressNodesIn_12
connect io.egress.`13`, egressNodesIn_13
connect io.egress.`14`, egressNodesIn_14
connect io.egress.`15`, egressNodesIn_15
connect io.egress.`16`, egressNodesIn_16
connect io.egress.`17`, egressNodesIn_17
connect io.egress.`18`, egressNodesIn_18
connect io.egress.`19`, egressNodesIn_19
connect io.egress.`20`, egressNodesIn_20
connect io.egress.`21`, egressNodesIn_21
connect io.egress.`22`, egressNodesIn_22
connect io.egress.`23`, egressNodesIn_23
connect io.egress.`24`, egressNodesIn_24
connect io.egress.`25`, egressNodesIn_25
connect io.egress.`26`, egressNodesIn_26
connect io.egress.`27`, egressNodesIn_27
connect io.egress.`28`, egressNodesIn_28
connect io.egress.`29`, egressNodesIn_29
connect io.egress.`30`, egressNodesIn_30
connect io.egress.`31`, egressNodesIn_31
connect io.egress.`32`, egressNodesIn_32
connect clockSourceNodesOut, io.router_clocks[0]
connect clockSourceNodesOut_1, io.router_clocks[1]
connect clockSourceNodesOut_2, io.router_clocks[2]
connect clockSourceNodesOut_3, io.router_clocks[3]
connect clockSourceNodesOut_4, io.router_clocks[4]
connect clockSourceNodesOut_5, io.router_clocks[5]
connect clockSourceNodesOut_6, io.router_clocks[6]
connect clockSourceNodesOut_7, io.router_clocks[7]
connect clockSourceNodesOut_8, io.router_clocks[8]
connect clockSourceNodesOut_9, io.router_clocks[9]
connect clockSourceNodesOut_10, io.router_clocks[10]
connect clockSourceNodesOut_11, io.router_clocks[11]
connect clockSourceNodesOut_12, io.router_clocks[12]
connect clockSourceNodesOut_13, io.router_clocks[13]
connect clockSourceNodesOut_14, io.router_clocks[14]
connect clockSourceNodesOut_15, io.router_clocks[15]
connect clockSourceNodesOut_16, io.router_clocks[16]
connect clockSourceNodesOut_17, io.router_clocks[17]
connect clockSourceNodesOut_18, io.router_clocks[18]
connect clockSourceNodesOut_19, io.router_clocks[19]
connect clockSourceNodesOut_20, io.router_clocks[20]
connect clockSourceNodesOut_21, io.router_clocks[21]
connect clockSourceNodesOut_22, io.router_clocks[22]
connect clockSourceNodesOut_23, io.router_clocks[23]
connect clockSourceNodesOut_24, io.router_clocks[24]
connect clockSourceNodesOut_25, io.router_clocks[25]
connect clockSourceNodesOut_26, io.router_clocks[26]
connect clockSourceNodesOut_27, io.router_clocks[27]
connect clockSourceNodesOut_28, io.router_clocks[28]
connect clockSourceNodesOut_29, io.router_clocks[29]
connect clockSourceNodesOut_30, io.router_clocks[30]
connect clockSourceNodesOut_31, io.router_clocks[31]
regreset debug_va_stall_ctr : UInt<64>, clock, reset, UInt<64>(0h0)
regreset debug_sa_stall_ctr : UInt<64>, clock, reset, UInt<64>(0h0)
node _debug_any_stall_ctr_T = add(debug_va_stall_ctr, debug_sa_stall_ctr)
node debug_any_stall_ctr = tail(_debug_any_stall_ctr_T, 1)
node _debug_va_stall_ctr_T = add(sinkIn.va_stall[0], sinkIn.va_stall[1])
node _debug_va_stall_ctr_T_1 = tail(_debug_va_stall_ctr_T, 1)
node _debug_va_stall_ctr_T_2 = add(_debug_va_stall_ctr_T_1, sinkIn.va_stall[2])
node _debug_va_stall_ctr_T_3 = tail(_debug_va_stall_ctr_T_2, 1)
node _debug_va_stall_ctr_T_4 = add(_debug_va_stall_ctr_T_3, sinkIn.va_stall[3])
node _debug_va_stall_ctr_T_5 = tail(_debug_va_stall_ctr_T_4, 1)
node _debug_va_stall_ctr_T_6 = add(sinkIn_1.va_stall[0], sinkIn_1.va_stall[1])
node _debug_va_stall_ctr_T_7 = tail(_debug_va_stall_ctr_T_6, 1)
node _debug_va_stall_ctr_T_8 = add(_debug_va_stall_ctr_T_7, sinkIn_1.va_stall[2])
node _debug_va_stall_ctr_T_9 = tail(_debug_va_stall_ctr_T_8, 1)
node _debug_va_stall_ctr_T_10 = add(_debug_va_stall_ctr_T_9, sinkIn_1.va_stall[3])
node _debug_va_stall_ctr_T_11 = tail(_debug_va_stall_ctr_T_10, 1)
node _debug_va_stall_ctr_T_12 = add(sinkIn_2.va_stall[0], sinkIn_2.va_stall[1])
node _debug_va_stall_ctr_T_13 = tail(_debug_va_stall_ctr_T_12, 1)
node _debug_va_stall_ctr_T_14 = add(_debug_va_stall_ctr_T_13, sinkIn_2.va_stall[2])
node _debug_va_stall_ctr_T_15 = tail(_debug_va_stall_ctr_T_14, 1)
node _debug_va_stall_ctr_T_16 = add(_debug_va_stall_ctr_T_15, sinkIn_2.va_stall[3])
node _debug_va_stall_ctr_T_17 = tail(_debug_va_stall_ctr_T_16, 1)
node _debug_va_stall_ctr_T_18 = add(sinkIn_3.va_stall[0], sinkIn_3.va_stall[1])
node _debug_va_stall_ctr_T_19 = tail(_debug_va_stall_ctr_T_18, 1)
node _debug_va_stall_ctr_T_20 = add(_debug_va_stall_ctr_T_19, sinkIn_3.va_stall[2])
node _debug_va_stall_ctr_T_21 = tail(_debug_va_stall_ctr_T_20, 1)
node _debug_va_stall_ctr_T_22 = add(sinkIn_4.va_stall[0], sinkIn_4.va_stall[1])
node _debug_va_stall_ctr_T_23 = tail(_debug_va_stall_ctr_T_22, 1)
node _debug_va_stall_ctr_T_24 = add(_debug_va_stall_ctr_T_23, sinkIn_4.va_stall[2])
node _debug_va_stall_ctr_T_25 = tail(_debug_va_stall_ctr_T_24, 1)
node _debug_va_stall_ctr_T_26 = add(_debug_va_stall_ctr_T_25, sinkIn_4.va_stall[3])
node _debug_va_stall_ctr_T_27 = tail(_debug_va_stall_ctr_T_26, 1)
node _debug_va_stall_ctr_T_28 = add(sinkIn_5.va_stall[0], sinkIn_5.va_stall[1])
node _debug_va_stall_ctr_T_29 = tail(_debug_va_stall_ctr_T_28, 1)
node _debug_va_stall_ctr_T_30 = add(_debug_va_stall_ctr_T_29, sinkIn_5.va_stall[2])
node _debug_va_stall_ctr_T_31 = tail(_debug_va_stall_ctr_T_30, 1)
node _debug_va_stall_ctr_T_32 = add(sinkIn_6.va_stall[0], sinkIn_6.va_stall[1])
node _debug_va_stall_ctr_T_33 = tail(_debug_va_stall_ctr_T_32, 1)
node _debug_va_stall_ctr_T_34 = add(_debug_va_stall_ctr_T_33, sinkIn_6.va_stall[2])
node _debug_va_stall_ctr_T_35 = tail(_debug_va_stall_ctr_T_34, 1)
node _debug_va_stall_ctr_T_36 = add(sinkIn_7.va_stall[0], sinkIn_7.va_stall[1])
node _debug_va_stall_ctr_T_37 = tail(_debug_va_stall_ctr_T_36, 1)
node _debug_va_stall_ctr_T_38 = add(_debug_va_stall_ctr_T_37, sinkIn_7.va_stall[2])
node _debug_va_stall_ctr_T_39 = tail(_debug_va_stall_ctr_T_38, 1)
node _debug_va_stall_ctr_T_40 = add(_debug_va_stall_ctr_T_39, sinkIn_7.va_stall[3])
node _debug_va_stall_ctr_T_41 = tail(_debug_va_stall_ctr_T_40, 1)
node _debug_va_stall_ctr_T_42 = add(sinkIn_8.va_stall[0], sinkIn_8.va_stall[1])
node _debug_va_stall_ctr_T_43 = tail(_debug_va_stall_ctr_T_42, 1)
node _debug_va_stall_ctr_T_44 = add(_debug_va_stall_ctr_T_43, sinkIn_8.va_stall[2])
node _debug_va_stall_ctr_T_45 = tail(_debug_va_stall_ctr_T_44, 1)
node _debug_va_stall_ctr_T_46 = add(_debug_va_stall_ctr_T_45, sinkIn_8.va_stall[3])
node _debug_va_stall_ctr_T_47 = tail(_debug_va_stall_ctr_T_46, 1)
node _debug_va_stall_ctr_T_48 = add(sinkIn_9.va_stall[0], sinkIn_9.va_stall[1])
node _debug_va_stall_ctr_T_49 = tail(_debug_va_stall_ctr_T_48, 1)
node _debug_va_stall_ctr_T_50 = add(_debug_va_stall_ctr_T_49, sinkIn_9.va_stall[2])
node _debug_va_stall_ctr_T_51 = tail(_debug_va_stall_ctr_T_50, 1)
node _debug_va_stall_ctr_T_52 = add(sinkIn_10.va_stall[0], sinkIn_10.va_stall[1])
node _debug_va_stall_ctr_T_53 = tail(_debug_va_stall_ctr_T_52, 1)
node _debug_va_stall_ctr_T_54 = add(_debug_va_stall_ctr_T_53, sinkIn_10.va_stall[2])
node _debug_va_stall_ctr_T_55 = tail(_debug_va_stall_ctr_T_54, 1)
node _debug_va_stall_ctr_T_56 = add(sinkIn_11.va_stall[0], sinkIn_11.va_stall[1])
node _debug_va_stall_ctr_T_57 = tail(_debug_va_stall_ctr_T_56, 1)
node _debug_va_stall_ctr_T_58 = add(_debug_va_stall_ctr_T_57, sinkIn_11.va_stall[2])
node _debug_va_stall_ctr_T_59 = tail(_debug_va_stall_ctr_T_58, 1)
node _debug_va_stall_ctr_T_60 = add(_debug_va_stall_ctr_T_59, sinkIn_11.va_stall[3])
node _debug_va_stall_ctr_T_61 = tail(_debug_va_stall_ctr_T_60, 1)
node _debug_va_stall_ctr_T_62 = add(sinkIn_12.va_stall[0], sinkIn_12.va_stall[1])
node _debug_va_stall_ctr_T_63 = tail(_debug_va_stall_ctr_T_62, 1)
node _debug_va_stall_ctr_T_64 = add(_debug_va_stall_ctr_T_63, sinkIn_12.va_stall[2])
node _debug_va_stall_ctr_T_65 = tail(_debug_va_stall_ctr_T_64, 1)
node _debug_va_stall_ctr_T_66 = add(_debug_va_stall_ctr_T_65, sinkIn_12.va_stall[3])
node _debug_va_stall_ctr_T_67 = tail(_debug_va_stall_ctr_T_66, 1)
node _debug_va_stall_ctr_T_68 = add(sinkIn_13.va_stall[0], sinkIn_13.va_stall[1])
node _debug_va_stall_ctr_T_69 = tail(_debug_va_stall_ctr_T_68, 1)
node _debug_va_stall_ctr_T_70 = add(_debug_va_stall_ctr_T_69, sinkIn_13.va_stall[2])
node _debug_va_stall_ctr_T_71 = tail(_debug_va_stall_ctr_T_70, 1)
node _debug_va_stall_ctr_T_72 = add(_debug_va_stall_ctr_T_71, sinkIn_13.va_stall[3])
node _debug_va_stall_ctr_T_73 = tail(_debug_va_stall_ctr_T_72, 1)
node _debug_va_stall_ctr_T_74 = add(sinkIn_14.va_stall[0], sinkIn_14.va_stall[1])
node _debug_va_stall_ctr_T_75 = tail(_debug_va_stall_ctr_T_74, 1)
node _debug_va_stall_ctr_T_76 = add(_debug_va_stall_ctr_T_75, sinkIn_14.va_stall[2])
node _debug_va_stall_ctr_T_77 = tail(_debug_va_stall_ctr_T_76, 1)
node _debug_va_stall_ctr_T_78 = add(sinkIn_15.va_stall[0], sinkIn_15.va_stall[1])
node _debug_va_stall_ctr_T_79 = tail(_debug_va_stall_ctr_T_78, 1)
node _debug_va_stall_ctr_T_80 = add(_debug_va_stall_ctr_T_79, sinkIn_15.va_stall[2])
node _debug_va_stall_ctr_T_81 = tail(_debug_va_stall_ctr_T_80, 1)
node _debug_va_stall_ctr_T_82 = add(_debug_va_stall_ctr_T_81, sinkIn_15.va_stall[3])
node _debug_va_stall_ctr_T_83 = tail(_debug_va_stall_ctr_T_82, 1)
node _debug_va_stall_ctr_T_84 = add(sinkIn_16.va_stall[0], sinkIn_16.va_stall[1])
node _debug_va_stall_ctr_T_85 = tail(_debug_va_stall_ctr_T_84, 1)
node _debug_va_stall_ctr_T_86 = add(_debug_va_stall_ctr_T_85, sinkIn_16.va_stall[2])
node _debug_va_stall_ctr_T_87 = tail(_debug_va_stall_ctr_T_86, 1)
node _debug_va_stall_ctr_T_88 = add(_debug_va_stall_ctr_T_87, sinkIn_16.va_stall[3])
node _debug_va_stall_ctr_T_89 = tail(_debug_va_stall_ctr_T_88, 1)
node _debug_va_stall_ctr_T_90 = add(sinkIn_17.va_stall[0], sinkIn_17.va_stall[1])
node _debug_va_stall_ctr_T_91 = tail(_debug_va_stall_ctr_T_90, 1)
node _debug_va_stall_ctr_T_92 = add(_debug_va_stall_ctr_T_91, sinkIn_17.va_stall[2])
node _debug_va_stall_ctr_T_93 = tail(_debug_va_stall_ctr_T_92, 1)
node _debug_va_stall_ctr_T_94 = add(sinkIn_18.va_stall[0], sinkIn_18.va_stall[1])
node _debug_va_stall_ctr_T_95 = tail(_debug_va_stall_ctr_T_94, 1)
node _debug_va_stall_ctr_T_96 = add(_debug_va_stall_ctr_T_95, sinkIn_18.va_stall[2])
node _debug_va_stall_ctr_T_97 = tail(_debug_va_stall_ctr_T_96, 1)
node _debug_va_stall_ctr_T_98 = add(_debug_va_stall_ctr_T_97, sinkIn_18.va_stall[3])
node _debug_va_stall_ctr_T_99 = tail(_debug_va_stall_ctr_T_98, 1)
node _debug_va_stall_ctr_T_100 = add(sinkIn_19.va_stall[0], sinkIn_19.va_stall[1])
node _debug_va_stall_ctr_T_101 = tail(_debug_va_stall_ctr_T_100, 1)
node _debug_va_stall_ctr_T_102 = add(_debug_va_stall_ctr_T_101, sinkIn_19.va_stall[2])
node _debug_va_stall_ctr_T_103 = tail(_debug_va_stall_ctr_T_102, 1)
node _debug_va_stall_ctr_T_104 = add(_debug_va_stall_ctr_T_103, sinkIn_19.va_stall[3])
node _debug_va_stall_ctr_T_105 = tail(_debug_va_stall_ctr_T_104, 1)
node _debug_va_stall_ctr_T_106 = add(_debug_va_stall_ctr_T_105, sinkIn_19.va_stall[4])
node _debug_va_stall_ctr_T_107 = tail(_debug_va_stall_ctr_T_106, 1)
node _debug_va_stall_ctr_T_108 = add(sinkIn_20.va_stall[0], sinkIn_20.va_stall[1])
node _debug_va_stall_ctr_T_109 = tail(_debug_va_stall_ctr_T_108, 1)
node _debug_va_stall_ctr_T_110 = add(_debug_va_stall_ctr_T_109, sinkIn_20.va_stall[2])
node _debug_va_stall_ctr_T_111 = tail(_debug_va_stall_ctr_T_110, 1)
node _debug_va_stall_ctr_T_112 = add(_debug_va_stall_ctr_T_111, sinkIn_20.va_stall[3])
node _debug_va_stall_ctr_T_113 = tail(_debug_va_stall_ctr_T_112, 1)
node _debug_va_stall_ctr_T_114 = add(_debug_va_stall_ctr_T_113, sinkIn_20.va_stall[4])
node _debug_va_stall_ctr_T_115 = tail(_debug_va_stall_ctr_T_114, 1)
node _debug_va_stall_ctr_T_116 = add(sinkIn_21.va_stall[0], sinkIn_21.va_stall[1])
node _debug_va_stall_ctr_T_117 = tail(_debug_va_stall_ctr_T_116, 1)
node _debug_va_stall_ctr_T_118 = add(_debug_va_stall_ctr_T_117, sinkIn_21.va_stall[2])
node _debug_va_stall_ctr_T_119 = tail(_debug_va_stall_ctr_T_118, 1)
node _debug_va_stall_ctr_T_120 = add(_debug_va_stall_ctr_T_119, sinkIn_21.va_stall[3])
node _debug_va_stall_ctr_T_121 = tail(_debug_va_stall_ctr_T_120, 1)
node _debug_va_stall_ctr_T_122 = add(sinkIn_22.va_stall[0], sinkIn_22.va_stall[1])
node _debug_va_stall_ctr_T_123 = tail(_debug_va_stall_ctr_T_122, 1)
node _debug_va_stall_ctr_T_124 = add(_debug_va_stall_ctr_T_123, sinkIn_22.va_stall[2])
node _debug_va_stall_ctr_T_125 = tail(_debug_va_stall_ctr_T_124, 1)
node _debug_va_stall_ctr_T_126 = add(sinkIn_23.va_stall[0], sinkIn_23.va_stall[1])
node _debug_va_stall_ctr_T_127 = tail(_debug_va_stall_ctr_T_126, 1)
node _debug_va_stall_ctr_T_128 = add(_debug_va_stall_ctr_T_127, sinkIn_23.va_stall[2])
node _debug_va_stall_ctr_T_129 = tail(_debug_va_stall_ctr_T_128, 1)
node _debug_va_stall_ctr_T_130 = add(_debug_va_stall_ctr_T_129, sinkIn_23.va_stall[3])
node _debug_va_stall_ctr_T_131 = tail(_debug_va_stall_ctr_T_130, 1)
node _debug_va_stall_ctr_T_132 = add(_debug_va_stall_ctr_T_131, sinkIn_23.va_stall[4])
node _debug_va_stall_ctr_T_133 = tail(_debug_va_stall_ctr_T_132, 1)
node _debug_va_stall_ctr_T_134 = add(sinkIn_24.va_stall[0], sinkIn_24.va_stall[1])
node _debug_va_stall_ctr_T_135 = tail(_debug_va_stall_ctr_T_134, 1)
node _debug_va_stall_ctr_T_136 = add(_debug_va_stall_ctr_T_135, sinkIn_24.va_stall[2])
node _debug_va_stall_ctr_T_137 = tail(_debug_va_stall_ctr_T_136, 1)
node _debug_va_stall_ctr_T_138 = add(_debug_va_stall_ctr_T_137, sinkIn_24.va_stall[3])
node _debug_va_stall_ctr_T_139 = tail(_debug_va_stall_ctr_T_138, 1)
node _debug_va_stall_ctr_T_140 = add(_debug_va_stall_ctr_T_139, sinkIn_24.va_stall[4])
node _debug_va_stall_ctr_T_141 = tail(_debug_va_stall_ctr_T_140, 1)
node _debug_va_stall_ctr_T_142 = add(sinkIn_25.va_stall[0], sinkIn_25.va_stall[1])
node _debug_va_stall_ctr_T_143 = tail(_debug_va_stall_ctr_T_142, 1)
node _debug_va_stall_ctr_T_144 = add(_debug_va_stall_ctr_T_143, sinkIn_25.va_stall[2])
node _debug_va_stall_ctr_T_145 = tail(_debug_va_stall_ctr_T_144, 1)
node _debug_va_stall_ctr_T_146 = add(_debug_va_stall_ctr_T_145, sinkIn_25.va_stall[3])
node _debug_va_stall_ctr_T_147 = tail(_debug_va_stall_ctr_T_146, 1)
node _debug_va_stall_ctr_T_148 = add(sinkIn_26.va_stall[0], sinkIn_26.va_stall[1])
node _debug_va_stall_ctr_T_149 = tail(_debug_va_stall_ctr_T_148, 1)
node _debug_va_stall_ctr_T_150 = add(_debug_va_stall_ctr_T_149, sinkIn_26.va_stall[2])
node _debug_va_stall_ctr_T_151 = tail(_debug_va_stall_ctr_T_150, 1)
node _debug_va_stall_ctr_T_152 = add(sinkIn_27.va_stall[0], sinkIn_27.va_stall[1])
node _debug_va_stall_ctr_T_153 = tail(_debug_va_stall_ctr_T_152, 1)
node _debug_va_stall_ctr_T_154 = add(_debug_va_stall_ctr_T_153, sinkIn_27.va_stall[2])
node _debug_va_stall_ctr_T_155 = tail(_debug_va_stall_ctr_T_154, 1)
node _debug_va_stall_ctr_T_156 = add(_debug_va_stall_ctr_T_155, sinkIn_27.va_stall[3])
node _debug_va_stall_ctr_T_157 = tail(_debug_va_stall_ctr_T_156, 1)
node _debug_va_stall_ctr_T_158 = add(sinkIn_28.va_stall[0], sinkIn_28.va_stall[1])
node _debug_va_stall_ctr_T_159 = tail(_debug_va_stall_ctr_T_158, 1)
node _debug_va_stall_ctr_T_160 = add(_debug_va_stall_ctr_T_5, _debug_va_stall_ctr_T_11)
node _debug_va_stall_ctr_T_161 = tail(_debug_va_stall_ctr_T_160, 1)
node _debug_va_stall_ctr_T_162 = add(_debug_va_stall_ctr_T_161, _debug_va_stall_ctr_T_17)
node _debug_va_stall_ctr_T_163 = tail(_debug_va_stall_ctr_T_162, 1)
node _debug_va_stall_ctr_T_164 = add(_debug_va_stall_ctr_T_163, _debug_va_stall_ctr_T_21)
node _debug_va_stall_ctr_T_165 = tail(_debug_va_stall_ctr_T_164, 1)
node _debug_va_stall_ctr_T_166 = add(_debug_va_stall_ctr_T_165, _debug_va_stall_ctr_T_27)
node _debug_va_stall_ctr_T_167 = tail(_debug_va_stall_ctr_T_166, 1)
node _debug_va_stall_ctr_T_168 = add(_debug_va_stall_ctr_T_167, _debug_va_stall_ctr_T_31)
node _debug_va_stall_ctr_T_169 = tail(_debug_va_stall_ctr_T_168, 1)
node _debug_va_stall_ctr_T_170 = add(_debug_va_stall_ctr_T_169, _debug_va_stall_ctr_T_35)
node _debug_va_stall_ctr_T_171 = tail(_debug_va_stall_ctr_T_170, 1)
node _debug_va_stall_ctr_T_172 = add(_debug_va_stall_ctr_T_171, _debug_va_stall_ctr_T_41)
node _debug_va_stall_ctr_T_173 = tail(_debug_va_stall_ctr_T_172, 1)
node _debug_va_stall_ctr_T_174 = add(_debug_va_stall_ctr_T_173, _debug_va_stall_ctr_T_47)
node _debug_va_stall_ctr_T_175 = tail(_debug_va_stall_ctr_T_174, 1)
node _debug_va_stall_ctr_T_176 = add(_debug_va_stall_ctr_T_175, _debug_va_stall_ctr_T_51)
node _debug_va_stall_ctr_T_177 = tail(_debug_va_stall_ctr_T_176, 1)
node _debug_va_stall_ctr_T_178 = add(_debug_va_stall_ctr_T_177, _debug_va_stall_ctr_T_55)
node _debug_va_stall_ctr_T_179 = tail(_debug_va_stall_ctr_T_178, 1)
node _debug_va_stall_ctr_T_180 = add(_debug_va_stall_ctr_T_179, _debug_va_stall_ctr_T_61)
node _debug_va_stall_ctr_T_181 = tail(_debug_va_stall_ctr_T_180, 1)
node _debug_va_stall_ctr_T_182 = add(_debug_va_stall_ctr_T_181, _debug_va_stall_ctr_T_67)
node _debug_va_stall_ctr_T_183 = tail(_debug_va_stall_ctr_T_182, 1)
node _debug_va_stall_ctr_T_184 = add(_debug_va_stall_ctr_T_183, _debug_va_stall_ctr_T_73)
node _debug_va_stall_ctr_T_185 = tail(_debug_va_stall_ctr_T_184, 1)
node _debug_va_stall_ctr_T_186 = add(_debug_va_stall_ctr_T_185, _debug_va_stall_ctr_T_77)
node _debug_va_stall_ctr_T_187 = tail(_debug_va_stall_ctr_T_186, 1)
node _debug_va_stall_ctr_T_188 = add(_debug_va_stall_ctr_T_187, _debug_va_stall_ctr_T_83)
node _debug_va_stall_ctr_T_189 = tail(_debug_va_stall_ctr_T_188, 1)
node _debug_va_stall_ctr_T_190 = add(_debug_va_stall_ctr_T_189, _debug_va_stall_ctr_T_89)
node _debug_va_stall_ctr_T_191 = tail(_debug_va_stall_ctr_T_190, 1)
node _debug_va_stall_ctr_T_192 = add(_debug_va_stall_ctr_T_191, _debug_va_stall_ctr_T_93)
node _debug_va_stall_ctr_T_193 = tail(_debug_va_stall_ctr_T_192, 1)
node _debug_va_stall_ctr_T_194 = add(_debug_va_stall_ctr_T_193, _debug_va_stall_ctr_T_99)
node _debug_va_stall_ctr_T_195 = tail(_debug_va_stall_ctr_T_194, 1)
node _debug_va_stall_ctr_T_196 = add(_debug_va_stall_ctr_T_195, _debug_va_stall_ctr_T_107)
node _debug_va_stall_ctr_T_197 = tail(_debug_va_stall_ctr_T_196, 1)
node _debug_va_stall_ctr_T_198 = add(_debug_va_stall_ctr_T_197, _debug_va_stall_ctr_T_115)
node _debug_va_stall_ctr_T_199 = tail(_debug_va_stall_ctr_T_198, 1)
node _debug_va_stall_ctr_T_200 = add(_debug_va_stall_ctr_T_199, _debug_va_stall_ctr_T_121)
node _debug_va_stall_ctr_T_201 = tail(_debug_va_stall_ctr_T_200, 1)
node _debug_va_stall_ctr_T_202 = add(_debug_va_stall_ctr_T_201, _debug_va_stall_ctr_T_125)
node _debug_va_stall_ctr_T_203 = tail(_debug_va_stall_ctr_T_202, 1)
node _debug_va_stall_ctr_T_204 = add(_debug_va_stall_ctr_T_203, _debug_va_stall_ctr_T_133)
node _debug_va_stall_ctr_T_205 = tail(_debug_va_stall_ctr_T_204, 1)
node _debug_va_stall_ctr_T_206 = add(_debug_va_stall_ctr_T_205, _debug_va_stall_ctr_T_141)
node _debug_va_stall_ctr_T_207 = tail(_debug_va_stall_ctr_T_206, 1)
node _debug_va_stall_ctr_T_208 = add(_debug_va_stall_ctr_T_207, _debug_va_stall_ctr_T_147)
node _debug_va_stall_ctr_T_209 = tail(_debug_va_stall_ctr_T_208, 1)
node _debug_va_stall_ctr_T_210 = add(_debug_va_stall_ctr_T_209, _debug_va_stall_ctr_T_151)
node _debug_va_stall_ctr_T_211 = tail(_debug_va_stall_ctr_T_210, 1)
node _debug_va_stall_ctr_T_212 = add(_debug_va_stall_ctr_T_211, _debug_va_stall_ctr_T_157)
node _debug_va_stall_ctr_T_213 = tail(_debug_va_stall_ctr_T_212, 1)
node _debug_va_stall_ctr_T_214 = add(_debug_va_stall_ctr_T_213, _debug_va_stall_ctr_T_159)
node _debug_va_stall_ctr_T_215 = tail(_debug_va_stall_ctr_T_214, 1)
node _debug_va_stall_ctr_T_216 = add(debug_va_stall_ctr, _debug_va_stall_ctr_T_215)
node _debug_va_stall_ctr_T_217 = tail(_debug_va_stall_ctr_T_216, 1)
connect debug_va_stall_ctr, _debug_va_stall_ctr_T_217
node _debug_sa_stall_ctr_T = add(sinkIn.sa_stall[0], sinkIn.sa_stall[1])
node _debug_sa_stall_ctr_T_1 = tail(_debug_sa_stall_ctr_T, 1)
node _debug_sa_stall_ctr_T_2 = add(_debug_sa_stall_ctr_T_1, sinkIn.sa_stall[2])
node _debug_sa_stall_ctr_T_3 = tail(_debug_sa_stall_ctr_T_2, 1)
node _debug_sa_stall_ctr_T_4 = add(_debug_sa_stall_ctr_T_3, sinkIn.sa_stall[3])
node _debug_sa_stall_ctr_T_5 = tail(_debug_sa_stall_ctr_T_4, 1)
node _debug_sa_stall_ctr_T_6 = add(sinkIn_1.sa_stall[0], sinkIn_1.sa_stall[1])
node _debug_sa_stall_ctr_T_7 = tail(_debug_sa_stall_ctr_T_6, 1)
node _debug_sa_stall_ctr_T_8 = add(_debug_sa_stall_ctr_T_7, sinkIn_1.sa_stall[2])
node _debug_sa_stall_ctr_T_9 = tail(_debug_sa_stall_ctr_T_8, 1)
node _debug_sa_stall_ctr_T_10 = add(_debug_sa_stall_ctr_T_9, sinkIn_1.sa_stall[3])
node _debug_sa_stall_ctr_T_11 = tail(_debug_sa_stall_ctr_T_10, 1)
node _debug_sa_stall_ctr_T_12 = add(sinkIn_2.sa_stall[0], sinkIn_2.sa_stall[1])
node _debug_sa_stall_ctr_T_13 = tail(_debug_sa_stall_ctr_T_12, 1)
node _debug_sa_stall_ctr_T_14 = add(_debug_sa_stall_ctr_T_13, sinkIn_2.sa_stall[2])
node _debug_sa_stall_ctr_T_15 = tail(_debug_sa_stall_ctr_T_14, 1)
node _debug_sa_stall_ctr_T_16 = add(_debug_sa_stall_ctr_T_15, sinkIn_2.sa_stall[3])
node _debug_sa_stall_ctr_T_17 = tail(_debug_sa_stall_ctr_T_16, 1)
node _debug_sa_stall_ctr_T_18 = add(sinkIn_3.sa_stall[0], sinkIn_3.sa_stall[1])
node _debug_sa_stall_ctr_T_19 = tail(_debug_sa_stall_ctr_T_18, 1)
node _debug_sa_stall_ctr_T_20 = add(_debug_sa_stall_ctr_T_19, sinkIn_3.sa_stall[2])
node _debug_sa_stall_ctr_T_21 = tail(_debug_sa_stall_ctr_T_20, 1)
node _debug_sa_stall_ctr_T_22 = add(sinkIn_4.sa_stall[0], sinkIn_4.sa_stall[1])
node _debug_sa_stall_ctr_T_23 = tail(_debug_sa_stall_ctr_T_22, 1)
node _debug_sa_stall_ctr_T_24 = add(_debug_sa_stall_ctr_T_23, sinkIn_4.sa_stall[2])
node _debug_sa_stall_ctr_T_25 = tail(_debug_sa_stall_ctr_T_24, 1)
node _debug_sa_stall_ctr_T_26 = add(_debug_sa_stall_ctr_T_25, sinkIn_4.sa_stall[3])
node _debug_sa_stall_ctr_T_27 = tail(_debug_sa_stall_ctr_T_26, 1)
node _debug_sa_stall_ctr_T_28 = add(sinkIn_5.sa_stall[0], sinkIn_5.sa_stall[1])
node _debug_sa_stall_ctr_T_29 = tail(_debug_sa_stall_ctr_T_28, 1)
node _debug_sa_stall_ctr_T_30 = add(_debug_sa_stall_ctr_T_29, sinkIn_5.sa_stall[2])
node _debug_sa_stall_ctr_T_31 = tail(_debug_sa_stall_ctr_T_30, 1)
node _debug_sa_stall_ctr_T_32 = add(sinkIn_6.sa_stall[0], sinkIn_6.sa_stall[1])
node _debug_sa_stall_ctr_T_33 = tail(_debug_sa_stall_ctr_T_32, 1)
node _debug_sa_stall_ctr_T_34 = add(_debug_sa_stall_ctr_T_33, sinkIn_6.sa_stall[2])
node _debug_sa_stall_ctr_T_35 = tail(_debug_sa_stall_ctr_T_34, 1)
node _debug_sa_stall_ctr_T_36 = add(sinkIn_7.sa_stall[0], sinkIn_7.sa_stall[1])
node _debug_sa_stall_ctr_T_37 = tail(_debug_sa_stall_ctr_T_36, 1)
node _debug_sa_stall_ctr_T_38 = add(_debug_sa_stall_ctr_T_37, sinkIn_7.sa_stall[2])
node _debug_sa_stall_ctr_T_39 = tail(_debug_sa_stall_ctr_T_38, 1)
node _debug_sa_stall_ctr_T_40 = add(_debug_sa_stall_ctr_T_39, sinkIn_7.sa_stall[3])
node _debug_sa_stall_ctr_T_41 = tail(_debug_sa_stall_ctr_T_40, 1)
node _debug_sa_stall_ctr_T_42 = add(sinkIn_8.sa_stall[0], sinkIn_8.sa_stall[1])
node _debug_sa_stall_ctr_T_43 = tail(_debug_sa_stall_ctr_T_42, 1)
node _debug_sa_stall_ctr_T_44 = add(_debug_sa_stall_ctr_T_43, sinkIn_8.sa_stall[2])
node _debug_sa_stall_ctr_T_45 = tail(_debug_sa_stall_ctr_T_44, 1)
node _debug_sa_stall_ctr_T_46 = add(_debug_sa_stall_ctr_T_45, sinkIn_8.sa_stall[3])
node _debug_sa_stall_ctr_T_47 = tail(_debug_sa_stall_ctr_T_46, 1)
node _debug_sa_stall_ctr_T_48 = add(sinkIn_9.sa_stall[0], sinkIn_9.sa_stall[1])
node _debug_sa_stall_ctr_T_49 = tail(_debug_sa_stall_ctr_T_48, 1)
node _debug_sa_stall_ctr_T_50 = add(_debug_sa_stall_ctr_T_49, sinkIn_9.sa_stall[2])
node _debug_sa_stall_ctr_T_51 = tail(_debug_sa_stall_ctr_T_50, 1)
node _debug_sa_stall_ctr_T_52 = add(sinkIn_10.sa_stall[0], sinkIn_10.sa_stall[1])
node _debug_sa_stall_ctr_T_53 = tail(_debug_sa_stall_ctr_T_52, 1)
node _debug_sa_stall_ctr_T_54 = add(_debug_sa_stall_ctr_T_53, sinkIn_10.sa_stall[2])
node _debug_sa_stall_ctr_T_55 = tail(_debug_sa_stall_ctr_T_54, 1)
node _debug_sa_stall_ctr_T_56 = add(sinkIn_11.sa_stall[0], sinkIn_11.sa_stall[1])
node _debug_sa_stall_ctr_T_57 = tail(_debug_sa_stall_ctr_T_56, 1)
node _debug_sa_stall_ctr_T_58 = add(_debug_sa_stall_ctr_T_57, sinkIn_11.sa_stall[2])
node _debug_sa_stall_ctr_T_59 = tail(_debug_sa_stall_ctr_T_58, 1)
node _debug_sa_stall_ctr_T_60 = add(_debug_sa_stall_ctr_T_59, sinkIn_11.sa_stall[3])
node _debug_sa_stall_ctr_T_61 = tail(_debug_sa_stall_ctr_T_60, 1)
node _debug_sa_stall_ctr_T_62 = add(sinkIn_12.sa_stall[0], sinkIn_12.sa_stall[1])
node _debug_sa_stall_ctr_T_63 = tail(_debug_sa_stall_ctr_T_62, 1)
node _debug_sa_stall_ctr_T_64 = add(_debug_sa_stall_ctr_T_63, sinkIn_12.sa_stall[2])
node _debug_sa_stall_ctr_T_65 = tail(_debug_sa_stall_ctr_T_64, 1)
node _debug_sa_stall_ctr_T_66 = add(_debug_sa_stall_ctr_T_65, sinkIn_12.sa_stall[3])
node _debug_sa_stall_ctr_T_67 = tail(_debug_sa_stall_ctr_T_66, 1)
node _debug_sa_stall_ctr_T_68 = add(sinkIn_13.sa_stall[0], sinkIn_13.sa_stall[1])
node _debug_sa_stall_ctr_T_69 = tail(_debug_sa_stall_ctr_T_68, 1)
node _debug_sa_stall_ctr_T_70 = add(_debug_sa_stall_ctr_T_69, sinkIn_13.sa_stall[2])
node _debug_sa_stall_ctr_T_71 = tail(_debug_sa_stall_ctr_T_70, 1)
node _debug_sa_stall_ctr_T_72 = add(_debug_sa_stall_ctr_T_71, sinkIn_13.sa_stall[3])
node _debug_sa_stall_ctr_T_73 = tail(_debug_sa_stall_ctr_T_72, 1)
node _debug_sa_stall_ctr_T_74 = add(sinkIn_14.sa_stall[0], sinkIn_14.sa_stall[1])
node _debug_sa_stall_ctr_T_75 = tail(_debug_sa_stall_ctr_T_74, 1)
node _debug_sa_stall_ctr_T_76 = add(_debug_sa_stall_ctr_T_75, sinkIn_14.sa_stall[2])
node _debug_sa_stall_ctr_T_77 = tail(_debug_sa_stall_ctr_T_76, 1)
node _debug_sa_stall_ctr_T_78 = add(sinkIn_15.sa_stall[0], sinkIn_15.sa_stall[1])
node _debug_sa_stall_ctr_T_79 = tail(_debug_sa_stall_ctr_T_78, 1)
node _debug_sa_stall_ctr_T_80 = add(_debug_sa_stall_ctr_T_79, sinkIn_15.sa_stall[2])
node _debug_sa_stall_ctr_T_81 = tail(_debug_sa_stall_ctr_T_80, 1)
node _debug_sa_stall_ctr_T_82 = add(_debug_sa_stall_ctr_T_81, sinkIn_15.sa_stall[3])
node _debug_sa_stall_ctr_T_83 = tail(_debug_sa_stall_ctr_T_82, 1)
node _debug_sa_stall_ctr_T_84 = add(sinkIn_16.sa_stall[0], sinkIn_16.sa_stall[1])
node _debug_sa_stall_ctr_T_85 = tail(_debug_sa_stall_ctr_T_84, 1)
node _debug_sa_stall_ctr_T_86 = add(_debug_sa_stall_ctr_T_85, sinkIn_16.sa_stall[2])
node _debug_sa_stall_ctr_T_87 = tail(_debug_sa_stall_ctr_T_86, 1)
node _debug_sa_stall_ctr_T_88 = add(_debug_sa_stall_ctr_T_87, sinkIn_16.sa_stall[3])
node _debug_sa_stall_ctr_T_89 = tail(_debug_sa_stall_ctr_T_88, 1)
node _debug_sa_stall_ctr_T_90 = add(sinkIn_17.sa_stall[0], sinkIn_17.sa_stall[1])
node _debug_sa_stall_ctr_T_91 = tail(_debug_sa_stall_ctr_T_90, 1)
node _debug_sa_stall_ctr_T_92 = add(_debug_sa_stall_ctr_T_91, sinkIn_17.sa_stall[2])
node _debug_sa_stall_ctr_T_93 = tail(_debug_sa_stall_ctr_T_92, 1)
node _debug_sa_stall_ctr_T_94 = add(sinkIn_18.sa_stall[0], sinkIn_18.sa_stall[1])
node _debug_sa_stall_ctr_T_95 = tail(_debug_sa_stall_ctr_T_94, 1)
node _debug_sa_stall_ctr_T_96 = add(_debug_sa_stall_ctr_T_95, sinkIn_18.sa_stall[2])
node _debug_sa_stall_ctr_T_97 = tail(_debug_sa_stall_ctr_T_96, 1)
node _debug_sa_stall_ctr_T_98 = add(_debug_sa_stall_ctr_T_97, sinkIn_18.sa_stall[3])
node _debug_sa_stall_ctr_T_99 = tail(_debug_sa_stall_ctr_T_98, 1)
node _debug_sa_stall_ctr_T_100 = add(sinkIn_19.sa_stall[0], sinkIn_19.sa_stall[1])
node _debug_sa_stall_ctr_T_101 = tail(_debug_sa_stall_ctr_T_100, 1)
node _debug_sa_stall_ctr_T_102 = add(_debug_sa_stall_ctr_T_101, sinkIn_19.sa_stall[2])
node _debug_sa_stall_ctr_T_103 = tail(_debug_sa_stall_ctr_T_102, 1)
node _debug_sa_stall_ctr_T_104 = add(_debug_sa_stall_ctr_T_103, sinkIn_19.sa_stall[3])
node _debug_sa_stall_ctr_T_105 = tail(_debug_sa_stall_ctr_T_104, 1)
node _debug_sa_stall_ctr_T_106 = add(_debug_sa_stall_ctr_T_105, sinkIn_19.sa_stall[4])
node _debug_sa_stall_ctr_T_107 = tail(_debug_sa_stall_ctr_T_106, 1)
node _debug_sa_stall_ctr_T_108 = add(sinkIn_20.sa_stall[0], sinkIn_20.sa_stall[1])
node _debug_sa_stall_ctr_T_109 = tail(_debug_sa_stall_ctr_T_108, 1)
node _debug_sa_stall_ctr_T_110 = add(_debug_sa_stall_ctr_T_109, sinkIn_20.sa_stall[2])
node _debug_sa_stall_ctr_T_111 = tail(_debug_sa_stall_ctr_T_110, 1)
node _debug_sa_stall_ctr_T_112 = add(_debug_sa_stall_ctr_T_111, sinkIn_20.sa_stall[3])
node _debug_sa_stall_ctr_T_113 = tail(_debug_sa_stall_ctr_T_112, 1)
node _debug_sa_stall_ctr_T_114 = add(_debug_sa_stall_ctr_T_113, sinkIn_20.sa_stall[4])
node _debug_sa_stall_ctr_T_115 = tail(_debug_sa_stall_ctr_T_114, 1)
node _debug_sa_stall_ctr_T_116 = add(sinkIn_21.sa_stall[0], sinkIn_21.sa_stall[1])
node _debug_sa_stall_ctr_T_117 = tail(_debug_sa_stall_ctr_T_116, 1)
node _debug_sa_stall_ctr_T_118 = add(_debug_sa_stall_ctr_T_117, sinkIn_21.sa_stall[2])
node _debug_sa_stall_ctr_T_119 = tail(_debug_sa_stall_ctr_T_118, 1)
node _debug_sa_stall_ctr_T_120 = add(_debug_sa_stall_ctr_T_119, sinkIn_21.sa_stall[3])
node _debug_sa_stall_ctr_T_121 = tail(_debug_sa_stall_ctr_T_120, 1)
node _debug_sa_stall_ctr_T_122 = add(sinkIn_22.sa_stall[0], sinkIn_22.sa_stall[1])
node _debug_sa_stall_ctr_T_123 = tail(_debug_sa_stall_ctr_T_122, 1)
node _debug_sa_stall_ctr_T_124 = add(_debug_sa_stall_ctr_T_123, sinkIn_22.sa_stall[2])
node _debug_sa_stall_ctr_T_125 = tail(_debug_sa_stall_ctr_T_124, 1)
node _debug_sa_stall_ctr_T_126 = add(sinkIn_23.sa_stall[0], sinkIn_23.sa_stall[1])
node _debug_sa_stall_ctr_T_127 = tail(_debug_sa_stall_ctr_T_126, 1)
node _debug_sa_stall_ctr_T_128 = add(_debug_sa_stall_ctr_T_127, sinkIn_23.sa_stall[2])
node _debug_sa_stall_ctr_T_129 = tail(_debug_sa_stall_ctr_T_128, 1)
node _debug_sa_stall_ctr_T_130 = add(_debug_sa_stall_ctr_T_129, sinkIn_23.sa_stall[3])
node _debug_sa_stall_ctr_T_131 = tail(_debug_sa_stall_ctr_T_130, 1)
node _debug_sa_stall_ctr_T_132 = add(_debug_sa_stall_ctr_T_131, sinkIn_23.sa_stall[4])
node _debug_sa_stall_ctr_T_133 = tail(_debug_sa_stall_ctr_T_132, 1)
node _debug_sa_stall_ctr_T_134 = add(sinkIn_24.sa_stall[0], sinkIn_24.sa_stall[1])
node _debug_sa_stall_ctr_T_135 = tail(_debug_sa_stall_ctr_T_134, 1)
node _debug_sa_stall_ctr_T_136 = add(_debug_sa_stall_ctr_T_135, sinkIn_24.sa_stall[2])
node _debug_sa_stall_ctr_T_137 = tail(_debug_sa_stall_ctr_T_136, 1)
node _debug_sa_stall_ctr_T_138 = add(_debug_sa_stall_ctr_T_137, sinkIn_24.sa_stall[3])
node _debug_sa_stall_ctr_T_139 = tail(_debug_sa_stall_ctr_T_138, 1)
node _debug_sa_stall_ctr_T_140 = add(_debug_sa_stall_ctr_T_139, sinkIn_24.sa_stall[4])
node _debug_sa_stall_ctr_T_141 = tail(_debug_sa_stall_ctr_T_140, 1)
node _debug_sa_stall_ctr_T_142 = add(sinkIn_25.sa_stall[0], sinkIn_25.sa_stall[1])
node _debug_sa_stall_ctr_T_143 = tail(_debug_sa_stall_ctr_T_142, 1)
node _debug_sa_stall_ctr_T_144 = add(_debug_sa_stall_ctr_T_143, sinkIn_25.sa_stall[2])
node _debug_sa_stall_ctr_T_145 = tail(_debug_sa_stall_ctr_T_144, 1)
node _debug_sa_stall_ctr_T_146 = add(_debug_sa_stall_ctr_T_145, sinkIn_25.sa_stall[3])
node _debug_sa_stall_ctr_T_147 = tail(_debug_sa_stall_ctr_T_146, 1)
node _debug_sa_stall_ctr_T_148 = add(sinkIn_26.sa_stall[0], sinkIn_26.sa_stall[1])
node _debug_sa_stall_ctr_T_149 = tail(_debug_sa_stall_ctr_T_148, 1)
node _debug_sa_stall_ctr_T_150 = add(_debug_sa_stall_ctr_T_149, sinkIn_26.sa_stall[2])
node _debug_sa_stall_ctr_T_151 = tail(_debug_sa_stall_ctr_T_150, 1)
node _debug_sa_stall_ctr_T_152 = add(sinkIn_27.sa_stall[0], sinkIn_27.sa_stall[1])
node _debug_sa_stall_ctr_T_153 = tail(_debug_sa_stall_ctr_T_152, 1)
node _debug_sa_stall_ctr_T_154 = add(_debug_sa_stall_ctr_T_153, sinkIn_27.sa_stall[2])
node _debug_sa_stall_ctr_T_155 = tail(_debug_sa_stall_ctr_T_154, 1)
node _debug_sa_stall_ctr_T_156 = add(_debug_sa_stall_ctr_T_155, sinkIn_27.sa_stall[3])
node _debug_sa_stall_ctr_T_157 = tail(_debug_sa_stall_ctr_T_156, 1)
node _debug_sa_stall_ctr_T_158 = add(sinkIn_28.sa_stall[0], sinkIn_28.sa_stall[1])
node _debug_sa_stall_ctr_T_159 = tail(_debug_sa_stall_ctr_T_158, 1)
node _debug_sa_stall_ctr_T_160 = add(_debug_sa_stall_ctr_T_5, _debug_sa_stall_ctr_T_11)
node _debug_sa_stall_ctr_T_161 = tail(_debug_sa_stall_ctr_T_160, 1)
node _debug_sa_stall_ctr_T_162 = add(_debug_sa_stall_ctr_T_161, _debug_sa_stall_ctr_T_17)
node _debug_sa_stall_ctr_T_163 = tail(_debug_sa_stall_ctr_T_162, 1)
node _debug_sa_stall_ctr_T_164 = add(_debug_sa_stall_ctr_T_163, _debug_sa_stall_ctr_T_21)
node _debug_sa_stall_ctr_T_165 = tail(_debug_sa_stall_ctr_T_164, 1)
node _debug_sa_stall_ctr_T_166 = add(_debug_sa_stall_ctr_T_165, _debug_sa_stall_ctr_T_27)
node _debug_sa_stall_ctr_T_167 = tail(_debug_sa_stall_ctr_T_166, 1)
node _debug_sa_stall_ctr_T_168 = add(_debug_sa_stall_ctr_T_167, _debug_sa_stall_ctr_T_31)
node _debug_sa_stall_ctr_T_169 = tail(_debug_sa_stall_ctr_T_168, 1)
node _debug_sa_stall_ctr_T_170 = add(_debug_sa_stall_ctr_T_169, _debug_sa_stall_ctr_T_35)
node _debug_sa_stall_ctr_T_171 = tail(_debug_sa_stall_ctr_T_170, 1)
node _debug_sa_stall_ctr_T_172 = add(_debug_sa_stall_ctr_T_171, _debug_sa_stall_ctr_T_41)
node _debug_sa_stall_ctr_T_173 = tail(_debug_sa_stall_ctr_T_172, 1)
node _debug_sa_stall_ctr_T_174 = add(_debug_sa_stall_ctr_T_173, _debug_sa_stall_ctr_T_47)
node _debug_sa_stall_ctr_T_175 = tail(_debug_sa_stall_ctr_T_174, 1)
node _debug_sa_stall_ctr_T_176 = add(_debug_sa_stall_ctr_T_175, _debug_sa_stall_ctr_T_51)
node _debug_sa_stall_ctr_T_177 = tail(_debug_sa_stall_ctr_T_176, 1)
node _debug_sa_stall_ctr_T_178 = add(_debug_sa_stall_ctr_T_177, _debug_sa_stall_ctr_T_55)
node _debug_sa_stall_ctr_T_179 = tail(_debug_sa_stall_ctr_T_178, 1)
node _debug_sa_stall_ctr_T_180 = add(_debug_sa_stall_ctr_T_179, _debug_sa_stall_ctr_T_61)
node _debug_sa_stall_ctr_T_181 = tail(_debug_sa_stall_ctr_T_180, 1)
node _debug_sa_stall_ctr_T_182 = add(_debug_sa_stall_ctr_T_181, _debug_sa_stall_ctr_T_67)
node _debug_sa_stall_ctr_T_183 = tail(_debug_sa_stall_ctr_T_182, 1)
node _debug_sa_stall_ctr_T_184 = add(_debug_sa_stall_ctr_T_183, _debug_sa_stall_ctr_T_73)
node _debug_sa_stall_ctr_T_185 = tail(_debug_sa_stall_ctr_T_184, 1)
node _debug_sa_stall_ctr_T_186 = add(_debug_sa_stall_ctr_T_185, _debug_sa_stall_ctr_T_77)
node _debug_sa_stall_ctr_T_187 = tail(_debug_sa_stall_ctr_T_186, 1)
node _debug_sa_stall_ctr_T_188 = add(_debug_sa_stall_ctr_T_187, _debug_sa_stall_ctr_T_83)
node _debug_sa_stall_ctr_T_189 = tail(_debug_sa_stall_ctr_T_188, 1)
node _debug_sa_stall_ctr_T_190 = add(_debug_sa_stall_ctr_T_189, _debug_sa_stall_ctr_T_89)
node _debug_sa_stall_ctr_T_191 = tail(_debug_sa_stall_ctr_T_190, 1)
node _debug_sa_stall_ctr_T_192 = add(_debug_sa_stall_ctr_T_191, _debug_sa_stall_ctr_T_93)
node _debug_sa_stall_ctr_T_193 = tail(_debug_sa_stall_ctr_T_192, 1)
node _debug_sa_stall_ctr_T_194 = add(_debug_sa_stall_ctr_T_193, _debug_sa_stall_ctr_T_99)
node _debug_sa_stall_ctr_T_195 = tail(_debug_sa_stall_ctr_T_194, 1)
node _debug_sa_stall_ctr_T_196 = add(_debug_sa_stall_ctr_T_195, _debug_sa_stall_ctr_T_107)
node _debug_sa_stall_ctr_T_197 = tail(_debug_sa_stall_ctr_T_196, 1)
node _debug_sa_stall_ctr_T_198 = add(_debug_sa_stall_ctr_T_197, _debug_sa_stall_ctr_T_115)
node _debug_sa_stall_ctr_T_199 = tail(_debug_sa_stall_ctr_T_198, 1)
node _debug_sa_stall_ctr_T_200 = add(_debug_sa_stall_ctr_T_199, _debug_sa_stall_ctr_T_121)
node _debug_sa_stall_ctr_T_201 = tail(_debug_sa_stall_ctr_T_200, 1)
node _debug_sa_stall_ctr_T_202 = add(_debug_sa_stall_ctr_T_201, _debug_sa_stall_ctr_T_125)
node _debug_sa_stall_ctr_T_203 = tail(_debug_sa_stall_ctr_T_202, 1)
node _debug_sa_stall_ctr_T_204 = add(_debug_sa_stall_ctr_T_203, _debug_sa_stall_ctr_T_133)
node _debug_sa_stall_ctr_T_205 = tail(_debug_sa_stall_ctr_T_204, 1)
node _debug_sa_stall_ctr_T_206 = add(_debug_sa_stall_ctr_T_205, _debug_sa_stall_ctr_T_141)
node _debug_sa_stall_ctr_T_207 = tail(_debug_sa_stall_ctr_T_206, 1)
node _debug_sa_stall_ctr_T_208 = add(_debug_sa_stall_ctr_T_207, _debug_sa_stall_ctr_T_147)
node _debug_sa_stall_ctr_T_209 = tail(_debug_sa_stall_ctr_T_208, 1)
node _debug_sa_stall_ctr_T_210 = add(_debug_sa_stall_ctr_T_209, _debug_sa_stall_ctr_T_151)
node _debug_sa_stall_ctr_T_211 = tail(_debug_sa_stall_ctr_T_210, 1)
node _debug_sa_stall_ctr_T_212 = add(_debug_sa_stall_ctr_T_211, _debug_sa_stall_ctr_T_157)
node _debug_sa_stall_ctr_T_213 = tail(_debug_sa_stall_ctr_T_212, 1)
node _debug_sa_stall_ctr_T_214 = add(_debug_sa_stall_ctr_T_213, _debug_sa_stall_ctr_T_159)
node _debug_sa_stall_ctr_T_215 = tail(_debug_sa_stall_ctr_T_214, 1)
node _debug_sa_stall_ctr_T_216 = add(debug_sa_stall_ctr, _debug_sa_stall_ctr_T_215)
node _debug_sa_stall_ctr_T_217 = tail(_debug_sa_stall_ctr_T_216, 1)
connect debug_sa_stall_ctr, _debug_sa_stall_ctr_T_217 | module NoC( // @[NoC.scala:141:9]
input clock, // @[NoC.scala:141:9]
input reset, // @[NoC.scala:141:9]
output io_ingress_36_flit_ready, // @[NoC.scala:143:16]
input io_ingress_36_flit_valid, // @[NoC.scala:143:16]
input io_ingress_36_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_36_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_36_flit_bits_payload, // @[NoC.scala:143:16]
input [4:0] io_ingress_36_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_35_flit_ready, // @[NoC.scala:143:16]
input io_ingress_35_flit_valid, // @[NoC.scala:143:16]
input io_ingress_35_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_35_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_35_flit_bits_payload, // @[NoC.scala:143:16]
input [4:0] io_ingress_35_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_34_flit_ready, // @[NoC.scala:143:16]
input io_ingress_34_flit_valid, // @[NoC.scala:143:16]
input io_ingress_34_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_34_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_34_flit_bits_payload, // @[NoC.scala:143:16]
input [4:0] io_ingress_34_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_33_flit_ready, // @[NoC.scala:143:16]
input io_ingress_33_flit_valid, // @[NoC.scala:143:16]
input io_ingress_33_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_33_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_33_flit_bits_payload, // @[NoC.scala:143:16]
input [4:0] io_ingress_33_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_32_flit_ready, // @[NoC.scala:143:16]
input io_ingress_32_flit_valid, // @[NoC.scala:143:16]
input io_ingress_32_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_32_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_32_flit_bits_payload, // @[NoC.scala:143:16]
input [4:0] io_ingress_32_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_31_flit_ready, // @[NoC.scala:143:16]
input io_ingress_31_flit_valid, // @[NoC.scala:143:16]
input io_ingress_31_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_31_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_31_flit_bits_payload, // @[NoC.scala:143:16]
input [4:0] io_ingress_31_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_30_flit_ready, // @[NoC.scala:143:16]
input io_ingress_30_flit_valid, // @[NoC.scala:143:16]
input io_ingress_30_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_30_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_30_flit_bits_payload, // @[NoC.scala:143:16]
input [4:0] io_ingress_30_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_29_flit_ready, // @[NoC.scala:143:16]
input io_ingress_29_flit_valid, // @[NoC.scala:143:16]
input io_ingress_29_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_29_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_29_flit_bits_payload, // @[NoC.scala:143:16]
input [4:0] io_ingress_29_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_28_flit_ready, // @[NoC.scala:143:16]
input io_ingress_28_flit_valid, // @[NoC.scala:143:16]
input io_ingress_28_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_28_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_28_flit_bits_payload, // @[NoC.scala:143:16]
input [4:0] io_ingress_28_flit_bits_egress_id, // @[NoC.scala:143:16]
input io_ingress_27_flit_valid, // @[NoC.scala:143:16]
output io_ingress_26_flit_ready, // @[NoC.scala:143:16]
input io_ingress_26_flit_valid, // @[NoC.scala:143:16]
input io_ingress_26_flit_bits_head, // @[NoC.scala:143:16]
input [72:0] io_ingress_26_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_26_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_25_flit_ready, // @[NoC.scala:143:16]
input io_ingress_25_flit_valid, // @[NoC.scala:143:16]
input io_ingress_25_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_25_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_25_flit_bits_payload, // @[NoC.scala:143:16]
input [4:0] io_ingress_25_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_24_flit_ready, // @[NoC.scala:143:16]
input io_ingress_24_flit_valid, // @[NoC.scala:143:16]
input io_ingress_24_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_24_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_24_flit_bits_payload, // @[NoC.scala:143:16]
input [4:0] io_ingress_24_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_23_flit_ready, // @[NoC.scala:143:16]
input io_ingress_23_flit_valid, // @[NoC.scala:143:16]
input io_ingress_23_flit_bits_head, // @[NoC.scala:143:16]
input [72:0] io_ingress_23_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_23_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_22_flit_ready, // @[NoC.scala:143:16]
input io_ingress_22_flit_valid, // @[NoC.scala:143:16]
input io_ingress_22_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_22_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_22_flit_bits_payload, // @[NoC.scala:143:16]
input [4:0] io_ingress_22_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_21_flit_ready, // @[NoC.scala:143:16]
input io_ingress_21_flit_valid, // @[NoC.scala:143:16]
input io_ingress_21_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_21_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_21_flit_bits_payload, // @[NoC.scala:143:16]
input [4:0] io_ingress_21_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_20_flit_ready, // @[NoC.scala:143:16]
input io_ingress_20_flit_valid, // @[NoC.scala:143:16]
input io_ingress_20_flit_bits_head, // @[NoC.scala:143:16]
input [72:0] io_ingress_20_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_20_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_19_flit_ready, // @[NoC.scala:143:16]
input io_ingress_19_flit_valid, // @[NoC.scala:143:16]
input io_ingress_19_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_19_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_19_flit_bits_payload, // @[NoC.scala:143:16]
input [4:0] io_ingress_19_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_18_flit_ready, // @[NoC.scala:143:16]
input io_ingress_18_flit_valid, // @[NoC.scala:143:16]
input io_ingress_18_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_18_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_18_flit_bits_payload, // @[NoC.scala:143:16]
input [4:0] io_ingress_18_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_17_flit_ready, // @[NoC.scala:143:16]
input io_ingress_17_flit_valid, // @[NoC.scala:143:16]
input io_ingress_17_flit_bits_head, // @[NoC.scala:143:16]
input [72:0] io_ingress_17_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_17_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_16_flit_ready, // @[NoC.scala:143:16]
input io_ingress_16_flit_valid, // @[NoC.scala:143:16]
input io_ingress_16_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_16_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_16_flit_bits_payload, // @[NoC.scala:143:16]
input [4:0] io_ingress_16_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_15_flit_ready, // @[NoC.scala:143:16]
input io_ingress_15_flit_valid, // @[NoC.scala:143:16]
input io_ingress_15_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_15_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_15_flit_bits_payload, // @[NoC.scala:143:16]
input [4:0] io_ingress_15_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_14_flit_ready, // @[NoC.scala:143:16]
input io_ingress_14_flit_valid, // @[NoC.scala:143:16]
input io_ingress_14_flit_bits_head, // @[NoC.scala:143:16]
input [72:0] io_ingress_14_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_14_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_13_flit_ready, // @[NoC.scala:143:16]
input io_ingress_13_flit_valid, // @[NoC.scala:143:16]
input io_ingress_13_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_13_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_13_flit_bits_payload, // @[NoC.scala:143:16]
input [4:0] io_ingress_13_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_12_flit_ready, // @[NoC.scala:143:16]
input io_ingress_12_flit_valid, // @[NoC.scala:143:16]
input io_ingress_12_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_12_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_12_flit_bits_payload, // @[NoC.scala:143:16]
input [4:0] io_ingress_12_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_11_flit_ready, // @[NoC.scala:143:16]
input io_ingress_11_flit_valid, // @[NoC.scala:143:16]
input io_ingress_11_flit_bits_head, // @[NoC.scala:143:16]
input [72:0] io_ingress_11_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_11_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_10_flit_ready, // @[NoC.scala:143:16]
input io_ingress_10_flit_valid, // @[NoC.scala:143:16]
input io_ingress_10_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_10_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_10_flit_bits_payload, // @[NoC.scala:143:16]
input [4:0] io_ingress_10_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_9_flit_ready, // @[NoC.scala:143:16]
input io_ingress_9_flit_valid, // @[NoC.scala:143:16]
input io_ingress_9_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_9_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_9_flit_bits_payload, // @[NoC.scala:143:16]
input [4:0] io_ingress_9_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_8_flit_ready, // @[NoC.scala:143:16]
input io_ingress_8_flit_valid, // @[NoC.scala:143:16]
input io_ingress_8_flit_bits_head, // @[NoC.scala:143:16]
input [72:0] io_ingress_8_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_8_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_7_flit_ready, // @[NoC.scala:143:16]
input io_ingress_7_flit_valid, // @[NoC.scala:143:16]
input io_ingress_7_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_7_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_7_flit_bits_payload, // @[NoC.scala:143:16]
input [4:0] io_ingress_7_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_6_flit_ready, // @[NoC.scala:143:16]
input io_ingress_6_flit_valid, // @[NoC.scala:143:16]
input io_ingress_6_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_6_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_6_flit_bits_payload, // @[NoC.scala:143:16]
input [4:0] io_ingress_6_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_5_flit_ready, // @[NoC.scala:143:16]
input io_ingress_5_flit_valid, // @[NoC.scala:143:16]
input io_ingress_5_flit_bits_head, // @[NoC.scala:143:16]
input [72:0] io_ingress_5_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_5_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_4_flit_ready, // @[NoC.scala:143:16]
input io_ingress_4_flit_valid, // @[NoC.scala:143:16]
input io_ingress_4_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_4_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_4_flit_bits_payload, // @[NoC.scala:143:16]
input [4:0] io_ingress_4_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_3_flit_ready, // @[NoC.scala:143:16]
input io_ingress_3_flit_valid, // @[NoC.scala:143:16]
input io_ingress_3_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_3_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_3_flit_bits_payload, // @[NoC.scala:143:16]
input [4:0] io_ingress_3_flit_bits_egress_id, // @[NoC.scala:143:16]
input io_ingress_2_flit_valid, // @[NoC.scala:143:16]
input io_ingress_1_flit_valid, // @[NoC.scala:143:16]
output io_ingress_0_flit_ready, // @[NoC.scala:143:16]
input io_ingress_0_flit_valid, // @[NoC.scala:143:16]
input io_ingress_0_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_0_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_0_flit_bits_payload, // @[NoC.scala:143:16]
input [4:0] io_ingress_0_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_egress_32_flit_valid, // @[NoC.scala:143:16]
output io_egress_32_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_32_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_32_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_31_flit_ready, // @[NoC.scala:143:16]
output io_egress_31_flit_valid, // @[NoC.scala:143:16]
output io_egress_31_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_31_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_31_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_30_flit_ready, // @[NoC.scala:143:16]
output io_egress_30_flit_valid, // @[NoC.scala:143:16]
output io_egress_30_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_30_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_30_flit_bits_payload, // @[NoC.scala:143:16]
output io_egress_29_flit_valid, // @[NoC.scala:143:16]
output io_egress_29_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_29_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_29_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_28_flit_ready, // @[NoC.scala:143:16]
output io_egress_28_flit_valid, // @[NoC.scala:143:16]
output io_egress_28_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_28_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_28_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_27_flit_ready, // @[NoC.scala:143:16]
output io_egress_27_flit_valid, // @[NoC.scala:143:16]
output io_egress_27_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_27_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_27_flit_bits_payload, // @[NoC.scala:143:16]
output io_egress_26_flit_valid, // @[NoC.scala:143:16]
output io_egress_26_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_26_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_26_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_25_flit_ready, // @[NoC.scala:143:16]
output io_egress_25_flit_valid, // @[NoC.scala:143:16]
output io_egress_25_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_25_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_25_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_24_flit_ready, // @[NoC.scala:143:16]
output io_egress_24_flit_valid, // @[NoC.scala:143:16]
output io_egress_24_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_24_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_24_flit_bits_payload, // @[NoC.scala:143:16]
output io_egress_23_flit_valid, // @[NoC.scala:143:16]
output io_egress_23_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_23_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_23_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_22_flit_ready, // @[NoC.scala:143:16]
output io_egress_22_flit_valid, // @[NoC.scala:143:16]
output io_egress_22_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_22_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_22_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_21_flit_ready, // @[NoC.scala:143:16]
output io_egress_21_flit_valid, // @[NoC.scala:143:16]
output io_egress_21_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_21_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_21_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_20_flit_ready, // @[NoC.scala:143:16]
output io_egress_20_flit_valid, // @[NoC.scala:143:16]
output io_egress_20_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_20_flit_bits_tail, // @[NoC.scala:143:16]
input io_egress_19_flit_ready, // @[NoC.scala:143:16]
output io_egress_19_flit_valid, // @[NoC.scala:143:16]
output io_egress_19_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_19_flit_bits_tail, // @[NoC.scala:143:16]
input io_egress_18_flit_ready, // @[NoC.scala:143:16]
output io_egress_18_flit_valid, // @[NoC.scala:143:16]
output io_egress_18_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_18_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_18_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_17_flit_ready, // @[NoC.scala:143:16]
output io_egress_17_flit_valid, // @[NoC.scala:143:16]
output io_egress_17_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_17_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_17_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_16_flit_ready, // @[NoC.scala:143:16]
output io_egress_16_flit_valid, // @[NoC.scala:143:16]
output io_egress_16_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_16_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_16_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_15_flit_ready, // @[NoC.scala:143:16]
output io_egress_15_flit_valid, // @[NoC.scala:143:16]
output io_egress_15_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_15_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_15_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_14_flit_ready, // @[NoC.scala:143:16]
output io_egress_14_flit_valid, // @[NoC.scala:143:16]
output io_egress_14_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_14_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_14_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_13_flit_ready, // @[NoC.scala:143:16]
output io_egress_13_flit_valid, // @[NoC.scala:143:16]
output io_egress_13_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_13_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_13_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_12_flit_ready, // @[NoC.scala:143:16]
output io_egress_12_flit_valid, // @[NoC.scala:143:16]
output io_egress_12_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_12_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_12_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_11_flit_ready, // @[NoC.scala:143:16]
output io_egress_11_flit_valid, // @[NoC.scala:143:16]
output io_egress_11_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_11_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_11_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_10_flit_ready, // @[NoC.scala:143:16]
output io_egress_10_flit_valid, // @[NoC.scala:143:16]
output io_egress_10_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_10_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_10_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_9_flit_ready, // @[NoC.scala:143:16]
output io_egress_9_flit_valid, // @[NoC.scala:143:16]
output io_egress_9_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_9_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_9_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_8_flit_ready, // @[NoC.scala:143:16]
output io_egress_8_flit_valid, // @[NoC.scala:143:16]
output io_egress_8_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_8_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_8_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_7_flit_ready, // @[NoC.scala:143:16]
output io_egress_7_flit_valid, // @[NoC.scala:143:16]
output io_egress_7_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_7_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_7_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_6_flit_ready, // @[NoC.scala:143:16]
output io_egress_6_flit_valid, // @[NoC.scala:143:16]
output io_egress_6_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_6_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_6_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_5_flit_ready, // @[NoC.scala:143:16]
output io_egress_5_flit_valid, // @[NoC.scala:143:16]
output io_egress_5_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_5_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_5_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_4_flit_ready, // @[NoC.scala:143:16]
output io_egress_4_flit_valid, // @[NoC.scala:143:16]
output io_egress_4_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_4_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_4_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_3_flit_ready, // @[NoC.scala:143:16]
output io_egress_3_flit_valid, // @[NoC.scala:143:16]
output io_egress_3_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_3_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_3_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_2_flit_ready, // @[NoC.scala:143:16]
output io_egress_2_flit_valid, // @[NoC.scala:143:16]
output io_egress_2_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_2_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_2_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_1_flit_ready, // @[NoC.scala:143:16]
output io_egress_1_flit_valid, // @[NoC.scala:143:16]
output io_egress_1_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_1_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_1_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_0_flit_ready, // @[NoC.scala:143:16]
output io_egress_0_flit_valid, // @[NoC.scala:143:16]
output io_egress_0_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_0_flit_bits_tail, // @[NoC.scala:143:16]
input io_router_clocks_0_clock, // @[NoC.scala:143:16]
input io_router_clocks_0_reset, // @[NoC.scala:143:16]
input io_router_clocks_1_clock, // @[NoC.scala:143:16]
input io_router_clocks_1_reset, // @[NoC.scala:143:16]
input io_router_clocks_2_clock, // @[NoC.scala:143:16]
input io_router_clocks_2_reset, // @[NoC.scala:143:16]
input io_router_clocks_3_clock, // @[NoC.scala:143:16]
input io_router_clocks_3_reset, // @[NoC.scala:143:16]
input io_router_clocks_4_clock, // @[NoC.scala:143:16]
input io_router_clocks_4_reset, // @[NoC.scala:143:16]
input io_router_clocks_5_clock, // @[NoC.scala:143:16]
input io_router_clocks_5_reset, // @[NoC.scala:143:16]
input io_router_clocks_6_clock, // @[NoC.scala:143:16]
input io_router_clocks_6_reset, // @[NoC.scala:143:16]
input io_router_clocks_7_clock, // @[NoC.scala:143:16]
input io_router_clocks_7_reset, // @[NoC.scala:143:16]
input io_router_clocks_8_clock, // @[NoC.scala:143:16]
input io_router_clocks_8_reset, // @[NoC.scala:143:16]
input io_router_clocks_9_clock, // @[NoC.scala:143:16]
input io_router_clocks_9_reset, // @[NoC.scala:143:16]
input io_router_clocks_10_clock, // @[NoC.scala:143:16]
input io_router_clocks_10_reset, // @[NoC.scala:143:16]
input io_router_clocks_11_clock, // @[NoC.scala:143:16]
input io_router_clocks_11_reset, // @[NoC.scala:143:16]
input io_router_clocks_13_clock, // @[NoC.scala:143:16]
input io_router_clocks_13_reset, // @[NoC.scala:143:16]
input io_router_clocks_14_clock, // @[NoC.scala:143:16]
input io_router_clocks_14_reset, // @[NoC.scala:143:16]
input io_router_clocks_16_clock, // @[NoC.scala:143:16]
input io_router_clocks_16_reset, // @[NoC.scala:143:16]
input io_router_clocks_17_clock, // @[NoC.scala:143:16]
input io_router_clocks_17_reset, // @[NoC.scala:143:16]
input io_router_clocks_18_clock, // @[NoC.scala:143:16]
input io_router_clocks_18_reset, // @[NoC.scala:143:16]
input io_router_clocks_19_clock, // @[NoC.scala:143:16]
input io_router_clocks_19_reset, // @[NoC.scala:143:16]
input io_router_clocks_20_clock, // @[NoC.scala:143:16]
input io_router_clocks_20_reset, // @[NoC.scala:143:16]
input io_router_clocks_21_clock, // @[NoC.scala:143:16]
input io_router_clocks_21_reset, // @[NoC.scala:143:16]
input io_router_clocks_22_clock, // @[NoC.scala:143:16]
input io_router_clocks_22_reset, // @[NoC.scala:143:16]
input io_router_clocks_23_clock, // @[NoC.scala:143:16]
input io_router_clocks_23_reset, // @[NoC.scala:143:16]
input io_router_clocks_24_clock, // @[NoC.scala:143:16]
input io_router_clocks_24_reset, // @[NoC.scala:143:16]
input io_router_clocks_25_clock, // @[NoC.scala:143:16]
input io_router_clocks_25_reset, // @[NoC.scala:143:16]
input io_router_clocks_26_clock, // @[NoC.scala:143:16]
input io_router_clocks_26_reset, // @[NoC.scala:143:16]
input io_router_clocks_27_clock, // @[NoC.scala:143:16]
input io_router_clocks_27_reset, // @[NoC.scala:143:16]
input io_router_clocks_29_clock, // @[NoC.scala:143:16]
input io_router_clocks_29_reset, // @[NoC.scala:143:16]
input io_router_clocks_30_clock, // @[NoC.scala:143:16]
input io_router_clocks_30_reset, // @[NoC.scala:143:16]
input io_router_clocks_31_clock, // @[NoC.scala:143:16]
input io_router_clocks_31_reset // @[NoC.scala:143:16]
);
wire [2:0] _router_sink_domain_31_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_31_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_31_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_31_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire _router_sink_domain_31_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_31_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_31_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_31_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_31_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_31_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_31_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_31_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_31_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_31_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_31_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_31_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_31_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_31_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_31_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_31_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_31_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_31_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_31_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_31_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_31_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_31_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_31_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_31_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_30_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_30_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_30_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_30_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_30_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_30_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_30_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_30_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40]
wire _router_sink_domain_30_auto_routers_source_nodes_out_3_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_30_auto_routers_source_nodes_out_3_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_30_auto_routers_source_nodes_out_3_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_30_auto_routers_source_nodes_out_3_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_30_auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_30_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_30_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_30_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_30_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_30_auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_30_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_30_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_30_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_30_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_30_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_30_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_30_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_30_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_30_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_30_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_30_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_30_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_30_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_30_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_30_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_30_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_30_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_30_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_30_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_30_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_30_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_30_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_30_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_30_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_30_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_30_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_30_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_30_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_30_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_30_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_30_auto_routers_dest_nodes_in_3_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_30_auto_routers_dest_nodes_in_3_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_30_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_30_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_30_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_30_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_30_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_30_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_29_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_29_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_29_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_29_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_29_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_29_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire _router_sink_domain_29_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_29_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_29_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_29_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_29_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_29_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_29_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_29_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_29_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_29_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_29_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_29_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_29_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_29_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_29_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_29_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_29_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_29_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_29_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_29_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_29_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_29_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_29_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_29_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_29_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_29_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_29_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_29_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_29_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_29_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_29_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_29_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_29_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_29_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_29_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_29_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_27_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_27_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_27_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_27_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_27_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_27_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_27_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_27_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40]
wire _router_sink_domain_27_auto_routers_source_nodes_out_3_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_27_auto_routers_source_nodes_out_3_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_27_auto_routers_source_nodes_out_3_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_27_auto_routers_source_nodes_out_3_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_27_auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_27_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_27_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_27_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_27_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_27_auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_27_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_27_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_27_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_27_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_27_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_27_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_27_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_27_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_27_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_27_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_27_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_27_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_27_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_27_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_27_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_27_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_27_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_27_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_27_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_27_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_27_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_27_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_27_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_27_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_27_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_27_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_27_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_27_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_27_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_27_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_27_auto_routers_dest_nodes_in_3_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_27_auto_routers_dest_nodes_in_3_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_27_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_27_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_27_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_27_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_27_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_27_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_26_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_26_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_26_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_26_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_26_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_26_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_26_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_26_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_26_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_26_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40]
wire _router_sink_domain_26_auto_routers_source_nodes_out_4_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_26_auto_routers_source_nodes_out_4_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_26_auto_routers_source_nodes_out_4_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_26_auto_routers_source_nodes_out_4_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_26_auto_routers_source_nodes_out_4_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_26_auto_routers_source_nodes_out_4_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_26_auto_routers_source_nodes_out_4_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_26_auto_routers_source_nodes_out_4_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_26_auto_routers_source_nodes_out_4_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_26_auto_routers_source_nodes_out_4_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_26_auto_routers_source_nodes_out_3_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_26_auto_routers_source_nodes_out_3_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_26_auto_routers_source_nodes_out_3_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_26_auto_routers_source_nodes_out_3_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_26_auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_26_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_26_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_26_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_26_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_26_auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_26_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_26_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_26_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_26_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_26_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_26_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_26_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_26_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_26_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_26_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_26_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_26_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_26_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_26_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_26_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_26_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_26_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_26_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_26_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_26_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_26_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_26_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_26_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_26_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_26_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_26_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_26_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_26_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_26_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_26_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_26_auto_routers_dest_nodes_in_4_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_26_auto_routers_dest_nodes_in_4_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_26_auto_routers_dest_nodes_in_3_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_26_auto_routers_dest_nodes_in_3_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_26_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_26_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_26_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_26_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_26_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_26_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_25_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_25_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_25_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_25_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_25_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_25_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_25_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_25_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_25_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_25_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40]
wire _router_sink_domain_25_auto_routers_source_nodes_out_4_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_25_auto_routers_source_nodes_out_4_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_25_auto_routers_source_nodes_out_4_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_25_auto_routers_source_nodes_out_4_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_25_auto_routers_source_nodes_out_4_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_25_auto_routers_source_nodes_out_4_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_25_auto_routers_source_nodes_out_4_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_25_auto_routers_source_nodes_out_4_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_25_auto_routers_source_nodes_out_4_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_25_auto_routers_source_nodes_out_4_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_25_auto_routers_source_nodes_out_3_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_25_auto_routers_source_nodes_out_3_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_25_auto_routers_source_nodes_out_3_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_25_auto_routers_source_nodes_out_3_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_25_auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_25_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_25_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_25_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_25_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_25_auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_25_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_25_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_25_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_25_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_25_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_25_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_25_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_25_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_25_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_25_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_25_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_25_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_25_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_25_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_25_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_25_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_25_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_25_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_25_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_25_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_25_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_25_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_25_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_25_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_25_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_25_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_25_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_25_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_25_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_25_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_25_auto_routers_dest_nodes_in_4_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_25_auto_routers_dest_nodes_in_4_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_25_auto_routers_dest_nodes_in_3_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_25_auto_routers_dest_nodes_in_3_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_25_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_25_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_25_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_25_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_25_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_25_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_24_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_24_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_24_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_24_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_24_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_24_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire _router_sink_domain_24_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_24_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_24_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_24_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_24_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_24_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_24_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_24_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_24_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_24_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_24_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_24_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_24_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_24_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_24_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_24_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_24_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_24_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_24_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_24_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_24_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_24_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_24_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_24_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_24_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_24_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_24_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_24_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_24_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_24_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_24_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_24_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_24_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_24_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_24_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_24_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_23_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_23_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_23_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_23_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_23_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_23_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_23_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_23_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40]
wire _router_sink_domain_23_auto_routers_source_nodes_out_3_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_23_auto_routers_source_nodes_out_3_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_23_auto_routers_source_nodes_out_3_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_23_auto_routers_source_nodes_out_3_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_23_auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_23_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_23_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_23_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_23_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_23_auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_23_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_23_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_23_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_23_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_23_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_23_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_23_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_23_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_23_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_23_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_23_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_23_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_23_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_23_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_23_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_23_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_23_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_23_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_23_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_23_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_23_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_23_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_23_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_23_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_23_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_23_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_23_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_23_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_23_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_23_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_23_auto_routers_dest_nodes_in_3_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_23_auto_routers_dest_nodes_in_3_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_23_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_23_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_23_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_23_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_23_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_23_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_22_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_22_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_22_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_22_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_22_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_22_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_22_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_22_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_22_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_22_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40]
wire _router_sink_domain_22_auto_routers_source_nodes_out_4_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_22_auto_routers_source_nodes_out_4_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_22_auto_routers_source_nodes_out_4_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_22_auto_routers_source_nodes_out_4_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_22_auto_routers_source_nodes_out_4_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_22_auto_routers_source_nodes_out_4_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_22_auto_routers_source_nodes_out_4_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_22_auto_routers_source_nodes_out_4_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_22_auto_routers_source_nodes_out_4_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_22_auto_routers_source_nodes_out_4_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_22_auto_routers_source_nodes_out_3_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_22_auto_routers_source_nodes_out_3_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_22_auto_routers_source_nodes_out_3_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_22_auto_routers_source_nodes_out_3_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_22_auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_22_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_22_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_22_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_22_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_22_auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_22_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_22_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_22_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_22_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_22_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_22_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_22_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_22_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_22_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_22_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_22_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_22_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_22_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_22_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_22_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_22_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_22_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_22_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_22_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_22_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_22_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_22_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_22_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_22_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_22_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_22_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_22_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_22_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_22_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_22_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_22_auto_routers_dest_nodes_in_4_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_22_auto_routers_dest_nodes_in_4_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_22_auto_routers_dest_nodes_in_3_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_22_auto_routers_dest_nodes_in_3_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_22_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_22_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_22_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_22_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_22_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_22_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_21_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_21_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_21_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_21_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_21_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_21_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_21_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_21_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_21_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_21_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40]
wire _router_sink_domain_21_auto_routers_source_nodes_out_4_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_21_auto_routers_source_nodes_out_4_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_21_auto_routers_source_nodes_out_4_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_21_auto_routers_source_nodes_out_4_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_21_auto_routers_source_nodes_out_4_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_21_auto_routers_source_nodes_out_4_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_21_auto_routers_source_nodes_out_4_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_21_auto_routers_source_nodes_out_4_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_21_auto_routers_source_nodes_out_4_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_21_auto_routers_source_nodes_out_4_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_21_auto_routers_source_nodes_out_3_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_21_auto_routers_source_nodes_out_3_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_21_auto_routers_source_nodes_out_3_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_21_auto_routers_source_nodes_out_3_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_21_auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_21_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_21_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_21_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_21_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_21_auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_21_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_21_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_21_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_21_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_21_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_21_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_21_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_21_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_21_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_21_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_21_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_21_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_21_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_21_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_21_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_21_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_21_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_21_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_21_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_21_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_21_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_21_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_21_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_21_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_21_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_21_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_21_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_21_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_21_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_21_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_21_auto_routers_dest_nodes_in_4_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_21_auto_routers_dest_nodes_in_4_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_21_auto_routers_dest_nodes_in_3_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_21_auto_routers_dest_nodes_in_3_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_21_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_21_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_21_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_21_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_21_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_21_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_20_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_20_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_20_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_20_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_20_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_20_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_20_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_20_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40]
wire _router_sink_domain_20_auto_routers_source_nodes_out_3_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_20_auto_routers_source_nodes_out_3_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_20_auto_routers_source_nodes_out_3_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_20_auto_routers_source_nodes_out_3_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_20_auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_20_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_20_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_20_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_20_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_20_auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_20_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_20_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_20_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_20_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_20_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_20_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_20_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_20_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_20_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_20_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_20_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_20_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_20_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_20_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_20_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_20_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_20_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_20_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_20_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_20_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_20_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_20_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_20_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_20_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_20_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_20_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_20_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_20_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_20_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_20_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_20_auto_routers_dest_nodes_in_3_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_20_auto_routers_dest_nodes_in_3_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_20_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_20_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_20_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_20_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_20_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_20_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_19_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_19_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_19_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_19_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_19_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_19_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire _router_sink_domain_19_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_19_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_19_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_19_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_19_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_19_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_19_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_19_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_19_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_19_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_19_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_19_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_19_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_19_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_19_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_19_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_19_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_19_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_19_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_19_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_19_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_19_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_19_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_19_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_19_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_19_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_19_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_19_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_19_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_19_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_19_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_19_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_19_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_19_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_19_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_19_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_18_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_18_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_18_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_18_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_18_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_18_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_18_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_18_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40]
wire _router_sink_domain_18_auto_routers_source_nodes_out_3_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_18_auto_routers_source_nodes_out_3_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_18_auto_routers_source_nodes_out_3_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_18_auto_routers_source_nodes_out_3_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_18_auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_18_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_18_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_18_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_18_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_18_auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_18_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_18_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_18_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_18_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_18_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_18_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_18_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_18_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_18_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_18_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_18_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_18_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_18_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_18_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_18_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_18_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_18_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_18_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_18_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_18_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_18_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_18_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_18_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_18_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_18_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_18_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_18_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_18_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_18_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_18_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_18_auto_routers_dest_nodes_in_3_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_18_auto_routers_dest_nodes_in_3_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_18_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_18_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_18_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_18_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_18_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_18_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_17_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_17_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_17_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_17_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_17_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_17_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_17_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_17_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40]
wire _router_sink_domain_17_auto_routers_source_nodes_out_3_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_17_auto_routers_source_nodes_out_3_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_17_auto_routers_source_nodes_out_3_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_17_auto_routers_source_nodes_out_3_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_17_auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_17_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_17_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_17_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_17_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_17_auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_17_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_17_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_17_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_17_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_17_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_17_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_17_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_17_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_17_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_17_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_17_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_17_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_17_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_17_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_17_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_17_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_17_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_17_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_17_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_17_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_17_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_17_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_17_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_17_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_17_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_17_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_17_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_17_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_17_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_17_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_17_auto_routers_dest_nodes_in_3_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_17_auto_routers_dest_nodes_in_3_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_17_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_17_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_17_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_17_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_17_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_17_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_16_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_16_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_16_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_16_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_16_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_16_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire _router_sink_domain_16_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_16_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_16_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_16_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_16_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_16_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_16_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_16_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_16_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_16_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_16_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_16_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_16_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_16_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_16_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_16_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_16_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_16_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_16_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_16_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_16_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_16_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_16_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_16_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_16_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_16_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_16_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_16_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_16_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_16_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_16_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_16_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_16_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_16_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_16_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_16_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_14_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_14_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_14_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_14_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_14_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_14_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_14_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_14_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40]
wire _router_sink_domain_14_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_14_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_14_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_14_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_14_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_14_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_14_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_14_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_14_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_14_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_14_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_14_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_13_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_13_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_13_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_13_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_13_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_13_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_13_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_13_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40]
wire _router_sink_domain_13_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_13_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_13_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_13_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_13_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_13_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_13_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_13_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_13_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_13_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_13_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_13_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_11_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_11_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_11_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_11_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_11_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_11_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_11_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_11_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40]
wire _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_11_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_11_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_10_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_10_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_10_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_10_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_10_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_10_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_10_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_10_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_9_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_9_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_9_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_9_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_9_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_9_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_9_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_9_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_8_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_8_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_8_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_8_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_8_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_8_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_8_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_8_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40]
wire _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_8_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_8_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_7_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_7_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_7_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_7_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_7_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_7_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_7_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_7_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40]
wire _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_7_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_7_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_6_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_6_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_6_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_6_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_6_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_6_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_6_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_6_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_5_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_5_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_5_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_5_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_5_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_5_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_5_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_5_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_4_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_4_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_4_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_4_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_4_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_4_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_4_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_4_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40]
wire _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_4_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_4_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_3_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_3_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_3_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_3_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_3_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_3_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_2_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_2_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_2_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_2_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_2_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_2_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_2_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_2_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40]
wire _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_2_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_2_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_1_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_1_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_1_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_1_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_1_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_1_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_1_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_1_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40]
wire _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_1_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_1_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire _router_sink_domain_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [7:0] _router_sink_domain_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
reg [63:0] debug_va_stall_ctr; // @[NoC.scala:163:37]
reg [63:0] debug_sa_stall_ctr; // @[NoC.scala:164:37]
wire [63:0] debug_any_stall_ctr = debug_va_stall_ctr + debug_sa_stall_ctr; // @[NoC.scala:163:37, :164:37, :165:50]
always @(posedge clock) begin // @[NoC.scala:141:9]
if (reset) begin // @[NoC.scala:141:9]
debug_va_stall_ctr <= 64'h0; // @[NoC.scala:163:37]
debug_sa_stall_ctr <= 64'h0; // @[NoC.scala:164:37]
end
else begin // @[NoC.scala:141:9]
debug_va_stall_ctr <=
debug_va_stall_ctr
+ {61'h0,
_router_sink_domain_auto_routers_debug_out_va_stall_0 + _router_sink_domain_auto_routers_debug_out_va_stall_1 + _router_sink_domain_1_auto_routers_debug_out_va_stall_0 + _router_sink_domain_1_auto_routers_debug_out_va_stall_1 + _router_sink_domain_1_auto_routers_debug_out_va_stall_2 + _router_sink_domain_1_auto_routers_debug_out_va_stall_3 + _router_sink_domain_2_auto_routers_debug_out_va_stall_0 + _router_sink_domain_2_auto_routers_debug_out_va_stall_1 + _router_sink_domain_2_auto_routers_debug_out_va_stall_2 + _router_sink_domain_2_auto_routers_debug_out_va_stall_3 + _router_sink_domain_3_auto_routers_debug_out_va_stall_0 + _router_sink_domain_3_auto_routers_debug_out_va_stall_2 + _router_sink_domain_4_auto_routers_debug_out_va_stall_0 + _router_sink_domain_4_auto_routers_debug_out_va_stall_1 + _router_sink_domain_4_auto_routers_debug_out_va_stall_2 + _router_sink_domain_4_auto_routers_debug_out_va_stall_3 + _router_sink_domain_5_auto_routers_debug_out_va_stall_0 + _router_sink_domain_5_auto_routers_debug_out_va_stall_1 + _router_sink_domain_5_auto_routers_debug_out_va_stall_2 + _router_sink_domain_6_auto_routers_debug_out_va_stall_0 + _router_sink_domain_6_auto_routers_debug_out_va_stall_1 + _router_sink_domain_6_auto_routers_debug_out_va_stall_2 + _router_sink_domain_7_auto_routers_debug_out_va_stall_0 + _router_sink_domain_7_auto_routers_debug_out_va_stall_1 + _router_sink_domain_7_auto_routers_debug_out_va_stall_2 + _router_sink_domain_7_auto_routers_debug_out_va_stall_3 + _router_sink_domain_8_auto_routers_debug_out_va_stall_0 + _router_sink_domain_8_auto_routers_debug_out_va_stall_1 + _router_sink_domain_8_auto_routers_debug_out_va_stall_2 + _router_sink_domain_8_auto_routers_debug_out_va_stall_3 + _router_sink_domain_9_auto_routers_debug_out_va_stall_0 + _router_sink_domain_9_auto_routers_debug_out_va_stall_1 + _router_sink_domain_9_auto_routers_debug_out_va_stall_2 + _router_sink_domain_10_auto_routers_debug_out_va_stall_0 + _router_sink_domain_10_auto_routers_debug_out_va_stall_1
+ _router_sink_domain_10_auto_routers_debug_out_va_stall_2 + _router_sink_domain_11_auto_routers_debug_out_va_stall_0 + _router_sink_domain_11_auto_routers_debug_out_va_stall_1 + _router_sink_domain_11_auto_routers_debug_out_va_stall_2 + _router_sink_domain_11_auto_routers_debug_out_va_stall_3 + _router_sink_domain_13_auto_routers_debug_out_va_stall_0 + _router_sink_domain_13_auto_routers_debug_out_va_stall_1 + _router_sink_domain_13_auto_routers_debug_out_va_stall_2 + _router_sink_domain_13_auto_routers_debug_out_va_stall_3 + _router_sink_domain_14_auto_routers_debug_out_va_stall_0 + _router_sink_domain_14_auto_routers_debug_out_va_stall_1 + _router_sink_domain_14_auto_routers_debug_out_va_stall_2 + _router_sink_domain_14_auto_routers_debug_out_va_stall_3 + _router_sink_domain_16_auto_routers_debug_out_va_stall_0 + _router_sink_domain_16_auto_routers_debug_out_va_stall_1 + _router_sink_domain_16_auto_routers_debug_out_va_stall_2 + _router_sink_domain_17_auto_routers_debug_out_va_stall_0 + _router_sink_domain_17_auto_routers_debug_out_va_stall_1 + _router_sink_domain_17_auto_routers_debug_out_va_stall_2 + _router_sink_domain_17_auto_routers_debug_out_va_stall_3 + _router_sink_domain_18_auto_routers_debug_out_va_stall_0 + _router_sink_domain_18_auto_routers_debug_out_va_stall_1 + _router_sink_domain_18_auto_routers_debug_out_va_stall_2 + _router_sink_domain_18_auto_routers_debug_out_va_stall_3 + _router_sink_domain_19_auto_routers_debug_out_va_stall_0 + _router_sink_domain_19_auto_routers_debug_out_va_stall_1 + _router_sink_domain_19_auto_routers_debug_out_va_stall_2 + _router_sink_domain_20_auto_routers_debug_out_va_stall_0 + _router_sink_domain_20_auto_routers_debug_out_va_stall_1 + _router_sink_domain_20_auto_routers_debug_out_va_stall_2 + _router_sink_domain_20_auto_routers_debug_out_va_stall_3 + _router_sink_domain_21_auto_routers_debug_out_va_stall_0 + _router_sink_domain_21_auto_routers_debug_out_va_stall_1 + _router_sink_domain_21_auto_routers_debug_out_va_stall_2
+ _router_sink_domain_21_auto_routers_debug_out_va_stall_3 + _router_sink_domain_21_auto_routers_debug_out_va_stall_4 + _router_sink_domain_22_auto_routers_debug_out_va_stall_0 + _router_sink_domain_22_auto_routers_debug_out_va_stall_1 + _router_sink_domain_22_auto_routers_debug_out_va_stall_2 + _router_sink_domain_22_auto_routers_debug_out_va_stall_3 + _router_sink_domain_22_auto_routers_debug_out_va_stall_4 + _router_sink_domain_23_auto_routers_debug_out_va_stall_0 + _router_sink_domain_23_auto_routers_debug_out_va_stall_1 + _router_sink_domain_23_auto_routers_debug_out_va_stall_2 + _router_sink_domain_23_auto_routers_debug_out_va_stall_3 + _router_sink_domain_24_auto_routers_debug_out_va_stall_0 + _router_sink_domain_24_auto_routers_debug_out_va_stall_1 + _router_sink_domain_24_auto_routers_debug_out_va_stall_2 + _router_sink_domain_25_auto_routers_debug_out_va_stall_0 + _router_sink_domain_25_auto_routers_debug_out_va_stall_1 + _router_sink_domain_25_auto_routers_debug_out_va_stall_2 + _router_sink_domain_25_auto_routers_debug_out_va_stall_3 + _router_sink_domain_25_auto_routers_debug_out_va_stall_4 + _router_sink_domain_26_auto_routers_debug_out_va_stall_0 + _router_sink_domain_26_auto_routers_debug_out_va_stall_1 + _router_sink_domain_26_auto_routers_debug_out_va_stall_2 + _router_sink_domain_26_auto_routers_debug_out_va_stall_3 + _router_sink_domain_26_auto_routers_debug_out_va_stall_4 + _router_sink_domain_27_auto_routers_debug_out_va_stall_0 + _router_sink_domain_27_auto_routers_debug_out_va_stall_1 + _router_sink_domain_27_auto_routers_debug_out_va_stall_2 + _router_sink_domain_27_auto_routers_debug_out_va_stall_3 + _router_sink_domain_29_auto_routers_debug_out_va_stall_0 + _router_sink_domain_29_auto_routers_debug_out_va_stall_1 + _router_sink_domain_29_auto_routers_debug_out_va_stall_2 + _router_sink_domain_30_auto_routers_debug_out_va_stall_0 + _router_sink_domain_30_auto_routers_debug_out_va_stall_1 + _router_sink_domain_30_auto_routers_debug_out_va_stall_2
+ _router_sink_domain_30_auto_routers_debug_out_va_stall_3 + _router_sink_domain_31_auto_routers_debug_out_va_stall_0 + _router_sink_domain_31_auto_routers_debug_out_va_stall_1}; // @[NoC.scala:41:40, :163:37, :166:{46,91,104}]
debug_sa_stall_ctr <=
debug_sa_stall_ctr
+ {61'h0,
_router_sink_domain_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_1_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_1_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_1_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_1_auto_routers_debug_out_sa_stall_3 + _router_sink_domain_2_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_2_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_2_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_2_auto_routers_debug_out_sa_stall_3 + _router_sink_domain_3_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_3_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_4_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_4_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_4_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_4_auto_routers_debug_out_sa_stall_3 + _router_sink_domain_5_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_5_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_5_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_6_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_6_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_6_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_7_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_7_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_7_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_7_auto_routers_debug_out_sa_stall_3 + _router_sink_domain_8_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_8_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_8_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_8_auto_routers_debug_out_sa_stall_3 + _router_sink_domain_9_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_9_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_9_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_10_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_10_auto_routers_debug_out_sa_stall_1
+ _router_sink_domain_10_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_11_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_11_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_11_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_11_auto_routers_debug_out_sa_stall_3 + _router_sink_domain_13_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_13_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_13_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_13_auto_routers_debug_out_sa_stall_3 + _router_sink_domain_14_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_14_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_14_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_14_auto_routers_debug_out_sa_stall_3 + _router_sink_domain_16_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_16_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_16_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_17_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_17_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_17_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_17_auto_routers_debug_out_sa_stall_3 + _router_sink_domain_18_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_18_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_18_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_18_auto_routers_debug_out_sa_stall_3 + _router_sink_domain_19_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_19_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_19_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_20_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_20_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_20_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_20_auto_routers_debug_out_sa_stall_3 + _router_sink_domain_21_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_21_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_21_auto_routers_debug_out_sa_stall_2
+ _router_sink_domain_21_auto_routers_debug_out_sa_stall_3 + _router_sink_domain_21_auto_routers_debug_out_sa_stall_4 + _router_sink_domain_22_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_22_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_22_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_22_auto_routers_debug_out_sa_stall_3 + _router_sink_domain_22_auto_routers_debug_out_sa_stall_4 + _router_sink_domain_23_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_23_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_23_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_23_auto_routers_debug_out_sa_stall_3 + _router_sink_domain_24_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_24_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_24_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_25_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_25_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_25_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_25_auto_routers_debug_out_sa_stall_3 + _router_sink_domain_25_auto_routers_debug_out_sa_stall_4 + _router_sink_domain_26_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_26_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_26_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_26_auto_routers_debug_out_sa_stall_3 + _router_sink_domain_26_auto_routers_debug_out_sa_stall_4 + _router_sink_domain_27_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_27_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_27_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_27_auto_routers_debug_out_sa_stall_3 + _router_sink_domain_29_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_29_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_29_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_30_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_30_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_30_auto_routers_debug_out_sa_stall_2
+ _router_sink_domain_30_auto_routers_debug_out_sa_stall_3 + _router_sink_domain_31_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_31_auto_routers_debug_out_sa_stall_1}; // @[NoC.scala:41:40, :164:37, :167:{46,91,104}]
end
always @(posedge) |
Generate the Verilog code corresponding to this FIRRTL code module BoomMSHR_3 :
input clock : Clock
input reset : Reset
output io : { flip id : UInt, flip req_pri_val : UInt<1>, req_pri_rdy : UInt<1>, flip req_sec_val : UInt<1>, req_sec_rdy : UInt<1>, flip clear_prefetch : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<8>, mispredict_mask : UInt<8>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip exception : UInt<1>, flip rob_pnr_idx : UInt<5>, flip rob_head_idx : UInt<5>, flip req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<4>, sdq_id : UInt<5>}, flip req_is_probe : UInt<1>, idx : { valid : UInt<1>, bits : UInt}, way : { valid : UInt<1>, bits : UInt}, tag : { valid : UInt<1>, bits : UInt}, mem_acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip mem_grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, mem_finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}, flip prober_state : { valid : UInt<1>, bits : UInt<40>}, refill : { flip ready : UInt<1>, valid : UInt<1>, bits : { way_en : UInt<4>, addr : UInt<12>, wmask : UInt<1>, data : UInt<64>}}, meta_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<4>, tag : UInt<20>, data : { coh : { state : UInt<2>}, tag : UInt<20>}}}, meta_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<4>, tag : UInt<20>}}, flip meta_resp : { valid : UInt<1>, bits : { coh : { state : UInt<2>}, tag : UInt<20>}}, wb_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { tag : UInt<20>, idx : UInt<6>, source : UInt<2>, param : UInt<3>, way_en : UInt<4>, voluntary : UInt<1>}}, commit_val : UInt<1>, commit_addr : UInt<40>, commit_coh : { state : UInt<2>}, lb_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, offset : UInt<3>}}, flip lb_resp : UInt<64>, lb_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, offset : UInt<3>, data : UInt<64>}}, replay : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<4>, sdq_id : UInt<5>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, is_hella : UInt<1>}}, flip wb_resp : UInt<1>, probe_rdy : UInt<1>}
regreset state : UInt<5>, clock, reset, UInt<5>(0h0)
reg req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<4>, sdq_id : UInt<5>}, clock
node req_idx = bits(req.addr, 11, 6)
node req_tag = shr(req.addr, 12)
node _req_block_addr_T = shr(req.addr, 6)
node req_block_addr = shl(_req_block_addr_T, 6)
regreset req_needs_wb : UInt<1>, clock, reset, UInt<1>(0h0)
wire new_coh_meta : { state : UInt<2>}
connect new_coh_meta.state, UInt<2>(0h0)
regreset new_coh : { state : UInt<2>}, clock, reset, new_coh_meta
node _r_T = eq(UInt<5>(0h10), UInt<5>(0h10))
node _r_T_1 = mux(_r_T, UInt<2>(0h2), UInt<2>(0h2))
node _r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _r_T_3 = mux(_r_T_2, UInt<2>(0h1), _r_T_1)
node _r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _r_T_5 = mux(_r_T_4, UInt<2>(0h0), _r_T_3)
node _r_T_6 = cat(_r_T_5, req.old_meta.coh.state)
node _r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _r_T_19 = eq(_r_T_18, _r_T_6)
node _r_T_20 = mux(_r_T_19, UInt<1>(0h0), UInt<1>(0h0))
node _r_T_21 = mux(_r_T_19, UInt<3>(0h5), UInt<1>(0h0))
node _r_T_22 = mux(_r_T_19, UInt<2>(0h0), UInt<1>(0h0))
node _r_T_23 = eq(_r_T_17, _r_T_6)
node _r_T_24 = mux(_r_T_23, UInt<1>(0h0), _r_T_20)
node _r_T_25 = mux(_r_T_23, UInt<3>(0h2), _r_T_21)
node _r_T_26 = mux(_r_T_23, UInt<2>(0h0), _r_T_22)
node _r_T_27 = eq(_r_T_16, _r_T_6)
node _r_T_28 = mux(_r_T_27, UInt<1>(0h0), _r_T_24)
node _r_T_29 = mux(_r_T_27, UInt<3>(0h1), _r_T_25)
node _r_T_30 = mux(_r_T_27, UInt<2>(0h0), _r_T_26)
node _r_T_31 = eq(_r_T_15, _r_T_6)
node _r_T_32 = mux(_r_T_31, UInt<1>(0h1), _r_T_28)
node _r_T_33 = mux(_r_T_31, UInt<3>(0h1), _r_T_29)
node _r_T_34 = mux(_r_T_31, UInt<2>(0h0), _r_T_30)
node _r_T_35 = eq(_r_T_14, _r_T_6)
node _r_T_36 = mux(_r_T_35, UInt<1>(0h0), _r_T_32)
node _r_T_37 = mux(_r_T_35, UInt<3>(0h5), _r_T_33)
node _r_T_38 = mux(_r_T_35, UInt<2>(0h0), _r_T_34)
node _r_T_39 = eq(_r_T_13, _r_T_6)
node _r_T_40 = mux(_r_T_39, UInt<1>(0h0), _r_T_36)
node _r_T_41 = mux(_r_T_39, UInt<3>(0h4), _r_T_37)
node _r_T_42 = mux(_r_T_39, UInt<2>(0h1), _r_T_38)
node _r_T_43 = eq(_r_T_12, _r_T_6)
node _r_T_44 = mux(_r_T_43, UInt<1>(0h0), _r_T_40)
node _r_T_45 = mux(_r_T_43, UInt<3>(0h0), _r_T_41)
node _r_T_46 = mux(_r_T_43, UInt<2>(0h1), _r_T_42)
node _r_T_47 = eq(_r_T_11, _r_T_6)
node _r_T_48 = mux(_r_T_47, UInt<1>(0h1), _r_T_44)
node _r_T_49 = mux(_r_T_47, UInt<3>(0h0), _r_T_45)
node _r_T_50 = mux(_r_T_47, UInt<2>(0h1), _r_T_46)
node _r_T_51 = eq(_r_T_10, _r_T_6)
node _r_T_52 = mux(_r_T_51, UInt<1>(0h0), _r_T_48)
node _r_T_53 = mux(_r_T_51, UInt<3>(0h5), _r_T_49)
node _r_T_54 = mux(_r_T_51, UInt<2>(0h0), _r_T_50)
node _r_T_55 = eq(_r_T_9, _r_T_6)
node _r_T_56 = mux(_r_T_55, UInt<1>(0h0), _r_T_52)
node _r_T_57 = mux(_r_T_55, UInt<3>(0h4), _r_T_53)
node _r_T_58 = mux(_r_T_55, UInt<2>(0h1), _r_T_54)
node _r_T_59 = eq(_r_T_8, _r_T_6)
node _r_T_60 = mux(_r_T_59, UInt<1>(0h0), _r_T_56)
node _r_T_61 = mux(_r_T_59, UInt<3>(0h3), _r_T_57)
node _r_T_62 = mux(_r_T_59, UInt<2>(0h2), _r_T_58)
node _r_T_63 = eq(_r_T_7, _r_T_6)
node r_1 = mux(_r_T_63, UInt<1>(0h1), _r_T_60)
node shrink_param = mux(_r_T_63, UInt<3>(0h3), _r_T_61)
node r_3 = mux(_r_T_63, UInt<2>(0h2), _r_T_62)
wire coh_on_clear : { state : UInt<2>}
connect coh_on_clear.state, r_3
node _grow_param_r_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _grow_param_r_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _grow_param_r_c_cat_T_2 = or(_grow_param_r_c_cat_T, _grow_param_r_c_cat_T_1)
node _grow_param_r_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _grow_param_r_c_cat_T_4 = or(_grow_param_r_c_cat_T_2, _grow_param_r_c_cat_T_3)
node _grow_param_r_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _grow_param_r_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _grow_param_r_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _grow_param_r_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _grow_param_r_c_cat_T_9 = or(_grow_param_r_c_cat_T_5, _grow_param_r_c_cat_T_6)
node _grow_param_r_c_cat_T_10 = or(_grow_param_r_c_cat_T_9, _grow_param_r_c_cat_T_7)
node _grow_param_r_c_cat_T_11 = or(_grow_param_r_c_cat_T_10, _grow_param_r_c_cat_T_8)
node _grow_param_r_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _grow_param_r_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _grow_param_r_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _grow_param_r_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _grow_param_r_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _grow_param_r_c_cat_T_17 = or(_grow_param_r_c_cat_T_12, _grow_param_r_c_cat_T_13)
node _grow_param_r_c_cat_T_18 = or(_grow_param_r_c_cat_T_17, _grow_param_r_c_cat_T_14)
node _grow_param_r_c_cat_T_19 = or(_grow_param_r_c_cat_T_18, _grow_param_r_c_cat_T_15)
node _grow_param_r_c_cat_T_20 = or(_grow_param_r_c_cat_T_19, _grow_param_r_c_cat_T_16)
node _grow_param_r_c_cat_T_21 = or(_grow_param_r_c_cat_T_11, _grow_param_r_c_cat_T_20)
node _grow_param_r_c_cat_T_22 = or(_grow_param_r_c_cat_T_4, _grow_param_r_c_cat_T_21)
node _grow_param_r_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _grow_param_r_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _grow_param_r_c_cat_T_25 = or(_grow_param_r_c_cat_T_23, _grow_param_r_c_cat_T_24)
node _grow_param_r_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _grow_param_r_c_cat_T_27 = or(_grow_param_r_c_cat_T_25, _grow_param_r_c_cat_T_26)
node _grow_param_r_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _grow_param_r_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _grow_param_r_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _grow_param_r_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _grow_param_r_c_cat_T_32 = or(_grow_param_r_c_cat_T_28, _grow_param_r_c_cat_T_29)
node _grow_param_r_c_cat_T_33 = or(_grow_param_r_c_cat_T_32, _grow_param_r_c_cat_T_30)
node _grow_param_r_c_cat_T_34 = or(_grow_param_r_c_cat_T_33, _grow_param_r_c_cat_T_31)
node _grow_param_r_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _grow_param_r_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _grow_param_r_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _grow_param_r_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _grow_param_r_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _grow_param_r_c_cat_T_40 = or(_grow_param_r_c_cat_T_35, _grow_param_r_c_cat_T_36)
node _grow_param_r_c_cat_T_41 = or(_grow_param_r_c_cat_T_40, _grow_param_r_c_cat_T_37)
node _grow_param_r_c_cat_T_42 = or(_grow_param_r_c_cat_T_41, _grow_param_r_c_cat_T_38)
node _grow_param_r_c_cat_T_43 = or(_grow_param_r_c_cat_T_42, _grow_param_r_c_cat_T_39)
node _grow_param_r_c_cat_T_44 = or(_grow_param_r_c_cat_T_34, _grow_param_r_c_cat_T_43)
node _grow_param_r_c_cat_T_45 = or(_grow_param_r_c_cat_T_27, _grow_param_r_c_cat_T_44)
node _grow_param_r_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3))
node _grow_param_r_c_cat_T_47 = or(_grow_param_r_c_cat_T_45, _grow_param_r_c_cat_T_46)
node _grow_param_r_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _grow_param_r_c_cat_T_49 = or(_grow_param_r_c_cat_T_47, _grow_param_r_c_cat_T_48)
node grow_param_r_c = cat(_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49)
node _grow_param_r_T = cat(grow_param_r_c, new_coh.state)
node _grow_param_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_2 = cat(_grow_param_r_T_1, UInt<2>(0h3))
node _grow_param_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_4 = cat(_grow_param_r_T_3, UInt<2>(0h2))
node _grow_param_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_6 = cat(_grow_param_r_T_5, UInt<2>(0h1))
node _grow_param_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _grow_param_r_T_8 = cat(_grow_param_r_T_7, UInt<2>(0h3))
node _grow_param_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _grow_param_r_T_10 = cat(_grow_param_r_T_9, UInt<2>(0h2))
node _grow_param_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _grow_param_r_T_12 = cat(_grow_param_r_T_11, UInt<2>(0h3))
node _grow_param_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _grow_param_r_T_14 = cat(_grow_param_r_T_13, UInt<2>(0h2))
node _grow_param_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_16 = cat(_grow_param_r_T_15, UInt<2>(0h0))
node _grow_param_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _grow_param_r_T_18 = cat(_grow_param_r_T_17, UInt<2>(0h1))
node _grow_param_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _grow_param_r_T_20 = cat(_grow_param_r_T_19, UInt<2>(0h0))
node _grow_param_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _grow_param_r_T_22 = cat(_grow_param_r_T_21, UInt<2>(0h1))
node _grow_param_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _grow_param_r_T_24 = cat(_grow_param_r_T_23, UInt<2>(0h0))
node _grow_param_r_T_25 = eq(_grow_param_r_T_24, _grow_param_r_T)
node _grow_param_r_T_26 = mux(_grow_param_r_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_27 = mux(_grow_param_r_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _grow_param_r_T_28 = eq(_grow_param_r_T_22, _grow_param_r_T)
node _grow_param_r_T_29 = mux(_grow_param_r_T_28, UInt<1>(0h0), _grow_param_r_T_26)
node _grow_param_r_T_30 = mux(_grow_param_r_T_28, UInt<2>(0h2), _grow_param_r_T_27)
node _grow_param_r_T_31 = eq(_grow_param_r_T_20, _grow_param_r_T)
node _grow_param_r_T_32 = mux(_grow_param_r_T_31, UInt<1>(0h0), _grow_param_r_T_29)
node _grow_param_r_T_33 = mux(_grow_param_r_T_31, UInt<2>(0h1), _grow_param_r_T_30)
node _grow_param_r_T_34 = eq(_grow_param_r_T_18, _grow_param_r_T)
node _grow_param_r_T_35 = mux(_grow_param_r_T_34, UInt<1>(0h0), _grow_param_r_T_32)
node _grow_param_r_T_36 = mux(_grow_param_r_T_34, UInt<2>(0h2), _grow_param_r_T_33)
node _grow_param_r_T_37 = eq(_grow_param_r_T_16, _grow_param_r_T)
node _grow_param_r_T_38 = mux(_grow_param_r_T_37, UInt<1>(0h0), _grow_param_r_T_35)
node _grow_param_r_T_39 = mux(_grow_param_r_T_37, UInt<2>(0h0), _grow_param_r_T_36)
node _grow_param_r_T_40 = eq(_grow_param_r_T_14, _grow_param_r_T)
node _grow_param_r_T_41 = mux(_grow_param_r_T_40, UInt<1>(0h1), _grow_param_r_T_38)
node _grow_param_r_T_42 = mux(_grow_param_r_T_40, UInt<2>(0h3), _grow_param_r_T_39)
node _grow_param_r_T_43 = eq(_grow_param_r_T_12, _grow_param_r_T)
node _grow_param_r_T_44 = mux(_grow_param_r_T_43, UInt<1>(0h1), _grow_param_r_T_41)
node _grow_param_r_T_45 = mux(_grow_param_r_T_43, UInt<2>(0h3), _grow_param_r_T_42)
node _grow_param_r_T_46 = eq(_grow_param_r_T_10, _grow_param_r_T)
node _grow_param_r_T_47 = mux(_grow_param_r_T_46, UInt<1>(0h1), _grow_param_r_T_44)
node _grow_param_r_T_48 = mux(_grow_param_r_T_46, UInt<2>(0h2), _grow_param_r_T_45)
node _grow_param_r_T_49 = eq(_grow_param_r_T_8, _grow_param_r_T)
node _grow_param_r_T_50 = mux(_grow_param_r_T_49, UInt<1>(0h1), _grow_param_r_T_47)
node _grow_param_r_T_51 = mux(_grow_param_r_T_49, UInt<2>(0h3), _grow_param_r_T_48)
node _grow_param_r_T_52 = eq(_grow_param_r_T_6, _grow_param_r_T)
node _grow_param_r_T_53 = mux(_grow_param_r_T_52, UInt<1>(0h1), _grow_param_r_T_50)
node _grow_param_r_T_54 = mux(_grow_param_r_T_52, UInt<2>(0h1), _grow_param_r_T_51)
node _grow_param_r_T_55 = eq(_grow_param_r_T_4, _grow_param_r_T)
node _grow_param_r_T_56 = mux(_grow_param_r_T_55, UInt<1>(0h1), _grow_param_r_T_53)
node _grow_param_r_T_57 = mux(_grow_param_r_T_55, UInt<2>(0h2), _grow_param_r_T_54)
node _grow_param_r_T_58 = eq(_grow_param_r_T_2, _grow_param_r_T)
node grow_param_r_1 = mux(_grow_param_r_T_58, UInt<1>(0h1), _grow_param_r_T_56)
node grow_param = mux(_grow_param_r_T_58, UInt<2>(0h3), _grow_param_r_T_57)
wire grow_param_meta : { state : UInt<2>}
connect grow_param_meta.state, grow_param
node _coh_on_grant_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _coh_on_grant_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _coh_on_grant_c_cat_T_2 = or(_coh_on_grant_c_cat_T, _coh_on_grant_c_cat_T_1)
node _coh_on_grant_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _coh_on_grant_c_cat_T_4 = or(_coh_on_grant_c_cat_T_2, _coh_on_grant_c_cat_T_3)
node _coh_on_grant_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _coh_on_grant_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _coh_on_grant_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _coh_on_grant_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _coh_on_grant_c_cat_T_9 = or(_coh_on_grant_c_cat_T_5, _coh_on_grant_c_cat_T_6)
node _coh_on_grant_c_cat_T_10 = or(_coh_on_grant_c_cat_T_9, _coh_on_grant_c_cat_T_7)
node _coh_on_grant_c_cat_T_11 = or(_coh_on_grant_c_cat_T_10, _coh_on_grant_c_cat_T_8)
node _coh_on_grant_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _coh_on_grant_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _coh_on_grant_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _coh_on_grant_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _coh_on_grant_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _coh_on_grant_c_cat_T_17 = or(_coh_on_grant_c_cat_T_12, _coh_on_grant_c_cat_T_13)
node _coh_on_grant_c_cat_T_18 = or(_coh_on_grant_c_cat_T_17, _coh_on_grant_c_cat_T_14)
node _coh_on_grant_c_cat_T_19 = or(_coh_on_grant_c_cat_T_18, _coh_on_grant_c_cat_T_15)
node _coh_on_grant_c_cat_T_20 = or(_coh_on_grant_c_cat_T_19, _coh_on_grant_c_cat_T_16)
node _coh_on_grant_c_cat_T_21 = or(_coh_on_grant_c_cat_T_11, _coh_on_grant_c_cat_T_20)
node _coh_on_grant_c_cat_T_22 = or(_coh_on_grant_c_cat_T_4, _coh_on_grant_c_cat_T_21)
node _coh_on_grant_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _coh_on_grant_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _coh_on_grant_c_cat_T_25 = or(_coh_on_grant_c_cat_T_23, _coh_on_grant_c_cat_T_24)
node _coh_on_grant_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _coh_on_grant_c_cat_T_27 = or(_coh_on_grant_c_cat_T_25, _coh_on_grant_c_cat_T_26)
node _coh_on_grant_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _coh_on_grant_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _coh_on_grant_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _coh_on_grant_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _coh_on_grant_c_cat_T_32 = or(_coh_on_grant_c_cat_T_28, _coh_on_grant_c_cat_T_29)
node _coh_on_grant_c_cat_T_33 = or(_coh_on_grant_c_cat_T_32, _coh_on_grant_c_cat_T_30)
node _coh_on_grant_c_cat_T_34 = or(_coh_on_grant_c_cat_T_33, _coh_on_grant_c_cat_T_31)
node _coh_on_grant_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _coh_on_grant_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _coh_on_grant_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _coh_on_grant_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _coh_on_grant_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _coh_on_grant_c_cat_T_40 = or(_coh_on_grant_c_cat_T_35, _coh_on_grant_c_cat_T_36)
node _coh_on_grant_c_cat_T_41 = or(_coh_on_grant_c_cat_T_40, _coh_on_grant_c_cat_T_37)
node _coh_on_grant_c_cat_T_42 = or(_coh_on_grant_c_cat_T_41, _coh_on_grant_c_cat_T_38)
node _coh_on_grant_c_cat_T_43 = or(_coh_on_grant_c_cat_T_42, _coh_on_grant_c_cat_T_39)
node _coh_on_grant_c_cat_T_44 = or(_coh_on_grant_c_cat_T_34, _coh_on_grant_c_cat_T_43)
node _coh_on_grant_c_cat_T_45 = or(_coh_on_grant_c_cat_T_27, _coh_on_grant_c_cat_T_44)
node _coh_on_grant_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3))
node _coh_on_grant_c_cat_T_47 = or(_coh_on_grant_c_cat_T_45, _coh_on_grant_c_cat_T_46)
node _coh_on_grant_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _coh_on_grant_c_cat_T_49 = or(_coh_on_grant_c_cat_T_47, _coh_on_grant_c_cat_T_48)
node coh_on_grant_c = cat(_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49)
node _coh_on_grant_T = cat(coh_on_grant_c, io.mem_grant.bits.param)
node _coh_on_grant_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _coh_on_grant_T_2 = cat(_coh_on_grant_T_1, UInt<2>(0h1))
node _coh_on_grant_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _coh_on_grant_T_4 = cat(_coh_on_grant_T_3, UInt<2>(0h0))
node _coh_on_grant_T_5 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _coh_on_grant_T_6 = cat(_coh_on_grant_T_5, UInt<2>(0h0))
node _coh_on_grant_T_7 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _coh_on_grant_T_8 = cat(_coh_on_grant_T_7, UInt<2>(0h0))
node _coh_on_grant_T_9 = eq(_coh_on_grant_T_2, _coh_on_grant_T)
node _coh_on_grant_T_10 = mux(_coh_on_grant_T_9, UInt<2>(0h1), UInt<2>(0h0))
node _coh_on_grant_T_11 = eq(_coh_on_grant_T_4, _coh_on_grant_T)
node _coh_on_grant_T_12 = mux(_coh_on_grant_T_11, UInt<2>(0h2), _coh_on_grant_T_10)
node _coh_on_grant_T_13 = eq(_coh_on_grant_T_6, _coh_on_grant_T)
node _coh_on_grant_T_14 = mux(_coh_on_grant_T_13, UInt<2>(0h2), _coh_on_grant_T_12)
node _coh_on_grant_T_15 = eq(_coh_on_grant_T_8, _coh_on_grant_T)
node _coh_on_grant_T_16 = mux(_coh_on_grant_T_15, UInt<2>(0h3), _coh_on_grant_T_14)
wire coh_on_grant : { state : UInt<2>}
connect coh_on_grant.state, _coh_on_grant_T_16
node _r1_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _r1_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _r1_c_cat_T_2 = or(_r1_c_cat_T, _r1_c_cat_T_1)
node _r1_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _r1_c_cat_T_4 = or(_r1_c_cat_T_2, _r1_c_cat_T_3)
node _r1_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _r1_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _r1_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _r1_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _r1_c_cat_T_9 = or(_r1_c_cat_T_5, _r1_c_cat_T_6)
node _r1_c_cat_T_10 = or(_r1_c_cat_T_9, _r1_c_cat_T_7)
node _r1_c_cat_T_11 = or(_r1_c_cat_T_10, _r1_c_cat_T_8)
node _r1_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _r1_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _r1_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _r1_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _r1_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _r1_c_cat_T_17 = or(_r1_c_cat_T_12, _r1_c_cat_T_13)
node _r1_c_cat_T_18 = or(_r1_c_cat_T_17, _r1_c_cat_T_14)
node _r1_c_cat_T_19 = or(_r1_c_cat_T_18, _r1_c_cat_T_15)
node _r1_c_cat_T_20 = or(_r1_c_cat_T_19, _r1_c_cat_T_16)
node _r1_c_cat_T_21 = or(_r1_c_cat_T_11, _r1_c_cat_T_20)
node _r1_c_cat_T_22 = or(_r1_c_cat_T_4, _r1_c_cat_T_21)
node _r1_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _r1_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _r1_c_cat_T_25 = or(_r1_c_cat_T_23, _r1_c_cat_T_24)
node _r1_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _r1_c_cat_T_27 = or(_r1_c_cat_T_25, _r1_c_cat_T_26)
node _r1_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _r1_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _r1_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _r1_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _r1_c_cat_T_32 = or(_r1_c_cat_T_28, _r1_c_cat_T_29)
node _r1_c_cat_T_33 = or(_r1_c_cat_T_32, _r1_c_cat_T_30)
node _r1_c_cat_T_34 = or(_r1_c_cat_T_33, _r1_c_cat_T_31)
node _r1_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _r1_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _r1_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _r1_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _r1_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _r1_c_cat_T_40 = or(_r1_c_cat_T_35, _r1_c_cat_T_36)
node _r1_c_cat_T_41 = or(_r1_c_cat_T_40, _r1_c_cat_T_37)
node _r1_c_cat_T_42 = or(_r1_c_cat_T_41, _r1_c_cat_T_38)
node _r1_c_cat_T_43 = or(_r1_c_cat_T_42, _r1_c_cat_T_39)
node _r1_c_cat_T_44 = or(_r1_c_cat_T_34, _r1_c_cat_T_43)
node _r1_c_cat_T_45 = or(_r1_c_cat_T_27, _r1_c_cat_T_44)
node _r1_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3))
node _r1_c_cat_T_47 = or(_r1_c_cat_T_45, _r1_c_cat_T_46)
node _r1_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _r1_c_cat_T_49 = or(_r1_c_cat_T_47, _r1_c_cat_T_48)
node r1_c = cat(_r1_c_cat_T_22, _r1_c_cat_T_49)
node _r1_T = cat(r1_c, new_coh.state)
node _r1_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_2 = cat(_r1_T_1, UInt<2>(0h3))
node _r1_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_4 = cat(_r1_T_3, UInt<2>(0h2))
node _r1_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_6 = cat(_r1_T_5, UInt<2>(0h1))
node _r1_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r1_T_8 = cat(_r1_T_7, UInt<2>(0h3))
node _r1_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r1_T_10 = cat(_r1_T_9, UInt<2>(0h2))
node _r1_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r1_T_12 = cat(_r1_T_11, UInt<2>(0h3))
node _r1_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r1_T_14 = cat(_r1_T_13, UInt<2>(0h2))
node _r1_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_16 = cat(_r1_T_15, UInt<2>(0h0))
node _r1_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r1_T_18 = cat(_r1_T_17, UInt<2>(0h1))
node _r1_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r1_T_20 = cat(_r1_T_19, UInt<2>(0h0))
node _r1_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r1_T_22 = cat(_r1_T_21, UInt<2>(0h1))
node _r1_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r1_T_24 = cat(_r1_T_23, UInt<2>(0h0))
node _r1_T_25 = eq(_r1_T_24, _r1_T)
node _r1_T_26 = mux(_r1_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_27 = mux(_r1_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _r1_T_28 = eq(_r1_T_22, _r1_T)
node _r1_T_29 = mux(_r1_T_28, UInt<1>(0h0), _r1_T_26)
node _r1_T_30 = mux(_r1_T_28, UInt<2>(0h2), _r1_T_27)
node _r1_T_31 = eq(_r1_T_20, _r1_T)
node _r1_T_32 = mux(_r1_T_31, UInt<1>(0h0), _r1_T_29)
node _r1_T_33 = mux(_r1_T_31, UInt<2>(0h1), _r1_T_30)
node _r1_T_34 = eq(_r1_T_18, _r1_T)
node _r1_T_35 = mux(_r1_T_34, UInt<1>(0h0), _r1_T_32)
node _r1_T_36 = mux(_r1_T_34, UInt<2>(0h2), _r1_T_33)
node _r1_T_37 = eq(_r1_T_16, _r1_T)
node _r1_T_38 = mux(_r1_T_37, UInt<1>(0h0), _r1_T_35)
node _r1_T_39 = mux(_r1_T_37, UInt<2>(0h0), _r1_T_36)
node _r1_T_40 = eq(_r1_T_14, _r1_T)
node _r1_T_41 = mux(_r1_T_40, UInt<1>(0h1), _r1_T_38)
node _r1_T_42 = mux(_r1_T_40, UInt<2>(0h3), _r1_T_39)
node _r1_T_43 = eq(_r1_T_12, _r1_T)
node _r1_T_44 = mux(_r1_T_43, UInt<1>(0h1), _r1_T_41)
node _r1_T_45 = mux(_r1_T_43, UInt<2>(0h3), _r1_T_42)
node _r1_T_46 = eq(_r1_T_10, _r1_T)
node _r1_T_47 = mux(_r1_T_46, UInt<1>(0h1), _r1_T_44)
node _r1_T_48 = mux(_r1_T_46, UInt<2>(0h2), _r1_T_45)
node _r1_T_49 = eq(_r1_T_8, _r1_T)
node _r1_T_50 = mux(_r1_T_49, UInt<1>(0h1), _r1_T_47)
node _r1_T_51 = mux(_r1_T_49, UInt<2>(0h3), _r1_T_48)
node _r1_T_52 = eq(_r1_T_6, _r1_T)
node _r1_T_53 = mux(_r1_T_52, UInt<1>(0h1), _r1_T_50)
node _r1_T_54 = mux(_r1_T_52, UInt<2>(0h1), _r1_T_51)
node _r1_T_55 = eq(_r1_T_4, _r1_T)
node _r1_T_56 = mux(_r1_T_55, UInt<1>(0h1), _r1_T_53)
node _r1_T_57 = mux(_r1_T_55, UInt<2>(0h2), _r1_T_54)
node _r1_T_58 = eq(_r1_T_2, _r1_T)
node r1_1 = mux(_r1_T_58, UInt<1>(0h1), _r1_T_56)
node r1_2 = mux(_r1_T_58, UInt<2>(0h3), _r1_T_57)
node _r2_c_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _r2_c_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _r2_c_cat_T_2 = or(_r2_c_cat_T, _r2_c_cat_T_1)
node _r2_c_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _r2_c_cat_T_4 = or(_r2_c_cat_T_2, _r2_c_cat_T_3)
node _r2_c_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _r2_c_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _r2_c_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _r2_c_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _r2_c_cat_T_9 = or(_r2_c_cat_T_5, _r2_c_cat_T_6)
node _r2_c_cat_T_10 = or(_r2_c_cat_T_9, _r2_c_cat_T_7)
node _r2_c_cat_T_11 = or(_r2_c_cat_T_10, _r2_c_cat_T_8)
node _r2_c_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _r2_c_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _r2_c_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _r2_c_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _r2_c_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _r2_c_cat_T_17 = or(_r2_c_cat_T_12, _r2_c_cat_T_13)
node _r2_c_cat_T_18 = or(_r2_c_cat_T_17, _r2_c_cat_T_14)
node _r2_c_cat_T_19 = or(_r2_c_cat_T_18, _r2_c_cat_T_15)
node _r2_c_cat_T_20 = or(_r2_c_cat_T_19, _r2_c_cat_T_16)
node _r2_c_cat_T_21 = or(_r2_c_cat_T_11, _r2_c_cat_T_20)
node _r2_c_cat_T_22 = or(_r2_c_cat_T_4, _r2_c_cat_T_21)
node _r2_c_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _r2_c_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _r2_c_cat_T_25 = or(_r2_c_cat_T_23, _r2_c_cat_T_24)
node _r2_c_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _r2_c_cat_T_27 = or(_r2_c_cat_T_25, _r2_c_cat_T_26)
node _r2_c_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _r2_c_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _r2_c_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _r2_c_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _r2_c_cat_T_32 = or(_r2_c_cat_T_28, _r2_c_cat_T_29)
node _r2_c_cat_T_33 = or(_r2_c_cat_T_32, _r2_c_cat_T_30)
node _r2_c_cat_T_34 = or(_r2_c_cat_T_33, _r2_c_cat_T_31)
node _r2_c_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _r2_c_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _r2_c_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _r2_c_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _r2_c_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _r2_c_cat_T_40 = or(_r2_c_cat_T_35, _r2_c_cat_T_36)
node _r2_c_cat_T_41 = or(_r2_c_cat_T_40, _r2_c_cat_T_37)
node _r2_c_cat_T_42 = or(_r2_c_cat_T_41, _r2_c_cat_T_38)
node _r2_c_cat_T_43 = or(_r2_c_cat_T_42, _r2_c_cat_T_39)
node _r2_c_cat_T_44 = or(_r2_c_cat_T_34, _r2_c_cat_T_43)
node _r2_c_cat_T_45 = or(_r2_c_cat_T_27, _r2_c_cat_T_44)
node _r2_c_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _r2_c_cat_T_47 = or(_r2_c_cat_T_45, _r2_c_cat_T_46)
node _r2_c_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _r2_c_cat_T_49 = or(_r2_c_cat_T_47, _r2_c_cat_T_48)
node r2_c = cat(_r2_c_cat_T_22, _r2_c_cat_T_49)
node _r2_T = cat(r2_c, new_coh.state)
node _r2_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_2 = cat(_r2_T_1, UInt<2>(0h3))
node _r2_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_4 = cat(_r2_T_3, UInt<2>(0h2))
node _r2_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_6 = cat(_r2_T_5, UInt<2>(0h1))
node _r2_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r2_T_8 = cat(_r2_T_7, UInt<2>(0h3))
node _r2_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r2_T_10 = cat(_r2_T_9, UInt<2>(0h2))
node _r2_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r2_T_12 = cat(_r2_T_11, UInt<2>(0h3))
node _r2_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r2_T_14 = cat(_r2_T_13, UInt<2>(0h2))
node _r2_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_16 = cat(_r2_T_15, UInt<2>(0h0))
node _r2_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r2_T_18 = cat(_r2_T_17, UInt<2>(0h1))
node _r2_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r2_T_20 = cat(_r2_T_19, UInt<2>(0h0))
node _r2_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r2_T_22 = cat(_r2_T_21, UInt<2>(0h1))
node _r2_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r2_T_24 = cat(_r2_T_23, UInt<2>(0h0))
node _r2_T_25 = eq(_r2_T_24, _r2_T)
node _r2_T_26 = mux(_r2_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_27 = mux(_r2_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _r2_T_28 = eq(_r2_T_22, _r2_T)
node _r2_T_29 = mux(_r2_T_28, UInt<1>(0h0), _r2_T_26)
node _r2_T_30 = mux(_r2_T_28, UInt<2>(0h2), _r2_T_27)
node _r2_T_31 = eq(_r2_T_20, _r2_T)
node _r2_T_32 = mux(_r2_T_31, UInt<1>(0h0), _r2_T_29)
node _r2_T_33 = mux(_r2_T_31, UInt<2>(0h1), _r2_T_30)
node _r2_T_34 = eq(_r2_T_18, _r2_T)
node _r2_T_35 = mux(_r2_T_34, UInt<1>(0h0), _r2_T_32)
node _r2_T_36 = mux(_r2_T_34, UInt<2>(0h2), _r2_T_33)
node _r2_T_37 = eq(_r2_T_16, _r2_T)
node _r2_T_38 = mux(_r2_T_37, UInt<1>(0h0), _r2_T_35)
node _r2_T_39 = mux(_r2_T_37, UInt<2>(0h0), _r2_T_36)
node _r2_T_40 = eq(_r2_T_14, _r2_T)
node _r2_T_41 = mux(_r2_T_40, UInt<1>(0h1), _r2_T_38)
node _r2_T_42 = mux(_r2_T_40, UInt<2>(0h3), _r2_T_39)
node _r2_T_43 = eq(_r2_T_12, _r2_T)
node _r2_T_44 = mux(_r2_T_43, UInt<1>(0h1), _r2_T_41)
node _r2_T_45 = mux(_r2_T_43, UInt<2>(0h3), _r2_T_42)
node _r2_T_46 = eq(_r2_T_10, _r2_T)
node _r2_T_47 = mux(_r2_T_46, UInt<1>(0h1), _r2_T_44)
node _r2_T_48 = mux(_r2_T_46, UInt<2>(0h2), _r2_T_45)
node _r2_T_49 = eq(_r2_T_8, _r2_T)
node _r2_T_50 = mux(_r2_T_49, UInt<1>(0h1), _r2_T_47)
node _r2_T_51 = mux(_r2_T_49, UInt<2>(0h3), _r2_T_48)
node _r2_T_52 = eq(_r2_T_6, _r2_T)
node _r2_T_53 = mux(_r2_T_52, UInt<1>(0h1), _r2_T_50)
node _r2_T_54 = mux(_r2_T_52, UInt<2>(0h1), _r2_T_51)
node _r2_T_55 = eq(_r2_T_4, _r2_T)
node _r2_T_56 = mux(_r2_T_55, UInt<1>(0h1), _r2_T_53)
node _r2_T_57 = mux(_r2_T_55, UInt<2>(0h2), _r2_T_54)
node _r2_T_58 = eq(_r2_T_2, _r2_T)
node r2_1 = mux(_r2_T_58, UInt<1>(0h1), _r2_T_56)
node r2_2 = mux(_r2_T_58, UInt<2>(0h3), _r2_T_57)
node _needs_second_acq_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _needs_second_acq_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _needs_second_acq_T_2 = or(_needs_second_acq_T, _needs_second_acq_T_1)
node _needs_second_acq_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _needs_second_acq_T_4 = or(_needs_second_acq_T_2, _needs_second_acq_T_3)
node _needs_second_acq_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _needs_second_acq_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _needs_second_acq_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _needs_second_acq_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _needs_second_acq_T_9 = or(_needs_second_acq_T_5, _needs_second_acq_T_6)
node _needs_second_acq_T_10 = or(_needs_second_acq_T_9, _needs_second_acq_T_7)
node _needs_second_acq_T_11 = or(_needs_second_acq_T_10, _needs_second_acq_T_8)
node _needs_second_acq_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _needs_second_acq_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _needs_second_acq_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _needs_second_acq_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _needs_second_acq_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _needs_second_acq_T_17 = or(_needs_second_acq_T_12, _needs_second_acq_T_13)
node _needs_second_acq_T_18 = or(_needs_second_acq_T_17, _needs_second_acq_T_14)
node _needs_second_acq_T_19 = or(_needs_second_acq_T_18, _needs_second_acq_T_15)
node _needs_second_acq_T_20 = or(_needs_second_acq_T_19, _needs_second_acq_T_16)
node _needs_second_acq_T_21 = or(_needs_second_acq_T_11, _needs_second_acq_T_20)
node _needs_second_acq_T_22 = or(_needs_second_acq_T_4, _needs_second_acq_T_21)
node _needs_second_acq_T_23 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _needs_second_acq_T_24 = or(_needs_second_acq_T_22, _needs_second_acq_T_23)
node _needs_second_acq_T_25 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _needs_second_acq_T_26 = or(_needs_second_acq_T_24, _needs_second_acq_T_25)
node _needs_second_acq_T_27 = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _needs_second_acq_T_28 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _needs_second_acq_T_29 = or(_needs_second_acq_T_27, _needs_second_acq_T_28)
node _needs_second_acq_T_30 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _needs_second_acq_T_31 = or(_needs_second_acq_T_29, _needs_second_acq_T_30)
node _needs_second_acq_T_32 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _needs_second_acq_T_33 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _needs_second_acq_T_34 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _needs_second_acq_T_35 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _needs_second_acq_T_36 = or(_needs_second_acq_T_32, _needs_second_acq_T_33)
node _needs_second_acq_T_37 = or(_needs_second_acq_T_36, _needs_second_acq_T_34)
node _needs_second_acq_T_38 = or(_needs_second_acq_T_37, _needs_second_acq_T_35)
node _needs_second_acq_T_39 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _needs_second_acq_T_40 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _needs_second_acq_T_41 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _needs_second_acq_T_42 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _needs_second_acq_T_43 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _needs_second_acq_T_44 = or(_needs_second_acq_T_39, _needs_second_acq_T_40)
node _needs_second_acq_T_45 = or(_needs_second_acq_T_44, _needs_second_acq_T_41)
node _needs_second_acq_T_46 = or(_needs_second_acq_T_45, _needs_second_acq_T_42)
node _needs_second_acq_T_47 = or(_needs_second_acq_T_46, _needs_second_acq_T_43)
node _needs_second_acq_T_48 = or(_needs_second_acq_T_38, _needs_second_acq_T_47)
node _needs_second_acq_T_49 = or(_needs_second_acq_T_31, _needs_second_acq_T_48)
node _needs_second_acq_T_50 = eq(req.uop.mem_cmd, UInt<2>(0h3))
node _needs_second_acq_T_51 = or(_needs_second_acq_T_49, _needs_second_acq_T_50)
node _needs_second_acq_T_52 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _needs_second_acq_T_53 = or(_needs_second_acq_T_51, _needs_second_acq_T_52)
node _needs_second_acq_T_54 = eq(_needs_second_acq_T_53, UInt<1>(0h0))
node cmd_requires_second_acquire = and(_needs_second_acq_T_26, _needs_second_acq_T_54)
node is_hit_again = and(r1_1, r2_1)
node _dirties_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _dirties_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _dirties_cat_T_2 = or(_dirties_cat_T, _dirties_cat_T_1)
node _dirties_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _dirties_cat_T_4 = or(_dirties_cat_T_2, _dirties_cat_T_3)
node _dirties_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _dirties_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _dirties_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _dirties_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _dirties_cat_T_9 = or(_dirties_cat_T_5, _dirties_cat_T_6)
node _dirties_cat_T_10 = or(_dirties_cat_T_9, _dirties_cat_T_7)
node _dirties_cat_T_11 = or(_dirties_cat_T_10, _dirties_cat_T_8)
node _dirties_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _dirties_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _dirties_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _dirties_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _dirties_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _dirties_cat_T_17 = or(_dirties_cat_T_12, _dirties_cat_T_13)
node _dirties_cat_T_18 = or(_dirties_cat_T_17, _dirties_cat_T_14)
node _dirties_cat_T_19 = or(_dirties_cat_T_18, _dirties_cat_T_15)
node _dirties_cat_T_20 = or(_dirties_cat_T_19, _dirties_cat_T_16)
node _dirties_cat_T_21 = or(_dirties_cat_T_11, _dirties_cat_T_20)
node _dirties_cat_T_22 = or(_dirties_cat_T_4, _dirties_cat_T_21)
node _dirties_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _dirties_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _dirties_cat_T_25 = or(_dirties_cat_T_23, _dirties_cat_T_24)
node _dirties_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _dirties_cat_T_27 = or(_dirties_cat_T_25, _dirties_cat_T_26)
node _dirties_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _dirties_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _dirties_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _dirties_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _dirties_cat_T_32 = or(_dirties_cat_T_28, _dirties_cat_T_29)
node _dirties_cat_T_33 = or(_dirties_cat_T_32, _dirties_cat_T_30)
node _dirties_cat_T_34 = or(_dirties_cat_T_33, _dirties_cat_T_31)
node _dirties_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _dirties_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _dirties_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _dirties_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _dirties_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _dirties_cat_T_40 = or(_dirties_cat_T_35, _dirties_cat_T_36)
node _dirties_cat_T_41 = or(_dirties_cat_T_40, _dirties_cat_T_37)
node _dirties_cat_T_42 = or(_dirties_cat_T_41, _dirties_cat_T_38)
node _dirties_cat_T_43 = or(_dirties_cat_T_42, _dirties_cat_T_39)
node _dirties_cat_T_44 = or(_dirties_cat_T_34, _dirties_cat_T_43)
node _dirties_cat_T_45 = or(_dirties_cat_T_27, _dirties_cat_T_44)
node _dirties_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _dirties_cat_T_47 = or(_dirties_cat_T_45, _dirties_cat_T_46)
node _dirties_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _dirties_cat_T_49 = or(_dirties_cat_T_47, _dirties_cat_T_48)
node dirties_cat = cat(_dirties_cat_T_22, _dirties_cat_T_49)
node _dirties_T = cat(UInt<1>(0h1), UInt<1>(0h1))
node dirties = eq(dirties_cat, _dirties_T)
node biggest_grow_param = mux(dirties, r2_2, r1_2)
wire dirtier_coh : { state : UInt<2>}
connect dirtier_coh.state, biggest_grow_param
node dirtier_cmd = mux(dirties, io.req.uop.mem_cmd, req.uop.mem_cmd)
node _T = and(io.mem_grant.ready, io.mem_grant.valid)
node _r_beats1_decode_T = dshl(UInt<12>(0hfff), io.mem_grant.bits.size)
node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 11, 0)
node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1)
node r_beats1_decode = shr(_r_beats1_decode_T_2, 3)
node r_beats1_opdata = bits(io.mem_grant.bits.opcode, 0, 0)
node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0))
regreset r_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _r_counter1_T = sub(r_counter, UInt<1>(0h1))
node r_counter1 = tail(_r_counter1_T, 1)
node r_1_1 = eq(r_counter, UInt<1>(0h0))
node _r_last_T = eq(r_counter, UInt<1>(0h1))
node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0))
node r_2 = or(_r_last_T, _r_last_T_1)
node refill_done = and(r_2, _T)
node _r_count_T = not(r_counter1)
node r_4 = and(r_beats1, _r_count_T)
when _T :
node _r_counter_T = mux(r_1_1, r_beats1, r_counter1)
connect r_counter, _r_counter_T
node refill_address_inc = shl(r_4, 3)
node _sec_rdy_T = eq(cmd_requires_second_acquire, UInt<1>(0h0))
node _sec_rdy_T_1 = eq(io.req_is_probe, UInt<1>(0h0))
node _sec_rdy_T_2 = and(_sec_rdy_T, _sec_rdy_T_1)
node _sec_rdy_T_3 = eq(state, UInt<5>(0h0))
node _sec_rdy_T_4 = eq(state, UInt<5>(0hd))
node _sec_rdy_T_5 = eq(state, UInt<5>(0he))
node _sec_rdy_T_6 = eq(state, UInt<5>(0hf))
node _sec_rdy_T_7 = or(_sec_rdy_T_3, _sec_rdy_T_4)
node _sec_rdy_T_8 = or(_sec_rdy_T_7, _sec_rdy_T_5)
node _sec_rdy_T_9 = or(_sec_rdy_T_8, _sec_rdy_T_6)
node _sec_rdy_T_10 = eq(_sec_rdy_T_9, UInt<1>(0h0))
node sec_rdy = and(_sec_rdy_T_2, _sec_rdy_T_10)
inst rpq of BranchKillableQueue_7
connect rpq.clock, clock
connect rpq.reset, reset
connect rpq.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect rpq.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect rpq.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect rpq.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect rpq.io.brupdate.b2.taken, io.brupdate.b2.taken
connect rpq.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect rpq.io.brupdate.b2.valid, io.brupdate.b2.valid
connect rpq.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect rpq.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect rpq.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect rpq.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect rpq.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect rpq.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect rpq.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect rpq.io.brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect rpq.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect rpq.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect rpq.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect rpq.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect rpq.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect rpq.io.brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect rpq.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect rpq.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect rpq.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect rpq.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect rpq.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect rpq.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect rpq.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect rpq.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect rpq.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect rpq.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect rpq.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect rpq.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect rpq.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect rpq.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect rpq.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect rpq.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect rpq.io.brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect rpq.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect rpq.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect rpq.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect rpq.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect rpq.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect rpq.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect rpq.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect rpq.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect rpq.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect rpq.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect rpq.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect rpq.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect rpq.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect rpq.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect rpq.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect rpq.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect rpq.io.brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect rpq.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect rpq.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect rpq.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect rpq.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect rpq.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect rpq.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect rpq.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect rpq.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect rpq.io.brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect rpq.io.brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect rpq.io.brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect rpq.io.brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect rpq.io.brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect rpq.io.brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect rpq.io.brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect rpq.io.brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect rpq.io.brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect rpq.io.brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect rpq.io.brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect rpq.io.brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect rpq.io.brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect rpq.io.brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect rpq.io.brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect rpq.io.brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect rpq.io.brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect rpq.io.brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect rpq.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect rpq.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect rpq.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect rpq.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect rpq.io.brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect rpq.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect rpq.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect rpq.io.flush, io.exception
node _T_1 = eq(state, UInt<5>(0h0))
node _T_2 = eq(rpq.io.empty, UInt<1>(0h0))
node _T_3 = and(_T_1, _T_2)
node _T_4 = eq(_T_3, UInt<1>(0h0))
node _T_5 = asUInt(reset)
node _T_6 = eq(_T_5, UInt<1>(0h0))
when _T_6 :
node _T_7 = eq(_T_4, UInt<1>(0h0))
when _T_7 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:131 assert(!(state === s_invalid && !rpq.io.empty))\n") : printf
assert(clock, _T_4, UInt<1>(0h1), "") : assert
node _rpq_io_enq_valid_T = and(io.req_pri_val, io.req_pri_rdy)
node _rpq_io_enq_valid_T_1 = and(io.req_sec_val, io.req_sec_rdy)
node _rpq_io_enq_valid_T_2 = or(_rpq_io_enq_valid_T, _rpq_io_enq_valid_T_1)
node _rpq_io_enq_valid_T_3 = eq(io.req.uop.mem_cmd, UInt<2>(0h2))
node _rpq_io_enq_valid_T_4 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _rpq_io_enq_valid_T_5 = or(_rpq_io_enq_valid_T_3, _rpq_io_enq_valid_T_4)
node _rpq_io_enq_valid_T_6 = eq(_rpq_io_enq_valid_T_5, UInt<1>(0h0))
node _rpq_io_enq_valid_T_7 = and(_rpq_io_enq_valid_T_2, _rpq_io_enq_valid_T_6)
connect rpq.io.enq.valid, _rpq_io_enq_valid_T_7
connect rpq.io.enq.bits.sdq_id, io.req.sdq_id
connect rpq.io.enq.bits.way_en, io.req.way_en
connect rpq.io.enq.bits.old_meta.tag, io.req.old_meta.tag
connect rpq.io.enq.bits.old_meta.coh.state, io.req.old_meta.coh.state
connect rpq.io.enq.bits.tag_match, io.req.tag_match
connect rpq.io.enq.bits.is_hella, io.req.is_hella
connect rpq.io.enq.bits.data, io.req.data
connect rpq.io.enq.bits.addr, io.req.addr
connect rpq.io.enq.bits.uop.debug_tsrc, io.req.uop.debug_tsrc
connect rpq.io.enq.bits.uop.debug_fsrc, io.req.uop.debug_fsrc
connect rpq.io.enq.bits.uop.bp_xcpt_if, io.req.uop.bp_xcpt_if
connect rpq.io.enq.bits.uop.bp_debug_if, io.req.uop.bp_debug_if
connect rpq.io.enq.bits.uop.xcpt_ma_if, io.req.uop.xcpt_ma_if
connect rpq.io.enq.bits.uop.xcpt_ae_if, io.req.uop.xcpt_ae_if
connect rpq.io.enq.bits.uop.xcpt_pf_if, io.req.uop.xcpt_pf_if
connect rpq.io.enq.bits.uop.fp_single, io.req.uop.fp_single
connect rpq.io.enq.bits.uop.fp_val, io.req.uop.fp_val
connect rpq.io.enq.bits.uop.frs3_en, io.req.uop.frs3_en
connect rpq.io.enq.bits.uop.lrs2_rtype, io.req.uop.lrs2_rtype
connect rpq.io.enq.bits.uop.lrs1_rtype, io.req.uop.lrs1_rtype
connect rpq.io.enq.bits.uop.dst_rtype, io.req.uop.dst_rtype
connect rpq.io.enq.bits.uop.ldst_val, io.req.uop.ldst_val
connect rpq.io.enq.bits.uop.lrs3, io.req.uop.lrs3
connect rpq.io.enq.bits.uop.lrs2, io.req.uop.lrs2
connect rpq.io.enq.bits.uop.lrs1, io.req.uop.lrs1
connect rpq.io.enq.bits.uop.ldst, io.req.uop.ldst
connect rpq.io.enq.bits.uop.ldst_is_rs1, io.req.uop.ldst_is_rs1
connect rpq.io.enq.bits.uop.flush_on_commit, io.req.uop.flush_on_commit
connect rpq.io.enq.bits.uop.is_unique, io.req.uop.is_unique
connect rpq.io.enq.bits.uop.is_sys_pc2epc, io.req.uop.is_sys_pc2epc
connect rpq.io.enq.bits.uop.uses_stq, io.req.uop.uses_stq
connect rpq.io.enq.bits.uop.uses_ldq, io.req.uop.uses_ldq
connect rpq.io.enq.bits.uop.is_amo, io.req.uop.is_amo
connect rpq.io.enq.bits.uop.is_fencei, io.req.uop.is_fencei
connect rpq.io.enq.bits.uop.is_fence, io.req.uop.is_fence
connect rpq.io.enq.bits.uop.mem_signed, io.req.uop.mem_signed
connect rpq.io.enq.bits.uop.mem_size, io.req.uop.mem_size
connect rpq.io.enq.bits.uop.mem_cmd, io.req.uop.mem_cmd
connect rpq.io.enq.bits.uop.bypassable, io.req.uop.bypassable
connect rpq.io.enq.bits.uop.exc_cause, io.req.uop.exc_cause
connect rpq.io.enq.bits.uop.exception, io.req.uop.exception
connect rpq.io.enq.bits.uop.stale_pdst, io.req.uop.stale_pdst
connect rpq.io.enq.bits.uop.ppred_busy, io.req.uop.ppred_busy
connect rpq.io.enq.bits.uop.prs3_busy, io.req.uop.prs3_busy
connect rpq.io.enq.bits.uop.prs2_busy, io.req.uop.prs2_busy
connect rpq.io.enq.bits.uop.prs1_busy, io.req.uop.prs1_busy
connect rpq.io.enq.bits.uop.ppred, io.req.uop.ppred
connect rpq.io.enq.bits.uop.prs3, io.req.uop.prs3
connect rpq.io.enq.bits.uop.prs2, io.req.uop.prs2
connect rpq.io.enq.bits.uop.prs1, io.req.uop.prs1
connect rpq.io.enq.bits.uop.pdst, io.req.uop.pdst
connect rpq.io.enq.bits.uop.rxq_idx, io.req.uop.rxq_idx
connect rpq.io.enq.bits.uop.stq_idx, io.req.uop.stq_idx
connect rpq.io.enq.bits.uop.ldq_idx, io.req.uop.ldq_idx
connect rpq.io.enq.bits.uop.rob_idx, io.req.uop.rob_idx
connect rpq.io.enq.bits.uop.csr_addr, io.req.uop.csr_addr
connect rpq.io.enq.bits.uop.imm_packed, io.req.uop.imm_packed
connect rpq.io.enq.bits.uop.taken, io.req.uop.taken
connect rpq.io.enq.bits.uop.pc_lob, io.req.uop.pc_lob
connect rpq.io.enq.bits.uop.edge_inst, io.req.uop.edge_inst
connect rpq.io.enq.bits.uop.ftq_idx, io.req.uop.ftq_idx
connect rpq.io.enq.bits.uop.br_tag, io.req.uop.br_tag
connect rpq.io.enq.bits.uop.br_mask, io.req.uop.br_mask
connect rpq.io.enq.bits.uop.is_sfb, io.req.uop.is_sfb
connect rpq.io.enq.bits.uop.is_jal, io.req.uop.is_jal
connect rpq.io.enq.bits.uop.is_jalr, io.req.uop.is_jalr
connect rpq.io.enq.bits.uop.is_br, io.req.uop.is_br
connect rpq.io.enq.bits.uop.iw_p2_poisoned, io.req.uop.iw_p2_poisoned
connect rpq.io.enq.bits.uop.iw_p1_poisoned, io.req.uop.iw_p1_poisoned
connect rpq.io.enq.bits.uop.iw_state, io.req.uop.iw_state
connect rpq.io.enq.bits.uop.ctrl.is_std, io.req.uop.ctrl.is_std
connect rpq.io.enq.bits.uop.ctrl.is_sta, io.req.uop.ctrl.is_sta
connect rpq.io.enq.bits.uop.ctrl.is_load, io.req.uop.ctrl.is_load
connect rpq.io.enq.bits.uop.ctrl.csr_cmd, io.req.uop.ctrl.csr_cmd
connect rpq.io.enq.bits.uop.ctrl.fcn_dw, io.req.uop.ctrl.fcn_dw
connect rpq.io.enq.bits.uop.ctrl.op_fcn, io.req.uop.ctrl.op_fcn
connect rpq.io.enq.bits.uop.ctrl.imm_sel, io.req.uop.ctrl.imm_sel
connect rpq.io.enq.bits.uop.ctrl.op2_sel, io.req.uop.ctrl.op2_sel
connect rpq.io.enq.bits.uop.ctrl.op1_sel, io.req.uop.ctrl.op1_sel
connect rpq.io.enq.bits.uop.ctrl.br_type, io.req.uop.ctrl.br_type
connect rpq.io.enq.bits.uop.fu_code, io.req.uop.fu_code
connect rpq.io.enq.bits.uop.iq_type, io.req.uop.iq_type
connect rpq.io.enq.bits.uop.debug_pc, io.req.uop.debug_pc
connect rpq.io.enq.bits.uop.is_rvc, io.req.uop.is_rvc
connect rpq.io.enq.bits.uop.debug_inst, io.req.uop.debug_inst
connect rpq.io.enq.bits.uop.inst, io.req.uop.inst
connect rpq.io.enq.bits.uop.uopc, io.req.uop.uopc
connect rpq.io.deq.ready, UInt<1>(0h0)
reg grantack : { valid : UInt<1>, bits : { sink : UInt<3>}}, clock
reg refill_ctr : UInt<3>, clock
reg commit_line : UInt<1>, clock
reg grant_had_data : UInt<1>, clock
reg finish_to_prefetch : UInt<1>, clock
regreset meta_hazard : UInt<2>, clock, reset, UInt<2>(0h0)
node _T_8 = neq(meta_hazard, UInt<1>(0h0))
when _T_8 :
node _meta_hazard_T = add(meta_hazard, UInt<1>(0h1))
node _meta_hazard_T_1 = tail(_meta_hazard_T, 1)
connect meta_hazard, _meta_hazard_T_1
node _T_9 = and(io.meta_write.ready, io.meta_write.valid)
when _T_9 :
connect meta_hazard, UInt<1>(0h1)
node _io_probe_rdy_T = eq(meta_hazard, UInt<1>(0h0))
node _io_probe_rdy_T_1 = eq(state, UInt<5>(0h0))
node _io_probe_rdy_T_2 = eq(state, UInt<5>(0h1))
node _io_probe_rdy_T_3 = eq(state, UInt<5>(0h2))
node _io_probe_rdy_T_4 = eq(state, UInt<5>(0h3))
node _io_probe_rdy_T_5 = or(_io_probe_rdy_T_1, _io_probe_rdy_T_2)
node _io_probe_rdy_T_6 = or(_io_probe_rdy_T_5, _io_probe_rdy_T_3)
node _io_probe_rdy_T_7 = or(_io_probe_rdy_T_6, _io_probe_rdy_T_4)
node _io_probe_rdy_T_8 = eq(state, UInt<5>(0h4))
node _io_probe_rdy_T_9 = and(_io_probe_rdy_T_8, grantack.valid)
node _io_probe_rdy_T_10 = or(_io_probe_rdy_T_7, _io_probe_rdy_T_9)
node _io_probe_rdy_T_11 = and(_io_probe_rdy_T, _io_probe_rdy_T_10)
connect io.probe_rdy, _io_probe_rdy_T_11
node _io_idx_valid_T = neq(state, UInt<5>(0h0))
connect io.idx.valid, _io_idx_valid_T
node _io_tag_valid_T = neq(state, UInt<5>(0h0))
connect io.tag.valid, _io_tag_valid_T
node _io_way_valid_T = eq(state, UInt<5>(0h0))
node _io_way_valid_T_1 = eq(state, UInt<5>(0h11))
node _io_way_valid_T_2 = or(_io_way_valid_T, _io_way_valid_T_1)
node _io_way_valid_T_3 = eq(_io_way_valid_T_2, UInt<1>(0h0))
connect io.way.valid, _io_way_valid_T_3
connect io.idx.bits, req_idx
connect io.tag.bits, req_tag
connect io.way.bits, req.way_en
connect io.meta_write.valid, UInt<1>(0h0)
invalidate io.meta_write.bits.data.tag
invalidate io.meta_write.bits.data.coh.state
invalidate io.meta_write.bits.tag
invalidate io.meta_write.bits.way_en
invalidate io.meta_write.bits.idx
connect io.req_pri_rdy, UInt<1>(0h0)
node _io_req_sec_rdy_T = and(sec_rdy, rpq.io.enq.ready)
connect io.req_sec_rdy, _io_req_sec_rdy_T
connect io.mem_acquire.valid, UInt<1>(0h0)
invalidate io.mem_acquire.bits.corrupt
invalidate io.mem_acquire.bits.data
invalidate io.mem_acquire.bits.mask
invalidate io.mem_acquire.bits.address
invalidate io.mem_acquire.bits.source
invalidate io.mem_acquire.bits.size
invalidate io.mem_acquire.bits.param
invalidate io.mem_acquire.bits.opcode
connect io.refill.valid, UInt<1>(0h0)
invalidate io.refill.bits.data
invalidate io.refill.bits.wmask
invalidate io.refill.bits.addr
invalidate io.refill.bits.way_en
connect io.replay.valid, UInt<1>(0h0)
invalidate io.replay.bits.sdq_id
invalidate io.replay.bits.way_en
invalidate io.replay.bits.old_meta.tag
invalidate io.replay.bits.old_meta.coh.state
invalidate io.replay.bits.tag_match
invalidate io.replay.bits.is_hella
invalidate io.replay.bits.data
invalidate io.replay.bits.addr
invalidate io.replay.bits.uop.debug_tsrc
invalidate io.replay.bits.uop.debug_fsrc
invalidate io.replay.bits.uop.bp_xcpt_if
invalidate io.replay.bits.uop.bp_debug_if
invalidate io.replay.bits.uop.xcpt_ma_if
invalidate io.replay.bits.uop.xcpt_ae_if
invalidate io.replay.bits.uop.xcpt_pf_if
invalidate io.replay.bits.uop.fp_single
invalidate io.replay.bits.uop.fp_val
invalidate io.replay.bits.uop.frs3_en
invalidate io.replay.bits.uop.lrs2_rtype
invalidate io.replay.bits.uop.lrs1_rtype
invalidate io.replay.bits.uop.dst_rtype
invalidate io.replay.bits.uop.ldst_val
invalidate io.replay.bits.uop.lrs3
invalidate io.replay.bits.uop.lrs2
invalidate io.replay.bits.uop.lrs1
invalidate io.replay.bits.uop.ldst
invalidate io.replay.bits.uop.ldst_is_rs1
invalidate io.replay.bits.uop.flush_on_commit
invalidate io.replay.bits.uop.is_unique
invalidate io.replay.bits.uop.is_sys_pc2epc
invalidate io.replay.bits.uop.uses_stq
invalidate io.replay.bits.uop.uses_ldq
invalidate io.replay.bits.uop.is_amo
invalidate io.replay.bits.uop.is_fencei
invalidate io.replay.bits.uop.is_fence
invalidate io.replay.bits.uop.mem_signed
invalidate io.replay.bits.uop.mem_size
invalidate io.replay.bits.uop.mem_cmd
invalidate io.replay.bits.uop.bypassable
invalidate io.replay.bits.uop.exc_cause
invalidate io.replay.bits.uop.exception
invalidate io.replay.bits.uop.stale_pdst
invalidate io.replay.bits.uop.ppred_busy
invalidate io.replay.bits.uop.prs3_busy
invalidate io.replay.bits.uop.prs2_busy
invalidate io.replay.bits.uop.prs1_busy
invalidate io.replay.bits.uop.ppred
invalidate io.replay.bits.uop.prs3
invalidate io.replay.bits.uop.prs2
invalidate io.replay.bits.uop.prs1
invalidate io.replay.bits.uop.pdst
invalidate io.replay.bits.uop.rxq_idx
invalidate io.replay.bits.uop.stq_idx
invalidate io.replay.bits.uop.ldq_idx
invalidate io.replay.bits.uop.rob_idx
invalidate io.replay.bits.uop.csr_addr
invalidate io.replay.bits.uop.imm_packed
invalidate io.replay.bits.uop.taken
invalidate io.replay.bits.uop.pc_lob
invalidate io.replay.bits.uop.edge_inst
invalidate io.replay.bits.uop.ftq_idx
invalidate io.replay.bits.uop.br_tag
invalidate io.replay.bits.uop.br_mask
invalidate io.replay.bits.uop.is_sfb
invalidate io.replay.bits.uop.is_jal
invalidate io.replay.bits.uop.is_jalr
invalidate io.replay.bits.uop.is_br
invalidate io.replay.bits.uop.iw_p2_poisoned
invalidate io.replay.bits.uop.iw_p1_poisoned
invalidate io.replay.bits.uop.iw_state
invalidate io.replay.bits.uop.ctrl.is_std
invalidate io.replay.bits.uop.ctrl.is_sta
invalidate io.replay.bits.uop.ctrl.is_load
invalidate io.replay.bits.uop.ctrl.csr_cmd
invalidate io.replay.bits.uop.ctrl.fcn_dw
invalidate io.replay.bits.uop.ctrl.op_fcn
invalidate io.replay.bits.uop.ctrl.imm_sel
invalidate io.replay.bits.uop.ctrl.op2_sel
invalidate io.replay.bits.uop.ctrl.op1_sel
invalidate io.replay.bits.uop.ctrl.br_type
invalidate io.replay.bits.uop.fu_code
invalidate io.replay.bits.uop.iq_type
invalidate io.replay.bits.uop.debug_pc
invalidate io.replay.bits.uop.is_rvc
invalidate io.replay.bits.uop.debug_inst
invalidate io.replay.bits.uop.inst
invalidate io.replay.bits.uop.uopc
connect io.wb_req.valid, UInt<1>(0h0)
invalidate io.wb_req.bits.voluntary
invalidate io.wb_req.bits.way_en
invalidate io.wb_req.bits.param
invalidate io.wb_req.bits.source
invalidate io.wb_req.bits.idx
invalidate io.wb_req.bits.tag
connect io.resp.valid, UInt<1>(0h0)
invalidate io.resp.bits.is_hella
invalidate io.resp.bits.data
invalidate io.resp.bits.uop.debug_tsrc
invalidate io.resp.bits.uop.debug_fsrc
invalidate io.resp.bits.uop.bp_xcpt_if
invalidate io.resp.bits.uop.bp_debug_if
invalidate io.resp.bits.uop.xcpt_ma_if
invalidate io.resp.bits.uop.xcpt_ae_if
invalidate io.resp.bits.uop.xcpt_pf_if
invalidate io.resp.bits.uop.fp_single
invalidate io.resp.bits.uop.fp_val
invalidate io.resp.bits.uop.frs3_en
invalidate io.resp.bits.uop.lrs2_rtype
invalidate io.resp.bits.uop.lrs1_rtype
invalidate io.resp.bits.uop.dst_rtype
invalidate io.resp.bits.uop.ldst_val
invalidate io.resp.bits.uop.lrs3
invalidate io.resp.bits.uop.lrs2
invalidate io.resp.bits.uop.lrs1
invalidate io.resp.bits.uop.ldst
invalidate io.resp.bits.uop.ldst_is_rs1
invalidate io.resp.bits.uop.flush_on_commit
invalidate io.resp.bits.uop.is_unique
invalidate io.resp.bits.uop.is_sys_pc2epc
invalidate io.resp.bits.uop.uses_stq
invalidate io.resp.bits.uop.uses_ldq
invalidate io.resp.bits.uop.is_amo
invalidate io.resp.bits.uop.is_fencei
invalidate io.resp.bits.uop.is_fence
invalidate io.resp.bits.uop.mem_signed
invalidate io.resp.bits.uop.mem_size
invalidate io.resp.bits.uop.mem_cmd
invalidate io.resp.bits.uop.bypassable
invalidate io.resp.bits.uop.exc_cause
invalidate io.resp.bits.uop.exception
invalidate io.resp.bits.uop.stale_pdst
invalidate io.resp.bits.uop.ppred_busy
invalidate io.resp.bits.uop.prs3_busy
invalidate io.resp.bits.uop.prs2_busy
invalidate io.resp.bits.uop.prs1_busy
invalidate io.resp.bits.uop.ppred
invalidate io.resp.bits.uop.prs3
invalidate io.resp.bits.uop.prs2
invalidate io.resp.bits.uop.prs1
invalidate io.resp.bits.uop.pdst
invalidate io.resp.bits.uop.rxq_idx
invalidate io.resp.bits.uop.stq_idx
invalidate io.resp.bits.uop.ldq_idx
invalidate io.resp.bits.uop.rob_idx
invalidate io.resp.bits.uop.csr_addr
invalidate io.resp.bits.uop.imm_packed
invalidate io.resp.bits.uop.taken
invalidate io.resp.bits.uop.pc_lob
invalidate io.resp.bits.uop.edge_inst
invalidate io.resp.bits.uop.ftq_idx
invalidate io.resp.bits.uop.br_tag
invalidate io.resp.bits.uop.br_mask
invalidate io.resp.bits.uop.is_sfb
invalidate io.resp.bits.uop.is_jal
invalidate io.resp.bits.uop.is_jalr
invalidate io.resp.bits.uop.is_br
invalidate io.resp.bits.uop.iw_p2_poisoned
invalidate io.resp.bits.uop.iw_p1_poisoned
invalidate io.resp.bits.uop.iw_state
invalidate io.resp.bits.uop.ctrl.is_std
invalidate io.resp.bits.uop.ctrl.is_sta
invalidate io.resp.bits.uop.ctrl.is_load
invalidate io.resp.bits.uop.ctrl.csr_cmd
invalidate io.resp.bits.uop.ctrl.fcn_dw
invalidate io.resp.bits.uop.ctrl.op_fcn
invalidate io.resp.bits.uop.ctrl.imm_sel
invalidate io.resp.bits.uop.ctrl.op2_sel
invalidate io.resp.bits.uop.ctrl.op1_sel
invalidate io.resp.bits.uop.ctrl.br_type
invalidate io.resp.bits.uop.fu_code
invalidate io.resp.bits.uop.iq_type
invalidate io.resp.bits.uop.debug_pc
invalidate io.resp.bits.uop.is_rvc
invalidate io.resp.bits.uop.debug_inst
invalidate io.resp.bits.uop.inst
invalidate io.resp.bits.uop.uopc
connect io.commit_val, UInt<1>(0h0)
connect io.commit_addr, req.addr
connect io.commit_coh, coh_on_grant
connect io.meta_read.valid, UInt<1>(0h0)
invalidate io.meta_read.bits.tag
invalidate io.meta_read.bits.way_en
invalidate io.meta_read.bits.idx
connect io.mem_finish.valid, UInt<1>(0h0)
invalidate io.mem_finish.bits.sink
connect io.lb_write.valid, UInt<1>(0h0)
invalidate io.lb_write.bits.data
invalidate io.lb_write.bits.offset
invalidate io.lb_write.bits.id
connect io.lb_read.valid, UInt<1>(0h0)
invalidate io.lb_read.bits.offset
invalidate io.lb_read.bits.id
connect io.mem_grant.ready, UInt<1>(0h0)
node _T_10 = and(io.req_sec_val, io.req_sec_rdy)
when _T_10 :
connect req.uop.mem_cmd, dirtier_cmd
when is_hit_again :
connect new_coh, dirtier_coh
node _T_11 = eq(state, UInt<5>(0h0))
when _T_11 :
connect io.req_pri_rdy, UInt<1>(0h1)
connect grant_had_data, UInt<1>(0h0)
node _T_12 = and(io.req_pri_val, io.req_pri_rdy)
when _T_12 :
wire state_new_state : UInt
connect state_new_state, state
connect grantack.valid, UInt<1>(0h0)
connect refill_ctr, UInt<1>(0h0)
node _state_T = asUInt(reset)
node _state_T_1 = eq(_state_T, UInt<1>(0h0))
when _state_T_1 :
node _state_T_2 = eq(rpq.io.enq.ready, UInt<1>(0h0))
when _state_T_2 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:194 assert(rpq.io.enq.ready)\n") : state_printf
assert(clock, rpq.io.enq.ready, UInt<1>(0h1), "") : state_assert
connect req, io.req
node _state_req_needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10))
node _state_req_needs_wb_r_T_1 = mux(_state_req_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2))
node _state_req_needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _state_req_needs_wb_r_T_3 = mux(_state_req_needs_wb_r_T_2, UInt<2>(0h1), _state_req_needs_wb_r_T_1)
node _state_req_needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _state_req_needs_wb_r_T_5 = mux(_state_req_needs_wb_r_T_4, UInt<2>(0h0), _state_req_needs_wb_r_T_3)
node _state_req_needs_wb_r_T_6 = cat(_state_req_needs_wb_r_T_5, io.req.old_meta.coh.state)
node _state_req_needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _state_req_needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _state_req_needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _state_req_needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _state_req_needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _state_req_needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _state_req_needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _state_req_needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _state_req_needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _state_req_needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _state_req_needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _state_req_needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _state_req_needs_wb_r_T_19 = eq(_state_req_needs_wb_r_T_18, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_20 = mux(_state_req_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0))
node _state_req_needs_wb_r_T_21 = mux(_state_req_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0))
node _state_req_needs_wb_r_T_22 = mux(_state_req_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0))
node _state_req_needs_wb_r_T_23 = eq(_state_req_needs_wb_r_T_17, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_24 = mux(_state_req_needs_wb_r_T_23, UInt<1>(0h0), _state_req_needs_wb_r_T_20)
node _state_req_needs_wb_r_T_25 = mux(_state_req_needs_wb_r_T_23, UInt<3>(0h2), _state_req_needs_wb_r_T_21)
node _state_req_needs_wb_r_T_26 = mux(_state_req_needs_wb_r_T_23, UInt<2>(0h0), _state_req_needs_wb_r_T_22)
node _state_req_needs_wb_r_T_27 = eq(_state_req_needs_wb_r_T_16, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_28 = mux(_state_req_needs_wb_r_T_27, UInt<1>(0h0), _state_req_needs_wb_r_T_24)
node _state_req_needs_wb_r_T_29 = mux(_state_req_needs_wb_r_T_27, UInt<3>(0h1), _state_req_needs_wb_r_T_25)
node _state_req_needs_wb_r_T_30 = mux(_state_req_needs_wb_r_T_27, UInt<2>(0h0), _state_req_needs_wb_r_T_26)
node _state_req_needs_wb_r_T_31 = eq(_state_req_needs_wb_r_T_15, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_32 = mux(_state_req_needs_wb_r_T_31, UInt<1>(0h1), _state_req_needs_wb_r_T_28)
node _state_req_needs_wb_r_T_33 = mux(_state_req_needs_wb_r_T_31, UInt<3>(0h1), _state_req_needs_wb_r_T_29)
node _state_req_needs_wb_r_T_34 = mux(_state_req_needs_wb_r_T_31, UInt<2>(0h0), _state_req_needs_wb_r_T_30)
node _state_req_needs_wb_r_T_35 = eq(_state_req_needs_wb_r_T_14, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_36 = mux(_state_req_needs_wb_r_T_35, UInt<1>(0h0), _state_req_needs_wb_r_T_32)
node _state_req_needs_wb_r_T_37 = mux(_state_req_needs_wb_r_T_35, UInt<3>(0h5), _state_req_needs_wb_r_T_33)
node _state_req_needs_wb_r_T_38 = mux(_state_req_needs_wb_r_T_35, UInt<2>(0h0), _state_req_needs_wb_r_T_34)
node _state_req_needs_wb_r_T_39 = eq(_state_req_needs_wb_r_T_13, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_40 = mux(_state_req_needs_wb_r_T_39, UInt<1>(0h0), _state_req_needs_wb_r_T_36)
node _state_req_needs_wb_r_T_41 = mux(_state_req_needs_wb_r_T_39, UInt<3>(0h4), _state_req_needs_wb_r_T_37)
node _state_req_needs_wb_r_T_42 = mux(_state_req_needs_wb_r_T_39, UInt<2>(0h1), _state_req_needs_wb_r_T_38)
node _state_req_needs_wb_r_T_43 = eq(_state_req_needs_wb_r_T_12, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_44 = mux(_state_req_needs_wb_r_T_43, UInt<1>(0h0), _state_req_needs_wb_r_T_40)
node _state_req_needs_wb_r_T_45 = mux(_state_req_needs_wb_r_T_43, UInt<3>(0h0), _state_req_needs_wb_r_T_41)
node _state_req_needs_wb_r_T_46 = mux(_state_req_needs_wb_r_T_43, UInt<2>(0h1), _state_req_needs_wb_r_T_42)
node _state_req_needs_wb_r_T_47 = eq(_state_req_needs_wb_r_T_11, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_48 = mux(_state_req_needs_wb_r_T_47, UInt<1>(0h1), _state_req_needs_wb_r_T_44)
node _state_req_needs_wb_r_T_49 = mux(_state_req_needs_wb_r_T_47, UInt<3>(0h0), _state_req_needs_wb_r_T_45)
node _state_req_needs_wb_r_T_50 = mux(_state_req_needs_wb_r_T_47, UInt<2>(0h1), _state_req_needs_wb_r_T_46)
node _state_req_needs_wb_r_T_51 = eq(_state_req_needs_wb_r_T_10, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_52 = mux(_state_req_needs_wb_r_T_51, UInt<1>(0h0), _state_req_needs_wb_r_T_48)
node _state_req_needs_wb_r_T_53 = mux(_state_req_needs_wb_r_T_51, UInt<3>(0h5), _state_req_needs_wb_r_T_49)
node _state_req_needs_wb_r_T_54 = mux(_state_req_needs_wb_r_T_51, UInt<2>(0h0), _state_req_needs_wb_r_T_50)
node _state_req_needs_wb_r_T_55 = eq(_state_req_needs_wb_r_T_9, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_56 = mux(_state_req_needs_wb_r_T_55, UInt<1>(0h0), _state_req_needs_wb_r_T_52)
node _state_req_needs_wb_r_T_57 = mux(_state_req_needs_wb_r_T_55, UInt<3>(0h4), _state_req_needs_wb_r_T_53)
node _state_req_needs_wb_r_T_58 = mux(_state_req_needs_wb_r_T_55, UInt<2>(0h1), _state_req_needs_wb_r_T_54)
node _state_req_needs_wb_r_T_59 = eq(_state_req_needs_wb_r_T_8, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_60 = mux(_state_req_needs_wb_r_T_59, UInt<1>(0h0), _state_req_needs_wb_r_T_56)
node _state_req_needs_wb_r_T_61 = mux(_state_req_needs_wb_r_T_59, UInt<3>(0h3), _state_req_needs_wb_r_T_57)
node _state_req_needs_wb_r_T_62 = mux(_state_req_needs_wb_r_T_59, UInt<2>(0h2), _state_req_needs_wb_r_T_58)
node _state_req_needs_wb_r_T_63 = eq(_state_req_needs_wb_r_T_7, _state_req_needs_wb_r_T_6)
node state_req_needs_wb_r_1 = mux(_state_req_needs_wb_r_T_63, UInt<1>(0h1), _state_req_needs_wb_r_T_60)
node state_req_needs_wb_r_2 = mux(_state_req_needs_wb_r_T_63, UInt<3>(0h3), _state_req_needs_wb_r_T_61)
node state_req_needs_wb_r_3 = mux(_state_req_needs_wb_r_T_63, UInt<2>(0h2), _state_req_needs_wb_r_T_62)
wire state_req_needs_wb_meta : { state : UInt<2>}
connect state_req_needs_wb_meta.state, state_req_needs_wb_r_3
connect req_needs_wb, state_req_needs_wb_r_1
when io.req.tag_match :
node _state_r_c_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_r_c_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_r_c_cat_T_2 = or(_state_r_c_cat_T, _state_r_c_cat_T_1)
node _state_r_c_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_r_c_cat_T_4 = or(_state_r_c_cat_T_2, _state_r_c_cat_T_3)
node _state_r_c_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_r_c_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_r_c_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_r_c_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_r_c_cat_T_9 = or(_state_r_c_cat_T_5, _state_r_c_cat_T_6)
node _state_r_c_cat_T_10 = or(_state_r_c_cat_T_9, _state_r_c_cat_T_7)
node _state_r_c_cat_T_11 = or(_state_r_c_cat_T_10, _state_r_c_cat_T_8)
node _state_r_c_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_r_c_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_r_c_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_r_c_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_r_c_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_r_c_cat_T_17 = or(_state_r_c_cat_T_12, _state_r_c_cat_T_13)
node _state_r_c_cat_T_18 = or(_state_r_c_cat_T_17, _state_r_c_cat_T_14)
node _state_r_c_cat_T_19 = or(_state_r_c_cat_T_18, _state_r_c_cat_T_15)
node _state_r_c_cat_T_20 = or(_state_r_c_cat_T_19, _state_r_c_cat_T_16)
node _state_r_c_cat_T_21 = or(_state_r_c_cat_T_11, _state_r_c_cat_T_20)
node _state_r_c_cat_T_22 = or(_state_r_c_cat_T_4, _state_r_c_cat_T_21)
node _state_r_c_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_r_c_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_r_c_cat_T_25 = or(_state_r_c_cat_T_23, _state_r_c_cat_T_24)
node _state_r_c_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_r_c_cat_T_27 = or(_state_r_c_cat_T_25, _state_r_c_cat_T_26)
node _state_r_c_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_r_c_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_r_c_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_r_c_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_r_c_cat_T_32 = or(_state_r_c_cat_T_28, _state_r_c_cat_T_29)
node _state_r_c_cat_T_33 = or(_state_r_c_cat_T_32, _state_r_c_cat_T_30)
node _state_r_c_cat_T_34 = or(_state_r_c_cat_T_33, _state_r_c_cat_T_31)
node _state_r_c_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_r_c_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_r_c_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_r_c_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_r_c_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_r_c_cat_T_40 = or(_state_r_c_cat_T_35, _state_r_c_cat_T_36)
node _state_r_c_cat_T_41 = or(_state_r_c_cat_T_40, _state_r_c_cat_T_37)
node _state_r_c_cat_T_42 = or(_state_r_c_cat_T_41, _state_r_c_cat_T_38)
node _state_r_c_cat_T_43 = or(_state_r_c_cat_T_42, _state_r_c_cat_T_39)
node _state_r_c_cat_T_44 = or(_state_r_c_cat_T_34, _state_r_c_cat_T_43)
node _state_r_c_cat_T_45 = or(_state_r_c_cat_T_27, _state_r_c_cat_T_44)
node _state_r_c_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _state_r_c_cat_T_47 = or(_state_r_c_cat_T_45, _state_r_c_cat_T_46)
node _state_r_c_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _state_r_c_cat_T_49 = or(_state_r_c_cat_T_47, _state_r_c_cat_T_48)
node state_r_c = cat(_state_r_c_cat_T_22, _state_r_c_cat_T_49)
node _state_r_T = cat(state_r_c, io.req.old_meta.coh.state)
node _state_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_2 = cat(_state_r_T_1, UInt<2>(0h3))
node _state_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_4 = cat(_state_r_T_3, UInt<2>(0h2))
node _state_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_6 = cat(_state_r_T_5, UInt<2>(0h1))
node _state_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_8 = cat(_state_r_T_7, UInt<2>(0h3))
node _state_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_10 = cat(_state_r_T_9, UInt<2>(0h2))
node _state_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_12 = cat(_state_r_T_11, UInt<2>(0h3))
node _state_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_14 = cat(_state_r_T_13, UInt<2>(0h2))
node _state_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_16 = cat(_state_r_T_15, UInt<2>(0h0))
node _state_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_18 = cat(_state_r_T_17, UInt<2>(0h1))
node _state_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_20 = cat(_state_r_T_19, UInt<2>(0h0))
node _state_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_22 = cat(_state_r_T_21, UInt<2>(0h1))
node _state_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_24 = cat(_state_r_T_23, UInt<2>(0h0))
node _state_r_T_25 = eq(_state_r_T_24, _state_r_T)
node _state_r_T_26 = mux(_state_r_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_27 = mux(_state_r_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _state_r_T_28 = eq(_state_r_T_22, _state_r_T)
node _state_r_T_29 = mux(_state_r_T_28, UInt<1>(0h0), _state_r_T_26)
node _state_r_T_30 = mux(_state_r_T_28, UInt<2>(0h2), _state_r_T_27)
node _state_r_T_31 = eq(_state_r_T_20, _state_r_T)
node _state_r_T_32 = mux(_state_r_T_31, UInt<1>(0h0), _state_r_T_29)
node _state_r_T_33 = mux(_state_r_T_31, UInt<2>(0h1), _state_r_T_30)
node _state_r_T_34 = eq(_state_r_T_18, _state_r_T)
node _state_r_T_35 = mux(_state_r_T_34, UInt<1>(0h0), _state_r_T_32)
node _state_r_T_36 = mux(_state_r_T_34, UInt<2>(0h2), _state_r_T_33)
node _state_r_T_37 = eq(_state_r_T_16, _state_r_T)
node _state_r_T_38 = mux(_state_r_T_37, UInt<1>(0h0), _state_r_T_35)
node _state_r_T_39 = mux(_state_r_T_37, UInt<2>(0h0), _state_r_T_36)
node _state_r_T_40 = eq(_state_r_T_14, _state_r_T)
node _state_r_T_41 = mux(_state_r_T_40, UInt<1>(0h1), _state_r_T_38)
node _state_r_T_42 = mux(_state_r_T_40, UInt<2>(0h3), _state_r_T_39)
node _state_r_T_43 = eq(_state_r_T_12, _state_r_T)
node _state_r_T_44 = mux(_state_r_T_43, UInt<1>(0h1), _state_r_T_41)
node _state_r_T_45 = mux(_state_r_T_43, UInt<2>(0h3), _state_r_T_42)
node _state_r_T_46 = eq(_state_r_T_10, _state_r_T)
node _state_r_T_47 = mux(_state_r_T_46, UInt<1>(0h1), _state_r_T_44)
node _state_r_T_48 = mux(_state_r_T_46, UInt<2>(0h2), _state_r_T_45)
node _state_r_T_49 = eq(_state_r_T_8, _state_r_T)
node _state_r_T_50 = mux(_state_r_T_49, UInt<1>(0h1), _state_r_T_47)
node _state_r_T_51 = mux(_state_r_T_49, UInt<2>(0h3), _state_r_T_48)
node _state_r_T_52 = eq(_state_r_T_6, _state_r_T)
node _state_r_T_53 = mux(_state_r_T_52, UInt<1>(0h1), _state_r_T_50)
node _state_r_T_54 = mux(_state_r_T_52, UInt<2>(0h1), _state_r_T_51)
node _state_r_T_55 = eq(_state_r_T_4, _state_r_T)
node _state_r_T_56 = mux(_state_r_T_55, UInt<1>(0h1), _state_r_T_53)
node _state_r_T_57 = mux(_state_r_T_55, UInt<2>(0h2), _state_r_T_54)
node _state_r_T_58 = eq(_state_r_T_2, _state_r_T)
node state_is_hit = mux(_state_r_T_58, UInt<1>(0h1), _state_r_T_56)
node state_r_2 = mux(_state_r_T_58, UInt<2>(0h3), _state_r_T_57)
wire state_coh_on_hit : { state : UInt<2>}
connect state_coh_on_hit.state, state_r_2
when state_is_hit :
node _state_T_3 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_T_4 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_T_5 = or(_state_T_3, _state_T_4)
node _state_T_6 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_T_7 = or(_state_T_5, _state_T_6)
node _state_T_8 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_T_9 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_T_10 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_T_11 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_T_12 = or(_state_T_8, _state_T_9)
node _state_T_13 = or(_state_T_12, _state_T_10)
node _state_T_14 = or(_state_T_13, _state_T_11)
node _state_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_T_17 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_T_18 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_T_19 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_T_20 = or(_state_T_15, _state_T_16)
node _state_T_21 = or(_state_T_20, _state_T_17)
node _state_T_22 = or(_state_T_21, _state_T_18)
node _state_T_23 = or(_state_T_22, _state_T_19)
node _state_T_24 = or(_state_T_14, _state_T_23)
node _state_T_25 = or(_state_T_7, _state_T_24)
node _state_T_26 = asUInt(reset)
node _state_T_27 = eq(_state_T_26, UInt<1>(0h0))
when _state_T_27 :
node _state_T_28 = eq(_state_T_25, UInt<1>(0h0))
when _state_T_28 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:201 assert(isWrite(io.req.uop.mem_cmd))\n") : state_printf_1
assert(clock, _state_T_25, UInt<1>(0h1), "") : state_assert_1
connect new_coh, state_coh_on_hit
connect state_new_state, UInt<5>(0hc)
else :
connect new_coh, io.req.old_meta.coh
connect state_new_state, UInt<5>(0h1)
else :
wire state_new_coh_meta : { state : UInt<2>}
connect state_new_coh_meta.state, UInt<2>(0h0)
connect new_coh, state_new_coh_meta
connect state_new_state, UInt<5>(0h1)
connect state, state_new_state
else :
node _T_13 = eq(state, UInt<5>(0h1))
when _T_13 :
connect io.mem_acquire.valid, UInt<1>(0h1)
node _io_mem_acquire_bits_T = cat(req_tag, req_idx)
node _io_mem_acquire_bits_T_1 = shl(_io_mem_acquire_bits_T, 6)
node _io_mem_acquire_bits_legal_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _io_mem_acquire_bits_legal_T_1 = xor(_io_mem_acquire_bits_T_1, UInt<1>(0h0))
node _io_mem_acquire_bits_legal_T_2 = cvt(_io_mem_acquire_bits_legal_T_1)
node _io_mem_acquire_bits_legal_T_3 = and(_io_mem_acquire_bits_legal_T_2, asSInt(UInt<33>(0h8c000000)))
node _io_mem_acquire_bits_legal_T_4 = asSInt(_io_mem_acquire_bits_legal_T_3)
node _io_mem_acquire_bits_legal_T_5 = eq(_io_mem_acquire_bits_legal_T_4, asSInt(UInt<1>(0h0)))
node _io_mem_acquire_bits_legal_T_6 = xor(_io_mem_acquire_bits_T_1, UInt<17>(0h10000))
node _io_mem_acquire_bits_legal_T_7 = cvt(_io_mem_acquire_bits_legal_T_6)
node _io_mem_acquire_bits_legal_T_8 = and(_io_mem_acquire_bits_legal_T_7, asSInt(UInt<33>(0h8c011000)))
node _io_mem_acquire_bits_legal_T_9 = asSInt(_io_mem_acquire_bits_legal_T_8)
node _io_mem_acquire_bits_legal_T_10 = eq(_io_mem_acquire_bits_legal_T_9, asSInt(UInt<1>(0h0)))
node _io_mem_acquire_bits_legal_T_11 = xor(_io_mem_acquire_bits_T_1, UInt<28>(0hc000000))
node _io_mem_acquire_bits_legal_T_12 = cvt(_io_mem_acquire_bits_legal_T_11)
node _io_mem_acquire_bits_legal_T_13 = and(_io_mem_acquire_bits_legal_T_12, asSInt(UInt<33>(0h8c000000)))
node _io_mem_acquire_bits_legal_T_14 = asSInt(_io_mem_acquire_bits_legal_T_13)
node _io_mem_acquire_bits_legal_T_15 = eq(_io_mem_acquire_bits_legal_T_14, asSInt(UInt<1>(0h0)))
node _io_mem_acquire_bits_legal_T_16 = or(_io_mem_acquire_bits_legal_T_5, _io_mem_acquire_bits_legal_T_10)
node _io_mem_acquire_bits_legal_T_17 = or(_io_mem_acquire_bits_legal_T_16, _io_mem_acquire_bits_legal_T_15)
node _io_mem_acquire_bits_legal_T_18 = and(_io_mem_acquire_bits_legal_T, _io_mem_acquire_bits_legal_T_17)
node _io_mem_acquire_bits_legal_T_19 = eq(UInt<3>(0h6), UInt<3>(0h6))
node _io_mem_acquire_bits_legal_T_20 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_19)
node _io_mem_acquire_bits_legal_T_21 = xor(_io_mem_acquire_bits_T_1, UInt<28>(0h8000000))
node _io_mem_acquire_bits_legal_T_22 = cvt(_io_mem_acquire_bits_legal_T_21)
node _io_mem_acquire_bits_legal_T_23 = and(_io_mem_acquire_bits_legal_T_22, asSInt(UInt<33>(0h8c010000)))
node _io_mem_acquire_bits_legal_T_24 = asSInt(_io_mem_acquire_bits_legal_T_23)
node _io_mem_acquire_bits_legal_T_25 = eq(_io_mem_acquire_bits_legal_T_24, asSInt(UInt<1>(0h0)))
node _io_mem_acquire_bits_legal_T_26 = xor(_io_mem_acquire_bits_T_1, UInt<32>(0h80000000))
node _io_mem_acquire_bits_legal_T_27 = cvt(_io_mem_acquire_bits_legal_T_26)
node _io_mem_acquire_bits_legal_T_28 = and(_io_mem_acquire_bits_legal_T_27, asSInt(UInt<33>(0h80000000)))
node _io_mem_acquire_bits_legal_T_29 = asSInt(_io_mem_acquire_bits_legal_T_28)
node _io_mem_acquire_bits_legal_T_30 = eq(_io_mem_acquire_bits_legal_T_29, asSInt(UInt<1>(0h0)))
node _io_mem_acquire_bits_legal_T_31 = or(_io_mem_acquire_bits_legal_T_25, _io_mem_acquire_bits_legal_T_30)
node _io_mem_acquire_bits_legal_T_32 = and(_io_mem_acquire_bits_legal_T_20, _io_mem_acquire_bits_legal_T_31)
node _io_mem_acquire_bits_legal_T_33 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_18)
node io_mem_acquire_bits_legal = or(_io_mem_acquire_bits_legal_T_33, _io_mem_acquire_bits_legal_T_32)
wire io_mem_acquire_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect io_mem_acquire_bits_a.opcode, UInt<3>(0h6)
connect io_mem_acquire_bits_a.param, grow_param
connect io_mem_acquire_bits_a.size, UInt<3>(0h6)
connect io_mem_acquire_bits_a.source, io.id
connect io_mem_acquire_bits_a.address, _io_mem_acquire_bits_T_1
node _io_mem_acquire_bits_a_mask_sizeOH_T = or(UInt<3>(0h6), UInt<3>(0h0))
node io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = bits(_io_mem_acquire_bits_a_mask_sizeOH_T, 1, 0)
node _io_mem_acquire_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sizeOH_shiftAmount)
node _io_mem_acquire_bits_a_mask_sizeOH_T_2 = bits(_io_mem_acquire_bits_a_mask_sizeOH_T_1, 2, 0)
node io_mem_acquire_bits_a_mask_sizeOH = or(_io_mem_acquire_bits_a_mask_sizeOH_T_2, UInt<1>(0h1))
node io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = geq(UInt<3>(0h6), UInt<2>(0h3))
node io_mem_acquire_bits_a_mask_sub_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 2, 2)
node io_mem_acquire_bits_a_mask_sub_sub_bit = bits(_io_mem_acquire_bits_T_1, 2, 2)
node io_mem_acquire_bits_a_mask_sub_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_sub_bit, UInt<1>(0h0))
node io_mem_acquire_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_nbit)
node _io_mem_acquire_bits_a_mask_sub_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_0_2)
node io_mem_acquire_bits_a_mask_sub_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T)
node io_mem_acquire_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_bit)
node _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_1_2)
node io_mem_acquire_bits_a_mask_sub_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1)
node io_mem_acquire_bits_a_mask_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 1, 1)
node io_mem_acquire_bits_a_mask_sub_bit = bits(_io_mem_acquire_bits_T_1, 1, 1)
node io_mem_acquire_bits_a_mask_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_bit, UInt<1>(0h0))
node io_mem_acquire_bits_a_mask_sub_0_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_nbit)
node _io_mem_acquire_bits_a_mask_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_0_2)
node io_mem_acquire_bits_a_mask_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T)
node io_mem_acquire_bits_a_mask_sub_1_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_bit)
node _io_mem_acquire_bits_a_mask_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_1_2)
node io_mem_acquire_bits_a_mask_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T_1)
node io_mem_acquire_bits_a_mask_sub_2_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_nbit)
node _io_mem_acquire_bits_a_mask_sub_acc_T_2 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_2_2)
node io_mem_acquire_bits_a_mask_sub_2_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_2)
node io_mem_acquire_bits_a_mask_sub_3_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_bit)
node _io_mem_acquire_bits_a_mask_sub_acc_T_3 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_3_2)
node io_mem_acquire_bits_a_mask_sub_3_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_3)
node io_mem_acquire_bits_a_mask_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 0, 0)
node io_mem_acquire_bits_a_mask_bit = bits(_io_mem_acquire_bits_T_1, 0, 0)
node io_mem_acquire_bits_a_mask_nbit = eq(io_mem_acquire_bits_a_mask_bit, UInt<1>(0h0))
node io_mem_acquire_bits_a_mask_eq = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq)
node io_mem_acquire_bits_a_mask_acc = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T)
node io_mem_acquire_bits_a_mask_eq_1 = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_1 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_1)
node io_mem_acquire_bits_a_mask_acc_1 = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T_1)
node io_mem_acquire_bits_a_mask_eq_2 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T_2 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_2)
node io_mem_acquire_bits_a_mask_acc_2 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_2)
node io_mem_acquire_bits_a_mask_eq_3 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_3 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_3)
node io_mem_acquire_bits_a_mask_acc_3 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_3)
node io_mem_acquire_bits_a_mask_eq_4 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T_4 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_4)
node io_mem_acquire_bits_a_mask_acc_4 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_4)
node io_mem_acquire_bits_a_mask_eq_5 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_5 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_5)
node io_mem_acquire_bits_a_mask_acc_5 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_5)
node io_mem_acquire_bits_a_mask_eq_6 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T_6 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_6)
node io_mem_acquire_bits_a_mask_acc_6 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_6)
node io_mem_acquire_bits_a_mask_eq_7 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_7 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_7)
node io_mem_acquire_bits_a_mask_acc_7 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_7)
node io_mem_acquire_bits_a_mask_lo_lo = cat(io_mem_acquire_bits_a_mask_acc_1, io_mem_acquire_bits_a_mask_acc)
node io_mem_acquire_bits_a_mask_lo_hi = cat(io_mem_acquire_bits_a_mask_acc_3, io_mem_acquire_bits_a_mask_acc_2)
node io_mem_acquire_bits_a_mask_lo = cat(io_mem_acquire_bits_a_mask_lo_hi, io_mem_acquire_bits_a_mask_lo_lo)
node io_mem_acquire_bits_a_mask_hi_lo = cat(io_mem_acquire_bits_a_mask_acc_5, io_mem_acquire_bits_a_mask_acc_4)
node io_mem_acquire_bits_a_mask_hi_hi = cat(io_mem_acquire_bits_a_mask_acc_7, io_mem_acquire_bits_a_mask_acc_6)
node io_mem_acquire_bits_a_mask_hi = cat(io_mem_acquire_bits_a_mask_hi_hi, io_mem_acquire_bits_a_mask_hi_lo)
node _io_mem_acquire_bits_a_mask_T = cat(io_mem_acquire_bits_a_mask_hi, io_mem_acquire_bits_a_mask_lo)
connect io_mem_acquire_bits_a.mask, _io_mem_acquire_bits_a_mask_T
invalidate io_mem_acquire_bits_a.data
connect io_mem_acquire_bits_a.corrupt, UInt<1>(0h0)
connect io.mem_acquire.bits, io_mem_acquire_bits_a
node _T_14 = and(io.mem_acquire.ready, io.mem_acquire.valid)
when _T_14 :
connect state, UInt<5>(0h2)
else :
node _T_15 = eq(state, UInt<5>(0h2))
when _T_15 :
node opdata = bits(io.mem_grant.bits.opcode, 0, 0)
when opdata :
connect io.mem_grant.ready, io.lb_write.ready
connect io.lb_write.valid, io.mem_grant.valid
connect io.lb_write.bits.id, io.id
node _io_lb_write_bits_offset_T = shr(refill_address_inc, 3)
connect io.lb_write.bits.offset, _io_lb_write_bits_offset_T
connect io.lb_write.bits.data, io.mem_grant.bits.data
else :
connect io.mem_grant.ready, UInt<1>(0h1)
node _T_16 = and(io.mem_grant.ready, io.mem_grant.valid)
when _T_16 :
node grant_had_data_opdata = bits(io.mem_grant.bits.opcode, 0, 0)
connect grant_had_data, grant_had_data_opdata
when refill_done :
node _grantack_valid_T = bits(io.mem_grant.bits.opcode, 2, 2)
node _grantack_valid_T_1 = bits(io.mem_grant.bits.opcode, 1, 1)
node _grantack_valid_T_2 = eq(_grantack_valid_T_1, UInt<1>(0h0))
node _grantack_valid_T_3 = and(_grantack_valid_T, _grantack_valid_T_2)
connect grantack.valid, _grantack_valid_T_3
wire grantack_bits_e : { sink : UInt<3>}
connect grantack_bits_e.sink, io.mem_grant.bits.sink
connect grantack.bits, grantack_bits_e
node _state_T_29 = mux(grant_had_data, UInt<5>(0h3), UInt<5>(0hc))
connect state, _state_T_29
node _T_17 = eq(grant_had_data, UInt<1>(0h0))
node _T_18 = and(_T_17, req_needs_wb)
node _T_19 = eq(_T_18, UInt<1>(0h0))
node _T_20 = asUInt(reset)
node _T_21 = eq(_T_20, UInt<1>(0h0))
when _T_21 :
node _T_22 = eq(_T_19, UInt<1>(0h0))
when _T_22 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:251 assert(!(!grant_had_data && req_needs_wb))\n") : printf_1
assert(clock, _T_19, UInt<1>(0h1), "") : assert_1
connect commit_line, UInt<1>(0h0)
connect new_coh, coh_on_grant
else :
node _T_23 = eq(state, UInt<5>(0h3))
when _T_23 :
node _drain_load_T = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h0))
node _drain_load_T_1 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h10))
node _drain_load_T_2 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6))
node _drain_load_T_3 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _drain_load_T_4 = or(_drain_load_T, _drain_load_T_1)
node _drain_load_T_5 = or(_drain_load_T_4, _drain_load_T_2)
node _drain_load_T_6 = or(_drain_load_T_5, _drain_load_T_3)
node _drain_load_T_7 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _drain_load_T_8 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _drain_load_T_9 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _drain_load_T_10 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _drain_load_T_11 = or(_drain_load_T_7, _drain_load_T_8)
node _drain_load_T_12 = or(_drain_load_T_11, _drain_load_T_9)
node _drain_load_T_13 = or(_drain_load_T_12, _drain_load_T_10)
node _drain_load_T_14 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _drain_load_T_15 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _drain_load_T_16 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _drain_load_T_17 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _drain_load_T_18 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _drain_load_T_19 = or(_drain_load_T_14, _drain_load_T_15)
node _drain_load_T_20 = or(_drain_load_T_19, _drain_load_T_16)
node _drain_load_T_21 = or(_drain_load_T_20, _drain_load_T_17)
node _drain_load_T_22 = or(_drain_load_T_21, _drain_load_T_18)
node _drain_load_T_23 = or(_drain_load_T_13, _drain_load_T_22)
node _drain_load_T_24 = or(_drain_load_T_6, _drain_load_T_23)
node _drain_load_T_25 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1))
node _drain_load_T_26 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11))
node _drain_load_T_27 = or(_drain_load_T_25, _drain_load_T_26)
node _drain_load_T_28 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _drain_load_T_29 = or(_drain_load_T_27, _drain_load_T_28)
node _drain_load_T_30 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _drain_load_T_31 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _drain_load_T_32 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _drain_load_T_33 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _drain_load_T_34 = or(_drain_load_T_30, _drain_load_T_31)
node _drain_load_T_35 = or(_drain_load_T_34, _drain_load_T_32)
node _drain_load_T_36 = or(_drain_load_T_35, _drain_load_T_33)
node _drain_load_T_37 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _drain_load_T_38 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _drain_load_T_39 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _drain_load_T_40 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _drain_load_T_41 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _drain_load_T_42 = or(_drain_load_T_37, _drain_load_T_38)
node _drain_load_T_43 = or(_drain_load_T_42, _drain_load_T_39)
node _drain_load_T_44 = or(_drain_load_T_43, _drain_load_T_40)
node _drain_load_T_45 = or(_drain_load_T_44, _drain_load_T_41)
node _drain_load_T_46 = or(_drain_load_T_36, _drain_load_T_45)
node _drain_load_T_47 = or(_drain_load_T_29, _drain_load_T_46)
node _drain_load_T_48 = eq(_drain_load_T_47, UInt<1>(0h0))
node _drain_load_T_49 = and(_drain_load_T_24, _drain_load_T_48)
node _drain_load_T_50 = neq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6))
node drain_load = and(_drain_load_T_49, _drain_load_T_50)
node _rp_addr_T = bits(rpq.io.deq.bits.addr, 5, 0)
node rp_addr_hi = cat(req_tag, req_idx)
node rp_addr = cat(rp_addr_hi, _rp_addr_T)
node _data_word_T = cat(UInt<1>(0h0), UInt<6>(0h0))
node data_word = dshr(io.lb_resp, _data_word_T)
node _T_24 = bits(rpq.io.deq.bits.addr, 5, 0)
node hi = cat(req_tag, req_idx)
node _T_25 = cat(hi, _T_24)
wire size : UInt<2>
connect size, rpq.io.deq.bits.uop.mem_size
node _rpq_io_deq_ready_T = and(io.resp.ready, io.lb_read.ready)
node _rpq_io_deq_ready_T_1 = and(_rpq_io_deq_ready_T, drain_load)
connect rpq.io.deq.ready, _rpq_io_deq_ready_T_1
node _io_lb_read_valid_T = and(rpq.io.deq.valid, drain_load)
connect io.lb_read.valid, _io_lb_read_valid_T
connect io.lb_read.bits.id, io.id
node _io_lb_read_bits_offset_T = shr(rpq.io.deq.bits.addr, 3)
connect io.lb_read.bits.offset, _io_lb_read_bits_offset_T
node _io_resp_valid_T = and(io.lb_read.ready, io.lb_read.valid)
node _io_resp_valid_T_1 = and(rpq.io.deq.valid, _io_resp_valid_T)
node _io_resp_valid_T_2 = and(_io_resp_valid_T_1, drain_load)
connect io.resp.valid, _io_resp_valid_T_2
connect io.resp.bits.uop, rpq.io.deq.bits.uop
node _io_resp_bits_data_shifted_T = bits(_T_25, 2, 2)
node _io_resp_bits_data_shifted_T_1 = bits(data_word, 63, 32)
node _io_resp_bits_data_shifted_T_2 = bits(data_word, 31, 0)
node io_resp_bits_data_shifted = mux(_io_resp_bits_data_shifted_T, _io_resp_bits_data_shifted_T_1, _io_resp_bits_data_shifted_T_2)
node io_resp_bits_data_doZero = and(UInt<1>(0h0), UInt<1>(0h0))
node io_resp_bits_data_zeroed = mux(io_resp_bits_data_doZero, UInt<1>(0h0), io_resp_bits_data_shifted)
node _io_resp_bits_data_T = eq(size, UInt<2>(0h2))
node _io_resp_bits_data_T_1 = or(_io_resp_bits_data_T, io_resp_bits_data_doZero)
node _io_resp_bits_data_T_2 = bits(io_resp_bits_data_zeroed, 31, 31)
node _io_resp_bits_data_T_3 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_2)
node _io_resp_bits_data_T_4 = mux(_io_resp_bits_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0))
node _io_resp_bits_data_T_5 = bits(data_word, 63, 32)
node _io_resp_bits_data_T_6 = mux(_io_resp_bits_data_T_1, _io_resp_bits_data_T_4, _io_resp_bits_data_T_5)
node _io_resp_bits_data_T_7 = cat(_io_resp_bits_data_T_6, io_resp_bits_data_zeroed)
node _io_resp_bits_data_shifted_T_3 = bits(_T_25, 1, 1)
node _io_resp_bits_data_shifted_T_4 = bits(_io_resp_bits_data_T_7, 31, 16)
node _io_resp_bits_data_shifted_T_5 = bits(_io_resp_bits_data_T_7, 15, 0)
node io_resp_bits_data_shifted_1 = mux(_io_resp_bits_data_shifted_T_3, _io_resp_bits_data_shifted_T_4, _io_resp_bits_data_shifted_T_5)
node io_resp_bits_data_doZero_1 = and(UInt<1>(0h0), UInt<1>(0h0))
node io_resp_bits_data_zeroed_1 = mux(io_resp_bits_data_doZero_1, UInt<1>(0h0), io_resp_bits_data_shifted_1)
node _io_resp_bits_data_T_8 = eq(size, UInt<1>(0h1))
node _io_resp_bits_data_T_9 = or(_io_resp_bits_data_T_8, io_resp_bits_data_doZero_1)
node _io_resp_bits_data_T_10 = bits(io_resp_bits_data_zeroed_1, 15, 15)
node _io_resp_bits_data_T_11 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_10)
node _io_resp_bits_data_T_12 = mux(_io_resp_bits_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0))
node _io_resp_bits_data_T_13 = bits(_io_resp_bits_data_T_7, 63, 16)
node _io_resp_bits_data_T_14 = mux(_io_resp_bits_data_T_9, _io_resp_bits_data_T_12, _io_resp_bits_data_T_13)
node _io_resp_bits_data_T_15 = cat(_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1)
node _io_resp_bits_data_shifted_T_6 = bits(_T_25, 0, 0)
node _io_resp_bits_data_shifted_T_7 = bits(_io_resp_bits_data_T_15, 15, 8)
node _io_resp_bits_data_shifted_T_8 = bits(_io_resp_bits_data_T_15, 7, 0)
node io_resp_bits_data_shifted_2 = mux(_io_resp_bits_data_shifted_T_6, _io_resp_bits_data_shifted_T_7, _io_resp_bits_data_shifted_T_8)
node io_resp_bits_data_doZero_2 = and(UInt<1>(0h1), UInt<1>(0h0))
node io_resp_bits_data_zeroed_2 = mux(io_resp_bits_data_doZero_2, UInt<1>(0h0), io_resp_bits_data_shifted_2)
node _io_resp_bits_data_T_16 = eq(size, UInt<1>(0h0))
node _io_resp_bits_data_T_17 = or(_io_resp_bits_data_T_16, io_resp_bits_data_doZero_2)
node _io_resp_bits_data_T_18 = bits(io_resp_bits_data_zeroed_2, 7, 7)
node _io_resp_bits_data_T_19 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_18)
node _io_resp_bits_data_T_20 = mux(_io_resp_bits_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0))
node _io_resp_bits_data_T_21 = bits(_io_resp_bits_data_T_15, 63, 8)
node _io_resp_bits_data_T_22 = mux(_io_resp_bits_data_T_17, _io_resp_bits_data_T_20, _io_resp_bits_data_T_21)
node _io_resp_bits_data_T_23 = cat(_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2)
connect io.resp.bits.data, _io_resp_bits_data_T_23
connect io.resp.bits.is_hella, rpq.io.deq.bits.is_hella
node _T_26 = and(rpq.io.deq.ready, rpq.io.deq.valid)
when _T_26 :
connect commit_line, UInt<1>(0h1)
else :
node _T_27 = eq(commit_line, UInt<1>(0h0))
node _T_28 = and(rpq.io.empty, _T_27)
when _T_28 :
node _T_29 = and(rpq.io.enq.ready, rpq.io.enq.valid)
node _T_30 = eq(_T_29, UInt<1>(0h0))
when _T_30 :
connect state, UInt<5>(0he)
connect finish_to_prefetch, UInt<1>(0h0)
else :
node _T_31 = eq(drain_load, UInt<1>(0h0))
node _T_32 = and(rpq.io.deq.valid, _T_31)
node _T_33 = or(rpq.io.empty, _T_32)
when _T_33 :
connect io.commit_val, UInt<1>(0h1)
connect state, UInt<5>(0h4)
else :
node _T_34 = eq(state, UInt<5>(0h4))
when _T_34 :
node _io_meta_read_valid_T = eq(io.prober_state.valid, UInt<1>(0h0))
node _io_meta_read_valid_T_1 = eq(grantack.valid, UInt<1>(0h0))
node _io_meta_read_valid_T_2 = or(_io_meta_read_valid_T, _io_meta_read_valid_T_1)
node _io_meta_read_valid_T_3 = bits(io.prober_state.bits, 11, 6)
node _io_meta_read_valid_T_4 = neq(_io_meta_read_valid_T_3, req_idx)
node _io_meta_read_valid_T_5 = or(_io_meta_read_valid_T_2, _io_meta_read_valid_T_4)
connect io.meta_read.valid, _io_meta_read_valid_T_5
connect io.meta_read.bits.idx, req_idx
connect io.meta_read.bits.tag, req_tag
connect io.meta_read.bits.way_en, req.way_en
node _T_35 = and(io.meta_read.ready, io.meta_read.valid)
when _T_35 :
connect state, UInt<5>(0h5)
else :
node _T_36 = eq(state, UInt<5>(0h5))
when _T_36 :
connect state, UInt<5>(0h6)
else :
node _T_37 = eq(state, UInt<5>(0h6))
when _T_37 :
node _needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10))
node _needs_wb_r_T_1 = mux(_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2))
node _needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _needs_wb_r_T_3 = mux(_needs_wb_r_T_2, UInt<2>(0h1), _needs_wb_r_T_1)
node _needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _needs_wb_r_T_5 = mux(_needs_wb_r_T_4, UInt<2>(0h0), _needs_wb_r_T_3)
node _needs_wb_r_T_6 = cat(_needs_wb_r_T_5, io.meta_resp.bits.coh.state)
node _needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _needs_wb_r_T_19 = eq(_needs_wb_r_T_18, _needs_wb_r_T_6)
node _needs_wb_r_T_20 = mux(_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0))
node _needs_wb_r_T_21 = mux(_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0))
node _needs_wb_r_T_22 = mux(_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0))
node _needs_wb_r_T_23 = eq(_needs_wb_r_T_17, _needs_wb_r_T_6)
node _needs_wb_r_T_24 = mux(_needs_wb_r_T_23, UInt<1>(0h0), _needs_wb_r_T_20)
node _needs_wb_r_T_25 = mux(_needs_wb_r_T_23, UInt<3>(0h2), _needs_wb_r_T_21)
node _needs_wb_r_T_26 = mux(_needs_wb_r_T_23, UInt<2>(0h0), _needs_wb_r_T_22)
node _needs_wb_r_T_27 = eq(_needs_wb_r_T_16, _needs_wb_r_T_6)
node _needs_wb_r_T_28 = mux(_needs_wb_r_T_27, UInt<1>(0h0), _needs_wb_r_T_24)
node _needs_wb_r_T_29 = mux(_needs_wb_r_T_27, UInt<3>(0h1), _needs_wb_r_T_25)
node _needs_wb_r_T_30 = mux(_needs_wb_r_T_27, UInt<2>(0h0), _needs_wb_r_T_26)
node _needs_wb_r_T_31 = eq(_needs_wb_r_T_15, _needs_wb_r_T_6)
node _needs_wb_r_T_32 = mux(_needs_wb_r_T_31, UInt<1>(0h1), _needs_wb_r_T_28)
node _needs_wb_r_T_33 = mux(_needs_wb_r_T_31, UInt<3>(0h1), _needs_wb_r_T_29)
node _needs_wb_r_T_34 = mux(_needs_wb_r_T_31, UInt<2>(0h0), _needs_wb_r_T_30)
node _needs_wb_r_T_35 = eq(_needs_wb_r_T_14, _needs_wb_r_T_6)
node _needs_wb_r_T_36 = mux(_needs_wb_r_T_35, UInt<1>(0h0), _needs_wb_r_T_32)
node _needs_wb_r_T_37 = mux(_needs_wb_r_T_35, UInt<3>(0h5), _needs_wb_r_T_33)
node _needs_wb_r_T_38 = mux(_needs_wb_r_T_35, UInt<2>(0h0), _needs_wb_r_T_34)
node _needs_wb_r_T_39 = eq(_needs_wb_r_T_13, _needs_wb_r_T_6)
node _needs_wb_r_T_40 = mux(_needs_wb_r_T_39, UInt<1>(0h0), _needs_wb_r_T_36)
node _needs_wb_r_T_41 = mux(_needs_wb_r_T_39, UInt<3>(0h4), _needs_wb_r_T_37)
node _needs_wb_r_T_42 = mux(_needs_wb_r_T_39, UInt<2>(0h1), _needs_wb_r_T_38)
node _needs_wb_r_T_43 = eq(_needs_wb_r_T_12, _needs_wb_r_T_6)
node _needs_wb_r_T_44 = mux(_needs_wb_r_T_43, UInt<1>(0h0), _needs_wb_r_T_40)
node _needs_wb_r_T_45 = mux(_needs_wb_r_T_43, UInt<3>(0h0), _needs_wb_r_T_41)
node _needs_wb_r_T_46 = mux(_needs_wb_r_T_43, UInt<2>(0h1), _needs_wb_r_T_42)
node _needs_wb_r_T_47 = eq(_needs_wb_r_T_11, _needs_wb_r_T_6)
node _needs_wb_r_T_48 = mux(_needs_wb_r_T_47, UInt<1>(0h1), _needs_wb_r_T_44)
node _needs_wb_r_T_49 = mux(_needs_wb_r_T_47, UInt<3>(0h0), _needs_wb_r_T_45)
node _needs_wb_r_T_50 = mux(_needs_wb_r_T_47, UInt<2>(0h1), _needs_wb_r_T_46)
node _needs_wb_r_T_51 = eq(_needs_wb_r_T_10, _needs_wb_r_T_6)
node _needs_wb_r_T_52 = mux(_needs_wb_r_T_51, UInt<1>(0h0), _needs_wb_r_T_48)
node _needs_wb_r_T_53 = mux(_needs_wb_r_T_51, UInt<3>(0h5), _needs_wb_r_T_49)
node _needs_wb_r_T_54 = mux(_needs_wb_r_T_51, UInt<2>(0h0), _needs_wb_r_T_50)
node _needs_wb_r_T_55 = eq(_needs_wb_r_T_9, _needs_wb_r_T_6)
node _needs_wb_r_T_56 = mux(_needs_wb_r_T_55, UInt<1>(0h0), _needs_wb_r_T_52)
node _needs_wb_r_T_57 = mux(_needs_wb_r_T_55, UInt<3>(0h4), _needs_wb_r_T_53)
node _needs_wb_r_T_58 = mux(_needs_wb_r_T_55, UInt<2>(0h1), _needs_wb_r_T_54)
node _needs_wb_r_T_59 = eq(_needs_wb_r_T_8, _needs_wb_r_T_6)
node _needs_wb_r_T_60 = mux(_needs_wb_r_T_59, UInt<1>(0h0), _needs_wb_r_T_56)
node _needs_wb_r_T_61 = mux(_needs_wb_r_T_59, UInt<3>(0h3), _needs_wb_r_T_57)
node _needs_wb_r_T_62 = mux(_needs_wb_r_T_59, UInt<2>(0h2), _needs_wb_r_T_58)
node _needs_wb_r_T_63 = eq(_needs_wb_r_T_7, _needs_wb_r_T_6)
node needs_wb = mux(_needs_wb_r_T_63, UInt<1>(0h1), _needs_wb_r_T_60)
node needs_wb_r_2 = mux(_needs_wb_r_T_63, UInt<3>(0h3), _needs_wb_r_T_61)
node needs_wb_r_3 = mux(_needs_wb_r_T_63, UInt<2>(0h2), _needs_wb_r_T_62)
wire needs_wb_meta : { state : UInt<2>}
connect needs_wb_meta.state, needs_wb_r_3
node _state_T_30 = eq(io.meta_resp.valid, UInt<1>(0h0))
node _state_T_31 = mux(needs_wb, UInt<5>(0h7), UInt<5>(0hb))
node _state_T_32 = mux(_state_T_30, UInt<5>(0h4), _state_T_31)
connect state, _state_T_32
else :
node _T_38 = eq(state, UInt<5>(0h7))
when _T_38 :
connect io.meta_write.valid, UInt<1>(0h1)
connect io.meta_write.bits.idx, req_idx
connect io.meta_write.bits.data.coh, coh_on_clear
connect io.meta_write.bits.data.tag, req_tag
connect io.meta_write.bits.way_en, req.way_en
node _T_39 = and(io.meta_write.ready, io.meta_write.valid)
when _T_39 :
connect state, UInt<5>(0h9)
else :
node _T_40 = eq(state, UInt<5>(0h9))
when _T_40 :
connect io.wb_req.valid, UInt<1>(0h1)
connect io.wb_req.bits.tag, req.old_meta.tag
connect io.wb_req.bits.idx, req_idx
connect io.wb_req.bits.param, shrink_param
connect io.wb_req.bits.way_en, req.way_en
connect io.wb_req.bits.source, io.id
connect io.wb_req.bits.voluntary, UInt<1>(0h1)
node _T_41 = and(io.wb_req.ready, io.wb_req.valid)
when _T_41 :
connect state, UInt<5>(0ha)
else :
node _T_42 = eq(state, UInt<5>(0ha))
when _T_42 :
when io.wb_resp :
connect state, UInt<5>(0hb)
else :
node _T_43 = eq(state, UInt<5>(0hb))
when _T_43 :
connect io.lb_read.valid, UInt<1>(0h1)
connect io.lb_read.bits.id, io.id
connect io.lb_read.bits.offset, refill_ctr
node _io_refill_valid_T = and(io.lb_read.ready, io.lb_read.valid)
connect io.refill.valid, _io_refill_valid_T
node _io_refill_bits_addr_T = shl(refill_ctr, 3)
node _io_refill_bits_addr_T_1 = or(req_block_addr, _io_refill_bits_addr_T)
connect io.refill.bits.addr, _io_refill_bits_addr_T_1
connect io.refill.bits.way_en, req.way_en
node _io_refill_bits_wmask_T = not(UInt<1>(0h0))
connect io.refill.bits.wmask, _io_refill_bits_wmask_T
connect io.refill.bits.data, io.lb_resp
node _T_44 = and(io.refill.ready, io.refill.valid)
when _T_44 :
node _refill_ctr_T = add(refill_ctr, UInt<1>(0h1))
node _refill_ctr_T_1 = tail(_refill_ctr_T, 1)
connect refill_ctr, _refill_ctr_T_1
node _T_45 = eq(refill_ctr, UInt<3>(0h7))
when _T_45 :
connect state, UInt<5>(0hc)
else :
node _T_46 = eq(state, UInt<5>(0hc))
when _T_46 :
connect io.replay.bits, rpq.io.deq.bits
connect io.replay.valid, rpq.io.deq.valid
connect rpq.io.deq.ready, io.replay.ready
connect io.replay.bits.way_en, req.way_en
node _io_replay_bits_addr_T = bits(rpq.io.deq.bits.addr, 5, 0)
node io_replay_bits_addr_hi = cat(req_tag, req_idx)
node _io_replay_bits_addr_T_1 = cat(io_replay_bits_addr_hi, _io_replay_bits_addr_T)
connect io.replay.bits.addr, _io_replay_bits_addr_T_1
node _T_47 = and(io.replay.ready, io.replay.valid)
node _T_48 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1))
node _T_49 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11))
node _T_50 = or(_T_48, _T_49)
node _T_51 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _T_52 = or(_T_50, _T_51)
node _T_53 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _T_54 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _T_55 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _T_56 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _T_57 = or(_T_53, _T_54)
node _T_58 = or(_T_57, _T_55)
node _T_59 = or(_T_58, _T_56)
node _T_60 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _T_61 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _T_62 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _T_63 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _T_64 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _T_65 = or(_T_60, _T_61)
node _T_66 = or(_T_65, _T_62)
node _T_67 = or(_T_66, _T_63)
node _T_68 = or(_T_67, _T_64)
node _T_69 = or(_T_59, _T_68)
node _T_70 = or(_T_52, _T_69)
node _T_71 = and(_T_47, _T_70)
when _T_71 :
node _r_c_cat_T = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1))
node _r_c_cat_T_1 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11))
node _r_c_cat_T_2 = or(_r_c_cat_T, _r_c_cat_T_1)
node _r_c_cat_T_3 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _r_c_cat_T_4 = or(_r_c_cat_T_2, _r_c_cat_T_3)
node _r_c_cat_T_5 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _r_c_cat_T_6 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _r_c_cat_T_7 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _r_c_cat_T_8 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _r_c_cat_T_9 = or(_r_c_cat_T_5, _r_c_cat_T_6)
node _r_c_cat_T_10 = or(_r_c_cat_T_9, _r_c_cat_T_7)
node _r_c_cat_T_11 = or(_r_c_cat_T_10, _r_c_cat_T_8)
node _r_c_cat_T_12 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _r_c_cat_T_13 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _r_c_cat_T_14 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _r_c_cat_T_15 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _r_c_cat_T_16 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _r_c_cat_T_17 = or(_r_c_cat_T_12, _r_c_cat_T_13)
node _r_c_cat_T_18 = or(_r_c_cat_T_17, _r_c_cat_T_14)
node _r_c_cat_T_19 = or(_r_c_cat_T_18, _r_c_cat_T_15)
node _r_c_cat_T_20 = or(_r_c_cat_T_19, _r_c_cat_T_16)
node _r_c_cat_T_21 = or(_r_c_cat_T_11, _r_c_cat_T_20)
node _r_c_cat_T_22 = or(_r_c_cat_T_4, _r_c_cat_T_21)
node _r_c_cat_T_23 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1))
node _r_c_cat_T_24 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11))
node _r_c_cat_T_25 = or(_r_c_cat_T_23, _r_c_cat_T_24)
node _r_c_cat_T_26 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _r_c_cat_T_27 = or(_r_c_cat_T_25, _r_c_cat_T_26)
node _r_c_cat_T_28 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _r_c_cat_T_29 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _r_c_cat_T_30 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _r_c_cat_T_31 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _r_c_cat_T_32 = or(_r_c_cat_T_28, _r_c_cat_T_29)
node _r_c_cat_T_33 = or(_r_c_cat_T_32, _r_c_cat_T_30)
node _r_c_cat_T_34 = or(_r_c_cat_T_33, _r_c_cat_T_31)
node _r_c_cat_T_35 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _r_c_cat_T_36 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _r_c_cat_T_37 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _r_c_cat_T_38 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _r_c_cat_T_39 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _r_c_cat_T_40 = or(_r_c_cat_T_35, _r_c_cat_T_36)
node _r_c_cat_T_41 = or(_r_c_cat_T_40, _r_c_cat_T_37)
node _r_c_cat_T_42 = or(_r_c_cat_T_41, _r_c_cat_T_38)
node _r_c_cat_T_43 = or(_r_c_cat_T_42, _r_c_cat_T_39)
node _r_c_cat_T_44 = or(_r_c_cat_T_34, _r_c_cat_T_43)
node _r_c_cat_T_45 = or(_r_c_cat_T_27, _r_c_cat_T_44)
node _r_c_cat_T_46 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<2>(0h3))
node _r_c_cat_T_47 = or(_r_c_cat_T_45, _r_c_cat_T_46)
node _r_c_cat_T_48 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6))
node _r_c_cat_T_49 = or(_r_c_cat_T_47, _r_c_cat_T_48)
node r_c = cat(_r_c_cat_T_22, _r_c_cat_T_49)
node _r_T_64 = cat(r_c, new_coh.state)
node _r_T_65 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_66 = cat(_r_T_65, UInt<2>(0h3))
node _r_T_67 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_68 = cat(_r_T_67, UInt<2>(0h2))
node _r_T_69 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_70 = cat(_r_T_69, UInt<2>(0h1))
node _r_T_71 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_72 = cat(_r_T_71, UInt<2>(0h3))
node _r_T_73 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_74 = cat(_r_T_73, UInt<2>(0h2))
node _r_T_75 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_76 = cat(_r_T_75, UInt<2>(0h3))
node _r_T_77 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_78 = cat(_r_T_77, UInt<2>(0h2))
node _r_T_79 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_80 = cat(_r_T_79, UInt<2>(0h0))
node _r_T_81 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_82 = cat(_r_T_81, UInt<2>(0h1))
node _r_T_83 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_84 = cat(_r_T_83, UInt<2>(0h0))
node _r_T_85 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_86 = cat(_r_T_85, UInt<2>(0h1))
node _r_T_87 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_88 = cat(_r_T_87, UInt<2>(0h0))
node _r_T_89 = eq(_r_T_88, _r_T_64)
node _r_T_90 = mux(_r_T_89, UInt<1>(0h0), UInt<1>(0h0))
node _r_T_91 = mux(_r_T_89, UInt<2>(0h1), UInt<1>(0h0))
node _r_T_92 = eq(_r_T_86, _r_T_64)
node _r_T_93 = mux(_r_T_92, UInt<1>(0h0), _r_T_90)
node _r_T_94 = mux(_r_T_92, UInt<2>(0h2), _r_T_91)
node _r_T_95 = eq(_r_T_84, _r_T_64)
node _r_T_96 = mux(_r_T_95, UInt<1>(0h0), _r_T_93)
node _r_T_97 = mux(_r_T_95, UInt<2>(0h1), _r_T_94)
node _r_T_98 = eq(_r_T_82, _r_T_64)
node _r_T_99 = mux(_r_T_98, UInt<1>(0h0), _r_T_96)
node _r_T_100 = mux(_r_T_98, UInt<2>(0h2), _r_T_97)
node _r_T_101 = eq(_r_T_80, _r_T_64)
node _r_T_102 = mux(_r_T_101, UInt<1>(0h0), _r_T_99)
node _r_T_103 = mux(_r_T_101, UInt<2>(0h0), _r_T_100)
node _r_T_104 = eq(_r_T_78, _r_T_64)
node _r_T_105 = mux(_r_T_104, UInt<1>(0h1), _r_T_102)
node _r_T_106 = mux(_r_T_104, UInt<2>(0h3), _r_T_103)
node _r_T_107 = eq(_r_T_76, _r_T_64)
node _r_T_108 = mux(_r_T_107, UInt<1>(0h1), _r_T_105)
node _r_T_109 = mux(_r_T_107, UInt<2>(0h3), _r_T_106)
node _r_T_110 = eq(_r_T_74, _r_T_64)
node _r_T_111 = mux(_r_T_110, UInt<1>(0h1), _r_T_108)
node _r_T_112 = mux(_r_T_110, UInt<2>(0h2), _r_T_109)
node _r_T_113 = eq(_r_T_72, _r_T_64)
node _r_T_114 = mux(_r_T_113, UInt<1>(0h1), _r_T_111)
node _r_T_115 = mux(_r_T_113, UInt<2>(0h3), _r_T_112)
node _r_T_116 = eq(_r_T_70, _r_T_64)
node _r_T_117 = mux(_r_T_116, UInt<1>(0h1), _r_T_114)
node _r_T_118 = mux(_r_T_116, UInt<2>(0h1), _r_T_115)
node _r_T_119 = eq(_r_T_68, _r_T_64)
node _r_T_120 = mux(_r_T_119, UInt<1>(0h1), _r_T_117)
node _r_T_121 = mux(_r_T_119, UInt<2>(0h2), _r_T_118)
node _r_T_122 = eq(_r_T_66, _r_T_64)
node is_hit = mux(_r_T_122, UInt<1>(0h1), _r_T_120)
node r_2_1 = mux(_r_T_122, UInt<2>(0h3), _r_T_121)
wire coh_on_hit : { state : UInt<2>}
connect coh_on_hit.state, r_2_1
node _T_72 = asUInt(reset)
node _T_73 = eq(_T_72, UInt<1>(0h0))
when _T_73 :
node _T_74 = eq(is_hit, UInt<1>(0h0))
when _T_74 :
printf(clock, UInt<1>(0h1), "Assertion failed: We still don't have permissions for this store\n at mshrs.scala:357 assert(is_hit, \"We still don't have permissions for this store\")\n") : printf_2
assert(clock, is_hit, UInt<1>(0h1), "") : assert_2
connect new_coh, coh_on_hit
node _T_75 = eq(rpq.io.enq.valid, UInt<1>(0h0))
node _T_76 = and(rpq.io.empty, _T_75)
when _T_76 :
connect state, UInt<5>(0hd)
else :
node _T_77 = eq(state, UInt<5>(0hd))
when _T_77 :
connect io.meta_write.valid, UInt<1>(0h1)
connect io.meta_write.bits.idx, req_idx
connect io.meta_write.bits.data.coh, new_coh
connect io.meta_write.bits.data.tag, req_tag
connect io.meta_write.bits.way_en, req.way_en
node _T_78 = and(io.meta_write.ready, io.meta_write.valid)
when _T_78 :
connect state, UInt<5>(0he)
connect finish_to_prefetch, UInt<1>(0h0)
else :
node _T_79 = eq(state, UInt<5>(0he))
when _T_79 :
connect io.mem_finish.valid, grantack.valid
connect io.mem_finish.bits, grantack.bits
node _T_80 = and(io.mem_finish.ready, io.mem_finish.valid)
node _T_81 = eq(grantack.valid, UInt<1>(0h0))
node _T_82 = or(_T_80, _T_81)
when _T_82 :
connect grantack.valid, UInt<1>(0h0)
connect state, UInt<5>(0hf)
else :
node _T_83 = eq(state, UInt<5>(0hf))
when _T_83 :
node _state_T_33 = mux(finish_to_prefetch, UInt<5>(0h11), UInt<5>(0h0))
connect state, _state_T_33
else :
node _T_84 = eq(state, UInt<5>(0h11))
when _T_84 :
connect io.req_pri_rdy, UInt<1>(0h1)
node _T_85 = eq(io.req_sec_rdy, UInt<1>(0h0))
node _T_86 = and(io.req_sec_val, _T_85)
node _T_87 = or(_T_86, io.clear_prefetch)
when _T_87 :
connect state, UInt<5>(0h0)
else :
node _T_88 = and(io.req_sec_val, io.req_sec_rdy)
when _T_88 :
node _r_c_cat_T_50 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _r_c_cat_T_51 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _r_c_cat_T_52 = or(_r_c_cat_T_50, _r_c_cat_T_51)
node _r_c_cat_T_53 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _r_c_cat_T_54 = or(_r_c_cat_T_52, _r_c_cat_T_53)
node _r_c_cat_T_55 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _r_c_cat_T_56 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _r_c_cat_T_57 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _r_c_cat_T_58 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _r_c_cat_T_59 = or(_r_c_cat_T_55, _r_c_cat_T_56)
node _r_c_cat_T_60 = or(_r_c_cat_T_59, _r_c_cat_T_57)
node _r_c_cat_T_61 = or(_r_c_cat_T_60, _r_c_cat_T_58)
node _r_c_cat_T_62 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _r_c_cat_T_63 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _r_c_cat_T_64 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _r_c_cat_T_65 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _r_c_cat_T_66 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _r_c_cat_T_67 = or(_r_c_cat_T_62, _r_c_cat_T_63)
node _r_c_cat_T_68 = or(_r_c_cat_T_67, _r_c_cat_T_64)
node _r_c_cat_T_69 = or(_r_c_cat_T_68, _r_c_cat_T_65)
node _r_c_cat_T_70 = or(_r_c_cat_T_69, _r_c_cat_T_66)
node _r_c_cat_T_71 = or(_r_c_cat_T_61, _r_c_cat_T_70)
node _r_c_cat_T_72 = or(_r_c_cat_T_54, _r_c_cat_T_71)
node _r_c_cat_T_73 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _r_c_cat_T_74 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _r_c_cat_T_75 = or(_r_c_cat_T_73, _r_c_cat_T_74)
node _r_c_cat_T_76 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _r_c_cat_T_77 = or(_r_c_cat_T_75, _r_c_cat_T_76)
node _r_c_cat_T_78 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _r_c_cat_T_79 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _r_c_cat_T_80 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _r_c_cat_T_81 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _r_c_cat_T_82 = or(_r_c_cat_T_78, _r_c_cat_T_79)
node _r_c_cat_T_83 = or(_r_c_cat_T_82, _r_c_cat_T_80)
node _r_c_cat_T_84 = or(_r_c_cat_T_83, _r_c_cat_T_81)
node _r_c_cat_T_85 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _r_c_cat_T_86 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _r_c_cat_T_87 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _r_c_cat_T_88 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _r_c_cat_T_89 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _r_c_cat_T_90 = or(_r_c_cat_T_85, _r_c_cat_T_86)
node _r_c_cat_T_91 = or(_r_c_cat_T_90, _r_c_cat_T_87)
node _r_c_cat_T_92 = or(_r_c_cat_T_91, _r_c_cat_T_88)
node _r_c_cat_T_93 = or(_r_c_cat_T_92, _r_c_cat_T_89)
node _r_c_cat_T_94 = or(_r_c_cat_T_84, _r_c_cat_T_93)
node _r_c_cat_T_95 = or(_r_c_cat_T_77, _r_c_cat_T_94)
node _r_c_cat_T_96 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _r_c_cat_T_97 = or(_r_c_cat_T_95, _r_c_cat_T_96)
node _r_c_cat_T_98 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _r_c_cat_T_99 = or(_r_c_cat_T_97, _r_c_cat_T_98)
node r_c_1 = cat(_r_c_cat_T_72, _r_c_cat_T_99)
node _r_T_123 = cat(r_c_1, new_coh.state)
node _r_T_124 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_125 = cat(_r_T_124, UInt<2>(0h3))
node _r_T_126 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_127 = cat(_r_T_126, UInt<2>(0h2))
node _r_T_128 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_129 = cat(_r_T_128, UInt<2>(0h1))
node _r_T_130 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_131 = cat(_r_T_130, UInt<2>(0h3))
node _r_T_132 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_133 = cat(_r_T_132, UInt<2>(0h2))
node _r_T_134 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_135 = cat(_r_T_134, UInt<2>(0h3))
node _r_T_136 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_137 = cat(_r_T_136, UInt<2>(0h2))
node _r_T_138 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_139 = cat(_r_T_138, UInt<2>(0h0))
node _r_T_140 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_141 = cat(_r_T_140, UInt<2>(0h1))
node _r_T_142 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_143 = cat(_r_T_142, UInt<2>(0h0))
node _r_T_144 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_145 = cat(_r_T_144, UInt<2>(0h1))
node _r_T_146 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_147 = cat(_r_T_146, UInt<2>(0h0))
node _r_T_148 = eq(_r_T_147, _r_T_123)
node _r_T_149 = mux(_r_T_148, UInt<1>(0h0), UInt<1>(0h0))
node _r_T_150 = mux(_r_T_148, UInt<2>(0h1), UInt<1>(0h0))
node _r_T_151 = eq(_r_T_145, _r_T_123)
node _r_T_152 = mux(_r_T_151, UInt<1>(0h0), _r_T_149)
node _r_T_153 = mux(_r_T_151, UInt<2>(0h2), _r_T_150)
node _r_T_154 = eq(_r_T_143, _r_T_123)
node _r_T_155 = mux(_r_T_154, UInt<1>(0h0), _r_T_152)
node _r_T_156 = mux(_r_T_154, UInt<2>(0h1), _r_T_153)
node _r_T_157 = eq(_r_T_141, _r_T_123)
node _r_T_158 = mux(_r_T_157, UInt<1>(0h0), _r_T_155)
node _r_T_159 = mux(_r_T_157, UInt<2>(0h2), _r_T_156)
node _r_T_160 = eq(_r_T_139, _r_T_123)
node _r_T_161 = mux(_r_T_160, UInt<1>(0h0), _r_T_158)
node _r_T_162 = mux(_r_T_160, UInt<2>(0h0), _r_T_159)
node _r_T_163 = eq(_r_T_137, _r_T_123)
node _r_T_164 = mux(_r_T_163, UInt<1>(0h1), _r_T_161)
node _r_T_165 = mux(_r_T_163, UInt<2>(0h3), _r_T_162)
node _r_T_166 = eq(_r_T_135, _r_T_123)
node _r_T_167 = mux(_r_T_166, UInt<1>(0h1), _r_T_164)
node _r_T_168 = mux(_r_T_166, UInt<2>(0h3), _r_T_165)
node _r_T_169 = eq(_r_T_133, _r_T_123)
node _r_T_170 = mux(_r_T_169, UInt<1>(0h1), _r_T_167)
node _r_T_171 = mux(_r_T_169, UInt<2>(0h2), _r_T_168)
node _r_T_172 = eq(_r_T_131, _r_T_123)
node _r_T_173 = mux(_r_T_172, UInt<1>(0h1), _r_T_170)
node _r_T_174 = mux(_r_T_172, UInt<2>(0h3), _r_T_171)
node _r_T_175 = eq(_r_T_129, _r_T_123)
node _r_T_176 = mux(_r_T_175, UInt<1>(0h1), _r_T_173)
node _r_T_177 = mux(_r_T_175, UInt<2>(0h1), _r_T_174)
node _r_T_178 = eq(_r_T_127, _r_T_123)
node _r_T_179 = mux(_r_T_178, UInt<1>(0h1), _r_T_176)
node _r_T_180 = mux(_r_T_178, UInt<2>(0h2), _r_T_177)
node _r_T_181 = eq(_r_T_125, _r_T_123)
node is_hit_1 = mux(_r_T_181, UInt<1>(0h1), _r_T_179)
node r_2_2 = mux(_r_T_181, UInt<2>(0h3), _r_T_180)
wire coh_on_hit_1 : { state : UInt<2>}
connect coh_on_hit_1.state, r_2_2
when is_hit_1 :
connect new_coh, coh_on_hit_1
connect state, UInt<5>(0h4)
else :
wire new_coh_meta_1 : { state : UInt<2>}
connect new_coh_meta_1.state, UInt<2>(0h0)
connect new_coh, new_coh_meta_1
connect state, UInt<5>(0h1)
else :
node _T_89 = and(io.req_pri_val, io.req_pri_rdy)
when _T_89 :
connect grant_had_data, UInt<1>(0h0)
wire state_new_state_1 : UInt
connect state_new_state_1, state
connect grantack.valid, UInt<1>(0h0)
connect refill_ctr, UInt<1>(0h0)
node _state_T_34 = asUInt(reset)
node _state_T_35 = eq(_state_T_34, UInt<1>(0h0))
when _state_T_35 :
node _state_T_36 = eq(rpq.io.enq.ready, UInt<1>(0h0))
when _state_T_36 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:194 assert(rpq.io.enq.ready)\n") : state_printf_2
assert(clock, rpq.io.enq.ready, UInt<1>(0h1), "") : state_assert_2
connect req, io.req
node _state_req_needs_wb_r_T_64 = eq(UInt<5>(0h10), UInt<5>(0h10))
node _state_req_needs_wb_r_T_65 = mux(_state_req_needs_wb_r_T_64, UInt<2>(0h2), UInt<2>(0h2))
node _state_req_needs_wb_r_T_66 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _state_req_needs_wb_r_T_67 = mux(_state_req_needs_wb_r_T_66, UInt<2>(0h1), _state_req_needs_wb_r_T_65)
node _state_req_needs_wb_r_T_68 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _state_req_needs_wb_r_T_69 = mux(_state_req_needs_wb_r_T_68, UInt<2>(0h0), _state_req_needs_wb_r_T_67)
node _state_req_needs_wb_r_T_70 = cat(_state_req_needs_wb_r_T_69, io.req.old_meta.coh.state)
node _state_req_needs_wb_r_T_71 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _state_req_needs_wb_r_T_72 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _state_req_needs_wb_r_T_73 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _state_req_needs_wb_r_T_74 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _state_req_needs_wb_r_T_75 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _state_req_needs_wb_r_T_76 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _state_req_needs_wb_r_T_77 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _state_req_needs_wb_r_T_78 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _state_req_needs_wb_r_T_79 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _state_req_needs_wb_r_T_80 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _state_req_needs_wb_r_T_81 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _state_req_needs_wb_r_T_82 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _state_req_needs_wb_r_T_83 = eq(_state_req_needs_wb_r_T_82, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_84 = mux(_state_req_needs_wb_r_T_83, UInt<1>(0h0), UInt<1>(0h0))
node _state_req_needs_wb_r_T_85 = mux(_state_req_needs_wb_r_T_83, UInt<3>(0h5), UInt<1>(0h0))
node _state_req_needs_wb_r_T_86 = mux(_state_req_needs_wb_r_T_83, UInt<2>(0h0), UInt<1>(0h0))
node _state_req_needs_wb_r_T_87 = eq(_state_req_needs_wb_r_T_81, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_88 = mux(_state_req_needs_wb_r_T_87, UInt<1>(0h0), _state_req_needs_wb_r_T_84)
node _state_req_needs_wb_r_T_89 = mux(_state_req_needs_wb_r_T_87, UInt<3>(0h2), _state_req_needs_wb_r_T_85)
node _state_req_needs_wb_r_T_90 = mux(_state_req_needs_wb_r_T_87, UInt<2>(0h0), _state_req_needs_wb_r_T_86)
node _state_req_needs_wb_r_T_91 = eq(_state_req_needs_wb_r_T_80, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_92 = mux(_state_req_needs_wb_r_T_91, UInt<1>(0h0), _state_req_needs_wb_r_T_88)
node _state_req_needs_wb_r_T_93 = mux(_state_req_needs_wb_r_T_91, UInt<3>(0h1), _state_req_needs_wb_r_T_89)
node _state_req_needs_wb_r_T_94 = mux(_state_req_needs_wb_r_T_91, UInt<2>(0h0), _state_req_needs_wb_r_T_90)
node _state_req_needs_wb_r_T_95 = eq(_state_req_needs_wb_r_T_79, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_96 = mux(_state_req_needs_wb_r_T_95, UInt<1>(0h1), _state_req_needs_wb_r_T_92)
node _state_req_needs_wb_r_T_97 = mux(_state_req_needs_wb_r_T_95, UInt<3>(0h1), _state_req_needs_wb_r_T_93)
node _state_req_needs_wb_r_T_98 = mux(_state_req_needs_wb_r_T_95, UInt<2>(0h0), _state_req_needs_wb_r_T_94)
node _state_req_needs_wb_r_T_99 = eq(_state_req_needs_wb_r_T_78, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_100 = mux(_state_req_needs_wb_r_T_99, UInt<1>(0h0), _state_req_needs_wb_r_T_96)
node _state_req_needs_wb_r_T_101 = mux(_state_req_needs_wb_r_T_99, UInt<3>(0h5), _state_req_needs_wb_r_T_97)
node _state_req_needs_wb_r_T_102 = mux(_state_req_needs_wb_r_T_99, UInt<2>(0h0), _state_req_needs_wb_r_T_98)
node _state_req_needs_wb_r_T_103 = eq(_state_req_needs_wb_r_T_77, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_104 = mux(_state_req_needs_wb_r_T_103, UInt<1>(0h0), _state_req_needs_wb_r_T_100)
node _state_req_needs_wb_r_T_105 = mux(_state_req_needs_wb_r_T_103, UInt<3>(0h4), _state_req_needs_wb_r_T_101)
node _state_req_needs_wb_r_T_106 = mux(_state_req_needs_wb_r_T_103, UInt<2>(0h1), _state_req_needs_wb_r_T_102)
node _state_req_needs_wb_r_T_107 = eq(_state_req_needs_wb_r_T_76, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_108 = mux(_state_req_needs_wb_r_T_107, UInt<1>(0h0), _state_req_needs_wb_r_T_104)
node _state_req_needs_wb_r_T_109 = mux(_state_req_needs_wb_r_T_107, UInt<3>(0h0), _state_req_needs_wb_r_T_105)
node _state_req_needs_wb_r_T_110 = mux(_state_req_needs_wb_r_T_107, UInt<2>(0h1), _state_req_needs_wb_r_T_106)
node _state_req_needs_wb_r_T_111 = eq(_state_req_needs_wb_r_T_75, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_112 = mux(_state_req_needs_wb_r_T_111, UInt<1>(0h1), _state_req_needs_wb_r_T_108)
node _state_req_needs_wb_r_T_113 = mux(_state_req_needs_wb_r_T_111, UInt<3>(0h0), _state_req_needs_wb_r_T_109)
node _state_req_needs_wb_r_T_114 = mux(_state_req_needs_wb_r_T_111, UInt<2>(0h1), _state_req_needs_wb_r_T_110)
node _state_req_needs_wb_r_T_115 = eq(_state_req_needs_wb_r_T_74, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_116 = mux(_state_req_needs_wb_r_T_115, UInt<1>(0h0), _state_req_needs_wb_r_T_112)
node _state_req_needs_wb_r_T_117 = mux(_state_req_needs_wb_r_T_115, UInt<3>(0h5), _state_req_needs_wb_r_T_113)
node _state_req_needs_wb_r_T_118 = mux(_state_req_needs_wb_r_T_115, UInt<2>(0h0), _state_req_needs_wb_r_T_114)
node _state_req_needs_wb_r_T_119 = eq(_state_req_needs_wb_r_T_73, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_120 = mux(_state_req_needs_wb_r_T_119, UInt<1>(0h0), _state_req_needs_wb_r_T_116)
node _state_req_needs_wb_r_T_121 = mux(_state_req_needs_wb_r_T_119, UInt<3>(0h4), _state_req_needs_wb_r_T_117)
node _state_req_needs_wb_r_T_122 = mux(_state_req_needs_wb_r_T_119, UInt<2>(0h1), _state_req_needs_wb_r_T_118)
node _state_req_needs_wb_r_T_123 = eq(_state_req_needs_wb_r_T_72, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_124 = mux(_state_req_needs_wb_r_T_123, UInt<1>(0h0), _state_req_needs_wb_r_T_120)
node _state_req_needs_wb_r_T_125 = mux(_state_req_needs_wb_r_T_123, UInt<3>(0h3), _state_req_needs_wb_r_T_121)
node _state_req_needs_wb_r_T_126 = mux(_state_req_needs_wb_r_T_123, UInt<2>(0h2), _state_req_needs_wb_r_T_122)
node _state_req_needs_wb_r_T_127 = eq(_state_req_needs_wb_r_T_71, _state_req_needs_wb_r_T_70)
node state_req_needs_wb_r_1_1 = mux(_state_req_needs_wb_r_T_127, UInt<1>(0h1), _state_req_needs_wb_r_T_124)
node state_req_needs_wb_r_2_1 = mux(_state_req_needs_wb_r_T_127, UInt<3>(0h3), _state_req_needs_wb_r_T_125)
node state_req_needs_wb_r_3_1 = mux(_state_req_needs_wb_r_T_127, UInt<2>(0h2), _state_req_needs_wb_r_T_126)
wire state_req_needs_wb_meta_1 : { state : UInt<2>}
connect state_req_needs_wb_meta_1.state, state_req_needs_wb_r_3_1
connect req_needs_wb, state_req_needs_wb_r_1_1
when io.req.tag_match :
node _state_r_c_cat_T_50 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_r_c_cat_T_51 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_r_c_cat_T_52 = or(_state_r_c_cat_T_50, _state_r_c_cat_T_51)
node _state_r_c_cat_T_53 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_r_c_cat_T_54 = or(_state_r_c_cat_T_52, _state_r_c_cat_T_53)
node _state_r_c_cat_T_55 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_r_c_cat_T_56 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_r_c_cat_T_57 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_r_c_cat_T_58 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_r_c_cat_T_59 = or(_state_r_c_cat_T_55, _state_r_c_cat_T_56)
node _state_r_c_cat_T_60 = or(_state_r_c_cat_T_59, _state_r_c_cat_T_57)
node _state_r_c_cat_T_61 = or(_state_r_c_cat_T_60, _state_r_c_cat_T_58)
node _state_r_c_cat_T_62 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_r_c_cat_T_63 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_r_c_cat_T_64 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_r_c_cat_T_65 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_r_c_cat_T_66 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_r_c_cat_T_67 = or(_state_r_c_cat_T_62, _state_r_c_cat_T_63)
node _state_r_c_cat_T_68 = or(_state_r_c_cat_T_67, _state_r_c_cat_T_64)
node _state_r_c_cat_T_69 = or(_state_r_c_cat_T_68, _state_r_c_cat_T_65)
node _state_r_c_cat_T_70 = or(_state_r_c_cat_T_69, _state_r_c_cat_T_66)
node _state_r_c_cat_T_71 = or(_state_r_c_cat_T_61, _state_r_c_cat_T_70)
node _state_r_c_cat_T_72 = or(_state_r_c_cat_T_54, _state_r_c_cat_T_71)
node _state_r_c_cat_T_73 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_r_c_cat_T_74 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_r_c_cat_T_75 = or(_state_r_c_cat_T_73, _state_r_c_cat_T_74)
node _state_r_c_cat_T_76 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_r_c_cat_T_77 = or(_state_r_c_cat_T_75, _state_r_c_cat_T_76)
node _state_r_c_cat_T_78 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_r_c_cat_T_79 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_r_c_cat_T_80 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_r_c_cat_T_81 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_r_c_cat_T_82 = or(_state_r_c_cat_T_78, _state_r_c_cat_T_79)
node _state_r_c_cat_T_83 = or(_state_r_c_cat_T_82, _state_r_c_cat_T_80)
node _state_r_c_cat_T_84 = or(_state_r_c_cat_T_83, _state_r_c_cat_T_81)
node _state_r_c_cat_T_85 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_r_c_cat_T_86 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_r_c_cat_T_87 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_r_c_cat_T_88 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_r_c_cat_T_89 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_r_c_cat_T_90 = or(_state_r_c_cat_T_85, _state_r_c_cat_T_86)
node _state_r_c_cat_T_91 = or(_state_r_c_cat_T_90, _state_r_c_cat_T_87)
node _state_r_c_cat_T_92 = or(_state_r_c_cat_T_91, _state_r_c_cat_T_88)
node _state_r_c_cat_T_93 = or(_state_r_c_cat_T_92, _state_r_c_cat_T_89)
node _state_r_c_cat_T_94 = or(_state_r_c_cat_T_84, _state_r_c_cat_T_93)
node _state_r_c_cat_T_95 = or(_state_r_c_cat_T_77, _state_r_c_cat_T_94)
node _state_r_c_cat_T_96 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _state_r_c_cat_T_97 = or(_state_r_c_cat_T_95, _state_r_c_cat_T_96)
node _state_r_c_cat_T_98 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _state_r_c_cat_T_99 = or(_state_r_c_cat_T_97, _state_r_c_cat_T_98)
node state_r_c_1 = cat(_state_r_c_cat_T_72, _state_r_c_cat_T_99)
node _state_r_T_59 = cat(state_r_c_1, io.req.old_meta.coh.state)
node _state_r_T_60 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_61 = cat(_state_r_T_60, UInt<2>(0h3))
node _state_r_T_62 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_63 = cat(_state_r_T_62, UInt<2>(0h2))
node _state_r_T_64 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_65 = cat(_state_r_T_64, UInt<2>(0h1))
node _state_r_T_66 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_67 = cat(_state_r_T_66, UInt<2>(0h3))
node _state_r_T_68 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_69 = cat(_state_r_T_68, UInt<2>(0h2))
node _state_r_T_70 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_71 = cat(_state_r_T_70, UInt<2>(0h3))
node _state_r_T_72 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_73 = cat(_state_r_T_72, UInt<2>(0h2))
node _state_r_T_74 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_75 = cat(_state_r_T_74, UInt<2>(0h0))
node _state_r_T_76 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_77 = cat(_state_r_T_76, UInt<2>(0h1))
node _state_r_T_78 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_79 = cat(_state_r_T_78, UInt<2>(0h0))
node _state_r_T_80 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_81 = cat(_state_r_T_80, UInt<2>(0h1))
node _state_r_T_82 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_83 = cat(_state_r_T_82, UInt<2>(0h0))
node _state_r_T_84 = eq(_state_r_T_83, _state_r_T_59)
node _state_r_T_85 = mux(_state_r_T_84, UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_86 = mux(_state_r_T_84, UInt<2>(0h1), UInt<1>(0h0))
node _state_r_T_87 = eq(_state_r_T_81, _state_r_T_59)
node _state_r_T_88 = mux(_state_r_T_87, UInt<1>(0h0), _state_r_T_85)
node _state_r_T_89 = mux(_state_r_T_87, UInt<2>(0h2), _state_r_T_86)
node _state_r_T_90 = eq(_state_r_T_79, _state_r_T_59)
node _state_r_T_91 = mux(_state_r_T_90, UInt<1>(0h0), _state_r_T_88)
node _state_r_T_92 = mux(_state_r_T_90, UInt<2>(0h1), _state_r_T_89)
node _state_r_T_93 = eq(_state_r_T_77, _state_r_T_59)
node _state_r_T_94 = mux(_state_r_T_93, UInt<1>(0h0), _state_r_T_91)
node _state_r_T_95 = mux(_state_r_T_93, UInt<2>(0h2), _state_r_T_92)
node _state_r_T_96 = eq(_state_r_T_75, _state_r_T_59)
node _state_r_T_97 = mux(_state_r_T_96, UInt<1>(0h0), _state_r_T_94)
node _state_r_T_98 = mux(_state_r_T_96, UInt<2>(0h0), _state_r_T_95)
node _state_r_T_99 = eq(_state_r_T_73, _state_r_T_59)
node _state_r_T_100 = mux(_state_r_T_99, UInt<1>(0h1), _state_r_T_97)
node _state_r_T_101 = mux(_state_r_T_99, UInt<2>(0h3), _state_r_T_98)
node _state_r_T_102 = eq(_state_r_T_71, _state_r_T_59)
node _state_r_T_103 = mux(_state_r_T_102, UInt<1>(0h1), _state_r_T_100)
node _state_r_T_104 = mux(_state_r_T_102, UInt<2>(0h3), _state_r_T_101)
node _state_r_T_105 = eq(_state_r_T_69, _state_r_T_59)
node _state_r_T_106 = mux(_state_r_T_105, UInt<1>(0h1), _state_r_T_103)
node _state_r_T_107 = mux(_state_r_T_105, UInt<2>(0h2), _state_r_T_104)
node _state_r_T_108 = eq(_state_r_T_67, _state_r_T_59)
node _state_r_T_109 = mux(_state_r_T_108, UInt<1>(0h1), _state_r_T_106)
node _state_r_T_110 = mux(_state_r_T_108, UInt<2>(0h3), _state_r_T_107)
node _state_r_T_111 = eq(_state_r_T_65, _state_r_T_59)
node _state_r_T_112 = mux(_state_r_T_111, UInt<1>(0h1), _state_r_T_109)
node _state_r_T_113 = mux(_state_r_T_111, UInt<2>(0h1), _state_r_T_110)
node _state_r_T_114 = eq(_state_r_T_63, _state_r_T_59)
node _state_r_T_115 = mux(_state_r_T_114, UInt<1>(0h1), _state_r_T_112)
node _state_r_T_116 = mux(_state_r_T_114, UInt<2>(0h2), _state_r_T_113)
node _state_r_T_117 = eq(_state_r_T_61, _state_r_T_59)
node state_is_hit_1 = mux(_state_r_T_117, UInt<1>(0h1), _state_r_T_115)
node state_r_2_1 = mux(_state_r_T_117, UInt<2>(0h3), _state_r_T_116)
wire state_coh_on_hit_1 : { state : UInt<2>}
connect state_coh_on_hit_1.state, state_r_2_1
when state_is_hit_1 :
node _state_T_37 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_T_38 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_T_39 = or(_state_T_37, _state_T_38)
node _state_T_40 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_T_41 = or(_state_T_39, _state_T_40)
node _state_T_42 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_T_43 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_T_44 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_T_45 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_T_46 = or(_state_T_42, _state_T_43)
node _state_T_47 = or(_state_T_46, _state_T_44)
node _state_T_48 = or(_state_T_47, _state_T_45)
node _state_T_49 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_T_50 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_T_51 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_T_52 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_T_53 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_T_54 = or(_state_T_49, _state_T_50)
node _state_T_55 = or(_state_T_54, _state_T_51)
node _state_T_56 = or(_state_T_55, _state_T_52)
node _state_T_57 = or(_state_T_56, _state_T_53)
node _state_T_58 = or(_state_T_48, _state_T_57)
node _state_T_59 = or(_state_T_41, _state_T_58)
node _state_T_60 = asUInt(reset)
node _state_T_61 = eq(_state_T_60, UInt<1>(0h0))
when _state_T_61 :
node _state_T_62 = eq(_state_T_59, UInt<1>(0h0))
when _state_T_62 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:201 assert(isWrite(io.req.uop.mem_cmd))\n") : state_printf_3
assert(clock, _state_T_59, UInt<1>(0h1), "") : state_assert_3
connect new_coh, state_coh_on_hit_1
connect state_new_state_1, UInt<5>(0hc)
else :
connect new_coh, io.req.old_meta.coh
connect state_new_state_1, UInt<5>(0h1)
else :
wire state_new_coh_meta_1 : { state : UInt<2>}
connect state_new_coh_meta_1.state, UInt<2>(0h0)
connect new_coh, state_new_coh_meta_1
connect state_new_state_1, UInt<5>(0h1)
connect state, state_new_state_1 | module BoomMSHR_3( // @[mshrs.scala:36:7]
input clock, // @[mshrs.scala:36:7]
input reset, // @[mshrs.scala:36:7]
input io_req_pri_val, // @[mshrs.scala:39:14]
output io_req_pri_rdy, // @[mshrs.scala:39:14]
input io_req_sec_val, // @[mshrs.scala:39:14]
output io_req_sec_rdy, // @[mshrs.scala:39:14]
input io_clear_prefetch, // @[mshrs.scala:39:14]
input [7:0] io_brupdate_b1_resolve_mask, // @[mshrs.scala:39:14]
input [7:0] io_brupdate_b1_mispredict_mask, // @[mshrs.scala:39:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[mshrs.scala:39:14]
input [31:0] io_brupdate_b2_uop_inst, // @[mshrs.scala:39:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_is_rvc, // @[mshrs.scala:39:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[mshrs.scala:39:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[mshrs.scala:39:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[mshrs.scala:39:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[mshrs.scala:39:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[mshrs.scala:39:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[mshrs.scala:39:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[mshrs.scala:39:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[mshrs.scala:39:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_is_br, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_is_jalr, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_is_jal, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_is_sfb, // @[mshrs.scala:39:14]
input [7:0] io_brupdate_b2_uop_br_mask, // @[mshrs.scala:39:14]
input [2:0] io_brupdate_b2_uop_br_tag, // @[mshrs.scala:39:14]
input [3:0] io_brupdate_b2_uop_ftq_idx, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_edge_inst, // @[mshrs.scala:39:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_taken, // @[mshrs.scala:39:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[mshrs.scala:39:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[mshrs.scala:39:14]
input [4:0] io_brupdate_b2_uop_rob_idx, // @[mshrs.scala:39:14]
input [2:0] io_brupdate_b2_uop_ldq_idx, // @[mshrs.scala:39:14]
input [2:0] io_brupdate_b2_uop_stq_idx, // @[mshrs.scala:39:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[mshrs.scala:39:14]
input [5:0] io_brupdate_b2_uop_pdst, // @[mshrs.scala:39:14]
input [5:0] io_brupdate_b2_uop_prs1, // @[mshrs.scala:39:14]
input [5:0] io_brupdate_b2_uop_prs2, // @[mshrs.scala:39:14]
input [5:0] io_brupdate_b2_uop_prs3, // @[mshrs.scala:39:14]
input [3:0] io_brupdate_b2_uop_ppred, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_prs1_busy, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_prs2_busy, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_prs3_busy, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_ppred_busy, // @[mshrs.scala:39:14]
input [5:0] io_brupdate_b2_uop_stale_pdst, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_exception, // @[mshrs.scala:39:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_bypassable, // @[mshrs.scala:39:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[mshrs.scala:39:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_mem_signed, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_is_fence, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_is_fencei, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_is_amo, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_uses_ldq, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_uses_stq, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_is_unique, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_flush_on_commit, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[mshrs.scala:39:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[mshrs.scala:39:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[mshrs.scala:39:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[mshrs.scala:39:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_ldst_val, // @[mshrs.scala:39:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[mshrs.scala:39:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[mshrs.scala:39:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_frs3_en, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_fp_val, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_fp_single, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_bp_debug_if, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[mshrs.scala:39:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[mshrs.scala:39:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[mshrs.scala:39:14]
input io_brupdate_b2_valid, // @[mshrs.scala:39:14]
input io_brupdate_b2_mispredict, // @[mshrs.scala:39:14]
input io_brupdate_b2_taken, // @[mshrs.scala:39:14]
input [2:0] io_brupdate_b2_cfi_type, // @[mshrs.scala:39:14]
input [1:0] io_brupdate_b2_pc_sel, // @[mshrs.scala:39:14]
input [39:0] io_brupdate_b2_jalr_target, // @[mshrs.scala:39:14]
input [20:0] io_brupdate_b2_target_offset, // @[mshrs.scala:39:14]
input io_exception, // @[mshrs.scala:39:14]
input [4:0] io_rob_pnr_idx, // @[mshrs.scala:39:14]
input [4:0] io_rob_head_idx, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_uopc, // @[mshrs.scala:39:14]
input [31:0] io_req_uop_inst, // @[mshrs.scala:39:14]
input [31:0] io_req_uop_debug_inst, // @[mshrs.scala:39:14]
input io_req_uop_is_rvc, // @[mshrs.scala:39:14]
input [39:0] io_req_uop_debug_pc, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_iq_type, // @[mshrs.scala:39:14]
input [9:0] io_req_uop_fu_code, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_ctrl_br_type, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_ctrl_op1_sel, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_ctrl_op2_sel, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_ctrl_imm_sel, // @[mshrs.scala:39:14]
input [4:0] io_req_uop_ctrl_op_fcn, // @[mshrs.scala:39:14]
input io_req_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14]
input io_req_uop_ctrl_is_load, // @[mshrs.scala:39:14]
input io_req_uop_ctrl_is_sta, // @[mshrs.scala:39:14]
input io_req_uop_ctrl_is_std, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_iw_state, // @[mshrs.scala:39:14]
input io_req_uop_iw_p1_poisoned, // @[mshrs.scala:39:14]
input io_req_uop_iw_p2_poisoned, // @[mshrs.scala:39:14]
input io_req_uop_is_br, // @[mshrs.scala:39:14]
input io_req_uop_is_jalr, // @[mshrs.scala:39:14]
input io_req_uop_is_jal, // @[mshrs.scala:39:14]
input io_req_uop_is_sfb, // @[mshrs.scala:39:14]
input [7:0] io_req_uop_br_mask, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_br_tag, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_ftq_idx, // @[mshrs.scala:39:14]
input io_req_uop_edge_inst, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_pc_lob, // @[mshrs.scala:39:14]
input io_req_uop_taken, // @[mshrs.scala:39:14]
input [19:0] io_req_uop_imm_packed, // @[mshrs.scala:39:14]
input [11:0] io_req_uop_csr_addr, // @[mshrs.scala:39:14]
input [4:0] io_req_uop_rob_idx, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_ldq_idx, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_stq_idx, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_rxq_idx, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_pdst, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_prs1, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_prs2, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_prs3, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_ppred, // @[mshrs.scala:39:14]
input io_req_uop_prs1_busy, // @[mshrs.scala:39:14]
input io_req_uop_prs2_busy, // @[mshrs.scala:39:14]
input io_req_uop_prs3_busy, // @[mshrs.scala:39:14]
input io_req_uop_ppred_busy, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_stale_pdst, // @[mshrs.scala:39:14]
input io_req_uop_exception, // @[mshrs.scala:39:14]
input [63:0] io_req_uop_exc_cause, // @[mshrs.scala:39:14]
input io_req_uop_bypassable, // @[mshrs.scala:39:14]
input [4:0] io_req_uop_mem_cmd, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_mem_size, // @[mshrs.scala:39:14]
input io_req_uop_mem_signed, // @[mshrs.scala:39:14]
input io_req_uop_is_fence, // @[mshrs.scala:39:14]
input io_req_uop_is_fencei, // @[mshrs.scala:39:14]
input io_req_uop_is_amo, // @[mshrs.scala:39:14]
input io_req_uop_uses_ldq, // @[mshrs.scala:39:14]
input io_req_uop_uses_stq, // @[mshrs.scala:39:14]
input io_req_uop_is_sys_pc2epc, // @[mshrs.scala:39:14]
input io_req_uop_is_unique, // @[mshrs.scala:39:14]
input io_req_uop_flush_on_commit, // @[mshrs.scala:39:14]
input io_req_uop_ldst_is_rs1, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_ldst, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_lrs1, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_lrs2, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_lrs3, // @[mshrs.scala:39:14]
input io_req_uop_ldst_val, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_dst_rtype, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_lrs1_rtype, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_lrs2_rtype, // @[mshrs.scala:39:14]
input io_req_uop_frs3_en, // @[mshrs.scala:39:14]
input io_req_uop_fp_val, // @[mshrs.scala:39:14]
input io_req_uop_fp_single, // @[mshrs.scala:39:14]
input io_req_uop_xcpt_pf_if, // @[mshrs.scala:39:14]
input io_req_uop_xcpt_ae_if, // @[mshrs.scala:39:14]
input io_req_uop_xcpt_ma_if, // @[mshrs.scala:39:14]
input io_req_uop_bp_debug_if, // @[mshrs.scala:39:14]
input io_req_uop_bp_xcpt_if, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_debug_fsrc, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_debug_tsrc, // @[mshrs.scala:39:14]
input [39:0] io_req_addr, // @[mshrs.scala:39:14]
input [63:0] io_req_data, // @[mshrs.scala:39:14]
input io_req_is_hella, // @[mshrs.scala:39:14]
input io_req_tag_match, // @[mshrs.scala:39:14]
input [1:0] io_req_old_meta_coh_state, // @[mshrs.scala:39:14]
input [19:0] io_req_old_meta_tag, // @[mshrs.scala:39:14]
input [3:0] io_req_way_en, // @[mshrs.scala:39:14]
input [4:0] io_req_sdq_id, // @[mshrs.scala:39:14]
input io_req_is_probe, // @[mshrs.scala:39:14]
output io_idx_valid, // @[mshrs.scala:39:14]
output [5:0] io_idx_bits, // @[mshrs.scala:39:14]
output io_way_valid, // @[mshrs.scala:39:14]
output [3:0] io_way_bits, // @[mshrs.scala:39:14]
output io_tag_valid, // @[mshrs.scala:39:14]
output [27:0] io_tag_bits, // @[mshrs.scala:39:14]
input io_mem_acquire_ready, // @[mshrs.scala:39:14]
output io_mem_acquire_valid, // @[mshrs.scala:39:14]
output [2:0] io_mem_acquire_bits_param, // @[mshrs.scala:39:14]
output [31:0] io_mem_acquire_bits_address, // @[mshrs.scala:39:14]
output io_mem_grant_ready, // @[mshrs.scala:39:14]
input io_mem_grant_valid, // @[mshrs.scala:39:14]
input [2:0] io_mem_grant_bits_opcode, // @[mshrs.scala:39:14]
input [1:0] io_mem_grant_bits_param, // @[mshrs.scala:39:14]
input [3:0] io_mem_grant_bits_size, // @[mshrs.scala:39:14]
input [1:0] io_mem_grant_bits_source, // @[mshrs.scala:39:14]
input [2:0] io_mem_grant_bits_sink, // @[mshrs.scala:39:14]
input io_mem_grant_bits_denied, // @[mshrs.scala:39:14]
input [63:0] io_mem_grant_bits_data, // @[mshrs.scala:39:14]
input io_mem_grant_bits_corrupt, // @[mshrs.scala:39:14]
input io_mem_finish_ready, // @[mshrs.scala:39:14]
output io_mem_finish_valid, // @[mshrs.scala:39:14]
output [2:0] io_mem_finish_bits_sink, // @[mshrs.scala:39:14]
input io_prober_state_valid, // @[mshrs.scala:39:14]
input [39:0] io_prober_state_bits, // @[mshrs.scala:39:14]
input io_refill_ready, // @[mshrs.scala:39:14]
output io_refill_valid, // @[mshrs.scala:39:14]
output [3:0] io_refill_bits_way_en, // @[mshrs.scala:39:14]
output [11:0] io_refill_bits_addr, // @[mshrs.scala:39:14]
output [63:0] io_refill_bits_data, // @[mshrs.scala:39:14]
input io_meta_write_ready, // @[mshrs.scala:39:14]
output io_meta_write_valid, // @[mshrs.scala:39:14]
output [5:0] io_meta_write_bits_idx, // @[mshrs.scala:39:14]
output [3:0] io_meta_write_bits_way_en, // @[mshrs.scala:39:14]
output [1:0] io_meta_write_bits_data_coh_state, // @[mshrs.scala:39:14]
output [19:0] io_meta_write_bits_data_tag, // @[mshrs.scala:39:14]
input io_meta_read_ready, // @[mshrs.scala:39:14]
output io_meta_read_valid, // @[mshrs.scala:39:14]
output [5:0] io_meta_read_bits_idx, // @[mshrs.scala:39:14]
output [3:0] io_meta_read_bits_way_en, // @[mshrs.scala:39:14]
output [19:0] io_meta_read_bits_tag, // @[mshrs.scala:39:14]
input io_meta_resp_valid, // @[mshrs.scala:39:14]
input [1:0] io_meta_resp_bits_coh_state, // @[mshrs.scala:39:14]
input [19:0] io_meta_resp_bits_tag, // @[mshrs.scala:39:14]
input io_wb_req_ready, // @[mshrs.scala:39:14]
output io_wb_req_valid, // @[mshrs.scala:39:14]
output [19:0] io_wb_req_bits_tag, // @[mshrs.scala:39:14]
output [5:0] io_wb_req_bits_idx, // @[mshrs.scala:39:14]
output [2:0] io_wb_req_bits_param, // @[mshrs.scala:39:14]
output [3:0] io_wb_req_bits_way_en, // @[mshrs.scala:39:14]
output io_commit_val, // @[mshrs.scala:39:14]
output [39:0] io_commit_addr, // @[mshrs.scala:39:14]
output [1:0] io_commit_coh_state, // @[mshrs.scala:39:14]
input io_lb_read_ready, // @[mshrs.scala:39:14]
output io_lb_read_valid, // @[mshrs.scala:39:14]
output [2:0] io_lb_read_bits_offset, // @[mshrs.scala:39:14]
input [63:0] io_lb_resp, // @[mshrs.scala:39:14]
input io_lb_write_ready, // @[mshrs.scala:39:14]
output io_lb_write_valid, // @[mshrs.scala:39:14]
output [2:0] io_lb_write_bits_offset, // @[mshrs.scala:39:14]
output [63:0] io_lb_write_bits_data, // @[mshrs.scala:39:14]
input io_replay_ready, // @[mshrs.scala:39:14]
output io_replay_valid, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_uopc, // @[mshrs.scala:39:14]
output [31:0] io_replay_bits_uop_inst, // @[mshrs.scala:39:14]
output [31:0] io_replay_bits_uop_debug_inst, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_rvc, // @[mshrs.scala:39:14]
output [39:0] io_replay_bits_uop_debug_pc, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_iq_type, // @[mshrs.scala:39:14]
output [9:0] io_replay_bits_uop_fu_code, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_ctrl_br_type, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_ctrl_op1_sel, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_ctrl_op2_sel, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_ctrl_imm_sel, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_uop_ctrl_op_fcn, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ctrl_is_load, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ctrl_is_sta, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ctrl_is_std, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_iw_state, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iw_p1_poisoned, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iw_p2_poisoned, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_br, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_jalr, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_jal, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_sfb, // @[mshrs.scala:39:14]
output [7:0] io_replay_bits_uop_br_mask, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_br_tag, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_ftq_idx, // @[mshrs.scala:39:14]
output io_replay_bits_uop_edge_inst, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_pc_lob, // @[mshrs.scala:39:14]
output io_replay_bits_uop_taken, // @[mshrs.scala:39:14]
output [19:0] io_replay_bits_uop_imm_packed, // @[mshrs.scala:39:14]
output [11:0] io_replay_bits_uop_csr_addr, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_uop_rob_idx, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_ldq_idx, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_stq_idx, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_rxq_idx, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_pdst, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_prs1, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_prs2, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_prs3, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_ppred, // @[mshrs.scala:39:14]
output io_replay_bits_uop_prs1_busy, // @[mshrs.scala:39:14]
output io_replay_bits_uop_prs2_busy, // @[mshrs.scala:39:14]
output io_replay_bits_uop_prs3_busy, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ppred_busy, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_stale_pdst, // @[mshrs.scala:39:14]
output io_replay_bits_uop_exception, // @[mshrs.scala:39:14]
output [63:0] io_replay_bits_uop_exc_cause, // @[mshrs.scala:39:14]
output io_replay_bits_uop_bypassable, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_uop_mem_cmd, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_mem_size, // @[mshrs.scala:39:14]
output io_replay_bits_uop_mem_signed, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_fence, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_fencei, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_amo, // @[mshrs.scala:39:14]
output io_replay_bits_uop_uses_ldq, // @[mshrs.scala:39:14]
output io_replay_bits_uop_uses_stq, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_unique, // @[mshrs.scala:39:14]
output io_replay_bits_uop_flush_on_commit, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_ldst, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_lrs1, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_lrs2, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_lrs3, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ldst_val, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_dst_rtype, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14]
output io_replay_bits_uop_frs3_en, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_val, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_single, // @[mshrs.scala:39:14]
output io_replay_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_bp_debug_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_debug_fsrc, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_debug_tsrc, // @[mshrs.scala:39:14]
output [39:0] io_replay_bits_addr, // @[mshrs.scala:39:14]
output [63:0] io_replay_bits_data, // @[mshrs.scala:39:14]
output io_replay_bits_is_hella, // @[mshrs.scala:39:14]
output io_replay_bits_tag_match, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_old_meta_coh_state, // @[mshrs.scala:39:14]
output [19:0] io_replay_bits_old_meta_tag, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_way_en, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_sdq_id, // @[mshrs.scala:39:14]
input io_resp_ready, // @[mshrs.scala:39:14]
output io_resp_valid, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_uopc, // @[mshrs.scala:39:14]
output [31:0] io_resp_bits_uop_inst, // @[mshrs.scala:39:14]
output [31:0] io_resp_bits_uop_debug_inst, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_rvc, // @[mshrs.scala:39:14]
output [39:0] io_resp_bits_uop_debug_pc, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_iq_type, // @[mshrs.scala:39:14]
output [9:0] io_resp_bits_uop_fu_code, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_ctrl_br_type, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[mshrs.scala:39:14]
output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ctrl_is_load, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ctrl_is_sta, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ctrl_is_std, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_iw_state, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iw_p1_poisoned, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iw_p2_poisoned, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_br, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_jalr, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_jal, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_sfb, // @[mshrs.scala:39:14]
output [7:0] io_resp_bits_uop_br_mask, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_br_tag, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_ftq_idx, // @[mshrs.scala:39:14]
output io_resp_bits_uop_edge_inst, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_pc_lob, // @[mshrs.scala:39:14]
output io_resp_bits_uop_taken, // @[mshrs.scala:39:14]
output [19:0] io_resp_bits_uop_imm_packed, // @[mshrs.scala:39:14]
output [11:0] io_resp_bits_uop_csr_addr, // @[mshrs.scala:39:14]
output [4:0] io_resp_bits_uop_rob_idx, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_ldq_idx, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_stq_idx, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_rxq_idx, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_pdst, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_prs1, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_prs2, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_prs3, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_ppred, // @[mshrs.scala:39:14]
output io_resp_bits_uop_prs1_busy, // @[mshrs.scala:39:14]
output io_resp_bits_uop_prs2_busy, // @[mshrs.scala:39:14]
output io_resp_bits_uop_prs3_busy, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ppred_busy, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_stale_pdst, // @[mshrs.scala:39:14]
output io_resp_bits_uop_exception, // @[mshrs.scala:39:14]
output [63:0] io_resp_bits_uop_exc_cause, // @[mshrs.scala:39:14]
output io_resp_bits_uop_bypassable, // @[mshrs.scala:39:14]
output [4:0] io_resp_bits_uop_mem_cmd, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_mem_size, // @[mshrs.scala:39:14]
output io_resp_bits_uop_mem_signed, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_fence, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_fencei, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_amo, // @[mshrs.scala:39:14]
output io_resp_bits_uop_uses_ldq, // @[mshrs.scala:39:14]
output io_resp_bits_uop_uses_stq, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_unique, // @[mshrs.scala:39:14]
output io_resp_bits_uop_flush_on_commit, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_ldst, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_lrs1, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_lrs2, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_lrs3, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ldst_val, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_dst_rtype, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14]
output io_resp_bits_uop_frs3_en, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_val, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_single, // @[mshrs.scala:39:14]
output io_resp_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_bp_debug_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_debug_fsrc, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_debug_tsrc, // @[mshrs.scala:39:14]
output [63:0] io_resp_bits_data, // @[mshrs.scala:39:14]
output io_resp_bits_is_hella, // @[mshrs.scala:39:14]
input io_wb_resp, // @[mshrs.scala:39:14]
output io_probe_rdy // @[mshrs.scala:39:14]
);
wire rpq_io_deq_ready; // @[mshrs.scala:135:20, :215:30, :222:40, :233:41, :256:45]
wire _rpq_io_enq_ready; // @[mshrs.scala:128:19]
wire _rpq_io_deq_valid; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_uopc; // @[mshrs.scala:128:19]
wire [31:0] _rpq_io_deq_bits_uop_inst; // @[mshrs.scala:128:19]
wire [31:0] _rpq_io_deq_bits_uop_debug_inst; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_rvc; // @[mshrs.scala:128:19]
wire [39:0] _rpq_io_deq_bits_uop_debug_pc; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_iq_type; // @[mshrs.scala:128:19]
wire [9:0] _rpq_io_deq_bits_uop_fu_code; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_ctrl_br_type; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_ctrl_op1_sel; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_ctrl_op2_sel; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_ctrl_imm_sel; // @[mshrs.scala:128:19]
wire [4:0] _rpq_io_deq_bits_uop_ctrl_op_fcn; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ctrl_fcn_dw; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_ctrl_csr_cmd; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ctrl_is_load; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ctrl_is_sta; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ctrl_is_std; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_iw_state; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iw_p1_poisoned; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iw_p2_poisoned; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_br; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_jalr; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_jal; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_sfb; // @[mshrs.scala:128:19]
wire [7:0] _rpq_io_deq_bits_uop_br_mask; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_br_tag; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_ftq_idx; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_edge_inst; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_pc_lob; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_taken; // @[mshrs.scala:128:19]
wire [19:0] _rpq_io_deq_bits_uop_imm_packed; // @[mshrs.scala:128:19]
wire [11:0] _rpq_io_deq_bits_uop_csr_addr; // @[mshrs.scala:128:19]
wire [4:0] _rpq_io_deq_bits_uop_rob_idx; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_ldq_idx; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_stq_idx; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_rxq_idx; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_pdst; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_prs1; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_prs2; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_prs3; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_ppred; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_prs1_busy; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_prs2_busy; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_prs3_busy; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ppred_busy; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_stale_pdst; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_exception; // @[mshrs.scala:128:19]
wire [63:0] _rpq_io_deq_bits_uop_exc_cause; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_bypassable; // @[mshrs.scala:128:19]
wire [4:0] _rpq_io_deq_bits_uop_mem_cmd; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_mem_size; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_mem_signed; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_fence; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_fencei; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_amo; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_uses_ldq; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_uses_stq; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_sys_pc2epc; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_unique; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_flush_on_commit; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ldst_is_rs1; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_ldst; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_lrs1; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_lrs2; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_lrs3; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ldst_val; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_dst_rtype; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_lrs1_rtype; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_lrs2_rtype; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_frs3_en; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_val; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_single; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_xcpt_pf_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_xcpt_ae_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_xcpt_ma_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_bp_debug_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_bp_xcpt_if; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_debug_fsrc; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_debug_tsrc; // @[mshrs.scala:128:19]
wire [39:0] _rpq_io_deq_bits_addr; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_is_hella; // @[mshrs.scala:128:19]
wire _rpq_io_empty; // @[mshrs.scala:128:19]
wire io_req_pri_val_0 = io_req_pri_val; // @[mshrs.scala:36:7]
wire io_req_sec_val_0 = io_req_sec_val; // @[mshrs.scala:36:7]
wire io_clear_prefetch_0 = io_clear_prefetch; // @[mshrs.scala:36:7]
wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[mshrs.scala:36:7]
wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[mshrs.scala:36:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[mshrs.scala:36:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[mshrs.scala:36:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[mshrs.scala:36:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[mshrs.scala:36:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[mshrs.scala:36:7]
wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[mshrs.scala:36:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[mshrs.scala:36:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[mshrs.scala:36:7]
wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[mshrs.scala:36:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[mshrs.scala:36:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[mshrs.scala:36:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[mshrs.scala:36:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[mshrs.scala:36:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[mshrs.scala:36:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[mshrs.scala:36:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[mshrs.scala:36:7]
wire io_exception_0 = io_exception; // @[mshrs.scala:36:7]
wire [4:0] io_rob_pnr_idx_0 = io_rob_pnr_idx; // @[mshrs.scala:36:7]
wire [4:0] io_rob_head_idx_0 = io_rob_head_idx; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_uopc_0 = io_req_uop_uopc; // @[mshrs.scala:36:7]
wire [31:0] io_req_uop_inst_0 = io_req_uop_inst; // @[mshrs.scala:36:7]
wire [31:0] io_req_uop_debug_inst_0 = io_req_uop_debug_inst; // @[mshrs.scala:36:7]
wire io_req_uop_is_rvc_0 = io_req_uop_is_rvc; // @[mshrs.scala:36:7]
wire [39:0] io_req_uop_debug_pc_0 = io_req_uop_debug_pc; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_iq_type_0 = io_req_uop_iq_type; // @[mshrs.scala:36:7]
wire [9:0] io_req_uop_fu_code_0 = io_req_uop_fu_code; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_ctrl_br_type_0 = io_req_uop_ctrl_br_type; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_ctrl_op1_sel_0 = io_req_uop_ctrl_op1_sel; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_ctrl_op2_sel_0 = io_req_uop_ctrl_op2_sel; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_ctrl_imm_sel_0 = io_req_uop_ctrl_imm_sel; // @[mshrs.scala:36:7]
wire [4:0] io_req_uop_ctrl_op_fcn_0 = io_req_uop_ctrl_op_fcn; // @[mshrs.scala:36:7]
wire io_req_uop_ctrl_fcn_dw_0 = io_req_uop_ctrl_fcn_dw; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_ctrl_csr_cmd_0 = io_req_uop_ctrl_csr_cmd; // @[mshrs.scala:36:7]
wire io_req_uop_ctrl_is_load_0 = io_req_uop_ctrl_is_load; // @[mshrs.scala:36:7]
wire io_req_uop_ctrl_is_sta_0 = io_req_uop_ctrl_is_sta; // @[mshrs.scala:36:7]
wire io_req_uop_ctrl_is_std_0 = io_req_uop_ctrl_is_std; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_iw_state_0 = io_req_uop_iw_state; // @[mshrs.scala:36:7]
wire io_req_uop_iw_p1_poisoned_0 = io_req_uop_iw_p1_poisoned; // @[mshrs.scala:36:7]
wire io_req_uop_iw_p2_poisoned_0 = io_req_uop_iw_p2_poisoned; // @[mshrs.scala:36:7]
wire io_req_uop_is_br_0 = io_req_uop_is_br; // @[mshrs.scala:36:7]
wire io_req_uop_is_jalr_0 = io_req_uop_is_jalr; // @[mshrs.scala:36:7]
wire io_req_uop_is_jal_0 = io_req_uop_is_jal; // @[mshrs.scala:36:7]
wire io_req_uop_is_sfb_0 = io_req_uop_is_sfb; // @[mshrs.scala:36:7]
wire [7:0] io_req_uop_br_mask_0 = io_req_uop_br_mask; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_br_tag_0 = io_req_uop_br_tag; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_ftq_idx_0 = io_req_uop_ftq_idx; // @[mshrs.scala:36:7]
wire io_req_uop_edge_inst_0 = io_req_uop_edge_inst; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_pc_lob_0 = io_req_uop_pc_lob; // @[mshrs.scala:36:7]
wire io_req_uop_taken_0 = io_req_uop_taken; // @[mshrs.scala:36:7]
wire [19:0] io_req_uop_imm_packed_0 = io_req_uop_imm_packed; // @[mshrs.scala:36:7]
wire [11:0] io_req_uop_csr_addr_0 = io_req_uop_csr_addr; // @[mshrs.scala:36:7]
wire [4:0] io_req_uop_rob_idx_0 = io_req_uop_rob_idx; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_ldq_idx_0 = io_req_uop_ldq_idx; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_stq_idx_0 = io_req_uop_stq_idx; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_rxq_idx_0 = io_req_uop_rxq_idx; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_pdst_0 = io_req_uop_pdst; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_prs1_0 = io_req_uop_prs1; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_prs2_0 = io_req_uop_prs2; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_prs3_0 = io_req_uop_prs3; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_ppred_0 = io_req_uop_ppred; // @[mshrs.scala:36:7]
wire io_req_uop_prs1_busy_0 = io_req_uop_prs1_busy; // @[mshrs.scala:36:7]
wire io_req_uop_prs2_busy_0 = io_req_uop_prs2_busy; // @[mshrs.scala:36:7]
wire io_req_uop_prs3_busy_0 = io_req_uop_prs3_busy; // @[mshrs.scala:36:7]
wire io_req_uop_ppred_busy_0 = io_req_uop_ppred_busy; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_stale_pdst_0 = io_req_uop_stale_pdst; // @[mshrs.scala:36:7]
wire io_req_uop_exception_0 = io_req_uop_exception; // @[mshrs.scala:36:7]
wire [63:0] io_req_uop_exc_cause_0 = io_req_uop_exc_cause; // @[mshrs.scala:36:7]
wire io_req_uop_bypassable_0 = io_req_uop_bypassable; // @[mshrs.scala:36:7]
wire [4:0] io_req_uop_mem_cmd_0 = io_req_uop_mem_cmd; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_mem_size_0 = io_req_uop_mem_size; // @[mshrs.scala:36:7]
wire io_req_uop_mem_signed_0 = io_req_uop_mem_signed; // @[mshrs.scala:36:7]
wire io_req_uop_is_fence_0 = io_req_uop_is_fence; // @[mshrs.scala:36:7]
wire io_req_uop_is_fencei_0 = io_req_uop_is_fencei; // @[mshrs.scala:36:7]
wire io_req_uop_is_amo_0 = io_req_uop_is_amo; // @[mshrs.scala:36:7]
wire io_req_uop_uses_ldq_0 = io_req_uop_uses_ldq; // @[mshrs.scala:36:7]
wire io_req_uop_uses_stq_0 = io_req_uop_uses_stq; // @[mshrs.scala:36:7]
wire io_req_uop_is_sys_pc2epc_0 = io_req_uop_is_sys_pc2epc; // @[mshrs.scala:36:7]
wire io_req_uop_is_unique_0 = io_req_uop_is_unique; // @[mshrs.scala:36:7]
wire io_req_uop_flush_on_commit_0 = io_req_uop_flush_on_commit; // @[mshrs.scala:36:7]
wire io_req_uop_ldst_is_rs1_0 = io_req_uop_ldst_is_rs1; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_ldst_0 = io_req_uop_ldst; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_lrs1_0 = io_req_uop_lrs1; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_lrs2_0 = io_req_uop_lrs2; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_lrs3_0 = io_req_uop_lrs3; // @[mshrs.scala:36:7]
wire io_req_uop_ldst_val_0 = io_req_uop_ldst_val; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_dst_rtype_0 = io_req_uop_dst_rtype; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_lrs1_rtype_0 = io_req_uop_lrs1_rtype; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_lrs2_rtype_0 = io_req_uop_lrs2_rtype; // @[mshrs.scala:36:7]
wire io_req_uop_frs3_en_0 = io_req_uop_frs3_en; // @[mshrs.scala:36:7]
wire io_req_uop_fp_val_0 = io_req_uop_fp_val; // @[mshrs.scala:36:7]
wire io_req_uop_fp_single_0 = io_req_uop_fp_single; // @[mshrs.scala:36:7]
wire io_req_uop_xcpt_pf_if_0 = io_req_uop_xcpt_pf_if; // @[mshrs.scala:36:7]
wire io_req_uop_xcpt_ae_if_0 = io_req_uop_xcpt_ae_if; // @[mshrs.scala:36:7]
wire io_req_uop_xcpt_ma_if_0 = io_req_uop_xcpt_ma_if; // @[mshrs.scala:36:7]
wire io_req_uop_bp_debug_if_0 = io_req_uop_bp_debug_if; // @[mshrs.scala:36:7]
wire io_req_uop_bp_xcpt_if_0 = io_req_uop_bp_xcpt_if; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_debug_fsrc_0 = io_req_uop_debug_fsrc; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_debug_tsrc_0 = io_req_uop_debug_tsrc; // @[mshrs.scala:36:7]
wire [39:0] io_req_addr_0 = io_req_addr; // @[mshrs.scala:36:7]
wire [63:0] io_req_data_0 = io_req_data; // @[mshrs.scala:36:7]
wire io_req_is_hella_0 = io_req_is_hella; // @[mshrs.scala:36:7]
wire io_req_tag_match_0 = io_req_tag_match; // @[mshrs.scala:36:7]
wire [1:0] io_req_old_meta_coh_state_0 = io_req_old_meta_coh_state; // @[mshrs.scala:36:7]
wire [19:0] io_req_old_meta_tag_0 = io_req_old_meta_tag; // @[mshrs.scala:36:7]
wire [3:0] io_req_way_en_0 = io_req_way_en; // @[mshrs.scala:36:7]
wire [4:0] io_req_sdq_id_0 = io_req_sdq_id; // @[mshrs.scala:36:7]
wire io_req_is_probe_0 = io_req_is_probe; // @[mshrs.scala:36:7]
wire io_mem_acquire_ready_0 = io_mem_acquire_ready; // @[mshrs.scala:36:7]
wire io_mem_grant_valid_0 = io_mem_grant_valid; // @[mshrs.scala:36:7]
wire [2:0] io_mem_grant_bits_opcode_0 = io_mem_grant_bits_opcode; // @[mshrs.scala:36:7]
wire [1:0] io_mem_grant_bits_param_0 = io_mem_grant_bits_param; // @[mshrs.scala:36:7]
wire [3:0] io_mem_grant_bits_size_0 = io_mem_grant_bits_size; // @[mshrs.scala:36:7]
wire [1:0] io_mem_grant_bits_source_0 = io_mem_grant_bits_source; // @[mshrs.scala:36:7]
wire [2:0] io_mem_grant_bits_sink_0 = io_mem_grant_bits_sink; // @[mshrs.scala:36:7]
wire io_mem_grant_bits_denied_0 = io_mem_grant_bits_denied; // @[mshrs.scala:36:7]
wire [63:0] io_mem_grant_bits_data_0 = io_mem_grant_bits_data; // @[mshrs.scala:36:7]
wire io_mem_grant_bits_corrupt_0 = io_mem_grant_bits_corrupt; // @[mshrs.scala:36:7]
wire io_mem_finish_ready_0 = io_mem_finish_ready; // @[mshrs.scala:36:7]
wire io_prober_state_valid_0 = io_prober_state_valid; // @[mshrs.scala:36:7]
wire [39:0] io_prober_state_bits_0 = io_prober_state_bits; // @[mshrs.scala:36:7]
wire io_refill_ready_0 = io_refill_ready; // @[mshrs.scala:36:7]
wire io_meta_write_ready_0 = io_meta_write_ready; // @[mshrs.scala:36:7]
wire io_meta_read_ready_0 = io_meta_read_ready; // @[mshrs.scala:36:7]
wire io_meta_resp_valid_0 = io_meta_resp_valid; // @[mshrs.scala:36:7]
wire [1:0] io_meta_resp_bits_coh_state_0 = io_meta_resp_bits_coh_state; // @[mshrs.scala:36:7]
wire [19:0] io_meta_resp_bits_tag_0 = io_meta_resp_bits_tag; // @[mshrs.scala:36:7]
wire io_wb_req_ready_0 = io_wb_req_ready; // @[mshrs.scala:36:7]
wire io_lb_read_ready_0 = io_lb_read_ready; // @[mshrs.scala:36:7]
wire [63:0] io_lb_resp_0 = io_lb_resp; // @[mshrs.scala:36:7]
wire io_lb_write_ready_0 = io_lb_write_ready; // @[mshrs.scala:36:7]
wire io_replay_ready_0 = io_replay_ready; // @[mshrs.scala:36:7]
wire io_resp_ready_0 = io_resp_ready; // @[mshrs.scala:36:7]
wire io_wb_resp_0 = io_wb_resp; // @[mshrs.scala:36:7]
wire _state_T = reset; // @[mshrs.scala:194:11]
wire _state_T_26 = reset; // @[mshrs.scala:201:15]
wire _state_T_34 = reset; // @[mshrs.scala:194:11]
wire _state_T_60 = reset; // @[mshrs.scala:201:15]
wire io_id = 1'h1; // @[mshrs.scala:36:7]
wire io_refill_bits_wmask = 1'h1; // @[mshrs.scala:36:7]
wire io_wb_req_bits_voluntary = 1'h1; // @[mshrs.scala:36:7]
wire io_lb_read_bits_id = 1'h1; // @[mshrs.scala:36:7]
wire io_lb_write_bits_id = 1'h1; // @[mshrs.scala:36:7]
wire _r_T = 1'h1; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24]
wire _io_mem_acquire_bits_legal_T_19 = 1'h1; // @[Parameters.scala:91:44]
wire _io_mem_acquire_bits_legal_T_20 = 1'h1; // @[Parameters.scala:684:29]
wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21]
wire io_mem_acquire_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26]
wire io_mem_acquire_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26]
wire io_mem_acquire_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29]
wire _needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24]
wire _io_refill_bits_wmask_T = 1'h1; // @[mshrs.scala:342:30]
wire _state_req_needs_wb_r_T_64 = 1'h1; // @[Metadata.scala:140:24]
wire [2:0] io_mem_acquire_bits_opcode = 3'h6; // @[mshrs.scala:36:7]
wire [2:0] io_mem_acquire_bits_a_opcode = 3'h6; // @[Edges.scala:346:17]
wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T = 3'h6; // @[Misc.scala:202:34]
wire [3:0] io_mem_acquire_bits_size = 4'h6; // @[mshrs.scala:36:7]
wire [3:0] _r_T_12 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _grow_param_r_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _r1_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _r2_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _state_req_needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _state_r_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] io_mem_acquire_bits_a_size = 4'h6; // @[Edges.scala:346:17]
wire [3:0] _needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _r_T_74 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _r_T_133 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _state_req_needs_wb_r_T_76 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _state_r_T_69 = 4'h6; // @[Metadata.scala:64:10]
wire [1:0] io_mem_acquire_bits_source = 2'h1; // @[mshrs.scala:36:7]
wire [1:0] io_wb_req_bits_source = 2'h1; // @[mshrs.scala:36:7]
wire [1:0] _grow_param_r_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _grow_param_r_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _grow_param_r_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _grow_param_r_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _coh_on_grant_T_5 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] io_mem_acquire_bits_a_source = 2'h1; // @[Edges.scala:346:17]
wire [1:0] _r_T_71 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_73 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_81 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_83 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_130 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_132 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_140 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_142 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_66 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_68 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_76 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_78 = 2'h1; // @[Metadata.scala:25:15]
wire [7:0] io_mem_acquire_bits_mask = 8'hFF; // @[mshrs.scala:36:7]
wire [7:0] io_mem_acquire_bits_a_mask = 8'hFF; // @[Edges.scala:346:17]
wire [7:0] _io_mem_acquire_bits_a_mask_T = 8'hFF; // @[Misc.scala:222:10]
wire [63:0] io_mem_acquire_bits_data = 64'h0; // @[mshrs.scala:36:7]
wire [63:0] io_mem_acquire_bits_a_data = 64'h0; // @[Edges.scala:346:17]
wire io_mem_acquire_bits_corrupt = 1'h0; // @[mshrs.scala:36:7]
wire _r_T_2 = 1'h0; // @[Metadata.scala:140:24]
wire _r_T_4 = 1'h0; // @[Metadata.scala:140:24]
wire _r_T_20 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_24 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_28 = 1'h0; // @[Misc.scala:38:9]
wire _grow_param_r_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _state_req_needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9]
wire _state_r_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _io_mem_acquire_bits_legal_T = 1'h0; // @[Parameters.scala:684:29]
wire _io_mem_acquire_bits_legal_T_18 = 1'h0; // @[Parameters.scala:684:54]
wire _io_mem_acquire_bits_legal_T_33 = 1'h0; // @[Parameters.scala:686:26]
wire io_mem_acquire_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17]
wire io_mem_acquire_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _io_mem_acquire_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire io_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31]
wire io_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31]
wire io_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31]
wire _needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24]
wire _needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24]
wire _needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9]
wire _needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9]
wire _needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_90 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_93 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_96 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_99 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_102 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_149 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_152 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_155 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_158 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_161 = 1'h0; // @[Misc.scala:35:9]
wire _state_req_needs_wb_r_T_66 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_68 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_84 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_88 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_92 = 1'h0; // @[Misc.scala:38:9]
wire _state_r_T_85 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_88 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_91 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_94 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_97 = 1'h0; // @[Misc.scala:35:9]
wire [19:0] io_meta_write_bits_tag = 20'h0; // @[mshrs.scala:36:7]
wire [1:0] new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _r_T_22 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_26 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_30 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_34 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_38 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _grow_param_r_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _grow_param_r_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _grow_param_r_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _grow_param_r_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _coh_on_grant_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _coh_on_grant_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_req_needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_r_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] state_new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_65 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_67 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_69 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_79 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_124 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_126 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_128 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_138 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _state_req_needs_wb_r_T_86 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_90 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_94 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_98 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_102 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_r_T_60 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_62 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_64 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_74 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] state_new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20]
wire [3:0] _grow_param_r_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _coh_on_grant_T_8 = 4'hC; // @[Metadata.scala:89:10]
wire [3:0] _r1_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _r2_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _state_r_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _r_T_88 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _r_T_147 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _state_r_T_83 = 4'hC; // @[Metadata.scala:72:10]
wire [1:0] _grow_param_r_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _grow_param_r_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _grow_param_r_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _grow_param_r_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _coh_on_grant_T_7 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _dirties_T = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] io_mem_acquire_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_hi_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_hi_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] _r_T_75 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_77 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_85 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_87 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_134 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_136 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_144 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_146 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_70 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_72 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_80 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_82 = 2'h3; // @[Metadata.scala:24:15]
wire [3:0] _grow_param_r_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r1_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r2_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _state_r_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r_T_86 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r_T_145 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _state_r_T_81 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r_T_14 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _grow_param_r_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _coh_on_grant_T_6 = 4'h4; // @[Metadata.scala:88:10]
wire [3:0] _r1_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _r2_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _state_req_needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _state_r_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12]
wire [3:0] _needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _r_T_84 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _r_T_143 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _state_req_needs_wb_r_T_78 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _state_r_T_79 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _r_T_13 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _grow_param_r_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r1_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r2_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _state_req_needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _state_r_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _r_T_82 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r_T_141 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _state_req_needs_wb_r_T_77 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _state_r_T_77 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r_T_10 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _grow_param_r_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _coh_on_grant_T_4 = 4'h0; // @[Metadata.scala:87:10]
wire [3:0] _r1_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _r2_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _state_req_needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _state_r_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _r_T_80 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _r_T_139 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _state_req_needs_wb_r_T_74 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _state_r_T_75 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _grow_param_r_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r1_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r2_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _state_r_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r_T_78 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r_T_137 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _state_r_T_73 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _grow_param_r_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r1_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r2_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _state_r_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] io_mem_acquire_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10]
wire [3:0] io_mem_acquire_bits_a_mask_hi = 4'hF; // @[Misc.scala:222:10]
wire [3:0] _r_T_76 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r_T_135 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _state_r_T_71 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r_T_11 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _grow_param_r_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r1_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r2_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _state_req_needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _state_r_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _r_T_72 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r_T_131 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _state_req_needs_wb_r_T_75 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _state_r_T_67 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r_T_9 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _grow_param_r_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _coh_on_grant_T_2 = 4'h1; // @[Metadata.scala:86:10]
wire [3:0] _r1_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _r2_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _state_req_needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _state_r_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _r_T_70 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _r_T_129 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _state_req_needs_wb_r_T_73 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _state_r_T_65 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _r_T_8 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _grow_param_r_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r1_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r2_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _state_req_needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _state_r_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _r_T_68 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r_T_127 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _state_req_needs_wb_r_T_72 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _state_r_T_63 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r_T_7 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _grow_param_r_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r1_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r2_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _state_req_needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _state_r_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _r_T_66 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r_T_125 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _state_req_needs_wb_r_T_71 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _state_r_T_61 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r_T_18 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _state_req_needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _state_req_needs_wb_r_T_82 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _r_T_17 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _state_req_needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _state_req_needs_wb_r_T_81 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _r_T_16 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _state_req_needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _state_req_needs_wb_r_T_80 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _r_T_15 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _state_req_needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _state_req_needs_wb_r_T_79 = 4'hB; // @[Metadata.scala:130:10]
wire [1:0] _r_T_1 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _r_T_3 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _r_T_5 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49]
wire [1:0] _needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_65 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_67 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_69 = 2'h2; // @[Metadata.scala:140:24]
wire [6:0] _data_word_T = 7'h0; // @[mshrs.scala:264:32]
wire [2:0] io_mem_acquire_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81]
wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27]
wire _io_req_sec_rdy_T; // @[mshrs.scala:159:37]
wire _io_idx_valid_T; // @[mshrs.scala:149:25]
wire [5:0] req_idx; // @[mshrs.scala:110:25]
wire _io_way_valid_T_3; // @[mshrs.scala:151:19]
wire _io_tag_valid_T; // @[mshrs.scala:150:25]
wire [27:0] req_tag; // @[mshrs.scala:111:26]
wire [2:0] io_mem_acquire_bits_a_param; // @[Edges.scala:346:17]
wire [31:0] io_mem_acquire_bits_a_address; // @[Edges.scala:346:17]
wire [2:0] grantack_bits_e_sink = io_mem_grant_bits_sink_0; // @[Edges.scala:451:17]
wire [63:0] io_lb_write_bits_data_0 = io_mem_grant_bits_data_0; // @[mshrs.scala:36:7]
wire [2:0] shrink_param; // @[Misc.scala:38:36]
wire [1:0] coh_on_grant_state; // @[Metadata.scala:160:20]
wire [63:0] io_refill_bits_data_0 = io_lb_resp_0; // @[mshrs.scala:36:7]
wire [63:0] data_word = io_lb_resp_0; // @[mshrs.scala:36:7, :264:26]
wire [39:0] _io_replay_bits_addr_T_1; // @[mshrs.scala:353:31]
wire [63:0] _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16]
wire _io_probe_rdy_T_11; // @[mshrs.scala:148:42]
wire io_idx_valid_0; // @[mshrs.scala:36:7]
wire [5:0] io_idx_bits_0; // @[mshrs.scala:36:7]
wire io_way_valid_0; // @[mshrs.scala:36:7]
wire [3:0] io_way_bits_0; // @[mshrs.scala:36:7]
wire io_tag_valid_0; // @[mshrs.scala:36:7]
wire [27:0] io_tag_bits_0; // @[mshrs.scala:36:7]
wire [2:0] io_mem_acquire_bits_param_0; // @[mshrs.scala:36:7]
wire [31:0] io_mem_acquire_bits_address_0; // @[mshrs.scala:36:7]
wire io_mem_acquire_valid_0; // @[mshrs.scala:36:7]
wire io_mem_grant_ready_0; // @[mshrs.scala:36:7]
wire [2:0] io_mem_finish_bits_sink_0; // @[mshrs.scala:36:7]
wire io_mem_finish_valid_0; // @[mshrs.scala:36:7]
wire [3:0] io_refill_bits_way_en_0; // @[mshrs.scala:36:7]
wire [11:0] io_refill_bits_addr_0; // @[mshrs.scala:36:7]
wire io_refill_valid_0; // @[mshrs.scala:36:7]
wire [1:0] io_meta_write_bits_data_coh_state_0; // @[mshrs.scala:36:7]
wire [19:0] io_meta_write_bits_data_tag_0; // @[mshrs.scala:36:7]
wire [5:0] io_meta_write_bits_idx_0; // @[mshrs.scala:36:7]
wire [3:0] io_meta_write_bits_way_en_0; // @[mshrs.scala:36:7]
wire io_meta_write_valid_0; // @[mshrs.scala:36:7]
wire [5:0] io_meta_read_bits_idx_0; // @[mshrs.scala:36:7]
wire [3:0] io_meta_read_bits_way_en_0; // @[mshrs.scala:36:7]
wire [19:0] io_meta_read_bits_tag_0; // @[mshrs.scala:36:7]
wire io_meta_read_valid_0; // @[mshrs.scala:36:7]
wire [19:0] io_wb_req_bits_tag_0; // @[mshrs.scala:36:7]
wire [5:0] io_wb_req_bits_idx_0; // @[mshrs.scala:36:7]
wire [2:0] io_wb_req_bits_param_0; // @[mshrs.scala:36:7]
wire [3:0] io_wb_req_bits_way_en_0; // @[mshrs.scala:36:7]
wire io_wb_req_valid_0; // @[mshrs.scala:36:7]
wire [1:0] io_commit_coh_state_0; // @[mshrs.scala:36:7]
wire [2:0] io_lb_read_bits_offset_0; // @[mshrs.scala:36:7]
wire io_lb_read_valid_0; // @[mshrs.scala:36:7]
wire [2:0] io_lb_write_bits_offset_0; // @[mshrs.scala:36:7]
wire io_lb_write_valid_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_ctrl_br_type_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ctrl_is_load_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ctrl_is_std_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_uopc_0; // @[mshrs.scala:36:7]
wire [31:0] io_replay_bits_uop_inst_0; // @[mshrs.scala:36:7]
wire [31:0] io_replay_bits_uop_debug_inst_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_rvc_0; // @[mshrs.scala:36:7]
wire [39:0] io_replay_bits_uop_debug_pc_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_iq_type_0; // @[mshrs.scala:36:7]
wire [9:0] io_replay_bits_uop_fu_code_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_iw_state_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_br_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_jalr_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_jal_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_sfb_0; // @[mshrs.scala:36:7]
wire [7:0] io_replay_bits_uop_br_mask_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_br_tag_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_edge_inst_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_pc_lob_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_taken_0; // @[mshrs.scala:36:7]
wire [19:0] io_replay_bits_uop_imm_packed_0; // @[mshrs.scala:36:7]
wire [11:0] io_replay_bits_uop_csr_addr_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_uop_rob_idx_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_stq_idx_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_pdst_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_prs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_prs2_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_prs3_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_ppred_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_exception_0; // @[mshrs.scala:36:7]
wire [63:0] io_replay_bits_uop_exc_cause_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_bypassable_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_mem_size_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_mem_signed_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_fence_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_fencei_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_amo_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_uses_stq_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_unique_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_ldst_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_lrs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_lrs2_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_lrs3_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ldst_val_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_frs3_en_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_val_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_single_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_old_meta_coh_state_0; // @[mshrs.scala:36:7]
wire [19:0] io_replay_bits_old_meta_tag_0; // @[mshrs.scala:36:7]
wire [39:0] io_replay_bits_addr_0; // @[mshrs.scala:36:7]
wire [63:0] io_replay_bits_data_0; // @[mshrs.scala:36:7]
wire io_replay_bits_is_hella_0; // @[mshrs.scala:36:7]
wire io_replay_bits_tag_match_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_way_en_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_sdq_id_0; // @[mshrs.scala:36:7]
wire io_replay_valid_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:36:7]
wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ctrl_is_load_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ctrl_is_std_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_uopc_0; // @[mshrs.scala:36:7]
wire [31:0] io_resp_bits_uop_inst_0; // @[mshrs.scala:36:7]
wire [31:0] io_resp_bits_uop_debug_inst_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_rvc_0; // @[mshrs.scala:36:7]
wire [39:0] io_resp_bits_uop_debug_pc_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_iq_type_0; // @[mshrs.scala:36:7]
wire [9:0] io_resp_bits_uop_fu_code_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_iw_state_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_br_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_jalr_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_jal_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_sfb_0; // @[mshrs.scala:36:7]
wire [7:0] io_resp_bits_uop_br_mask_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_br_tag_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_edge_inst_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_pc_lob_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_taken_0; // @[mshrs.scala:36:7]
wire [19:0] io_resp_bits_uop_imm_packed_0; // @[mshrs.scala:36:7]
wire [11:0] io_resp_bits_uop_csr_addr_0; // @[mshrs.scala:36:7]
wire [4:0] io_resp_bits_uop_rob_idx_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_stq_idx_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_pdst_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_prs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_prs2_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_prs3_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_ppred_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_exception_0; // @[mshrs.scala:36:7]
wire [63:0] io_resp_bits_uop_exc_cause_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_bypassable_0; // @[mshrs.scala:36:7]
wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_mem_size_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_mem_signed_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_fence_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_fencei_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_amo_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_uses_stq_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_unique_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_ldst_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_lrs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_lrs2_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_lrs3_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ldst_val_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_frs3_en_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_val_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_single_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7]
wire [63:0] io_resp_bits_data_0; // @[mshrs.scala:36:7]
wire io_resp_bits_is_hella_0; // @[mshrs.scala:36:7]
wire io_resp_valid_0; // @[mshrs.scala:36:7]
wire io_req_pri_rdy_0; // @[mshrs.scala:36:7]
wire io_req_sec_rdy_0; // @[mshrs.scala:36:7]
wire io_commit_val_0; // @[mshrs.scala:36:7]
wire [39:0] io_commit_addr_0; // @[mshrs.scala:36:7]
wire io_probe_rdy_0; // @[mshrs.scala:36:7]
reg [4:0] state; // @[mshrs.scala:107:22]
reg [6:0] req_uop_uopc; // @[mshrs.scala:109:20]
reg [31:0] req_uop_inst; // @[mshrs.scala:109:20]
reg [31:0] req_uop_debug_inst; // @[mshrs.scala:109:20]
reg req_uop_is_rvc; // @[mshrs.scala:109:20]
reg [39:0] req_uop_debug_pc; // @[mshrs.scala:109:20]
reg [2:0] req_uop_iq_type; // @[mshrs.scala:109:20]
reg [9:0] req_uop_fu_code; // @[mshrs.scala:109:20]
reg [3:0] req_uop_ctrl_br_type; // @[mshrs.scala:109:20]
reg [1:0] req_uop_ctrl_op1_sel; // @[mshrs.scala:109:20]
reg [2:0] req_uop_ctrl_op2_sel; // @[mshrs.scala:109:20]
reg [2:0] req_uop_ctrl_imm_sel; // @[mshrs.scala:109:20]
reg [4:0] req_uop_ctrl_op_fcn; // @[mshrs.scala:109:20]
reg req_uop_ctrl_fcn_dw; // @[mshrs.scala:109:20]
reg [2:0] req_uop_ctrl_csr_cmd; // @[mshrs.scala:109:20]
reg req_uop_ctrl_is_load; // @[mshrs.scala:109:20]
reg req_uop_ctrl_is_sta; // @[mshrs.scala:109:20]
reg req_uop_ctrl_is_std; // @[mshrs.scala:109:20]
reg [1:0] req_uop_iw_state; // @[mshrs.scala:109:20]
reg req_uop_iw_p1_poisoned; // @[mshrs.scala:109:20]
reg req_uop_iw_p2_poisoned; // @[mshrs.scala:109:20]
reg req_uop_is_br; // @[mshrs.scala:109:20]
reg req_uop_is_jalr; // @[mshrs.scala:109:20]
reg req_uop_is_jal; // @[mshrs.scala:109:20]
reg req_uop_is_sfb; // @[mshrs.scala:109:20]
reg [7:0] req_uop_br_mask; // @[mshrs.scala:109:20]
reg [2:0] req_uop_br_tag; // @[mshrs.scala:109:20]
reg [3:0] req_uop_ftq_idx; // @[mshrs.scala:109:20]
reg req_uop_edge_inst; // @[mshrs.scala:109:20]
reg [5:0] req_uop_pc_lob; // @[mshrs.scala:109:20]
reg req_uop_taken; // @[mshrs.scala:109:20]
reg [19:0] req_uop_imm_packed; // @[mshrs.scala:109:20]
reg [11:0] req_uop_csr_addr; // @[mshrs.scala:109:20]
reg [4:0] req_uop_rob_idx; // @[mshrs.scala:109:20]
reg [2:0] req_uop_ldq_idx; // @[mshrs.scala:109:20]
reg [2:0] req_uop_stq_idx; // @[mshrs.scala:109:20]
reg [1:0] req_uop_rxq_idx; // @[mshrs.scala:109:20]
reg [5:0] req_uop_pdst; // @[mshrs.scala:109:20]
reg [5:0] req_uop_prs1; // @[mshrs.scala:109:20]
reg [5:0] req_uop_prs2; // @[mshrs.scala:109:20]
reg [5:0] req_uop_prs3; // @[mshrs.scala:109:20]
reg [3:0] req_uop_ppred; // @[mshrs.scala:109:20]
reg req_uop_prs1_busy; // @[mshrs.scala:109:20]
reg req_uop_prs2_busy; // @[mshrs.scala:109:20]
reg req_uop_prs3_busy; // @[mshrs.scala:109:20]
reg req_uop_ppred_busy; // @[mshrs.scala:109:20]
reg [5:0] req_uop_stale_pdst; // @[mshrs.scala:109:20]
reg req_uop_exception; // @[mshrs.scala:109:20]
reg [63:0] req_uop_exc_cause; // @[mshrs.scala:109:20]
reg req_uop_bypassable; // @[mshrs.scala:109:20]
reg [4:0] req_uop_mem_cmd; // @[mshrs.scala:109:20]
reg [1:0] req_uop_mem_size; // @[mshrs.scala:109:20]
reg req_uop_mem_signed; // @[mshrs.scala:109:20]
reg req_uop_is_fence; // @[mshrs.scala:109:20]
reg req_uop_is_fencei; // @[mshrs.scala:109:20]
reg req_uop_is_amo; // @[mshrs.scala:109:20]
reg req_uop_uses_ldq; // @[mshrs.scala:109:20]
reg req_uop_uses_stq; // @[mshrs.scala:109:20]
reg req_uop_is_sys_pc2epc; // @[mshrs.scala:109:20]
reg req_uop_is_unique; // @[mshrs.scala:109:20]
reg req_uop_flush_on_commit; // @[mshrs.scala:109:20]
reg req_uop_ldst_is_rs1; // @[mshrs.scala:109:20]
reg [5:0] req_uop_ldst; // @[mshrs.scala:109:20]
reg [5:0] req_uop_lrs1; // @[mshrs.scala:109:20]
reg [5:0] req_uop_lrs2; // @[mshrs.scala:109:20]
reg [5:0] req_uop_lrs3; // @[mshrs.scala:109:20]
reg req_uop_ldst_val; // @[mshrs.scala:109:20]
reg [1:0] req_uop_dst_rtype; // @[mshrs.scala:109:20]
reg [1:0] req_uop_lrs1_rtype; // @[mshrs.scala:109:20]
reg [1:0] req_uop_lrs2_rtype; // @[mshrs.scala:109:20]
reg req_uop_frs3_en; // @[mshrs.scala:109:20]
reg req_uop_fp_val; // @[mshrs.scala:109:20]
reg req_uop_fp_single; // @[mshrs.scala:109:20]
reg req_uop_xcpt_pf_if; // @[mshrs.scala:109:20]
reg req_uop_xcpt_ae_if; // @[mshrs.scala:109:20]
reg req_uop_xcpt_ma_if; // @[mshrs.scala:109:20]
reg req_uop_bp_debug_if; // @[mshrs.scala:109:20]
reg req_uop_bp_xcpt_if; // @[mshrs.scala:109:20]
reg [1:0] req_uop_debug_fsrc; // @[mshrs.scala:109:20]
reg [1:0] req_uop_debug_tsrc; // @[mshrs.scala:109:20]
reg [39:0] req_addr; // @[mshrs.scala:109:20]
assign io_commit_addr_0 = req_addr; // @[mshrs.scala:36:7, :109:20]
reg [63:0] req_data; // @[mshrs.scala:109:20]
reg req_is_hella; // @[mshrs.scala:109:20]
reg req_tag_match; // @[mshrs.scala:109:20]
reg [1:0] req_old_meta_coh_state; // @[mshrs.scala:109:20]
reg [19:0] req_old_meta_tag; // @[mshrs.scala:109:20]
assign io_wb_req_bits_tag_0 = req_old_meta_tag; // @[mshrs.scala:36:7, :109:20]
reg [3:0] req_way_en; // @[mshrs.scala:109:20]
assign io_way_bits_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_refill_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_meta_write_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_meta_read_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_wb_req_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_replay_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
reg [4:0] req_sdq_id; // @[mshrs.scala:109:20]
assign req_idx = req_addr[11:6]; // @[mshrs.scala:109:20, :110:25]
assign io_idx_bits_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign io_meta_write_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign io_meta_read_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign io_wb_req_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign req_tag = req_addr[39:12]; // @[mshrs.scala:109:20, :111:26]
assign io_tag_bits_0 = req_tag; // @[mshrs.scala:36:7, :111:26]
wire [33:0] _req_block_addr_T = req_addr[39:6]; // @[mshrs.scala:109:20, :112:34]
wire [39:0] req_block_addr = {_req_block_addr_T, 6'h0}; // @[mshrs.scala:112:{34,51}]
reg req_needs_wb; // @[mshrs.scala:113:29]
reg [1:0] new_coh_state; // @[mshrs.scala:115:24]
wire [3:0] _r_T_6 = {2'h2, req_old_meta_coh_state}; // @[Metadata.scala:120:19]
wire _r_T_19 = _r_T_6 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _r_T_21 = _r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _r_T_23 = _r_T_6 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _r_T_25 = _r_T_23 ? 3'h2 : _r_T_21; // @[Misc.scala:38:36, :56:20]
wire _r_T_27 = _r_T_6 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _r_T_29 = _r_T_27 ? 3'h1 : _r_T_25; // @[Misc.scala:38:36, :56:20]
wire _r_T_31 = _r_T_6 == 4'hB; // @[Misc.scala:56:20]
wire _r_T_32 = _r_T_31; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_33 = _r_T_31 ? 3'h1 : _r_T_29; // @[Misc.scala:38:36, :56:20]
wire _r_T_35 = _r_T_6 == 4'h4; // @[Misc.scala:56:20]
wire _r_T_36 = ~_r_T_35 & _r_T_32; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_37 = _r_T_35 ? 3'h5 : _r_T_33; // @[Misc.scala:38:36, :56:20]
wire _r_T_39 = _r_T_6 == 4'h5; // @[Misc.scala:56:20]
wire _r_T_40 = ~_r_T_39 & _r_T_36; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_41 = _r_T_39 ? 3'h4 : _r_T_37; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_42 = {1'h0, _r_T_39}; // @[Misc.scala:38:63, :56:20]
wire _r_T_43 = _r_T_6 == 4'h6; // @[Misc.scala:56:20]
wire _r_T_44 = ~_r_T_43 & _r_T_40; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_45 = _r_T_43 ? 3'h0 : _r_T_41; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_46 = _r_T_43 ? 2'h1 : _r_T_42; // @[Misc.scala:38:63, :56:20]
wire _r_T_47 = _r_T_6 == 4'h7; // @[Misc.scala:56:20]
wire _r_T_48 = _r_T_47 | _r_T_44; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_49 = _r_T_47 ? 3'h0 : _r_T_45; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_50 = _r_T_47 ? 2'h1 : _r_T_46; // @[Misc.scala:38:63, :56:20]
wire _r_T_51 = _r_T_6 == 4'h0; // @[Misc.scala:56:20]
wire _r_T_52 = ~_r_T_51 & _r_T_48; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_53 = _r_T_51 ? 3'h5 : _r_T_49; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_54 = _r_T_51 ? 2'h0 : _r_T_50; // @[Misc.scala:38:63, :56:20]
wire _r_T_55 = _r_T_6 == 4'h1; // @[Misc.scala:56:20]
wire _r_T_56 = ~_r_T_55 & _r_T_52; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_57 = _r_T_55 ? 3'h4 : _r_T_53; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_58 = _r_T_55 ? 2'h1 : _r_T_54; // @[Misc.scala:38:63, :56:20]
wire _r_T_59 = _r_T_6 == 4'h2; // @[Misc.scala:56:20]
wire _r_T_60 = ~_r_T_59 & _r_T_56; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_61 = _r_T_59 ? 3'h3 : _r_T_57; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_62 = _r_T_59 ? 2'h2 : _r_T_58; // @[Misc.scala:38:63, :56:20]
wire _r_T_63 = _r_T_6 == 4'h3; // @[Misc.scala:56:20]
wire r_1 = _r_T_63 | _r_T_60; // @[Misc.scala:38:9, :56:20]
assign shrink_param = _r_T_63 ? 3'h3 : _r_T_61; // @[Misc.scala:38:36, :56:20]
assign io_wb_req_bits_param_0 = shrink_param; // @[Misc.scala:38:36]
wire [1:0] r_3 = _r_T_63 ? 2'h2 : _r_T_62; // @[Misc.scala:38:63, :56:20]
wire [1:0] coh_on_clear_state = r_3; // @[Misc.scala:38:63]
wire _GEN = req_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32]
wire _grow_param_r_c_cat_T; // @[Consts.scala:90:32]
assign _grow_param_r_c_cat_T = _GEN; // @[Consts.scala:90:32]
wire _grow_param_r_c_cat_T_23; // @[Consts.scala:90:32]
assign _grow_param_r_c_cat_T_23 = _GEN; // @[Consts.scala:90:32]
wire _coh_on_grant_c_cat_T; // @[Consts.scala:90:32]
assign _coh_on_grant_c_cat_T = _GEN; // @[Consts.scala:90:32]
wire _coh_on_grant_c_cat_T_23; // @[Consts.scala:90:32]
assign _coh_on_grant_c_cat_T_23 = _GEN; // @[Consts.scala:90:32]
wire _r1_c_cat_T; // @[Consts.scala:90:32]
assign _r1_c_cat_T = _GEN; // @[Consts.scala:90:32]
wire _r1_c_cat_T_23; // @[Consts.scala:90:32]
assign _r1_c_cat_T_23 = _GEN; // @[Consts.scala:90:32]
wire _needs_second_acq_T_27; // @[Consts.scala:90:32]
assign _needs_second_acq_T_27 = _GEN; // @[Consts.scala:90:32]
wire _GEN_0 = req_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49]
wire _grow_param_r_c_cat_T_1; // @[Consts.scala:90:49]
assign _grow_param_r_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49]
wire _grow_param_r_c_cat_T_24; // @[Consts.scala:90:49]
assign _grow_param_r_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49]
wire _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:49]
assign _coh_on_grant_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49]
wire _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:49]
assign _coh_on_grant_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49]
wire _r1_c_cat_T_1; // @[Consts.scala:90:49]
assign _r1_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49]
wire _r1_c_cat_T_24; // @[Consts.scala:90:49]
assign _r1_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49]
wire _needs_second_acq_T_28; // @[Consts.scala:90:49]
assign _needs_second_acq_T_28 = _GEN_0; // @[Consts.scala:90:49]
wire _grow_param_r_c_cat_T_2 = _grow_param_r_c_cat_T | _grow_param_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _GEN_1 = req_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66]
wire _grow_param_r_c_cat_T_3; // @[Consts.scala:90:66]
assign _grow_param_r_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66]
wire _grow_param_r_c_cat_T_26; // @[Consts.scala:90:66]
assign _grow_param_r_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66]
wire _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:66]
assign _coh_on_grant_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66]
wire _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:66]
assign _coh_on_grant_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66]
wire _r1_c_cat_T_3; // @[Consts.scala:90:66]
assign _r1_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66]
wire _r1_c_cat_T_26; // @[Consts.scala:90:66]
assign _r1_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66]
wire _needs_second_acq_T_30; // @[Consts.scala:90:66]
assign _needs_second_acq_T_30 = _GEN_1; // @[Consts.scala:90:66]
wire _grow_param_r_c_cat_T_4 = _grow_param_r_c_cat_T_2 | _grow_param_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _GEN_2 = req_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_5; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_5 = _GEN_2; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_28; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_28 = _GEN_2; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_5; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_5 = _GEN_2; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_28; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_28 = _GEN_2; // @[package.scala:16:47]
wire _r1_c_cat_T_5; // @[package.scala:16:47]
assign _r1_c_cat_T_5 = _GEN_2; // @[package.scala:16:47]
wire _r1_c_cat_T_28; // @[package.scala:16:47]
assign _r1_c_cat_T_28 = _GEN_2; // @[package.scala:16:47]
wire _needs_second_acq_T_32; // @[package.scala:16:47]
assign _needs_second_acq_T_32 = _GEN_2; // @[package.scala:16:47]
wire _GEN_3 = req_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_6; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_6 = _GEN_3; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_29; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_29 = _GEN_3; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_6; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_6 = _GEN_3; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_29; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_29 = _GEN_3; // @[package.scala:16:47]
wire _r1_c_cat_T_6; // @[package.scala:16:47]
assign _r1_c_cat_T_6 = _GEN_3; // @[package.scala:16:47]
wire _r1_c_cat_T_29; // @[package.scala:16:47]
assign _r1_c_cat_T_29 = _GEN_3; // @[package.scala:16:47]
wire _needs_second_acq_T_33; // @[package.scala:16:47]
assign _needs_second_acq_T_33 = _GEN_3; // @[package.scala:16:47]
wire _GEN_4 = req_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_7; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_7 = _GEN_4; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_30; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_30 = _GEN_4; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_7; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_7 = _GEN_4; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_30; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_30 = _GEN_4; // @[package.scala:16:47]
wire _r1_c_cat_T_7; // @[package.scala:16:47]
assign _r1_c_cat_T_7 = _GEN_4; // @[package.scala:16:47]
wire _r1_c_cat_T_30; // @[package.scala:16:47]
assign _r1_c_cat_T_30 = _GEN_4; // @[package.scala:16:47]
wire _needs_second_acq_T_34; // @[package.scala:16:47]
assign _needs_second_acq_T_34 = _GEN_4; // @[package.scala:16:47]
wire _GEN_5 = req_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_8; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_8 = _GEN_5; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_31; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_31 = _GEN_5; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_8; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_8 = _GEN_5; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_31; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_31 = _GEN_5; // @[package.scala:16:47]
wire _r1_c_cat_T_8; // @[package.scala:16:47]
assign _r1_c_cat_T_8 = _GEN_5; // @[package.scala:16:47]
wire _r1_c_cat_T_31; // @[package.scala:16:47]
assign _r1_c_cat_T_31 = _GEN_5; // @[package.scala:16:47]
wire _needs_second_acq_T_35; // @[package.scala:16:47]
assign _needs_second_acq_T_35 = _GEN_5; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_9 = _grow_param_r_c_cat_T_5 | _grow_param_r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_10 = _grow_param_r_c_cat_T_9 | _grow_param_r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_11 = _grow_param_r_c_cat_T_10 | _grow_param_r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _GEN_6 = req_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_12; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_12 = _GEN_6; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_35; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_35 = _GEN_6; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_12; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_12 = _GEN_6; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_35; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_35 = _GEN_6; // @[package.scala:16:47]
wire _r1_c_cat_T_12; // @[package.scala:16:47]
assign _r1_c_cat_T_12 = _GEN_6; // @[package.scala:16:47]
wire _r1_c_cat_T_35; // @[package.scala:16:47]
assign _r1_c_cat_T_35 = _GEN_6; // @[package.scala:16:47]
wire _needs_second_acq_T_39; // @[package.scala:16:47]
assign _needs_second_acq_T_39 = _GEN_6; // @[package.scala:16:47]
wire _GEN_7 = req_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_13; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_13 = _GEN_7; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_36; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_36 = _GEN_7; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_13; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_13 = _GEN_7; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_36; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_36 = _GEN_7; // @[package.scala:16:47]
wire _r1_c_cat_T_13; // @[package.scala:16:47]
assign _r1_c_cat_T_13 = _GEN_7; // @[package.scala:16:47]
wire _r1_c_cat_T_36; // @[package.scala:16:47]
assign _r1_c_cat_T_36 = _GEN_7; // @[package.scala:16:47]
wire _needs_second_acq_T_40; // @[package.scala:16:47]
assign _needs_second_acq_T_40 = _GEN_7; // @[package.scala:16:47]
wire _GEN_8 = req_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_14; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_14 = _GEN_8; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_37; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_37 = _GEN_8; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_14; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_14 = _GEN_8; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_37; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_37 = _GEN_8; // @[package.scala:16:47]
wire _r1_c_cat_T_14; // @[package.scala:16:47]
assign _r1_c_cat_T_14 = _GEN_8; // @[package.scala:16:47]
wire _r1_c_cat_T_37; // @[package.scala:16:47]
assign _r1_c_cat_T_37 = _GEN_8; // @[package.scala:16:47]
wire _needs_second_acq_T_41; // @[package.scala:16:47]
assign _needs_second_acq_T_41 = _GEN_8; // @[package.scala:16:47]
wire _GEN_9 = req_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_15; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_15 = _GEN_9; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_38; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_38 = _GEN_9; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_15; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_15 = _GEN_9; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_38; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_38 = _GEN_9; // @[package.scala:16:47]
wire _r1_c_cat_T_15; // @[package.scala:16:47]
assign _r1_c_cat_T_15 = _GEN_9; // @[package.scala:16:47]
wire _r1_c_cat_T_38; // @[package.scala:16:47]
assign _r1_c_cat_T_38 = _GEN_9; // @[package.scala:16:47]
wire _needs_second_acq_T_42; // @[package.scala:16:47]
assign _needs_second_acq_T_42 = _GEN_9; // @[package.scala:16:47]
wire _GEN_10 = req_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_16; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_16 = _GEN_10; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_39; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_39 = _GEN_10; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_16; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_16 = _GEN_10; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_39; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_39 = _GEN_10; // @[package.scala:16:47]
wire _r1_c_cat_T_16; // @[package.scala:16:47]
assign _r1_c_cat_T_16 = _GEN_10; // @[package.scala:16:47]
wire _r1_c_cat_T_39; // @[package.scala:16:47]
assign _r1_c_cat_T_39 = _GEN_10; // @[package.scala:16:47]
wire _needs_second_acq_T_43; // @[package.scala:16:47]
assign _needs_second_acq_T_43 = _GEN_10; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_17 = _grow_param_r_c_cat_T_12 | _grow_param_r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_18 = _grow_param_r_c_cat_T_17 | _grow_param_r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_19 = _grow_param_r_c_cat_T_18 | _grow_param_r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_20 = _grow_param_r_c_cat_T_19 | _grow_param_r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_21 = _grow_param_r_c_cat_T_11 | _grow_param_r_c_cat_T_20; // @[package.scala:81:59]
wire _grow_param_r_c_cat_T_22 = _grow_param_r_c_cat_T_4 | _grow_param_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _grow_param_r_c_cat_T_25 = _grow_param_r_c_cat_T_23 | _grow_param_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _grow_param_r_c_cat_T_27 = _grow_param_r_c_cat_T_25 | _grow_param_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _grow_param_r_c_cat_T_32 = _grow_param_r_c_cat_T_28 | _grow_param_r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_33 = _grow_param_r_c_cat_T_32 | _grow_param_r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_34 = _grow_param_r_c_cat_T_33 | _grow_param_r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_40 = _grow_param_r_c_cat_T_35 | _grow_param_r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_41 = _grow_param_r_c_cat_T_40 | _grow_param_r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_42 = _grow_param_r_c_cat_T_41 | _grow_param_r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_43 = _grow_param_r_c_cat_T_42 | _grow_param_r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_44 = _grow_param_r_c_cat_T_34 | _grow_param_r_c_cat_T_43; // @[package.scala:81:59]
wire _grow_param_r_c_cat_T_45 = _grow_param_r_c_cat_T_27 | _grow_param_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _GEN_11 = req_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54]
wire _grow_param_r_c_cat_T_46; // @[Consts.scala:91:54]
assign _grow_param_r_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54]
wire _coh_on_grant_c_cat_T_46; // @[Consts.scala:91:54]
assign _coh_on_grant_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54]
wire _r1_c_cat_T_46; // @[Consts.scala:91:54]
assign _r1_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54]
wire _needs_second_acq_T_50; // @[Consts.scala:91:54]
assign _needs_second_acq_T_50 = _GEN_11; // @[Consts.scala:91:54]
wire _grow_param_r_c_cat_T_47 = _grow_param_r_c_cat_T_45 | _grow_param_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _GEN_12 = req_uop_mem_cmd == 5'h6; // @[Consts.scala:91:71]
wire _grow_param_r_c_cat_T_48; // @[Consts.scala:91:71]
assign _grow_param_r_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71]
wire _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:71]
assign _coh_on_grant_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71]
wire _r1_c_cat_T_48; // @[Consts.scala:91:71]
assign _r1_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71]
wire _needs_second_acq_T_52; // @[Consts.scala:91:71]
assign _needs_second_acq_T_52 = _GEN_12; // @[Consts.scala:91:71]
wire _grow_param_r_c_cat_T_49 = _grow_param_r_c_cat_T_47 | _grow_param_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] grow_param_r_c = {_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _grow_param_r_T = {grow_param_r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _grow_param_r_T_25 = _grow_param_r_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_27 = {1'h0, _grow_param_r_T_25}; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_28 = _grow_param_r_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_30 = _grow_param_r_T_28 ? 2'h2 : _grow_param_r_T_27; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_31 = _grow_param_r_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_33 = _grow_param_r_T_31 ? 2'h1 : _grow_param_r_T_30; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_34 = _grow_param_r_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_36 = _grow_param_r_T_34 ? 2'h2 : _grow_param_r_T_33; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_37 = _grow_param_r_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_39 = _grow_param_r_T_37 ? 2'h0 : _grow_param_r_T_36; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_40 = _grow_param_r_T == 4'hE; // @[Misc.scala:49:20]
wire _grow_param_r_T_41 = _grow_param_r_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_42 = _grow_param_r_T_40 ? 2'h3 : _grow_param_r_T_39; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_43 = &_grow_param_r_T; // @[Misc.scala:49:20]
wire _grow_param_r_T_44 = _grow_param_r_T_43 | _grow_param_r_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_45 = _grow_param_r_T_43 ? 2'h3 : _grow_param_r_T_42; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_46 = _grow_param_r_T == 4'h6; // @[Misc.scala:49:20]
wire _grow_param_r_T_47 = _grow_param_r_T_46 | _grow_param_r_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_48 = _grow_param_r_T_46 ? 2'h2 : _grow_param_r_T_45; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_49 = _grow_param_r_T == 4'h7; // @[Misc.scala:49:20]
wire _grow_param_r_T_50 = _grow_param_r_T_49 | _grow_param_r_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_51 = _grow_param_r_T_49 ? 2'h3 : _grow_param_r_T_48; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_52 = _grow_param_r_T == 4'h1; // @[Misc.scala:49:20]
wire _grow_param_r_T_53 = _grow_param_r_T_52 | _grow_param_r_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_54 = _grow_param_r_T_52 ? 2'h1 : _grow_param_r_T_51; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_55 = _grow_param_r_T == 4'h2; // @[Misc.scala:49:20]
wire _grow_param_r_T_56 = _grow_param_r_T_55 | _grow_param_r_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_57 = _grow_param_r_T_55 ? 2'h2 : _grow_param_r_T_54; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_58 = _grow_param_r_T == 4'h3; // @[Misc.scala:49:20]
wire grow_param_r_1 = _grow_param_r_T_58 | _grow_param_r_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] grow_param = _grow_param_r_T_58 ? 2'h3 : _grow_param_r_T_57; // @[Misc.scala:35:36, :49:20]
wire [1:0] grow_param_meta_state = grow_param; // @[Misc.scala:35:36]
wire _coh_on_grant_c_cat_T_2 = _coh_on_grant_c_cat_T | _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _coh_on_grant_c_cat_T_4 = _coh_on_grant_c_cat_T_2 | _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _coh_on_grant_c_cat_T_9 = _coh_on_grant_c_cat_T_5 | _coh_on_grant_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_10 = _coh_on_grant_c_cat_T_9 | _coh_on_grant_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_11 = _coh_on_grant_c_cat_T_10 | _coh_on_grant_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_17 = _coh_on_grant_c_cat_T_12 | _coh_on_grant_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_18 = _coh_on_grant_c_cat_T_17 | _coh_on_grant_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_19 = _coh_on_grant_c_cat_T_18 | _coh_on_grant_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_20 = _coh_on_grant_c_cat_T_19 | _coh_on_grant_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_21 = _coh_on_grant_c_cat_T_11 | _coh_on_grant_c_cat_T_20; // @[package.scala:81:59]
wire _coh_on_grant_c_cat_T_22 = _coh_on_grant_c_cat_T_4 | _coh_on_grant_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _coh_on_grant_c_cat_T_25 = _coh_on_grant_c_cat_T_23 | _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _coh_on_grant_c_cat_T_27 = _coh_on_grant_c_cat_T_25 | _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _coh_on_grant_c_cat_T_32 = _coh_on_grant_c_cat_T_28 | _coh_on_grant_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_33 = _coh_on_grant_c_cat_T_32 | _coh_on_grant_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_34 = _coh_on_grant_c_cat_T_33 | _coh_on_grant_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_40 = _coh_on_grant_c_cat_T_35 | _coh_on_grant_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_41 = _coh_on_grant_c_cat_T_40 | _coh_on_grant_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_42 = _coh_on_grant_c_cat_T_41 | _coh_on_grant_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_43 = _coh_on_grant_c_cat_T_42 | _coh_on_grant_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_44 = _coh_on_grant_c_cat_T_34 | _coh_on_grant_c_cat_T_43; // @[package.scala:81:59]
wire _coh_on_grant_c_cat_T_45 = _coh_on_grant_c_cat_T_27 | _coh_on_grant_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _coh_on_grant_c_cat_T_47 = _coh_on_grant_c_cat_T_45 | _coh_on_grant_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _coh_on_grant_c_cat_T_49 = _coh_on_grant_c_cat_T_47 | _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] coh_on_grant_c = {_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _coh_on_grant_T = {coh_on_grant_c, io_mem_grant_bits_param_0}; // @[Metadata.scala:29:18, :84:18]
wire _coh_on_grant_T_9 = _coh_on_grant_T == 4'h1; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_10 = {1'h0, _coh_on_grant_T_9}; // @[Metadata.scala:84:38]
wire _coh_on_grant_T_11 = _coh_on_grant_T == 4'h0; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_12 = _coh_on_grant_T_11 ? 2'h2 : _coh_on_grant_T_10; // @[Metadata.scala:84:38]
wire _coh_on_grant_T_13 = _coh_on_grant_T == 4'h4; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_14 = _coh_on_grant_T_13 ? 2'h2 : _coh_on_grant_T_12; // @[Metadata.scala:84:38]
wire _coh_on_grant_T_15 = _coh_on_grant_T == 4'hC; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_16 = _coh_on_grant_T_15 ? 2'h3 : _coh_on_grant_T_14; // @[Metadata.scala:84:38]
assign coh_on_grant_state = _coh_on_grant_T_16; // @[Metadata.scala:84:38, :160:20]
assign io_commit_coh_state_0 = coh_on_grant_state; // @[Metadata.scala:160:20]
wire _r1_c_cat_T_2 = _r1_c_cat_T | _r1_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _r1_c_cat_T_4 = _r1_c_cat_T_2 | _r1_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _r1_c_cat_T_9 = _r1_c_cat_T_5 | _r1_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_10 = _r1_c_cat_T_9 | _r1_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_11 = _r1_c_cat_T_10 | _r1_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_17 = _r1_c_cat_T_12 | _r1_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_18 = _r1_c_cat_T_17 | _r1_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_19 = _r1_c_cat_T_18 | _r1_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_20 = _r1_c_cat_T_19 | _r1_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_21 = _r1_c_cat_T_11 | _r1_c_cat_T_20; // @[package.scala:81:59]
wire _r1_c_cat_T_22 = _r1_c_cat_T_4 | _r1_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _r1_c_cat_T_25 = _r1_c_cat_T_23 | _r1_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _r1_c_cat_T_27 = _r1_c_cat_T_25 | _r1_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _r1_c_cat_T_32 = _r1_c_cat_T_28 | _r1_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_33 = _r1_c_cat_T_32 | _r1_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_34 = _r1_c_cat_T_33 | _r1_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_40 = _r1_c_cat_T_35 | _r1_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_41 = _r1_c_cat_T_40 | _r1_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_42 = _r1_c_cat_T_41 | _r1_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_43 = _r1_c_cat_T_42 | _r1_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_44 = _r1_c_cat_T_34 | _r1_c_cat_T_43; // @[package.scala:81:59]
wire _r1_c_cat_T_45 = _r1_c_cat_T_27 | _r1_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _r1_c_cat_T_47 = _r1_c_cat_T_45 | _r1_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _r1_c_cat_T_49 = _r1_c_cat_T_47 | _r1_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r1_c = {_r1_c_cat_T_22, _r1_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _r1_T = {r1_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r1_T_25 = _r1_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r1_T_27 = {1'h0, _r1_T_25}; // @[Misc.scala:35:36, :49:20]
wire _r1_T_28 = _r1_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r1_T_30 = _r1_T_28 ? 2'h2 : _r1_T_27; // @[Misc.scala:35:36, :49:20]
wire _r1_T_31 = _r1_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r1_T_33 = _r1_T_31 ? 2'h1 : _r1_T_30; // @[Misc.scala:35:36, :49:20]
wire _r1_T_34 = _r1_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r1_T_36 = _r1_T_34 ? 2'h2 : _r1_T_33; // @[Misc.scala:35:36, :49:20]
wire _r1_T_37 = _r1_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r1_T_39 = _r1_T_37 ? 2'h0 : _r1_T_36; // @[Misc.scala:35:36, :49:20]
wire _r1_T_40 = _r1_T == 4'hE; // @[Misc.scala:49:20]
wire _r1_T_41 = _r1_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_42 = _r1_T_40 ? 2'h3 : _r1_T_39; // @[Misc.scala:35:36, :49:20]
wire _r1_T_43 = &_r1_T; // @[Misc.scala:49:20]
wire _r1_T_44 = _r1_T_43 | _r1_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_45 = _r1_T_43 ? 2'h3 : _r1_T_42; // @[Misc.scala:35:36, :49:20]
wire _r1_T_46 = _r1_T == 4'h6; // @[Misc.scala:49:20]
wire _r1_T_47 = _r1_T_46 | _r1_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_48 = _r1_T_46 ? 2'h2 : _r1_T_45; // @[Misc.scala:35:36, :49:20]
wire _r1_T_49 = _r1_T == 4'h7; // @[Misc.scala:49:20]
wire _r1_T_50 = _r1_T_49 | _r1_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_51 = _r1_T_49 ? 2'h3 : _r1_T_48; // @[Misc.scala:35:36, :49:20]
wire _r1_T_52 = _r1_T == 4'h1; // @[Misc.scala:49:20]
wire _r1_T_53 = _r1_T_52 | _r1_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_54 = _r1_T_52 ? 2'h1 : _r1_T_51; // @[Misc.scala:35:36, :49:20]
wire _r1_T_55 = _r1_T == 4'h2; // @[Misc.scala:49:20]
wire _r1_T_56 = _r1_T_55 | _r1_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_57 = _r1_T_55 ? 2'h2 : _r1_T_54; // @[Misc.scala:35:36, :49:20]
wire _r1_T_58 = _r1_T == 4'h3; // @[Misc.scala:49:20]
wire r1_1 = _r1_T_58 | _r1_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] r1_2 = _r1_T_58 ? 2'h3 : _r1_T_57; // @[Misc.scala:35:36, :49:20]
wire _GEN_13 = io_req_uop_mem_cmd_0 == 5'h1; // @[Consts.scala:90:32]
wire _r2_c_cat_T; // @[Consts.scala:90:32]
assign _r2_c_cat_T = _GEN_13; // @[Consts.scala:90:32]
wire _r2_c_cat_T_23; // @[Consts.scala:90:32]
assign _r2_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32]
wire _needs_second_acq_T; // @[Consts.scala:90:32]
assign _needs_second_acq_T = _GEN_13; // @[Consts.scala:90:32]
wire _dirties_cat_T; // @[Consts.scala:90:32]
assign _dirties_cat_T = _GEN_13; // @[Consts.scala:90:32]
wire _dirties_cat_T_23; // @[Consts.scala:90:32]
assign _dirties_cat_T_23 = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T; // @[Consts.scala:90:32]
assign _state_r_c_cat_T = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T_23; // @[Consts.scala:90:32]
assign _state_r_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32]
wire _state_T_3; // @[Consts.scala:90:32]
assign _state_T_3 = _GEN_13; // @[Consts.scala:90:32]
wire _r_c_cat_T_50; // @[Consts.scala:90:32]
assign _r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32]
wire _r_c_cat_T_73; // @[Consts.scala:90:32]
assign _r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T_50; // @[Consts.scala:90:32]
assign _state_r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T_73; // @[Consts.scala:90:32]
assign _state_r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32]
wire _state_T_37; // @[Consts.scala:90:32]
assign _state_T_37 = _GEN_13; // @[Consts.scala:90:32]
wire _GEN_14 = io_req_uop_mem_cmd_0 == 5'h11; // @[Consts.scala:90:49]
wire _r2_c_cat_T_1; // @[Consts.scala:90:49]
assign _r2_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _r2_c_cat_T_24; // @[Consts.scala:90:49]
assign _r2_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49]
wire _needs_second_acq_T_1; // @[Consts.scala:90:49]
assign _needs_second_acq_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _dirties_cat_T_1; // @[Consts.scala:90:49]
assign _dirties_cat_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _dirties_cat_T_24; // @[Consts.scala:90:49]
assign _dirties_cat_T_24 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_1; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_24; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49]
wire _state_T_4; // @[Consts.scala:90:49]
assign _state_T_4 = _GEN_14; // @[Consts.scala:90:49]
wire _r_c_cat_T_51; // @[Consts.scala:90:49]
assign _r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49]
wire _r_c_cat_T_74; // @[Consts.scala:90:49]
assign _r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_51; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_74; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49]
wire _state_T_38; // @[Consts.scala:90:49]
assign _state_T_38 = _GEN_14; // @[Consts.scala:90:49]
wire _r2_c_cat_T_2 = _r2_c_cat_T | _r2_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _GEN_15 = io_req_uop_mem_cmd_0 == 5'h7; // @[Consts.scala:90:66]
wire _r2_c_cat_T_3; // @[Consts.scala:90:66]
assign _r2_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _r2_c_cat_T_26; // @[Consts.scala:90:66]
assign _r2_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66]
wire _needs_second_acq_T_3; // @[Consts.scala:90:66]
assign _needs_second_acq_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _dirties_cat_T_3; // @[Consts.scala:90:66]
assign _dirties_cat_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _dirties_cat_T_26; // @[Consts.scala:90:66]
assign _dirties_cat_T_26 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_3; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_26; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66]
wire _state_T_6; // @[Consts.scala:90:66]
assign _state_T_6 = _GEN_15; // @[Consts.scala:90:66]
wire _r_c_cat_T_53; // @[Consts.scala:90:66]
assign _r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66]
wire _r_c_cat_T_76; // @[Consts.scala:90:66]
assign _r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_53; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_76; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66]
wire _state_T_40; // @[Consts.scala:90:66]
assign _state_T_40 = _GEN_15; // @[Consts.scala:90:66]
wire _r2_c_cat_T_4 = _r2_c_cat_T_2 | _r2_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _GEN_16 = io_req_uop_mem_cmd_0 == 5'h4; // @[package.scala:16:47]
wire _r2_c_cat_T_5; // @[package.scala:16:47]
assign _r2_c_cat_T_5 = _GEN_16; // @[package.scala:16:47]
wire _r2_c_cat_T_28; // @[package.scala:16:47]
assign _r2_c_cat_T_28 = _GEN_16; // @[package.scala:16:47]
wire _needs_second_acq_T_5; // @[package.scala:16:47]
assign _needs_second_acq_T_5 = _GEN_16; // @[package.scala:16:47]
wire _dirties_cat_T_5; // @[package.scala:16:47]
assign _dirties_cat_T_5 = _GEN_16; // @[package.scala:16:47]
wire _dirties_cat_T_28; // @[package.scala:16:47]
assign _dirties_cat_T_28 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_5; // @[package.scala:16:47]
assign _state_r_c_cat_T_5 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_28; // @[package.scala:16:47]
assign _state_r_c_cat_T_28 = _GEN_16; // @[package.scala:16:47]
wire _state_T_8; // @[package.scala:16:47]
assign _state_T_8 = _GEN_16; // @[package.scala:16:47]
wire _r_c_cat_T_55; // @[package.scala:16:47]
assign _r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47]
wire _r_c_cat_T_78; // @[package.scala:16:47]
assign _r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_55; // @[package.scala:16:47]
assign _state_r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_78; // @[package.scala:16:47]
assign _state_r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47]
wire _state_T_42; // @[package.scala:16:47]
assign _state_T_42 = _GEN_16; // @[package.scala:16:47]
wire _GEN_17 = io_req_uop_mem_cmd_0 == 5'h9; // @[package.scala:16:47]
wire _r2_c_cat_T_6; // @[package.scala:16:47]
assign _r2_c_cat_T_6 = _GEN_17; // @[package.scala:16:47]
wire _r2_c_cat_T_29; // @[package.scala:16:47]
assign _r2_c_cat_T_29 = _GEN_17; // @[package.scala:16:47]
wire _needs_second_acq_T_6; // @[package.scala:16:47]
assign _needs_second_acq_T_6 = _GEN_17; // @[package.scala:16:47]
wire _dirties_cat_T_6; // @[package.scala:16:47]
assign _dirties_cat_T_6 = _GEN_17; // @[package.scala:16:47]
wire _dirties_cat_T_29; // @[package.scala:16:47]
assign _dirties_cat_T_29 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_6; // @[package.scala:16:47]
assign _state_r_c_cat_T_6 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_29; // @[package.scala:16:47]
assign _state_r_c_cat_T_29 = _GEN_17; // @[package.scala:16:47]
wire _state_T_9; // @[package.scala:16:47]
assign _state_T_9 = _GEN_17; // @[package.scala:16:47]
wire _r_c_cat_T_56; // @[package.scala:16:47]
assign _r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47]
wire _r_c_cat_T_79; // @[package.scala:16:47]
assign _r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_56; // @[package.scala:16:47]
assign _state_r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_79; // @[package.scala:16:47]
assign _state_r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47]
wire _state_T_43; // @[package.scala:16:47]
assign _state_T_43 = _GEN_17; // @[package.scala:16:47]
wire _GEN_18 = io_req_uop_mem_cmd_0 == 5'hA; // @[package.scala:16:47]
wire _r2_c_cat_T_7; // @[package.scala:16:47]
assign _r2_c_cat_T_7 = _GEN_18; // @[package.scala:16:47]
wire _r2_c_cat_T_30; // @[package.scala:16:47]
assign _r2_c_cat_T_30 = _GEN_18; // @[package.scala:16:47]
wire _needs_second_acq_T_7; // @[package.scala:16:47]
assign _needs_second_acq_T_7 = _GEN_18; // @[package.scala:16:47]
wire _dirties_cat_T_7; // @[package.scala:16:47]
assign _dirties_cat_T_7 = _GEN_18; // @[package.scala:16:47]
wire _dirties_cat_T_30; // @[package.scala:16:47]
assign _dirties_cat_T_30 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_7; // @[package.scala:16:47]
assign _state_r_c_cat_T_7 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_30; // @[package.scala:16:47]
assign _state_r_c_cat_T_30 = _GEN_18; // @[package.scala:16:47]
wire _state_T_10; // @[package.scala:16:47]
assign _state_T_10 = _GEN_18; // @[package.scala:16:47]
wire _r_c_cat_T_57; // @[package.scala:16:47]
assign _r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47]
wire _r_c_cat_T_80; // @[package.scala:16:47]
assign _r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_57; // @[package.scala:16:47]
assign _state_r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_80; // @[package.scala:16:47]
assign _state_r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47]
wire _state_T_44; // @[package.scala:16:47]
assign _state_T_44 = _GEN_18; // @[package.scala:16:47]
wire _GEN_19 = io_req_uop_mem_cmd_0 == 5'hB; // @[package.scala:16:47]
wire _r2_c_cat_T_8; // @[package.scala:16:47]
assign _r2_c_cat_T_8 = _GEN_19; // @[package.scala:16:47]
wire _r2_c_cat_T_31; // @[package.scala:16:47]
assign _r2_c_cat_T_31 = _GEN_19; // @[package.scala:16:47]
wire _needs_second_acq_T_8; // @[package.scala:16:47]
assign _needs_second_acq_T_8 = _GEN_19; // @[package.scala:16:47]
wire _dirties_cat_T_8; // @[package.scala:16:47]
assign _dirties_cat_T_8 = _GEN_19; // @[package.scala:16:47]
wire _dirties_cat_T_31; // @[package.scala:16:47]
assign _dirties_cat_T_31 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_8; // @[package.scala:16:47]
assign _state_r_c_cat_T_8 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_31; // @[package.scala:16:47]
assign _state_r_c_cat_T_31 = _GEN_19; // @[package.scala:16:47]
wire _state_T_11; // @[package.scala:16:47]
assign _state_T_11 = _GEN_19; // @[package.scala:16:47]
wire _r_c_cat_T_58; // @[package.scala:16:47]
assign _r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47]
wire _r_c_cat_T_81; // @[package.scala:16:47]
assign _r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_58; // @[package.scala:16:47]
assign _state_r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_81; // @[package.scala:16:47]
assign _state_r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47]
wire _state_T_45; // @[package.scala:16:47]
assign _state_T_45 = _GEN_19; // @[package.scala:16:47]
wire _r2_c_cat_T_9 = _r2_c_cat_T_5 | _r2_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_10 = _r2_c_cat_T_9 | _r2_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_11 = _r2_c_cat_T_10 | _r2_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _GEN_20 = io_req_uop_mem_cmd_0 == 5'h8; // @[package.scala:16:47]
wire _r2_c_cat_T_12; // @[package.scala:16:47]
assign _r2_c_cat_T_12 = _GEN_20; // @[package.scala:16:47]
wire _r2_c_cat_T_35; // @[package.scala:16:47]
assign _r2_c_cat_T_35 = _GEN_20; // @[package.scala:16:47]
wire _needs_second_acq_T_12; // @[package.scala:16:47]
assign _needs_second_acq_T_12 = _GEN_20; // @[package.scala:16:47]
wire _dirties_cat_T_12; // @[package.scala:16:47]
assign _dirties_cat_T_12 = _GEN_20; // @[package.scala:16:47]
wire _dirties_cat_T_35; // @[package.scala:16:47]
assign _dirties_cat_T_35 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_12; // @[package.scala:16:47]
assign _state_r_c_cat_T_12 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_35; // @[package.scala:16:47]
assign _state_r_c_cat_T_35 = _GEN_20; // @[package.scala:16:47]
wire _state_T_15; // @[package.scala:16:47]
assign _state_T_15 = _GEN_20; // @[package.scala:16:47]
wire _r_c_cat_T_62; // @[package.scala:16:47]
assign _r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47]
wire _r_c_cat_T_85; // @[package.scala:16:47]
assign _r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_62; // @[package.scala:16:47]
assign _state_r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_85; // @[package.scala:16:47]
assign _state_r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47]
wire _state_T_49; // @[package.scala:16:47]
assign _state_T_49 = _GEN_20; // @[package.scala:16:47]
wire _GEN_21 = io_req_uop_mem_cmd_0 == 5'hC; // @[package.scala:16:47]
wire _r2_c_cat_T_13; // @[package.scala:16:47]
assign _r2_c_cat_T_13 = _GEN_21; // @[package.scala:16:47]
wire _r2_c_cat_T_36; // @[package.scala:16:47]
assign _r2_c_cat_T_36 = _GEN_21; // @[package.scala:16:47]
wire _needs_second_acq_T_13; // @[package.scala:16:47]
assign _needs_second_acq_T_13 = _GEN_21; // @[package.scala:16:47]
wire _dirties_cat_T_13; // @[package.scala:16:47]
assign _dirties_cat_T_13 = _GEN_21; // @[package.scala:16:47]
wire _dirties_cat_T_36; // @[package.scala:16:47]
assign _dirties_cat_T_36 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_13; // @[package.scala:16:47]
assign _state_r_c_cat_T_13 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_36; // @[package.scala:16:47]
assign _state_r_c_cat_T_36 = _GEN_21; // @[package.scala:16:47]
wire _state_T_16; // @[package.scala:16:47]
assign _state_T_16 = _GEN_21; // @[package.scala:16:47]
wire _r_c_cat_T_63; // @[package.scala:16:47]
assign _r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47]
wire _r_c_cat_T_86; // @[package.scala:16:47]
assign _r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_63; // @[package.scala:16:47]
assign _state_r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_86; // @[package.scala:16:47]
assign _state_r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47]
wire _state_T_50; // @[package.scala:16:47]
assign _state_T_50 = _GEN_21; // @[package.scala:16:47]
wire _GEN_22 = io_req_uop_mem_cmd_0 == 5'hD; // @[package.scala:16:47]
wire _r2_c_cat_T_14; // @[package.scala:16:47]
assign _r2_c_cat_T_14 = _GEN_22; // @[package.scala:16:47]
wire _r2_c_cat_T_37; // @[package.scala:16:47]
assign _r2_c_cat_T_37 = _GEN_22; // @[package.scala:16:47]
wire _needs_second_acq_T_14; // @[package.scala:16:47]
assign _needs_second_acq_T_14 = _GEN_22; // @[package.scala:16:47]
wire _dirties_cat_T_14; // @[package.scala:16:47]
assign _dirties_cat_T_14 = _GEN_22; // @[package.scala:16:47]
wire _dirties_cat_T_37; // @[package.scala:16:47]
assign _dirties_cat_T_37 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_14; // @[package.scala:16:47]
assign _state_r_c_cat_T_14 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_37; // @[package.scala:16:47]
assign _state_r_c_cat_T_37 = _GEN_22; // @[package.scala:16:47]
wire _state_T_17; // @[package.scala:16:47]
assign _state_T_17 = _GEN_22; // @[package.scala:16:47]
wire _r_c_cat_T_64; // @[package.scala:16:47]
assign _r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47]
wire _r_c_cat_T_87; // @[package.scala:16:47]
assign _r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_64; // @[package.scala:16:47]
assign _state_r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_87; // @[package.scala:16:47]
assign _state_r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47]
wire _state_T_51; // @[package.scala:16:47]
assign _state_T_51 = _GEN_22; // @[package.scala:16:47]
wire _GEN_23 = io_req_uop_mem_cmd_0 == 5'hE; // @[package.scala:16:47]
wire _r2_c_cat_T_15; // @[package.scala:16:47]
assign _r2_c_cat_T_15 = _GEN_23; // @[package.scala:16:47]
wire _r2_c_cat_T_38; // @[package.scala:16:47]
assign _r2_c_cat_T_38 = _GEN_23; // @[package.scala:16:47]
wire _needs_second_acq_T_15; // @[package.scala:16:47]
assign _needs_second_acq_T_15 = _GEN_23; // @[package.scala:16:47]
wire _dirties_cat_T_15; // @[package.scala:16:47]
assign _dirties_cat_T_15 = _GEN_23; // @[package.scala:16:47]
wire _dirties_cat_T_38; // @[package.scala:16:47]
assign _dirties_cat_T_38 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_15; // @[package.scala:16:47]
assign _state_r_c_cat_T_15 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_38; // @[package.scala:16:47]
assign _state_r_c_cat_T_38 = _GEN_23; // @[package.scala:16:47]
wire _state_T_18; // @[package.scala:16:47]
assign _state_T_18 = _GEN_23; // @[package.scala:16:47]
wire _r_c_cat_T_65; // @[package.scala:16:47]
assign _r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47]
wire _r_c_cat_T_88; // @[package.scala:16:47]
assign _r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_65; // @[package.scala:16:47]
assign _state_r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_88; // @[package.scala:16:47]
assign _state_r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47]
wire _state_T_52; // @[package.scala:16:47]
assign _state_T_52 = _GEN_23; // @[package.scala:16:47]
wire _GEN_24 = io_req_uop_mem_cmd_0 == 5'hF; // @[package.scala:16:47]
wire _r2_c_cat_T_16; // @[package.scala:16:47]
assign _r2_c_cat_T_16 = _GEN_24; // @[package.scala:16:47]
wire _r2_c_cat_T_39; // @[package.scala:16:47]
assign _r2_c_cat_T_39 = _GEN_24; // @[package.scala:16:47]
wire _needs_second_acq_T_16; // @[package.scala:16:47]
assign _needs_second_acq_T_16 = _GEN_24; // @[package.scala:16:47]
wire _dirties_cat_T_16; // @[package.scala:16:47]
assign _dirties_cat_T_16 = _GEN_24; // @[package.scala:16:47]
wire _dirties_cat_T_39; // @[package.scala:16:47]
assign _dirties_cat_T_39 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_16; // @[package.scala:16:47]
assign _state_r_c_cat_T_16 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_39; // @[package.scala:16:47]
assign _state_r_c_cat_T_39 = _GEN_24; // @[package.scala:16:47]
wire _state_T_19; // @[package.scala:16:47]
assign _state_T_19 = _GEN_24; // @[package.scala:16:47]
wire _r_c_cat_T_66; // @[package.scala:16:47]
assign _r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47]
wire _r_c_cat_T_89; // @[package.scala:16:47]
assign _r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_66; // @[package.scala:16:47]
assign _state_r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_89; // @[package.scala:16:47]
assign _state_r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47]
wire _state_T_53; // @[package.scala:16:47]
assign _state_T_53 = _GEN_24; // @[package.scala:16:47]
wire _r2_c_cat_T_17 = _r2_c_cat_T_12 | _r2_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_18 = _r2_c_cat_T_17 | _r2_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_19 = _r2_c_cat_T_18 | _r2_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_20 = _r2_c_cat_T_19 | _r2_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_21 = _r2_c_cat_T_11 | _r2_c_cat_T_20; // @[package.scala:81:59]
wire _r2_c_cat_T_22 = _r2_c_cat_T_4 | _r2_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _r2_c_cat_T_25 = _r2_c_cat_T_23 | _r2_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _r2_c_cat_T_27 = _r2_c_cat_T_25 | _r2_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _r2_c_cat_T_32 = _r2_c_cat_T_28 | _r2_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_33 = _r2_c_cat_T_32 | _r2_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_34 = _r2_c_cat_T_33 | _r2_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_40 = _r2_c_cat_T_35 | _r2_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_41 = _r2_c_cat_T_40 | _r2_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_42 = _r2_c_cat_T_41 | _r2_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_43 = _r2_c_cat_T_42 | _r2_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_44 = _r2_c_cat_T_34 | _r2_c_cat_T_43; // @[package.scala:81:59]
wire _r2_c_cat_T_45 = _r2_c_cat_T_27 | _r2_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _GEN_25 = io_req_uop_mem_cmd_0 == 5'h3; // @[Consts.scala:91:54]
wire _r2_c_cat_T_46; // @[Consts.scala:91:54]
assign _r2_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54]
wire _needs_second_acq_T_23; // @[Consts.scala:91:54]
assign _needs_second_acq_T_23 = _GEN_25; // @[Consts.scala:91:54]
wire _dirties_cat_T_46; // @[Consts.scala:91:54]
assign _dirties_cat_T_46 = _GEN_25; // @[Consts.scala:91:54]
wire _rpq_io_enq_valid_T_4; // @[Consts.scala:88:52]
assign _rpq_io_enq_valid_T_4 = _GEN_25; // @[Consts.scala:88:52, :91:54]
wire _state_r_c_cat_T_46; // @[Consts.scala:91:54]
assign _state_r_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54]
wire _r_c_cat_T_96; // @[Consts.scala:91:54]
assign _r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54]
wire _state_r_c_cat_T_96; // @[Consts.scala:91:54]
assign _state_r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54]
wire _r2_c_cat_T_47 = _r2_c_cat_T_45 | _r2_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _GEN_26 = io_req_uop_mem_cmd_0 == 5'h6; // @[Consts.scala:91:71]
wire _r2_c_cat_T_48; // @[Consts.scala:91:71]
assign _r2_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71]
wire _needs_second_acq_T_25; // @[Consts.scala:91:71]
assign _needs_second_acq_T_25 = _GEN_26; // @[Consts.scala:91:71]
wire _dirties_cat_T_48; // @[Consts.scala:91:71]
assign _dirties_cat_T_48 = _GEN_26; // @[Consts.scala:91:71]
wire _state_r_c_cat_T_48; // @[Consts.scala:91:71]
assign _state_r_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71]
wire _r_c_cat_T_98; // @[Consts.scala:91:71]
assign _r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71]
wire _state_r_c_cat_T_98; // @[Consts.scala:91:71]
assign _state_r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71]
wire _r2_c_cat_T_49 = _r2_c_cat_T_47 | _r2_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r2_c = {_r2_c_cat_T_22, _r2_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _r2_T = {r2_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r2_T_25 = _r2_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r2_T_27 = {1'h0, _r2_T_25}; // @[Misc.scala:35:36, :49:20]
wire _r2_T_28 = _r2_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r2_T_30 = _r2_T_28 ? 2'h2 : _r2_T_27; // @[Misc.scala:35:36, :49:20]
wire _r2_T_31 = _r2_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r2_T_33 = _r2_T_31 ? 2'h1 : _r2_T_30; // @[Misc.scala:35:36, :49:20]
wire _r2_T_34 = _r2_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r2_T_36 = _r2_T_34 ? 2'h2 : _r2_T_33; // @[Misc.scala:35:36, :49:20]
wire _r2_T_37 = _r2_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r2_T_39 = _r2_T_37 ? 2'h0 : _r2_T_36; // @[Misc.scala:35:36, :49:20]
wire _r2_T_40 = _r2_T == 4'hE; // @[Misc.scala:49:20]
wire _r2_T_41 = _r2_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_42 = _r2_T_40 ? 2'h3 : _r2_T_39; // @[Misc.scala:35:36, :49:20]
wire _r2_T_43 = &_r2_T; // @[Misc.scala:49:20]
wire _r2_T_44 = _r2_T_43 | _r2_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_45 = _r2_T_43 ? 2'h3 : _r2_T_42; // @[Misc.scala:35:36, :49:20]
wire _r2_T_46 = _r2_T == 4'h6; // @[Misc.scala:49:20]
wire _r2_T_47 = _r2_T_46 | _r2_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_48 = _r2_T_46 ? 2'h2 : _r2_T_45; // @[Misc.scala:35:36, :49:20]
wire _r2_T_49 = _r2_T == 4'h7; // @[Misc.scala:49:20]
wire _r2_T_50 = _r2_T_49 | _r2_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_51 = _r2_T_49 ? 2'h3 : _r2_T_48; // @[Misc.scala:35:36, :49:20]
wire _r2_T_52 = _r2_T == 4'h1; // @[Misc.scala:49:20]
wire _r2_T_53 = _r2_T_52 | _r2_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_54 = _r2_T_52 ? 2'h1 : _r2_T_51; // @[Misc.scala:35:36, :49:20]
wire _r2_T_55 = _r2_T == 4'h2; // @[Misc.scala:49:20]
wire _r2_T_56 = _r2_T_55 | _r2_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_57 = _r2_T_55 ? 2'h2 : _r2_T_54; // @[Misc.scala:35:36, :49:20]
wire _r2_T_58 = _r2_T == 4'h3; // @[Misc.scala:49:20]
wire r2_1 = _r2_T_58 | _r2_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] r2_2 = _r2_T_58 ? 2'h3 : _r2_T_57; // @[Misc.scala:35:36, :49:20]
wire _needs_second_acq_T_2 = _needs_second_acq_T | _needs_second_acq_T_1; // @[Consts.scala:90:{32,42,49}]
wire _needs_second_acq_T_4 = _needs_second_acq_T_2 | _needs_second_acq_T_3; // @[Consts.scala:90:{42,59,66}]
wire _needs_second_acq_T_9 = _needs_second_acq_T_5 | _needs_second_acq_T_6; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_10 = _needs_second_acq_T_9 | _needs_second_acq_T_7; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_11 = _needs_second_acq_T_10 | _needs_second_acq_T_8; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_17 = _needs_second_acq_T_12 | _needs_second_acq_T_13; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_18 = _needs_second_acq_T_17 | _needs_second_acq_T_14; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_19 = _needs_second_acq_T_18 | _needs_second_acq_T_15; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_20 = _needs_second_acq_T_19 | _needs_second_acq_T_16; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_21 = _needs_second_acq_T_11 | _needs_second_acq_T_20; // @[package.scala:81:59]
wire _needs_second_acq_T_22 = _needs_second_acq_T_4 | _needs_second_acq_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _needs_second_acq_T_24 = _needs_second_acq_T_22 | _needs_second_acq_T_23; // @[Consts.scala:90:76, :91:{47,54}]
wire _needs_second_acq_T_26 = _needs_second_acq_T_24 | _needs_second_acq_T_25; // @[Consts.scala:91:{47,64,71}]
wire _needs_second_acq_T_29 = _needs_second_acq_T_27 | _needs_second_acq_T_28; // @[Consts.scala:90:{32,42,49}]
wire _needs_second_acq_T_31 = _needs_second_acq_T_29 | _needs_second_acq_T_30; // @[Consts.scala:90:{42,59,66}]
wire _needs_second_acq_T_36 = _needs_second_acq_T_32 | _needs_second_acq_T_33; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_37 = _needs_second_acq_T_36 | _needs_second_acq_T_34; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_38 = _needs_second_acq_T_37 | _needs_second_acq_T_35; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_44 = _needs_second_acq_T_39 | _needs_second_acq_T_40; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_45 = _needs_second_acq_T_44 | _needs_second_acq_T_41; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_46 = _needs_second_acq_T_45 | _needs_second_acq_T_42; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_47 = _needs_second_acq_T_46 | _needs_second_acq_T_43; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_48 = _needs_second_acq_T_38 | _needs_second_acq_T_47; // @[package.scala:81:59]
wire _needs_second_acq_T_49 = _needs_second_acq_T_31 | _needs_second_acq_T_48; // @[Consts.scala:87:44, :90:{59,76}]
wire _needs_second_acq_T_51 = _needs_second_acq_T_49 | _needs_second_acq_T_50; // @[Consts.scala:90:76, :91:{47,54}]
wire _needs_second_acq_T_53 = _needs_second_acq_T_51 | _needs_second_acq_T_52; // @[Consts.scala:91:{47,64,71}]
wire _needs_second_acq_T_54 = ~_needs_second_acq_T_53; // @[Metadata.scala:104:57]
wire cmd_requires_second_acquire = _needs_second_acq_T_26 & _needs_second_acq_T_54; // @[Metadata.scala:104:{54,57}]
wire is_hit_again = r1_1 & r2_1; // @[Misc.scala:35:9]
wire _dirties_cat_T_2 = _dirties_cat_T | _dirties_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _dirties_cat_T_4 = _dirties_cat_T_2 | _dirties_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _dirties_cat_T_9 = _dirties_cat_T_5 | _dirties_cat_T_6; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_10 = _dirties_cat_T_9 | _dirties_cat_T_7; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_11 = _dirties_cat_T_10 | _dirties_cat_T_8; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_17 = _dirties_cat_T_12 | _dirties_cat_T_13; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_18 = _dirties_cat_T_17 | _dirties_cat_T_14; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_19 = _dirties_cat_T_18 | _dirties_cat_T_15; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_20 = _dirties_cat_T_19 | _dirties_cat_T_16; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_21 = _dirties_cat_T_11 | _dirties_cat_T_20; // @[package.scala:81:59]
wire _dirties_cat_T_22 = _dirties_cat_T_4 | _dirties_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _dirties_cat_T_25 = _dirties_cat_T_23 | _dirties_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _dirties_cat_T_27 = _dirties_cat_T_25 | _dirties_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _dirties_cat_T_32 = _dirties_cat_T_28 | _dirties_cat_T_29; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_33 = _dirties_cat_T_32 | _dirties_cat_T_30; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_34 = _dirties_cat_T_33 | _dirties_cat_T_31; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_40 = _dirties_cat_T_35 | _dirties_cat_T_36; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_41 = _dirties_cat_T_40 | _dirties_cat_T_37; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_42 = _dirties_cat_T_41 | _dirties_cat_T_38; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_43 = _dirties_cat_T_42 | _dirties_cat_T_39; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_44 = _dirties_cat_T_34 | _dirties_cat_T_43; // @[package.scala:81:59]
wire _dirties_cat_T_45 = _dirties_cat_T_27 | _dirties_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _dirties_cat_T_47 = _dirties_cat_T_45 | _dirties_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _dirties_cat_T_49 = _dirties_cat_T_47 | _dirties_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] dirties_cat = {_dirties_cat_T_22, _dirties_cat_T_49}; // @[Metadata.scala:29:18]
wire dirties = &dirties_cat; // @[Metadata.scala:29:18, :106:42]
wire [1:0] biggest_grow_param = dirties ? r2_2 : r1_2; // @[Misc.scala:35:36]
wire [1:0] dirtier_coh_state = biggest_grow_param; // @[Metadata.scala:107:33, :160:20]
wire [4:0] dirtier_cmd = dirties ? io_req_uop_mem_cmd_0 : req_uop_mem_cmd; // @[Metadata.scala:106:42, :109:27]
wire _T_16 = io_mem_grant_ready_0 & io_mem_grant_valid_0; // @[Decoupled.scala:51:35]
wire [26:0] _r_beats1_decode_T = 27'hFFF << io_mem_grant_bits_size_0; // @[package.scala:243:71]
wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire r_beats1_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36]
wire opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36]
wire grant_had_data_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36]
wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] r_counter; // @[Edges.scala:229:27]
wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28]
wire r_1_1 = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire r_2 = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire refill_done = r_2 & _T_16; // @[Decoupled.scala:51:35]
wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _r_counter_T = r_1_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] refill_address_inc = {r_4, 3'h0}; // @[Edges.scala:234:25, :269:29]
wire _sec_rdy_T = ~cmd_requires_second_acquire; // @[Metadata.scala:104:54]
wire _sec_rdy_T_1 = ~io_req_is_probe_0; // @[mshrs.scala:36:7, :125:50]
wire _sec_rdy_T_2 = _sec_rdy_T & _sec_rdy_T_1; // @[mshrs.scala:125:{18,47,50}]
wire _sec_rdy_T_3 = ~(|state); // @[package.scala:16:47]
wire _sec_rdy_T_4 = state == 5'hD; // @[package.scala:16:47]
wire _sec_rdy_T_5 = state == 5'hE; // @[package.scala:16:47]
wire _sec_rdy_T_6 = state == 5'hF; // @[package.scala:16:47]
wire _sec_rdy_T_7 = _sec_rdy_T_3 | _sec_rdy_T_4; // @[package.scala:16:47, :81:59]
wire _sec_rdy_T_8 = _sec_rdy_T_7 | _sec_rdy_T_5; // @[package.scala:16:47, :81:59]
wire _sec_rdy_T_9 = _sec_rdy_T_8 | _sec_rdy_T_6; // @[package.scala:16:47, :81:59]
wire _sec_rdy_T_10 = ~_sec_rdy_T_9; // @[package.scala:81:59]
wire sec_rdy = _sec_rdy_T_2 & _sec_rdy_T_10; // @[mshrs.scala:125:{47,67}, :126:18]
wire _rpq_io_enq_valid_T = io_req_pri_val_0 & io_req_pri_rdy_0; // @[mshrs.scala:36:7, :133:40]
wire _rpq_io_enq_valid_T_1 = io_req_sec_val_0 & io_req_sec_rdy_0; // @[mshrs.scala:36:7, :133:78]
wire _rpq_io_enq_valid_T_2 = _rpq_io_enq_valid_T | _rpq_io_enq_valid_T_1; // @[mshrs.scala:133:{40,59,78}]
wire _rpq_io_enq_valid_T_3 = io_req_uop_mem_cmd_0 == 5'h2; // @[Consts.scala:88:35]
wire _rpq_io_enq_valid_T_5 = _rpq_io_enq_valid_T_3 | _rpq_io_enq_valid_T_4; // @[Consts.scala:88:{35,45,52}]
wire _rpq_io_enq_valid_T_6 = ~_rpq_io_enq_valid_T_5; // @[Consts.scala:88:45]
wire _rpq_io_enq_valid_T_7 = _rpq_io_enq_valid_T_2 & _rpq_io_enq_valid_T_6; // @[mshrs.scala:133:{59,98,101}]
reg grantack_valid; // @[mshrs.scala:138:21]
reg [2:0] grantack_bits_sink; // @[mshrs.scala:138:21]
assign io_mem_finish_bits_sink_0 = grantack_bits_sink; // @[mshrs.scala:36:7, :138:21]
reg [2:0] refill_ctr; // @[mshrs.scala:139:24]
reg commit_line; // @[mshrs.scala:140:24]
reg grant_had_data; // @[mshrs.scala:141:27]
reg finish_to_prefetch; // @[mshrs.scala:142:31]
reg [1:0] meta_hazard; // @[mshrs.scala:145:28]
wire [2:0] _meta_hazard_T = {1'h0, meta_hazard} + 3'h1; // @[mshrs.scala:145:28, :146:59]
wire [1:0] _meta_hazard_T_1 = _meta_hazard_T[1:0]; // @[mshrs.scala:146:59]
wire _io_probe_rdy_T = meta_hazard == 2'h0; // @[mshrs.scala:145:28, :148:34]
wire _io_probe_rdy_T_1 = ~(|state); // @[package.scala:16:47]
wire _io_probe_rdy_T_2 = state == 5'h1; // @[package.scala:16:47]
wire _io_probe_rdy_T_3 = state == 5'h2; // @[package.scala:16:47]
wire _io_probe_rdy_T_4 = state == 5'h3; // @[package.scala:16:47]
wire _io_probe_rdy_T_5 = _io_probe_rdy_T_1 | _io_probe_rdy_T_2; // @[package.scala:16:47, :81:59]
wire _io_probe_rdy_T_6 = _io_probe_rdy_T_5 | _io_probe_rdy_T_3; // @[package.scala:16:47, :81:59]
wire _io_probe_rdy_T_7 = _io_probe_rdy_T_6 | _io_probe_rdy_T_4; // @[package.scala:16:47, :81:59]
wire _io_probe_rdy_T_8 = state == 5'h4; // @[mshrs.scala:107:22, :148:129]
wire _io_probe_rdy_T_9 = _io_probe_rdy_T_8 & grantack_valid; // @[mshrs.scala:138:21, :148:{129,145}]
wire _io_probe_rdy_T_10 = _io_probe_rdy_T_7 | _io_probe_rdy_T_9; // @[package.scala:81:59]
assign _io_probe_rdy_T_11 = _io_probe_rdy_T & _io_probe_rdy_T_10; // @[mshrs.scala:148:{34,42,119}]
assign io_probe_rdy_0 = _io_probe_rdy_T_11; // @[mshrs.scala:36:7, :148:42]
assign _io_idx_valid_T = |state; // @[package.scala:16:47]
assign io_idx_valid_0 = _io_idx_valid_T; // @[mshrs.scala:36:7, :149:25]
assign _io_tag_valid_T = |state; // @[package.scala:16:47]
assign io_tag_valid_0 = _io_tag_valid_T; // @[mshrs.scala:36:7, :150:25]
wire _io_way_valid_T = ~(|state); // @[package.scala:16:47]
wire _io_way_valid_T_1 = state == 5'h11; // @[package.scala:16:47]
wire _io_way_valid_T_2 = _io_way_valid_T | _io_way_valid_T_1; // @[package.scala:16:47, :81:59]
assign _io_way_valid_T_3 = ~_io_way_valid_T_2; // @[package.scala:81:59]
assign io_way_valid_0 = _io_way_valid_T_3; // @[mshrs.scala:36:7, :151:19]
assign _io_req_sec_rdy_T = sec_rdy & _rpq_io_enq_ready; // @[mshrs.scala:125:67, :128:19, :159:37]
assign io_req_sec_rdy_0 = _io_req_sec_rdy_T; // @[mshrs.scala:36:7, :159:37]
wire [4:0] state_new_state; // @[mshrs.scala:191:29]
wire _state_T_1 = ~_state_T; // @[mshrs.scala:194:11]
wire _state_T_2 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :194:11]
wire [3:0] _GEN_27 = {2'h2, io_req_old_meta_coh_state_0}; // @[Metadata.scala:120:19]
wire [3:0] _state_req_needs_wb_r_T_6; // @[Metadata.scala:120:19]
assign _state_req_needs_wb_r_T_6 = _GEN_27; // @[Metadata.scala:120:19]
wire [3:0] _state_req_needs_wb_r_T_70; // @[Metadata.scala:120:19]
assign _state_req_needs_wb_r_T_70 = _GEN_27; // @[Metadata.scala:120:19]
wire _state_req_needs_wb_r_T_19 = _state_req_needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_21 = _state_req_needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_23 = _state_req_needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_25 = _state_req_needs_wb_r_T_23 ? 3'h2 : _state_req_needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_27 = _state_req_needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_29 = _state_req_needs_wb_r_T_27 ? 3'h1 : _state_req_needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_31 = _state_req_needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_32 = _state_req_needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_33 = _state_req_needs_wb_r_T_31 ? 3'h1 : _state_req_needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_35 = _state_req_needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_36 = ~_state_req_needs_wb_r_T_35 & _state_req_needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_37 = _state_req_needs_wb_r_T_35 ? 3'h5 : _state_req_needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_39 = _state_req_needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_40 = ~_state_req_needs_wb_r_T_39 & _state_req_needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_41 = _state_req_needs_wb_r_T_39 ? 3'h4 : _state_req_needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_42 = {1'h0, _state_req_needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_43 = _state_req_needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_44 = ~_state_req_needs_wb_r_T_43 & _state_req_needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_45 = _state_req_needs_wb_r_T_43 ? 3'h0 : _state_req_needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_46 = _state_req_needs_wb_r_T_43 ? 2'h1 : _state_req_needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_47 = _state_req_needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_48 = _state_req_needs_wb_r_T_47 | _state_req_needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_49 = _state_req_needs_wb_r_T_47 ? 3'h0 : _state_req_needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_50 = _state_req_needs_wb_r_T_47 ? 2'h1 : _state_req_needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_51 = _state_req_needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_52 = ~_state_req_needs_wb_r_T_51 & _state_req_needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_53 = _state_req_needs_wb_r_T_51 ? 3'h5 : _state_req_needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_54 = _state_req_needs_wb_r_T_51 ? 2'h0 : _state_req_needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_55 = _state_req_needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_56 = ~_state_req_needs_wb_r_T_55 & _state_req_needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_57 = _state_req_needs_wb_r_T_55 ? 3'h4 : _state_req_needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_58 = _state_req_needs_wb_r_T_55 ? 2'h1 : _state_req_needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_59 = _state_req_needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_60 = ~_state_req_needs_wb_r_T_59 & _state_req_needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_61 = _state_req_needs_wb_r_T_59 ? 3'h3 : _state_req_needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_62 = _state_req_needs_wb_r_T_59 ? 2'h2 : _state_req_needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_63 = _state_req_needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20]
wire state_req_needs_wb_r_1 = _state_req_needs_wb_r_T_63 | _state_req_needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20]
wire [2:0] state_req_needs_wb_r_2 = _state_req_needs_wb_r_T_63 ? 3'h3 : _state_req_needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20]
wire [1:0] state_req_needs_wb_r_3 = _state_req_needs_wb_r_T_63 ? 2'h2 : _state_req_needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20]
wire [1:0] state_req_needs_wb_meta_state = state_req_needs_wb_r_3; // @[Misc.scala:38:63]
wire _state_r_c_cat_T_2 = _state_r_c_cat_T | _state_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_4 = _state_r_c_cat_T_2 | _state_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_9 = _state_r_c_cat_T_5 | _state_r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_10 = _state_r_c_cat_T_9 | _state_r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_11 = _state_r_c_cat_T_10 | _state_r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_17 = _state_r_c_cat_T_12 | _state_r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_18 = _state_r_c_cat_T_17 | _state_r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_19 = _state_r_c_cat_T_18 | _state_r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_20 = _state_r_c_cat_T_19 | _state_r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_21 = _state_r_c_cat_T_11 | _state_r_c_cat_T_20; // @[package.scala:81:59]
wire _state_r_c_cat_T_22 = _state_r_c_cat_T_4 | _state_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_25 = _state_r_c_cat_T_23 | _state_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_27 = _state_r_c_cat_T_25 | _state_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_32 = _state_r_c_cat_T_28 | _state_r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_33 = _state_r_c_cat_T_32 | _state_r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_34 = _state_r_c_cat_T_33 | _state_r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_40 = _state_r_c_cat_T_35 | _state_r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_41 = _state_r_c_cat_T_40 | _state_r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_42 = _state_r_c_cat_T_41 | _state_r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_43 = _state_r_c_cat_T_42 | _state_r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_44 = _state_r_c_cat_T_34 | _state_r_c_cat_T_43; // @[package.scala:81:59]
wire _state_r_c_cat_T_45 = _state_r_c_cat_T_27 | _state_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_47 = _state_r_c_cat_T_45 | _state_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _state_r_c_cat_T_49 = _state_r_c_cat_T_47 | _state_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] state_r_c = {_state_r_c_cat_T_22, _state_r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _state_r_T = {state_r_c, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19]
wire _state_r_T_25 = _state_r_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_27 = {1'h0, _state_r_T_25}; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_28 = _state_r_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_30 = _state_r_T_28 ? 2'h2 : _state_r_T_27; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_31 = _state_r_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_33 = _state_r_T_31 ? 2'h1 : _state_r_T_30; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_34 = _state_r_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_36 = _state_r_T_34 ? 2'h2 : _state_r_T_33; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_37 = _state_r_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_39 = _state_r_T_37 ? 2'h0 : _state_r_T_36; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_40 = _state_r_T == 4'hE; // @[Misc.scala:49:20]
wire _state_r_T_41 = _state_r_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_42 = _state_r_T_40 ? 2'h3 : _state_r_T_39; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_43 = &_state_r_T; // @[Misc.scala:49:20]
wire _state_r_T_44 = _state_r_T_43 | _state_r_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_45 = _state_r_T_43 ? 2'h3 : _state_r_T_42; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_46 = _state_r_T == 4'h6; // @[Misc.scala:49:20]
wire _state_r_T_47 = _state_r_T_46 | _state_r_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_48 = _state_r_T_46 ? 2'h2 : _state_r_T_45; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_49 = _state_r_T == 4'h7; // @[Misc.scala:49:20]
wire _state_r_T_50 = _state_r_T_49 | _state_r_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_51 = _state_r_T_49 ? 2'h3 : _state_r_T_48; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_52 = _state_r_T == 4'h1; // @[Misc.scala:49:20]
wire _state_r_T_53 = _state_r_T_52 | _state_r_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_54 = _state_r_T_52 ? 2'h1 : _state_r_T_51; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_55 = _state_r_T == 4'h2; // @[Misc.scala:49:20]
wire _state_r_T_56 = _state_r_T_55 | _state_r_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_57 = _state_r_T_55 ? 2'h2 : _state_r_T_54; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_58 = _state_r_T == 4'h3; // @[Misc.scala:49:20]
wire state_is_hit = _state_r_T_58 | _state_r_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] state_r_2 = _state_r_T_58 ? 2'h3 : _state_r_T_57; // @[Misc.scala:35:36, :49:20]
wire [1:0] state_coh_on_hit_state = state_r_2; // @[Misc.scala:35:36]
wire _state_T_5 = _state_T_3 | _state_T_4; // @[Consts.scala:90:{32,42,49}]
wire _state_T_7 = _state_T_5 | _state_T_6; // @[Consts.scala:90:{42,59,66}]
wire _state_T_12 = _state_T_8 | _state_T_9; // @[package.scala:16:47, :81:59]
wire _state_T_13 = _state_T_12 | _state_T_10; // @[package.scala:16:47, :81:59]
wire _state_T_14 = _state_T_13 | _state_T_11; // @[package.scala:16:47, :81:59]
wire _state_T_20 = _state_T_15 | _state_T_16; // @[package.scala:16:47, :81:59]
wire _state_T_21 = _state_T_20 | _state_T_17; // @[package.scala:16:47, :81:59]
wire _state_T_22 = _state_T_21 | _state_T_18; // @[package.scala:16:47, :81:59]
wire _state_T_23 = _state_T_22 | _state_T_19; // @[package.scala:16:47, :81:59]
wire _state_T_24 = _state_T_14 | _state_T_23; // @[package.scala:81:59]
wire _state_T_25 = _state_T_7 | _state_T_24; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_T_27 = ~_state_T_26; // @[mshrs.scala:201:15]
wire _state_T_28 = ~_state_T_25; // @[Consts.scala:90:76]
assign state_new_state = io_req_tag_match_0 & state_is_hit ? 5'hC : 5'h1; // @[Misc.scala:35:9]
assign io_mem_acquire_valid_0 = (|state) & _io_probe_rdy_T_2; // @[package.scala:16:47]
wire [33:0] _GEN_28 = {req_tag, req_idx}; // @[mshrs.scala:110:25, :111:26, :227:28]
wire [33:0] _io_mem_acquire_bits_T; // @[mshrs.scala:227:28]
assign _io_mem_acquire_bits_T = _GEN_28; // @[mshrs.scala:227:28]
wire [33:0] rp_addr_hi; // @[mshrs.scala:261:22]
assign rp_addr_hi = _GEN_28; // @[mshrs.scala:227:28, :261:22]
wire [33:0] hi; // @[mshrs.scala:266:10]
assign hi = _GEN_28; // @[mshrs.scala:227:28, :266:10]
wire [33:0] io_replay_bits_addr_hi; // @[mshrs.scala:353:31]
assign io_replay_bits_addr_hi = _GEN_28; // @[mshrs.scala:227:28, :353:31]
wire [39:0] _io_mem_acquire_bits_T_1 = {_io_mem_acquire_bits_T, 6'h0}; // @[mshrs.scala:227:{28,47}]
wire [39:0] _io_mem_acquire_bits_legal_T_1 = _io_mem_acquire_bits_T_1; // @[Parameters.scala:137:31]
wire [40:0] _io_mem_acquire_bits_legal_T_2 = {1'h0, _io_mem_acquire_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_mem_acquire_bits_legal_T_3 = _io_mem_acquire_bits_legal_T_2 & 41'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_mem_acquire_bits_legal_T_4 = _io_mem_acquire_bits_legal_T_3; // @[Parameters.scala:137:46]
wire _io_mem_acquire_bits_legal_T_5 = _io_mem_acquire_bits_legal_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _io_mem_acquire_bits_legal_T_6 = {_io_mem_acquire_bits_T_1[39:17], _io_mem_acquire_bits_T_1[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31]
wire [40:0] _io_mem_acquire_bits_legal_T_7 = {1'h0, _io_mem_acquire_bits_legal_T_6}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_mem_acquire_bits_legal_T_8 = _io_mem_acquire_bits_legal_T_7 & 41'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_mem_acquire_bits_legal_T_9 = _io_mem_acquire_bits_legal_T_8; // @[Parameters.scala:137:46]
wire _io_mem_acquire_bits_legal_T_10 = _io_mem_acquire_bits_legal_T_9 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _io_mem_acquire_bits_legal_T_11 = {_io_mem_acquire_bits_T_1[39:28], _io_mem_acquire_bits_T_1[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31]
wire [40:0] _io_mem_acquire_bits_legal_T_12 = {1'h0, _io_mem_acquire_bits_legal_T_11}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_mem_acquire_bits_legal_T_13 = _io_mem_acquire_bits_legal_T_12 & 41'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_mem_acquire_bits_legal_T_14 = _io_mem_acquire_bits_legal_T_13; // @[Parameters.scala:137:46]
wire _io_mem_acquire_bits_legal_T_15 = _io_mem_acquire_bits_legal_T_14 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_mem_acquire_bits_legal_T_16 = _io_mem_acquire_bits_legal_T_5 | _io_mem_acquire_bits_legal_T_10; // @[Parameters.scala:685:42]
wire _io_mem_acquire_bits_legal_T_17 = _io_mem_acquire_bits_legal_T_16 | _io_mem_acquire_bits_legal_T_15; // @[Parameters.scala:685:42]
wire [39:0] _io_mem_acquire_bits_legal_T_21 = {_io_mem_acquire_bits_T_1[39:28], _io_mem_acquire_bits_T_1[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31]
wire [40:0] _io_mem_acquire_bits_legal_T_22 = {1'h0, _io_mem_acquire_bits_legal_T_21}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_mem_acquire_bits_legal_T_23 = _io_mem_acquire_bits_legal_T_22 & 41'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_mem_acquire_bits_legal_T_24 = _io_mem_acquire_bits_legal_T_23; // @[Parameters.scala:137:46]
wire _io_mem_acquire_bits_legal_T_25 = _io_mem_acquire_bits_legal_T_24 == 41'h0; // @[Parameters.scala:137:{46,59}]
assign io_mem_acquire_bits_a_address = _io_mem_acquire_bits_T_1[31:0]; // @[Edges.scala:346:17]
wire [39:0] _io_mem_acquire_bits_legal_T_26 = {_io_mem_acquire_bits_T_1[39:32], io_mem_acquire_bits_a_address ^ 32'h80000000}; // @[Edges.scala:346:17]
wire [40:0] _io_mem_acquire_bits_legal_T_27 = {1'h0, _io_mem_acquire_bits_legal_T_26}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_mem_acquire_bits_legal_T_28 = _io_mem_acquire_bits_legal_T_27 & 41'h80000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_mem_acquire_bits_legal_T_29 = _io_mem_acquire_bits_legal_T_28; // @[Parameters.scala:137:46]
wire _io_mem_acquire_bits_legal_T_30 = _io_mem_acquire_bits_legal_T_29 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_mem_acquire_bits_legal_T_31 = _io_mem_acquire_bits_legal_T_25 | _io_mem_acquire_bits_legal_T_30; // @[Parameters.scala:685:42]
wire _io_mem_acquire_bits_legal_T_32 = _io_mem_acquire_bits_legal_T_31; // @[Parameters.scala:684:54, :685:42]
wire io_mem_acquire_bits_legal = _io_mem_acquire_bits_legal_T_32; // @[Parameters.scala:684:54, :686:26]
assign io_mem_acquire_bits_param_0 = io_mem_acquire_bits_a_param; // @[Edges.scala:346:17]
assign io_mem_acquire_bits_address_0 = io_mem_acquire_bits_a_address; // @[Edges.scala:346:17]
assign io_mem_acquire_bits_a_param = {1'h0, grow_param}; // @[Misc.scala:35:36]
wire io_mem_acquire_bits_a_mask_sub_sub_bit = _io_mem_acquire_bits_T_1[2]; // @[Misc.scala:210:26]
wire io_mem_acquire_bits_a_mask_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire io_mem_acquire_bits_a_mask_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T = io_mem_acquire_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38]
wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = io_mem_acquire_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_sub_bit = _io_mem_acquire_bits_T_1[1]; // @[Misc.scala:210:26]
wire io_mem_acquire_bits_a_mask_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire io_mem_acquire_bits_a_mask_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire io_mem_acquire_bits_a_mask_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire io_mem_acquire_bits_a_mask_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_bit = _io_mem_acquire_bits_T_1[0]; // @[Misc.scala:210:26]
wire io_mem_acquire_bits_a_mask_nbit = ~io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire io_mem_acquire_bits_a_mask_eq = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T = io_mem_acquire_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_1 = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_1 = io_mem_acquire_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_2 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_2 = io_mem_acquire_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_3 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_3 = io_mem_acquire_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_4 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_4 = io_mem_acquire_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_5 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_5 = io_mem_acquire_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_6 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_6 = io_mem_acquire_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_7 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_7 = io_mem_acquire_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38]
wire _GEN_29 = ~(|state) | _io_probe_rdy_T_2; // @[package.scala:16:47]
assign io_lb_write_valid_0 = ~_GEN_29 & _io_probe_rdy_T_3 & opdata & io_mem_grant_valid_0; // @[package.scala:16:47]
wire [8:0] _io_lb_write_bits_offset_T = refill_address_inc[11:3]; // @[Edges.scala:269:29]
assign io_lb_write_bits_offset_0 = _io_lb_write_bits_offset_T[2:0]; // @[mshrs.scala:36:7, :238:{31,53}]
assign io_mem_grant_ready_0 = ~_GEN_29 & _io_probe_rdy_T_3 & (~opdata | io_lb_write_ready_0); // @[package.scala:16:47]
wire _grantack_valid_T = io_mem_grant_bits_opcode_0[2]; // @[Edges.scala:71:36]
wire _grantack_valid_T_1 = io_mem_grant_bits_opcode_0[1]; // @[Edges.scala:71:52]
wire _grantack_valid_T_2 = ~_grantack_valid_T_1; // @[Edges.scala:71:{43,52}]
wire _grantack_valid_T_3 = _grantack_valid_T & _grantack_valid_T_2; // @[Edges.scala:71:{36,40,43}]
wire [4:0] _state_T_29 = grant_had_data ? 5'h3 : 5'hC; // @[mshrs.scala:141:27, :250:19]
wire _drain_load_T = _rpq_io_deq_bits_uop_mem_cmd == 5'h0; // @[package.scala:16:47]
wire _drain_load_T_1 = _rpq_io_deq_bits_uop_mem_cmd == 5'h10; // @[package.scala:16:47]
wire _GEN_30 = _rpq_io_deq_bits_uop_mem_cmd == 5'h6; // @[package.scala:16:47]
wire _drain_load_T_2; // @[package.scala:16:47]
assign _drain_load_T_2 = _GEN_30; // @[package.scala:16:47]
wire _r_c_cat_T_48; // @[Consts.scala:91:71]
assign _r_c_cat_T_48 = _GEN_30; // @[package.scala:16:47]
wire _GEN_31 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[package.scala:16:47]
wire _drain_load_T_3; // @[package.scala:16:47]
assign _drain_load_T_3 = _GEN_31; // @[package.scala:16:47]
wire _drain_load_T_28; // @[Consts.scala:90:66]
assign _drain_load_T_28 = _GEN_31; // @[package.scala:16:47]
wire _drain_load_T_4 = _drain_load_T | _drain_load_T_1; // @[package.scala:16:47, :81:59]
wire _drain_load_T_5 = _drain_load_T_4 | _drain_load_T_2; // @[package.scala:16:47, :81:59]
wire _drain_load_T_6 = _drain_load_T_5 | _drain_load_T_3; // @[package.scala:16:47, :81:59]
wire _GEN_32 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _drain_load_T_7; // @[package.scala:16:47]
assign _drain_load_T_7 = _GEN_32; // @[package.scala:16:47]
wire _drain_load_T_30; // @[package.scala:16:47]
assign _drain_load_T_30 = _GEN_32; // @[package.scala:16:47]
wire _GEN_33 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _drain_load_T_8; // @[package.scala:16:47]
assign _drain_load_T_8 = _GEN_33; // @[package.scala:16:47]
wire _drain_load_T_31; // @[package.scala:16:47]
assign _drain_load_T_31 = _GEN_33; // @[package.scala:16:47]
wire _GEN_34 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _drain_load_T_9; // @[package.scala:16:47]
assign _drain_load_T_9 = _GEN_34; // @[package.scala:16:47]
wire _drain_load_T_32; // @[package.scala:16:47]
assign _drain_load_T_32 = _GEN_34; // @[package.scala:16:47]
wire _GEN_35 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _drain_load_T_10; // @[package.scala:16:47]
assign _drain_load_T_10 = _GEN_35; // @[package.scala:16:47]
wire _drain_load_T_33; // @[package.scala:16:47]
assign _drain_load_T_33 = _GEN_35; // @[package.scala:16:47]
wire _drain_load_T_11 = _drain_load_T_7 | _drain_load_T_8; // @[package.scala:16:47, :81:59]
wire _drain_load_T_12 = _drain_load_T_11 | _drain_load_T_9; // @[package.scala:16:47, :81:59]
wire _drain_load_T_13 = _drain_load_T_12 | _drain_load_T_10; // @[package.scala:16:47, :81:59]
wire _GEN_36 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _drain_load_T_14; // @[package.scala:16:47]
assign _drain_load_T_14 = _GEN_36; // @[package.scala:16:47]
wire _drain_load_T_37; // @[package.scala:16:47]
assign _drain_load_T_37 = _GEN_36; // @[package.scala:16:47]
wire _GEN_37 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _drain_load_T_15; // @[package.scala:16:47]
assign _drain_load_T_15 = _GEN_37; // @[package.scala:16:47]
wire _drain_load_T_38; // @[package.scala:16:47]
assign _drain_load_T_38 = _GEN_37; // @[package.scala:16:47]
wire _GEN_38 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _drain_load_T_16; // @[package.scala:16:47]
assign _drain_load_T_16 = _GEN_38; // @[package.scala:16:47]
wire _drain_load_T_39; // @[package.scala:16:47]
assign _drain_load_T_39 = _GEN_38; // @[package.scala:16:47]
wire _GEN_39 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _drain_load_T_17; // @[package.scala:16:47]
assign _drain_load_T_17 = _GEN_39; // @[package.scala:16:47]
wire _drain_load_T_40; // @[package.scala:16:47]
assign _drain_load_T_40 = _GEN_39; // @[package.scala:16:47]
wire _GEN_40 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _drain_load_T_18; // @[package.scala:16:47]
assign _drain_load_T_18 = _GEN_40; // @[package.scala:16:47]
wire _drain_load_T_41; // @[package.scala:16:47]
assign _drain_load_T_41 = _GEN_40; // @[package.scala:16:47]
wire _drain_load_T_19 = _drain_load_T_14 | _drain_load_T_15; // @[package.scala:16:47, :81:59]
wire _drain_load_T_20 = _drain_load_T_19 | _drain_load_T_16; // @[package.scala:16:47, :81:59]
wire _drain_load_T_21 = _drain_load_T_20 | _drain_load_T_17; // @[package.scala:16:47, :81:59]
wire _drain_load_T_22 = _drain_load_T_21 | _drain_load_T_18; // @[package.scala:16:47, :81:59]
wire _drain_load_T_23 = _drain_load_T_13 | _drain_load_T_22; // @[package.scala:81:59]
wire _drain_load_T_24 = _drain_load_T_6 | _drain_load_T_23; // @[package.scala:81:59]
wire _drain_load_T_25 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32]
wire _drain_load_T_26 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49]
wire _drain_load_T_27 = _drain_load_T_25 | _drain_load_T_26; // @[Consts.scala:90:{32,42,49}]
wire _drain_load_T_29 = _drain_load_T_27 | _drain_load_T_28; // @[Consts.scala:90:{42,59,66}]
wire _drain_load_T_34 = _drain_load_T_30 | _drain_load_T_31; // @[package.scala:16:47, :81:59]
wire _drain_load_T_35 = _drain_load_T_34 | _drain_load_T_32; // @[package.scala:16:47, :81:59]
wire _drain_load_T_36 = _drain_load_T_35 | _drain_load_T_33; // @[package.scala:16:47, :81:59]
wire _drain_load_T_42 = _drain_load_T_37 | _drain_load_T_38; // @[package.scala:16:47, :81:59]
wire _drain_load_T_43 = _drain_load_T_42 | _drain_load_T_39; // @[package.scala:16:47, :81:59]
wire _drain_load_T_44 = _drain_load_T_43 | _drain_load_T_40; // @[package.scala:16:47, :81:59]
wire _drain_load_T_45 = _drain_load_T_44 | _drain_load_T_41; // @[package.scala:16:47, :81:59]
wire _drain_load_T_46 = _drain_load_T_36 | _drain_load_T_45; // @[package.scala:81:59]
wire _drain_load_T_47 = _drain_load_T_29 | _drain_load_T_46; // @[Consts.scala:87:44, :90:{59,76}]
wire _drain_load_T_48 = ~_drain_load_T_47; // @[Consts.scala:90:76]
wire _drain_load_T_49 = _drain_load_T_24 & _drain_load_T_48; // @[Consts.scala:89:68]
wire _drain_load_T_50 = _rpq_io_deq_bits_uop_mem_cmd != 5'h6; // @[mshrs.scala:128:19, :259:51]
wire drain_load = _drain_load_T_49 & _drain_load_T_50; // @[mshrs.scala:257:59, :258:60, :259:51]
wire [5:0] _rp_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :261:61]
wire [39:0] rp_addr = {rp_addr_hi, _rp_addr_T}; // @[mshrs.scala:261:{22,61}]
wire [1:0] size; // @[AMOALU.scala:11:18]
wire _rpq_io_deq_ready_T = io_resp_ready_0 & io_lb_read_ready_0; // @[mshrs.scala:36:7, :270:45]
wire _rpq_io_deq_ready_T_1 = _rpq_io_deq_ready_T & drain_load; // @[mshrs.scala:258:60, :270:{45,65}]
wire _io_lb_read_valid_T = _rpq_io_deq_valid & drain_load; // @[mshrs.scala:128:19, :258:60, :271:48]
wire [36:0] _io_lb_read_bits_offset_T = _rpq_io_deq_bits_addr[39:3]; // @[mshrs.scala:128:19, :273:52]
wire _GEN_41 = io_lb_read_ready_0 & io_lb_read_valid_0; // @[Decoupled.scala:51:35]
wire _io_resp_valid_T; // @[Decoupled.scala:51:35]
assign _io_resp_valid_T = _GEN_41; // @[Decoupled.scala:51:35]
wire _io_refill_valid_T; // @[Decoupled.scala:51:35]
assign _io_refill_valid_T = _GEN_41; // @[Decoupled.scala:51:35]
wire _io_resp_valid_T_1 = _rpq_io_deq_valid & _io_resp_valid_T; // @[Decoupled.scala:51:35]
wire _io_resp_valid_T_2 = _io_resp_valid_T_1 & drain_load; // @[mshrs.scala:258:60, :275:{43,62}]
wire _GEN_42 = ~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3; // @[package.scala:16:47]
assign io_resp_valid_0 = ~_GEN_42 & _io_probe_rdy_T_4 & _io_resp_valid_T_2; // @[package.scala:16:47]
wire _io_resp_bits_data_shifted_T = _rpq_io_deq_bits_addr[2]; // @[AMOALU.scala:42:29]
wire [31:0] _io_resp_bits_data_shifted_T_1 = data_word[63:32]; // @[AMOALU.scala:42:37]
wire [31:0] _io_resp_bits_data_T_5 = data_word[63:32]; // @[AMOALU.scala:42:37, :45:94]
wire [31:0] _io_resp_bits_data_shifted_T_2 = data_word[31:0]; // @[AMOALU.scala:42:55]
wire [31:0] io_resp_bits_data_shifted = _io_resp_bits_data_shifted_T ? _io_resp_bits_data_shifted_T_1 : _io_resp_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}]
wire [31:0] io_resp_bits_data_zeroed = io_resp_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23]
wire _io_resp_bits_data_T = size == 2'h2; // @[AMOALU.scala:11:18, :45:26]
wire _io_resp_bits_data_T_1 = _io_resp_bits_data_T; // @[AMOALU.scala:45:{26,34}]
wire _io_resp_bits_data_T_2 = io_resp_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81]
wire _io_resp_bits_data_T_3 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_2; // @[AMOALU.scala:45:{72,81}]
wire [31:0] _io_resp_bits_data_T_4 = {32{_io_resp_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}]
wire [31:0] _io_resp_bits_data_T_6 = _io_resp_bits_data_T_1 ? _io_resp_bits_data_T_4 : _io_resp_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _io_resp_bits_data_T_7 = {_io_resp_bits_data_T_6, io_resp_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}]
wire _io_resp_bits_data_shifted_T_3 = _rpq_io_deq_bits_addr[1]; // @[AMOALU.scala:42:29]
wire [15:0] _io_resp_bits_data_shifted_T_4 = _io_resp_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16]
wire [15:0] _io_resp_bits_data_shifted_T_5 = _io_resp_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16]
wire [15:0] io_resp_bits_data_shifted_1 = _io_resp_bits_data_shifted_T_3 ? _io_resp_bits_data_shifted_T_4 : _io_resp_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}]
wire [15:0] io_resp_bits_data_zeroed_1 = io_resp_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23]
wire _io_resp_bits_data_T_8 = size == 2'h1; // @[AMOALU.scala:11:18, :45:26]
wire _io_resp_bits_data_T_9 = _io_resp_bits_data_T_8; // @[AMOALU.scala:45:{26,34}]
wire _io_resp_bits_data_T_10 = io_resp_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81]
wire _io_resp_bits_data_T_11 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_10; // @[AMOALU.scala:45:{72,81}]
wire [47:0] _io_resp_bits_data_T_12 = {48{_io_resp_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}]
wire [47:0] _io_resp_bits_data_T_13 = _io_resp_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}]
wire [47:0] _io_resp_bits_data_T_14 = _io_resp_bits_data_T_9 ? _io_resp_bits_data_T_12 : _io_resp_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _io_resp_bits_data_T_15 = {_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}]
wire _io_resp_bits_data_shifted_T_6 = _rpq_io_deq_bits_addr[0]; // @[AMOALU.scala:42:29]
wire [7:0] _io_resp_bits_data_shifted_T_7 = _io_resp_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16]
wire [7:0] _io_resp_bits_data_shifted_T_8 = _io_resp_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16]
wire [7:0] io_resp_bits_data_shifted_2 = _io_resp_bits_data_shifted_T_6 ? _io_resp_bits_data_shifted_T_7 : _io_resp_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}]
wire [7:0] io_resp_bits_data_zeroed_2 = io_resp_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23]
wire _io_resp_bits_data_T_16 = size == 2'h0; // @[AMOALU.scala:11:18, :45:26]
wire _io_resp_bits_data_T_17 = _io_resp_bits_data_T_16; // @[AMOALU.scala:45:{26,34}]
wire _io_resp_bits_data_T_18 = io_resp_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81]
wire _io_resp_bits_data_T_19 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_18; // @[AMOALU.scala:45:{72,81}]
wire [55:0] _io_resp_bits_data_T_20 = {56{_io_resp_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}]
wire [55:0] _io_resp_bits_data_T_21 = _io_resp_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}]
wire [55:0] _io_resp_bits_data_T_22 = _io_resp_bits_data_T_17 ? _io_resp_bits_data_T_20 : _io_resp_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}]
assign _io_resp_bits_data_T_23 = {_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}]
assign io_resp_bits_data_0 = _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16]
wire _T_26 = rpq_io_deq_ready & _rpq_io_deq_valid; // @[Decoupled.scala:51:35]
wire _T_28 = _rpq_io_empty & ~commit_line; // @[mshrs.scala:128:19, :140:24, :282:{31,34}]
wire _T_33 = _rpq_io_empty | _rpq_io_deq_valid & ~drain_load; // @[mshrs.scala:128:19, :258:60, :288:{31,52,55}]
assign io_commit_val_0 = ~_GEN_42 & _io_probe_rdy_T_4 & ~(_T_26 | _T_28) & _T_33; // @[Decoupled.scala:51:35]
wire _io_meta_read_valid_T = ~io_prober_state_valid_0; // @[mshrs.scala:36:7, :295:27]
wire _io_meta_read_valid_T_1 = ~grantack_valid; // @[mshrs.scala:138:21, :295:53]
wire _io_meta_read_valid_T_2 = _io_meta_read_valid_T | _io_meta_read_valid_T_1; // @[mshrs.scala:295:{27,50,53}]
wire [5:0] _io_meta_read_valid_T_3 = io_prober_state_bits_0[11:6]; // @[mshrs.scala:36:7, :295:93]
wire _io_meta_read_valid_T_4 = _io_meta_read_valid_T_3 != req_idx; // @[mshrs.scala:110:25, :295:{93,120}]
wire _io_meta_read_valid_T_5 = _io_meta_read_valid_T_2 | _io_meta_read_valid_T_4; // @[mshrs.scala:295:{50,69,120}]
assign io_meta_read_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4) & _io_probe_rdy_T_8 & _io_meta_read_valid_T_5; // @[package.scala:16:47]
assign io_meta_write_bits_data_tag_0 = req_tag[19:0]; // @[mshrs.scala:36:7, :111:26, :297:27]
assign io_meta_read_bits_tag_0 = req_tag[19:0]; // @[mshrs.scala:36:7, :111:26, :297:27]
wire _T_36 = state == 5'h5; // @[mshrs.scala:107:22, :302:22]
wire _T_37 = state == 5'h6; // @[mshrs.scala:107:22, :304:22]
wire [3:0] _needs_wb_r_T_6 = {2'h2, io_meta_resp_bits_coh_state_0}; // @[Metadata.scala:120:19]
wire _needs_wb_r_T_19 = _needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _needs_wb_r_T_21 = _needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_23 = _needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _needs_wb_r_T_25 = _needs_wb_r_T_23 ? 3'h2 : _needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_27 = _needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _needs_wb_r_T_29 = _needs_wb_r_T_27 ? 3'h1 : _needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_31 = _needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20]
wire _needs_wb_r_T_32 = _needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_33 = _needs_wb_r_T_31 ? 3'h1 : _needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_35 = _needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20]
wire _needs_wb_r_T_36 = ~_needs_wb_r_T_35 & _needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_37 = _needs_wb_r_T_35 ? 3'h5 : _needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_39 = _needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20]
wire _needs_wb_r_T_40 = ~_needs_wb_r_T_39 & _needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_41 = _needs_wb_r_T_39 ? 3'h4 : _needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_42 = {1'h0, _needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_43 = _needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20]
wire _needs_wb_r_T_44 = ~_needs_wb_r_T_43 & _needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_45 = _needs_wb_r_T_43 ? 3'h0 : _needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_46 = _needs_wb_r_T_43 ? 2'h1 : _needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_47 = _needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20]
wire _needs_wb_r_T_48 = _needs_wb_r_T_47 | _needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_49 = _needs_wb_r_T_47 ? 3'h0 : _needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_50 = _needs_wb_r_T_47 ? 2'h1 : _needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_51 = _needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20]
wire _needs_wb_r_T_52 = ~_needs_wb_r_T_51 & _needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_53 = _needs_wb_r_T_51 ? 3'h5 : _needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_54 = _needs_wb_r_T_51 ? 2'h0 : _needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_55 = _needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20]
wire _needs_wb_r_T_56 = ~_needs_wb_r_T_55 & _needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_57 = _needs_wb_r_T_55 ? 3'h4 : _needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_58 = _needs_wb_r_T_55 ? 2'h1 : _needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_59 = _needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20]
wire _needs_wb_r_T_60 = ~_needs_wb_r_T_59 & _needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_61 = _needs_wb_r_T_59 ? 3'h3 : _needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_62 = _needs_wb_r_T_59 ? 2'h2 : _needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_63 = _needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20]
wire needs_wb = _needs_wb_r_T_63 | _needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20]
wire [2:0] needs_wb_r_2 = _needs_wb_r_T_63 ? 3'h3 : _needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20]
wire [1:0] needs_wb_r_3 = _needs_wb_r_T_63 ? 2'h2 : _needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20]
wire [1:0] needs_wb_meta_state = needs_wb_r_3; // @[Misc.scala:38:63]
wire _state_T_30 = ~io_meta_resp_valid_0; // @[mshrs.scala:36:7, :306:18]
wire [4:0] _state_T_31 = needs_wb ? 5'h7 : 5'hB; // @[Misc.scala:38:9]
wire [4:0] _state_T_32 = _state_T_30 ? 5'h4 : _state_T_31; // @[mshrs.scala:306:{17,18}, :307:17]
wire _T_38 = state == 5'h7; // @[mshrs.scala:107:22, :308:22]
wire _T_40 = state == 5'h9; // @[mshrs.scala:107:22, :318:22]
assign io_wb_req_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38) & _T_40; // @[package.scala:16:47]
wire _T_42 = state == 5'hA; // @[mshrs.scala:107:22, :330:22]
wire _T_43 = state == 5'hB; // @[mshrs.scala:107:22, :334:22]
wire _GEN_43 = _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42; // @[mshrs.scala:148:129, :179:26, :294:39, :302:{22,41}, :304:{22,41}, :308:{22,40}, :318:{22,36}, :330:{22,37}, :334:41]
assign io_lb_read_valid_0 = ~_GEN_42 & (_io_probe_rdy_T_4 ? _io_lb_read_valid_T : ~_GEN_43 & _T_43); // @[package.scala:16:47]
assign io_lb_read_bits_offset_0 = _io_probe_rdy_T_4 ? _io_lb_read_bits_offset_T[2:0] : refill_ctr; // @[package.scala:16:47]
wire _GEN_44 = _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _GEN_43; // @[package.scala:16:47]
assign io_refill_valid_0 = ~(~(|state) | _GEN_44) & _T_43 & _io_refill_valid_T; // @[Decoupled.scala:51:35]
wire [5:0] _io_refill_bits_addr_T = {refill_ctr, 3'h0}; // @[mshrs.scala:139:24, :340:59]
wire [39:0] _io_refill_bits_addr_T_1 = {req_block_addr[39:6], req_block_addr[5:0] | _io_refill_bits_addr_T}; // @[mshrs.scala:112:51, :340:{45,59}]
assign io_refill_bits_addr_0 = _io_refill_bits_addr_T_1[11:0]; // @[mshrs.scala:36:7, :340:{27,45}]
wire [3:0] _refill_ctr_T = {1'h0, refill_ctr} + 4'h1; // @[mshrs.scala:139:24, :345:32]
wire [2:0] _refill_ctr_T_1 = _refill_ctr_T[2:0]; // @[mshrs.scala:345:32]
wire _T_46 = state == 5'hC; // @[mshrs.scala:107:22, :350:22]
wire _GEN_45 = _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43; // @[mshrs.scala:148:129, :164:26, :294:39, :302:{22,41}, :304:{22,41}, :308:{22,40}, :318:{22,36}, :330:{22,37}, :334:{22,41}, :350:39]
wire _GEN_46 = _io_probe_rdy_T_4 | _GEN_45; // @[package.scala:16:47]
assign io_replay_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_46) & _T_46 & _rpq_io_deq_valid; // @[package.scala:16:47]
assign rpq_io_deq_ready = ~_GEN_42 & (_io_probe_rdy_T_4 ? _rpq_io_deq_ready_T_1 : ~_GEN_45 & _T_46 & io_replay_ready_0); // @[package.scala:16:47]
wire [5:0] _io_replay_bits_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :353:70]
assign _io_replay_bits_addr_T_1 = {io_replay_bits_addr_hi, _io_replay_bits_addr_T}; // @[mshrs.scala:353:{31,70}]
assign io_replay_bits_addr_0 = _io_replay_bits_addr_T_1; // @[mshrs.scala:36:7, :353:31]
wire _T_48 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32]
wire _r_c_cat_T; // @[Consts.scala:90:32]
assign _r_c_cat_T = _T_48; // @[Consts.scala:90:32]
wire _r_c_cat_T_23; // @[Consts.scala:90:32]
assign _r_c_cat_T_23 = _T_48; // @[Consts.scala:90:32]
wire _T_49 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49]
wire _r_c_cat_T_1; // @[Consts.scala:90:49]
assign _r_c_cat_T_1 = _T_49; // @[Consts.scala:90:49]
wire _r_c_cat_T_24; // @[Consts.scala:90:49]
assign _r_c_cat_T_24 = _T_49; // @[Consts.scala:90:49]
wire _T_51 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66]
wire _r_c_cat_T_3; // @[Consts.scala:90:66]
assign _r_c_cat_T_3 = _T_51; // @[Consts.scala:90:66]
wire _r_c_cat_T_26; // @[Consts.scala:90:66]
assign _r_c_cat_T_26 = _T_51; // @[Consts.scala:90:66]
wire _T_53 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _r_c_cat_T_5; // @[package.scala:16:47]
assign _r_c_cat_T_5 = _T_53; // @[package.scala:16:47]
wire _r_c_cat_T_28; // @[package.scala:16:47]
assign _r_c_cat_T_28 = _T_53; // @[package.scala:16:47]
wire _T_54 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _r_c_cat_T_6; // @[package.scala:16:47]
assign _r_c_cat_T_6 = _T_54; // @[package.scala:16:47]
wire _r_c_cat_T_29; // @[package.scala:16:47]
assign _r_c_cat_T_29 = _T_54; // @[package.scala:16:47]
wire _T_55 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _r_c_cat_T_7; // @[package.scala:16:47]
assign _r_c_cat_T_7 = _T_55; // @[package.scala:16:47]
wire _r_c_cat_T_30; // @[package.scala:16:47]
assign _r_c_cat_T_30 = _T_55; // @[package.scala:16:47]
wire _T_56 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _r_c_cat_T_8; // @[package.scala:16:47]
assign _r_c_cat_T_8 = _T_56; // @[package.scala:16:47]
wire _r_c_cat_T_31; // @[package.scala:16:47]
assign _r_c_cat_T_31 = _T_56; // @[package.scala:16:47]
wire _T_60 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _r_c_cat_T_12; // @[package.scala:16:47]
assign _r_c_cat_T_12 = _T_60; // @[package.scala:16:47]
wire _r_c_cat_T_35; // @[package.scala:16:47]
assign _r_c_cat_T_35 = _T_60; // @[package.scala:16:47]
wire _T_61 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _r_c_cat_T_13; // @[package.scala:16:47]
assign _r_c_cat_T_13 = _T_61; // @[package.scala:16:47]
wire _r_c_cat_T_36; // @[package.scala:16:47]
assign _r_c_cat_T_36 = _T_61; // @[package.scala:16:47]
wire _T_62 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _r_c_cat_T_14; // @[package.scala:16:47]
assign _r_c_cat_T_14 = _T_62; // @[package.scala:16:47]
wire _r_c_cat_T_37; // @[package.scala:16:47]
assign _r_c_cat_T_37 = _T_62; // @[package.scala:16:47]
wire _T_63 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _r_c_cat_T_15; // @[package.scala:16:47]
assign _r_c_cat_T_15 = _T_63; // @[package.scala:16:47]
wire _r_c_cat_T_38; // @[package.scala:16:47]
assign _r_c_cat_T_38 = _T_63; // @[package.scala:16:47]
wire _T_64 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _r_c_cat_T_16; // @[package.scala:16:47]
assign _r_c_cat_T_16 = _T_64; // @[package.scala:16:47]
wire _r_c_cat_T_39; // @[package.scala:16:47]
assign _r_c_cat_T_39 = _T_64; // @[package.scala:16:47]
wire _T_71 = io_replay_ready_0 & io_replay_valid_0 & (_T_48 | _T_49 | _T_51 | _T_53 | _T_54 | _T_55 | _T_56 | _T_60 | _T_61 | _T_62 | _T_63 | _T_64); // @[Decoupled.scala:51:35]
wire _r_c_cat_T_2 = _r_c_cat_T | _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_4 = _r_c_cat_T_2 | _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_9 = _r_c_cat_T_5 | _r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_10 = _r_c_cat_T_9 | _r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_11 = _r_c_cat_T_10 | _r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_17 = _r_c_cat_T_12 | _r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_18 = _r_c_cat_T_17 | _r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_19 = _r_c_cat_T_18 | _r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_20 = _r_c_cat_T_19 | _r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_21 = _r_c_cat_T_11 | _r_c_cat_T_20; // @[package.scala:81:59]
wire _r_c_cat_T_22 = _r_c_cat_T_4 | _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_25 = _r_c_cat_T_23 | _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_27 = _r_c_cat_T_25 | _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_32 = _r_c_cat_T_28 | _r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_33 = _r_c_cat_T_32 | _r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_34 = _r_c_cat_T_33 | _r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_40 = _r_c_cat_T_35 | _r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_41 = _r_c_cat_T_40 | _r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_42 = _r_c_cat_T_41 | _r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_43 = _r_c_cat_T_42 | _r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_44 = _r_c_cat_T_34 | _r_c_cat_T_43; // @[package.scala:81:59]
wire _r_c_cat_T_45 = _r_c_cat_T_27 | _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_46 = _rpq_io_deq_bits_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54]
wire _r_c_cat_T_47 = _r_c_cat_T_45 | _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _r_c_cat_T_49 = _r_c_cat_T_47 | _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _r_T_64 = {r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r_T_89 = _r_T_64 == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r_T_91 = {1'h0, _r_T_89}; // @[Misc.scala:35:36, :49:20]
wire _r_T_92 = _r_T_64 == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r_T_94 = _r_T_92 ? 2'h2 : _r_T_91; // @[Misc.scala:35:36, :49:20]
wire _r_T_95 = _r_T_64 == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r_T_97 = _r_T_95 ? 2'h1 : _r_T_94; // @[Misc.scala:35:36, :49:20]
wire _r_T_98 = _r_T_64 == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r_T_100 = _r_T_98 ? 2'h2 : _r_T_97; // @[Misc.scala:35:36, :49:20]
wire _r_T_101 = _r_T_64 == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r_T_103 = _r_T_101 ? 2'h0 : _r_T_100; // @[Misc.scala:35:36, :49:20]
wire _r_T_104 = _r_T_64 == 4'hE; // @[Misc.scala:49:20]
wire _r_T_105 = _r_T_104; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_106 = _r_T_104 ? 2'h3 : _r_T_103; // @[Misc.scala:35:36, :49:20]
wire _r_T_107 = &_r_T_64; // @[Misc.scala:49:20]
wire _r_T_108 = _r_T_107 | _r_T_105; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_109 = _r_T_107 ? 2'h3 : _r_T_106; // @[Misc.scala:35:36, :49:20]
wire _r_T_110 = _r_T_64 == 4'h6; // @[Misc.scala:49:20]
wire _r_T_111 = _r_T_110 | _r_T_108; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_112 = _r_T_110 ? 2'h2 : _r_T_109; // @[Misc.scala:35:36, :49:20]
wire _r_T_113 = _r_T_64 == 4'h7; // @[Misc.scala:49:20]
wire _r_T_114 = _r_T_113 | _r_T_111; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_115 = _r_T_113 ? 2'h3 : _r_T_112; // @[Misc.scala:35:36, :49:20]
wire _r_T_116 = _r_T_64 == 4'h1; // @[Misc.scala:49:20]
wire _r_T_117 = _r_T_116 | _r_T_114; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_118 = _r_T_116 ? 2'h1 : _r_T_115; // @[Misc.scala:35:36, :49:20]
wire _r_T_119 = _r_T_64 == 4'h2; // @[Misc.scala:49:20]
wire _r_T_120 = _r_T_119 | _r_T_117; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_121 = _r_T_119 ? 2'h2 : _r_T_118; // @[Misc.scala:35:36, :49:20]
wire _r_T_122 = _r_T_64 == 4'h3; // @[Misc.scala:49:20]
wire is_hit = _r_T_122 | _r_T_120; // @[Misc.scala:35:9, :49:20]
wire [1:0] r_2_1 = _r_T_122 ? 2'h3 : _r_T_121; // @[Misc.scala:35:36, :49:20]
wire [1:0] coh_on_hit_state = r_2_1; // @[Misc.scala:35:36]
wire _GEN_47 = _T_40 | _T_42 | _T_43 | _T_46; // @[mshrs.scala:156:26, :318:{22,36}, :330:{22,37}, :334:{22,41}, :350:{22,39}, :363:44]
assign io_meta_write_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37) & (_T_38 | ~_GEN_47 & _sec_rdy_T_4); // @[package.scala:16:47]
assign io_meta_write_bits_data_coh_state_0 = _T_38 ? coh_on_clear_state : new_coh_state; // @[Metadata.scala:160:20]
wire _GEN_48 = _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43 | _T_46 | _sec_rdy_T_4; // @[package.scala:16:47]
assign io_mem_finish_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_48) & _sec_rdy_T_5 & grantack_valid; // @[package.scala:16:47]
wire [4:0] _state_T_33 = finish_to_prefetch ? 5'h11 : 5'h0; // @[mshrs.scala:142:31, :381:17]
wire _GEN_49 = _sec_rdy_T_4 | _sec_rdy_T_5 | _sec_rdy_T_6; // @[package.scala:16:47]
wire _GEN_50 = _T_46 | _GEN_49; // @[mshrs.scala:158:26, :350:{22,39}, :363:44, :373:42, :380:42, :382:38]
wire _GEN_51 = _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43 | _GEN_50; // @[package.scala:16:47]
wire _GEN_52 = _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_51; // @[package.scala:16:47]
assign io_req_pri_rdy_0 = ~(|state) | ~_GEN_52 & _io_way_valid_T_1; // @[package.scala:16:47]
wire _T_87 = io_req_sec_val_0 & ~io_req_sec_rdy_0 | io_clear_prefetch_0; // @[mshrs.scala:36:7, :384:{27,30,47}]
wire _r_c_cat_T_52 = _r_c_cat_T_50 | _r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_54 = _r_c_cat_T_52 | _r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_59 = _r_c_cat_T_55 | _r_c_cat_T_56; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_60 = _r_c_cat_T_59 | _r_c_cat_T_57; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_61 = _r_c_cat_T_60 | _r_c_cat_T_58; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_67 = _r_c_cat_T_62 | _r_c_cat_T_63; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_68 = _r_c_cat_T_67 | _r_c_cat_T_64; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_69 = _r_c_cat_T_68 | _r_c_cat_T_65; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_70 = _r_c_cat_T_69 | _r_c_cat_T_66; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_71 = _r_c_cat_T_61 | _r_c_cat_T_70; // @[package.scala:81:59]
wire _r_c_cat_T_72 = _r_c_cat_T_54 | _r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_75 = _r_c_cat_T_73 | _r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_77 = _r_c_cat_T_75 | _r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_82 = _r_c_cat_T_78 | _r_c_cat_T_79; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_83 = _r_c_cat_T_82 | _r_c_cat_T_80; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_84 = _r_c_cat_T_83 | _r_c_cat_T_81; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_90 = _r_c_cat_T_85 | _r_c_cat_T_86; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_91 = _r_c_cat_T_90 | _r_c_cat_T_87; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_92 = _r_c_cat_T_91 | _r_c_cat_T_88; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_93 = _r_c_cat_T_92 | _r_c_cat_T_89; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_94 = _r_c_cat_T_84 | _r_c_cat_T_93; // @[package.scala:81:59]
wire _r_c_cat_T_95 = _r_c_cat_T_77 | _r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_97 = _r_c_cat_T_95 | _r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}]
wire _r_c_cat_T_99 = _r_c_cat_T_97 | _r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r_c_1 = {_r_c_cat_T_72, _r_c_cat_T_99}; // @[Metadata.scala:29:18]
wire [3:0] _r_T_123 = {r_c_1, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r_T_148 = _r_T_123 == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r_T_150 = {1'h0, _r_T_148}; // @[Misc.scala:35:36, :49:20]
wire _r_T_151 = _r_T_123 == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r_T_153 = _r_T_151 ? 2'h2 : _r_T_150; // @[Misc.scala:35:36, :49:20]
wire _r_T_154 = _r_T_123 == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r_T_156 = _r_T_154 ? 2'h1 : _r_T_153; // @[Misc.scala:35:36, :49:20]
wire _r_T_157 = _r_T_123 == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r_T_159 = _r_T_157 ? 2'h2 : _r_T_156; // @[Misc.scala:35:36, :49:20]
wire _r_T_160 = _r_T_123 == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r_T_162 = _r_T_160 ? 2'h0 : _r_T_159; // @[Misc.scala:35:36, :49:20]
wire _r_T_163 = _r_T_123 == 4'hE; // @[Misc.scala:49:20]
wire _r_T_164 = _r_T_163; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_165 = _r_T_163 ? 2'h3 : _r_T_162; // @[Misc.scala:35:36, :49:20]
wire _r_T_166 = &_r_T_123; // @[Misc.scala:49:20]
wire _r_T_167 = _r_T_166 | _r_T_164; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_168 = _r_T_166 ? 2'h3 : _r_T_165; // @[Misc.scala:35:36, :49:20]
wire _r_T_169 = _r_T_123 == 4'h6; // @[Misc.scala:49:20]
wire _r_T_170 = _r_T_169 | _r_T_167; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_171 = _r_T_169 ? 2'h2 : _r_T_168; // @[Misc.scala:35:36, :49:20]
wire _r_T_172 = _r_T_123 == 4'h7; // @[Misc.scala:49:20]
wire _r_T_173 = _r_T_172 | _r_T_170; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_174 = _r_T_172 ? 2'h3 : _r_T_171; // @[Misc.scala:35:36, :49:20]
wire _r_T_175 = _r_T_123 == 4'h1; // @[Misc.scala:49:20]
wire _r_T_176 = _r_T_175 | _r_T_173; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_177 = _r_T_175 ? 2'h1 : _r_T_174; // @[Misc.scala:35:36, :49:20]
wire _r_T_178 = _r_T_123 == 4'h2; // @[Misc.scala:49:20]
wire _r_T_179 = _r_T_178 | _r_T_176; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_180 = _r_T_178 ? 2'h2 : _r_T_177; // @[Misc.scala:35:36, :49:20]
wire _r_T_181 = _r_T_123 == 4'h3; // @[Misc.scala:49:20]
wire is_hit_1 = _r_T_181 | _r_T_179; // @[Misc.scala:35:9, :49:20]
wire [1:0] r_2_2 = _r_T_181 ? 2'h3 : _r_T_180; // @[Misc.scala:35:36, :49:20]
wire [1:0] coh_on_hit_1_state = r_2_2; // @[Misc.scala:35:36]
wire [4:0] state_new_state_1; // @[mshrs.scala:191:29]
wire _state_T_35 = ~_state_T_34; // @[mshrs.scala:194:11]
wire _state_T_36 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :194:11]
wire _state_req_needs_wb_r_T_83 = _state_req_needs_wb_r_T_70 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_85 = _state_req_needs_wb_r_T_83 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_87 = _state_req_needs_wb_r_T_70 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_89 = _state_req_needs_wb_r_T_87 ? 3'h2 : _state_req_needs_wb_r_T_85; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_91 = _state_req_needs_wb_r_T_70 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_93 = _state_req_needs_wb_r_T_91 ? 3'h1 : _state_req_needs_wb_r_T_89; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_95 = _state_req_needs_wb_r_T_70 == 4'hB; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_96 = _state_req_needs_wb_r_T_95; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_97 = _state_req_needs_wb_r_T_95 ? 3'h1 : _state_req_needs_wb_r_T_93; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_99 = _state_req_needs_wb_r_T_70 == 4'h4; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_100 = ~_state_req_needs_wb_r_T_99 & _state_req_needs_wb_r_T_96; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_101 = _state_req_needs_wb_r_T_99 ? 3'h5 : _state_req_needs_wb_r_T_97; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_103 = _state_req_needs_wb_r_T_70 == 4'h5; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_104 = ~_state_req_needs_wb_r_T_103 & _state_req_needs_wb_r_T_100; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_105 = _state_req_needs_wb_r_T_103 ? 3'h4 : _state_req_needs_wb_r_T_101; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_106 = {1'h0, _state_req_needs_wb_r_T_103}; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_107 = _state_req_needs_wb_r_T_70 == 4'h6; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_108 = ~_state_req_needs_wb_r_T_107 & _state_req_needs_wb_r_T_104; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_109 = _state_req_needs_wb_r_T_107 ? 3'h0 : _state_req_needs_wb_r_T_105; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_110 = _state_req_needs_wb_r_T_107 ? 2'h1 : _state_req_needs_wb_r_T_106; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_111 = _state_req_needs_wb_r_T_70 == 4'h7; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_112 = _state_req_needs_wb_r_T_111 | _state_req_needs_wb_r_T_108; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_113 = _state_req_needs_wb_r_T_111 ? 3'h0 : _state_req_needs_wb_r_T_109; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_114 = _state_req_needs_wb_r_T_111 ? 2'h1 : _state_req_needs_wb_r_T_110; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_115 = _state_req_needs_wb_r_T_70 == 4'h0; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_116 = ~_state_req_needs_wb_r_T_115 & _state_req_needs_wb_r_T_112; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_117 = _state_req_needs_wb_r_T_115 ? 3'h5 : _state_req_needs_wb_r_T_113; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_118 = _state_req_needs_wb_r_T_115 ? 2'h0 : _state_req_needs_wb_r_T_114; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_119 = _state_req_needs_wb_r_T_70 == 4'h1; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_120 = ~_state_req_needs_wb_r_T_119 & _state_req_needs_wb_r_T_116; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_121 = _state_req_needs_wb_r_T_119 ? 3'h4 : _state_req_needs_wb_r_T_117; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_122 = _state_req_needs_wb_r_T_119 ? 2'h1 : _state_req_needs_wb_r_T_118; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_123 = _state_req_needs_wb_r_T_70 == 4'h2; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_124 = ~_state_req_needs_wb_r_T_123 & _state_req_needs_wb_r_T_120; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_125 = _state_req_needs_wb_r_T_123 ? 3'h3 : _state_req_needs_wb_r_T_121; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_126 = _state_req_needs_wb_r_T_123 ? 2'h2 : _state_req_needs_wb_r_T_122; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_127 = _state_req_needs_wb_r_T_70 == 4'h3; // @[Misc.scala:56:20]
wire state_req_needs_wb_r_1_1 = _state_req_needs_wb_r_T_127 | _state_req_needs_wb_r_T_124; // @[Misc.scala:38:9, :56:20]
wire [2:0] state_req_needs_wb_r_2_1 = _state_req_needs_wb_r_T_127 ? 3'h3 : _state_req_needs_wb_r_T_125; // @[Misc.scala:38:36, :56:20]
wire [1:0] state_req_needs_wb_r_3_1 = _state_req_needs_wb_r_T_127 ? 2'h2 : _state_req_needs_wb_r_T_126; // @[Misc.scala:38:63, :56:20]
wire [1:0] state_req_needs_wb_meta_1_state = state_req_needs_wb_r_3_1; // @[Misc.scala:38:63]
wire _state_r_c_cat_T_52 = _state_r_c_cat_T_50 | _state_r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_54 = _state_r_c_cat_T_52 | _state_r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_59 = _state_r_c_cat_T_55 | _state_r_c_cat_T_56; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_60 = _state_r_c_cat_T_59 | _state_r_c_cat_T_57; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_61 = _state_r_c_cat_T_60 | _state_r_c_cat_T_58; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_67 = _state_r_c_cat_T_62 | _state_r_c_cat_T_63; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_68 = _state_r_c_cat_T_67 | _state_r_c_cat_T_64; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_69 = _state_r_c_cat_T_68 | _state_r_c_cat_T_65; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_70 = _state_r_c_cat_T_69 | _state_r_c_cat_T_66; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_71 = _state_r_c_cat_T_61 | _state_r_c_cat_T_70; // @[package.scala:81:59]
wire _state_r_c_cat_T_72 = _state_r_c_cat_T_54 | _state_r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_75 = _state_r_c_cat_T_73 | _state_r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_77 = _state_r_c_cat_T_75 | _state_r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_82 = _state_r_c_cat_T_78 | _state_r_c_cat_T_79; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_83 = _state_r_c_cat_T_82 | _state_r_c_cat_T_80; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_84 = _state_r_c_cat_T_83 | _state_r_c_cat_T_81; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_90 = _state_r_c_cat_T_85 | _state_r_c_cat_T_86; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_91 = _state_r_c_cat_T_90 | _state_r_c_cat_T_87; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_92 = _state_r_c_cat_T_91 | _state_r_c_cat_T_88; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_93 = _state_r_c_cat_T_92 | _state_r_c_cat_T_89; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_94 = _state_r_c_cat_T_84 | _state_r_c_cat_T_93; // @[package.scala:81:59]
wire _state_r_c_cat_T_95 = _state_r_c_cat_T_77 | _state_r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_97 = _state_r_c_cat_T_95 | _state_r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}]
wire _state_r_c_cat_T_99 = _state_r_c_cat_T_97 | _state_r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}]
wire [1:0] state_r_c_1 = {_state_r_c_cat_T_72, _state_r_c_cat_T_99}; // @[Metadata.scala:29:18]
wire [3:0] _state_r_T_59 = {state_r_c_1, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19]
wire _state_r_T_84 = _state_r_T_59 == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_86 = {1'h0, _state_r_T_84}; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_87 = _state_r_T_59 == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_89 = _state_r_T_87 ? 2'h2 : _state_r_T_86; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_90 = _state_r_T_59 == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_92 = _state_r_T_90 ? 2'h1 : _state_r_T_89; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_93 = _state_r_T_59 == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_95 = _state_r_T_93 ? 2'h2 : _state_r_T_92; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_96 = _state_r_T_59 == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_98 = _state_r_T_96 ? 2'h0 : _state_r_T_95; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_99 = _state_r_T_59 == 4'hE; // @[Misc.scala:49:20]
wire _state_r_T_100 = _state_r_T_99; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_101 = _state_r_T_99 ? 2'h3 : _state_r_T_98; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_102 = &_state_r_T_59; // @[Misc.scala:49:20]
wire _state_r_T_103 = _state_r_T_102 | _state_r_T_100; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_104 = _state_r_T_102 ? 2'h3 : _state_r_T_101; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_105 = _state_r_T_59 == 4'h6; // @[Misc.scala:49:20]
wire _state_r_T_106 = _state_r_T_105 | _state_r_T_103; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_107 = _state_r_T_105 ? 2'h2 : _state_r_T_104; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_108 = _state_r_T_59 == 4'h7; // @[Misc.scala:49:20]
wire _state_r_T_109 = _state_r_T_108 | _state_r_T_106; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_110 = _state_r_T_108 ? 2'h3 : _state_r_T_107; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_111 = _state_r_T_59 == 4'h1; // @[Misc.scala:49:20]
wire _state_r_T_112 = _state_r_T_111 | _state_r_T_109; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_113 = _state_r_T_111 ? 2'h1 : _state_r_T_110; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_114 = _state_r_T_59 == 4'h2; // @[Misc.scala:49:20]
wire _state_r_T_115 = _state_r_T_114 | _state_r_T_112; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_116 = _state_r_T_114 ? 2'h2 : _state_r_T_113; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_117 = _state_r_T_59 == 4'h3; // @[Misc.scala:49:20]
wire state_is_hit_1 = _state_r_T_117 | _state_r_T_115; // @[Misc.scala:35:9, :49:20]
wire [1:0] state_r_2_1 = _state_r_T_117 ? 2'h3 : _state_r_T_116; // @[Misc.scala:35:36, :49:20]
wire [1:0] state_coh_on_hit_1_state = state_r_2_1; // @[Misc.scala:35:36]
wire _state_T_39 = _state_T_37 | _state_T_38; // @[Consts.scala:90:{32,42,49}]
wire _state_T_41 = _state_T_39 | _state_T_40; // @[Consts.scala:90:{42,59,66}]
wire _state_T_46 = _state_T_42 | _state_T_43; // @[package.scala:16:47, :81:59]
wire _state_T_47 = _state_T_46 | _state_T_44; // @[package.scala:16:47, :81:59]
wire _state_T_48 = _state_T_47 | _state_T_45; // @[package.scala:16:47, :81:59]
wire _state_T_54 = _state_T_49 | _state_T_50; // @[package.scala:16:47, :81:59]
wire _state_T_55 = _state_T_54 | _state_T_51; // @[package.scala:16:47, :81:59]
wire _state_T_56 = _state_T_55 | _state_T_52; // @[package.scala:16:47, :81:59]
wire _state_T_57 = _state_T_56 | _state_T_53; // @[package.scala:16:47, :81:59]
wire _state_T_58 = _state_T_48 | _state_T_57; // @[package.scala:81:59]
wire _state_T_59 = _state_T_41 | _state_T_58; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_T_61 = ~_state_T_60; // @[mshrs.scala:201:15]
wire _state_T_62 = ~_state_T_59; // @[Consts.scala:90:76] |
Generate the Verilog code corresponding to this FIRRTL code module Tile_233 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_489
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_233( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_489 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_23 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_EntryData_23( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae = io_x_ae_0; // @[package.scala:267:30]
wire io_y_sw = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr = io_x_sr_0; // @[package.scala:267:30]
wire io_y_pw = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr = io_x_pr_0; // @[package.scala:267:30]
wire io_y_pal = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_140 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_161
connect io_out_sink_valid_0.clock, clock
connect io_out_sink_valid_0.reset, reset
connect io_out_sink_valid_0.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_valid_0.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_140( // @[AsyncQueue.scala:58:7]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in = 1'h1; // @[ShiftReg.scala:45:23]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_161 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_115 :
input clock : Clock
input reset : Reset
output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[7], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}}
wire next_state : UInt
wire next_uopc : UInt
wire next_lrs1_rtype : UInt
wire next_lrs2_rtype : UInt
regreset state : UInt<2>, clock, reset, UInt<2>(0h0)
regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0)
connect p1_poisoned, UInt<1>(0h0)
connect p2_poisoned, UInt<1>(0h0)
node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned)
node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned)
wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate slot_uop_uop.debug_tsrc
invalidate slot_uop_uop.debug_fsrc
invalidate slot_uop_uop.bp_xcpt_if
invalidate slot_uop_uop.bp_debug_if
invalidate slot_uop_uop.xcpt_ma_if
invalidate slot_uop_uop.xcpt_ae_if
invalidate slot_uop_uop.xcpt_pf_if
invalidate slot_uop_uop.fp_single
invalidate slot_uop_uop.fp_val
invalidate slot_uop_uop.frs3_en
invalidate slot_uop_uop.lrs2_rtype
invalidate slot_uop_uop.lrs1_rtype
invalidate slot_uop_uop.dst_rtype
invalidate slot_uop_uop.ldst_val
invalidate slot_uop_uop.lrs3
invalidate slot_uop_uop.lrs2
invalidate slot_uop_uop.lrs1
invalidate slot_uop_uop.ldst
invalidate slot_uop_uop.ldst_is_rs1
invalidate slot_uop_uop.flush_on_commit
invalidate slot_uop_uop.is_unique
invalidate slot_uop_uop.is_sys_pc2epc
invalidate slot_uop_uop.uses_stq
invalidate slot_uop_uop.uses_ldq
invalidate slot_uop_uop.is_amo
invalidate slot_uop_uop.is_fencei
invalidate slot_uop_uop.is_fence
invalidate slot_uop_uop.mem_signed
invalidate slot_uop_uop.mem_size
invalidate slot_uop_uop.mem_cmd
invalidate slot_uop_uop.bypassable
invalidate slot_uop_uop.exc_cause
invalidate slot_uop_uop.exception
invalidate slot_uop_uop.stale_pdst
invalidate slot_uop_uop.ppred_busy
invalidate slot_uop_uop.prs3_busy
invalidate slot_uop_uop.prs2_busy
invalidate slot_uop_uop.prs1_busy
invalidate slot_uop_uop.ppred
invalidate slot_uop_uop.prs3
invalidate slot_uop_uop.prs2
invalidate slot_uop_uop.prs1
invalidate slot_uop_uop.pdst
invalidate slot_uop_uop.rxq_idx
invalidate slot_uop_uop.stq_idx
invalidate slot_uop_uop.ldq_idx
invalidate slot_uop_uop.rob_idx
invalidate slot_uop_uop.csr_addr
invalidate slot_uop_uop.imm_packed
invalidate slot_uop_uop.taken
invalidate slot_uop_uop.pc_lob
invalidate slot_uop_uop.edge_inst
invalidate slot_uop_uop.ftq_idx
invalidate slot_uop_uop.br_tag
invalidate slot_uop_uop.br_mask
invalidate slot_uop_uop.is_sfb
invalidate slot_uop_uop.is_jal
invalidate slot_uop_uop.is_jalr
invalidate slot_uop_uop.is_br
invalidate slot_uop_uop.iw_p2_poisoned
invalidate slot_uop_uop.iw_p1_poisoned
invalidate slot_uop_uop.iw_state
invalidate slot_uop_uop.ctrl.is_std
invalidate slot_uop_uop.ctrl.is_sta
invalidate slot_uop_uop.ctrl.is_load
invalidate slot_uop_uop.ctrl.csr_cmd
invalidate slot_uop_uop.ctrl.fcn_dw
invalidate slot_uop_uop.ctrl.op_fcn
invalidate slot_uop_uop.ctrl.imm_sel
invalidate slot_uop_uop.ctrl.op2_sel
invalidate slot_uop_uop.ctrl.op1_sel
invalidate slot_uop_uop.ctrl.br_type
invalidate slot_uop_uop.fu_code
invalidate slot_uop_uop.iq_type
invalidate slot_uop_uop.debug_pc
invalidate slot_uop_uop.is_rvc
invalidate slot_uop_uop.debug_inst
invalidate slot_uop_uop.inst
invalidate slot_uop_uop.uopc
connect slot_uop_uop.uopc, UInt<7>(0h0)
connect slot_uop_uop.bypassable, UInt<1>(0h0)
connect slot_uop_uop.fp_val, UInt<1>(0h0)
connect slot_uop_uop.uses_stq, UInt<1>(0h0)
connect slot_uop_uop.uses_ldq, UInt<1>(0h0)
connect slot_uop_uop.pdst, UInt<1>(0h0)
connect slot_uop_uop.dst_rtype, UInt<2>(0h2)
wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate slot_uop_cs.is_std
invalidate slot_uop_cs.is_sta
invalidate slot_uop_cs.is_load
invalidate slot_uop_cs.csr_cmd
invalidate slot_uop_cs.fcn_dw
invalidate slot_uop_cs.op_fcn
invalidate slot_uop_cs.imm_sel
invalidate slot_uop_cs.op2_sel
invalidate slot_uop_cs.op1_sel
invalidate slot_uop_cs.br_type
connect slot_uop_cs.br_type, UInt<4>(0h0)
connect slot_uop_cs.csr_cmd, UInt<3>(0h0)
connect slot_uop_cs.is_load, UInt<1>(0h0)
connect slot_uop_cs.is_sta, UInt<1>(0h0)
connect slot_uop_cs.is_std, UInt<1>(0h0)
connect slot_uop_uop.ctrl, slot_uop_cs
regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop
node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop)
when io.kill :
connect state, UInt<2>(0h0)
else :
when io.in_uop.valid :
connect state, io.in_uop.bits.iw_state
else :
when io.clear :
connect state, UInt<2>(0h0)
else :
connect state, next_state
connect next_state, state
connect next_uopc, slot_uop.uopc
connect next_lrs1_rtype, slot_uop.lrs1_rtype
connect next_lrs2_rtype, slot_uop.lrs2_rtype
when io.kill :
connect next_state, UInt<2>(0h0)
else :
node _T = eq(state, UInt<2>(0h1))
node _T_1 = and(io.grant, _T)
node _T_2 = eq(state, UInt<2>(0h2))
node _T_3 = and(io.grant, _T_2)
node _T_4 = and(_T_3, p1)
node _T_5 = and(_T_4, p2)
node _T_6 = and(_T_5, ppred)
node _T_7 = or(_T_1, _T_6)
when _T_7 :
node _T_8 = or(p1_poisoned, p2_poisoned)
node _T_9 = and(io.ldspec_miss, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
connect next_state, UInt<2>(0h0)
else :
node _T_11 = eq(state, UInt<2>(0h2))
node _T_12 = and(io.grant, _T_11)
when _T_12 :
node _T_13 = or(p1_poisoned, p2_poisoned)
node _T_14 = and(io.ldspec_miss, _T_13)
node _T_15 = eq(_T_14, UInt<1>(0h0))
when _T_15 :
connect next_state, UInt<2>(0h1)
when p1 :
connect slot_uop.uopc, UInt<7>(0h3)
connect next_uopc, UInt<7>(0h3)
connect slot_uop.lrs1_rtype, UInt<2>(0h2)
connect next_lrs1_rtype, UInt<2>(0h2)
else :
connect slot_uop.lrs2_rtype, UInt<2>(0h2)
connect next_lrs2_rtype, UInt<2>(0h2)
when io.in_uop.valid :
connect slot_uop, io.in_uop.bits
node _T_16 = eq(state, UInt<2>(0h0))
node _T_17 = or(_T_16, io.clear)
node _T_18 = or(_T_17, io.kill)
node _T_19 = asUInt(reset)
node _T_20 = eq(_T_19, UInt<1>(0h0))
when _T_20 :
node _T_21 = eq(_T_18, UInt<1>(0h0))
when _T_21 :
printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf
assert(clock, _T_18, UInt<1>(0h1), "") : assert
wire next_p1 : UInt<1>
connect next_p1, p1
wire next_p2 : UInt<1>
connect next_p2, p2
wire next_p3 : UInt<1>
connect next_p3, p3
wire next_ppred : UInt<1>
connect next_ppred, ppred
when io.in_uop.valid :
node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0))
connect p1, _p1_T
node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0))
connect p2, _p2_T
node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0))
connect p3, _p3_T
node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0))
connect ppred, _ppred_T
node _T_22 = and(io.ldspec_miss, next_p1_poisoned)
when _T_22 :
node _T_23 = neq(next_uop.prs1, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1
assert(clock, _T_23, UInt<1>(0h1), "") : assert_1
connect p1, UInt<1>(0h0)
node _T_27 = and(io.ldspec_miss, next_p2_poisoned)
when _T_27 :
node _T_28 = neq(next_uop.prs2, UInt<1>(0h0))
node _T_29 = asUInt(reset)
node _T_30 = eq(_T_29, UInt<1>(0h0))
when _T_30 :
node _T_31 = eq(_T_28, UInt<1>(0h0))
when _T_31 :
printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2
assert(clock, _T_28, UInt<1>(0h1), "") : assert_2
connect p2, UInt<1>(0h0)
node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1)
node _T_33 = and(io.wakeup_ports[0].valid, _T_32)
when _T_33 :
connect p1, UInt<1>(0h1)
node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2)
node _T_35 = and(io.wakeup_ports[0].valid, _T_34)
when _T_35 :
connect p2, UInt<1>(0h1)
node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3)
node _T_37 = and(io.wakeup_ports[0].valid, _T_36)
when _T_37 :
connect p3, UInt<1>(0h1)
node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1)
node _T_39 = and(io.wakeup_ports[1].valid, _T_38)
when _T_39 :
connect p1, UInt<1>(0h1)
node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2)
node _T_41 = and(io.wakeup_ports[1].valid, _T_40)
when _T_41 :
connect p2, UInt<1>(0h1)
node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3)
node _T_43 = and(io.wakeup_ports[1].valid, _T_42)
when _T_43 :
connect p3, UInt<1>(0h1)
node _T_44 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs1)
node _T_45 = and(io.wakeup_ports[2].valid, _T_44)
when _T_45 :
connect p1, UInt<1>(0h1)
node _T_46 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs2)
node _T_47 = and(io.wakeup_ports[2].valid, _T_46)
when _T_47 :
connect p2, UInt<1>(0h1)
node _T_48 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs3)
node _T_49 = and(io.wakeup_ports[2].valid, _T_48)
when _T_49 :
connect p3, UInt<1>(0h1)
node _T_50 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs1)
node _T_51 = and(io.wakeup_ports[3].valid, _T_50)
when _T_51 :
connect p1, UInt<1>(0h1)
node _T_52 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs2)
node _T_53 = and(io.wakeup_ports[3].valid, _T_52)
when _T_53 :
connect p2, UInt<1>(0h1)
node _T_54 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs3)
node _T_55 = and(io.wakeup_ports[3].valid, _T_54)
when _T_55 :
connect p3, UInt<1>(0h1)
node _T_56 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs1)
node _T_57 = and(io.wakeup_ports[4].valid, _T_56)
when _T_57 :
connect p1, UInt<1>(0h1)
node _T_58 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs2)
node _T_59 = and(io.wakeup_ports[4].valid, _T_58)
when _T_59 :
connect p2, UInt<1>(0h1)
node _T_60 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs3)
node _T_61 = and(io.wakeup_ports[4].valid, _T_60)
when _T_61 :
connect p3, UInt<1>(0h1)
node _T_62 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs1)
node _T_63 = and(io.wakeup_ports[5].valid, _T_62)
when _T_63 :
connect p1, UInt<1>(0h1)
node _T_64 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs2)
node _T_65 = and(io.wakeup_ports[5].valid, _T_64)
when _T_65 :
connect p2, UInt<1>(0h1)
node _T_66 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs3)
node _T_67 = and(io.wakeup_ports[5].valid, _T_66)
when _T_67 :
connect p3, UInt<1>(0h1)
node _T_68 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs1)
node _T_69 = and(io.wakeup_ports[6].valid, _T_68)
when _T_69 :
connect p1, UInt<1>(0h1)
node _T_70 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs2)
node _T_71 = and(io.wakeup_ports[6].valid, _T_70)
when _T_71 :
connect p2, UInt<1>(0h1)
node _T_72 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs3)
node _T_73 = and(io.wakeup_ports[6].valid, _T_72)
when _T_73 :
connect p3, UInt<1>(0h1)
node _T_74 = eq(io.pred_wakeup_port.bits, next_uop.ppred)
node _T_75 = and(io.pred_wakeup_port.valid, _T_74)
when _T_75 :
connect ppred, UInt<1>(0h1)
node _T_76 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0))
node _T_77 = and(io.spec_ld_wakeup[0].valid, _T_76)
node _T_78 = eq(_T_77, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3
assert(clock, _T_78, UInt<1>(0h1), "") : assert_3
node _T_82 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1)
node _T_83 = and(io.spec_ld_wakeup[0].valid, _T_82)
node _T_84 = eq(next_uop.lrs1_rtype, UInt<2>(0h0))
node _T_85 = and(_T_83, _T_84)
when _T_85 :
connect p1, UInt<1>(0h1)
connect p1_poisoned, UInt<1>(0h1)
node _T_86 = eq(next_p1_poisoned, UInt<1>(0h0))
node _T_87 = asUInt(reset)
node _T_88 = eq(_T_87, UInt<1>(0h0))
when _T_88 :
node _T_89 = eq(_T_86, UInt<1>(0h0))
when _T_89 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4
assert(clock, _T_86, UInt<1>(0h1), "") : assert_4
node _T_90 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2)
node _T_91 = and(io.spec_ld_wakeup[0].valid, _T_90)
node _T_92 = eq(next_uop.lrs2_rtype, UInt<2>(0h0))
node _T_93 = and(_T_91, _T_92)
when _T_93 :
connect p2, UInt<1>(0h1)
connect p2_poisoned, UInt<1>(0h1)
node _T_94 = eq(next_p2_poisoned, UInt<1>(0h0))
node _T_95 = asUInt(reset)
node _T_96 = eq(_T_95, UInt<1>(0h0))
when _T_96 :
node _T_97 = eq(_T_94, UInt<1>(0h0))
when _T_97 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5
assert(clock, _T_94, UInt<1>(0h1), "") : assert_5
node _next_br_mask_T = not(io.brupdate.b1.resolve_mask)
node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T)
node _T_98 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask)
node _T_99 = neq(_T_98, UInt<1>(0h0))
when _T_99 :
connect next_state, UInt<2>(0h0)
node _T_100 = eq(io.in_uop.valid, UInt<1>(0h0))
when _T_100 :
connect slot_uop.br_mask, next_br_mask
node _io_request_T = neq(state, UInt<2>(0h0))
node _io_request_T_1 = and(_io_request_T, p1)
node _io_request_T_2 = and(_io_request_T_1, p2)
node _io_request_T_3 = and(_io_request_T_2, p3)
node _io_request_T_4 = and(_io_request_T_3, ppred)
node _io_request_T_5 = eq(io.kill, UInt<1>(0h0))
node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5)
connect io.request, _io_request_T_6
node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal)
node high_priority = or(_high_priority_T, slot_uop.is_jalr)
node _io_request_hp_T = and(io.request, high_priority)
connect io.request_hp, _io_request_hp_T
node _T_101 = eq(state, UInt<2>(0h1))
when _T_101 :
node _io_request_T_7 = and(p1, p2)
node _io_request_T_8 = and(_io_request_T_7, p3)
node _io_request_T_9 = and(_io_request_T_8, ppred)
node _io_request_T_10 = eq(io.kill, UInt<1>(0h0))
node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10)
connect io.request, _io_request_T_11
else :
node _T_102 = eq(state, UInt<2>(0h2))
when _T_102 :
node _io_request_T_12 = or(p1, p2)
node _io_request_T_13 = and(_io_request_T_12, ppred)
node _io_request_T_14 = eq(io.kill, UInt<1>(0h0))
node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14)
connect io.request, _io_request_T_15
else :
connect io.request, UInt<1>(0h0)
node _io_valid_T = neq(state, UInt<2>(0h0))
connect io.valid, _io_valid_T
connect io.uop, slot_uop
connect io.uop.iw_p1_poisoned, p1_poisoned
connect io.uop.iw_p2_poisoned, p2_poisoned
node _may_vacate_T = eq(state, UInt<2>(0h1))
node _may_vacate_T_1 = eq(state, UInt<2>(0h2))
node _may_vacate_T_2 = and(_may_vacate_T_1, p1)
node _may_vacate_T_3 = and(_may_vacate_T_2, p2)
node _may_vacate_T_4 = and(_may_vacate_T_3, ppred)
node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4)
node may_vacate = and(io.grant, _may_vacate_T_5)
node _squash_grant_T = or(p1_poisoned, p2_poisoned)
node squash_grant = and(io.ldspec_miss, _squash_grant_T)
node _io_will_be_valid_T = neq(state, UInt<2>(0h0))
node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0))
node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1)
node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0))
node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3)
connect io.will_be_valid, _io_will_be_valid_T_4
connect io.out_uop, slot_uop
connect io.out_uop.iw_state, next_state
connect io.out_uop.uopc, next_uopc
connect io.out_uop.lrs1_rtype, next_lrs1_rtype
connect io.out_uop.lrs2_rtype, next_lrs2_rtype
connect io.out_uop.br_mask, next_br_mask
node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0))
connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T
node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0))
connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T
node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0))
connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T
node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0))
connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T
connect io.out_uop.iw_p1_poisoned, p1_poisoned
connect io.out_uop.iw_p2_poisoned, p2_poisoned
node _T_103 = eq(state, UInt<2>(0h2))
when _T_103 :
node _T_104 = and(p1, p2)
node _T_105 = and(_T_104, ppred)
when _T_105 :
skip
else :
node _T_106 = and(p1, ppred)
when _T_106 :
connect io.uop.uopc, slot_uop.uopc
connect io.uop.lrs2_rtype, UInt<2>(0h2)
else :
node _T_107 = and(p2, ppred)
when _T_107 :
connect io.uop.uopc, UInt<7>(0h3)
connect io.uop.lrs1_rtype, UInt<2>(0h2)
connect io.debug.p1, p1
connect io.debug.p2, p2
connect io.debug.p3, p3
connect io.debug.ppred, ppred
connect io.debug.state, state | module IssueSlot_115( // @[issue-slot.scala:69:7]
input clock, // @[issue-slot.scala:69:7]
input reset, // @[issue-slot.scala:69:7]
output io_valid, // @[issue-slot.scala:73:14]
output io_will_be_valid, // @[issue-slot.scala:73:14]
output io_request, // @[issue-slot.scala:73:14]
output io_request_hp, // @[issue-slot.scala:73:14]
input io_grant, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_valid, // @[issue-slot.scala:73:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14]
input io_kill, // @[issue-slot.scala:73:14]
input io_clear, // @[issue-slot.scala:73:14]
input io_ldspec_miss, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14]
input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14]
input io_in_uop_valid, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14]
input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:73:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:73:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_is_br, // @[issue-slot.scala:73:14]
output io_out_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_out_uop_is_jal, // @[issue-slot.scala:73:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_out_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_out_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_out_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_out_uop_is_fence, // @[issue-slot.scala:73:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_out_uop_is_amo, // @[issue-slot.scala:73:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_out_uop_is_unique, // @[issue-slot.scala:73:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_out_uop_fp_val, // @[issue-slot.scala:73:14]
output io_out_uop_fp_single, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14]
output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_uop_is_br, // @[issue-slot.scala:73:14]
output io_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_uop_is_jal, // @[issue-slot.scala:73:14]
output io_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14]
output io_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14]
output io_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_uop_is_fence, // @[issue-slot.scala:73:14]
output io_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_uop_is_amo, // @[issue-slot.scala:73:14]
output io_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_uop_is_unique, // @[issue-slot.scala:73:14]
output io_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14]
output io_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_uop_fp_val, // @[issue-slot.scala:73:14]
output io_uop_fp_single, // @[issue-slot.scala:73:14]
output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output io_debug_p1, // @[issue-slot.scala:73:14]
output io_debug_p2, // @[issue-slot.scala:73:14]
output io_debug_p3, // @[issue-slot.scala:73:14]
output io_debug_ppred, // @[issue-slot.scala:73:14]
output [1:0] io_debug_state // @[issue-slot.scala:73:14]
);
wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7]
wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7]
wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7]
wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire _io_valid_T; // @[issue-slot.scala:79:24]
wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32]
wire _io_request_hp_T; // @[issue-slot.scala:243:31]
wire [6:0] next_uopc; // @[issue-slot.scala:82:29]
wire [1:0] next_state; // @[issue-slot.scala:81:29]
wire [15:0] next_br_mask; // @[util.scala:85:25]
wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28]
wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28]
wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28]
wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28]
wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29]
wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29]
wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire io_debug_p1_0; // @[issue-slot.scala:69:7]
wire io_debug_p2_0; // @[issue-slot.scala:69:7]
wire io_debug_p3_0; // @[issue-slot.scala:69:7]
wire io_debug_ppred_0; // @[issue-slot.scala:69:7]
wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7]
wire io_valid_0; // @[issue-slot.scala:69:7]
wire io_will_be_valid_0; // @[issue-slot.scala:69:7]
wire io_request_0; // @[issue-slot.scala:69:7]
wire io_request_hp_0; // @[issue-slot.scala:69:7]
assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29]
assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29]
assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29]
assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29]
reg [1:0] state; // @[issue-slot.scala:86:22]
assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22]
reg p1; // @[issue-slot.scala:87:22]
assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22]
wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25]
reg p2; // @[issue-slot.scala:88:22]
assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22]
wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25]
reg p3; // @[issue-slot.scala:89:22]
assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22]
wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25]
reg ppred; // @[issue-slot.scala:90:22]
assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22]
wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28]
reg p1_poisoned; // @[issue-slot.scala:95:28]
assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
reg p2_poisoned; // @[issue-slot.scala:96:28]
assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29]
wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29]
reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_rvc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25]
assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25]
assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25]
assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_is_br; // @[issue-slot.scala:102:25]
assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jalr; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jal; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sfb; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25]
assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25]
assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_edge_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25]
assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_taken; // @[issue-slot.scala:102:25]
assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25]
assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25]
assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25]
assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25]
assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25]
assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25]
assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25]
assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_exception; // @[issue-slot.scala:102:25]
assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25]
assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bypassable; // @[issue-slot.scala:102:25]
assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_mem_signed; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fence; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fencei; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_amo; // @[issue-slot.scala:102:25]
assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_stq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_unique; // @[issue-slot.scala:102:25]
assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25]
assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_val; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25]
assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25]
reg slot_uop_frs3_en; // @[issue-slot.scala:102:25]
assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_val; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_single; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25]
wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}]
wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25]
wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}]
wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18]
wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51]
wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23]
assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51]
assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51]
wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17]
assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11]
wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11]
wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11]
wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14]
wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24]
wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24]
wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27]
wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_17 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 4, 0)
node _source_ok_T = shr(io.in.a.bits.source, 5)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<5>(0h1f))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits = bits(_uncommonBits_T, 4, 0)
node _T_4 = shr(io.in.a.bits.source, 5)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<5>(0h1f))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 4, 0)
node _T_24 = shr(io.in.a.bits.source, 5)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<5>(0h1f))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<14>(0h2000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_39 = cvt(_T_38)
node _T_40 = and(_T_39, asSInt(UInt<13>(0h1000)))
node _T_41 = asSInt(_T_40)
node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0)))
node _T_43 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_44 = cvt(_T_43)
node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000)))
node _T_46 = asSInt(_T_45)
node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<18>(0h2f000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_54 = cvt(_T_53)
node _T_55 = and(_T_54, asSInt(UInt<17>(0h10000)))
node _T_56 = asSInt(_T_55)
node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0)))
node _T_58 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_64 = cvt(_T_63)
node _T_65 = and(_T_64, asSInt(UInt<27>(0h4000000)))
node _T_66 = asSInt(_T_65)
node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0)))
node _T_68 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_69 = cvt(_T_68)
node _T_70 = and(_T_69, asSInt(UInt<13>(0h1000)))
node _T_71 = asSInt(_T_70)
node _T_72 = eq(_T_71, asSInt(UInt<1>(0h0)))
node _T_73 = or(_T_37, _T_42)
node _T_74 = or(_T_73, _T_47)
node _T_75 = or(_T_74, _T_52)
node _T_76 = or(_T_75, _T_57)
node _T_77 = or(_T_76, _T_62)
node _T_78 = or(_T_77, _T_67)
node _T_79 = or(_T_78, _T_72)
node _T_80 = and(_T_32, _T_79)
node _T_81 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_82 = or(UInt<1>(0h0), _T_81)
node _T_83 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_84 = cvt(_T_83)
node _T_85 = and(_T_84, asSInt(UInt<17>(0h10000)))
node _T_86 = asSInt(_T_85)
node _T_87 = eq(_T_86, asSInt(UInt<1>(0h0)))
node _T_88 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_89 = cvt(_T_88)
node _T_90 = and(_T_89, asSInt(UInt<29>(0h10000000)))
node _T_91 = asSInt(_T_90)
node _T_92 = eq(_T_91, asSInt(UInt<1>(0h0)))
node _T_93 = or(_T_87, _T_92)
node _T_94 = and(_T_82, _T_93)
node _T_95 = or(UInt<1>(0h0), _T_80)
node _T_96 = or(_T_95, _T_94)
node _T_97 = and(_T_31, _T_96)
node _T_98 = asUInt(reset)
node _T_99 = eq(_T_98, UInt<1>(0h0))
when _T_99 :
node _T_100 = eq(_T_97, UInt<1>(0h0))
when _T_100 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_97, UInt<1>(0h1), "") : assert_2
node _T_101 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_102 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_103 = and(_T_101, _T_102)
node _T_104 = or(UInt<1>(0h0), _T_103)
node _T_105 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_106 = cvt(_T_105)
node _T_107 = and(_T_106, asSInt(UInt<14>(0h2000)))
node _T_108 = asSInt(_T_107)
node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0)))
node _T_110 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_116 = cvt(_T_115)
node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000)))
node _T_118 = asSInt(_T_117)
node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0)))
node _T_120 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_121 = cvt(_T_120)
node _T_122 = and(_T_121, asSInt(UInt<18>(0h2f000)))
node _T_123 = asSInt(_T_122)
node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0)))
node _T_125 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_126 = cvt(_T_125)
node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000)))
node _T_128 = asSInt(_T_127)
node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0)))
node _T_130 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_131 = cvt(_T_130)
node _T_132 = and(_T_131, asSInt(UInt<13>(0h1000)))
node _T_133 = asSInt(_T_132)
node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0)))
node _T_135 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_136 = cvt(_T_135)
node _T_137 = and(_T_136, asSInt(UInt<17>(0h10000)))
node _T_138 = asSInt(_T_137)
node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0)))
node _T_140 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_141 = cvt(_T_140)
node _T_142 = and(_T_141, asSInt(UInt<27>(0h4000000)))
node _T_143 = asSInt(_T_142)
node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0)))
node _T_145 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_146 = cvt(_T_145)
node _T_147 = and(_T_146, asSInt(UInt<13>(0h1000)))
node _T_148 = asSInt(_T_147)
node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0)))
node _T_150 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_151 = cvt(_T_150)
node _T_152 = and(_T_151, asSInt(UInt<29>(0h10000000)))
node _T_153 = asSInt(_T_152)
node _T_154 = eq(_T_153, asSInt(UInt<1>(0h0)))
node _T_155 = or(_T_109, _T_114)
node _T_156 = or(_T_155, _T_119)
node _T_157 = or(_T_156, _T_124)
node _T_158 = or(_T_157, _T_129)
node _T_159 = or(_T_158, _T_134)
node _T_160 = or(_T_159, _T_139)
node _T_161 = or(_T_160, _T_144)
node _T_162 = or(_T_161, _T_149)
node _T_163 = or(_T_162, _T_154)
node _T_164 = and(_T_104, _T_163)
node _T_165 = or(UInt<1>(0h0), _T_164)
node _T_166 = and(UInt<1>(0h0), _T_165)
node _T_167 = asUInt(reset)
node _T_168 = eq(_T_167, UInt<1>(0h0))
when _T_168 :
node _T_169 = eq(_T_166, UInt<1>(0h0))
when _T_169 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_166, UInt<1>(0h1), "") : assert_3
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_173 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_173, UInt<1>(0h1), "") : assert_5
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(is_aligned, UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_180 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_181 = asUInt(reset)
node _T_182 = eq(_T_181, UInt<1>(0h0))
when _T_182 :
node _T_183 = eq(_T_180, UInt<1>(0h0))
when _T_183 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_180, UInt<1>(0h1), "") : assert_7
node _T_184 = not(io.in.a.bits.mask)
node _T_185 = eq(_T_184, UInt<1>(0h0))
node _T_186 = asUInt(reset)
node _T_187 = eq(_T_186, UInt<1>(0h0))
when _T_187 :
node _T_188 = eq(_T_185, UInt<1>(0h0))
when _T_188 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_185, UInt<1>(0h1), "") : assert_8
node _T_189 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_190 = asUInt(reset)
node _T_191 = eq(_T_190, UInt<1>(0h0))
when _T_191 :
node _T_192 = eq(_T_189, UInt<1>(0h0))
when _T_192 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_189, UInt<1>(0h1), "") : assert_9
node _T_193 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_193 :
node _T_194 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_195 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_196 = and(_T_194, _T_195)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 4, 0)
node _T_197 = shr(io.in.a.bits.source, 5)
node _T_198 = eq(_T_197, UInt<1>(0h0))
node _T_199 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_200 = and(_T_198, _T_199)
node _T_201 = leq(uncommonBits_2, UInt<5>(0h1f))
node _T_202 = and(_T_200, _T_201)
node _T_203 = and(_T_196, _T_202)
node _T_204 = or(UInt<1>(0h0), _T_203)
node _T_205 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_206 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_207 = cvt(_T_206)
node _T_208 = and(_T_207, asSInt(UInt<14>(0h2000)))
node _T_209 = asSInt(_T_208)
node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0)))
node _T_211 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_217 = cvt(_T_216)
node _T_218 = and(_T_217, asSInt(UInt<17>(0h10000)))
node _T_219 = asSInt(_T_218)
node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0)))
node _T_221 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_222 = cvt(_T_221)
node _T_223 = and(_T_222, asSInt(UInt<18>(0h2f000)))
node _T_224 = asSInt(_T_223)
node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0)))
node _T_226 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_227 = cvt(_T_226)
node _T_228 = and(_T_227, asSInt(UInt<17>(0h10000)))
node _T_229 = asSInt(_T_228)
node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0)))
node _T_231 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_232 = cvt(_T_231)
node _T_233 = and(_T_232, asSInt(UInt<13>(0h1000)))
node _T_234 = asSInt(_T_233)
node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0)))
node _T_236 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_237 = cvt(_T_236)
node _T_238 = and(_T_237, asSInt(UInt<27>(0h4000000)))
node _T_239 = asSInt(_T_238)
node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0)))
node _T_241 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_242 = cvt(_T_241)
node _T_243 = and(_T_242, asSInt(UInt<13>(0h1000)))
node _T_244 = asSInt(_T_243)
node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0)))
node _T_246 = or(_T_210, _T_215)
node _T_247 = or(_T_246, _T_220)
node _T_248 = or(_T_247, _T_225)
node _T_249 = or(_T_248, _T_230)
node _T_250 = or(_T_249, _T_235)
node _T_251 = or(_T_250, _T_240)
node _T_252 = or(_T_251, _T_245)
node _T_253 = and(_T_205, _T_252)
node _T_254 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_255 = or(UInt<1>(0h0), _T_254)
node _T_256 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_257 = cvt(_T_256)
node _T_258 = and(_T_257, asSInt(UInt<17>(0h10000)))
node _T_259 = asSInt(_T_258)
node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0)))
node _T_261 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_262 = cvt(_T_261)
node _T_263 = and(_T_262, asSInt(UInt<29>(0h10000000)))
node _T_264 = asSInt(_T_263)
node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0)))
node _T_266 = or(_T_260, _T_265)
node _T_267 = and(_T_255, _T_266)
node _T_268 = or(UInt<1>(0h0), _T_253)
node _T_269 = or(_T_268, _T_267)
node _T_270 = and(_T_204, _T_269)
node _T_271 = asUInt(reset)
node _T_272 = eq(_T_271, UInt<1>(0h0))
when _T_272 :
node _T_273 = eq(_T_270, UInt<1>(0h0))
when _T_273 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_270, UInt<1>(0h1), "") : assert_10
node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_276 = and(_T_274, _T_275)
node _T_277 = or(UInt<1>(0h0), _T_276)
node _T_278 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_279 = cvt(_T_278)
node _T_280 = and(_T_279, asSInt(UInt<14>(0h2000)))
node _T_281 = asSInt(_T_280)
node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0)))
node _T_283 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_284 = cvt(_T_283)
node _T_285 = and(_T_284, asSInt(UInt<13>(0h1000)))
node _T_286 = asSInt(_T_285)
node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0)))
node _T_288 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_289 = cvt(_T_288)
node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000)))
node _T_291 = asSInt(_T_290)
node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0)))
node _T_293 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_294 = cvt(_T_293)
node _T_295 = and(_T_294, asSInt(UInt<18>(0h2f000)))
node _T_296 = asSInt(_T_295)
node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0)))
node _T_298 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_299 = cvt(_T_298)
node _T_300 = and(_T_299, asSInt(UInt<17>(0h10000)))
node _T_301 = asSInt(_T_300)
node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0)))
node _T_303 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_304 = cvt(_T_303)
node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000)))
node _T_306 = asSInt(_T_305)
node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0)))
node _T_308 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_309 = cvt(_T_308)
node _T_310 = and(_T_309, asSInt(UInt<17>(0h10000)))
node _T_311 = asSInt(_T_310)
node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0)))
node _T_313 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_314 = cvt(_T_313)
node _T_315 = and(_T_314, asSInt(UInt<27>(0h4000000)))
node _T_316 = asSInt(_T_315)
node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0)))
node _T_318 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_319 = cvt(_T_318)
node _T_320 = and(_T_319, asSInt(UInt<13>(0h1000)))
node _T_321 = asSInt(_T_320)
node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0)))
node _T_323 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_324 = cvt(_T_323)
node _T_325 = and(_T_324, asSInt(UInt<29>(0h10000000)))
node _T_326 = asSInt(_T_325)
node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0)))
node _T_328 = or(_T_282, _T_287)
node _T_329 = or(_T_328, _T_292)
node _T_330 = or(_T_329, _T_297)
node _T_331 = or(_T_330, _T_302)
node _T_332 = or(_T_331, _T_307)
node _T_333 = or(_T_332, _T_312)
node _T_334 = or(_T_333, _T_317)
node _T_335 = or(_T_334, _T_322)
node _T_336 = or(_T_335, _T_327)
node _T_337 = and(_T_277, _T_336)
node _T_338 = or(UInt<1>(0h0), _T_337)
node _T_339 = and(UInt<1>(0h0), _T_338)
node _T_340 = asUInt(reset)
node _T_341 = eq(_T_340, UInt<1>(0h0))
when _T_341 :
node _T_342 = eq(_T_339, UInt<1>(0h0))
when _T_342 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_339, UInt<1>(0h1), "") : assert_11
node _T_343 = asUInt(reset)
node _T_344 = eq(_T_343, UInt<1>(0h0))
when _T_344 :
node _T_345 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_345 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_346 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_347 = asUInt(reset)
node _T_348 = eq(_T_347, UInt<1>(0h0))
when _T_348 :
node _T_349 = eq(_T_346, UInt<1>(0h0))
when _T_349 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_346, UInt<1>(0h1), "") : assert_13
node _T_350 = asUInt(reset)
node _T_351 = eq(_T_350, UInt<1>(0h0))
when _T_351 :
node _T_352 = eq(is_aligned, UInt<1>(0h0))
when _T_352 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_353 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_354 = asUInt(reset)
node _T_355 = eq(_T_354, UInt<1>(0h0))
when _T_355 :
node _T_356 = eq(_T_353, UInt<1>(0h0))
when _T_356 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_353, UInt<1>(0h1), "") : assert_15
node _T_357 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_358 = asUInt(reset)
node _T_359 = eq(_T_358, UInt<1>(0h0))
when _T_359 :
node _T_360 = eq(_T_357, UInt<1>(0h0))
when _T_360 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_357, UInt<1>(0h1), "") : assert_16
node _T_361 = not(io.in.a.bits.mask)
node _T_362 = eq(_T_361, UInt<1>(0h0))
node _T_363 = asUInt(reset)
node _T_364 = eq(_T_363, UInt<1>(0h0))
when _T_364 :
node _T_365 = eq(_T_362, UInt<1>(0h0))
when _T_365 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_362, UInt<1>(0h1), "") : assert_17
node _T_366 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_T_366, UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_366, UInt<1>(0h1), "") : assert_18
node _T_370 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_370 :
node _T_371 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_372 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_373 = and(_T_371, _T_372)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 4, 0)
node _T_374 = shr(io.in.a.bits.source, 5)
node _T_375 = eq(_T_374, UInt<1>(0h0))
node _T_376 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_377 = and(_T_375, _T_376)
node _T_378 = leq(uncommonBits_3, UInt<5>(0h1f))
node _T_379 = and(_T_377, _T_378)
node _T_380 = and(_T_373, _T_379)
node _T_381 = or(UInt<1>(0h0), _T_380)
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(_T_381, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_381, UInt<1>(0h1), "") : assert_19
node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_386 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_387 = and(_T_385, _T_386)
node _T_388 = or(UInt<1>(0h0), _T_387)
node _T_389 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_390 = cvt(_T_389)
node _T_391 = and(_T_390, asSInt(UInt<13>(0h1000)))
node _T_392 = asSInt(_T_391)
node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0)))
node _T_394 = and(_T_388, _T_393)
node _T_395 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_396 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_397 = and(_T_395, _T_396)
node _T_398 = or(UInt<1>(0h0), _T_397)
node _T_399 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_400 = cvt(_T_399)
node _T_401 = and(_T_400, asSInt(UInt<14>(0h2000)))
node _T_402 = asSInt(_T_401)
node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0)))
node _T_404 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_405 = cvt(_T_404)
node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000)))
node _T_407 = asSInt(_T_406)
node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0)))
node _T_409 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_410 = cvt(_T_409)
node _T_411 = and(_T_410, asSInt(UInt<18>(0h2f000)))
node _T_412 = asSInt(_T_411)
node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0)))
node _T_414 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_415 = cvt(_T_414)
node _T_416 = and(_T_415, asSInt(UInt<17>(0h10000)))
node _T_417 = asSInt(_T_416)
node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0)))
node _T_419 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_420 = cvt(_T_419)
node _T_421 = and(_T_420, asSInt(UInt<13>(0h1000)))
node _T_422 = asSInt(_T_421)
node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0)))
node _T_424 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_425 = cvt(_T_424)
node _T_426 = and(_T_425, asSInt(UInt<17>(0h10000)))
node _T_427 = asSInt(_T_426)
node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0)))
node _T_429 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_430 = cvt(_T_429)
node _T_431 = and(_T_430, asSInt(UInt<27>(0h4000000)))
node _T_432 = asSInt(_T_431)
node _T_433 = eq(_T_432, asSInt(UInt<1>(0h0)))
node _T_434 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_435 = cvt(_T_434)
node _T_436 = and(_T_435, asSInt(UInt<13>(0h1000)))
node _T_437 = asSInt(_T_436)
node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0)))
node _T_439 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_440 = cvt(_T_439)
node _T_441 = and(_T_440, asSInt(UInt<29>(0h10000000)))
node _T_442 = asSInt(_T_441)
node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0)))
node _T_444 = or(_T_403, _T_408)
node _T_445 = or(_T_444, _T_413)
node _T_446 = or(_T_445, _T_418)
node _T_447 = or(_T_446, _T_423)
node _T_448 = or(_T_447, _T_428)
node _T_449 = or(_T_448, _T_433)
node _T_450 = or(_T_449, _T_438)
node _T_451 = or(_T_450, _T_443)
node _T_452 = and(_T_398, _T_451)
node _T_453 = or(UInt<1>(0h0), _T_394)
node _T_454 = or(_T_453, _T_452)
node _T_455 = asUInt(reset)
node _T_456 = eq(_T_455, UInt<1>(0h0))
when _T_456 :
node _T_457 = eq(_T_454, UInt<1>(0h0))
when _T_457 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_454, UInt<1>(0h1), "") : assert_20
node _T_458 = asUInt(reset)
node _T_459 = eq(_T_458, UInt<1>(0h0))
when _T_459 :
node _T_460 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(is_aligned, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_464 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_464, UInt<1>(0h1), "") : assert_23
node _T_468 = eq(io.in.a.bits.mask, mask)
node _T_469 = asUInt(reset)
node _T_470 = eq(_T_469, UInt<1>(0h0))
when _T_470 :
node _T_471 = eq(_T_468, UInt<1>(0h0))
when _T_471 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_468, UInt<1>(0h1), "") : assert_24
node _T_472 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_473 = asUInt(reset)
node _T_474 = eq(_T_473, UInt<1>(0h0))
when _T_474 :
node _T_475 = eq(_T_472, UInt<1>(0h0))
when _T_475 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_472, UInt<1>(0h1), "") : assert_25
node _T_476 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_476 :
node _T_477 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_478 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_479 = and(_T_477, _T_478)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0)
node _T_480 = shr(io.in.a.bits.source, 5)
node _T_481 = eq(_T_480, UInt<1>(0h0))
node _T_482 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_483 = and(_T_481, _T_482)
node _T_484 = leq(uncommonBits_4, UInt<5>(0h1f))
node _T_485 = and(_T_483, _T_484)
node _T_486 = and(_T_479, _T_485)
node _T_487 = or(UInt<1>(0h0), _T_486)
node _T_488 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_489 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_490 = and(_T_488, _T_489)
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_493 = cvt(_T_492)
node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000)))
node _T_495 = asSInt(_T_494)
node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0)))
node _T_497 = and(_T_491, _T_496)
node _T_498 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_499 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_500 = and(_T_498, _T_499)
node _T_501 = or(UInt<1>(0h0), _T_500)
node _T_502 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_503 = cvt(_T_502)
node _T_504 = and(_T_503, asSInt(UInt<14>(0h2000)))
node _T_505 = asSInt(_T_504)
node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0)))
node _T_507 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_508 = cvt(_T_507)
node _T_509 = and(_T_508, asSInt(UInt<18>(0h2f000)))
node _T_510 = asSInt(_T_509)
node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0)))
node _T_512 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_513 = cvt(_T_512)
node _T_514 = and(_T_513, asSInt(UInt<17>(0h10000)))
node _T_515 = asSInt(_T_514)
node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0)))
node _T_517 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_518 = cvt(_T_517)
node _T_519 = and(_T_518, asSInt(UInt<13>(0h1000)))
node _T_520 = asSInt(_T_519)
node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0)))
node _T_522 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_523 = cvt(_T_522)
node _T_524 = and(_T_523, asSInt(UInt<17>(0h10000)))
node _T_525 = asSInt(_T_524)
node _T_526 = eq(_T_525, asSInt(UInt<1>(0h0)))
node _T_527 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_528 = cvt(_T_527)
node _T_529 = and(_T_528, asSInt(UInt<27>(0h4000000)))
node _T_530 = asSInt(_T_529)
node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0)))
node _T_532 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_533 = cvt(_T_532)
node _T_534 = and(_T_533, asSInt(UInt<13>(0h1000)))
node _T_535 = asSInt(_T_534)
node _T_536 = eq(_T_535, asSInt(UInt<1>(0h0)))
node _T_537 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_538 = cvt(_T_537)
node _T_539 = and(_T_538, asSInt(UInt<29>(0h10000000)))
node _T_540 = asSInt(_T_539)
node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0)))
node _T_542 = or(_T_506, _T_511)
node _T_543 = or(_T_542, _T_516)
node _T_544 = or(_T_543, _T_521)
node _T_545 = or(_T_544, _T_526)
node _T_546 = or(_T_545, _T_531)
node _T_547 = or(_T_546, _T_536)
node _T_548 = or(_T_547, _T_541)
node _T_549 = and(_T_501, _T_548)
node _T_550 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_551 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_552 = cvt(_T_551)
node _T_553 = and(_T_552, asSInt(UInt<17>(0h10000)))
node _T_554 = asSInt(_T_553)
node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0)))
node _T_556 = and(_T_550, _T_555)
node _T_557 = or(UInt<1>(0h0), _T_497)
node _T_558 = or(_T_557, _T_549)
node _T_559 = or(_T_558, _T_556)
node _T_560 = and(_T_487, _T_559)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_560, UInt<1>(0h1), "") : assert_26
node _T_564 = asUInt(reset)
node _T_565 = eq(_T_564, UInt<1>(0h0))
when _T_565 :
node _T_566 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_566 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_567 = asUInt(reset)
node _T_568 = eq(_T_567, UInt<1>(0h0))
when _T_568 :
node _T_569 = eq(is_aligned, UInt<1>(0h0))
when _T_569 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_570 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_571 = asUInt(reset)
node _T_572 = eq(_T_571, UInt<1>(0h0))
when _T_572 :
node _T_573 = eq(_T_570, UInt<1>(0h0))
when _T_573 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_570, UInt<1>(0h1), "") : assert_29
node _T_574 = eq(io.in.a.bits.mask, mask)
node _T_575 = asUInt(reset)
node _T_576 = eq(_T_575, UInt<1>(0h0))
when _T_576 :
node _T_577 = eq(_T_574, UInt<1>(0h0))
when _T_577 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_574, UInt<1>(0h1), "") : assert_30
node _T_578 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_578 :
node _T_579 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_580 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_581 = and(_T_579, _T_580)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0)
node _T_582 = shr(io.in.a.bits.source, 5)
node _T_583 = eq(_T_582, UInt<1>(0h0))
node _T_584 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_585 = and(_T_583, _T_584)
node _T_586 = leq(uncommonBits_5, UInt<5>(0h1f))
node _T_587 = and(_T_585, _T_586)
node _T_588 = and(_T_581, _T_587)
node _T_589 = or(UInt<1>(0h0), _T_588)
node _T_590 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_591 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_592 = and(_T_590, _T_591)
node _T_593 = or(UInt<1>(0h0), _T_592)
node _T_594 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_595 = cvt(_T_594)
node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000)))
node _T_597 = asSInt(_T_596)
node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0)))
node _T_599 = and(_T_593, _T_598)
node _T_600 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_601 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_602 = and(_T_600, _T_601)
node _T_603 = or(UInt<1>(0h0), _T_602)
node _T_604 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_605 = cvt(_T_604)
node _T_606 = and(_T_605, asSInt(UInt<14>(0h2000)))
node _T_607 = asSInt(_T_606)
node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0)))
node _T_609 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_610 = cvt(_T_609)
node _T_611 = and(_T_610, asSInt(UInt<18>(0h2f000)))
node _T_612 = asSInt(_T_611)
node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0)))
node _T_614 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_615 = cvt(_T_614)
node _T_616 = and(_T_615, asSInt(UInt<17>(0h10000)))
node _T_617 = asSInt(_T_616)
node _T_618 = eq(_T_617, asSInt(UInt<1>(0h0)))
node _T_619 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_620 = cvt(_T_619)
node _T_621 = and(_T_620, asSInt(UInt<13>(0h1000)))
node _T_622 = asSInt(_T_621)
node _T_623 = eq(_T_622, asSInt(UInt<1>(0h0)))
node _T_624 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_625 = cvt(_T_624)
node _T_626 = and(_T_625, asSInt(UInt<17>(0h10000)))
node _T_627 = asSInt(_T_626)
node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0)))
node _T_629 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_630 = cvt(_T_629)
node _T_631 = and(_T_630, asSInt(UInt<27>(0h4000000)))
node _T_632 = asSInt(_T_631)
node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0)))
node _T_634 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_635 = cvt(_T_634)
node _T_636 = and(_T_635, asSInt(UInt<13>(0h1000)))
node _T_637 = asSInt(_T_636)
node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0)))
node _T_639 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_640 = cvt(_T_639)
node _T_641 = and(_T_640, asSInt(UInt<29>(0h10000000)))
node _T_642 = asSInt(_T_641)
node _T_643 = eq(_T_642, asSInt(UInt<1>(0h0)))
node _T_644 = or(_T_608, _T_613)
node _T_645 = or(_T_644, _T_618)
node _T_646 = or(_T_645, _T_623)
node _T_647 = or(_T_646, _T_628)
node _T_648 = or(_T_647, _T_633)
node _T_649 = or(_T_648, _T_638)
node _T_650 = or(_T_649, _T_643)
node _T_651 = and(_T_603, _T_650)
node _T_652 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_653 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_654 = cvt(_T_653)
node _T_655 = and(_T_654, asSInt(UInt<17>(0h10000)))
node _T_656 = asSInt(_T_655)
node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0)))
node _T_658 = and(_T_652, _T_657)
node _T_659 = or(UInt<1>(0h0), _T_599)
node _T_660 = or(_T_659, _T_651)
node _T_661 = or(_T_660, _T_658)
node _T_662 = and(_T_589, _T_661)
node _T_663 = asUInt(reset)
node _T_664 = eq(_T_663, UInt<1>(0h0))
when _T_664 :
node _T_665 = eq(_T_662, UInt<1>(0h0))
when _T_665 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_662, UInt<1>(0h1), "") : assert_31
node _T_666 = asUInt(reset)
node _T_667 = eq(_T_666, UInt<1>(0h0))
when _T_667 :
node _T_668 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_668 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_669 = asUInt(reset)
node _T_670 = eq(_T_669, UInt<1>(0h0))
when _T_670 :
node _T_671 = eq(is_aligned, UInt<1>(0h0))
when _T_671 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_672 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_673 = asUInt(reset)
node _T_674 = eq(_T_673, UInt<1>(0h0))
when _T_674 :
node _T_675 = eq(_T_672, UInt<1>(0h0))
when _T_675 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_672, UInt<1>(0h1), "") : assert_34
node _T_676 = not(mask)
node _T_677 = and(io.in.a.bits.mask, _T_676)
node _T_678 = eq(_T_677, UInt<1>(0h0))
node _T_679 = asUInt(reset)
node _T_680 = eq(_T_679, UInt<1>(0h0))
when _T_680 :
node _T_681 = eq(_T_678, UInt<1>(0h0))
when _T_681 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_678, UInt<1>(0h1), "") : assert_35
node _T_682 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_682 :
node _T_683 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_684 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_685 = and(_T_683, _T_684)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0)
node _T_686 = shr(io.in.a.bits.source, 5)
node _T_687 = eq(_T_686, UInt<1>(0h0))
node _T_688 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_689 = and(_T_687, _T_688)
node _T_690 = leq(uncommonBits_6, UInt<5>(0h1f))
node _T_691 = and(_T_689, _T_690)
node _T_692 = and(_T_685, _T_691)
node _T_693 = or(UInt<1>(0h0), _T_692)
node _T_694 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_695 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_696 = and(_T_694, _T_695)
node _T_697 = or(UInt<1>(0h0), _T_696)
node _T_698 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_699 = cvt(_T_698)
node _T_700 = and(_T_699, asSInt(UInt<14>(0h2000)))
node _T_701 = asSInt(_T_700)
node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0)))
node _T_703 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_704 = cvt(_T_703)
node _T_705 = and(_T_704, asSInt(UInt<13>(0h1000)))
node _T_706 = asSInt(_T_705)
node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0)))
node _T_708 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_709 = cvt(_T_708)
node _T_710 = and(_T_709, asSInt(UInt<18>(0h2f000)))
node _T_711 = asSInt(_T_710)
node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0)))
node _T_713 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_714 = cvt(_T_713)
node _T_715 = and(_T_714, asSInt(UInt<17>(0h10000)))
node _T_716 = asSInt(_T_715)
node _T_717 = eq(_T_716, asSInt(UInt<1>(0h0)))
node _T_718 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_719 = cvt(_T_718)
node _T_720 = and(_T_719, asSInt(UInt<13>(0h1000)))
node _T_721 = asSInt(_T_720)
node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0)))
node _T_723 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_724 = cvt(_T_723)
node _T_725 = and(_T_724, asSInt(UInt<17>(0h10000)))
node _T_726 = asSInt(_T_725)
node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0)))
node _T_728 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_729 = cvt(_T_728)
node _T_730 = and(_T_729, asSInt(UInt<27>(0h4000000)))
node _T_731 = asSInt(_T_730)
node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0)))
node _T_733 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_734 = cvt(_T_733)
node _T_735 = and(_T_734, asSInt(UInt<13>(0h1000)))
node _T_736 = asSInt(_T_735)
node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0)))
node _T_738 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_739 = cvt(_T_738)
node _T_740 = and(_T_739, asSInt(UInt<29>(0h10000000)))
node _T_741 = asSInt(_T_740)
node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0)))
node _T_743 = or(_T_702, _T_707)
node _T_744 = or(_T_743, _T_712)
node _T_745 = or(_T_744, _T_717)
node _T_746 = or(_T_745, _T_722)
node _T_747 = or(_T_746, _T_727)
node _T_748 = or(_T_747, _T_732)
node _T_749 = or(_T_748, _T_737)
node _T_750 = or(_T_749, _T_742)
node _T_751 = and(_T_697, _T_750)
node _T_752 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_753 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_754 = cvt(_T_753)
node _T_755 = and(_T_754, asSInt(UInt<17>(0h10000)))
node _T_756 = asSInt(_T_755)
node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0)))
node _T_758 = and(_T_752, _T_757)
node _T_759 = or(UInt<1>(0h0), _T_751)
node _T_760 = or(_T_759, _T_758)
node _T_761 = and(_T_693, _T_760)
node _T_762 = asUInt(reset)
node _T_763 = eq(_T_762, UInt<1>(0h0))
when _T_763 :
node _T_764 = eq(_T_761, UInt<1>(0h0))
when _T_764 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_761, UInt<1>(0h1), "") : assert_36
node _T_765 = asUInt(reset)
node _T_766 = eq(_T_765, UInt<1>(0h0))
when _T_766 :
node _T_767 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_767 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_768 = asUInt(reset)
node _T_769 = eq(_T_768, UInt<1>(0h0))
when _T_769 :
node _T_770 = eq(is_aligned, UInt<1>(0h0))
when _T_770 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_771 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_772 = asUInt(reset)
node _T_773 = eq(_T_772, UInt<1>(0h0))
when _T_773 :
node _T_774 = eq(_T_771, UInt<1>(0h0))
when _T_774 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_771, UInt<1>(0h1), "") : assert_39
node _T_775 = eq(io.in.a.bits.mask, mask)
node _T_776 = asUInt(reset)
node _T_777 = eq(_T_776, UInt<1>(0h0))
when _T_777 :
node _T_778 = eq(_T_775, UInt<1>(0h0))
when _T_778 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_775, UInt<1>(0h1), "") : assert_40
node _T_779 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_779 :
node _T_780 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_781 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_782 = and(_T_780, _T_781)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0)
node _T_783 = shr(io.in.a.bits.source, 5)
node _T_784 = eq(_T_783, UInt<1>(0h0))
node _T_785 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_786 = and(_T_784, _T_785)
node _T_787 = leq(uncommonBits_7, UInt<5>(0h1f))
node _T_788 = and(_T_786, _T_787)
node _T_789 = and(_T_782, _T_788)
node _T_790 = or(UInt<1>(0h0), _T_789)
node _T_791 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_792 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_793 = and(_T_791, _T_792)
node _T_794 = or(UInt<1>(0h0), _T_793)
node _T_795 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_796 = cvt(_T_795)
node _T_797 = and(_T_796, asSInt(UInt<14>(0h2000)))
node _T_798 = asSInt(_T_797)
node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0)))
node _T_800 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_801 = cvt(_T_800)
node _T_802 = and(_T_801, asSInt(UInt<13>(0h1000)))
node _T_803 = asSInt(_T_802)
node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0)))
node _T_805 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_806 = cvt(_T_805)
node _T_807 = and(_T_806, asSInt(UInt<18>(0h2f000)))
node _T_808 = asSInt(_T_807)
node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0)))
node _T_810 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_811 = cvt(_T_810)
node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000)))
node _T_813 = asSInt(_T_812)
node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0)))
node _T_815 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_816 = cvt(_T_815)
node _T_817 = and(_T_816, asSInt(UInt<13>(0h1000)))
node _T_818 = asSInt(_T_817)
node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0)))
node _T_820 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_821 = cvt(_T_820)
node _T_822 = and(_T_821, asSInt(UInt<17>(0h10000)))
node _T_823 = asSInt(_T_822)
node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0)))
node _T_825 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_826 = cvt(_T_825)
node _T_827 = and(_T_826, asSInt(UInt<27>(0h4000000)))
node _T_828 = asSInt(_T_827)
node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0)))
node _T_830 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_831 = cvt(_T_830)
node _T_832 = and(_T_831, asSInt(UInt<13>(0h1000)))
node _T_833 = asSInt(_T_832)
node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0)))
node _T_835 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_836 = cvt(_T_835)
node _T_837 = and(_T_836, asSInt(UInt<29>(0h10000000)))
node _T_838 = asSInt(_T_837)
node _T_839 = eq(_T_838, asSInt(UInt<1>(0h0)))
node _T_840 = or(_T_799, _T_804)
node _T_841 = or(_T_840, _T_809)
node _T_842 = or(_T_841, _T_814)
node _T_843 = or(_T_842, _T_819)
node _T_844 = or(_T_843, _T_824)
node _T_845 = or(_T_844, _T_829)
node _T_846 = or(_T_845, _T_834)
node _T_847 = or(_T_846, _T_839)
node _T_848 = and(_T_794, _T_847)
node _T_849 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_850 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_851 = cvt(_T_850)
node _T_852 = and(_T_851, asSInt(UInt<17>(0h10000)))
node _T_853 = asSInt(_T_852)
node _T_854 = eq(_T_853, asSInt(UInt<1>(0h0)))
node _T_855 = and(_T_849, _T_854)
node _T_856 = or(UInt<1>(0h0), _T_848)
node _T_857 = or(_T_856, _T_855)
node _T_858 = and(_T_790, _T_857)
node _T_859 = asUInt(reset)
node _T_860 = eq(_T_859, UInt<1>(0h0))
when _T_860 :
node _T_861 = eq(_T_858, UInt<1>(0h0))
when _T_861 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_858, UInt<1>(0h1), "") : assert_41
node _T_862 = asUInt(reset)
node _T_863 = eq(_T_862, UInt<1>(0h0))
when _T_863 :
node _T_864 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_864 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_865 = asUInt(reset)
node _T_866 = eq(_T_865, UInt<1>(0h0))
when _T_866 :
node _T_867 = eq(is_aligned, UInt<1>(0h0))
when _T_867 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_868 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_869 = asUInt(reset)
node _T_870 = eq(_T_869, UInt<1>(0h0))
when _T_870 :
node _T_871 = eq(_T_868, UInt<1>(0h0))
when _T_871 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_868, UInt<1>(0h1), "") : assert_44
node _T_872 = eq(io.in.a.bits.mask, mask)
node _T_873 = asUInt(reset)
node _T_874 = eq(_T_873, UInt<1>(0h0))
when _T_874 :
node _T_875 = eq(_T_872, UInt<1>(0h0))
when _T_875 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_872, UInt<1>(0h1), "") : assert_45
node _T_876 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_876 :
node _T_877 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_878 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_879 = and(_T_877, _T_878)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0)
node _T_880 = shr(io.in.a.bits.source, 5)
node _T_881 = eq(_T_880, UInt<1>(0h0))
node _T_882 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_883 = and(_T_881, _T_882)
node _T_884 = leq(uncommonBits_8, UInt<5>(0h1f))
node _T_885 = and(_T_883, _T_884)
node _T_886 = and(_T_879, _T_885)
node _T_887 = or(UInt<1>(0h0), _T_886)
node _T_888 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_889 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_890 = and(_T_888, _T_889)
node _T_891 = or(UInt<1>(0h0), _T_890)
node _T_892 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_893 = cvt(_T_892)
node _T_894 = and(_T_893, asSInt(UInt<13>(0h1000)))
node _T_895 = asSInt(_T_894)
node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0)))
node _T_897 = and(_T_891, _T_896)
node _T_898 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_899 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_900 = cvt(_T_899)
node _T_901 = and(_T_900, asSInt(UInt<14>(0h2000)))
node _T_902 = asSInt(_T_901)
node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0)))
node _T_904 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_905 = cvt(_T_904)
node _T_906 = and(_T_905, asSInt(UInt<17>(0h10000)))
node _T_907 = asSInt(_T_906)
node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0)))
node _T_909 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_910 = cvt(_T_909)
node _T_911 = and(_T_910, asSInt(UInt<18>(0h2f000)))
node _T_912 = asSInt(_T_911)
node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0)))
node _T_914 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_915 = cvt(_T_914)
node _T_916 = and(_T_915, asSInt(UInt<17>(0h10000)))
node _T_917 = asSInt(_T_916)
node _T_918 = eq(_T_917, asSInt(UInt<1>(0h0)))
node _T_919 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_920 = cvt(_T_919)
node _T_921 = and(_T_920, asSInt(UInt<13>(0h1000)))
node _T_922 = asSInt(_T_921)
node _T_923 = eq(_T_922, asSInt(UInt<1>(0h0)))
node _T_924 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_925 = cvt(_T_924)
node _T_926 = and(_T_925, asSInt(UInt<27>(0h4000000)))
node _T_927 = asSInt(_T_926)
node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0)))
node _T_929 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_930 = cvt(_T_929)
node _T_931 = and(_T_930, asSInt(UInt<13>(0h1000)))
node _T_932 = asSInt(_T_931)
node _T_933 = eq(_T_932, asSInt(UInt<1>(0h0)))
node _T_934 = or(_T_903, _T_908)
node _T_935 = or(_T_934, _T_913)
node _T_936 = or(_T_935, _T_918)
node _T_937 = or(_T_936, _T_923)
node _T_938 = or(_T_937, _T_928)
node _T_939 = or(_T_938, _T_933)
node _T_940 = and(_T_898, _T_939)
node _T_941 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_942 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_943 = and(_T_941, _T_942)
node _T_944 = or(UInt<1>(0h0), _T_943)
node _T_945 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_946 = cvt(_T_945)
node _T_947 = and(_T_946, asSInt(UInt<17>(0h10000)))
node _T_948 = asSInt(_T_947)
node _T_949 = eq(_T_948, asSInt(UInt<1>(0h0)))
node _T_950 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_951 = cvt(_T_950)
node _T_952 = and(_T_951, asSInt(UInt<29>(0h10000000)))
node _T_953 = asSInt(_T_952)
node _T_954 = eq(_T_953, asSInt(UInt<1>(0h0)))
node _T_955 = or(_T_949, _T_954)
node _T_956 = and(_T_944, _T_955)
node _T_957 = or(UInt<1>(0h0), _T_897)
node _T_958 = or(_T_957, _T_940)
node _T_959 = or(_T_958, _T_956)
node _T_960 = and(_T_887, _T_959)
node _T_961 = asUInt(reset)
node _T_962 = eq(_T_961, UInt<1>(0h0))
when _T_962 :
node _T_963 = eq(_T_960, UInt<1>(0h0))
when _T_963 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_960, UInt<1>(0h1), "") : assert_46
node _T_964 = asUInt(reset)
node _T_965 = eq(_T_964, UInt<1>(0h0))
when _T_965 :
node _T_966 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_966 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_967 = asUInt(reset)
node _T_968 = eq(_T_967, UInt<1>(0h0))
when _T_968 :
node _T_969 = eq(is_aligned, UInt<1>(0h0))
when _T_969 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_970 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_971 = asUInt(reset)
node _T_972 = eq(_T_971, UInt<1>(0h0))
when _T_972 :
node _T_973 = eq(_T_970, UInt<1>(0h0))
when _T_973 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_970, UInt<1>(0h1), "") : assert_49
node _T_974 = eq(io.in.a.bits.mask, mask)
node _T_975 = asUInt(reset)
node _T_976 = eq(_T_975, UInt<1>(0h0))
when _T_976 :
node _T_977 = eq(_T_974, UInt<1>(0h0))
when _T_977 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_974, UInt<1>(0h1), "") : assert_50
node _T_978 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_979 = asUInt(reset)
node _T_980 = eq(_T_979, UInt<1>(0h0))
when _T_980 :
node _T_981 = eq(_T_978, UInt<1>(0h0))
when _T_981 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_978, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_982 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_983 = asUInt(reset)
node _T_984 = eq(_T_983, UInt<1>(0h0))
when _T_984 :
node _T_985 = eq(_T_982, UInt<1>(0h0))
when _T_985 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_982, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 4, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 5)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<5>(0h1f))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8))
node _T_986 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_986 :
node _T_987 = asUInt(reset)
node _T_988 = eq(_T_987, UInt<1>(0h0))
when _T_988 :
node _T_989 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_989 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_990 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_991 = asUInt(reset)
node _T_992 = eq(_T_991, UInt<1>(0h0))
when _T_992 :
node _T_993 = eq(_T_990, UInt<1>(0h0))
when _T_993 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_990, UInt<1>(0h1), "") : assert_54
node _T_994 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_995 = asUInt(reset)
node _T_996 = eq(_T_995, UInt<1>(0h0))
when _T_996 :
node _T_997 = eq(_T_994, UInt<1>(0h0))
when _T_997 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_994, UInt<1>(0h1), "") : assert_55
node _T_998 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_999 = asUInt(reset)
node _T_1000 = eq(_T_999, UInt<1>(0h0))
when _T_1000 :
node _T_1001 = eq(_T_998, UInt<1>(0h0))
when _T_1001 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_998, UInt<1>(0h1), "") : assert_56
node _T_1002 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1003 = asUInt(reset)
node _T_1004 = eq(_T_1003, UInt<1>(0h0))
when _T_1004 :
node _T_1005 = eq(_T_1002, UInt<1>(0h0))
when _T_1005 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1002, UInt<1>(0h1), "") : assert_57
node _T_1006 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1006 :
node _T_1007 = asUInt(reset)
node _T_1008 = eq(_T_1007, UInt<1>(0h0))
when _T_1008 :
node _T_1009 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1009 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_1010 = asUInt(reset)
node _T_1011 = eq(_T_1010, UInt<1>(0h0))
when _T_1011 :
node _T_1012 = eq(sink_ok, UInt<1>(0h0))
when _T_1012 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1013 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1014 = asUInt(reset)
node _T_1015 = eq(_T_1014, UInt<1>(0h0))
when _T_1015 :
node _T_1016 = eq(_T_1013, UInt<1>(0h0))
when _T_1016 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1013, UInt<1>(0h1), "") : assert_60
node _T_1017 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1018 = asUInt(reset)
node _T_1019 = eq(_T_1018, UInt<1>(0h0))
when _T_1019 :
node _T_1020 = eq(_T_1017, UInt<1>(0h0))
when _T_1020 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1017, UInt<1>(0h1), "") : assert_61
node _T_1021 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1022 = asUInt(reset)
node _T_1023 = eq(_T_1022, UInt<1>(0h0))
when _T_1023 :
node _T_1024 = eq(_T_1021, UInt<1>(0h0))
when _T_1024 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1021, UInt<1>(0h1), "") : assert_62
node _T_1025 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1026 = asUInt(reset)
node _T_1027 = eq(_T_1026, UInt<1>(0h0))
when _T_1027 :
node _T_1028 = eq(_T_1025, UInt<1>(0h0))
when _T_1028 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1025, UInt<1>(0h1), "") : assert_63
node _T_1029 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1030 = or(UInt<1>(0h1), _T_1029)
node _T_1031 = asUInt(reset)
node _T_1032 = eq(_T_1031, UInt<1>(0h0))
when _T_1032 :
node _T_1033 = eq(_T_1030, UInt<1>(0h0))
when _T_1033 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1030, UInt<1>(0h1), "") : assert_64
node _T_1034 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1034 :
node _T_1035 = asUInt(reset)
node _T_1036 = eq(_T_1035, UInt<1>(0h0))
when _T_1036 :
node _T_1037 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1037 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_1038 = asUInt(reset)
node _T_1039 = eq(_T_1038, UInt<1>(0h0))
when _T_1039 :
node _T_1040 = eq(sink_ok, UInt<1>(0h0))
when _T_1040 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1041 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1042 = asUInt(reset)
node _T_1043 = eq(_T_1042, UInt<1>(0h0))
when _T_1043 :
node _T_1044 = eq(_T_1041, UInt<1>(0h0))
when _T_1044 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1041, UInt<1>(0h1), "") : assert_67
node _T_1045 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1046 = asUInt(reset)
node _T_1047 = eq(_T_1046, UInt<1>(0h0))
when _T_1047 :
node _T_1048 = eq(_T_1045, UInt<1>(0h0))
when _T_1048 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1045, UInt<1>(0h1), "") : assert_68
node _T_1049 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1050 = asUInt(reset)
node _T_1051 = eq(_T_1050, UInt<1>(0h0))
when _T_1051 :
node _T_1052 = eq(_T_1049, UInt<1>(0h0))
when _T_1052 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1049, UInt<1>(0h1), "") : assert_69
node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1054 = or(_T_1053, io.in.d.bits.corrupt)
node _T_1055 = asUInt(reset)
node _T_1056 = eq(_T_1055, UInt<1>(0h0))
when _T_1056 :
node _T_1057 = eq(_T_1054, UInt<1>(0h0))
when _T_1057 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1054, UInt<1>(0h1), "") : assert_70
node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1059 = or(UInt<1>(0h1), _T_1058)
node _T_1060 = asUInt(reset)
node _T_1061 = eq(_T_1060, UInt<1>(0h0))
when _T_1061 :
node _T_1062 = eq(_T_1059, UInt<1>(0h0))
when _T_1062 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1059, UInt<1>(0h1), "") : assert_71
node _T_1063 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1063 :
node _T_1064 = asUInt(reset)
node _T_1065 = eq(_T_1064, UInt<1>(0h0))
when _T_1065 :
node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1066 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1068 = asUInt(reset)
node _T_1069 = eq(_T_1068, UInt<1>(0h0))
when _T_1069 :
node _T_1070 = eq(_T_1067, UInt<1>(0h0))
when _T_1070 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1067, UInt<1>(0h1), "") : assert_73
node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1072 = asUInt(reset)
node _T_1073 = eq(_T_1072, UInt<1>(0h0))
when _T_1073 :
node _T_1074 = eq(_T_1071, UInt<1>(0h0))
when _T_1074 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1071, UInt<1>(0h1), "") : assert_74
node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1076 = or(UInt<1>(0h1), _T_1075)
node _T_1077 = asUInt(reset)
node _T_1078 = eq(_T_1077, UInt<1>(0h0))
when _T_1078 :
node _T_1079 = eq(_T_1076, UInt<1>(0h0))
when _T_1079 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1076, UInt<1>(0h1), "") : assert_75
node _T_1080 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1080 :
node _T_1081 = asUInt(reset)
node _T_1082 = eq(_T_1081, UInt<1>(0h0))
when _T_1082 :
node _T_1083 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1083 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_1084 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1085 = asUInt(reset)
node _T_1086 = eq(_T_1085, UInt<1>(0h0))
when _T_1086 :
node _T_1087 = eq(_T_1084, UInt<1>(0h0))
when _T_1087 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1084, UInt<1>(0h1), "") : assert_77
node _T_1088 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1089 = or(_T_1088, io.in.d.bits.corrupt)
node _T_1090 = asUInt(reset)
node _T_1091 = eq(_T_1090, UInt<1>(0h0))
when _T_1091 :
node _T_1092 = eq(_T_1089, UInt<1>(0h0))
when _T_1092 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1089, UInt<1>(0h1), "") : assert_78
node _T_1093 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1094 = or(UInt<1>(0h1), _T_1093)
node _T_1095 = asUInt(reset)
node _T_1096 = eq(_T_1095, UInt<1>(0h0))
when _T_1096 :
node _T_1097 = eq(_T_1094, UInt<1>(0h0))
when _T_1097 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1094, UInt<1>(0h1), "") : assert_79
node _T_1098 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1098 :
node _T_1099 = asUInt(reset)
node _T_1100 = eq(_T_1099, UInt<1>(0h0))
when _T_1100 :
node _T_1101 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1101 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_1102 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1103 = asUInt(reset)
node _T_1104 = eq(_T_1103, UInt<1>(0h0))
when _T_1104 :
node _T_1105 = eq(_T_1102, UInt<1>(0h0))
when _T_1105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1102, UInt<1>(0h1), "") : assert_81
node _T_1106 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1107 = asUInt(reset)
node _T_1108 = eq(_T_1107, UInt<1>(0h0))
when _T_1108 :
node _T_1109 = eq(_T_1106, UInt<1>(0h0))
when _T_1109 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1106, UInt<1>(0h1), "") : assert_82
node _T_1110 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1111 = or(UInt<1>(0h1), _T_1110)
node _T_1112 = asUInt(reset)
node _T_1113 = eq(_T_1112, UInt<1>(0h0))
when _T_1113 :
node _T_1114 = eq(_T_1111, UInt<1>(0h0))
when _T_1114 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1111, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<5>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1115 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1116 = asUInt(reset)
node _T_1117 = eq(_T_1116, UInt<1>(0h0))
when _T_1117 :
node _T_1118 = eq(_T_1115, UInt<1>(0h0))
when _T_1118 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1115, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<5>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1119 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1120 = asUInt(reset)
node _T_1121 = eq(_T_1120, UInt<1>(0h0))
when _T_1121 :
node _T_1122 = eq(_T_1119, UInt<1>(0h0))
when _T_1122 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1119, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_4.bits.sink, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1123 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1124 = asUInt(reset)
node _T_1125 = eq(_T_1124, UInt<1>(0h0))
when _T_1125 :
node _T_1126 = eq(_T_1123, UInt<1>(0h0))
when _T_1126 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1123, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1127 = eq(a_first, UInt<1>(0h0))
node _T_1128 = and(io.in.a.valid, _T_1127)
when _T_1128 :
node _T_1129 = eq(io.in.a.bits.opcode, opcode)
node _T_1130 = asUInt(reset)
node _T_1131 = eq(_T_1130, UInt<1>(0h0))
when _T_1131 :
node _T_1132 = eq(_T_1129, UInt<1>(0h0))
when _T_1132 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1129, UInt<1>(0h1), "") : assert_87
node _T_1133 = eq(io.in.a.bits.param, param)
node _T_1134 = asUInt(reset)
node _T_1135 = eq(_T_1134, UInt<1>(0h0))
when _T_1135 :
node _T_1136 = eq(_T_1133, UInt<1>(0h0))
when _T_1136 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1133, UInt<1>(0h1), "") : assert_88
node _T_1137 = eq(io.in.a.bits.size, size)
node _T_1138 = asUInt(reset)
node _T_1139 = eq(_T_1138, UInt<1>(0h0))
when _T_1139 :
node _T_1140 = eq(_T_1137, UInt<1>(0h0))
when _T_1140 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1137, UInt<1>(0h1), "") : assert_89
node _T_1141 = eq(io.in.a.bits.source, source)
node _T_1142 = asUInt(reset)
node _T_1143 = eq(_T_1142, UInt<1>(0h0))
when _T_1143 :
node _T_1144 = eq(_T_1141, UInt<1>(0h0))
when _T_1144 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1141, UInt<1>(0h1), "") : assert_90
node _T_1145 = eq(io.in.a.bits.address, address)
node _T_1146 = asUInt(reset)
node _T_1147 = eq(_T_1146, UInt<1>(0h0))
when _T_1147 :
node _T_1148 = eq(_T_1145, UInt<1>(0h0))
when _T_1148 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1145, UInt<1>(0h1), "") : assert_91
node _T_1149 = and(io.in.a.ready, io.in.a.valid)
node _T_1150 = and(_T_1149, a_first)
when _T_1150 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1151 = eq(d_first, UInt<1>(0h0))
node _T_1152 = and(io.in.d.valid, _T_1151)
when _T_1152 :
node _T_1153 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1154 = asUInt(reset)
node _T_1155 = eq(_T_1154, UInt<1>(0h0))
when _T_1155 :
node _T_1156 = eq(_T_1153, UInt<1>(0h0))
when _T_1156 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1153, UInt<1>(0h1), "") : assert_92
node _T_1157 = eq(io.in.d.bits.param, param_1)
node _T_1158 = asUInt(reset)
node _T_1159 = eq(_T_1158, UInt<1>(0h0))
when _T_1159 :
node _T_1160 = eq(_T_1157, UInt<1>(0h0))
when _T_1160 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1157, UInt<1>(0h1), "") : assert_93
node _T_1161 = eq(io.in.d.bits.size, size_1)
node _T_1162 = asUInt(reset)
node _T_1163 = eq(_T_1162, UInt<1>(0h0))
when _T_1163 :
node _T_1164 = eq(_T_1161, UInt<1>(0h0))
when _T_1164 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1161, UInt<1>(0h1), "") : assert_94
node _T_1165 = eq(io.in.d.bits.source, source_1)
node _T_1166 = asUInt(reset)
node _T_1167 = eq(_T_1166, UInt<1>(0h0))
when _T_1167 :
node _T_1168 = eq(_T_1165, UInt<1>(0h0))
when _T_1168 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1165, UInt<1>(0h1), "") : assert_95
node _T_1169 = eq(io.in.d.bits.sink, sink)
node _T_1170 = asUInt(reset)
node _T_1171 = eq(_T_1170, UInt<1>(0h0))
when _T_1171 :
node _T_1172 = eq(_T_1169, UInt<1>(0h0))
when _T_1172 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1169, UInt<1>(0h1), "") : assert_96
node _T_1173 = eq(io.in.d.bits.denied, denied)
node _T_1174 = asUInt(reset)
node _T_1175 = eq(_T_1174, UInt<1>(0h0))
when _T_1175 :
node _T_1176 = eq(_T_1173, UInt<1>(0h0))
when _T_1176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1173, UInt<1>(0h1), "") : assert_97
node _T_1177 = and(io.in.d.ready, io.in.d.valid)
node _T_1178 = and(_T_1177, d_first)
when _T_1178 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<32>, clock, reset, UInt<32>(0h0)
regreset inflight_opcodes : UInt<128>, clock, reset, UInt<128>(0h0)
regreset inflight_sizes : UInt<256>, clock, reset, UInt<256>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<32>
connect a_set, UInt<32>(0h0)
wire a_set_wo_ready : UInt<32>
connect a_set_wo_ready, UInt<32>(0h0)
wire a_opcodes_set : UInt<128>
connect a_opcodes_set, UInt<128>(0h0)
wire a_sizes_set : UInt<256>
connect a_sizes_set, UInt<256>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1179 = and(io.in.a.valid, a_first_1)
node _T_1180 = and(_T_1179, UInt<1>(0h1))
when _T_1180 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1181 = and(io.in.a.ready, io.in.a.valid)
node _T_1182 = and(_T_1181, a_first_1)
node _T_1183 = and(_T_1182, UInt<1>(0h1))
when _T_1183 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1184 = dshr(inflight, io.in.a.bits.source)
node _T_1185 = bits(_T_1184, 0, 0)
node _T_1186 = eq(_T_1185, UInt<1>(0h0))
node _T_1187 = asUInt(reset)
node _T_1188 = eq(_T_1187, UInt<1>(0h0))
when _T_1188 :
node _T_1189 = eq(_T_1186, UInt<1>(0h0))
when _T_1189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1186, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<32>
connect d_clr, UInt<32>(0h0)
wire d_clr_wo_ready : UInt<32>
connect d_clr_wo_ready, UInt<32>(0h0)
wire d_opcodes_clr : UInt<128>
connect d_opcodes_clr, UInt<128>(0h0)
wire d_sizes_clr : UInt<256>
connect d_sizes_clr, UInt<256>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1190 = and(io.in.d.valid, d_first_1)
node _T_1191 = and(_T_1190, UInt<1>(0h1))
node _T_1192 = eq(d_release_ack, UInt<1>(0h0))
node _T_1193 = and(_T_1191, _T_1192)
when _T_1193 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1194 = and(io.in.d.ready, io.in.d.valid)
node _T_1195 = and(_T_1194, d_first_1)
node _T_1196 = and(_T_1195, UInt<1>(0h1))
node _T_1197 = eq(d_release_ack, UInt<1>(0h0))
node _T_1198 = and(_T_1196, _T_1197)
when _T_1198 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1199 = and(io.in.d.valid, d_first_1)
node _T_1200 = and(_T_1199, UInt<1>(0h1))
node _T_1201 = eq(d_release_ack, UInt<1>(0h0))
node _T_1202 = and(_T_1200, _T_1201)
when _T_1202 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1203 = dshr(inflight, io.in.d.bits.source)
node _T_1204 = bits(_T_1203, 0, 0)
node _T_1205 = or(_T_1204, same_cycle_resp)
node _T_1206 = asUInt(reset)
node _T_1207 = eq(_T_1206, UInt<1>(0h0))
when _T_1207 :
node _T_1208 = eq(_T_1205, UInt<1>(0h0))
when _T_1208 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1205, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1209 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1210 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1211 = or(_T_1209, _T_1210)
node _T_1212 = asUInt(reset)
node _T_1213 = eq(_T_1212, UInt<1>(0h0))
when _T_1213 :
node _T_1214 = eq(_T_1211, UInt<1>(0h0))
when _T_1214 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1211, UInt<1>(0h1), "") : assert_100
node _T_1215 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1216 = asUInt(reset)
node _T_1217 = eq(_T_1216, UInt<1>(0h0))
when _T_1217 :
node _T_1218 = eq(_T_1215, UInt<1>(0h0))
when _T_1218 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1215, UInt<1>(0h1), "") : assert_101
else :
node _T_1219 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1220 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1221 = or(_T_1219, _T_1220)
node _T_1222 = asUInt(reset)
node _T_1223 = eq(_T_1222, UInt<1>(0h0))
when _T_1223 :
node _T_1224 = eq(_T_1221, UInt<1>(0h0))
when _T_1224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1221, UInt<1>(0h1), "") : assert_102
node _T_1225 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1226 = asUInt(reset)
node _T_1227 = eq(_T_1226, UInt<1>(0h0))
when _T_1227 :
node _T_1228 = eq(_T_1225, UInt<1>(0h0))
when _T_1228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1225, UInt<1>(0h1), "") : assert_103
node _T_1229 = and(io.in.d.valid, d_first_1)
node _T_1230 = and(_T_1229, a_first_1)
node _T_1231 = and(_T_1230, io.in.a.valid)
node _T_1232 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1233 = and(_T_1231, _T_1232)
node _T_1234 = eq(d_release_ack, UInt<1>(0h0))
node _T_1235 = and(_T_1233, _T_1234)
when _T_1235 :
node _T_1236 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1237 = or(_T_1236, io.in.a.ready)
node _T_1238 = asUInt(reset)
node _T_1239 = eq(_T_1238, UInt<1>(0h0))
when _T_1239 :
node _T_1240 = eq(_T_1237, UInt<1>(0h0))
when _T_1240 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1237, UInt<1>(0h1), "") : assert_104
node _T_1241 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1242 = orr(a_set_wo_ready)
node _T_1243 = eq(_T_1242, UInt<1>(0h0))
node _T_1244 = or(_T_1241, _T_1243)
node _T_1245 = asUInt(reset)
node _T_1246 = eq(_T_1245, UInt<1>(0h0))
when _T_1246 :
node _T_1247 = eq(_T_1244, UInt<1>(0h0))
when _T_1247 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1244, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_34
node _T_1248 = orr(inflight)
node _T_1249 = eq(_T_1248, UInt<1>(0h0))
node _T_1250 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1251 = or(_T_1249, _T_1250)
node _T_1252 = lt(watchdog, plusarg_reader.out)
node _T_1253 = or(_T_1251, _T_1252)
node _T_1254 = asUInt(reset)
node _T_1255 = eq(_T_1254, UInt<1>(0h0))
when _T_1255 :
node _T_1256 = eq(_T_1253, UInt<1>(0h0))
when _T_1256 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1253, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1257 = and(io.in.a.ready, io.in.a.valid)
node _T_1258 = and(io.in.d.ready, io.in.d.valid)
node _T_1259 = or(_T_1257, _T_1258)
when _T_1259 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<32>, clock, reset, UInt<32>(0h0)
regreset inflight_opcodes_1 : UInt<128>, clock, reset, UInt<128>(0h0)
regreset inflight_sizes_1 : UInt<256>, clock, reset, UInt<256>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<5>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<5>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<32>
connect c_set, UInt<32>(0h0)
wire c_set_wo_ready : UInt<32>
connect c_set_wo_ready, UInt<32>(0h0)
wire c_opcodes_set : UInt<128>
connect c_opcodes_set, UInt<128>(0h0)
wire c_sizes_set : UInt<256>
connect c_sizes_set, UInt<256>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<5>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1260 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<5>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1261 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1262 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1263 = and(_T_1261, _T_1262)
node _T_1264 = and(_T_1260, _T_1263)
when _T_1264 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<5>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1265 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1266 = and(_T_1265, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<5>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1267 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1268 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1269 = and(_T_1267, _T_1268)
node _T_1270 = and(_T_1266, _T_1269)
when _T_1270 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<5>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1271 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1272 = bits(_T_1271, 0, 0)
node _T_1273 = eq(_T_1272, UInt<1>(0h0))
node _T_1274 = asUInt(reset)
node _T_1275 = eq(_T_1274, UInt<1>(0h0))
when _T_1275 :
node _T_1276 = eq(_T_1273, UInt<1>(0h0))
when _T_1276 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1273, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<32>
connect d_clr_1, UInt<32>(0h0)
wire d_clr_wo_ready_1 : UInt<32>
connect d_clr_wo_ready_1, UInt<32>(0h0)
wire d_opcodes_clr_1 : UInt<128>
connect d_opcodes_clr_1, UInt<128>(0h0)
wire d_sizes_clr_1 : UInt<256>
connect d_sizes_clr_1, UInt<256>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1277 = and(io.in.d.valid, d_first_2)
node _T_1278 = and(_T_1277, UInt<1>(0h1))
node _T_1279 = and(_T_1278, d_release_ack_1)
when _T_1279 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1280 = and(io.in.d.ready, io.in.d.valid)
node _T_1281 = and(_T_1280, d_first_2)
node _T_1282 = and(_T_1281, UInt<1>(0h1))
node _T_1283 = and(_T_1282, d_release_ack_1)
when _T_1283 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1284 = and(io.in.d.valid, d_first_2)
node _T_1285 = and(_T_1284, UInt<1>(0h1))
node _T_1286 = and(_T_1285, d_release_ack_1)
when _T_1286 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1287 = dshr(inflight_1, io.in.d.bits.source)
node _T_1288 = bits(_T_1287, 0, 0)
node _T_1289 = or(_T_1288, same_cycle_resp_1)
node _T_1290 = asUInt(reset)
node _T_1291 = eq(_T_1290, UInt<1>(0h0))
when _T_1291 :
node _T_1292 = eq(_T_1289, UInt<1>(0h0))
when _T_1292 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1289, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<5>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1293 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1294 = asUInt(reset)
node _T_1295 = eq(_T_1294, UInt<1>(0h0))
when _T_1295 :
node _T_1296 = eq(_T_1293, UInt<1>(0h0))
when _T_1296 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1293, UInt<1>(0h1), "") : assert_109
else :
node _T_1297 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1298 = asUInt(reset)
node _T_1299 = eq(_T_1298, UInt<1>(0h0))
when _T_1299 :
node _T_1300 = eq(_T_1297, UInt<1>(0h0))
when _T_1300 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1297, UInt<1>(0h1), "") : assert_110
node _T_1301 = and(io.in.d.valid, d_first_2)
node _T_1302 = and(_T_1301, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<5>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1303 = and(_T_1302, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<5>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1304 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1305 = and(_T_1303, _T_1304)
node _T_1306 = and(_T_1305, d_release_ack_1)
node _T_1307 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1308 = and(_T_1306, _T_1307)
when _T_1308 :
node _T_1309 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<5>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1310 = or(_T_1309, _WIRE_23.ready)
node _T_1311 = asUInt(reset)
node _T_1312 = eq(_T_1311, UInt<1>(0h0))
when _T_1312 :
node _T_1313 = eq(_T_1310, UInt<1>(0h0))
when _T_1313 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1310, UInt<1>(0h1), "") : assert_111
node _T_1314 = orr(c_set_wo_ready)
when _T_1314 :
node _T_1315 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1316 = asUInt(reset)
node _T_1317 = eq(_T_1316, UInt<1>(0h0))
when _T_1317 :
node _T_1318 = eq(_T_1315, UInt<1>(0h0))
when _T_1318 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1315, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_35
node _T_1319 = orr(inflight_1)
node _T_1320 = eq(_T_1319, UInt<1>(0h0))
node _T_1321 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1322 = or(_T_1320, _T_1321)
node _T_1323 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1324 = or(_T_1322, _T_1323)
node _T_1325 = asUInt(reset)
node _T_1326 = eq(_T_1325, UInt<1>(0h0))
when _T_1326 :
node _T_1327 = eq(_T_1324, UInt<1>(0h0))
when _T_1327 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1324, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<5>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1328 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1329 = and(io.in.d.ready, io.in.d.valid)
node _T_1330 = or(_T_1328, _T_1329)
when _T_1330 :
connect watchdog_1, UInt<1>(0h0)
extmodule plusarg_reader_36 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_37 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor_17( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:56:48]
wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:48]
wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] c_set = 32'h0; // @[Monitor.scala:738:34]
wire [31:0] c_set_wo_ready = 32'h0; // @[Monitor.scala:739:34]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52]
wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79]
wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77]
wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35]
wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35]
wire [255:0] c_sizes_set = 256'h0; // @[Monitor.scala:741:34]
wire [127:0] c_opcodes_set = 128'h0; // @[Monitor.scala:740:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _T_1257 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1257; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1257; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [4:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1330 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1330; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1330; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1330; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [4:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [31:0] inflight; // @[Monitor.scala:614:27]
reg [127:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [255:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [31:0] a_set; // @[Monitor.scala:626:34]
wire [31:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [127:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [255:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [127:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [127:0] _a_opcode_lookup_T_6 = {124'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [127:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [255:0] _a_size_lookup_T_6 = {248'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[255:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [31:0] _GEN_3 = {27'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35]
wire [31:0] _GEN_4 = 32'h1 << _GEN_3; // @[OneHot.scala:58:35]
wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [31:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 32'h0; // @[OneHot.scala:58:35]
wire _T_1183 = _T_1257 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1183 ? _a_set_T : 32'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1183 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1183 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1183 ? _a_opcodes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1183 ? _a_sizes_set_T_1[255:0] : 256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [31:0] d_clr; // @[Monitor.scala:664:34]
wire [31:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [127:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [255:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46]
wire _T_1229 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [31:0] _GEN_6 = {27'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [31:0] _GEN_7 = 32'h1 << _GEN_6; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1229 & ~d_release_ack ? _d_clr_wo_ready_T : 32'h0; // @[OneHot.scala:58:35]
wire _T_1198 = _T_1330 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1198 ? _d_clr_T : 32'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1198 ? _d_opcodes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1198 ? _d_sizes_clr_T_5[255:0] : 256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [31:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [31:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [31:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [127:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [127:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [127:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [255:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [31:0] inflight_1; // @[Monitor.scala:726:35]
wire [31:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [127:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [127:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [255:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [127:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [127:0] _c_opcode_lookup_T_6 = {124'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [127:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [255:0] _c_size_lookup_T_6 = {248'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[255:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [31:0] d_clr_1; // @[Monitor.scala:774:34]
wire [31:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [127:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [255:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1301 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1301 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 32'h0; // @[OneHot.scala:58:35]
wire _T_1283 = _T_1330 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1283 ? _d_clr_T_1 : 32'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1283 ? _d_opcodes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1283 ? _d_sizes_clr_T_11[255:0] : 256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113]
wire [31:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [31:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [127:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [127:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module LoopBranchPredictorColumn_3 :
input clock : Clock
input reset : Reset
output io : { flip f2_req_valid : UInt<1>, flip f2_req_idx : UInt, flip f3_req_fire : UInt<1>, flip f3_pred_in : UInt<1>, f3_pred : UInt<1>, f3_meta : { s_cnt : UInt<10>}, flip update_mispredict : UInt<1>, flip update_repair : UInt<1>, flip update_idx : UInt, flip update_resolve_dir : UInt<1>, flip update_meta : { s_cnt : UInt<10>}}
regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1)
regreset reset_idx : UInt<4>, clock, reset, UInt<4>(0h0)
node _reset_idx_T = add(reset_idx, doing_reset)
node _reset_idx_T_1 = tail(_reset_idx_T, 1)
connect reset_idx, _reset_idx_T_1
node _T = eq(reset_idx, UInt<4>(0hf))
when _T :
connect doing_reset, UInt<1>(0h0)
reg entries : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}[16], clock
node _f2_entry_T = or(io.f2_req_idx, UInt<4>(0h0))
node _f2_entry_T_1 = bits(_f2_entry_T, 3, 0)
wire f2_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}
connect f2_entry, entries[_f2_entry_T_1]
node _T_1 = eq(io.update_idx, io.f2_req_idx)
node _T_2 = and(io.update_repair, _T_1)
when _T_2 :
connect f2_entry.s_cnt, io.update_meta.s_cnt
else :
node _T_3 = eq(io.update_idx, io.f2_req_idx)
node _T_4 = and(io.update_mispredict, _T_3)
when _T_4 :
connect f2_entry.s_cnt, UInt<1>(0h0)
reg f3_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}, clock
connect f3_entry, f2_entry
reg f3_scnt_REG : UInt, clock
connect f3_scnt_REG, io.f2_req_idx
node _f3_scnt_T = eq(io.update_idx, f3_scnt_REG)
node _f3_scnt_T_1 = and(io.update_repair, _f3_scnt_T)
node f3_scnt = mux(_f3_scnt_T_1, io.update_meta.s_cnt, f3_entry.s_cnt)
node _f3_tag_T = bits(io.f2_req_idx, 13, 4)
reg f3_tag : UInt, clock
connect f3_tag, _f3_tag_T
connect io.f3_pred, io.f3_pred_in
connect io.f3_meta.s_cnt, f3_scnt
node _T_5 = eq(f3_entry.tag, f3_tag)
when _T_5 :
node _T_6 = eq(f3_scnt, f3_entry.p_cnt)
node _T_7 = eq(f3_entry.conf, UInt<3>(0h7))
node _T_8 = and(_T_6, _T_7)
when _T_8 :
node _io_f3_pred_T = eq(io.f3_pred_in, UInt<1>(0h0))
connect io.f3_pred, _io_f3_pred_T
reg f4_fire : UInt<1>, clock
connect f4_fire, io.f3_req_fire
reg f4_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}, clock
connect f4_entry, f3_entry
reg f4_tag : UInt, clock
connect f4_tag, f3_tag
reg f4_scnt : UInt, clock
connect f4_scnt, f3_scnt
reg f4_idx_REG : UInt, clock
connect f4_idx_REG, io.f2_req_idx
reg f4_idx : UInt, clock
connect f4_idx, f4_idx_REG
when f4_fire :
node _T_9 = eq(f4_entry.tag, f4_tag)
when _T_9 :
node _T_10 = eq(f4_scnt, f4_entry.p_cnt)
node _T_11 = eq(f4_entry.conf, UInt<3>(0h7))
node _T_12 = and(_T_10, _T_11)
when _T_12 :
node _T_13 = or(f4_idx, UInt<4>(0h0))
node _T_14 = bits(_T_13, 3, 0)
connect entries[_T_14].age, UInt<3>(0h7)
node _T_15 = or(f4_idx, UInt<4>(0h0))
node _T_16 = bits(_T_15, 3, 0)
connect entries[_T_16].s_cnt, UInt<1>(0h0)
else :
node _T_17 = or(f4_idx, UInt<4>(0h0))
node _T_18 = bits(_T_17, 3, 0)
node _entries_s_cnt_T = add(f4_scnt, UInt<1>(0h1))
node _entries_s_cnt_T_1 = tail(_entries_s_cnt_T, 1)
connect entries[_T_18].s_cnt, _entries_s_cnt_T_1
node _T_19 = or(f4_idx, UInt<4>(0h0))
node _T_20 = bits(_T_19, 3, 0)
node _entries_age_T = eq(f4_entry.age, UInt<3>(0h7))
node _entries_age_T_1 = add(f4_entry.age, UInt<1>(0h1))
node _entries_age_T_2 = tail(_entries_age_T_1, 1)
node _entries_age_T_3 = mux(_entries_age_T, UInt<3>(0h7), _entries_age_T_2)
connect entries[_T_20].age, _entries_age_T_3
node _entry_T = or(io.update_idx, UInt<4>(0h0))
node _entry_T_1 = bits(_entry_T, 3, 0)
node tag = bits(io.update_idx, 13, 4)
node tag_match = eq(entries[_entry_T_1].tag, tag)
node ctr_match = eq(entries[_entry_T_1].p_cnt, io.update_meta.s_cnt)
wire wentry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}
connect wentry, entries[_entry_T_1]
node _T_21 = eq(doing_reset, UInt<1>(0h0))
node _T_22 = and(io.update_mispredict, _T_21)
when _T_22 :
node _T_23 = eq(entries[_entry_T_1].conf, UInt<3>(0h7))
node _T_24 = and(_T_23, tag_match)
when _T_24 :
connect wentry.s_cnt, UInt<1>(0h0)
connect wentry.conf, UInt<1>(0h0)
else :
node _T_25 = eq(entries[_entry_T_1].conf, UInt<3>(0h7))
node _T_26 = eq(tag_match, UInt<1>(0h0))
node _T_27 = and(_T_25, _T_26)
when _T_27 :
skip
else :
node _T_28 = neq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_29 = and(_T_28, tag_match)
node _T_30 = and(_T_29, ctr_match)
when _T_30 :
node _wentry_conf_T = add(entries[_entry_T_1].conf, UInt<1>(0h1))
node _wentry_conf_T_1 = tail(_wentry_conf_T, 1)
connect wentry.conf, _wentry_conf_T_1
connect wentry.s_cnt, UInt<1>(0h0)
else :
node _T_31 = neq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_32 = and(_T_31, tag_match)
node _T_33 = eq(ctr_match, UInt<1>(0h0))
node _T_34 = and(_T_32, _T_33)
when _T_34 :
connect wentry.conf, UInt<1>(0h0)
connect wentry.s_cnt, UInt<1>(0h0)
connect wentry.p_cnt, io.update_meta.s_cnt
else :
node _T_35 = neq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_36 = eq(tag_match, UInt<1>(0h0))
node _T_37 = and(_T_35, _T_36)
node _T_38 = eq(entries[_entry_T_1].age, UInt<1>(0h0))
node _T_39 = and(_T_37, _T_38)
when _T_39 :
connect wentry.tag, tag
connect wentry.conf, UInt<1>(0h1)
connect wentry.s_cnt, UInt<1>(0h0)
connect wentry.p_cnt, io.update_meta.s_cnt
else :
node _T_40 = neq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_41 = eq(tag_match, UInt<1>(0h0))
node _T_42 = and(_T_40, _T_41)
node _T_43 = neq(entries[_entry_T_1].age, UInt<1>(0h0))
node _T_44 = and(_T_42, _T_43)
when _T_44 :
node _wentry_age_T = sub(entries[_entry_T_1].age, UInt<1>(0h1))
node _wentry_age_T_1 = tail(_wentry_age_T, 1)
connect wentry.age, _wentry_age_T_1
else :
node _T_45 = eq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_46 = and(_T_45, tag_match)
node _T_47 = and(_T_46, ctr_match)
when _T_47 :
connect wentry.conf, UInt<1>(0h1)
connect wentry.age, UInt<3>(0h7)
connect wentry.s_cnt, UInt<1>(0h0)
else :
node _T_48 = eq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_49 = and(_T_48, tag_match)
node _T_50 = eq(ctr_match, UInt<1>(0h0))
node _T_51 = and(_T_49, _T_50)
when _T_51 :
connect wentry.p_cnt, io.update_meta.s_cnt
connect wentry.age, UInt<3>(0h7)
connect wentry.s_cnt, UInt<1>(0h0)
else :
node _T_52 = eq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_53 = eq(tag_match, UInt<1>(0h0))
node _T_54 = and(_T_52, _T_53)
when _T_54 :
connect wentry.tag, tag
connect wentry.conf, UInt<1>(0h1)
connect wentry.age, UInt<3>(0h7)
connect wentry.s_cnt, UInt<1>(0h0)
connect wentry.p_cnt, io.update_meta.s_cnt
node _T_55 = or(io.update_idx, UInt<4>(0h0))
node _T_56 = bits(_T_55, 3, 0)
connect entries[_T_56], wentry
else :
node _T_57 = eq(doing_reset, UInt<1>(0h0))
node _T_58 = and(io.update_repair, _T_57)
when _T_58 :
node _T_59 = eq(io.update_idx, f4_idx)
node _T_60 = and(f4_fire, _T_59)
node _T_61 = eq(_T_60, UInt<1>(0h0))
node _T_62 = and(tag_match, _T_61)
when _T_62 :
connect wentry.s_cnt, io.update_meta.s_cnt
node _T_63 = or(io.update_idx, UInt<4>(0h0))
node _T_64 = bits(_T_63, 3, 0)
connect entries[_T_64], wentry
when doing_reset :
wire _entries_WIRE : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}
connect _entries_WIRE.s_cnt, UInt<10>(0h0)
connect _entries_WIRE.p_cnt, UInt<10>(0h0)
connect _entries_WIRE.age, UInt<3>(0h0)
connect _entries_WIRE.conf, UInt<3>(0h0)
connect _entries_WIRE.tag, UInt<10>(0h0)
connect entries[reset_idx], _entries_WIRE | module LoopBranchPredictorColumn_3( // @[loop.scala:39:9]
input clock, // @[loop.scala:39:9]
input reset, // @[loop.scala:39:9]
input io_f2_req_valid, // @[loop.scala:43:16]
input [36:0] io_f2_req_idx, // @[loop.scala:43:16]
input io_f3_req_fire, // @[loop.scala:43:16]
input io_f3_pred_in, // @[loop.scala:43:16]
output io_f3_pred, // @[loop.scala:43:16]
output [9:0] io_f3_meta_s_cnt, // @[loop.scala:43:16]
input io_update_mispredict, // @[loop.scala:43:16]
input io_update_repair, // @[loop.scala:43:16]
input [36:0] io_update_idx, // @[loop.scala:43:16]
input io_update_resolve_dir, // @[loop.scala:43:16]
input [9:0] io_update_meta_s_cnt // @[loop.scala:43:16]
);
wire io_f2_req_valid_0 = io_f2_req_valid; // @[loop.scala:39:9]
wire [36:0] io_f2_req_idx_0 = io_f2_req_idx; // @[loop.scala:39:9]
wire io_f3_req_fire_0 = io_f3_req_fire; // @[loop.scala:39:9]
wire io_f3_pred_in_0 = io_f3_pred_in; // @[loop.scala:39:9]
wire io_update_mispredict_0 = io_update_mispredict; // @[loop.scala:39:9]
wire io_update_repair_0 = io_update_repair; // @[loop.scala:39:9]
wire [36:0] io_update_idx_0 = io_update_idx; // @[loop.scala:39:9]
wire io_update_resolve_dir_0 = io_update_resolve_dir; // @[loop.scala:39:9]
wire [9:0] io_update_meta_s_cnt_0 = io_update_meta_s_cnt; // @[loop.scala:39:9]
wire [2:0] _entries_WIRE_conf = 3'h0; // @[loop.scala:176:43]
wire [2:0] _entries_WIRE_age = 3'h0; // @[loop.scala:176:43]
wire [9:0] _entries_WIRE_tag = 10'h0; // @[loop.scala:176:43]
wire [9:0] _entries_WIRE_p_cnt = 10'h0; // @[loop.scala:176:43]
wire [9:0] _entries_WIRE_s_cnt = 10'h0; // @[loop.scala:176:43]
wire [36:0] _f2_entry_T = io_f2_req_idx_0; // @[loop.scala:39:9]
wire [9:0] f3_scnt; // @[loop.scala:73:23]
wire [36:0] _entry_T = io_update_idx_0; // @[loop.scala:39:9]
wire [9:0] io_f3_meta_s_cnt_0; // @[loop.scala:39:9]
wire io_f3_pred_0; // @[loop.scala:39:9]
reg doing_reset; // @[loop.scala:59:30]
reg [3:0] reset_idx; // @[loop.scala:60:28]
wire [4:0] _reset_idx_T = {1'h0, reset_idx} + {4'h0, doing_reset}; // @[loop.scala:59:30, :60:28, :61:28]
wire [3:0] _reset_idx_T_1 = _reset_idx_T[3:0]; // @[loop.scala:61:28]
reg [9:0] entries_0_tag; // @[loop.scala:65:22]
reg [2:0] entries_0_conf; // @[loop.scala:65:22]
reg [2:0] entries_0_age; // @[loop.scala:65:22]
reg [9:0] entries_0_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_0_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_1_tag; // @[loop.scala:65:22]
reg [2:0] entries_1_conf; // @[loop.scala:65:22]
reg [2:0] entries_1_age; // @[loop.scala:65:22]
reg [9:0] entries_1_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_1_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_2_tag; // @[loop.scala:65:22]
reg [2:0] entries_2_conf; // @[loop.scala:65:22]
reg [2:0] entries_2_age; // @[loop.scala:65:22]
reg [9:0] entries_2_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_2_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_3_tag; // @[loop.scala:65:22]
reg [2:0] entries_3_conf; // @[loop.scala:65:22]
reg [2:0] entries_3_age; // @[loop.scala:65:22]
reg [9:0] entries_3_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_3_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_4_tag; // @[loop.scala:65:22]
reg [2:0] entries_4_conf; // @[loop.scala:65:22]
reg [2:0] entries_4_age; // @[loop.scala:65:22]
reg [9:0] entries_4_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_4_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_5_tag; // @[loop.scala:65:22]
reg [2:0] entries_5_conf; // @[loop.scala:65:22]
reg [2:0] entries_5_age; // @[loop.scala:65:22]
reg [9:0] entries_5_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_5_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_6_tag; // @[loop.scala:65:22]
reg [2:0] entries_6_conf; // @[loop.scala:65:22]
reg [2:0] entries_6_age; // @[loop.scala:65:22]
reg [9:0] entries_6_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_6_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_7_tag; // @[loop.scala:65:22]
reg [2:0] entries_7_conf; // @[loop.scala:65:22]
reg [2:0] entries_7_age; // @[loop.scala:65:22]
reg [9:0] entries_7_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_7_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_8_tag; // @[loop.scala:65:22]
reg [2:0] entries_8_conf; // @[loop.scala:65:22]
reg [2:0] entries_8_age; // @[loop.scala:65:22]
reg [9:0] entries_8_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_8_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_9_tag; // @[loop.scala:65:22]
reg [2:0] entries_9_conf; // @[loop.scala:65:22]
reg [2:0] entries_9_age; // @[loop.scala:65:22]
reg [9:0] entries_9_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_9_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_10_tag; // @[loop.scala:65:22]
reg [2:0] entries_10_conf; // @[loop.scala:65:22]
reg [2:0] entries_10_age; // @[loop.scala:65:22]
reg [9:0] entries_10_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_10_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_11_tag; // @[loop.scala:65:22]
reg [2:0] entries_11_conf; // @[loop.scala:65:22]
reg [2:0] entries_11_age; // @[loop.scala:65:22]
reg [9:0] entries_11_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_11_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_12_tag; // @[loop.scala:65:22]
reg [2:0] entries_12_conf; // @[loop.scala:65:22]
reg [2:0] entries_12_age; // @[loop.scala:65:22]
reg [9:0] entries_12_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_12_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_13_tag; // @[loop.scala:65:22]
reg [2:0] entries_13_conf; // @[loop.scala:65:22]
reg [2:0] entries_13_age; // @[loop.scala:65:22]
reg [9:0] entries_13_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_13_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_14_tag; // @[loop.scala:65:22]
reg [2:0] entries_14_conf; // @[loop.scala:65:22]
reg [2:0] entries_14_age; // @[loop.scala:65:22]
reg [9:0] entries_14_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_14_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_15_tag; // @[loop.scala:65:22]
reg [2:0] entries_15_conf; // @[loop.scala:65:22]
reg [2:0] entries_15_age; // @[loop.scala:65:22]
reg [9:0] entries_15_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_15_s_cnt; // @[loop.scala:65:22]
wire [3:0] _f2_entry_T_1 = _f2_entry_T[3:0];
wire [9:0] f2_entry_tag; // @[loop.scala:66:28]
wire [2:0] f2_entry_conf; // @[loop.scala:66:28]
wire [2:0] f2_entry_age; // @[loop.scala:66:28]
wire [9:0] f2_entry_p_cnt; // @[loop.scala:66:28]
wire [9:0] f2_entry_s_cnt; // @[loop.scala:66:28]
wire [15:0][9:0] _GEN = {{entries_15_tag}, {entries_14_tag}, {entries_13_tag}, {entries_12_tag}, {entries_11_tag}, {entries_10_tag}, {entries_9_tag}, {entries_8_tag}, {entries_7_tag}, {entries_6_tag}, {entries_5_tag}, {entries_4_tag}, {entries_3_tag}, {entries_2_tag}, {entries_1_tag}, {entries_0_tag}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_tag = _GEN[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][2:0] _GEN_0 = {{entries_15_conf}, {entries_14_conf}, {entries_13_conf}, {entries_12_conf}, {entries_11_conf}, {entries_10_conf}, {entries_9_conf}, {entries_8_conf}, {entries_7_conf}, {entries_6_conf}, {entries_5_conf}, {entries_4_conf}, {entries_3_conf}, {entries_2_conf}, {entries_1_conf}, {entries_0_conf}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_conf = _GEN_0[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][2:0] _GEN_1 = {{entries_15_age}, {entries_14_age}, {entries_13_age}, {entries_12_age}, {entries_11_age}, {entries_10_age}, {entries_9_age}, {entries_8_age}, {entries_7_age}, {entries_6_age}, {entries_5_age}, {entries_4_age}, {entries_3_age}, {entries_2_age}, {entries_1_age}, {entries_0_age}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_age = _GEN_1[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][9:0] _GEN_2 = {{entries_15_p_cnt}, {entries_14_p_cnt}, {entries_13_p_cnt}, {entries_12_p_cnt}, {entries_11_p_cnt}, {entries_10_p_cnt}, {entries_9_p_cnt}, {entries_8_p_cnt}, {entries_7_p_cnt}, {entries_6_p_cnt}, {entries_5_p_cnt}, {entries_4_p_cnt}, {entries_3_p_cnt}, {entries_2_p_cnt}, {entries_1_p_cnt}, {entries_0_p_cnt}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_p_cnt = _GEN_2[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][9:0] _GEN_3 = {{entries_15_s_cnt}, {entries_14_s_cnt}, {entries_13_s_cnt}, {entries_12_s_cnt}, {entries_11_s_cnt}, {entries_10_s_cnt}, {entries_9_s_cnt}, {entries_8_s_cnt}, {entries_7_s_cnt}, {entries_6_s_cnt}, {entries_5_s_cnt}, {entries_4_s_cnt}, {entries_3_s_cnt}, {entries_2_s_cnt}, {entries_1_s_cnt}, {entries_0_s_cnt}}; // @[loop.scala:65:22, :66:28]
wire _T_3 = io_update_idx_0 == io_f2_req_idx_0; // @[loop.scala:39:9, :67:45]
assign f2_entry_s_cnt = io_update_repair_0 & _T_3 ? io_update_meta_s_cnt_0 : io_update_mispredict_0 & _T_3 ? 10'h0 : _GEN_3[_f2_entry_T_1]; // @[loop.scala:39:9, :66:28, :67:{28,45,64}, :68:22, :69:{39,75}, :70:22]
reg [9:0] f3_entry_tag; // @[loop.scala:72:27]
reg [2:0] f3_entry_conf; // @[loop.scala:72:27]
reg [2:0] f3_entry_age; // @[loop.scala:72:27]
reg [9:0] f3_entry_p_cnt; // @[loop.scala:72:27]
reg [9:0] f3_entry_s_cnt; // @[loop.scala:72:27]
reg [36:0] f3_scnt_REG; // @[loop.scala:73:69]
wire _f3_scnt_T = io_update_idx_0 == f3_scnt_REG; // @[loop.scala:39:9, :73:{58,69}]
wire _f3_scnt_T_1 = io_update_repair_0 & _f3_scnt_T; // @[loop.scala:39:9, :73:{41,58}]
assign f3_scnt = _f3_scnt_T_1 ? io_update_meta_s_cnt_0 : f3_entry_s_cnt; // @[loop.scala:39:9, :72:27, :73:{23,41}]
assign io_f3_meta_s_cnt_0 = f3_scnt; // @[loop.scala:39:9, :73:23]
wire [9:0] _f3_tag_T = io_f2_req_idx_0[13:4]; // @[loop.scala:39:9, :76:41]
reg [9:0] f3_tag; // @[loop.scala:76:27]
wire _io_f3_pred_T = ~io_f3_pred_in_0; // @[loop.scala:39:9, :83:23]
assign io_f3_pred_0 = f3_entry_tag == f3_tag & f3_scnt == f3_entry_p_cnt & (&f3_entry_conf) ? _io_f3_pred_T : io_f3_pred_in_0; // @[loop.scala:39:9, :72:27, :73:23, :76:27, :78:16, :81:{24,36}, :82:{21,40,57,66}, :83:{20,23}]
reg f4_fire; // @[loop.scala:88:27]
reg [9:0] f4_entry_tag; // @[loop.scala:89:27]
reg [2:0] f4_entry_conf; // @[loop.scala:89:27]
reg [2:0] f4_entry_age; // @[loop.scala:89:27]
reg [9:0] f4_entry_p_cnt; // @[loop.scala:89:27]
reg [9:0] f4_entry_s_cnt; // @[loop.scala:89:27]
reg [9:0] f4_tag; // @[loop.scala:90:27]
reg [9:0] f4_scnt; // @[loop.scala:91:27]
reg [36:0] f4_idx_REG; // @[loop.scala:92:35]
reg [36:0] f4_idx; // @[loop.scala:92:27]
wire [10:0] _entries_s_cnt_T = {1'h0, f4_scnt} + 11'h1; // @[loop.scala:91:27, :101:44]
wire [9:0] _entries_s_cnt_T_1 = _entries_s_cnt_T[9:0]; // @[loop.scala:101:44]
wire _entries_age_T = &f4_entry_age; // @[loop.scala:89:27, :102:53]
wire [3:0] _entries_age_T_1 = {1'h0, f4_entry_age} + 4'h1; // @[loop.scala:89:27, :102:80]
wire [2:0] _entries_age_T_2 = _entries_age_T_1[2:0]; // @[loop.scala:102:80]
wire [2:0] _entries_age_T_3 = _entries_age_T ? 3'h7 : _entries_age_T_2; // @[loop.scala:102:{39,53,80}]
wire [3:0] _entry_T_1 = _entry_T[3:0];
wire [9:0] tag = io_update_idx_0[13:4]; // @[loop.scala:39:9, :109:28]
wire tag_match = _GEN[_entry_T_1] == tag; // @[loop.scala:66:28, :109:28, :110:31]
wire ctr_match = _GEN_2[_entry_T_1] == io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :111:33]
wire [9:0] wentry_tag; // @[loop.scala:112:26]
wire [2:0] wentry_conf; // @[loop.scala:112:26]
wire [2:0] wentry_age; // @[loop.scala:112:26]
wire [9:0] wentry_p_cnt; // @[loop.scala:112:26]
wire [9:0] wentry_s_cnt; // @[loop.scala:112:26]
wire _T_22 = io_update_mispredict_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:{32,35}]
wire _T_24 = (&_GEN_0[_entry_T_1]) & tag_match; // @[loop.scala:66:28, :110:31, :117:{24,32}]
wire _T_27 = (&_GEN_0[_entry_T_1]) & ~tag_match; // @[loop.scala:66:28, :110:31, :117:24, :122:{39,42}]
wire _T_30 = (|_GEN_0[_entry_T_1]) & tag_match & ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:{31,39,52}]
wire [3:0] _wentry_conf_T = {1'h0, _GEN_0[_entry_T_1]} + 4'h1; // @[loop.scala:66:28, :102:80, :110:31, :126:36]
wire [2:0] _wentry_conf_T_1 = _wentry_conf_T[2:0]; // @[loop.scala:126:36]
wire _T_34 = (|_GEN_0[_entry_T_1]) & tag_match & ~ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:31, :130:{39,52,55}]
wire _T_39 = (|_GEN_0[_entry_T_1]) & ~tag_match & _GEN_1[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :122:42, :125:31, :136:{39,53,66}]
wire _T_44 = (|_GEN_0[_entry_T_1]) & ~tag_match & (|_GEN_1[_entry_T_1]); // @[loop.scala:66:28, :110:31, :122:42, :125:31, :143:{39,53,66}]
wire [3:0] _wentry_age_T = {1'h0, _GEN_1[_entry_T_1]} - 4'h1; // @[loop.scala:66:28, :110:31, :144:33]
wire [2:0] _wentry_age_T_1 = _wentry_age_T[2:0]; // @[loop.scala:144:33]
wire _T_52 = _GEN_0[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :147:31]
wire _T_47 = _T_52 & tag_match & ctr_match; // @[loop.scala:110:31, :111:33, :147:{31,39,52}]
wire _T_51 = _T_52 & tag_match & ~ctr_match; // @[loop.scala:110:31, :111:33, :130:55, :147:31, :153:{39,52}]
wire _T_54 = _T_52 & ~tag_match; // @[loop.scala:110:31, :122:42, :147:31, :159:39]
wire _GEN_4 = _T_47 | _T_51; // @[loop.scala:112:26, :147:{39,52,66}, :153:{39,52,67}, :159:54]
wire _GEN_5 = _T_30 | _T_34; // @[loop.scala:112:26, :125:{39,52,66}, :130:{39,52,67}, :136:75]
assign wentry_tag = ~_T_22 | _T_24 | _T_27 | _GEN_5 | ~(_T_39 | ~(_T_44 | _GEN_4 | ~_T_54)) ? _GEN[_entry_T_1] : tag; // @[loop.scala:66:28, :109:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:66, :130:67, :136:{39,53,75}, :137:22, :143:{39,53,75}, :147:66, :153:67, :159:{39,54}]
assign wentry_conf = _T_22 ? (_T_24 ? 3'h0 : _T_27 ? _GEN_0[_entry_T_1] : _T_30 ? _wentry_conf_T_1 : _T_34 ? 3'h0 : _T_39 | ~(_T_44 | ~(_T_47 | ~(_T_51 | ~_T_54))) ? 3'h1 : _GEN_0[_entry_T_1]) : _GEN_0[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :119:22, :122:{39,54}, :125:{39,52,66}, :126:{22,36}, :130:{39,52,67}, :131:22, :136:{39,53,75}, :138:22, :143:{39,53,75}, :147:{39,52,66}, :148:22, :153:{39,52,67}, :159:{39,54}]
wire _GEN_6 = _T_51 | _T_54; // @[loop.scala:112:26, :153:{39,52,67}, :155:22, :159:{39,54}, :162:22]
wire _GEN_7 = _T_34 | _T_39; // @[loop.scala:112:26, :130:{39,52,67}, :136:{39,53,75}, :143:75]
assign wentry_age = ~_T_22 | _T_24 | _T_27 | _T_30 | _GEN_7 ? _GEN_1[_entry_T_1] : _T_44 ? _wentry_age_T_1 : _T_47 | _GEN_6 ? 3'h7 : _GEN_1[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :136:75, :143:{39,53,75}, :144:{20,33}, :147:{39,52,66}, :149:22, :153:67, :155:22, :159:54, :162:22]
assign wentry_p_cnt = ~_T_22 | _T_24 | _T_27 | _T_30 | ~(_GEN_7 | ~(_T_44 | _T_47 | ~_GEN_6)) ? _GEN_2[_entry_T_1] : io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :133:22, :136:75, :140:22, :143:{39,53,75}, :147:{39,52,66}, :153:67, :155:22, :159:54, :162:22]
wire _T_58 = io_update_repair_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:35, :168:35]
wire _T_62 = tag_match & ~(f4_fire & io_update_idx_0 == f4_idx); // @[loop.scala:39:9, :88:27, :92:27, :110:31, :169:{23,26,36,53}]
assign wentry_s_cnt = _T_22 ? (_T_24 | ~(_T_27 | ~(_GEN_5 | _T_39 | ~(_T_44 | ~(_GEN_4 | _T_54)))) ? 10'h0 : _GEN_3[_entry_T_1]) : _T_58 & _T_62 ? io_update_meta_s_cnt_0 : _GEN_3[_entry_T_1]; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :118:22, :122:{39,54}, :125:66, :127:22, :130:67, :132:22, :136:{39,53,75}, :139:22, :143:{39,53,75}, :147:66, :150:22, :153:67, :156:22, :159:{39,54}, :163:22, :168:{35,52}, :169:{23,66}, :170:22]
wire _T_12 = f4_scnt == f4_entry_p_cnt & (&f4_entry_conf); // @[loop.scala:89:27, :91:27, :97:{23,42,59}]
wire _GEN_8 = f4_fire & f4_entry_tag == f4_tag; // @[loop.scala:65:22, :88:27, :89:27, :90:27, :95:20, :96:{26,38}, :97:68]
always @(posedge clock) begin // @[loop.scala:39:9]
if (reset) begin // @[loop.scala:39:9]
doing_reset <= 1'h1; // @[loop.scala:59:30]
reset_idx <= 4'h0; // @[loop.scala:60:28]
end
else begin // @[loop.scala:39:9]
doing_reset <= reset_idx != 4'hF & doing_reset; // @[loop.scala:59:30, :60:28, :62:{21,38,52}]
reset_idx <= _reset_idx_T_1; // @[loop.scala:60:28, :61:28]
end
if (doing_reset & reset_idx == 4'h0) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_0_tag <= 10'h0; // @[loop.scala:65:22]
entries_0_conf <= 3'h0; // @[loop.scala:65:22]
entries_0_age <= 3'h0; // @[loop.scala:65:22]
entries_0_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h0 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h0) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_0_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_0_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_0_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_0_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_0_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :98:33]
entries_0_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :99:33]
entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :102:33]
entries_0_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :101:33]
entries_0_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h1) begin // @[loop.scala:59:30, :60:28, :102:80, :114:49, :175:24, :176:26]
entries_1_tag <= 10'h0; // @[loop.scala:65:22]
entries_1_conf <= 3'h0; // @[loop.scala:65:22]
entries_1_age <= 3'h0; // @[loop.scala:65:22]
entries_1_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h1 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h1) begin // @[loop.scala:39:9, :65:22, :95:20, :102:80, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_1_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_1_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_1_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_1_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_1_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :98:33, :102:80]
entries_1_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :99:33, :102:80]
entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :102:{33,80}]
entries_1_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :101:33, :102:80]
entries_1_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h2) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_2_tag <= 10'h0; // @[loop.scala:65:22]
entries_2_conf <= 3'h0; // @[loop.scala:65:22]
entries_2_age <= 3'h0; // @[loop.scala:65:22]
entries_2_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h2 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h2) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_2_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_2_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_2_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_2_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_2_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :98:33]
entries_2_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :99:33]
entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :102:33]
entries_2_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :101:33]
entries_2_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h3) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_3_tag <= 10'h0; // @[loop.scala:65:22]
entries_3_conf <= 3'h0; // @[loop.scala:65:22]
entries_3_age <= 3'h0; // @[loop.scala:65:22]
entries_3_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h3 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h3) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_3_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_3_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_3_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_3_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_3_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :98:33]
entries_3_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :99:33]
entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :102:33]
entries_3_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :101:33]
entries_3_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h4) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_4_tag <= 10'h0; // @[loop.scala:65:22]
entries_4_conf <= 3'h0; // @[loop.scala:65:22]
entries_4_age <= 3'h0; // @[loop.scala:65:22]
entries_4_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h4 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h4) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_4_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_4_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_4_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_4_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_4_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :98:33]
entries_4_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :99:33]
entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :102:33]
entries_4_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :101:33]
entries_4_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h5) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_5_tag <= 10'h0; // @[loop.scala:65:22]
entries_5_conf <= 3'h0; // @[loop.scala:65:22]
entries_5_age <= 3'h0; // @[loop.scala:65:22]
entries_5_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h5 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h5) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_5_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_5_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_5_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_5_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_5_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :98:33]
entries_5_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :99:33]
entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :102:33]
entries_5_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :101:33]
entries_5_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h6) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_6_tag <= 10'h0; // @[loop.scala:65:22]
entries_6_conf <= 3'h0; // @[loop.scala:65:22]
entries_6_age <= 3'h0; // @[loop.scala:65:22]
entries_6_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h6 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h6) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_6_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_6_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_6_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_6_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_6_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :98:33]
entries_6_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :99:33]
entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :102:33]
entries_6_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :101:33]
entries_6_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h7) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_7_tag <= 10'h0; // @[loop.scala:65:22]
entries_7_conf <= 3'h0; // @[loop.scala:65:22]
entries_7_age <= 3'h0; // @[loop.scala:65:22]
entries_7_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h7 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h7) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_7_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_7_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_7_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_7_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_7_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :98:33]
entries_7_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :99:33]
entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :102:33]
entries_7_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :101:33]
entries_7_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h8) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_8_tag <= 10'h0; // @[loop.scala:65:22]
entries_8_conf <= 3'h0; // @[loop.scala:65:22]
entries_8_age <= 3'h0; // @[loop.scala:65:22]
entries_8_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h8 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h8) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_8_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_8_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_8_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_8_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_8_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :98:33]
entries_8_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :99:33]
entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :102:33]
entries_8_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :101:33]
entries_8_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h9) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_9_tag <= 10'h0; // @[loop.scala:65:22]
entries_9_conf <= 3'h0; // @[loop.scala:65:22]
entries_9_age <= 3'h0; // @[loop.scala:65:22]
entries_9_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h9 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h9) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_9_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_9_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_9_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_9_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_9_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :98:33]
entries_9_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :99:33]
entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :102:33]
entries_9_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :101:33]
entries_9_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hA) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_10_tag <= 10'h0; // @[loop.scala:65:22]
entries_10_conf <= 3'h0; // @[loop.scala:65:22]
entries_10_age <= 3'h0; // @[loop.scala:65:22]
entries_10_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hA : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hA) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_10_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_10_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_10_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_10_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_10_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :98:33]
entries_10_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :99:33]
entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :102:33]
entries_10_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :101:33]
entries_10_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hB) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_11_tag <= 10'h0; // @[loop.scala:65:22]
entries_11_conf <= 3'h0; // @[loop.scala:65:22]
entries_11_age <= 3'h0; // @[loop.scala:65:22]
entries_11_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hB : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hB) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_11_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_11_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_11_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_11_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_11_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :98:33]
entries_11_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :99:33]
entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :102:33]
entries_11_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :101:33]
entries_11_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hC) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_12_tag <= 10'h0; // @[loop.scala:65:22]
entries_12_conf <= 3'h0; // @[loop.scala:65:22]
entries_12_age <= 3'h0; // @[loop.scala:65:22]
entries_12_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hC : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hC) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_12_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_12_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_12_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_12_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_12_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :98:33]
entries_12_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :99:33]
entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :102:33]
entries_12_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :101:33]
entries_12_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hD) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_13_tag <= 10'h0; // @[loop.scala:65:22]
entries_13_conf <= 3'h0; // @[loop.scala:65:22]
entries_13_age <= 3'h0; // @[loop.scala:65:22]
entries_13_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hD : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hD) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_13_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_13_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_13_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_13_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_13_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :98:33]
entries_13_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :99:33]
entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :102:33]
entries_13_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :101:33]
entries_13_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hE) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_14_tag <= 10'h0; // @[loop.scala:65:22]
entries_14_conf <= 3'h0; // @[loop.scala:65:22]
entries_14_age <= 3'h0; // @[loop.scala:65:22]
entries_14_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hE : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hE) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_14_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_14_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_14_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_14_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_14_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :98:33]
entries_14_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :99:33]
entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :102:33]
entries_14_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :101:33]
entries_14_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & (&reset_idx)) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_15_tag <= 10'h0; // @[loop.scala:65:22]
entries_15_conf <= 3'h0; // @[loop.scala:65:22]
entries_15_age <= 3'h0; // @[loop.scala:65:22]
entries_15_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? (&(io_update_idx_0[3:0])) : _T_58 & _T_62 & (&(io_update_idx_0[3:0]))) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_15_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_15_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_15_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_15_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_15_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :98:33]
entries_15_age <= 3'h7; // @[loop.scala:65:22]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :99:33]
entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :102:33]
entries_15_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :101:33]
entries_15_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
f3_entry_tag <= f2_entry_tag; // @[loop.scala:66:28, :72:27]
f3_entry_conf <= f2_entry_conf; // @[loop.scala:66:28, :72:27]
f3_entry_age <= f2_entry_age; // @[loop.scala:66:28, :72:27]
f3_entry_p_cnt <= f2_entry_p_cnt; // @[loop.scala:66:28, :72:27]
f3_entry_s_cnt <= f2_entry_s_cnt; // @[loop.scala:66:28, :72:27]
f3_scnt_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :73:69]
f3_tag <= _f3_tag_T; // @[loop.scala:76:{27,41}]
f4_fire <= io_f3_req_fire_0; // @[loop.scala:39:9, :88:27]
f4_entry_tag <= f3_entry_tag; // @[loop.scala:72:27, :89:27]
f4_entry_conf <= f3_entry_conf; // @[loop.scala:72:27, :89:27]
f4_entry_age <= f3_entry_age; // @[loop.scala:72:27, :89:27]
f4_entry_p_cnt <= f3_entry_p_cnt; // @[loop.scala:72:27, :89:27]
f4_entry_s_cnt <= f3_entry_s_cnt; // @[loop.scala:72:27, :89:27]
f4_tag <= f3_tag; // @[loop.scala:76:27, :90:27]
f4_scnt <= f3_scnt; // @[loop.scala:73:23, :91:27]
f4_idx_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :92:35]
f4_idx <= f4_idx_REG; // @[loop.scala:92:{27,35}]
always @(posedge)
assign io_f3_pred = io_f3_pred_0; // @[loop.scala:39:9]
assign io_f3_meta_s_cnt = io_f3_meta_s_cnt_0; // @[loop.scala:39:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module INToRecFN_i32_e8_s24_7 :
output io : { flip signedIn : UInt<1>, flip in : UInt<32>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node _intAsRawFloat_sign_T = bits(io.in, 31, 31)
node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T)
node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in)
node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1)
node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in)
node _intAsRawFloat_extAbsIn_T = cat(UInt<32>(0h0), intAsRawFloat_absIn)
node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 31, 0)
node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0)
node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1)
node _intAsRawFloat_adjustedNormDist_T_2 = bits(intAsRawFloat_extAbsIn, 2, 2)
node _intAsRawFloat_adjustedNormDist_T_3 = bits(intAsRawFloat_extAbsIn, 3, 3)
node _intAsRawFloat_adjustedNormDist_T_4 = bits(intAsRawFloat_extAbsIn, 4, 4)
node _intAsRawFloat_adjustedNormDist_T_5 = bits(intAsRawFloat_extAbsIn, 5, 5)
node _intAsRawFloat_adjustedNormDist_T_6 = bits(intAsRawFloat_extAbsIn, 6, 6)
node _intAsRawFloat_adjustedNormDist_T_7 = bits(intAsRawFloat_extAbsIn, 7, 7)
node _intAsRawFloat_adjustedNormDist_T_8 = bits(intAsRawFloat_extAbsIn, 8, 8)
node _intAsRawFloat_adjustedNormDist_T_9 = bits(intAsRawFloat_extAbsIn, 9, 9)
node _intAsRawFloat_adjustedNormDist_T_10 = bits(intAsRawFloat_extAbsIn, 10, 10)
node _intAsRawFloat_adjustedNormDist_T_11 = bits(intAsRawFloat_extAbsIn, 11, 11)
node _intAsRawFloat_adjustedNormDist_T_12 = bits(intAsRawFloat_extAbsIn, 12, 12)
node _intAsRawFloat_adjustedNormDist_T_13 = bits(intAsRawFloat_extAbsIn, 13, 13)
node _intAsRawFloat_adjustedNormDist_T_14 = bits(intAsRawFloat_extAbsIn, 14, 14)
node _intAsRawFloat_adjustedNormDist_T_15 = bits(intAsRawFloat_extAbsIn, 15, 15)
node _intAsRawFloat_adjustedNormDist_T_16 = bits(intAsRawFloat_extAbsIn, 16, 16)
node _intAsRawFloat_adjustedNormDist_T_17 = bits(intAsRawFloat_extAbsIn, 17, 17)
node _intAsRawFloat_adjustedNormDist_T_18 = bits(intAsRawFloat_extAbsIn, 18, 18)
node _intAsRawFloat_adjustedNormDist_T_19 = bits(intAsRawFloat_extAbsIn, 19, 19)
node _intAsRawFloat_adjustedNormDist_T_20 = bits(intAsRawFloat_extAbsIn, 20, 20)
node _intAsRawFloat_adjustedNormDist_T_21 = bits(intAsRawFloat_extAbsIn, 21, 21)
node _intAsRawFloat_adjustedNormDist_T_22 = bits(intAsRawFloat_extAbsIn, 22, 22)
node _intAsRawFloat_adjustedNormDist_T_23 = bits(intAsRawFloat_extAbsIn, 23, 23)
node _intAsRawFloat_adjustedNormDist_T_24 = bits(intAsRawFloat_extAbsIn, 24, 24)
node _intAsRawFloat_adjustedNormDist_T_25 = bits(intAsRawFloat_extAbsIn, 25, 25)
node _intAsRawFloat_adjustedNormDist_T_26 = bits(intAsRawFloat_extAbsIn, 26, 26)
node _intAsRawFloat_adjustedNormDist_T_27 = bits(intAsRawFloat_extAbsIn, 27, 27)
node _intAsRawFloat_adjustedNormDist_T_28 = bits(intAsRawFloat_extAbsIn, 28, 28)
node _intAsRawFloat_adjustedNormDist_T_29 = bits(intAsRawFloat_extAbsIn, 29, 29)
node _intAsRawFloat_adjustedNormDist_T_30 = bits(intAsRawFloat_extAbsIn, 30, 30)
node _intAsRawFloat_adjustedNormDist_T_31 = bits(intAsRawFloat_extAbsIn, 31, 31)
node _intAsRawFloat_adjustedNormDist_T_32 = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<5>(0h1e), UInt<5>(0h1f))
node _intAsRawFloat_adjustedNormDist_T_33 = mux(_intAsRawFloat_adjustedNormDist_T_2, UInt<5>(0h1d), _intAsRawFloat_adjustedNormDist_T_32)
node _intAsRawFloat_adjustedNormDist_T_34 = mux(_intAsRawFloat_adjustedNormDist_T_3, UInt<5>(0h1c), _intAsRawFloat_adjustedNormDist_T_33)
node _intAsRawFloat_adjustedNormDist_T_35 = mux(_intAsRawFloat_adjustedNormDist_T_4, UInt<5>(0h1b), _intAsRawFloat_adjustedNormDist_T_34)
node _intAsRawFloat_adjustedNormDist_T_36 = mux(_intAsRawFloat_adjustedNormDist_T_5, UInt<5>(0h1a), _intAsRawFloat_adjustedNormDist_T_35)
node _intAsRawFloat_adjustedNormDist_T_37 = mux(_intAsRawFloat_adjustedNormDist_T_6, UInt<5>(0h19), _intAsRawFloat_adjustedNormDist_T_36)
node _intAsRawFloat_adjustedNormDist_T_38 = mux(_intAsRawFloat_adjustedNormDist_T_7, UInt<5>(0h18), _intAsRawFloat_adjustedNormDist_T_37)
node _intAsRawFloat_adjustedNormDist_T_39 = mux(_intAsRawFloat_adjustedNormDist_T_8, UInt<5>(0h17), _intAsRawFloat_adjustedNormDist_T_38)
node _intAsRawFloat_adjustedNormDist_T_40 = mux(_intAsRawFloat_adjustedNormDist_T_9, UInt<5>(0h16), _intAsRawFloat_adjustedNormDist_T_39)
node _intAsRawFloat_adjustedNormDist_T_41 = mux(_intAsRawFloat_adjustedNormDist_T_10, UInt<5>(0h15), _intAsRawFloat_adjustedNormDist_T_40)
node _intAsRawFloat_adjustedNormDist_T_42 = mux(_intAsRawFloat_adjustedNormDist_T_11, UInt<5>(0h14), _intAsRawFloat_adjustedNormDist_T_41)
node _intAsRawFloat_adjustedNormDist_T_43 = mux(_intAsRawFloat_adjustedNormDist_T_12, UInt<5>(0h13), _intAsRawFloat_adjustedNormDist_T_42)
node _intAsRawFloat_adjustedNormDist_T_44 = mux(_intAsRawFloat_adjustedNormDist_T_13, UInt<5>(0h12), _intAsRawFloat_adjustedNormDist_T_43)
node _intAsRawFloat_adjustedNormDist_T_45 = mux(_intAsRawFloat_adjustedNormDist_T_14, UInt<5>(0h11), _intAsRawFloat_adjustedNormDist_T_44)
node _intAsRawFloat_adjustedNormDist_T_46 = mux(_intAsRawFloat_adjustedNormDist_T_15, UInt<5>(0h10), _intAsRawFloat_adjustedNormDist_T_45)
node _intAsRawFloat_adjustedNormDist_T_47 = mux(_intAsRawFloat_adjustedNormDist_T_16, UInt<4>(0hf), _intAsRawFloat_adjustedNormDist_T_46)
node _intAsRawFloat_adjustedNormDist_T_48 = mux(_intAsRawFloat_adjustedNormDist_T_17, UInt<4>(0he), _intAsRawFloat_adjustedNormDist_T_47)
node _intAsRawFloat_adjustedNormDist_T_49 = mux(_intAsRawFloat_adjustedNormDist_T_18, UInt<4>(0hd), _intAsRawFloat_adjustedNormDist_T_48)
node _intAsRawFloat_adjustedNormDist_T_50 = mux(_intAsRawFloat_adjustedNormDist_T_19, UInt<4>(0hc), _intAsRawFloat_adjustedNormDist_T_49)
node _intAsRawFloat_adjustedNormDist_T_51 = mux(_intAsRawFloat_adjustedNormDist_T_20, UInt<4>(0hb), _intAsRawFloat_adjustedNormDist_T_50)
node _intAsRawFloat_adjustedNormDist_T_52 = mux(_intAsRawFloat_adjustedNormDist_T_21, UInt<4>(0ha), _intAsRawFloat_adjustedNormDist_T_51)
node _intAsRawFloat_adjustedNormDist_T_53 = mux(_intAsRawFloat_adjustedNormDist_T_22, UInt<4>(0h9), _intAsRawFloat_adjustedNormDist_T_52)
node _intAsRawFloat_adjustedNormDist_T_54 = mux(_intAsRawFloat_adjustedNormDist_T_23, UInt<4>(0h8), _intAsRawFloat_adjustedNormDist_T_53)
node _intAsRawFloat_adjustedNormDist_T_55 = mux(_intAsRawFloat_adjustedNormDist_T_24, UInt<3>(0h7), _intAsRawFloat_adjustedNormDist_T_54)
node _intAsRawFloat_adjustedNormDist_T_56 = mux(_intAsRawFloat_adjustedNormDist_T_25, UInt<3>(0h6), _intAsRawFloat_adjustedNormDist_T_55)
node _intAsRawFloat_adjustedNormDist_T_57 = mux(_intAsRawFloat_adjustedNormDist_T_26, UInt<3>(0h5), _intAsRawFloat_adjustedNormDist_T_56)
node _intAsRawFloat_adjustedNormDist_T_58 = mux(_intAsRawFloat_adjustedNormDist_T_27, UInt<3>(0h4), _intAsRawFloat_adjustedNormDist_T_57)
node _intAsRawFloat_adjustedNormDist_T_59 = mux(_intAsRawFloat_adjustedNormDist_T_28, UInt<2>(0h3), _intAsRawFloat_adjustedNormDist_T_58)
node _intAsRawFloat_adjustedNormDist_T_60 = mux(_intAsRawFloat_adjustedNormDist_T_29, UInt<2>(0h2), _intAsRawFloat_adjustedNormDist_T_59)
node _intAsRawFloat_adjustedNormDist_T_61 = mux(_intAsRawFloat_adjustedNormDist_T_30, UInt<1>(0h1), _intAsRawFloat_adjustedNormDist_T_60)
node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_31, UInt<1>(0h0), _intAsRawFloat_adjustedNormDist_T_61)
node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist)
node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 31, 0)
wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<8>, sig : UInt<33>}
connect intAsRawFloat.isNaN, UInt<1>(0h0)
connect intAsRawFloat.isInf, UInt<1>(0h0)
node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 31, 31)
node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0))
connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1
connect intAsRawFloat.sign, intAsRawFloat_sign
node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 4, 0)
node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T)
node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1)
node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2)
connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3
connect intAsRawFloat.sig, intAsRawFloat_sig
inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie6_is32_oe8_os24_7
connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0)
connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig
connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp
connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign
connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero
connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf
connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN
connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundAnyRawFNToRecFN.io.out
connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags | module INToRecFN_i32_e8_s24_7( // @[INToRecFN.scala:43:7]
input [31:0] io_in, // @[INToRecFN.scala:46:16]
output [32:0] io_out // @[INToRecFN.scala:46:16]
);
wire [31:0] io_in_0 = io_in; // @[INToRecFN.scala:43:7]
wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire [2:0] io_roundingMode = 3'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15]
wire io_signedIn = 1'h1; // @[INToRecFN.scala:43:7]
wire io_detectTininess = 1'h1; // @[INToRecFN.scala:43:7]
wire [32:0] io_out_0; // @[INToRecFN.scala:43:7]
wire [4:0] io_exceptionFlags; // @[INToRecFN.scala:43:7]
wire _intAsRawFloat_sign_T = io_in_0[31]; // @[rawFloatFromIN.scala:51:34]
wire intAsRawFloat_sign = _intAsRawFloat_sign_T; // @[rawFloatFromIN.scala:51:{29,34}]
wire intAsRawFloat_sign_0 = intAsRawFloat_sign; // @[rawFloatFromIN.scala:51:29, :59:23]
wire [32:0] _intAsRawFloat_absIn_T = 33'h0 - {1'h0, io_in_0}; // @[rawFloatFromIN.scala:52:31]
wire [31:0] _intAsRawFloat_absIn_T_1 = _intAsRawFloat_absIn_T[31:0]; // @[rawFloatFromIN.scala:52:31]
wire [31:0] intAsRawFloat_absIn = intAsRawFloat_sign ? _intAsRawFloat_absIn_T_1 : io_in_0; // @[rawFloatFromIN.scala:51:29, :52:{24,31}]
wire [63:0] _intAsRawFloat_extAbsIn_T = {32'h0, intAsRawFloat_absIn}; // @[rawFloatFromIN.scala:52:24, :53:44]
wire [31:0] intAsRawFloat_extAbsIn = _intAsRawFloat_extAbsIn_T[31:0]; // @[rawFloatFromIN.scala:53:{44,53}]
wire _intAsRawFloat_adjustedNormDist_T = intAsRawFloat_extAbsIn[0]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_1 = intAsRawFloat_extAbsIn[1]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_2 = intAsRawFloat_extAbsIn[2]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_3 = intAsRawFloat_extAbsIn[3]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_4 = intAsRawFloat_extAbsIn[4]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_5 = intAsRawFloat_extAbsIn[5]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_6 = intAsRawFloat_extAbsIn[6]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_7 = intAsRawFloat_extAbsIn[7]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_8 = intAsRawFloat_extAbsIn[8]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_9 = intAsRawFloat_extAbsIn[9]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_10 = intAsRawFloat_extAbsIn[10]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_11 = intAsRawFloat_extAbsIn[11]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_12 = intAsRawFloat_extAbsIn[12]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_13 = intAsRawFloat_extAbsIn[13]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_14 = intAsRawFloat_extAbsIn[14]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_15 = intAsRawFloat_extAbsIn[15]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_16 = intAsRawFloat_extAbsIn[16]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_17 = intAsRawFloat_extAbsIn[17]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_18 = intAsRawFloat_extAbsIn[18]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_19 = intAsRawFloat_extAbsIn[19]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_20 = intAsRawFloat_extAbsIn[20]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_21 = intAsRawFloat_extAbsIn[21]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_22 = intAsRawFloat_extAbsIn[22]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_23 = intAsRawFloat_extAbsIn[23]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_24 = intAsRawFloat_extAbsIn[24]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_25 = intAsRawFloat_extAbsIn[25]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_26 = intAsRawFloat_extAbsIn[26]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_27 = intAsRawFloat_extAbsIn[27]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_28 = intAsRawFloat_extAbsIn[28]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_29 = intAsRawFloat_extAbsIn[29]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_30 = intAsRawFloat_extAbsIn[30]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_31 = intAsRawFloat_extAbsIn[31]; // @[rawFloatFromIN.scala:53:53]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_32 = {4'hF, ~_intAsRawFloat_adjustedNormDist_T_1}; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_33 = _intAsRawFloat_adjustedNormDist_T_2 ? 5'h1D : _intAsRawFloat_adjustedNormDist_T_32; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_34 = _intAsRawFloat_adjustedNormDist_T_3 ? 5'h1C : _intAsRawFloat_adjustedNormDist_T_33; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_35 = _intAsRawFloat_adjustedNormDist_T_4 ? 5'h1B : _intAsRawFloat_adjustedNormDist_T_34; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_36 = _intAsRawFloat_adjustedNormDist_T_5 ? 5'h1A : _intAsRawFloat_adjustedNormDist_T_35; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_37 = _intAsRawFloat_adjustedNormDist_T_6 ? 5'h19 : _intAsRawFloat_adjustedNormDist_T_36; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_38 = _intAsRawFloat_adjustedNormDist_T_7 ? 5'h18 : _intAsRawFloat_adjustedNormDist_T_37; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_39 = _intAsRawFloat_adjustedNormDist_T_8 ? 5'h17 : _intAsRawFloat_adjustedNormDist_T_38; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_40 = _intAsRawFloat_adjustedNormDist_T_9 ? 5'h16 : _intAsRawFloat_adjustedNormDist_T_39; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_41 = _intAsRawFloat_adjustedNormDist_T_10 ? 5'h15 : _intAsRawFloat_adjustedNormDist_T_40; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_42 = _intAsRawFloat_adjustedNormDist_T_11 ? 5'h14 : _intAsRawFloat_adjustedNormDist_T_41; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_43 = _intAsRawFloat_adjustedNormDist_T_12 ? 5'h13 : _intAsRawFloat_adjustedNormDist_T_42; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_44 = _intAsRawFloat_adjustedNormDist_T_13 ? 5'h12 : _intAsRawFloat_adjustedNormDist_T_43; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_45 = _intAsRawFloat_adjustedNormDist_T_14 ? 5'h11 : _intAsRawFloat_adjustedNormDist_T_44; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_46 = _intAsRawFloat_adjustedNormDist_T_15 ? 5'h10 : _intAsRawFloat_adjustedNormDist_T_45; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_47 = _intAsRawFloat_adjustedNormDist_T_16 ? 5'hF : _intAsRawFloat_adjustedNormDist_T_46; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_48 = _intAsRawFloat_adjustedNormDist_T_17 ? 5'hE : _intAsRawFloat_adjustedNormDist_T_47; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_49 = _intAsRawFloat_adjustedNormDist_T_18 ? 5'hD : _intAsRawFloat_adjustedNormDist_T_48; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_50 = _intAsRawFloat_adjustedNormDist_T_19 ? 5'hC : _intAsRawFloat_adjustedNormDist_T_49; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_51 = _intAsRawFloat_adjustedNormDist_T_20 ? 5'hB : _intAsRawFloat_adjustedNormDist_T_50; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_52 = _intAsRawFloat_adjustedNormDist_T_21 ? 5'hA : _intAsRawFloat_adjustedNormDist_T_51; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_53 = _intAsRawFloat_adjustedNormDist_T_22 ? 5'h9 : _intAsRawFloat_adjustedNormDist_T_52; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_54 = _intAsRawFloat_adjustedNormDist_T_23 ? 5'h8 : _intAsRawFloat_adjustedNormDist_T_53; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_55 = _intAsRawFloat_adjustedNormDist_T_24 ? 5'h7 : _intAsRawFloat_adjustedNormDist_T_54; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_56 = _intAsRawFloat_adjustedNormDist_T_25 ? 5'h6 : _intAsRawFloat_adjustedNormDist_T_55; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_57 = _intAsRawFloat_adjustedNormDist_T_26 ? 5'h5 : _intAsRawFloat_adjustedNormDist_T_56; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_58 = _intAsRawFloat_adjustedNormDist_T_27 ? 5'h4 : _intAsRawFloat_adjustedNormDist_T_57; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_59 = _intAsRawFloat_adjustedNormDist_T_28 ? 5'h3 : _intAsRawFloat_adjustedNormDist_T_58; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_60 = _intAsRawFloat_adjustedNormDist_T_29 ? 5'h2 : _intAsRawFloat_adjustedNormDist_T_59; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_61 = _intAsRawFloat_adjustedNormDist_T_30 ? 5'h1 : _intAsRawFloat_adjustedNormDist_T_60; // @[Mux.scala:50:70]
wire [4:0] intAsRawFloat_adjustedNormDist = _intAsRawFloat_adjustedNormDist_T_31 ? 5'h0 : _intAsRawFloat_adjustedNormDist_T_61; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_out_sExp_T = intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70]
wire [62:0] _intAsRawFloat_sig_T = {31'h0, intAsRawFloat_extAbsIn} << intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70]
wire [31:0] intAsRawFloat_sig = _intAsRawFloat_sig_T[31:0]; // @[rawFloatFromIN.scala:56:{22,41}]
wire _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:62:23]
wire [7:0] _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:64:72]
wire intAsRawFloat_isZero; // @[rawFloatFromIN.scala:59:23]
wire [7:0] intAsRawFloat_sExp; // @[rawFloatFromIN.scala:59:23]
wire [32:0] intAsRawFloat_sig_0; // @[rawFloatFromIN.scala:59:23]
wire _intAsRawFloat_out_isZero_T = intAsRawFloat_sig[31]; // @[rawFloatFromIN.scala:56:41, :62:28]
assign _intAsRawFloat_out_isZero_T_1 = ~_intAsRawFloat_out_isZero_T; // @[rawFloatFromIN.scala:62:{23,28}]
assign intAsRawFloat_isZero = _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:59:23, :62:23]
wire [4:0] _intAsRawFloat_out_sExp_T_1 = ~_intAsRawFloat_out_sExp_T; // @[rawFloatFromIN.scala:64:{36,53}]
wire [6:0] _intAsRawFloat_out_sExp_T_2 = {2'h2, _intAsRawFloat_out_sExp_T_1}; // @[rawFloatFromIN.scala:64:{33,36}]
assign _intAsRawFloat_out_sExp_T_3 = {1'h0, _intAsRawFloat_out_sExp_T_2}; // @[rawFloatFromIN.scala:64:{33,72}]
assign intAsRawFloat_sExp = _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:59:23, :64:72]
assign intAsRawFloat_sig_0 = {1'h0, intAsRawFloat_sig}; // @[rawFloatFromIN.scala:56:41, :59:23, :65:20]
RoundAnyRawFNToRecFN_ie6_is32_oe8_os24_7 roundAnyRawFNToRecFN ( // @[INToRecFN.scala:60:15]
.io_in_isZero (intAsRawFloat_isZero), // @[rawFloatFromIN.scala:59:23]
.io_in_sign (intAsRawFloat_sign_0), // @[rawFloatFromIN.scala:59:23]
.io_in_sExp (intAsRawFloat_sExp), // @[rawFloatFromIN.scala:59:23]
.io_in_sig (intAsRawFloat_sig_0), // @[rawFloatFromIN.scala:59:23]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags)
); // @[INToRecFN.scala:60:15]
assign io_out = io_out_0; // @[INToRecFN.scala:43:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_27 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_38
connect io_out_sink_valid.clock, clock
connect io_out_sink_valid.reset, reset
connect io_out_sink_valid.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_valid.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_27( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_38 io_out_sink_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncQueueSource_DebugInternalBundle :
input clock : Clock
input reset : Reset
output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resumereq : UInt<1>, hartsel : UInt<10>, ackhavereset : UInt<1>, hasel : UInt<1>, hamask : UInt<1>[8], hrmask : UInt<1>[8]}}, async : { mem : { resumereq : UInt<1>, hartsel : UInt<10>, ackhavereset : UInt<1>, hasel : UInt<1>, hamask : UInt<1>[8], hrmask : UInt<1>[8]}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}}
wire sink_ready : UInt<1>
connect sink_ready, UInt<1>(0h1)
reg mem : { resumereq : UInt<1>, hartsel : UInt<10>, ackhavereset : UInt<1>, hasel : UInt<1>, hamask : UInt<1>[8], hrmask : UInt<1>[8]}[1], clock
node _widx_T = asAsyncReset(reset)
node _widx_T_1 = and(io.enq.ready, io.enq.valid)
node _widx_T_2 = eq(sink_ready, UInt<1>(0h0))
wire widx_incremented : UInt<1>
regreset widx_widx_bin : UInt, clock, _widx_T, UInt<1>(0h0)
connect widx_widx_bin, widx_incremented
node _widx_incremented_T = add(widx_widx_bin, _widx_T_1)
node _widx_incremented_T_1 = tail(_widx_incremented_T, 1)
node _widx_incremented_T_2 = mux(_widx_T_2, UInt<1>(0h0), _widx_incremented_T_1)
connect widx_incremented, _widx_incremented_T_2
node _widx_T_3 = shr(widx_incremented, 1)
node widx = xor(widx_incremented, _widx_T_3)
inst ridx_ridx_gray of AsyncResetSynchronizerShiftReg_w1_d3_i0_11
connect ridx_ridx_gray.clock, clock
connect ridx_ridx_gray.reset, reset
connect ridx_ridx_gray.io.d, io.async.ridx
wire ridx : UInt<1>
connect ridx, ridx_ridx_gray.io.q
node _ready_T = xor(ridx, UInt<1>(0h1))
node _ready_T_1 = neq(widx, _ready_T)
node ready = and(sink_ready, _ready_T_1)
node _T = and(io.enq.ready, io.enq.valid)
when _T :
connect mem[0], io.enq.bits
node _ready_reg_T = asAsyncReset(reset)
regreset ready_reg : UInt<1>, clock, _ready_reg_T, UInt<1>(0h0)
connect ready_reg, ready
node _io_enq_ready_T = and(ready_reg, sink_ready)
connect io.enq.ready, _io_enq_ready_T
node _widx_reg_T = asAsyncReset(reset)
regreset widx_gray : UInt, clock, _widx_reg_T, UInt<1>(0h0)
connect widx_gray, widx
connect io.async.widx, widx_gray
connect io.async.mem, mem
inst source_valid_0 of AsyncValidSync_8
inst source_valid_1 of AsyncValidSync_9
inst sink_extend of AsyncValidSync_10
inst sink_valid of AsyncValidSync_11
node _source_valid_0_reset_T = asUInt(reset)
node _source_valid_0_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>(0h0))
node _source_valid_0_reset_T_2 = or(_source_valid_0_reset_T, _source_valid_0_reset_T_1)
node _source_valid_0_reset_T_3 = asAsyncReset(_source_valid_0_reset_T_2)
connect source_valid_0.reset, _source_valid_0_reset_T_3
node _source_valid_1_reset_T = asUInt(reset)
node _source_valid_1_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>(0h0))
node _source_valid_1_reset_T_2 = or(_source_valid_1_reset_T, _source_valid_1_reset_T_1)
node _source_valid_1_reset_T_3 = asAsyncReset(_source_valid_1_reset_T_2)
connect source_valid_1.reset, _source_valid_1_reset_T_3
node _sink_extend_reset_T = asUInt(reset)
node _sink_extend_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>(0h0))
node _sink_extend_reset_T_2 = or(_sink_extend_reset_T, _sink_extend_reset_T_1)
node _sink_extend_reset_T_3 = asAsyncReset(_sink_extend_reset_T_2)
connect sink_extend.reset, _sink_extend_reset_T_3
node _sink_valid_reset_T = asAsyncReset(reset)
connect sink_valid.reset, _sink_valid_reset_T
connect source_valid_0.clock, clock
connect source_valid_1.clock, clock
connect sink_extend.clock, clock
connect sink_valid.clock, clock
connect source_valid_0.io.in, UInt<1>(0h1)
connect source_valid_1.io.in, source_valid_0.io.out
connect io.async.safe.widx_valid, source_valid_1.io.out
connect sink_extend.io.in, io.async.safe.ridx_valid
connect sink_valid.io.in, sink_extend.io.out
connect sink_ready, sink_valid.io.out
node _io_async_safe_source_reset_n_T = asUInt(reset)
node _io_async_safe_source_reset_n_T_1 = eq(_io_async_safe_source_reset_n_T, UInt<1>(0h0))
connect io.async.safe.source_reset_n, _io_async_safe_source_reset_n_T_1 | module AsyncQueueSource_DebugInternalBundle( // @[AsyncQueue.scala:70:7]
input clock, // @[AsyncQueue.scala:70:7]
input reset, // @[AsyncQueue.scala:70:7]
output io_enq_ready, // @[AsyncQueue.scala:73:14]
input io_enq_valid, // @[AsyncQueue.scala:73:14]
input io_enq_bits_resumereq, // @[AsyncQueue.scala:73:14]
input [9:0] io_enq_bits_hartsel, // @[AsyncQueue.scala:73:14]
input io_enq_bits_ackhavereset, // @[AsyncQueue.scala:73:14]
input io_enq_bits_hasel, // @[AsyncQueue.scala:73:14]
input io_enq_bits_hamask_0, // @[AsyncQueue.scala:73:14]
input io_enq_bits_hamask_1, // @[AsyncQueue.scala:73:14]
input io_enq_bits_hamask_2, // @[AsyncQueue.scala:73:14]
input io_enq_bits_hamask_3, // @[AsyncQueue.scala:73:14]
input io_enq_bits_hamask_4, // @[AsyncQueue.scala:73:14]
input io_enq_bits_hamask_5, // @[AsyncQueue.scala:73:14]
input io_enq_bits_hamask_6, // @[AsyncQueue.scala:73:14]
input io_enq_bits_hamask_7, // @[AsyncQueue.scala:73:14]
input io_enq_bits_hrmask_0, // @[AsyncQueue.scala:73:14]
input io_enq_bits_hrmask_1, // @[AsyncQueue.scala:73:14]
input io_enq_bits_hrmask_2, // @[AsyncQueue.scala:73:14]
input io_enq_bits_hrmask_3, // @[AsyncQueue.scala:73:14]
input io_enq_bits_hrmask_4, // @[AsyncQueue.scala:73:14]
input io_enq_bits_hrmask_5, // @[AsyncQueue.scala:73:14]
input io_enq_bits_hrmask_6, // @[AsyncQueue.scala:73:14]
input io_enq_bits_hrmask_7, // @[AsyncQueue.scala:73:14]
output io_async_mem_0_resumereq, // @[AsyncQueue.scala:73:14]
output [9:0] io_async_mem_0_hartsel, // @[AsyncQueue.scala:73:14]
output io_async_mem_0_ackhavereset, // @[AsyncQueue.scala:73:14]
output io_async_mem_0_hasel, // @[AsyncQueue.scala:73:14]
output io_async_mem_0_hamask_0, // @[AsyncQueue.scala:73:14]
output io_async_mem_0_hamask_1, // @[AsyncQueue.scala:73:14]
output io_async_mem_0_hamask_2, // @[AsyncQueue.scala:73:14]
output io_async_mem_0_hamask_3, // @[AsyncQueue.scala:73:14]
output io_async_mem_0_hamask_4, // @[AsyncQueue.scala:73:14]
output io_async_mem_0_hamask_5, // @[AsyncQueue.scala:73:14]
output io_async_mem_0_hamask_6, // @[AsyncQueue.scala:73:14]
output io_async_mem_0_hamask_7, // @[AsyncQueue.scala:73:14]
output io_async_mem_0_hrmask_0, // @[AsyncQueue.scala:73:14]
output io_async_mem_0_hrmask_1, // @[AsyncQueue.scala:73:14]
output io_async_mem_0_hrmask_2, // @[AsyncQueue.scala:73:14]
output io_async_mem_0_hrmask_3, // @[AsyncQueue.scala:73:14]
output io_async_mem_0_hrmask_4, // @[AsyncQueue.scala:73:14]
output io_async_mem_0_hrmask_5, // @[AsyncQueue.scala:73:14]
output io_async_mem_0_hrmask_6, // @[AsyncQueue.scala:73:14]
output io_async_mem_0_hrmask_7, // @[AsyncQueue.scala:73:14]
input io_async_ridx, // @[AsyncQueue.scala:73:14]
output io_async_widx, // @[AsyncQueue.scala:73:14]
input io_async_safe_ridx_valid, // @[AsyncQueue.scala:73:14]
output io_async_safe_widx_valid, // @[AsyncQueue.scala:73:14]
output io_async_safe_source_reset_n, // @[AsyncQueue.scala:73:14]
input io_async_safe_sink_reset_n // @[AsyncQueue.scala:73:14]
);
wire _sink_extend_io_out; // @[AsyncQueue.scala:105:30]
wire _source_valid_0_io_out; // @[AsyncQueue.scala:102:32]
wire io_enq_valid_0 = io_enq_valid; // @[AsyncQueue.scala:70:7]
wire io_enq_bits_resumereq_0 = io_enq_bits_resumereq; // @[AsyncQueue.scala:70:7]
wire [9:0] io_enq_bits_hartsel_0 = io_enq_bits_hartsel; // @[AsyncQueue.scala:70:7]
wire io_enq_bits_ackhavereset_0 = io_enq_bits_ackhavereset; // @[AsyncQueue.scala:70:7]
wire io_enq_bits_hasel_0 = io_enq_bits_hasel; // @[AsyncQueue.scala:70:7]
wire io_enq_bits_hamask_0_0 = io_enq_bits_hamask_0; // @[AsyncQueue.scala:70:7]
wire io_enq_bits_hamask_1_0 = io_enq_bits_hamask_1; // @[AsyncQueue.scala:70:7]
wire io_enq_bits_hamask_2_0 = io_enq_bits_hamask_2; // @[AsyncQueue.scala:70:7]
wire io_enq_bits_hamask_3_0 = io_enq_bits_hamask_3; // @[AsyncQueue.scala:70:7]
wire io_enq_bits_hamask_4_0 = io_enq_bits_hamask_4; // @[AsyncQueue.scala:70:7]
wire io_enq_bits_hamask_5_0 = io_enq_bits_hamask_5; // @[AsyncQueue.scala:70:7]
wire io_enq_bits_hamask_6_0 = io_enq_bits_hamask_6; // @[AsyncQueue.scala:70:7]
wire io_enq_bits_hamask_7_0 = io_enq_bits_hamask_7; // @[AsyncQueue.scala:70:7]
wire io_enq_bits_hrmask_0_0 = io_enq_bits_hrmask_0; // @[AsyncQueue.scala:70:7]
wire io_enq_bits_hrmask_1_0 = io_enq_bits_hrmask_1; // @[AsyncQueue.scala:70:7]
wire io_enq_bits_hrmask_2_0 = io_enq_bits_hrmask_2; // @[AsyncQueue.scala:70:7]
wire io_enq_bits_hrmask_3_0 = io_enq_bits_hrmask_3; // @[AsyncQueue.scala:70:7]
wire io_enq_bits_hrmask_4_0 = io_enq_bits_hrmask_4; // @[AsyncQueue.scala:70:7]
wire io_enq_bits_hrmask_5_0 = io_enq_bits_hrmask_5; // @[AsyncQueue.scala:70:7]
wire io_enq_bits_hrmask_6_0 = io_enq_bits_hrmask_6; // @[AsyncQueue.scala:70:7]
wire io_enq_bits_hrmask_7_0 = io_enq_bits_hrmask_7; // @[AsyncQueue.scala:70:7]
wire io_async_ridx_0 = io_async_ridx; // @[AsyncQueue.scala:70:7]
wire io_async_safe_ridx_valid_0 = io_async_safe_ridx_valid; // @[AsyncQueue.scala:70:7]
wire io_async_safe_sink_reset_n_0 = io_async_safe_sink_reset_n; // @[AsyncQueue.scala:70:7]
wire _widx_T = reset; // @[AsyncQueue.scala:83:30]
wire _ready_reg_T = reset; // @[AsyncQueue.scala:90:35]
wire _widx_reg_T = reset; // @[AsyncQueue.scala:93:34]
wire _source_valid_0_reset_T = reset; // @[AsyncQueue.scala:107:36]
wire _source_valid_1_reset_T = reset; // @[AsyncQueue.scala:108:36]
wire _sink_extend_reset_T = reset; // @[AsyncQueue.scala:109:36]
wire _sink_valid_reset_T = reset; // @[AsyncQueue.scala:110:35]
wire _io_async_safe_source_reset_n_T = reset; // @[AsyncQueue.scala:123:34]
wire _widx_T_3 = 1'h0; // @[AsyncQueue.scala:54:32]
wire _io_enq_ready_T; // @[AsyncQueue.scala:91:29]
wire _io_async_safe_source_reset_n_T_1; // @[AsyncQueue.scala:123:27]
wire io_enq_ready_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_0_hamask_0_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_0_hamask_1_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_0_hamask_2_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_0_hamask_3_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_0_hamask_4_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_0_hamask_5_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_0_hamask_6_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_0_hamask_7_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_0_hrmask_0_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_0_hrmask_1_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_0_hrmask_2_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_0_hrmask_3_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_0_hrmask_4_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_0_hrmask_5_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_0_hrmask_6_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_0_hrmask_7_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_0_resumereq_0; // @[AsyncQueue.scala:70:7]
wire [9:0] io_async_mem_0_hartsel_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_0_ackhavereset_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_0_hasel_0; // @[AsyncQueue.scala:70:7]
wire io_async_safe_widx_valid_0; // @[AsyncQueue.scala:70:7]
wire io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:70:7]
wire io_async_widx_0; // @[AsyncQueue.scala:70:7]
wire sink_ready; // @[AsyncQueue.scala:81:28]
reg mem_0_resumereq; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_resumereq_0 = mem_0_resumereq; // @[AsyncQueue.scala:70:7, :82:16]
reg [9:0] mem_0_hartsel; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_hartsel_0 = mem_0_hartsel; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_0_ackhavereset; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_ackhavereset_0 = mem_0_ackhavereset; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_0_hasel; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_hasel_0 = mem_0_hasel; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_0_hamask_0; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_hamask_0_0 = mem_0_hamask_0; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_0_hamask_1; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_hamask_1_0 = mem_0_hamask_1; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_0_hamask_2; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_hamask_2_0 = mem_0_hamask_2; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_0_hamask_3; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_hamask_3_0 = mem_0_hamask_3; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_0_hamask_4; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_hamask_4_0 = mem_0_hamask_4; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_0_hamask_5; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_hamask_5_0 = mem_0_hamask_5; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_0_hamask_6; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_hamask_6_0 = mem_0_hamask_6; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_0_hamask_7; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_hamask_7_0 = mem_0_hamask_7; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_0_hrmask_0; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_hrmask_0_0 = mem_0_hrmask_0; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_0_hrmask_1; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_hrmask_1_0 = mem_0_hrmask_1; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_0_hrmask_2; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_hrmask_2_0 = mem_0_hrmask_2; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_0_hrmask_3; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_hrmask_3_0 = mem_0_hrmask_3; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_0_hrmask_4; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_hrmask_4_0 = mem_0_hrmask_4; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_0_hrmask_5; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_hrmask_5_0 = mem_0_hrmask_5; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_0_hrmask_6; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_hrmask_6_0 = mem_0_hrmask_6; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_0_hrmask_7; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_hrmask_7_0 = mem_0_hrmask_7; // @[AsyncQueue.scala:70:7, :82:16]
wire _widx_T_1 = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35]
wire _widx_T_2 = ~sink_ready; // @[AsyncQueue.scala:81:28, :83:77]
wire _widx_incremented_T_2; // @[AsyncQueue.scala:53:23]
wire widx_incremented; // @[AsyncQueue.scala:51:27]
wire widx = widx_incremented; // @[AsyncQueue.scala:51:27, :54:17]
reg widx_widx_bin; // @[AsyncQueue.scala:52:25]
wire [1:0] _widx_incremented_T = {1'h0, widx_widx_bin} + {1'h0, _widx_T_1}; // @[Decoupled.scala:51:35]
wire _widx_incremented_T_1 = _widx_incremented_T[0]; // @[AsyncQueue.scala:53:43]
assign _widx_incremented_T_2 = ~_widx_T_2 & _widx_incremented_T_1; // @[AsyncQueue.scala:53:{23,43}, :83:77]
assign widx_incremented = _widx_incremented_T_2; // @[AsyncQueue.scala:51:27, :53:23]
wire ridx; // @[ShiftReg.scala:48:24]
wire _ready_T = ~ridx; // @[ShiftReg.scala:48:24]
wire _ready_T_1 = widx != _ready_T; // @[AsyncQueue.scala:54:17, :85:{34,44}]
wire ready = sink_ready & _ready_T_1; // @[AsyncQueue.scala:81:28, :85:{26,34}]
reg ready_reg; // @[AsyncQueue.scala:90:56]
assign _io_enq_ready_T = ready_reg & sink_ready; // @[AsyncQueue.scala:81:28, :90:56, :91:29]
assign io_enq_ready_0 = _io_enq_ready_T; // @[AsyncQueue.scala:70:7, :91:29]
reg widx_gray; // @[AsyncQueue.scala:93:55]
assign io_async_widx_0 = widx_gray; // @[AsyncQueue.scala:70:7, :93:55]
wire _source_valid_0_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46]
wire _source_valid_0_reset_T_2 = _source_valid_0_reset_T | _source_valid_0_reset_T_1; // @[AsyncQueue.scala:107:{36,43,46}]
wire _source_valid_0_reset_T_3 = _source_valid_0_reset_T_2; // @[AsyncQueue.scala:107:{43,65}]
wire _source_valid_1_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46, :108:46]
wire _source_valid_1_reset_T_2 = _source_valid_1_reset_T | _source_valid_1_reset_T_1; // @[AsyncQueue.scala:108:{36,43,46}]
wire _source_valid_1_reset_T_3 = _source_valid_1_reset_T_2; // @[AsyncQueue.scala:108:{43,65}]
wire _sink_extend_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46, :109:46]
wire _sink_extend_reset_T_2 = _sink_extend_reset_T | _sink_extend_reset_T_1; // @[AsyncQueue.scala:109:{36,43,46}]
wire _sink_extend_reset_T_3 = _sink_extend_reset_T_2; // @[AsyncQueue.scala:109:{43,65}]
assign _io_async_safe_source_reset_n_T_1 = ~_io_async_safe_source_reset_n_T; // @[AsyncQueue.scala:123:{27,34}]
assign io_async_safe_source_reset_n_0 = _io_async_safe_source_reset_n_T_1; // @[AsyncQueue.scala:70:7, :123:27]
always @(posedge clock) begin // @[AsyncQueue.scala:70:7]
if (_widx_T_1) begin // @[Decoupled.scala:51:35]
mem_0_resumereq <= io_enq_bits_resumereq_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_hartsel <= io_enq_bits_hartsel_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_ackhavereset <= io_enq_bits_ackhavereset_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_hasel <= io_enq_bits_hasel_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_hamask_0 <= io_enq_bits_hamask_0_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_hamask_1 <= io_enq_bits_hamask_1_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_hamask_2 <= io_enq_bits_hamask_2_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_hamask_3 <= io_enq_bits_hamask_3_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_hamask_4 <= io_enq_bits_hamask_4_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_hamask_5 <= io_enq_bits_hamask_5_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_hamask_6 <= io_enq_bits_hamask_6_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_hamask_7 <= io_enq_bits_hamask_7_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_hrmask_0 <= io_enq_bits_hrmask_0_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_hrmask_1 <= io_enq_bits_hrmask_1_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_hrmask_2 <= io_enq_bits_hrmask_2_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_hrmask_3 <= io_enq_bits_hrmask_3_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_hrmask_4 <= io_enq_bits_hrmask_4_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_hrmask_5 <= io_enq_bits_hrmask_5_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_hrmask_6 <= io_enq_bits_hrmask_6_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_hrmask_7 <= io_enq_bits_hrmask_7_0; // @[AsyncQueue.scala:70:7, :82:16]
end
always @(posedge)
always @(posedge clock or posedge _widx_T) begin // @[AsyncQueue.scala:70:7, :83:30]
if (_widx_T) // @[AsyncQueue.scala:70:7, :83:30]
widx_widx_bin <= 1'h0; // @[AsyncQueue.scala:52:25]
else // @[AsyncQueue.scala:70:7]
widx_widx_bin <= widx_incremented; // @[AsyncQueue.scala:51:27, :52:25]
always @(posedge, posedge)
always @(posedge clock or posedge _ready_reg_T) begin // @[AsyncQueue.scala:70:7, :90:35]
if (_ready_reg_T) // @[AsyncQueue.scala:70:7, :90:35]
ready_reg <= 1'h0; // @[AsyncQueue.scala:90:56]
else // @[AsyncQueue.scala:70:7]
ready_reg <= ready; // @[AsyncQueue.scala:85:26, :90:56]
always @(posedge, posedge)
always @(posedge clock or posedge _widx_reg_T) begin // @[AsyncQueue.scala:70:7, :93:34]
if (_widx_reg_T) // @[AsyncQueue.scala:70:7, :93:34]
widx_gray <= 1'h0; // @[AsyncQueue.scala:93:55]
else // @[AsyncQueue.scala:70:7]
widx_gray <= widx; // @[AsyncQueue.scala:54:17, :93:55]
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53_1 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>}
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _roundMagUp_T = and(roundingMode_min, io.in.sign)
node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0))
node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1)
node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2)
node adjustedSig = shl(io.in.sig, 0)
wire common_expOut : UInt<12>
wire common_fractOut : UInt<52>
wire common_overflow : UInt<1>
wire common_totalUnderflow : UInt<1>
wire common_underflow : UInt<1>
wire common_inexact : UInt<1>
node _roundMask_T = bits(io.in.sExp, 11, 0)
node _roundMask_T_1 = not(_roundMask_T)
node roundMask_msb = bits(_roundMask_T_1, 11, 11)
node roundMask_lsbs = bits(_roundMask_T_1, 10, 0)
node roundMask_msb_1 = bits(roundMask_lsbs, 10, 10)
node roundMask_lsbs_1 = bits(roundMask_lsbs, 9, 0)
node roundMask_msb_2 = bits(roundMask_lsbs_1, 9, 9)
node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 8, 0)
node roundMask_msb_3 = bits(roundMask_lsbs_2, 8, 8)
node roundMask_lsbs_3 = bits(roundMask_lsbs_2, 7, 0)
node roundMask_msb_4 = bits(roundMask_lsbs_3, 7, 7)
node roundMask_lsbs_4 = bits(roundMask_lsbs_3, 6, 0)
node roundMask_msb_5 = bits(roundMask_lsbs_4, 6, 6)
node roundMask_lsbs_5 = bits(roundMask_lsbs_4, 5, 0)
node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_5)
node _roundMask_T_2 = bits(roundMask_shift, 63, 13)
node _roundMask_T_3 = bits(_roundMask_T_2, 31, 0)
node _roundMask_T_4 = shl(UInt<16>(0hffff), 16)
node _roundMask_T_5 = xor(UInt<32>(0hffffffff), _roundMask_T_4)
node _roundMask_T_6 = shr(_roundMask_T_3, 16)
node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5)
node _roundMask_T_8 = bits(_roundMask_T_3, 15, 0)
node _roundMask_T_9 = shl(_roundMask_T_8, 16)
node _roundMask_T_10 = not(_roundMask_T_5)
node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10)
node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11)
node _roundMask_T_13 = bits(_roundMask_T_5, 23, 0)
node _roundMask_T_14 = shl(_roundMask_T_13, 8)
node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14)
node _roundMask_T_16 = shr(_roundMask_T_12, 8)
node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15)
node _roundMask_T_18 = bits(_roundMask_T_12, 23, 0)
node _roundMask_T_19 = shl(_roundMask_T_18, 8)
node _roundMask_T_20 = not(_roundMask_T_15)
node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20)
node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21)
node _roundMask_T_23 = bits(_roundMask_T_15, 27, 0)
node _roundMask_T_24 = shl(_roundMask_T_23, 4)
node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24)
node _roundMask_T_26 = shr(_roundMask_T_22, 4)
node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25)
node _roundMask_T_28 = bits(_roundMask_T_22, 27, 0)
node _roundMask_T_29 = shl(_roundMask_T_28, 4)
node _roundMask_T_30 = not(_roundMask_T_25)
node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30)
node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31)
node _roundMask_T_33 = bits(_roundMask_T_25, 29, 0)
node _roundMask_T_34 = shl(_roundMask_T_33, 2)
node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34)
node _roundMask_T_36 = shr(_roundMask_T_32, 2)
node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35)
node _roundMask_T_38 = bits(_roundMask_T_32, 29, 0)
node _roundMask_T_39 = shl(_roundMask_T_38, 2)
node _roundMask_T_40 = not(_roundMask_T_35)
node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40)
node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41)
node _roundMask_T_43 = bits(_roundMask_T_35, 30, 0)
node _roundMask_T_44 = shl(_roundMask_T_43, 1)
node _roundMask_T_45 = xor(_roundMask_T_35, _roundMask_T_44)
node _roundMask_T_46 = shr(_roundMask_T_42, 1)
node _roundMask_T_47 = and(_roundMask_T_46, _roundMask_T_45)
node _roundMask_T_48 = bits(_roundMask_T_42, 30, 0)
node _roundMask_T_49 = shl(_roundMask_T_48, 1)
node _roundMask_T_50 = not(_roundMask_T_45)
node _roundMask_T_51 = and(_roundMask_T_49, _roundMask_T_50)
node _roundMask_T_52 = or(_roundMask_T_47, _roundMask_T_51)
node _roundMask_T_53 = bits(_roundMask_T_2, 50, 32)
node _roundMask_T_54 = bits(_roundMask_T_53, 15, 0)
node _roundMask_T_55 = shl(UInt<8>(0hff), 8)
node _roundMask_T_56 = xor(UInt<16>(0hffff), _roundMask_T_55)
node _roundMask_T_57 = shr(_roundMask_T_54, 8)
node _roundMask_T_58 = and(_roundMask_T_57, _roundMask_T_56)
node _roundMask_T_59 = bits(_roundMask_T_54, 7, 0)
node _roundMask_T_60 = shl(_roundMask_T_59, 8)
node _roundMask_T_61 = not(_roundMask_T_56)
node _roundMask_T_62 = and(_roundMask_T_60, _roundMask_T_61)
node _roundMask_T_63 = or(_roundMask_T_58, _roundMask_T_62)
node _roundMask_T_64 = bits(_roundMask_T_56, 11, 0)
node _roundMask_T_65 = shl(_roundMask_T_64, 4)
node _roundMask_T_66 = xor(_roundMask_T_56, _roundMask_T_65)
node _roundMask_T_67 = shr(_roundMask_T_63, 4)
node _roundMask_T_68 = and(_roundMask_T_67, _roundMask_T_66)
node _roundMask_T_69 = bits(_roundMask_T_63, 11, 0)
node _roundMask_T_70 = shl(_roundMask_T_69, 4)
node _roundMask_T_71 = not(_roundMask_T_66)
node _roundMask_T_72 = and(_roundMask_T_70, _roundMask_T_71)
node _roundMask_T_73 = or(_roundMask_T_68, _roundMask_T_72)
node _roundMask_T_74 = bits(_roundMask_T_66, 13, 0)
node _roundMask_T_75 = shl(_roundMask_T_74, 2)
node _roundMask_T_76 = xor(_roundMask_T_66, _roundMask_T_75)
node _roundMask_T_77 = shr(_roundMask_T_73, 2)
node _roundMask_T_78 = and(_roundMask_T_77, _roundMask_T_76)
node _roundMask_T_79 = bits(_roundMask_T_73, 13, 0)
node _roundMask_T_80 = shl(_roundMask_T_79, 2)
node _roundMask_T_81 = not(_roundMask_T_76)
node _roundMask_T_82 = and(_roundMask_T_80, _roundMask_T_81)
node _roundMask_T_83 = or(_roundMask_T_78, _roundMask_T_82)
node _roundMask_T_84 = bits(_roundMask_T_76, 14, 0)
node _roundMask_T_85 = shl(_roundMask_T_84, 1)
node _roundMask_T_86 = xor(_roundMask_T_76, _roundMask_T_85)
node _roundMask_T_87 = shr(_roundMask_T_83, 1)
node _roundMask_T_88 = and(_roundMask_T_87, _roundMask_T_86)
node _roundMask_T_89 = bits(_roundMask_T_83, 14, 0)
node _roundMask_T_90 = shl(_roundMask_T_89, 1)
node _roundMask_T_91 = not(_roundMask_T_86)
node _roundMask_T_92 = and(_roundMask_T_90, _roundMask_T_91)
node _roundMask_T_93 = or(_roundMask_T_88, _roundMask_T_92)
node _roundMask_T_94 = bits(_roundMask_T_53, 18, 16)
node _roundMask_T_95 = bits(_roundMask_T_94, 1, 0)
node _roundMask_T_96 = bits(_roundMask_T_95, 0, 0)
node _roundMask_T_97 = bits(_roundMask_T_95, 1, 1)
node _roundMask_T_98 = cat(_roundMask_T_96, _roundMask_T_97)
node _roundMask_T_99 = bits(_roundMask_T_94, 2, 2)
node _roundMask_T_100 = cat(_roundMask_T_98, _roundMask_T_99)
node _roundMask_T_101 = cat(_roundMask_T_93, _roundMask_T_100)
node _roundMask_T_102 = cat(_roundMask_T_52, _roundMask_T_101)
node _roundMask_T_103 = not(_roundMask_T_102)
node _roundMask_T_104 = mux(roundMask_msb_5, UInt<1>(0h0), _roundMask_T_103)
node _roundMask_T_105 = not(_roundMask_T_104)
node _roundMask_T_106 = not(_roundMask_T_105)
node _roundMask_T_107 = mux(roundMask_msb_4, UInt<1>(0h0), _roundMask_T_106)
node _roundMask_T_108 = not(_roundMask_T_107)
node _roundMask_T_109 = not(_roundMask_T_108)
node _roundMask_T_110 = mux(roundMask_msb_3, UInt<1>(0h0), _roundMask_T_109)
node _roundMask_T_111 = not(_roundMask_T_110)
node _roundMask_T_112 = not(_roundMask_T_111)
node _roundMask_T_113 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_112)
node _roundMask_T_114 = not(_roundMask_T_113)
node _roundMask_T_115 = cat(_roundMask_T_114, UInt<3>(0h7))
node roundMask_msb_6 = bits(roundMask_lsbs_1, 9, 9)
node roundMask_lsbs_6 = bits(roundMask_lsbs_1, 8, 0)
node roundMask_msb_7 = bits(roundMask_lsbs_6, 8, 8)
node roundMask_lsbs_7 = bits(roundMask_lsbs_6, 7, 0)
node roundMask_msb_8 = bits(roundMask_lsbs_7, 7, 7)
node roundMask_lsbs_8 = bits(roundMask_lsbs_7, 6, 0)
node roundMask_msb_9 = bits(roundMask_lsbs_8, 6, 6)
node roundMask_lsbs_9 = bits(roundMask_lsbs_8, 5, 0)
node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_9)
node _roundMask_T_116 = bits(roundMask_shift_1, 2, 0)
node _roundMask_T_117 = bits(_roundMask_T_116, 1, 0)
node _roundMask_T_118 = bits(_roundMask_T_117, 0, 0)
node _roundMask_T_119 = bits(_roundMask_T_117, 1, 1)
node _roundMask_T_120 = cat(_roundMask_T_118, _roundMask_T_119)
node _roundMask_T_121 = bits(_roundMask_T_116, 2, 2)
node _roundMask_T_122 = cat(_roundMask_T_120, _roundMask_T_121)
node _roundMask_T_123 = mux(roundMask_msb_9, _roundMask_T_122, UInt<1>(0h0))
node _roundMask_T_124 = mux(roundMask_msb_8, _roundMask_T_123, UInt<1>(0h0))
node _roundMask_T_125 = mux(roundMask_msb_7, _roundMask_T_124, UInt<1>(0h0))
node _roundMask_T_126 = mux(roundMask_msb_6, _roundMask_T_125, UInt<1>(0h0))
node _roundMask_T_127 = mux(roundMask_msb_1, _roundMask_T_115, _roundMask_T_126)
node _roundMask_T_128 = mux(roundMask_msb, _roundMask_T_127, UInt<1>(0h0))
node _roundMask_T_129 = or(_roundMask_T_128, UInt<1>(0h0))
node roundMask = cat(_roundMask_T_129, UInt<2>(0h3))
node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask)
node shiftedRoundMask = shr(_shiftedRoundMask_T, 1)
node _roundPosMask_T = not(shiftedRoundMask)
node roundPosMask = and(_roundPosMask_T, roundMask)
node _roundPosBit_T = and(adjustedSig, roundPosMask)
node roundPosBit = orr(_roundPosBit_T)
node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask)
node anyRoundExtra = orr(_anyRoundExtra_T)
node anyRound = or(roundPosBit, anyRoundExtra)
node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit)
node _roundIncr_T_2 = and(roundMagUp, anyRound)
node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2)
node _roundedSig_T = or(adjustedSig, roundMask)
node _roundedSig_T_1 = shr(_roundedSig_T, 2)
node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1))
node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit)
node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0))
node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4)
node _roundedSig_T_6 = shr(roundMask, 1)
node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<55>(0h0))
node _roundedSig_T_8 = not(_roundedSig_T_7)
node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8)
node _roundedSig_T_10 = not(roundMask)
node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10)
node _roundedSig_T_12 = shr(_roundedSig_T_11, 2)
node _roundedSig_T_13 = and(roundingMode_odd, anyRound)
node _roundedSig_T_14 = shr(roundPosMask, 1)
node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0))
node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15)
node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16)
node _sRoundedExp_T = shr(roundedSig, 53)
node _sRoundedExp_T_1 = cvt(_sRoundedExp_T)
node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1)
node _common_expOut_T = bits(sRoundedExp, 11, 0)
connect common_expOut, _common_expOut_T
node _common_fractOut_T = bits(roundedSig, 52, 1)
node _common_fractOut_T_1 = bits(roundedSig, 51, 0)
node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1)
connect common_fractOut, _common_fractOut_T_2
node _common_overflow_T = shr(sRoundedExp, 10)
node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3)))
connect common_overflow, _common_overflow_T_1
node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<11>(0h3ce)))
connect common_totalUnderflow, _common_totalUnderflow_T
node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2)
node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1)
node unboundedRange_roundPosBit = mux(UInt<1>(0h0), _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1)
node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2)
node _unboundedRange_anyRound_T_1 = and(UInt<1>(0h0), _unboundedRange_anyRound_T)
node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0)
node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2)
node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3)
node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit)
node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound)
node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2)
node _roundCarry_T = bits(roundedSig, 54, 54)
node _roundCarry_T_1 = bits(roundedSig, 53, 53)
node roundCarry = mux(UInt<1>(0h0), _roundCarry_T, _roundCarry_T_1)
node _common_underflow_T = shr(io.in.sExp, 11)
node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0)))
node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1)
node _common_underflow_T_3 = bits(roundMask, 3, 3)
node _common_underflow_T_4 = bits(roundMask, 2, 2)
node _common_underflow_T_5 = mux(UInt<1>(0h0), _common_underflow_T_3, _common_underflow_T_4)
node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5)
node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1))
node _common_underflow_T_8 = bits(roundMask, 4, 4)
node _common_underflow_T_9 = bits(roundMask, 3, 3)
node _common_underflow_T_10 = mux(UInt<1>(0h0), _common_underflow_T_8, _common_underflow_T_9)
node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0))
node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11)
node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry)
node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit)
node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr)
node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0))
node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16)
node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17)
connect common_underflow, _common_underflow_T_18
node _common_inexact_T = or(common_totalUnderflow, anyRound)
connect common_inexact, _common_inexact_T
node isNaNOut = or(io.invalidExc, io.in.isNaN)
node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf)
node _commonCase_T = eq(isNaNOut, UInt<1>(0h0))
node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0))
node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1)
node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0))
node commonCase = and(_commonCase_T_2, _commonCase_T_3)
node overflow = and(commonCase, common_overflow)
node underflow = and(commonCase, common_underflow)
node _inexact_T = and(commonCase, common_inexact)
node inexact = or(overflow, _inexact_T)
node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp)
node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow)
node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd)
node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1)
node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0))
node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T)
node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp)
node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T)
node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign)
node _expOut_T = or(io.in.isZero, common_totalUnderflow)
node _expOut_T_1 = mux(_expOut_T, UInt<12>(0he00), UInt<1>(0h0))
node _expOut_T_2 = not(_expOut_T_1)
node _expOut_T_3 = and(common_expOut, _expOut_T_2)
node _expOut_T_4 = not(UInt<12>(0h3ce))
node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0))
node _expOut_T_6 = not(_expOut_T_5)
node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6)
node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<12>(0h400), UInt<1>(0h0))
node _expOut_T_9 = not(_expOut_T_8)
node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9)
node _expOut_T_11 = mux(notNaN_isInfOut, UInt<12>(0h200), UInt<1>(0h0))
node _expOut_T_12 = not(_expOut_T_11)
node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12)
node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<12>(0h3ce), UInt<1>(0h0))
node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14)
node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<12>(0hbff), UInt<1>(0h0))
node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16)
node _expOut_T_18 = mux(notNaN_isInfOut, UInt<12>(0hc00), UInt<1>(0h0))
node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18)
node _expOut_T_20 = mux(isNaNOut, UInt<12>(0he00), UInt<1>(0h0))
node expOut = or(_expOut_T_19, _expOut_T_20)
node _fractOut_T = or(isNaNOut, io.in.isZero)
node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow)
node _fractOut_T_2 = mux(isNaNOut, UInt<52>(0h8000000000000), UInt<1>(0h0))
node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut)
node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<52>(0hfffffffffffff), UInt<52>(0h0))
node fractOut = or(_fractOut_T_3, _fractOut_T_4)
node _io_out_T = cat(signOut, expOut)
node _io_out_T_1 = cat(_io_out_T, fractOut)
connect io.out, _io_out_T_1
node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc)
node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow)
node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact)
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53_1( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_infiniteExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [12:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [55:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [64:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc_0 = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [12:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [55:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [31:0] _roundMask_T_5 = 32'hFFFF; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_4 = 32'hFFFF0000; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_10 = 32'hFFFF0000; // @[primitives.scala:77:20]
wire [23:0] _roundMask_T_13 = 24'hFFFF; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_14 = 32'hFFFF00; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_15 = 32'hFF00FF; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_20 = 32'hFF00FF00; // @[primitives.scala:77:20]
wire [27:0] _roundMask_T_23 = 28'hFF00FF; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_24 = 32'hFF00FF0; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_25 = 32'hF0F0F0F; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_30 = 32'hF0F0F0F0; // @[primitives.scala:77:20]
wire [29:0] _roundMask_T_33 = 30'hF0F0F0F; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_34 = 32'h3C3C3C3C; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_35 = 32'h33333333; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_40 = 32'hCCCCCCCC; // @[primitives.scala:77:20]
wire [30:0] _roundMask_T_43 = 31'h33333333; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_44 = 32'h66666666; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_45 = 32'h55555555; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_50 = 32'hAAAAAAAA; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_56 = 16'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_55 = 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_61 = 16'hFF00; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_64 = 12'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_65 = 16'hFF0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_66 = 16'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_71 = 16'hF0F0; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_74 = 14'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_75 = 16'h3C3C; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_76 = 16'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_81 = 16'hCCCC; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_84 = 15'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_85 = 16'h6666; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_86 = 16'h5555; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_91 = 16'hAAAA; // @[primitives.scala:77:20]
wire _common_underflow_T_16 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:27]
wire [11:0] _expOut_T_4 = 12'hC31; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire io_detectTininess = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire _unboundedRange_anyRound_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:205:30]
wire _common_underflow_T_7 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:222:49]
wire _common_underflow_T_12 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:222:77]
wire _common_underflow_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:226:38]
wire _common_underflow_T_14 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:227:45]
wire _common_underflow_T_15 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:227:60]
wire [55:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22]
wire [64:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66]
wire [64:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53]
wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53]
wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53]
wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53]
wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53]
wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53]
wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}]
wire roundMagUp = _roundMagUp_T | _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}]
wire [11:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37]
wire [11:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [51:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16]
wire [51:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50]
wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31]
wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40]
wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49]
wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire [11:0] _roundMask_T = io_in_sExp_0[11:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37]
wire [11:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21]
wire roundMask_msb = _roundMask_T_1[11]; // @[primitives.scala:52:21, :58:25]
wire [10:0] roundMask_lsbs = _roundMask_T_1[10:0]; // @[primitives.scala:52:21, :59:26]
wire roundMask_msb_1 = roundMask_lsbs[10]; // @[primitives.scala:58:25, :59:26]
wire [9:0] roundMask_lsbs_1 = roundMask_lsbs[9:0]; // @[primitives.scala:59:26]
wire roundMask_msb_2 = roundMask_lsbs_1[9]; // @[primitives.scala:58:25, :59:26]
wire roundMask_msb_6 = roundMask_lsbs_1[9]; // @[primitives.scala:58:25, :59:26]
wire [8:0] roundMask_lsbs_2 = roundMask_lsbs_1[8:0]; // @[primitives.scala:59:26]
wire [8:0] roundMask_lsbs_6 = roundMask_lsbs_1[8:0]; // @[primitives.scala:59:26]
wire roundMask_msb_3 = roundMask_lsbs_2[8]; // @[primitives.scala:58:25, :59:26]
wire [7:0] roundMask_lsbs_3 = roundMask_lsbs_2[7:0]; // @[primitives.scala:59:26]
wire roundMask_msb_4 = roundMask_lsbs_3[7]; // @[primitives.scala:58:25, :59:26]
wire [6:0] roundMask_lsbs_4 = roundMask_lsbs_3[6:0]; // @[primitives.scala:59:26]
wire roundMask_msb_5 = roundMask_lsbs_4[6]; // @[primitives.scala:58:25, :59:26]
wire [5:0] roundMask_lsbs_5 = roundMask_lsbs_4[5:0]; // @[primitives.scala:59:26]
wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_5); // @[primitives.scala:59:26, :76:56]
wire [50:0] _roundMask_T_2 = roundMask_shift[63:13]; // @[primitives.scala:76:56, :78:22]
wire [31:0] _roundMask_T_3 = _roundMask_T_2[31:0]; // @[primitives.scala:77:20, :78:22]
wire [15:0] _roundMask_T_6 = _roundMask_T_3[31:16]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_7 = {16'h0, _roundMask_T_6}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_8 = _roundMask_T_3[15:0]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_9 = {_roundMask_T_8, 16'h0}; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_11 = _roundMask_T_9 & 32'hFFFF0000; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20]
wire [23:0] _roundMask_T_16 = _roundMask_T_12[31:8]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_17 = {8'h0, _roundMask_T_16 & 24'hFF00FF}; // @[primitives.scala:77:20]
wire [23:0] _roundMask_T_18 = _roundMask_T_12[23:0]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_19 = {_roundMask_T_18, 8'h0}; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_21 = _roundMask_T_19 & 32'hFF00FF00; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20]
wire [27:0] _roundMask_T_26 = _roundMask_T_22[31:4]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_27 = {4'h0, _roundMask_T_26 & 28'hF0F0F0F}; // @[primitives.scala:77:20]
wire [27:0] _roundMask_T_28 = _roundMask_T_22[27:0]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_29 = {_roundMask_T_28, 4'h0}; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_31 = _roundMask_T_29 & 32'hF0F0F0F0; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20]
wire [29:0] _roundMask_T_36 = _roundMask_T_32[31:2]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_37 = {2'h0, _roundMask_T_36 & 30'h33333333}; // @[primitives.scala:77:20]
wire [29:0] _roundMask_T_38 = _roundMask_T_32[29:0]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_39 = {_roundMask_T_38, 2'h0}; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_41 = _roundMask_T_39 & 32'hCCCCCCCC; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20]
wire [30:0] _roundMask_T_46 = _roundMask_T_42[31:1]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_47 = {1'h0, _roundMask_T_46 & 31'h55555555}; // @[primitives.scala:77:20]
wire [30:0] _roundMask_T_48 = _roundMask_T_42[30:0]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_49 = {_roundMask_T_48, 1'h0}; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_51 = _roundMask_T_49 & 32'hAAAAAAAA; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_52 = _roundMask_T_47 | _roundMask_T_51; // @[primitives.scala:77:20]
wire [18:0] _roundMask_T_53 = _roundMask_T_2[50:32]; // @[primitives.scala:77:20, :78:22]
wire [15:0] _roundMask_T_54 = _roundMask_T_53[15:0]; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_57 = _roundMask_T_54[15:8]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_58 = {8'h0, _roundMask_T_57}; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_59 = _roundMask_T_54[7:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_60 = {_roundMask_T_59, 8'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_62 = _roundMask_T_60 & 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_63 = _roundMask_T_58 | _roundMask_T_62; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_67 = _roundMask_T_63[15:4]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_68 = {4'h0, _roundMask_T_67 & 12'hF0F}; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_69 = _roundMask_T_63[11:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_70 = {_roundMask_T_69, 4'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_72 = _roundMask_T_70 & 16'hF0F0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_73 = _roundMask_T_68 | _roundMask_T_72; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_77 = _roundMask_T_73[15:2]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_78 = {2'h0, _roundMask_T_77 & 14'h3333}; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_79 = _roundMask_T_73[13:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_80 = {_roundMask_T_79, 2'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_82 = _roundMask_T_80 & 16'hCCCC; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_83 = _roundMask_T_78 | _roundMask_T_82; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_87 = _roundMask_T_83[15:1]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_88 = {1'h0, _roundMask_T_87 & 15'h5555}; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_89 = _roundMask_T_83[14:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_90 = {_roundMask_T_89, 1'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_92 = _roundMask_T_90 & 16'hAAAA; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_93 = _roundMask_T_88 | _roundMask_T_92; // @[primitives.scala:77:20]
wire [2:0] _roundMask_T_94 = _roundMask_T_53[18:16]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_95 = _roundMask_T_94[1:0]; // @[primitives.scala:77:20]
wire _roundMask_T_96 = _roundMask_T_95[0]; // @[primitives.scala:77:20]
wire _roundMask_T_97 = _roundMask_T_95[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_98 = {_roundMask_T_96, _roundMask_T_97}; // @[primitives.scala:77:20]
wire _roundMask_T_99 = _roundMask_T_94[2]; // @[primitives.scala:77:20]
wire [2:0] _roundMask_T_100 = {_roundMask_T_98, _roundMask_T_99}; // @[primitives.scala:77:20]
wire [18:0] _roundMask_T_101 = {_roundMask_T_93, _roundMask_T_100}; // @[primitives.scala:77:20]
wire [50:0] _roundMask_T_102 = {_roundMask_T_52, _roundMask_T_101}; // @[primitives.scala:77:20]
wire [50:0] _roundMask_T_103 = ~_roundMask_T_102; // @[primitives.scala:73:32, :77:20]
wire [50:0] _roundMask_T_104 = roundMask_msb_5 ? 51'h0 : _roundMask_T_103; // @[primitives.scala:58:25, :73:{21,32}]
wire [50:0] _roundMask_T_105 = ~_roundMask_T_104; // @[primitives.scala:73:{17,21}]
wire [50:0] _roundMask_T_106 = ~_roundMask_T_105; // @[primitives.scala:73:{17,32}]
wire [50:0] _roundMask_T_107 = roundMask_msb_4 ? 51'h0 : _roundMask_T_106; // @[primitives.scala:58:25, :73:{21,32}]
wire [50:0] _roundMask_T_108 = ~_roundMask_T_107; // @[primitives.scala:73:{17,21}]
wire [50:0] _roundMask_T_109 = ~_roundMask_T_108; // @[primitives.scala:73:{17,32}]
wire [50:0] _roundMask_T_110 = roundMask_msb_3 ? 51'h0 : _roundMask_T_109; // @[primitives.scala:58:25, :73:{21,32}]
wire [50:0] _roundMask_T_111 = ~_roundMask_T_110; // @[primitives.scala:73:{17,21}]
wire [50:0] _roundMask_T_112 = ~_roundMask_T_111; // @[primitives.scala:73:{17,32}]
wire [50:0] _roundMask_T_113 = roundMask_msb_2 ? 51'h0 : _roundMask_T_112; // @[primitives.scala:58:25, :73:{21,32}]
wire [50:0] _roundMask_T_114 = ~_roundMask_T_113; // @[primitives.scala:73:{17,21}]
wire [53:0] _roundMask_T_115 = {_roundMask_T_114, 3'h7}; // @[primitives.scala:68:58, :73:17]
wire roundMask_msb_7 = roundMask_lsbs_6[8]; // @[primitives.scala:58:25, :59:26]
wire [7:0] roundMask_lsbs_7 = roundMask_lsbs_6[7:0]; // @[primitives.scala:59:26]
wire roundMask_msb_8 = roundMask_lsbs_7[7]; // @[primitives.scala:58:25, :59:26]
wire [6:0] roundMask_lsbs_8 = roundMask_lsbs_7[6:0]; // @[primitives.scala:59:26]
wire roundMask_msb_9 = roundMask_lsbs_8[6]; // @[primitives.scala:58:25, :59:26]
wire [5:0] roundMask_lsbs_9 = roundMask_lsbs_8[5:0]; // @[primitives.scala:59:26]
wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_9); // @[primitives.scala:59:26, :76:56]
wire [2:0] _roundMask_T_116 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22]
wire [1:0] _roundMask_T_117 = _roundMask_T_116[1:0]; // @[primitives.scala:77:20, :78:22]
wire _roundMask_T_118 = _roundMask_T_117[0]; // @[primitives.scala:77:20]
wire _roundMask_T_119 = _roundMask_T_117[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_120 = {_roundMask_T_118, _roundMask_T_119}; // @[primitives.scala:77:20]
wire _roundMask_T_121 = _roundMask_T_116[2]; // @[primitives.scala:77:20, :78:22]
wire [2:0] _roundMask_T_122 = {_roundMask_T_120, _roundMask_T_121}; // @[primitives.scala:77:20]
wire [2:0] _roundMask_T_123 = roundMask_msb_9 ? _roundMask_T_122 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20]
wire [2:0] _roundMask_T_124 = roundMask_msb_8 ? _roundMask_T_123 : 3'h0; // @[primitives.scala:58:25, :62:24]
wire [2:0] _roundMask_T_125 = roundMask_msb_7 ? _roundMask_T_124 : 3'h0; // @[primitives.scala:58:25, :62:24]
wire [2:0] _roundMask_T_126 = roundMask_msb_6 ? _roundMask_T_125 : 3'h0; // @[primitives.scala:58:25, :62:24]
wire [53:0] _roundMask_T_127 = roundMask_msb_1 ? _roundMask_T_115 : {51'h0, _roundMask_T_126}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58]
wire [53:0] _roundMask_T_128 = roundMask_msb ? _roundMask_T_127 : 54'h0; // @[primitives.scala:58:25, :62:24, :67:24]
wire [53:0] _roundMask_T_129 = _roundMask_T_128; // @[primitives.scala:62:24]
wire [55:0] roundMask = {_roundMask_T_129, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}]
wire [56:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41]
wire [55:0] shiftedRoundMask = _shiftedRoundMask_T[56:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}]
wire [55:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28]
wire [55:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}]
wire [55:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40]
wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}]
wire [55:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42]
wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}]
wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36]
wire _GEN = roundingMode_near_even | roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38]
wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38]
assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38]
wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38]
assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38]
wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32]
assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32]
wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}]
wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29]
wire roundIncr = _roundIncr_T_1 | _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29]
wire [55:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32]
wire [53:0] _roundedSig_T_1 = _roundedSig_T[55:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}]
wire [54:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 55'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}]
wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49]
wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30]
wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30]
wire [54:0] _roundedSig_T_6 = roundMask[55:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35]
wire [54:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 55'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35]
wire [54:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}]
wire [54:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21]
wire [55:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32]
wire [55:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}]
wire [53:0] _roundedSig_T_12 = _roundedSig_T_11[55:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}]
wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42]
wire [54:0] _roundedSig_T_14 = roundPosMask[55:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67]
wire [54:0] _roundedSig_T_15 = _roundedSig_T_13 ? _roundedSig_T_14 : 55'h0; // @[RoundAnyRawFNToRecFN.scala:181:{24,42,67}]
wire [54:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} | _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24]
wire [54:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47]
wire [1:0] _sRoundedExp_T = roundedSig[54:53]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54]
wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}]
wire [13:0] sRoundedExp = {io_in_sExp_0[12], io_in_sExp_0} + {{11{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}]
assign _common_expOut_T = sRoundedExp[11:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37]
assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37]
wire [51:0] _common_fractOut_T = roundedSig[52:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27]
wire [51:0] _common_fractOut_T_1 = roundedSig[51:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27]
assign _common_fractOut_T_2 = _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:189:16, :191:27]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16]
wire [3:0] _common_overflow_T = sRoundedExp[13:10]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30]
assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}]
assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50]
assign _common_totalUnderflow_T = $signed(sRoundedExp) < 14'sh3CE; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31]
assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31]
wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45]
wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44]
wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61]
wire unboundedRange_roundPosBit = _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:203:{16,61}]
wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63]
wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}]
wire unboundedRange_anyRound = _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{49,70}]
wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}]
wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29]
wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 | _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29]
wire _roundCarry_T = roundedSig[54]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27]
wire _roundCarry_T_1 = roundedSig[53]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27]
wire roundCarry = _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:211:16, :213:27]
wire [1:0] _common_underflow_T = io_in_sExp_0[12:11]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49]
wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}]
wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}]
wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57]
wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49]
wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71]
wire _common_underflow_T_5 = _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:221:{30,71}]
wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30]
wire _common_underflow_T_17 = _common_underflow_T_6; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76]
wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49]
wire _common_underflow_T_10 = _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:223:39, :225:49]
wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}]
assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76]
assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40]
assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49]
assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49]
wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34]
wire notNaN_isSpecialInfOut = io_infiniteExc_0 | io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49]
wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22]
wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36]
wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}]
wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32]
wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32]
wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43]
wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}]
wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}]
wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20]
wire _pegMinNonzeroMagOut_T_1 = roundMagUp | roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60]
wire pegMinNonzeroMagOut = _pegMinNonzeroMagOut_T & _pegMinNonzeroMagOut_T_1; // @[RoundAnyRawFNToRecFN.scala:245:{20,45,60}]
wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42]
wire pegMaxFiniteMagOut = overflow & _pegMaxFiniteMagOut_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :246:{39,42}]
wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:238:32, :243:60, :248:45]
wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}]
wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22]
wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32]
wire [11:0] _expOut_T_1 = _expOut_T ? 12'hE00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [11:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [11:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [11:0] _expOut_T_5 = pegMinNonzeroMagOut ? 12'hC31 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :257:18]
wire [11:0] _expOut_T_6 = ~_expOut_T_5; // @[RoundAnyRawFNToRecFN.scala:257:{14,18}]
wire [11:0] _expOut_T_7 = _expOut_T_3 & _expOut_T_6; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17, :257:14]
wire [11:0] _expOut_T_8 = {1'h0, pegMaxFiniteMagOut, 10'h0}; // @[RoundAnyRawFNToRecFN.scala:246:39, :261:18]
wire [11:0] _expOut_T_9 = ~_expOut_T_8; // @[RoundAnyRawFNToRecFN.scala:261:{14,18}]
wire [11:0] _expOut_T_10 = _expOut_T_7 & _expOut_T_9; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17, :261:14]
wire [11:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 9'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18]
wire [11:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}]
wire [11:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14]
wire [11:0] _expOut_T_14 = pegMinNonzeroMagOut ? 12'h3CE : 12'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :269:16]
wire [11:0] _expOut_T_15 = _expOut_T_13 | _expOut_T_14; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18, :269:16]
wire [11:0] _expOut_T_16 = pegMaxFiniteMagOut ? 12'hBFF : 12'h0; // @[RoundAnyRawFNToRecFN.scala:246:39, :273:16]
wire [11:0] _expOut_T_17 = _expOut_T_15 | _expOut_T_16; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15, :273:16]
wire [11:0] _expOut_T_18 = notNaN_isInfOut ? 12'hC00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16]
wire [11:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16]
wire [11:0] _expOut_T_20 = isNaNOut ? 12'hE00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16]
wire [11:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16]
wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22]
wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}]
wire [51:0] _fractOut_T_2 = {isNaNOut, 51'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16]
wire [51:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16]
wire [51:0] _fractOut_T_4 = {52{pegMaxFiniteMagOut}}; // @[RoundAnyRawFNToRecFN.scala:246:39, :284:13]
wire [51:0] fractOut = _fractOut_T_3 | _fractOut_T_4; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11, :284:13]
wire [12:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, io_infiniteExc_0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23]
wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}]
wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}]
assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_80 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_97
connect io_out_source_valid_0.clock, clock
connect io_out_source_valid_0.reset, reset
connect io_out_source_valid_0.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_valid_0.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_80( // @[AsyncQueue.scala:58:7]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in = 1'h1; // @[ShiftReg.scala:45:23]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_97 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMasterToNoC_5 :
input clock : Clock
input reset : Reset
output io : { flip tilelink : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, flits : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}}
inst a of TLAToNoC_5
connect a.clock, clock
connect a.reset, reset
inst b of TLBFromNoC_5
connect b.clock, clock
connect b.reset, reset
inst c of TLCToNoC_5
connect c.clock, clock
connect c.reset, reset
inst d of TLDFromNoC_5
connect d.clock, clock
connect d.reset, reset
inst e of TLEToNoC_5
connect e.clock, clock
connect e.reset, reset
connect a.io.protocol, io.tilelink.a
connect io.tilelink.b.bits, b.io.protocol.bits
connect io.tilelink.b.valid, b.io.protocol.valid
connect b.io.protocol.ready, io.tilelink.b.ready
connect c.io.protocol, io.tilelink.c
connect io.tilelink.d.bits, d.io.protocol.bits
connect io.tilelink.d.valid, d.io.protocol.valid
connect d.io.protocol.ready, io.tilelink.d.ready
connect e.io.protocol, io.tilelink.e
connect io.flits.a.bits, a.io.flit.bits
connect io.flits.a.valid, a.io.flit.valid
connect a.io.flit.ready, io.flits.a.ready
connect b.io.flit, io.flits.b
connect io.flits.c.bits, c.io.flit.bits
connect io.flits.c.valid, c.io.flit.valid
connect c.io.flit.ready, io.flits.c.ready
connect d.io.flit, io.flits.d
connect io.flits.e.bits, e.io.flit.bits
connect io.flits.e.valid, e.io.flit.valid
connect e.io.flit.ready, io.flits.e.ready | module TLMasterToNoC_5( // @[Tilelink.scala:37:7]
input clock, // @[Tilelink.scala:37:7]
input reset, // @[Tilelink.scala:37:7]
output io_tilelink_a_ready, // @[Tilelink.scala:44:14]
input io_tilelink_a_valid, // @[Tilelink.scala:44:14]
input [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:44:14]
input [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:44:14]
input [3:0] io_tilelink_a_bits_size, // @[Tilelink.scala:44:14]
input [5:0] io_tilelink_a_bits_source, // @[Tilelink.scala:44:14]
input [31:0] io_tilelink_a_bits_address, // @[Tilelink.scala:44:14]
input [7:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:44:14]
input [63:0] io_tilelink_a_bits_data, // @[Tilelink.scala:44:14]
input io_tilelink_a_bits_corrupt, // @[Tilelink.scala:44:14]
input io_tilelink_b_ready, // @[Tilelink.scala:44:14]
output io_tilelink_b_valid, // @[Tilelink.scala:44:14]
output [2:0] io_tilelink_b_bits_opcode, // @[Tilelink.scala:44:14]
output [1:0] io_tilelink_b_bits_param, // @[Tilelink.scala:44:14]
output [3:0] io_tilelink_b_bits_size, // @[Tilelink.scala:44:14]
output [5:0] io_tilelink_b_bits_source, // @[Tilelink.scala:44:14]
output [31:0] io_tilelink_b_bits_address, // @[Tilelink.scala:44:14]
output [7:0] io_tilelink_b_bits_mask, // @[Tilelink.scala:44:14]
output [63:0] io_tilelink_b_bits_data, // @[Tilelink.scala:44:14]
output io_tilelink_b_bits_corrupt, // @[Tilelink.scala:44:14]
output io_tilelink_c_ready, // @[Tilelink.scala:44:14]
input io_tilelink_c_valid, // @[Tilelink.scala:44:14]
input [2:0] io_tilelink_c_bits_opcode, // @[Tilelink.scala:44:14]
input [2:0] io_tilelink_c_bits_param, // @[Tilelink.scala:44:14]
input [3:0] io_tilelink_c_bits_size, // @[Tilelink.scala:44:14]
input [5:0] io_tilelink_c_bits_source, // @[Tilelink.scala:44:14]
input [31:0] io_tilelink_c_bits_address, // @[Tilelink.scala:44:14]
input [63:0] io_tilelink_c_bits_data, // @[Tilelink.scala:44:14]
input io_tilelink_c_bits_corrupt, // @[Tilelink.scala:44:14]
input io_tilelink_d_ready, // @[Tilelink.scala:44:14]
output io_tilelink_d_valid, // @[Tilelink.scala:44:14]
output [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:44:14]
output [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:44:14]
output [3:0] io_tilelink_d_bits_size, // @[Tilelink.scala:44:14]
output [5:0] io_tilelink_d_bits_source, // @[Tilelink.scala:44:14]
output [4:0] io_tilelink_d_bits_sink, // @[Tilelink.scala:44:14]
output io_tilelink_d_bits_denied, // @[Tilelink.scala:44:14]
output [63:0] io_tilelink_d_bits_data, // @[Tilelink.scala:44:14]
output io_tilelink_d_bits_corrupt, // @[Tilelink.scala:44:14]
output io_tilelink_e_ready, // @[Tilelink.scala:44:14]
input io_tilelink_e_valid, // @[Tilelink.scala:44:14]
input [4:0] io_tilelink_e_bits_sink, // @[Tilelink.scala:44:14]
input io_flits_a_ready, // @[Tilelink.scala:44:14]
output io_flits_a_valid, // @[Tilelink.scala:44:14]
output io_flits_a_bits_head, // @[Tilelink.scala:44:14]
output io_flits_a_bits_tail, // @[Tilelink.scala:44:14]
output [72:0] io_flits_a_bits_payload, // @[Tilelink.scala:44:14]
output [4:0] io_flits_a_bits_egress_id, // @[Tilelink.scala:44:14]
output io_flits_b_ready, // @[Tilelink.scala:44:14]
input io_flits_b_valid, // @[Tilelink.scala:44:14]
input io_flits_b_bits_head, // @[Tilelink.scala:44:14]
input io_flits_b_bits_tail, // @[Tilelink.scala:44:14]
input [72:0] io_flits_b_bits_payload, // @[Tilelink.scala:44:14]
input io_flits_c_ready, // @[Tilelink.scala:44:14]
output io_flits_c_valid, // @[Tilelink.scala:44:14]
output io_flits_c_bits_head, // @[Tilelink.scala:44:14]
output io_flits_c_bits_tail, // @[Tilelink.scala:44:14]
output [72:0] io_flits_c_bits_payload, // @[Tilelink.scala:44:14]
output [4:0] io_flits_c_bits_egress_id, // @[Tilelink.scala:44:14]
output io_flits_d_ready, // @[Tilelink.scala:44:14]
input io_flits_d_valid, // @[Tilelink.scala:44:14]
input io_flits_d_bits_head, // @[Tilelink.scala:44:14]
input io_flits_d_bits_tail, // @[Tilelink.scala:44:14]
input [72:0] io_flits_d_bits_payload, // @[Tilelink.scala:44:14]
input io_flits_e_ready, // @[Tilelink.scala:44:14]
output io_flits_e_valid, // @[Tilelink.scala:44:14]
output io_flits_e_bits_head, // @[Tilelink.scala:44:14]
output [72:0] io_flits_e_bits_payload, // @[Tilelink.scala:44:14]
output [5:0] io_flits_e_bits_egress_id // @[Tilelink.scala:44:14]
);
wire [4:0] _e_io_flit_bits_payload; // @[Tilelink.scala:58:17]
wire [64:0] _c_io_flit_bits_payload; // @[Tilelink.scala:56:17]
TLAToNoC_5 a ( // @[Tilelink.scala:54:17]
.clock (clock),
.reset (reset),
.io_protocol_ready (io_tilelink_a_ready),
.io_protocol_valid (io_tilelink_a_valid),
.io_protocol_bits_opcode (io_tilelink_a_bits_opcode),
.io_protocol_bits_param (io_tilelink_a_bits_param),
.io_protocol_bits_size (io_tilelink_a_bits_size),
.io_protocol_bits_source (io_tilelink_a_bits_source),
.io_protocol_bits_address (io_tilelink_a_bits_address),
.io_protocol_bits_mask (io_tilelink_a_bits_mask),
.io_protocol_bits_data (io_tilelink_a_bits_data),
.io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt),
.io_flit_ready (io_flits_a_ready),
.io_flit_valid (io_flits_a_valid),
.io_flit_bits_head (io_flits_a_bits_head),
.io_flit_bits_tail (io_flits_a_bits_tail),
.io_flit_bits_payload (io_flits_a_bits_payload),
.io_flit_bits_egress_id (io_flits_a_bits_egress_id)
); // @[Tilelink.scala:54:17]
TLBFromNoC_1 b ( // @[Tilelink.scala:55:17]
.clock (clock),
.reset (reset),
.io_protocol_ready (io_tilelink_b_ready),
.io_protocol_valid (io_tilelink_b_valid),
.io_protocol_bits_opcode (io_tilelink_b_bits_opcode),
.io_protocol_bits_param (io_tilelink_b_bits_param),
.io_protocol_bits_size (io_tilelink_b_bits_size),
.io_protocol_bits_source (io_tilelink_b_bits_source),
.io_protocol_bits_address (io_tilelink_b_bits_address),
.io_protocol_bits_mask (io_tilelink_b_bits_mask),
.io_protocol_bits_data (io_tilelink_b_bits_data),
.io_protocol_bits_corrupt (io_tilelink_b_bits_corrupt),
.io_flit_ready (io_flits_b_ready),
.io_flit_valid (io_flits_b_valid),
.io_flit_bits_head (io_flits_b_bits_head),
.io_flit_bits_tail (io_flits_b_bits_tail),
.io_flit_bits_payload (io_flits_b_bits_payload)
); // @[Tilelink.scala:55:17]
TLCToNoC_5 c ( // @[Tilelink.scala:56:17]
.clock (clock),
.reset (reset),
.io_protocol_ready (io_tilelink_c_ready),
.io_protocol_valid (io_tilelink_c_valid),
.io_protocol_bits_opcode (io_tilelink_c_bits_opcode),
.io_protocol_bits_param (io_tilelink_c_bits_param),
.io_protocol_bits_size (io_tilelink_c_bits_size),
.io_protocol_bits_source (io_tilelink_c_bits_source),
.io_protocol_bits_address (io_tilelink_c_bits_address),
.io_protocol_bits_data (io_tilelink_c_bits_data),
.io_protocol_bits_corrupt (io_tilelink_c_bits_corrupt),
.io_flit_ready (io_flits_c_ready),
.io_flit_valid (io_flits_c_valid),
.io_flit_bits_head (io_flits_c_bits_head),
.io_flit_bits_tail (io_flits_c_bits_tail),
.io_flit_bits_payload (_c_io_flit_bits_payload),
.io_flit_bits_egress_id (io_flits_c_bits_egress_id)
); // @[Tilelink.scala:56:17]
TLDFromNoC_1 d ( // @[Tilelink.scala:57:17]
.clock (clock),
.reset (reset),
.io_protocol_ready (io_tilelink_d_ready),
.io_protocol_valid (io_tilelink_d_valid),
.io_protocol_bits_opcode (io_tilelink_d_bits_opcode),
.io_protocol_bits_param (io_tilelink_d_bits_param),
.io_protocol_bits_size (io_tilelink_d_bits_size),
.io_protocol_bits_source (io_tilelink_d_bits_source),
.io_protocol_bits_sink (io_tilelink_d_bits_sink),
.io_protocol_bits_denied (io_tilelink_d_bits_denied),
.io_protocol_bits_data (io_tilelink_d_bits_data),
.io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt),
.io_flit_ready (io_flits_d_ready),
.io_flit_valid (io_flits_d_valid),
.io_flit_bits_head (io_flits_d_bits_head),
.io_flit_bits_tail (io_flits_d_bits_tail),
.io_flit_bits_payload (io_flits_d_bits_payload[64:0]) // @[Tilelink.scala:68:14]
); // @[Tilelink.scala:57:17]
TLEToNoC e ( // @[Tilelink.scala:58:17]
.clock (clock),
.reset (reset),
.io_protocol_ready (io_tilelink_e_ready),
.io_protocol_valid (io_tilelink_e_valid),
.io_protocol_bits_sink (io_tilelink_e_bits_sink),
.io_flit_ready (io_flits_e_ready),
.io_flit_valid (io_flits_e_valid),
.io_flit_bits_head (io_flits_e_bits_head),
.io_flit_bits_payload (_e_io_flit_bits_payload),
.io_flit_bits_egress_id (io_flits_e_bits_egress_id)
); // @[Tilelink.scala:58:17]
assign io_flits_c_bits_payload = {8'h0, _c_io_flit_bits_payload}; // @[Tilelink.scala:37:7, :56:17, :67:14]
assign io_flits_e_bits_payload = {68'h0, _e_io_flit_bits_payload}; // @[Tilelink.scala:37:7, :58:17, :69:14]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_28 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, flip out_credit_available : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}}
inst route_buffer of Queue2_Flit_56
connect route_buffer.clock, clock
connect route_buffer.reset, reset
inst route_q of Queue2_RouteComputerResp_28
connect route_q.clock, clock
connect route_q.reset, reset
node _T = eq(UInt<5>(0h10), io.in.bits.egress_id)
node _T_1 = eq(UInt<5>(0h12), io.in.bits.egress_id)
node _T_2 = eq(UInt<5>(0h14), io.in.bits.egress_id)
node _T_3 = eq(UInt<5>(0h16), io.in.bits.egress_id)
node _T_4 = or(_T, _T_1)
node _T_5 = or(_T_4, _T_2)
node _T_6 = or(_T_5, _T_3)
node _T_7 = eq(_T_6, UInt<1>(0h0))
node _T_8 = and(io.in.valid, _T_7)
node _T_9 = eq(_T_8, UInt<1>(0h0))
node _T_10 = asUInt(reset)
node _T_11 = eq(_T_10, UInt<1>(0h0))
when _T_11 :
node _T_12 = eq(_T_9, UInt<1>(0h0))
when _T_12 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf
assert(clock, _T_9, UInt<1>(0h1), "") : assert
connect route_buffer.io.enq.bits.head, io.in.bits.head
connect route_buffer.io.enq.bits.tail, io.in.bits.tail
connect route_buffer.io.enq.bits.flow.ingress_node, UInt<4>(0he)
connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h1)
connect route_buffer.io.enq.bits.flow.vnet_id, UInt<1>(0h1)
node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<5>(0h10), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<5>(0h12), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<5>(0h14), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<5>(0h16), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<3>(0h5), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<3>(0h6), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<4>(0h9), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<4>(0ha), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_T_4, _route_buffer_io_enq_bits_flow_egress_node_T_5)
node _route_buffer_io_enq_bits_flow_egress_node_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_T_8, _route_buffer_io_enq_bits_flow_egress_node_T_6)
node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_9, _route_buffer_io_enq_bits_flow_egress_node_T_7)
wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4>
connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_10
connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE
node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<5>(0h10), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<5>(0h12), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<5>(0h14), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<5>(0h16), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h1), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h1), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h1), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h1), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, _route_buffer_io_enq_bits_flow_egress_node_id_T_5)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_8, _route_buffer_io_enq_bits_flow_egress_node_id_T_6)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_9, _route_buffer_io_enq_bits_flow_egress_node_id_T_7)
wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1>
connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_10
connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE
connect route_buffer.io.enq.bits.payload, io.in.bits.payload
invalidate route_buffer.io.enq.bits.virt_channel_id
connect io.router_req.bits.src_virt_id, UInt<1>(0h0)
connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id
connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node
connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id
connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node
connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id
node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<4>(0he))
node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0))
node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T)
node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest)
node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2)
connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3
node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready)
node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head)
node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0))
node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2)
connect io.router_req.valid, _io_router_req_valid_T_3
node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0))
node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T)
node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest)
node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2)
connect io.in.ready, _io_in_ready_T_3
node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid)
connect route_q.io.enq.valid, _route_q_io_enq_valid_T
connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0]
connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1]
connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2]
connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0]
connect route_q.io.enq.bits.vc_sel.`1`[1], io.router_resp.vc_sel.`1`[1]
connect route_q.io.enq.bits.vc_sel.`1`[2], io.router_resp.vc_sel.`1`[2]
connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0]
node _T_13 = and(io.in.ready, io.in.valid)
node _T_14 = and(_T_13, io.in.bits.head)
node _T_15 = and(_T_14, at_dest)
when _T_15 :
connect route_q.io.enq.valid, UInt<1>(0h1)
connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`1`[1], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`1`[2], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0)
node _T_16 = eq(UInt<4>(0hb), io.in.bits.egress_id)
when _T_16 :
connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1)
node _T_17 = eq(route_q.io.enq.ready, UInt<1>(0h0))
node _T_18 = and(route_q.io.enq.valid, _T_17)
node _T_19 = eq(_T_18, UInt<1>(0h0))
node _T_20 = asUInt(reset)
node _T_21 = eq(_T_20, UInt<1>(0h0))
when _T_21 :
node _T_22 = eq(_T_19, UInt<1>(0h0))
when _T_22 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1
assert(clock, _T_19, UInt<1>(0h1), "") : assert_1
inst vcalloc_buffer of Queue2_Flit_57
connect vcalloc_buffer.clock, clock
connect vcalloc_buffer.reset, reset
inst vcalloc_q of Queue1_VCAllocResp_28
connect vcalloc_q.clock, clock
connect vcalloc_q.reset, reset
connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id
connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id
connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node
connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id
connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node
connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id
connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload
connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail
connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head
connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0`
connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1`
connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2`
connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow
connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0)
node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T)
node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1)
node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3)
node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4)
connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5
node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid)
node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head)
node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready)
node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready)
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3
node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T)
node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1)
node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3)
node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4)
node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6)
node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7)
connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8
node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid)
node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail)
connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1
node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T
connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2]
connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0]
connect vcalloc_q.io.enq.bits.vc_sel.`1`[1], io.vcalloc_resp.vc_sel.`1`[1]
connect vcalloc_q.io.enq.bits.vc_sel.`1`[2], io.vcalloc_resp.vc_sel.`1`[2]
connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0]
node _T_23 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0))
node _T_24 = and(vcalloc_q.io.enq.valid, _T_23)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = asUInt(reset)
node _T_27 = eq(_T_26, UInt<1>(0h0))
when _T_27 :
node _T_28 = eq(_T_25, UInt<1>(0h0))
when _T_28 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2
assert(clock, _T_25, UInt<1>(0h1), "") : assert_2
connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0`
connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1`
connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2`
connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail
node c_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[2], vcalloc_q.io.deq.bits.vc_sel.`0`[1])
node _c_T = cat(c_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[0])
node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[2], vcalloc_q.io.deq.bits.vc_sel.`1`[1])
node _c_T_1 = cat(c_hi_1, vcalloc_q.io.deq.bits.vc_sel.`1`[0])
node c_hi_2 = cat(vcalloc_q.io.deq.bits.vc_sel.`2`[0], _c_T_1)
node _c_T_2 = cat(c_hi_2, _c_T)
node c_hi_3 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1])
node _c_T_3 = cat(c_hi_3, io.out_credit_available.`0`[0])
node c_hi_4 = cat(io.out_credit_available.`1`[2], io.out_credit_available.`1`[1])
node _c_T_4 = cat(c_hi_4, io.out_credit_available.`1`[0])
node c_hi_5 = cat(io.out_credit_available.`2`[0], _c_T_4)
node _c_T_5 = cat(c_hi_5, _c_T_3)
node _c_T_6 = and(_c_T_2, _c_T_5)
node c = neq(_c_T_6, UInt<1>(0h0))
node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid)
node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c)
node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0))
node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2)
connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3
node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid)
node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c)
node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0))
node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2)
connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3
node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid)
node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T)
connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1
wire out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}
connect io.out[0], out_bundle
node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid)
connect out_bundle.valid, _out_bundle_valid_T
connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits
connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0)
node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1])
node out_channel_oh_0 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node _out_channel_oh_T_1 = or(vcalloc_q.io.deq.bits.vc_sel.`1`[0], vcalloc_q.io.deq.bits.vc_sel.`1`[1])
node out_channel_oh_1 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`1`[2])
node out_bundle_bits_out_virt_channel_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[2], vcalloc_q.io.deq.bits.vc_sel.`0`[1])
node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[0])
node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 2, 2)
node out_bundle_bits_out_virt_channel_lo = bits(_out_bundle_bits_out_virt_channel_T, 1, 0)
node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1)
node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo)
node _out_bundle_bits_out_virt_channel_T_3 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 1)
node _out_bundle_bits_out_virt_channel_T_4 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_3)
node out_bundle_bits_out_virt_channel_hi_2 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[2], vcalloc_q.io.deq.bits.vc_sel.`1`[1])
node _out_bundle_bits_out_virt_channel_T_5 = cat(out_bundle_bits_out_virt_channel_hi_2, vcalloc_q.io.deq.bits.vc_sel.`1`[0])
node out_bundle_bits_out_virt_channel_hi_3 = bits(_out_bundle_bits_out_virt_channel_T_5, 2, 2)
node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T_5, 1, 0)
node _out_bundle_bits_out_virt_channel_T_6 = orr(out_bundle_bits_out_virt_channel_hi_3)
node _out_bundle_bits_out_virt_channel_T_7 = or(out_bundle_bits_out_virt_channel_hi_3, out_bundle_bits_out_virt_channel_lo_1)
node _out_bundle_bits_out_virt_channel_T_8 = bits(_out_bundle_bits_out_virt_channel_T_7, 1, 1)
node _out_bundle_bits_out_virt_channel_T_9 = cat(_out_bundle_bits_out_virt_channel_T_6, _out_bundle_bits_out_virt_channel_T_8)
node _out_bundle_bits_out_virt_channel_T_10 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_4, UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_11 = mux(out_channel_oh_1, _out_bundle_bits_out_virt_channel_T_9, UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_12 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_13 = or(_out_bundle_bits_out_virt_channel_T_10, _out_bundle_bits_out_virt_channel_T_11)
node _out_bundle_bits_out_virt_channel_T_14 = or(_out_bundle_bits_out_virt_channel_T_13, _out_bundle_bits_out_virt_channel_T_12)
wire _out_bundle_bits_out_virt_channel_WIRE : UInt<2>
connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_14
connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE
node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0))
node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T)
connect io.debug.va_stall, _io_debug_va_stall_T_1
node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T)
connect io.debug.sa_stall, _io_debug_sa_stall_T_1 | module IngressUnit_28( // @[IngressUnit.scala:11:7]
input clock, // @[IngressUnit.scala:11:7]
input reset, // @[IngressUnit.scala:11:7]
output [3:0] io_router_req_bits_flow_egress_node, // @[IngressUnit.scala:24:14]
output [1:0] io_router_req_bits_flow_egress_node_id, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_1_1, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_1_2, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_2, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_1_1, // @[IngressUnit.scala:24:14]
input io_out_credit_available_1_2, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14]
input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14]
output io_out_0_valid, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14]
output [144:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14]
output io_in_ready, // @[IngressUnit.scala:24:14]
input io_in_valid, // @[IngressUnit.scala:24:14]
input io_in_bits_head, // @[IngressUnit.scala:24:14]
input io_in_bits_tail, // @[IngressUnit.scala:24:14]
input [144:0] io_in_bits_payload, // @[IngressUnit.scala:24:14]
input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14]
);
wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30]
wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23]
wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23]
wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28]
wire [144:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'h10; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = io_in_bits_egress_id == 5'h12; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = io_in_bits_egress_id == 5'h14; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = io_in_bits_egress_id == 5'h16; // @[IngressUnit.scala:30:72]
wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_10 = {1'h0, (_route_buffer_io_enq_bits_flow_egress_node_id_T_4 ? 3'h5 : 3'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_5 ? 3'h6 : 3'h0)} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_6 ? 4'h9 : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_7 ? 4'hA : 4'h0); // @[Mux.scala:30:73]
wire [1:0] route_buffer_io_enq_bits_flow_egress_node_id = {1'h0, _route_buffer_io_enq_bits_flow_egress_node_id_T_4 | _route_buffer_io_enq_bits_flow_egress_node_id_T_5 | _route_buffer_io_enq_bits_flow_egress_node_id_T_6 | _route_buffer_io_enq_bits_flow_egress_node_id_T_7}; // @[Mux.scala:30:73]
wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 == 4'hE; // @[Mux.scala:30:73]
wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 != 4'hE; // @[Mux.scala:30:73]
wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}]
wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29]
wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] |
Generate the Verilog code corresponding to this FIRRTL code module TLFragmenter_TileResetSetter :
input clock : Clock
input reset : Reset
output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn.d.bits.corrupt
invalidate anonIn.d.bits.data
invalidate anonIn.d.bits.denied
invalidate anonIn.d.bits.sink
invalidate anonIn.d.bits.source
invalidate anonIn.d.bits.size
invalidate anonIn.d.bits.param
invalidate anonIn.d.bits.opcode
invalidate anonIn.d.valid
invalidate anonIn.d.ready
invalidate anonIn.a.bits.corrupt
invalidate anonIn.a.bits.data
invalidate anonIn.a.bits.mask
invalidate anonIn.a.bits.address
invalidate anonIn.a.bits.source
invalidate anonIn.a.bits.size
invalidate anonIn.a.bits.param
invalidate anonIn.a.bits.opcode
invalidate anonIn.a.valid
invalidate anonIn.a.ready
inst monitor of TLMonitor_23
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, anonIn.d.bits.data
connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied
connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink
connect monitor.io.in.d.bits.source, anonIn.d.bits.source
connect monitor.io.in.d.bits.size, anonIn.d.bits.size
connect monitor.io.in.d.bits.param, anonIn.d.bits.param
connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode
connect monitor.io.in.d.valid, anonIn.d.valid
connect monitor.io.in.d.ready, anonIn.d.ready
connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, anonIn.a.bits.data
connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask
connect monitor.io.in.a.bits.address, anonIn.a.bits.address
connect monitor.io.in.a.bits.source, anonIn.a.bits.source
connect monitor.io.in.a.bits.size, anonIn.a.bits.size
connect monitor.io.in.a.bits.param, anonIn.a.bits.param
connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode
connect monitor.io.in.a.valid, anonIn.a.valid
connect monitor.io.in.a.ready, anonIn.a.ready
wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonOut.d.bits.corrupt
invalidate anonOut.d.bits.data
invalidate anonOut.d.bits.denied
invalidate anonOut.d.bits.sink
invalidate anonOut.d.bits.source
invalidate anonOut.d.bits.size
invalidate anonOut.d.bits.param
invalidate anonOut.d.bits.opcode
invalidate anonOut.d.valid
invalidate anonOut.d.ready
invalidate anonOut.a.bits.corrupt
invalidate anonOut.a.bits.data
invalidate anonOut.a.bits.mask
invalidate anonOut.a.bits.address
invalidate anonOut.a.bits.source
invalidate anonOut.a.bits.size
invalidate anonOut.a.bits.param
invalidate anonOut.a.bits.opcode
invalidate anonOut.a.valid
invalidate anonOut.a.ready
connect auto.anon_out, anonOut
connect anonIn, auto.anon_in
regreset acknum : UInt<3>, clock, reset, UInt<3>(0h0)
reg dOrig : UInt, clock
regreset dToggle : UInt<1>, clock, reset, UInt<1>(0h0)
node dFragnum = bits(anonOut.d.bits.source, 2, 0)
node dFirst = eq(acknum, UInt<1>(0h0))
node dLast = eq(dFragnum, UInt<1>(0h0))
node dsizeOH_shiftAmount = bits(anonOut.d.bits.size, 1, 0)
node _dsizeOH_T = dshl(UInt<1>(0h1), dsizeOH_shiftAmount)
node dsizeOH = bits(_dsizeOH_T, 3, 0)
node _dsizeOH1_T = dshl(UInt<3>(0h7), anonOut.d.bits.size)
node _dsizeOH1_T_1 = bits(_dsizeOH1_T, 2, 0)
node dsizeOH1 = not(_dsizeOH1_T_1)
node dHasData = bits(anonOut.d.bits.opcode, 0, 0)
node acknum_fragment = shl(dFragnum, 0)
node acknum_size = shr(dsizeOH1, 3)
node _T = eq(anonOut.d.valid, UInt<1>(0h0))
node _T_1 = and(acknum_fragment, acknum_size)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = or(_T, _T_2)
node _T_4 = asUInt(reset)
node _T_5 = eq(_T_4, UInt<1>(0h0))
when _T_5 :
node _T_6 = eq(_T_3, UInt<1>(0h0))
when _T_6 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:214 assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U)\n") : printf
assert(clock, _T_3, UInt<1>(0h1), "") : assert
node _dFirst_acknum_T = mux(dHasData, acknum_size, UInt<1>(0h0))
node dFirst_acknum = or(acknum_fragment, _dFirst_acknum_T)
node _ack_decrement_T = shr(dsizeOH, 3)
node ack_decrement = mux(dHasData, UInt<1>(0h1), _ack_decrement_T)
node _dFirst_size_T = shl(dFragnum, 3)
node _dFirst_size_T_1 = or(_dFirst_size_T, dsizeOH1)
node _dFirst_size_T_2 = shl(_dFirst_size_T_1, 1)
node _dFirst_size_T_3 = or(_dFirst_size_T_2, UInt<1>(0h1))
node _dFirst_size_T_4 = cat(UInt<1>(0h0), _dFirst_size_T_1)
node _dFirst_size_T_5 = not(_dFirst_size_T_4)
node _dFirst_size_T_6 = and(_dFirst_size_T_3, _dFirst_size_T_5)
node dFirst_size_hi = bits(_dFirst_size_T_6, 6, 4)
node dFirst_size_lo = bits(_dFirst_size_T_6, 3, 0)
node _dFirst_size_T_7 = orr(dFirst_size_hi)
node _dFirst_size_T_8 = or(dFirst_size_hi, dFirst_size_lo)
node dFirst_size_hi_1 = bits(_dFirst_size_T_8, 3, 2)
node dFirst_size_lo_1 = bits(_dFirst_size_T_8, 1, 0)
node _dFirst_size_T_9 = orr(dFirst_size_hi_1)
node _dFirst_size_T_10 = or(dFirst_size_hi_1, dFirst_size_lo_1)
node _dFirst_size_T_11 = bits(_dFirst_size_T_10, 1, 1)
node _dFirst_size_T_12 = cat(_dFirst_size_T_9, _dFirst_size_T_11)
node dFirst_size = cat(_dFirst_size_T_7, _dFirst_size_T_12)
node _T_7 = and(anonOut.d.ready, anonOut.d.valid)
when _T_7 :
node _acknum_T = sub(acknum, ack_decrement)
node _acknum_T_1 = tail(_acknum_T, 1)
node _acknum_T_2 = mux(dFirst, dFirst_acknum, _acknum_T_1)
connect acknum, _acknum_T_2
when dFirst :
connect dOrig, dFirst_size
node _dToggle_T = bits(anonOut.d.bits.source, 3, 3)
connect dToggle, _dToggle_T
node _drop_T = eq(dHasData, UInt<1>(0h0))
node _drop_T_1 = mux(UInt<1>(0h0), dFirst, dLast)
node _drop_T_2 = eq(_drop_T_1, UInt<1>(0h0))
node drop = and(_drop_T, _drop_T_2)
node _anonOut_d_ready_T = or(anonIn.d.ready, drop)
connect anonOut.d.ready, _anonOut_d_ready_T
node _anonIn_d_valid_T = eq(drop, UInt<1>(0h0))
node _anonIn_d_valid_T_1 = and(anonOut.d.valid, _anonIn_d_valid_T)
connect anonIn.d.valid, _anonIn_d_valid_T_1
connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt
connect anonIn.d.bits.data, anonOut.d.bits.data
connect anonIn.d.bits.denied, anonOut.d.bits.denied
connect anonIn.d.bits.sink, anonOut.d.bits.sink
connect anonIn.d.bits.source, anonOut.d.bits.source
connect anonIn.d.bits.size, anonOut.d.bits.size
connect anonIn.d.bits.param, anonOut.d.bits.param
connect anonIn.d.bits.opcode, anonOut.d.bits.opcode
node _anonIn_d_bits_source_T = shr(anonOut.d.bits.source, 4)
connect anonIn.d.bits.source, _anonIn_d_bits_source_T
node _anonIn_d_bits_size_T = mux(dFirst, dFirst_size, dOrig)
connect anonIn.d.bits.size, _anonIn_d_bits_size_T
inst repeater of Repeater_TLBundleA_a21d64s5k1z3u_1
connect repeater.clock, clock
connect repeater.reset, reset
connect repeater.io.enq, anonIn.a
node _find_T = xor(repeater.io.deq.bits.address, UInt<1>(0h0))
node _find_T_1 = cvt(_find_T)
node _find_T_2 = and(_find_T_1, asSInt(UInt<1>(0h0)))
node _find_T_3 = asSInt(_find_T_2)
node _find_T_4 = eq(_find_T_3, asSInt(UInt<1>(0h0)))
wire find : UInt<1>[1]
connect find[0], _find_T_4
node _limit_T = eq(UInt<1>(0h0), repeater.io.deq.bits.opcode)
node _limit_T_1 = mux(_limit_T, UInt<2>(0h3), UInt<2>(0h3))
node _limit_T_2 = eq(UInt<1>(0h1), repeater.io.deq.bits.opcode)
node _limit_T_3 = mux(_limit_T_2, UInt<2>(0h3), _limit_T_1)
node _limit_T_4 = eq(UInt<2>(0h2), repeater.io.deq.bits.opcode)
node _limit_T_5 = mux(_limit_T_4, UInt<2>(0h3), _limit_T_3)
node _limit_T_6 = eq(UInt<2>(0h3), repeater.io.deq.bits.opcode)
node _limit_T_7 = mux(_limit_T_6, UInt<2>(0h3), _limit_T_5)
node _limit_T_8 = eq(UInt<3>(0h4), repeater.io.deq.bits.opcode)
node _limit_T_9 = mux(_limit_T_8, UInt<2>(0h3), _limit_T_7)
node _limit_T_10 = eq(UInt<3>(0h5), repeater.io.deq.bits.opcode)
node limit = mux(_limit_T_10, UInt<2>(0h3), _limit_T_9)
node _aFrag_T = gt(repeater.io.deq.bits.size, limit)
node aFrag = mux(_aFrag_T, limit, repeater.io.deq.bits.size)
node _aOrigOH1_T = dshl(UInt<6>(0h3f), repeater.io.deq.bits.size)
node _aOrigOH1_T_1 = bits(_aOrigOH1_T, 5, 0)
node aOrigOH1 = not(_aOrigOH1_T_1)
node _aFragOH1_T = dshl(UInt<3>(0h7), aFrag)
node _aFragOH1_T_1 = bits(_aFragOH1_T, 2, 0)
node aFragOH1 = not(_aFragOH1_T_1)
node _aHasData_opdata_T = bits(repeater.io.deq.bits.opcode, 2, 2)
node aHasData = eq(_aHasData_opdata_T, UInt<1>(0h0))
node aMask = mux(aHasData, UInt<1>(0h0), aFragOH1)
regreset gennum : UInt<3>, clock, reset, UInt<3>(0h0)
node aFirst = eq(gennum, UInt<1>(0h0))
node _old_gennum1_T = shr(aOrigOH1, 3)
node _old_gennum1_T_1 = sub(gennum, UInt<1>(0h1))
node _old_gennum1_T_2 = tail(_old_gennum1_T_1, 1)
node old_gennum1 = mux(aFirst, _old_gennum1_T, _old_gennum1_T_2)
node _new_gennum_T = not(old_gennum1)
node _new_gennum_T_1 = shr(aMask, 3)
node _new_gennum_T_2 = or(_new_gennum_T, _new_gennum_T_1)
node new_gennum = not(_new_gennum_T_2)
node _aFragnum_T = shr(old_gennum1, 0)
node _aFragnum_T_1 = not(_aFragnum_T)
node _aFragnum_T_2 = shr(aFragOH1, 3)
node _aFragnum_T_3 = or(_aFragnum_T_1, _aFragnum_T_2)
node aFragnum = not(_aFragnum_T_3)
node aLast = eq(aFragnum, UInt<1>(0h0))
reg aToggle_r : UInt<1>, clock
when aFirst :
connect aToggle_r, dToggle
node _aToggle_T = mux(aFirst, dToggle, aToggle_r)
node aToggle = eq(_aToggle_T, UInt<1>(0h0))
node _T_8 = and(anonOut.a.ready, anonOut.a.valid)
when _T_8 :
connect gennum, new_gennum
node _repeater_io_repeat_T = eq(aHasData, UInt<1>(0h0))
node _repeater_io_repeat_T_1 = neq(aFragnum, UInt<1>(0h0))
node _repeater_io_repeat_T_2 = and(_repeater_io_repeat_T, _repeater_io_repeat_T_1)
connect repeater.io.repeat, _repeater_io_repeat_T_2
connect anonOut.a.bits, repeater.io.deq.bits
connect anonOut.a.valid, repeater.io.deq.valid
connect repeater.io.deq.ready, anonOut.a.ready
node _anonOut_a_bits_address_T = shl(old_gennum1, 3)
node _anonOut_a_bits_address_T_1 = not(aOrigOH1)
node _anonOut_a_bits_address_T_2 = or(_anonOut_a_bits_address_T, _anonOut_a_bits_address_T_1)
node _anonOut_a_bits_address_T_3 = or(_anonOut_a_bits_address_T_2, aFragOH1)
node _anonOut_a_bits_address_T_4 = or(_anonOut_a_bits_address_T_3, UInt<3>(0h7))
node _anonOut_a_bits_address_T_5 = not(_anonOut_a_bits_address_T_4)
node _anonOut_a_bits_address_T_6 = or(repeater.io.deq.bits.address, _anonOut_a_bits_address_T_5)
connect anonOut.a.bits.address, _anonOut_a_bits_address_T_6
node anonOut_a_bits_source_hi = cat(repeater.io.deq.bits.source, aToggle)
node _anonOut_a_bits_source_T = cat(anonOut_a_bits_source_hi, aFragnum)
connect anonOut.a.bits.source, _anonOut_a_bits_source_T
connect anonOut.a.bits.size, aFrag
node _T_9 = eq(repeater.io.full, UInt<1>(0h0))
node _T_10 = eq(aHasData, UInt<1>(0h0))
node _T_11 = or(_T_9, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:321 assert (!repeater.io.full || !aHasData)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
connect anonOut.a.bits.data, anonIn.a.bits.data
node _T_15 = eq(repeater.io.full, UInt<1>(0h0))
node _T_16 = eq(repeater.io.deq.bits.mask, UInt<8>(0hff))
node _T_17 = or(_T_15, _T_16)
node _T_18 = asUInt(reset)
node _T_19 = eq(_T_18, UInt<1>(0h0))
when _T_19 :
node _T_20 = eq(_T_17, UInt<1>(0h0))
when _T_20 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:324 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n") : printf_2
assert(clock, _T_17, UInt<1>(0h1), "") : assert_2
node _anonOut_a_bits_mask_T = mux(repeater.io.full, UInt<8>(0hff), anonIn.a.bits.mask)
connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T
wire anonOut_a_bits_user_out : { }
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<21>(0h0)
connect _WIRE.bits.source, UInt<5>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<21>(0h0)
connect _WIRE_2.bits.source, UInt<5>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<9>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<21>(0h0)
connect _WIRE_6.bits.source, UInt<9>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<9>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<21>(0h0)
connect _WIRE_8.bits.source, UInt<9>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_10.bits.sink, UInt<1>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0) | module TLFragmenter_TileResetSetter( // @[Fragmenter.scala:92:9]
input clock, // @[Fragmenter.scala:92:9]
input reset, // @[Fragmenter.scala:92:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [20:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [8:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [20:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [8:0] auto_anon_out_d_bits_source // @[LazyModuleImp.scala:107:25]
);
wire _repeater_io_full; // @[Fragmenter.scala:274:30]
wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30]
wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30]
wire [4:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30]
wire [20:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30]
wire [7:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30]
wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[Fragmenter.scala:92:9]
wire [4:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[Fragmenter.scala:92:9]
wire [20:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[Fragmenter.scala:92:9]
wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[Fragmenter.scala:92:9]
wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[Fragmenter.scala:92:9]
wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[Fragmenter.scala:92:9]
wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[Fragmenter.scala:92:9]
wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Fragmenter.scala:92:9]
wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Fragmenter.scala:92:9]
wire [1:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Fragmenter.scala:92:9]
wire [8:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Fragmenter.scala:92:9]
wire [63:0] auto_anon_in_d_bits_data = 64'h0; // @[Fragmenter.scala:92:9]
wire [63:0] auto_anon_out_d_bits_data = 64'h0; // @[Fragmenter.scala:92:9]
wire [63:0] anonIn_d_bits_data = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] anonOut_d_bits_data = 64'h0; // @[MixedNode.scala:542:17]
wire [1:0] auto_anon_in_d_bits_param = 2'h0; // @[Fragmenter.scala:92:9]
wire [1:0] auto_anon_out_d_bits_param = 2'h0; // @[Fragmenter.scala:92:9]
wire [1:0] anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17]
wire auto_anon_in_d_bits_sink = 1'h0; // @[Fragmenter.scala:92:9]
wire auto_anon_in_d_bits_denied = 1'h0; // @[Fragmenter.scala:92:9]
wire auto_anon_in_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:92:9]
wire auto_anon_out_d_bits_sink = 1'h0; // @[Fragmenter.scala:92:9]
wire auto_anon_out_d_bits_denied = 1'h0; // @[Fragmenter.scala:92:9]
wire auto_anon_out_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:92:9]
wire anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17]
wire anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17]
wire anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire acknum_size = 1'h0; // @[Fragmenter.scala:213:36]
wire _dFirst_acknum_T = 1'h0; // @[Fragmenter.scala:215:50]
wire _new_gennum_T_1 = 1'h0; // @[Fragmenter.scala:306:50]
wire _aFragnum_T_2 = 1'h0; // @[Fragmenter.scala:307:84]
wire [1:0] _limit_T_1 = 2'h3; // @[Fragmenter.scala:288:49]
wire [1:0] _limit_T_3 = 2'h3; // @[Fragmenter.scala:288:49]
wire [1:0] _limit_T_5 = 2'h3; // @[Fragmenter.scala:288:49]
wire [1:0] _limit_T_7 = 2'h3; // @[Fragmenter.scala:288:49]
wire [1:0] _limit_T_9 = 2'h3; // @[Fragmenter.scala:288:49]
wire [1:0] limit = 2'h3; // @[Fragmenter.scala:288:49]
wire _find_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire find_0 = 1'h1; // @[Parameters.scala:616:12]
wire [21:0] _find_T_2 = 22'h0; // @[Parameters.scala:137:46]
wire [21:0] _find_T_3 = 22'h0; // @[Parameters.scala:137:46]
wire anonIn_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[Fragmenter.scala:92:9]
wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[Fragmenter.scala:92:9]
wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[Fragmenter.scala:92:9]
wire [2:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[Fragmenter.scala:92:9]
wire [4:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[Fragmenter.scala:92:9]
wire [20:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[Fragmenter.scala:92:9]
wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[Fragmenter.scala:92:9]
wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[Fragmenter.scala:92:9]
wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[Fragmenter.scala:92:9]
wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[Fragmenter.scala:92:9]
wire anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Fragmenter.scala:92:9]
wire anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [1:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [8:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [20:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire anonOut_d_ready; // @[MixedNode.scala:542:17]
wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Fragmenter.scala:92:9]
wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Fragmenter.scala:92:9]
wire [1:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Fragmenter.scala:92:9]
wire [8:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Fragmenter.scala:92:9]
wire auto_anon_in_a_ready_0; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_in_d_bits_opcode_0; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_in_d_bits_size_0; // @[Fragmenter.scala:92:9]
wire [4:0] auto_anon_in_d_bits_source_0; // @[Fragmenter.scala:92:9]
wire auto_anon_in_d_valid_0; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_out_a_bits_param_0; // @[Fragmenter.scala:92:9]
wire [1:0] auto_anon_out_a_bits_size_0; // @[Fragmenter.scala:92:9]
wire [8:0] auto_anon_out_a_bits_source_0; // @[Fragmenter.scala:92:9]
wire [20:0] auto_anon_out_a_bits_address_0; // @[Fragmenter.scala:92:9]
wire [7:0] auto_anon_out_a_bits_mask_0; // @[Fragmenter.scala:92:9]
wire [63:0] auto_anon_out_a_bits_data_0; // @[Fragmenter.scala:92:9]
wire auto_anon_out_a_bits_corrupt_0; // @[Fragmenter.scala:92:9]
wire auto_anon_out_a_valid_0; // @[Fragmenter.scala:92:9]
wire auto_anon_out_d_ready_0; // @[Fragmenter.scala:92:9]
assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[Fragmenter.scala:92:9]
assign anonOut_a_bits_data = anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire _anonIn_d_valid_T_1; // @[Fragmenter.scala:236:36]
assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[Fragmenter.scala:92:9]
assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Fragmenter.scala:92:9]
wire [2:0] _anonIn_d_bits_size_T; // @[Fragmenter.scala:239:32]
assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[Fragmenter.scala:92:9]
wire [4:0] _anonIn_d_bits_source_T; // @[Fragmenter.scala:238:47]
assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Fragmenter.scala:92:9]
wire [8:0] _anonOut_a_bits_source_T; // @[Fragmenter.scala:317:33]
assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Fragmenter.scala:92:9]
wire [20:0] _anonOut_a_bits_address_T_6; // @[Fragmenter.scala:316:49]
assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Fragmenter.scala:92:9]
wire [7:0] _anonOut_a_bits_mask_T; // @[Fragmenter.scala:325:31]
assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Fragmenter.scala:92:9]
wire _anonOut_d_ready_T; // @[Fragmenter.scala:235:35]
assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Fragmenter.scala:92:9]
assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] dsizeOH_shiftAmount = anonOut_d_bits_size; // @[OneHot.scala:64:49]
reg [2:0] acknum; // @[Fragmenter.scala:201:29]
reg [2:0] dOrig; // @[Fragmenter.scala:202:24]
reg dToggle; // @[Fragmenter.scala:203:30]
wire [2:0] dFragnum = anonOut_d_bits_source[2:0]; // @[Fragmenter.scala:204:41]
wire [2:0] acknum_fragment = dFragnum; // @[Fragmenter.scala:204:41, :212:40]
wire dFirst = acknum == 3'h0; // @[Fragmenter.scala:201:29, :205:29]
wire dLast = dFragnum == 3'h0; // @[Fragmenter.scala:204:41, :206:30]
wire _drop_T_1 = dLast; // @[Fragmenter.scala:206:30, :234:37]
wire [3:0] _dsizeOH_T = 4'h1 << dsizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [3:0] dsizeOH = _dsizeOH_T; // @[OneHot.scala:65:{12,27}]
wire [5:0] _dsizeOH1_T = 6'h7 << anonOut_d_bits_size; // @[package.scala:243:71]
wire [2:0] _dsizeOH1_T_1 = _dsizeOH1_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] dsizeOH1 = ~_dsizeOH1_T_1; // @[package.scala:243:{46,76}]
wire dHasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [2:0] dFirst_acknum = acknum_fragment; // @[Fragmenter.scala:212:40, :215:45]
wire _ack_decrement_T = dsizeOH[3]; // @[OneHot.scala:65:27]
wire ack_decrement = dHasData | _ack_decrement_T; // @[Fragmenter.scala:216:{32,56}]
wire [5:0] _dFirst_size_T = {dFragnum, 3'h0}; // @[Fragmenter.scala:204:41, :218:47]
wire [5:0] _dFirst_size_T_1 = {_dFirst_size_T[5:3], _dFirst_size_T[2:0] | dsizeOH1}; // @[package.scala:243:46]
wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala:241:35]
wire [6:0] _dFirst_size_T_3 = {_dFirst_size_T_2[6:1], 1'h1}; // @[package.scala:241:{35,40}]
wire [6:0] _dFirst_size_T_4 = {1'h0, _dFirst_size_T_1}; // @[package.scala:241:53]
wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala:241:{49,53}]
wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala:241:{40,47,49}]
wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala:30:18]
wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala:31:18]
wire _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi} | dFirst_size_lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _dFirst_size_T_11 = _dFirst_size_T_10[1]; // @[OneHot.scala:32:28]
wire [1:0] _dFirst_size_T_12 = {_dFirst_size_T_9, _dFirst_size_T_11}; // @[OneHot.scala:32:{10,14}]
wire [2:0] dFirst_size = {_dFirst_size_T_7, _dFirst_size_T_12}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _acknum_T = {1'h0, acknum} - {3'h0, ack_decrement}; // @[Fragmenter.scala:201:29, :216:32, :221:55]
wire [2:0] _acknum_T_1 = _acknum_T[2:0]; // @[Fragmenter.scala:221:55]
wire [2:0] _acknum_T_2 = dFirst ? dFirst_acknum : _acknum_T_1; // @[Fragmenter.scala:205:29, :215:45, :221:{24,55}]
wire _dToggle_T = anonOut_d_bits_source[3]; // @[Fragmenter.scala:224:41]
wire _drop_T = ~dHasData; // @[Fragmenter.scala:234:20]
wire _drop_T_2 = ~_drop_T_1; // @[Fragmenter.scala:234:{33,37}]
wire drop = _drop_T & _drop_T_2; // @[Fragmenter.scala:234:{20,30,33}]
assign _anonOut_d_ready_T = anonIn_d_ready | drop; // @[Fragmenter.scala:234:30, :235:35]
assign anonOut_d_ready = _anonOut_d_ready_T; // @[Fragmenter.scala:235:35]
wire _anonIn_d_valid_T = ~drop; // @[Fragmenter.scala:234:30, :236:39]
assign _anonIn_d_valid_T_1 = anonOut_d_valid & _anonIn_d_valid_T; // @[Fragmenter.scala:236:{36,39}]
assign anonIn_d_valid = _anonIn_d_valid_T_1; // @[Fragmenter.scala:236:36]
assign _anonIn_d_bits_source_T = anonOut_d_bits_source[8:4]; // @[Fragmenter.scala:238:47]
assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Fragmenter.scala:238:47]
assign _anonIn_d_bits_size_T = dFirst ? dFirst_size : dOrig; // @[OneHot.scala:32:10]
assign anonIn_d_bits_size = _anonIn_d_bits_size_T; // @[Fragmenter.scala:239:32]
wire [20:0] _find_T; // @[Parameters.scala:137:31]
wire [21:0] _find_T_1 = {1'h0, _find_T}; // @[Parameters.scala:137:{31,41}]
wire _limit_T = _repeater_io_deq_bits_opcode == 3'h0; // @[Fragmenter.scala:274:30, :288:49]
wire _limit_T_2 = _repeater_io_deq_bits_opcode == 3'h1; // @[Fragmenter.scala:274:30, :288:49]
wire _limit_T_4 = _repeater_io_deq_bits_opcode == 3'h2; // @[Fragmenter.scala:274:30, :288:49]
wire _limit_T_6 = _repeater_io_deq_bits_opcode == 3'h3; // @[Fragmenter.scala:274:30, :288:49]
wire _limit_T_8 = _repeater_io_deq_bits_opcode == 3'h4; // @[Fragmenter.scala:274:30, :288:49]
wire _limit_T_10 = _repeater_io_deq_bits_opcode == 3'h5; // @[Fragmenter.scala:274:30, :288:49]
wire _aFrag_T = _repeater_io_deq_bits_size[2]; // @[Fragmenter.scala:274:30, :297:31]
wire [2:0] aFrag = _aFrag_T ? 3'h3 : _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30, :297:{24,31}]
wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71]
wire [5:0] _aOrigOH1_T_1 = _aOrigOH1_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1; // @[package.scala:243:{46,76}]
wire [9:0] _aFragOH1_T = 10'h7 << aFrag; // @[package.scala:243:71]
wire [2:0] _aFragOH1_T_1 = _aFragOH1_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] aFragOH1 = ~_aFragOH1_T_1; // @[package.scala:243:{46,76}]
wire _aHasData_opdata_T = _repeater_io_deq_bits_opcode[2]; // @[Fragmenter.scala:274:30]
wire aHasData = ~_aHasData_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] aMask = aHasData ? 3'h0 : aFragOH1; // @[package.scala:243:46]
reg [2:0] gennum; // @[Fragmenter.scala:303:29]
wire aFirst = gennum == 3'h0; // @[Fragmenter.scala:303:29, :304:29]
wire [2:0] _old_gennum1_T = aOrigOH1[5:3]; // @[package.scala:243:46]
wire [3:0] _old_gennum1_T_1 = {1'h0, gennum} - 4'h1; // @[Fragmenter.scala:303:29, :305:79]
wire [2:0] _old_gennum1_T_2 = _old_gennum1_T_1[2:0]; // @[Fragmenter.scala:305:79]
wire [2:0] old_gennum1 = aFirst ? _old_gennum1_T : _old_gennum1_T_2; // @[Fragmenter.scala:304:29, :305:{30,48,79}]
wire [2:0] _aFragnum_T = old_gennum1; // @[Fragmenter.scala:305:30, :307:40]
wire [2:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala:305:30, :306:28]
wire [2:0] _new_gennum_T_2 = _new_gennum_T; // @[Fragmenter.scala:306:{28,41}]
wire [2:0] new_gennum = ~_new_gennum_T_2; // @[Fragmenter.scala:306:{26,41}]
wire [2:0] _aFragnum_T_1 = ~_aFragnum_T; // @[Fragmenter.scala:307:{26,40}]
wire [2:0] _aFragnum_T_3 = _aFragnum_T_1; // @[Fragmenter.scala:307:{26,72}]
wire [2:0] aFragnum = ~_aFragnum_T_3; // @[Fragmenter.scala:307:{24,72}]
wire aLast = ~(|aFragnum); // @[Fragmenter.scala:307:24, :308:30]
reg aToggle_r; // @[Fragmenter.scala:309:54]
wire _aToggle_T = aFirst ? dToggle : aToggle_r; // @[Fragmenter.scala:203:30, :304:29, :309:{27,54}]
wire aToggle = ~_aToggle_T; // @[Fragmenter.scala:309:{23,27}]
wire _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala:314:31]
wire _repeater_io_repeat_T_1 = |aFragnum; // @[Fragmenter.scala:307:24, :308:30, :314:53]
wire _repeater_io_repeat_T_2 = _repeater_io_repeat_T & _repeater_io_repeat_T_1; // @[Fragmenter.scala:314:{31,41,53}]
wire [5:0] _anonOut_a_bits_address_T = {old_gennum1, 3'h0}; // @[Fragmenter.scala:305:30, :316:65]
wire [5:0] _anonOut_a_bits_address_T_1 = ~aOrigOH1; // @[package.scala:243:46]
wire [5:0] _anonOut_a_bits_address_T_2 = _anonOut_a_bits_address_T | _anonOut_a_bits_address_T_1; // @[Fragmenter.scala:316:{65,88,90}]
wire [5:0] _anonOut_a_bits_address_T_3 = {_anonOut_a_bits_address_T_2[5:3], _anonOut_a_bits_address_T_2[2:0] | aFragOH1}; // @[package.scala:243:46]
wire [5:0] _anonOut_a_bits_address_T_4 = {_anonOut_a_bits_address_T_3[5:3], 3'h7}; // @[Fragmenter.scala:316:{100,111}]
wire [5:0] _anonOut_a_bits_address_T_5 = ~_anonOut_a_bits_address_T_4; // @[Fragmenter.scala:316:{51,111}]
assign _anonOut_a_bits_address_T_6 = {_repeater_io_deq_bits_address[20:6], _repeater_io_deq_bits_address[5:0] | _anonOut_a_bits_address_T_5}; // @[Fragmenter.scala:274:30, :316:{49,51}]
assign anonOut_a_bits_address = _anonOut_a_bits_address_T_6; // @[Fragmenter.scala:316:49]
wire [5:0] anonOut_a_bits_source_hi = {_repeater_io_deq_bits_source, aToggle}; // @[Fragmenter.scala:274:30, :309:23, :317:33]
assign _anonOut_a_bits_source_T = {anonOut_a_bits_source_hi, aFragnum}; // @[Fragmenter.scala:307:24, :317:33]
assign anonOut_a_bits_source = _anonOut_a_bits_source_T; // @[Fragmenter.scala:317:33]
assign anonOut_a_bits_size = aFrag[1:0]; // @[Fragmenter.scala:297:24, :318:25] |
Generate the Verilog code corresponding to this FIRRTL code module MultiNextLinePrefetcher :
input clock : Clock
input reset : Reset
output io : { flip snoop : { valid : UInt<1>, bits : { write : UInt<1>, address : UInt}}, request : { flip ready : UInt<1>, valid : UInt<1>, bits : { write : UInt<1>, address : UInt}}, hit : UInt<1>}
connect io.request.valid, UInt<1>(0h0)
invalidate io.request.bits.address
invalidate io.request.bits.write
connect io.request.bits.address, UInt<1>(0h0)
connect io.hit, UInt<1>(0h0)
inst singles_0 of SingleNextLinePrefetcher
connect singles_0.clock, clock
connect singles_0.reset, reset
inst singles_1 of SingleNextLinePrefetcher_1
connect singles_1.clock, clock
connect singles_1.reset, reset
inst singles_2 of SingleNextLinePrefetcher_2
connect singles_2.clock, clock
connect singles_2.reset, reset
inst singles_3 of SingleNextLinePrefetcher_3
connect singles_3.clock, clock
connect singles_3.reset, reset
node _any_hit_T = or(singles_0.io.hit, singles_1.io.hit)
node _any_hit_T_1 = or(_any_hit_T, singles_2.io.hit)
node any_hit = or(_any_hit_T_1, singles_3.io.hit)
connect singles_0.io.snoop.valid, UInt<1>(0h0)
connect singles_1.io.snoop.valid, UInt<1>(0h0)
connect singles_2.io.snoop.valid, UInt<1>(0h0)
connect singles_3.io.snoop.valid, UInt<1>(0h0)
connect singles_0.io.snoop.bits.address, io.snoop.bits.address
connect singles_0.io.snoop.bits.write, io.snoop.bits.write
connect singles_1.io.snoop.bits.address, io.snoop.bits.address
connect singles_1.io.snoop.bits.write, io.snoop.bits.write
connect singles_2.io.snoop.bits.address, io.snoop.bits.address
connect singles_2.io.snoop.bits.write, io.snoop.bits.write
connect singles_3.io.snoop.bits.address, io.snoop.bits.address
connect singles_3.io.snoop.bits.write, io.snoop.bits.write
regreset state_reg : UInt<6>, clock, reset, UInt<6>(0h0)
when io.snoop.valid :
node _T = eq(any_hit, UInt<1>(0h0))
wire moreRecentVec : UInt<4>[3]
node _moreRecentVec_moreRecentVec_0_T = bits(state_reg, 2, 0)
node _moreRecentVec_moreRecentVec_0_T_1 = cat(_moreRecentVec_moreRecentVec_0_T, UInt<1>(0h0))
connect moreRecentVec[0], _moreRecentVec_moreRecentVec_0_T_1
node _moreRecentVec_moreRecentVec_1_T = bits(state_reg, 4, 3)
node _moreRecentVec_moreRecentVec_1_T_1 = cat(_moreRecentVec_moreRecentVec_1_T, UInt<2>(0h0))
connect moreRecentVec[1], _moreRecentVec_moreRecentVec_1_T_1
node _moreRecentVec_moreRecentVec_2_T = bits(state_reg, 5, 5)
node _moreRecentVec_moreRecentVec_2_T_1 = cat(_moreRecentVec_moreRecentVec_2_T, UInt<3>(0h0))
connect moreRecentVec[2], _moreRecentVec_moreRecentVec_2_T_1
node _mruWayDec_upperMoreRecent_T = bits(moreRecentVec[0], 3, 1)
node mruWayDec_upperMoreRecent = andr(_mruWayDec_upperMoreRecent_T)
node mruWayDec_0 = and(mruWayDec_upperMoreRecent, UInt<1>(0h1))
node _mruWayDec_upperMoreRecent_T_1 = bits(moreRecentVec[1], 3, 2)
node mruWayDec_upperMoreRecent_1 = andr(_mruWayDec_upperMoreRecent_T_1)
node _mruWayDec_lowerMoreRecent_T = bits(moreRecentVec[0], 1, 1)
node _mruWayDec_lowerMoreRecent_T_1 = eq(_mruWayDec_lowerMoreRecent_T, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_2 = bits(moreRecentVec[1], 1, 1)
node _mruWayDec_lowerMoreRecent_T_3 = eq(_mruWayDec_lowerMoreRecent_T_2, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_4 = bits(moreRecentVec[2], 1, 1)
node _mruWayDec_lowerMoreRecent_T_5 = eq(_mruWayDec_lowerMoreRecent_T_4, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_6 = and(_mruWayDec_lowerMoreRecent_T_1, _mruWayDec_lowerMoreRecent_T_3)
node mruWayDec_lowerMoreRecent = and(_mruWayDec_lowerMoreRecent_T_6, _mruWayDec_lowerMoreRecent_T_5)
node mruWayDec_1 = and(mruWayDec_upperMoreRecent_1, mruWayDec_lowerMoreRecent)
node _mruWayDec_upperMoreRecent_T_2 = bits(moreRecentVec[2], 3, 3)
node mruWayDec_upperMoreRecent_2 = andr(_mruWayDec_upperMoreRecent_T_2)
node _mruWayDec_lowerMoreRecent_T_7 = bits(moreRecentVec[0], 2, 2)
node _mruWayDec_lowerMoreRecent_T_8 = eq(_mruWayDec_lowerMoreRecent_T_7, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_9 = bits(moreRecentVec[1], 2, 2)
node _mruWayDec_lowerMoreRecent_T_10 = eq(_mruWayDec_lowerMoreRecent_T_9, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_11 = bits(moreRecentVec[2], 2, 2)
node _mruWayDec_lowerMoreRecent_T_12 = eq(_mruWayDec_lowerMoreRecent_T_11, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_13 = and(_mruWayDec_lowerMoreRecent_T_8, _mruWayDec_lowerMoreRecent_T_10)
node mruWayDec_lowerMoreRecent_1 = and(_mruWayDec_lowerMoreRecent_T_13, _mruWayDec_lowerMoreRecent_T_12)
node mruWayDec_2 = and(mruWayDec_upperMoreRecent_2, mruWayDec_lowerMoreRecent_1)
node _mruWayDec_lowerMoreRecent_T_14 = bits(moreRecentVec[0], 3, 3)
node _mruWayDec_lowerMoreRecent_T_15 = eq(_mruWayDec_lowerMoreRecent_T_14, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_16 = bits(moreRecentVec[1], 3, 3)
node _mruWayDec_lowerMoreRecent_T_17 = eq(_mruWayDec_lowerMoreRecent_T_16, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_18 = bits(moreRecentVec[2], 3, 3)
node _mruWayDec_lowerMoreRecent_T_19 = eq(_mruWayDec_lowerMoreRecent_T_18, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_20 = and(_mruWayDec_lowerMoreRecent_T_15, _mruWayDec_lowerMoreRecent_T_17)
node mruWayDec_lowerMoreRecent_2 = and(_mruWayDec_lowerMoreRecent_T_20, _mruWayDec_lowerMoreRecent_T_19)
node mruWayDec_3 = and(UInt<1>(0h1), mruWayDec_lowerMoreRecent_2)
node lo = cat(mruWayDec_1, mruWayDec_0)
node hi = cat(mruWayDec_3, mruWayDec_2)
node _T_1 = cat(hi, lo)
node hi_1 = bits(_T_1, 3, 2)
node lo_1 = bits(_T_1, 1, 0)
node _T_2 = orr(hi_1)
node _T_3 = or(hi_1, lo_1)
node _T_4 = bits(_T_3, 1, 1)
node _T_5 = cat(_T_2, _T_4)
node _T_6 = eq(_T_5, UInt<1>(0h0))
node _T_7 = and(_T, _T_6)
node _T_8 = or(singles_0.io.hit, _T_7)
when _T_8 :
connect singles_0.io.snoop.valid, UInt<1>(0h1)
wire moreRecentVec_1 : UInt<4>[3]
node _moreRecentVec_moreRecentVec_0_T_2 = bits(state_reg, 2, 0)
node _moreRecentVec_moreRecentVec_0_T_3 = cat(_moreRecentVec_moreRecentVec_0_T_2, UInt<1>(0h0))
connect moreRecentVec_1[0], _moreRecentVec_moreRecentVec_0_T_3
node _moreRecentVec_moreRecentVec_1_T_2 = bits(state_reg, 4, 3)
node _moreRecentVec_moreRecentVec_1_T_3 = cat(_moreRecentVec_moreRecentVec_1_T_2, UInt<2>(0h0))
connect moreRecentVec_1[1], _moreRecentVec_moreRecentVec_1_T_3
node _moreRecentVec_moreRecentVec_2_T_2 = bits(state_reg, 5, 5)
node _moreRecentVec_moreRecentVec_2_T_3 = cat(_moreRecentVec_moreRecentVec_2_T_2, UInt<3>(0h0))
connect moreRecentVec_1[2], _moreRecentVec_moreRecentVec_2_T_3
node _mruWayDec_upperMoreRecent_T_3 = bits(moreRecentVec_1[0], 3, 1)
node mruWayDec_upperMoreRecent_3 = andr(_mruWayDec_upperMoreRecent_T_3)
node mruWayDec_0_1 = and(mruWayDec_upperMoreRecent_3, UInt<1>(0h1))
node _mruWayDec_upperMoreRecent_T_4 = bits(moreRecentVec_1[1], 3, 2)
node mruWayDec_upperMoreRecent_4 = andr(_mruWayDec_upperMoreRecent_T_4)
node _mruWayDec_lowerMoreRecent_T_21 = bits(moreRecentVec_1[0], 1, 1)
node _mruWayDec_lowerMoreRecent_T_22 = eq(_mruWayDec_lowerMoreRecent_T_21, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_23 = bits(moreRecentVec_1[1], 1, 1)
node _mruWayDec_lowerMoreRecent_T_24 = eq(_mruWayDec_lowerMoreRecent_T_23, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_25 = bits(moreRecentVec_1[2], 1, 1)
node _mruWayDec_lowerMoreRecent_T_26 = eq(_mruWayDec_lowerMoreRecent_T_25, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_27 = and(_mruWayDec_lowerMoreRecent_T_22, _mruWayDec_lowerMoreRecent_T_24)
node mruWayDec_lowerMoreRecent_3 = and(_mruWayDec_lowerMoreRecent_T_27, _mruWayDec_lowerMoreRecent_T_26)
node mruWayDec_1_1 = and(mruWayDec_upperMoreRecent_4, mruWayDec_lowerMoreRecent_3)
node _mruWayDec_upperMoreRecent_T_5 = bits(moreRecentVec_1[2], 3, 3)
node mruWayDec_upperMoreRecent_5 = andr(_mruWayDec_upperMoreRecent_T_5)
node _mruWayDec_lowerMoreRecent_T_28 = bits(moreRecentVec_1[0], 2, 2)
node _mruWayDec_lowerMoreRecent_T_29 = eq(_mruWayDec_lowerMoreRecent_T_28, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_30 = bits(moreRecentVec_1[1], 2, 2)
node _mruWayDec_lowerMoreRecent_T_31 = eq(_mruWayDec_lowerMoreRecent_T_30, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_32 = bits(moreRecentVec_1[2], 2, 2)
node _mruWayDec_lowerMoreRecent_T_33 = eq(_mruWayDec_lowerMoreRecent_T_32, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_34 = and(_mruWayDec_lowerMoreRecent_T_29, _mruWayDec_lowerMoreRecent_T_31)
node mruWayDec_lowerMoreRecent_4 = and(_mruWayDec_lowerMoreRecent_T_34, _mruWayDec_lowerMoreRecent_T_33)
node mruWayDec_2_1 = and(mruWayDec_upperMoreRecent_5, mruWayDec_lowerMoreRecent_4)
node _mruWayDec_lowerMoreRecent_T_35 = bits(moreRecentVec_1[0], 3, 3)
node _mruWayDec_lowerMoreRecent_T_36 = eq(_mruWayDec_lowerMoreRecent_T_35, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_37 = bits(moreRecentVec_1[1], 3, 3)
node _mruWayDec_lowerMoreRecent_T_38 = eq(_mruWayDec_lowerMoreRecent_T_37, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_39 = bits(moreRecentVec_1[2], 3, 3)
node _mruWayDec_lowerMoreRecent_T_40 = eq(_mruWayDec_lowerMoreRecent_T_39, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_41 = and(_mruWayDec_lowerMoreRecent_T_36, _mruWayDec_lowerMoreRecent_T_38)
node mruWayDec_lowerMoreRecent_5 = and(_mruWayDec_lowerMoreRecent_T_41, _mruWayDec_lowerMoreRecent_T_40)
node mruWayDec_3_1 = and(UInt<1>(0h1), mruWayDec_lowerMoreRecent_5)
node lo_2 = cat(mruWayDec_1_1, mruWayDec_0_1)
node hi_2 = cat(mruWayDec_3_1, mruWayDec_2_1)
node _T_9 = cat(hi_2, lo_2)
node hi_3 = bits(_T_9, 3, 2)
node lo_3 = bits(_T_9, 1, 0)
node _T_10 = orr(hi_3)
node _T_11 = or(hi_3, lo_3)
node _T_12 = bits(_T_11, 1, 1)
node _T_13 = cat(_T_10, _T_12)
wire state_reg_nextState : UInt<4>[3]
wire state_reg_moreRecentVec : UInt<4>[3]
node _state_reg_moreRecentVec_moreRecentVec_0_T = bits(state_reg, 2, 0)
node _state_reg_moreRecentVec_moreRecentVec_0_T_1 = cat(_state_reg_moreRecentVec_moreRecentVec_0_T, UInt<1>(0h0))
connect state_reg_moreRecentVec[0], _state_reg_moreRecentVec_moreRecentVec_0_T_1
node _state_reg_moreRecentVec_moreRecentVec_1_T = bits(state_reg, 4, 3)
node _state_reg_moreRecentVec_moreRecentVec_1_T_1 = cat(_state_reg_moreRecentVec_moreRecentVec_1_T, UInt<2>(0h0))
connect state_reg_moreRecentVec[1], _state_reg_moreRecentVec_moreRecentVec_1_T_1
node _state_reg_moreRecentVec_moreRecentVec_2_T = bits(state_reg, 5, 5)
node _state_reg_moreRecentVec_moreRecentVec_2_T_1 = cat(_state_reg_moreRecentVec_moreRecentVec_2_T, UInt<3>(0h0))
connect state_reg_moreRecentVec[2], _state_reg_moreRecentVec_moreRecentVec_2_T_1
node state_reg_wayDec_shiftAmount = bits(_T_13, 1, 0)
node _state_reg_wayDec_T = dshl(UInt<1>(0h1), state_reg_wayDec_shiftAmount)
node state_reg_wayDec = bits(_state_reg_wayDec_T, 3, 0)
node _state_reg_nextState_0_T = eq(UInt<1>(0h0), _T_13)
node _state_reg_nextState_0_T_1 = or(state_reg_moreRecentVec[0], state_reg_wayDec)
node _state_reg_nextState_0_T_2 = mux(_state_reg_nextState_0_T, UInt<4>(0h0), _state_reg_nextState_0_T_1)
connect state_reg_nextState[0], _state_reg_nextState_0_T_2
node _state_reg_nextState_1_T = eq(UInt<1>(0h1), _T_13)
node _state_reg_nextState_1_T_1 = or(state_reg_moreRecentVec[1], state_reg_wayDec)
node _state_reg_nextState_1_T_2 = mux(_state_reg_nextState_1_T, UInt<4>(0h0), _state_reg_nextState_1_T_1)
connect state_reg_nextState[1], _state_reg_nextState_1_T_2
node _state_reg_nextState_2_T = eq(UInt<2>(0h2), _T_13)
node _state_reg_nextState_2_T_1 = or(state_reg_moreRecentVec[2], state_reg_wayDec)
node _state_reg_nextState_2_T_2 = mux(_state_reg_nextState_2_T, UInt<4>(0h0), _state_reg_nextState_2_T_1)
connect state_reg_nextState[2], _state_reg_nextState_2_T_2
node _state_reg_T = bits(state_reg_nextState[0], 3, 1)
node _state_reg_T_1 = bits(state_reg_nextState[1], 3, 2)
node _state_reg_T_2 = cat(_state_reg_T_1, _state_reg_T)
node _state_reg_T_3 = bits(state_reg_nextState[2], 3, 3)
node _state_reg_T_4 = cat(_state_reg_T_3, _state_reg_T_2)
connect state_reg, _state_reg_T_4
when singles_0.io.hit :
wire state_reg_nextState_1 : UInt<4>[3]
wire state_reg_moreRecentVec_1 : UInt<4>[3]
node _state_reg_moreRecentVec_moreRecentVec_0_T_2 = bits(state_reg, 2, 0)
node _state_reg_moreRecentVec_moreRecentVec_0_T_3 = cat(_state_reg_moreRecentVec_moreRecentVec_0_T_2, UInt<1>(0h0))
connect state_reg_moreRecentVec_1[0], _state_reg_moreRecentVec_moreRecentVec_0_T_3
node _state_reg_moreRecentVec_moreRecentVec_1_T_2 = bits(state_reg, 4, 3)
node _state_reg_moreRecentVec_moreRecentVec_1_T_3 = cat(_state_reg_moreRecentVec_moreRecentVec_1_T_2, UInt<2>(0h0))
connect state_reg_moreRecentVec_1[1], _state_reg_moreRecentVec_moreRecentVec_1_T_3
node _state_reg_moreRecentVec_moreRecentVec_2_T_2 = bits(state_reg, 5, 5)
node _state_reg_moreRecentVec_moreRecentVec_2_T_3 = cat(_state_reg_moreRecentVec_moreRecentVec_2_T_2, UInt<3>(0h0))
connect state_reg_moreRecentVec_1[2], _state_reg_moreRecentVec_moreRecentVec_2_T_3
node _state_reg_wayDec_T_1 = dshl(UInt<1>(0h1), UInt<2>(0h0))
node state_reg_wayDec_1 = bits(_state_reg_wayDec_T_1, 3, 0)
node _state_reg_nextState_0_T_3 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _state_reg_nextState_0_T_4 = or(state_reg_moreRecentVec_1[0], state_reg_wayDec_1)
node _state_reg_nextState_0_T_5 = mux(_state_reg_nextState_0_T_3, UInt<4>(0h0), _state_reg_nextState_0_T_4)
connect state_reg_nextState_1[0], _state_reg_nextState_0_T_5
node _state_reg_nextState_1_T_3 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _state_reg_nextState_1_T_4 = or(state_reg_moreRecentVec_1[1], state_reg_wayDec_1)
node _state_reg_nextState_1_T_5 = mux(_state_reg_nextState_1_T_3, UInt<4>(0h0), _state_reg_nextState_1_T_4)
connect state_reg_nextState_1[1], _state_reg_nextState_1_T_5
node _state_reg_nextState_2_T_3 = eq(UInt<2>(0h2), UInt<1>(0h0))
node _state_reg_nextState_2_T_4 = or(state_reg_moreRecentVec_1[2], state_reg_wayDec_1)
node _state_reg_nextState_2_T_5 = mux(_state_reg_nextState_2_T_3, UInt<4>(0h0), _state_reg_nextState_2_T_4)
connect state_reg_nextState_1[2], _state_reg_nextState_2_T_5
node _state_reg_T_5 = bits(state_reg_nextState_1[0], 3, 1)
node _state_reg_T_6 = bits(state_reg_nextState_1[1], 3, 2)
node _state_reg_T_7 = cat(_state_reg_T_6, _state_reg_T_5)
node _state_reg_T_8 = bits(state_reg_nextState_1[2], 3, 3)
node _state_reg_T_9 = cat(_state_reg_T_8, _state_reg_T_7)
connect state_reg, _state_reg_T_9
node _T_14 = eq(any_hit, UInt<1>(0h0))
wire moreRecentVec_2 : UInt<4>[3]
node _moreRecentVec_moreRecentVec_0_T_4 = bits(state_reg, 2, 0)
node _moreRecentVec_moreRecentVec_0_T_5 = cat(_moreRecentVec_moreRecentVec_0_T_4, UInt<1>(0h0))
connect moreRecentVec_2[0], _moreRecentVec_moreRecentVec_0_T_5
node _moreRecentVec_moreRecentVec_1_T_4 = bits(state_reg, 4, 3)
node _moreRecentVec_moreRecentVec_1_T_5 = cat(_moreRecentVec_moreRecentVec_1_T_4, UInt<2>(0h0))
connect moreRecentVec_2[1], _moreRecentVec_moreRecentVec_1_T_5
node _moreRecentVec_moreRecentVec_2_T_4 = bits(state_reg, 5, 5)
node _moreRecentVec_moreRecentVec_2_T_5 = cat(_moreRecentVec_moreRecentVec_2_T_4, UInt<3>(0h0))
connect moreRecentVec_2[2], _moreRecentVec_moreRecentVec_2_T_5
node _mruWayDec_upperMoreRecent_T_6 = bits(moreRecentVec_2[0], 3, 1)
node mruWayDec_upperMoreRecent_6 = andr(_mruWayDec_upperMoreRecent_T_6)
node mruWayDec_0_2 = and(mruWayDec_upperMoreRecent_6, UInt<1>(0h1))
node _mruWayDec_upperMoreRecent_T_7 = bits(moreRecentVec_2[1], 3, 2)
node mruWayDec_upperMoreRecent_7 = andr(_mruWayDec_upperMoreRecent_T_7)
node _mruWayDec_lowerMoreRecent_T_42 = bits(moreRecentVec_2[0], 1, 1)
node _mruWayDec_lowerMoreRecent_T_43 = eq(_mruWayDec_lowerMoreRecent_T_42, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_44 = bits(moreRecentVec_2[1], 1, 1)
node _mruWayDec_lowerMoreRecent_T_45 = eq(_mruWayDec_lowerMoreRecent_T_44, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_46 = bits(moreRecentVec_2[2], 1, 1)
node _mruWayDec_lowerMoreRecent_T_47 = eq(_mruWayDec_lowerMoreRecent_T_46, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_48 = and(_mruWayDec_lowerMoreRecent_T_43, _mruWayDec_lowerMoreRecent_T_45)
node mruWayDec_lowerMoreRecent_6 = and(_mruWayDec_lowerMoreRecent_T_48, _mruWayDec_lowerMoreRecent_T_47)
node mruWayDec_1_2 = and(mruWayDec_upperMoreRecent_7, mruWayDec_lowerMoreRecent_6)
node _mruWayDec_upperMoreRecent_T_8 = bits(moreRecentVec_2[2], 3, 3)
node mruWayDec_upperMoreRecent_8 = andr(_mruWayDec_upperMoreRecent_T_8)
node _mruWayDec_lowerMoreRecent_T_49 = bits(moreRecentVec_2[0], 2, 2)
node _mruWayDec_lowerMoreRecent_T_50 = eq(_mruWayDec_lowerMoreRecent_T_49, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_51 = bits(moreRecentVec_2[1], 2, 2)
node _mruWayDec_lowerMoreRecent_T_52 = eq(_mruWayDec_lowerMoreRecent_T_51, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_53 = bits(moreRecentVec_2[2], 2, 2)
node _mruWayDec_lowerMoreRecent_T_54 = eq(_mruWayDec_lowerMoreRecent_T_53, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_55 = and(_mruWayDec_lowerMoreRecent_T_50, _mruWayDec_lowerMoreRecent_T_52)
node mruWayDec_lowerMoreRecent_7 = and(_mruWayDec_lowerMoreRecent_T_55, _mruWayDec_lowerMoreRecent_T_54)
node mruWayDec_2_2 = and(mruWayDec_upperMoreRecent_8, mruWayDec_lowerMoreRecent_7)
node _mruWayDec_lowerMoreRecent_T_56 = bits(moreRecentVec_2[0], 3, 3)
node _mruWayDec_lowerMoreRecent_T_57 = eq(_mruWayDec_lowerMoreRecent_T_56, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_58 = bits(moreRecentVec_2[1], 3, 3)
node _mruWayDec_lowerMoreRecent_T_59 = eq(_mruWayDec_lowerMoreRecent_T_58, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_60 = bits(moreRecentVec_2[2], 3, 3)
node _mruWayDec_lowerMoreRecent_T_61 = eq(_mruWayDec_lowerMoreRecent_T_60, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_62 = and(_mruWayDec_lowerMoreRecent_T_57, _mruWayDec_lowerMoreRecent_T_59)
node mruWayDec_lowerMoreRecent_8 = and(_mruWayDec_lowerMoreRecent_T_62, _mruWayDec_lowerMoreRecent_T_61)
node mruWayDec_3_2 = and(UInt<1>(0h1), mruWayDec_lowerMoreRecent_8)
node lo_4 = cat(mruWayDec_1_2, mruWayDec_0_2)
node hi_4 = cat(mruWayDec_3_2, mruWayDec_2_2)
node _T_15 = cat(hi_4, lo_4)
node hi_5 = bits(_T_15, 3, 2)
node lo_5 = bits(_T_15, 1, 0)
node _T_16 = orr(hi_5)
node _T_17 = or(hi_5, lo_5)
node _T_18 = bits(_T_17, 1, 1)
node _T_19 = cat(_T_16, _T_18)
node _T_20 = eq(_T_19, UInt<1>(0h1))
node _T_21 = and(_T_14, _T_20)
node _T_22 = or(singles_1.io.hit, _T_21)
when _T_22 :
connect singles_1.io.snoop.valid, UInt<1>(0h1)
wire moreRecentVec_3 : UInt<4>[3]
node _moreRecentVec_moreRecentVec_0_T_6 = bits(state_reg, 2, 0)
node _moreRecentVec_moreRecentVec_0_T_7 = cat(_moreRecentVec_moreRecentVec_0_T_6, UInt<1>(0h0))
connect moreRecentVec_3[0], _moreRecentVec_moreRecentVec_0_T_7
node _moreRecentVec_moreRecentVec_1_T_6 = bits(state_reg, 4, 3)
node _moreRecentVec_moreRecentVec_1_T_7 = cat(_moreRecentVec_moreRecentVec_1_T_6, UInt<2>(0h0))
connect moreRecentVec_3[1], _moreRecentVec_moreRecentVec_1_T_7
node _moreRecentVec_moreRecentVec_2_T_6 = bits(state_reg, 5, 5)
node _moreRecentVec_moreRecentVec_2_T_7 = cat(_moreRecentVec_moreRecentVec_2_T_6, UInt<3>(0h0))
connect moreRecentVec_3[2], _moreRecentVec_moreRecentVec_2_T_7
node _mruWayDec_upperMoreRecent_T_9 = bits(moreRecentVec_3[0], 3, 1)
node mruWayDec_upperMoreRecent_9 = andr(_mruWayDec_upperMoreRecent_T_9)
node mruWayDec_0_3 = and(mruWayDec_upperMoreRecent_9, UInt<1>(0h1))
node _mruWayDec_upperMoreRecent_T_10 = bits(moreRecentVec_3[1], 3, 2)
node mruWayDec_upperMoreRecent_10 = andr(_mruWayDec_upperMoreRecent_T_10)
node _mruWayDec_lowerMoreRecent_T_63 = bits(moreRecentVec_3[0], 1, 1)
node _mruWayDec_lowerMoreRecent_T_64 = eq(_mruWayDec_lowerMoreRecent_T_63, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_65 = bits(moreRecentVec_3[1], 1, 1)
node _mruWayDec_lowerMoreRecent_T_66 = eq(_mruWayDec_lowerMoreRecent_T_65, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_67 = bits(moreRecentVec_3[2], 1, 1)
node _mruWayDec_lowerMoreRecent_T_68 = eq(_mruWayDec_lowerMoreRecent_T_67, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_69 = and(_mruWayDec_lowerMoreRecent_T_64, _mruWayDec_lowerMoreRecent_T_66)
node mruWayDec_lowerMoreRecent_9 = and(_mruWayDec_lowerMoreRecent_T_69, _mruWayDec_lowerMoreRecent_T_68)
node mruWayDec_1_3 = and(mruWayDec_upperMoreRecent_10, mruWayDec_lowerMoreRecent_9)
node _mruWayDec_upperMoreRecent_T_11 = bits(moreRecentVec_3[2], 3, 3)
node mruWayDec_upperMoreRecent_11 = andr(_mruWayDec_upperMoreRecent_T_11)
node _mruWayDec_lowerMoreRecent_T_70 = bits(moreRecentVec_3[0], 2, 2)
node _mruWayDec_lowerMoreRecent_T_71 = eq(_mruWayDec_lowerMoreRecent_T_70, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_72 = bits(moreRecentVec_3[1], 2, 2)
node _mruWayDec_lowerMoreRecent_T_73 = eq(_mruWayDec_lowerMoreRecent_T_72, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_74 = bits(moreRecentVec_3[2], 2, 2)
node _mruWayDec_lowerMoreRecent_T_75 = eq(_mruWayDec_lowerMoreRecent_T_74, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_76 = and(_mruWayDec_lowerMoreRecent_T_71, _mruWayDec_lowerMoreRecent_T_73)
node mruWayDec_lowerMoreRecent_10 = and(_mruWayDec_lowerMoreRecent_T_76, _mruWayDec_lowerMoreRecent_T_75)
node mruWayDec_2_3 = and(mruWayDec_upperMoreRecent_11, mruWayDec_lowerMoreRecent_10)
node _mruWayDec_lowerMoreRecent_T_77 = bits(moreRecentVec_3[0], 3, 3)
node _mruWayDec_lowerMoreRecent_T_78 = eq(_mruWayDec_lowerMoreRecent_T_77, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_79 = bits(moreRecentVec_3[1], 3, 3)
node _mruWayDec_lowerMoreRecent_T_80 = eq(_mruWayDec_lowerMoreRecent_T_79, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_81 = bits(moreRecentVec_3[2], 3, 3)
node _mruWayDec_lowerMoreRecent_T_82 = eq(_mruWayDec_lowerMoreRecent_T_81, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_83 = and(_mruWayDec_lowerMoreRecent_T_78, _mruWayDec_lowerMoreRecent_T_80)
node mruWayDec_lowerMoreRecent_11 = and(_mruWayDec_lowerMoreRecent_T_83, _mruWayDec_lowerMoreRecent_T_82)
node mruWayDec_3_3 = and(UInt<1>(0h1), mruWayDec_lowerMoreRecent_11)
node lo_6 = cat(mruWayDec_1_3, mruWayDec_0_3)
node hi_6 = cat(mruWayDec_3_3, mruWayDec_2_3)
node _T_23 = cat(hi_6, lo_6)
node hi_7 = bits(_T_23, 3, 2)
node lo_7 = bits(_T_23, 1, 0)
node _T_24 = orr(hi_7)
node _T_25 = or(hi_7, lo_7)
node _T_26 = bits(_T_25, 1, 1)
node _T_27 = cat(_T_24, _T_26)
wire state_reg_nextState_2 : UInt<4>[3]
wire state_reg_moreRecentVec_2 : UInt<4>[3]
node _state_reg_moreRecentVec_moreRecentVec_0_T_4 = bits(state_reg, 2, 0)
node _state_reg_moreRecentVec_moreRecentVec_0_T_5 = cat(_state_reg_moreRecentVec_moreRecentVec_0_T_4, UInt<1>(0h0))
connect state_reg_moreRecentVec_2[0], _state_reg_moreRecentVec_moreRecentVec_0_T_5
node _state_reg_moreRecentVec_moreRecentVec_1_T_4 = bits(state_reg, 4, 3)
node _state_reg_moreRecentVec_moreRecentVec_1_T_5 = cat(_state_reg_moreRecentVec_moreRecentVec_1_T_4, UInt<2>(0h0))
connect state_reg_moreRecentVec_2[1], _state_reg_moreRecentVec_moreRecentVec_1_T_5
node _state_reg_moreRecentVec_moreRecentVec_2_T_4 = bits(state_reg, 5, 5)
node _state_reg_moreRecentVec_moreRecentVec_2_T_5 = cat(_state_reg_moreRecentVec_moreRecentVec_2_T_4, UInt<3>(0h0))
connect state_reg_moreRecentVec_2[2], _state_reg_moreRecentVec_moreRecentVec_2_T_5
node state_reg_wayDec_shiftAmount_1 = bits(_T_27, 1, 0)
node _state_reg_wayDec_T_2 = dshl(UInt<1>(0h1), state_reg_wayDec_shiftAmount_1)
node state_reg_wayDec_2 = bits(_state_reg_wayDec_T_2, 3, 0)
node _state_reg_nextState_0_T_6 = eq(UInt<1>(0h0), _T_27)
node _state_reg_nextState_0_T_7 = or(state_reg_moreRecentVec_2[0], state_reg_wayDec_2)
node _state_reg_nextState_0_T_8 = mux(_state_reg_nextState_0_T_6, UInt<4>(0h0), _state_reg_nextState_0_T_7)
connect state_reg_nextState_2[0], _state_reg_nextState_0_T_8
node _state_reg_nextState_1_T_6 = eq(UInt<1>(0h1), _T_27)
node _state_reg_nextState_1_T_7 = or(state_reg_moreRecentVec_2[1], state_reg_wayDec_2)
node _state_reg_nextState_1_T_8 = mux(_state_reg_nextState_1_T_6, UInt<4>(0h0), _state_reg_nextState_1_T_7)
connect state_reg_nextState_2[1], _state_reg_nextState_1_T_8
node _state_reg_nextState_2_T_6 = eq(UInt<2>(0h2), _T_27)
node _state_reg_nextState_2_T_7 = or(state_reg_moreRecentVec_2[2], state_reg_wayDec_2)
node _state_reg_nextState_2_T_8 = mux(_state_reg_nextState_2_T_6, UInt<4>(0h0), _state_reg_nextState_2_T_7)
connect state_reg_nextState_2[2], _state_reg_nextState_2_T_8
node _state_reg_T_10 = bits(state_reg_nextState_2[0], 3, 1)
node _state_reg_T_11 = bits(state_reg_nextState_2[1], 3, 2)
node _state_reg_T_12 = cat(_state_reg_T_11, _state_reg_T_10)
node _state_reg_T_13 = bits(state_reg_nextState_2[2], 3, 3)
node _state_reg_T_14 = cat(_state_reg_T_13, _state_reg_T_12)
connect state_reg, _state_reg_T_14
when singles_1.io.hit :
wire state_reg_nextState_3 : UInt<4>[3]
wire state_reg_moreRecentVec_3 : UInt<4>[3]
node _state_reg_moreRecentVec_moreRecentVec_0_T_6 = bits(state_reg, 2, 0)
node _state_reg_moreRecentVec_moreRecentVec_0_T_7 = cat(_state_reg_moreRecentVec_moreRecentVec_0_T_6, UInt<1>(0h0))
connect state_reg_moreRecentVec_3[0], _state_reg_moreRecentVec_moreRecentVec_0_T_7
node _state_reg_moreRecentVec_moreRecentVec_1_T_6 = bits(state_reg, 4, 3)
node _state_reg_moreRecentVec_moreRecentVec_1_T_7 = cat(_state_reg_moreRecentVec_moreRecentVec_1_T_6, UInt<2>(0h0))
connect state_reg_moreRecentVec_3[1], _state_reg_moreRecentVec_moreRecentVec_1_T_7
node _state_reg_moreRecentVec_moreRecentVec_2_T_6 = bits(state_reg, 5, 5)
node _state_reg_moreRecentVec_moreRecentVec_2_T_7 = cat(_state_reg_moreRecentVec_moreRecentVec_2_T_6, UInt<3>(0h0))
connect state_reg_moreRecentVec_3[2], _state_reg_moreRecentVec_moreRecentVec_2_T_7
node _state_reg_wayDec_T_3 = dshl(UInt<1>(0h1), UInt<2>(0h1))
node state_reg_wayDec_3 = bits(_state_reg_wayDec_T_3, 3, 0)
node _state_reg_nextState_0_T_9 = eq(UInt<1>(0h0), UInt<1>(0h1))
node _state_reg_nextState_0_T_10 = or(state_reg_moreRecentVec_3[0], state_reg_wayDec_3)
node _state_reg_nextState_0_T_11 = mux(_state_reg_nextState_0_T_9, UInt<4>(0h0), _state_reg_nextState_0_T_10)
connect state_reg_nextState_3[0], _state_reg_nextState_0_T_11
node _state_reg_nextState_1_T_9 = eq(UInt<1>(0h1), UInt<1>(0h1))
node _state_reg_nextState_1_T_10 = or(state_reg_moreRecentVec_3[1], state_reg_wayDec_3)
node _state_reg_nextState_1_T_11 = mux(_state_reg_nextState_1_T_9, UInt<4>(0h0), _state_reg_nextState_1_T_10)
connect state_reg_nextState_3[1], _state_reg_nextState_1_T_11
node _state_reg_nextState_2_T_9 = eq(UInt<2>(0h2), UInt<1>(0h1))
node _state_reg_nextState_2_T_10 = or(state_reg_moreRecentVec_3[2], state_reg_wayDec_3)
node _state_reg_nextState_2_T_11 = mux(_state_reg_nextState_2_T_9, UInt<4>(0h0), _state_reg_nextState_2_T_10)
connect state_reg_nextState_3[2], _state_reg_nextState_2_T_11
node _state_reg_T_15 = bits(state_reg_nextState_3[0], 3, 1)
node _state_reg_T_16 = bits(state_reg_nextState_3[1], 3, 2)
node _state_reg_T_17 = cat(_state_reg_T_16, _state_reg_T_15)
node _state_reg_T_18 = bits(state_reg_nextState_3[2], 3, 3)
node _state_reg_T_19 = cat(_state_reg_T_18, _state_reg_T_17)
connect state_reg, _state_reg_T_19
node _T_28 = eq(any_hit, UInt<1>(0h0))
wire moreRecentVec_4 : UInt<4>[3]
node _moreRecentVec_moreRecentVec_0_T_8 = bits(state_reg, 2, 0)
node _moreRecentVec_moreRecentVec_0_T_9 = cat(_moreRecentVec_moreRecentVec_0_T_8, UInt<1>(0h0))
connect moreRecentVec_4[0], _moreRecentVec_moreRecentVec_0_T_9
node _moreRecentVec_moreRecentVec_1_T_8 = bits(state_reg, 4, 3)
node _moreRecentVec_moreRecentVec_1_T_9 = cat(_moreRecentVec_moreRecentVec_1_T_8, UInt<2>(0h0))
connect moreRecentVec_4[1], _moreRecentVec_moreRecentVec_1_T_9
node _moreRecentVec_moreRecentVec_2_T_8 = bits(state_reg, 5, 5)
node _moreRecentVec_moreRecentVec_2_T_9 = cat(_moreRecentVec_moreRecentVec_2_T_8, UInt<3>(0h0))
connect moreRecentVec_4[2], _moreRecentVec_moreRecentVec_2_T_9
node _mruWayDec_upperMoreRecent_T_12 = bits(moreRecentVec_4[0], 3, 1)
node mruWayDec_upperMoreRecent_12 = andr(_mruWayDec_upperMoreRecent_T_12)
node mruWayDec_0_4 = and(mruWayDec_upperMoreRecent_12, UInt<1>(0h1))
node _mruWayDec_upperMoreRecent_T_13 = bits(moreRecentVec_4[1], 3, 2)
node mruWayDec_upperMoreRecent_13 = andr(_mruWayDec_upperMoreRecent_T_13)
node _mruWayDec_lowerMoreRecent_T_84 = bits(moreRecentVec_4[0], 1, 1)
node _mruWayDec_lowerMoreRecent_T_85 = eq(_mruWayDec_lowerMoreRecent_T_84, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_86 = bits(moreRecentVec_4[1], 1, 1)
node _mruWayDec_lowerMoreRecent_T_87 = eq(_mruWayDec_lowerMoreRecent_T_86, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_88 = bits(moreRecentVec_4[2], 1, 1)
node _mruWayDec_lowerMoreRecent_T_89 = eq(_mruWayDec_lowerMoreRecent_T_88, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_90 = and(_mruWayDec_lowerMoreRecent_T_85, _mruWayDec_lowerMoreRecent_T_87)
node mruWayDec_lowerMoreRecent_12 = and(_mruWayDec_lowerMoreRecent_T_90, _mruWayDec_lowerMoreRecent_T_89)
node mruWayDec_1_4 = and(mruWayDec_upperMoreRecent_13, mruWayDec_lowerMoreRecent_12)
node _mruWayDec_upperMoreRecent_T_14 = bits(moreRecentVec_4[2], 3, 3)
node mruWayDec_upperMoreRecent_14 = andr(_mruWayDec_upperMoreRecent_T_14)
node _mruWayDec_lowerMoreRecent_T_91 = bits(moreRecentVec_4[0], 2, 2)
node _mruWayDec_lowerMoreRecent_T_92 = eq(_mruWayDec_lowerMoreRecent_T_91, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_93 = bits(moreRecentVec_4[1], 2, 2)
node _mruWayDec_lowerMoreRecent_T_94 = eq(_mruWayDec_lowerMoreRecent_T_93, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_95 = bits(moreRecentVec_4[2], 2, 2)
node _mruWayDec_lowerMoreRecent_T_96 = eq(_mruWayDec_lowerMoreRecent_T_95, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_97 = and(_mruWayDec_lowerMoreRecent_T_92, _mruWayDec_lowerMoreRecent_T_94)
node mruWayDec_lowerMoreRecent_13 = and(_mruWayDec_lowerMoreRecent_T_97, _mruWayDec_lowerMoreRecent_T_96)
node mruWayDec_2_4 = and(mruWayDec_upperMoreRecent_14, mruWayDec_lowerMoreRecent_13)
node _mruWayDec_lowerMoreRecent_T_98 = bits(moreRecentVec_4[0], 3, 3)
node _mruWayDec_lowerMoreRecent_T_99 = eq(_mruWayDec_lowerMoreRecent_T_98, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_100 = bits(moreRecentVec_4[1], 3, 3)
node _mruWayDec_lowerMoreRecent_T_101 = eq(_mruWayDec_lowerMoreRecent_T_100, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_102 = bits(moreRecentVec_4[2], 3, 3)
node _mruWayDec_lowerMoreRecent_T_103 = eq(_mruWayDec_lowerMoreRecent_T_102, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_104 = and(_mruWayDec_lowerMoreRecent_T_99, _mruWayDec_lowerMoreRecent_T_101)
node mruWayDec_lowerMoreRecent_14 = and(_mruWayDec_lowerMoreRecent_T_104, _mruWayDec_lowerMoreRecent_T_103)
node mruWayDec_3_4 = and(UInt<1>(0h1), mruWayDec_lowerMoreRecent_14)
node lo_8 = cat(mruWayDec_1_4, mruWayDec_0_4)
node hi_8 = cat(mruWayDec_3_4, mruWayDec_2_4)
node _T_29 = cat(hi_8, lo_8)
node hi_9 = bits(_T_29, 3, 2)
node lo_9 = bits(_T_29, 1, 0)
node _T_30 = orr(hi_9)
node _T_31 = or(hi_9, lo_9)
node _T_32 = bits(_T_31, 1, 1)
node _T_33 = cat(_T_30, _T_32)
node _T_34 = eq(_T_33, UInt<2>(0h2))
node _T_35 = and(_T_28, _T_34)
node _T_36 = or(singles_2.io.hit, _T_35)
when _T_36 :
connect singles_2.io.snoop.valid, UInt<1>(0h1)
wire moreRecentVec_5 : UInt<4>[3]
node _moreRecentVec_moreRecentVec_0_T_10 = bits(state_reg, 2, 0)
node _moreRecentVec_moreRecentVec_0_T_11 = cat(_moreRecentVec_moreRecentVec_0_T_10, UInt<1>(0h0))
connect moreRecentVec_5[0], _moreRecentVec_moreRecentVec_0_T_11
node _moreRecentVec_moreRecentVec_1_T_10 = bits(state_reg, 4, 3)
node _moreRecentVec_moreRecentVec_1_T_11 = cat(_moreRecentVec_moreRecentVec_1_T_10, UInt<2>(0h0))
connect moreRecentVec_5[1], _moreRecentVec_moreRecentVec_1_T_11
node _moreRecentVec_moreRecentVec_2_T_10 = bits(state_reg, 5, 5)
node _moreRecentVec_moreRecentVec_2_T_11 = cat(_moreRecentVec_moreRecentVec_2_T_10, UInt<3>(0h0))
connect moreRecentVec_5[2], _moreRecentVec_moreRecentVec_2_T_11
node _mruWayDec_upperMoreRecent_T_15 = bits(moreRecentVec_5[0], 3, 1)
node mruWayDec_upperMoreRecent_15 = andr(_mruWayDec_upperMoreRecent_T_15)
node mruWayDec_0_5 = and(mruWayDec_upperMoreRecent_15, UInt<1>(0h1))
node _mruWayDec_upperMoreRecent_T_16 = bits(moreRecentVec_5[1], 3, 2)
node mruWayDec_upperMoreRecent_16 = andr(_mruWayDec_upperMoreRecent_T_16)
node _mruWayDec_lowerMoreRecent_T_105 = bits(moreRecentVec_5[0], 1, 1)
node _mruWayDec_lowerMoreRecent_T_106 = eq(_mruWayDec_lowerMoreRecent_T_105, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_107 = bits(moreRecentVec_5[1], 1, 1)
node _mruWayDec_lowerMoreRecent_T_108 = eq(_mruWayDec_lowerMoreRecent_T_107, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_109 = bits(moreRecentVec_5[2], 1, 1)
node _mruWayDec_lowerMoreRecent_T_110 = eq(_mruWayDec_lowerMoreRecent_T_109, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_111 = and(_mruWayDec_lowerMoreRecent_T_106, _mruWayDec_lowerMoreRecent_T_108)
node mruWayDec_lowerMoreRecent_15 = and(_mruWayDec_lowerMoreRecent_T_111, _mruWayDec_lowerMoreRecent_T_110)
node mruWayDec_1_5 = and(mruWayDec_upperMoreRecent_16, mruWayDec_lowerMoreRecent_15)
node _mruWayDec_upperMoreRecent_T_17 = bits(moreRecentVec_5[2], 3, 3)
node mruWayDec_upperMoreRecent_17 = andr(_mruWayDec_upperMoreRecent_T_17)
node _mruWayDec_lowerMoreRecent_T_112 = bits(moreRecentVec_5[0], 2, 2)
node _mruWayDec_lowerMoreRecent_T_113 = eq(_mruWayDec_lowerMoreRecent_T_112, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_114 = bits(moreRecentVec_5[1], 2, 2)
node _mruWayDec_lowerMoreRecent_T_115 = eq(_mruWayDec_lowerMoreRecent_T_114, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_116 = bits(moreRecentVec_5[2], 2, 2)
node _mruWayDec_lowerMoreRecent_T_117 = eq(_mruWayDec_lowerMoreRecent_T_116, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_118 = and(_mruWayDec_lowerMoreRecent_T_113, _mruWayDec_lowerMoreRecent_T_115)
node mruWayDec_lowerMoreRecent_16 = and(_mruWayDec_lowerMoreRecent_T_118, _mruWayDec_lowerMoreRecent_T_117)
node mruWayDec_2_5 = and(mruWayDec_upperMoreRecent_17, mruWayDec_lowerMoreRecent_16)
node _mruWayDec_lowerMoreRecent_T_119 = bits(moreRecentVec_5[0], 3, 3)
node _mruWayDec_lowerMoreRecent_T_120 = eq(_mruWayDec_lowerMoreRecent_T_119, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_121 = bits(moreRecentVec_5[1], 3, 3)
node _mruWayDec_lowerMoreRecent_T_122 = eq(_mruWayDec_lowerMoreRecent_T_121, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_123 = bits(moreRecentVec_5[2], 3, 3)
node _mruWayDec_lowerMoreRecent_T_124 = eq(_mruWayDec_lowerMoreRecent_T_123, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_125 = and(_mruWayDec_lowerMoreRecent_T_120, _mruWayDec_lowerMoreRecent_T_122)
node mruWayDec_lowerMoreRecent_17 = and(_mruWayDec_lowerMoreRecent_T_125, _mruWayDec_lowerMoreRecent_T_124)
node mruWayDec_3_5 = and(UInt<1>(0h1), mruWayDec_lowerMoreRecent_17)
node lo_10 = cat(mruWayDec_1_5, mruWayDec_0_5)
node hi_10 = cat(mruWayDec_3_5, mruWayDec_2_5)
node _T_37 = cat(hi_10, lo_10)
node hi_11 = bits(_T_37, 3, 2)
node lo_11 = bits(_T_37, 1, 0)
node _T_38 = orr(hi_11)
node _T_39 = or(hi_11, lo_11)
node _T_40 = bits(_T_39, 1, 1)
node _T_41 = cat(_T_38, _T_40)
wire state_reg_nextState_4 : UInt<4>[3]
wire state_reg_moreRecentVec_4 : UInt<4>[3]
node _state_reg_moreRecentVec_moreRecentVec_0_T_8 = bits(state_reg, 2, 0)
node _state_reg_moreRecentVec_moreRecentVec_0_T_9 = cat(_state_reg_moreRecentVec_moreRecentVec_0_T_8, UInt<1>(0h0))
connect state_reg_moreRecentVec_4[0], _state_reg_moreRecentVec_moreRecentVec_0_T_9
node _state_reg_moreRecentVec_moreRecentVec_1_T_8 = bits(state_reg, 4, 3)
node _state_reg_moreRecentVec_moreRecentVec_1_T_9 = cat(_state_reg_moreRecentVec_moreRecentVec_1_T_8, UInt<2>(0h0))
connect state_reg_moreRecentVec_4[1], _state_reg_moreRecentVec_moreRecentVec_1_T_9
node _state_reg_moreRecentVec_moreRecentVec_2_T_8 = bits(state_reg, 5, 5)
node _state_reg_moreRecentVec_moreRecentVec_2_T_9 = cat(_state_reg_moreRecentVec_moreRecentVec_2_T_8, UInt<3>(0h0))
connect state_reg_moreRecentVec_4[2], _state_reg_moreRecentVec_moreRecentVec_2_T_9
node state_reg_wayDec_shiftAmount_2 = bits(_T_41, 1, 0)
node _state_reg_wayDec_T_4 = dshl(UInt<1>(0h1), state_reg_wayDec_shiftAmount_2)
node state_reg_wayDec_4 = bits(_state_reg_wayDec_T_4, 3, 0)
node _state_reg_nextState_0_T_12 = eq(UInt<1>(0h0), _T_41)
node _state_reg_nextState_0_T_13 = or(state_reg_moreRecentVec_4[0], state_reg_wayDec_4)
node _state_reg_nextState_0_T_14 = mux(_state_reg_nextState_0_T_12, UInt<4>(0h0), _state_reg_nextState_0_T_13)
connect state_reg_nextState_4[0], _state_reg_nextState_0_T_14
node _state_reg_nextState_1_T_12 = eq(UInt<1>(0h1), _T_41)
node _state_reg_nextState_1_T_13 = or(state_reg_moreRecentVec_4[1], state_reg_wayDec_4)
node _state_reg_nextState_1_T_14 = mux(_state_reg_nextState_1_T_12, UInt<4>(0h0), _state_reg_nextState_1_T_13)
connect state_reg_nextState_4[1], _state_reg_nextState_1_T_14
node _state_reg_nextState_2_T_12 = eq(UInt<2>(0h2), _T_41)
node _state_reg_nextState_2_T_13 = or(state_reg_moreRecentVec_4[2], state_reg_wayDec_4)
node _state_reg_nextState_2_T_14 = mux(_state_reg_nextState_2_T_12, UInt<4>(0h0), _state_reg_nextState_2_T_13)
connect state_reg_nextState_4[2], _state_reg_nextState_2_T_14
node _state_reg_T_20 = bits(state_reg_nextState_4[0], 3, 1)
node _state_reg_T_21 = bits(state_reg_nextState_4[1], 3, 2)
node _state_reg_T_22 = cat(_state_reg_T_21, _state_reg_T_20)
node _state_reg_T_23 = bits(state_reg_nextState_4[2], 3, 3)
node _state_reg_T_24 = cat(_state_reg_T_23, _state_reg_T_22)
connect state_reg, _state_reg_T_24
when singles_2.io.hit :
wire state_reg_nextState_5 : UInt<4>[3]
wire state_reg_moreRecentVec_5 : UInt<4>[3]
node _state_reg_moreRecentVec_moreRecentVec_0_T_10 = bits(state_reg, 2, 0)
node _state_reg_moreRecentVec_moreRecentVec_0_T_11 = cat(_state_reg_moreRecentVec_moreRecentVec_0_T_10, UInt<1>(0h0))
connect state_reg_moreRecentVec_5[0], _state_reg_moreRecentVec_moreRecentVec_0_T_11
node _state_reg_moreRecentVec_moreRecentVec_1_T_10 = bits(state_reg, 4, 3)
node _state_reg_moreRecentVec_moreRecentVec_1_T_11 = cat(_state_reg_moreRecentVec_moreRecentVec_1_T_10, UInt<2>(0h0))
connect state_reg_moreRecentVec_5[1], _state_reg_moreRecentVec_moreRecentVec_1_T_11
node _state_reg_moreRecentVec_moreRecentVec_2_T_10 = bits(state_reg, 5, 5)
node _state_reg_moreRecentVec_moreRecentVec_2_T_11 = cat(_state_reg_moreRecentVec_moreRecentVec_2_T_10, UInt<3>(0h0))
connect state_reg_moreRecentVec_5[2], _state_reg_moreRecentVec_moreRecentVec_2_T_11
node _state_reg_wayDec_T_5 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node state_reg_wayDec_5 = bits(_state_reg_wayDec_T_5, 3, 0)
node _state_reg_nextState_0_T_15 = eq(UInt<1>(0h0), UInt<2>(0h2))
node _state_reg_nextState_0_T_16 = or(state_reg_moreRecentVec_5[0], state_reg_wayDec_5)
node _state_reg_nextState_0_T_17 = mux(_state_reg_nextState_0_T_15, UInt<4>(0h0), _state_reg_nextState_0_T_16)
connect state_reg_nextState_5[0], _state_reg_nextState_0_T_17
node _state_reg_nextState_1_T_15 = eq(UInt<1>(0h1), UInt<2>(0h2))
node _state_reg_nextState_1_T_16 = or(state_reg_moreRecentVec_5[1], state_reg_wayDec_5)
node _state_reg_nextState_1_T_17 = mux(_state_reg_nextState_1_T_15, UInt<4>(0h0), _state_reg_nextState_1_T_16)
connect state_reg_nextState_5[1], _state_reg_nextState_1_T_17
node _state_reg_nextState_2_T_15 = eq(UInt<2>(0h2), UInt<2>(0h2))
node _state_reg_nextState_2_T_16 = or(state_reg_moreRecentVec_5[2], state_reg_wayDec_5)
node _state_reg_nextState_2_T_17 = mux(_state_reg_nextState_2_T_15, UInt<4>(0h0), _state_reg_nextState_2_T_16)
connect state_reg_nextState_5[2], _state_reg_nextState_2_T_17
node _state_reg_T_25 = bits(state_reg_nextState_5[0], 3, 1)
node _state_reg_T_26 = bits(state_reg_nextState_5[1], 3, 2)
node _state_reg_T_27 = cat(_state_reg_T_26, _state_reg_T_25)
node _state_reg_T_28 = bits(state_reg_nextState_5[2], 3, 3)
node _state_reg_T_29 = cat(_state_reg_T_28, _state_reg_T_27)
connect state_reg, _state_reg_T_29
node _T_42 = eq(any_hit, UInt<1>(0h0))
wire moreRecentVec_6 : UInt<4>[3]
node _moreRecentVec_moreRecentVec_0_T_12 = bits(state_reg, 2, 0)
node _moreRecentVec_moreRecentVec_0_T_13 = cat(_moreRecentVec_moreRecentVec_0_T_12, UInt<1>(0h0))
connect moreRecentVec_6[0], _moreRecentVec_moreRecentVec_0_T_13
node _moreRecentVec_moreRecentVec_1_T_12 = bits(state_reg, 4, 3)
node _moreRecentVec_moreRecentVec_1_T_13 = cat(_moreRecentVec_moreRecentVec_1_T_12, UInt<2>(0h0))
connect moreRecentVec_6[1], _moreRecentVec_moreRecentVec_1_T_13
node _moreRecentVec_moreRecentVec_2_T_12 = bits(state_reg, 5, 5)
node _moreRecentVec_moreRecentVec_2_T_13 = cat(_moreRecentVec_moreRecentVec_2_T_12, UInt<3>(0h0))
connect moreRecentVec_6[2], _moreRecentVec_moreRecentVec_2_T_13
node _mruWayDec_upperMoreRecent_T_18 = bits(moreRecentVec_6[0], 3, 1)
node mruWayDec_upperMoreRecent_18 = andr(_mruWayDec_upperMoreRecent_T_18)
node mruWayDec_0_6 = and(mruWayDec_upperMoreRecent_18, UInt<1>(0h1))
node _mruWayDec_upperMoreRecent_T_19 = bits(moreRecentVec_6[1], 3, 2)
node mruWayDec_upperMoreRecent_19 = andr(_mruWayDec_upperMoreRecent_T_19)
node _mruWayDec_lowerMoreRecent_T_126 = bits(moreRecentVec_6[0], 1, 1)
node _mruWayDec_lowerMoreRecent_T_127 = eq(_mruWayDec_lowerMoreRecent_T_126, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_128 = bits(moreRecentVec_6[1], 1, 1)
node _mruWayDec_lowerMoreRecent_T_129 = eq(_mruWayDec_lowerMoreRecent_T_128, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_130 = bits(moreRecentVec_6[2], 1, 1)
node _mruWayDec_lowerMoreRecent_T_131 = eq(_mruWayDec_lowerMoreRecent_T_130, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_132 = and(_mruWayDec_lowerMoreRecent_T_127, _mruWayDec_lowerMoreRecent_T_129)
node mruWayDec_lowerMoreRecent_18 = and(_mruWayDec_lowerMoreRecent_T_132, _mruWayDec_lowerMoreRecent_T_131)
node mruWayDec_1_6 = and(mruWayDec_upperMoreRecent_19, mruWayDec_lowerMoreRecent_18)
node _mruWayDec_upperMoreRecent_T_20 = bits(moreRecentVec_6[2], 3, 3)
node mruWayDec_upperMoreRecent_20 = andr(_mruWayDec_upperMoreRecent_T_20)
node _mruWayDec_lowerMoreRecent_T_133 = bits(moreRecentVec_6[0], 2, 2)
node _mruWayDec_lowerMoreRecent_T_134 = eq(_mruWayDec_lowerMoreRecent_T_133, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_135 = bits(moreRecentVec_6[1], 2, 2)
node _mruWayDec_lowerMoreRecent_T_136 = eq(_mruWayDec_lowerMoreRecent_T_135, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_137 = bits(moreRecentVec_6[2], 2, 2)
node _mruWayDec_lowerMoreRecent_T_138 = eq(_mruWayDec_lowerMoreRecent_T_137, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_139 = and(_mruWayDec_lowerMoreRecent_T_134, _mruWayDec_lowerMoreRecent_T_136)
node mruWayDec_lowerMoreRecent_19 = and(_mruWayDec_lowerMoreRecent_T_139, _mruWayDec_lowerMoreRecent_T_138)
node mruWayDec_2_6 = and(mruWayDec_upperMoreRecent_20, mruWayDec_lowerMoreRecent_19)
node _mruWayDec_lowerMoreRecent_T_140 = bits(moreRecentVec_6[0], 3, 3)
node _mruWayDec_lowerMoreRecent_T_141 = eq(_mruWayDec_lowerMoreRecent_T_140, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_142 = bits(moreRecentVec_6[1], 3, 3)
node _mruWayDec_lowerMoreRecent_T_143 = eq(_mruWayDec_lowerMoreRecent_T_142, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_144 = bits(moreRecentVec_6[2], 3, 3)
node _mruWayDec_lowerMoreRecent_T_145 = eq(_mruWayDec_lowerMoreRecent_T_144, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_146 = and(_mruWayDec_lowerMoreRecent_T_141, _mruWayDec_lowerMoreRecent_T_143)
node mruWayDec_lowerMoreRecent_20 = and(_mruWayDec_lowerMoreRecent_T_146, _mruWayDec_lowerMoreRecent_T_145)
node mruWayDec_3_6 = and(UInt<1>(0h1), mruWayDec_lowerMoreRecent_20)
node lo_12 = cat(mruWayDec_1_6, mruWayDec_0_6)
node hi_12 = cat(mruWayDec_3_6, mruWayDec_2_6)
node _T_43 = cat(hi_12, lo_12)
node hi_13 = bits(_T_43, 3, 2)
node lo_13 = bits(_T_43, 1, 0)
node _T_44 = orr(hi_13)
node _T_45 = or(hi_13, lo_13)
node _T_46 = bits(_T_45, 1, 1)
node _T_47 = cat(_T_44, _T_46)
node _T_48 = eq(_T_47, UInt<2>(0h3))
node _T_49 = and(_T_42, _T_48)
node _T_50 = or(singles_3.io.hit, _T_49)
when _T_50 :
connect singles_3.io.snoop.valid, UInt<1>(0h1)
wire moreRecentVec_7 : UInt<4>[3]
node _moreRecentVec_moreRecentVec_0_T_14 = bits(state_reg, 2, 0)
node _moreRecentVec_moreRecentVec_0_T_15 = cat(_moreRecentVec_moreRecentVec_0_T_14, UInt<1>(0h0))
connect moreRecentVec_7[0], _moreRecentVec_moreRecentVec_0_T_15
node _moreRecentVec_moreRecentVec_1_T_14 = bits(state_reg, 4, 3)
node _moreRecentVec_moreRecentVec_1_T_15 = cat(_moreRecentVec_moreRecentVec_1_T_14, UInt<2>(0h0))
connect moreRecentVec_7[1], _moreRecentVec_moreRecentVec_1_T_15
node _moreRecentVec_moreRecentVec_2_T_14 = bits(state_reg, 5, 5)
node _moreRecentVec_moreRecentVec_2_T_15 = cat(_moreRecentVec_moreRecentVec_2_T_14, UInt<3>(0h0))
connect moreRecentVec_7[2], _moreRecentVec_moreRecentVec_2_T_15
node _mruWayDec_upperMoreRecent_T_21 = bits(moreRecentVec_7[0], 3, 1)
node mruWayDec_upperMoreRecent_21 = andr(_mruWayDec_upperMoreRecent_T_21)
node mruWayDec_0_7 = and(mruWayDec_upperMoreRecent_21, UInt<1>(0h1))
node _mruWayDec_upperMoreRecent_T_22 = bits(moreRecentVec_7[1], 3, 2)
node mruWayDec_upperMoreRecent_22 = andr(_mruWayDec_upperMoreRecent_T_22)
node _mruWayDec_lowerMoreRecent_T_147 = bits(moreRecentVec_7[0], 1, 1)
node _mruWayDec_lowerMoreRecent_T_148 = eq(_mruWayDec_lowerMoreRecent_T_147, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_149 = bits(moreRecentVec_7[1], 1, 1)
node _mruWayDec_lowerMoreRecent_T_150 = eq(_mruWayDec_lowerMoreRecent_T_149, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_151 = bits(moreRecentVec_7[2], 1, 1)
node _mruWayDec_lowerMoreRecent_T_152 = eq(_mruWayDec_lowerMoreRecent_T_151, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_153 = and(_mruWayDec_lowerMoreRecent_T_148, _mruWayDec_lowerMoreRecent_T_150)
node mruWayDec_lowerMoreRecent_21 = and(_mruWayDec_lowerMoreRecent_T_153, _mruWayDec_lowerMoreRecent_T_152)
node mruWayDec_1_7 = and(mruWayDec_upperMoreRecent_22, mruWayDec_lowerMoreRecent_21)
node _mruWayDec_upperMoreRecent_T_23 = bits(moreRecentVec_7[2], 3, 3)
node mruWayDec_upperMoreRecent_23 = andr(_mruWayDec_upperMoreRecent_T_23)
node _mruWayDec_lowerMoreRecent_T_154 = bits(moreRecentVec_7[0], 2, 2)
node _mruWayDec_lowerMoreRecent_T_155 = eq(_mruWayDec_lowerMoreRecent_T_154, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_156 = bits(moreRecentVec_7[1], 2, 2)
node _mruWayDec_lowerMoreRecent_T_157 = eq(_mruWayDec_lowerMoreRecent_T_156, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_158 = bits(moreRecentVec_7[2], 2, 2)
node _mruWayDec_lowerMoreRecent_T_159 = eq(_mruWayDec_lowerMoreRecent_T_158, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_160 = and(_mruWayDec_lowerMoreRecent_T_155, _mruWayDec_lowerMoreRecent_T_157)
node mruWayDec_lowerMoreRecent_22 = and(_mruWayDec_lowerMoreRecent_T_160, _mruWayDec_lowerMoreRecent_T_159)
node mruWayDec_2_7 = and(mruWayDec_upperMoreRecent_23, mruWayDec_lowerMoreRecent_22)
node _mruWayDec_lowerMoreRecent_T_161 = bits(moreRecentVec_7[0], 3, 3)
node _mruWayDec_lowerMoreRecent_T_162 = eq(_mruWayDec_lowerMoreRecent_T_161, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_163 = bits(moreRecentVec_7[1], 3, 3)
node _mruWayDec_lowerMoreRecent_T_164 = eq(_mruWayDec_lowerMoreRecent_T_163, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_165 = bits(moreRecentVec_7[2], 3, 3)
node _mruWayDec_lowerMoreRecent_T_166 = eq(_mruWayDec_lowerMoreRecent_T_165, UInt<1>(0h0))
node _mruWayDec_lowerMoreRecent_T_167 = and(_mruWayDec_lowerMoreRecent_T_162, _mruWayDec_lowerMoreRecent_T_164)
node mruWayDec_lowerMoreRecent_23 = and(_mruWayDec_lowerMoreRecent_T_167, _mruWayDec_lowerMoreRecent_T_166)
node mruWayDec_3_7 = and(UInt<1>(0h1), mruWayDec_lowerMoreRecent_23)
node lo_14 = cat(mruWayDec_1_7, mruWayDec_0_7)
node hi_14 = cat(mruWayDec_3_7, mruWayDec_2_7)
node _T_51 = cat(hi_14, lo_14)
node hi_15 = bits(_T_51, 3, 2)
node lo_15 = bits(_T_51, 1, 0)
node _T_52 = orr(hi_15)
node _T_53 = or(hi_15, lo_15)
node _T_54 = bits(_T_53, 1, 1)
node _T_55 = cat(_T_52, _T_54)
wire state_reg_nextState_6 : UInt<4>[3]
wire state_reg_moreRecentVec_6 : UInt<4>[3]
node _state_reg_moreRecentVec_moreRecentVec_0_T_12 = bits(state_reg, 2, 0)
node _state_reg_moreRecentVec_moreRecentVec_0_T_13 = cat(_state_reg_moreRecentVec_moreRecentVec_0_T_12, UInt<1>(0h0))
connect state_reg_moreRecentVec_6[0], _state_reg_moreRecentVec_moreRecentVec_0_T_13
node _state_reg_moreRecentVec_moreRecentVec_1_T_12 = bits(state_reg, 4, 3)
node _state_reg_moreRecentVec_moreRecentVec_1_T_13 = cat(_state_reg_moreRecentVec_moreRecentVec_1_T_12, UInt<2>(0h0))
connect state_reg_moreRecentVec_6[1], _state_reg_moreRecentVec_moreRecentVec_1_T_13
node _state_reg_moreRecentVec_moreRecentVec_2_T_12 = bits(state_reg, 5, 5)
node _state_reg_moreRecentVec_moreRecentVec_2_T_13 = cat(_state_reg_moreRecentVec_moreRecentVec_2_T_12, UInt<3>(0h0))
connect state_reg_moreRecentVec_6[2], _state_reg_moreRecentVec_moreRecentVec_2_T_13
node state_reg_wayDec_shiftAmount_3 = bits(_T_55, 1, 0)
node _state_reg_wayDec_T_6 = dshl(UInt<1>(0h1), state_reg_wayDec_shiftAmount_3)
node state_reg_wayDec_6 = bits(_state_reg_wayDec_T_6, 3, 0)
node _state_reg_nextState_0_T_18 = eq(UInt<1>(0h0), _T_55)
node _state_reg_nextState_0_T_19 = or(state_reg_moreRecentVec_6[0], state_reg_wayDec_6)
node _state_reg_nextState_0_T_20 = mux(_state_reg_nextState_0_T_18, UInt<4>(0h0), _state_reg_nextState_0_T_19)
connect state_reg_nextState_6[0], _state_reg_nextState_0_T_20
node _state_reg_nextState_1_T_18 = eq(UInt<1>(0h1), _T_55)
node _state_reg_nextState_1_T_19 = or(state_reg_moreRecentVec_6[1], state_reg_wayDec_6)
node _state_reg_nextState_1_T_20 = mux(_state_reg_nextState_1_T_18, UInt<4>(0h0), _state_reg_nextState_1_T_19)
connect state_reg_nextState_6[1], _state_reg_nextState_1_T_20
node _state_reg_nextState_2_T_18 = eq(UInt<2>(0h2), _T_55)
node _state_reg_nextState_2_T_19 = or(state_reg_moreRecentVec_6[2], state_reg_wayDec_6)
node _state_reg_nextState_2_T_20 = mux(_state_reg_nextState_2_T_18, UInt<4>(0h0), _state_reg_nextState_2_T_19)
connect state_reg_nextState_6[2], _state_reg_nextState_2_T_20
node _state_reg_T_30 = bits(state_reg_nextState_6[0], 3, 1)
node _state_reg_T_31 = bits(state_reg_nextState_6[1], 3, 2)
node _state_reg_T_32 = cat(_state_reg_T_31, _state_reg_T_30)
node _state_reg_T_33 = bits(state_reg_nextState_6[2], 3, 3)
node _state_reg_T_34 = cat(_state_reg_T_33, _state_reg_T_32)
connect state_reg, _state_reg_T_34
when singles_3.io.hit :
wire state_reg_nextState_7 : UInt<4>[3]
wire state_reg_moreRecentVec_7 : UInt<4>[3]
node _state_reg_moreRecentVec_moreRecentVec_0_T_14 = bits(state_reg, 2, 0)
node _state_reg_moreRecentVec_moreRecentVec_0_T_15 = cat(_state_reg_moreRecentVec_moreRecentVec_0_T_14, UInt<1>(0h0))
connect state_reg_moreRecentVec_7[0], _state_reg_moreRecentVec_moreRecentVec_0_T_15
node _state_reg_moreRecentVec_moreRecentVec_1_T_14 = bits(state_reg, 4, 3)
node _state_reg_moreRecentVec_moreRecentVec_1_T_15 = cat(_state_reg_moreRecentVec_moreRecentVec_1_T_14, UInt<2>(0h0))
connect state_reg_moreRecentVec_7[1], _state_reg_moreRecentVec_moreRecentVec_1_T_15
node _state_reg_moreRecentVec_moreRecentVec_2_T_14 = bits(state_reg, 5, 5)
node _state_reg_moreRecentVec_moreRecentVec_2_T_15 = cat(_state_reg_moreRecentVec_moreRecentVec_2_T_14, UInt<3>(0h0))
connect state_reg_moreRecentVec_7[2], _state_reg_moreRecentVec_moreRecentVec_2_T_15
node _state_reg_wayDec_T_7 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node state_reg_wayDec_7 = bits(_state_reg_wayDec_T_7, 3, 0)
node _state_reg_nextState_0_T_21 = eq(UInt<1>(0h0), UInt<2>(0h3))
node _state_reg_nextState_0_T_22 = or(state_reg_moreRecentVec_7[0], state_reg_wayDec_7)
node _state_reg_nextState_0_T_23 = mux(_state_reg_nextState_0_T_21, UInt<4>(0h0), _state_reg_nextState_0_T_22)
connect state_reg_nextState_7[0], _state_reg_nextState_0_T_23
node _state_reg_nextState_1_T_21 = eq(UInt<1>(0h1), UInt<2>(0h3))
node _state_reg_nextState_1_T_22 = or(state_reg_moreRecentVec_7[1], state_reg_wayDec_7)
node _state_reg_nextState_1_T_23 = mux(_state_reg_nextState_1_T_21, UInt<4>(0h0), _state_reg_nextState_1_T_22)
connect state_reg_nextState_7[1], _state_reg_nextState_1_T_23
node _state_reg_nextState_2_T_21 = eq(UInt<2>(0h2), UInt<2>(0h3))
node _state_reg_nextState_2_T_22 = or(state_reg_moreRecentVec_7[2], state_reg_wayDec_7)
node _state_reg_nextState_2_T_23 = mux(_state_reg_nextState_2_T_21, UInt<4>(0h0), _state_reg_nextState_2_T_22)
connect state_reg_nextState_7[2], _state_reg_nextState_2_T_23
node _state_reg_T_35 = bits(state_reg_nextState_7[0], 3, 1)
node _state_reg_T_36 = bits(state_reg_nextState_7[1], 3, 2)
node _state_reg_T_37 = cat(_state_reg_T_36, _state_reg_T_35)
node _state_reg_T_38 = bits(state_reg_nextState_7[2], 3, 3)
node _state_reg_T_39 = cat(_state_reg_T_38, _state_reg_T_37)
connect state_reg, _state_reg_T_39
inst arb of RRArbiter
connect arb.clock, clock
connect arb.reset, reset
connect arb.io.in[0], singles_0.io.request
connect arb.io.in[1], singles_1.io.request
connect arb.io.in[2], singles_2.io.request
connect arb.io.in[3], singles_3.io.request
connect io.request.bits, arb.io.out.bits
connect io.request.valid, arb.io.out.valid
connect arb.io.out.ready, io.request.ready | module MultiNextLinePrefetcher( // @[NextLine.scala:109:7]
input clock, // @[NextLine.scala:109:7]
input reset, // @[NextLine.scala:109:7]
input io_snoop_valid, // @[AbstractPrefetcher.scala:41:14]
input io_snoop_bits_write, // @[AbstractPrefetcher.scala:41:14]
input [31:0] io_snoop_bits_address, // @[AbstractPrefetcher.scala:41:14]
input io_request_ready, // @[AbstractPrefetcher.scala:41:14]
output io_request_valid, // @[AbstractPrefetcher.scala:41:14]
output io_request_bits_write, // @[AbstractPrefetcher.scala:41:14]
output [31:0] io_request_bits_address // @[AbstractPrefetcher.scala:41:14]
);
wire _arb_io_in_0_ready; // @[NextLine.scala:128:19]
wire _arb_io_in_1_ready; // @[NextLine.scala:128:19]
wire _arb_io_in_2_ready; // @[NextLine.scala:128:19]
wire _arb_io_in_3_ready; // @[NextLine.scala:128:19]
wire _singles_3_io_request_valid; // @[NextLine.scala:17:53]
wire _singles_3_io_request_bits_write; // @[NextLine.scala:17:53]
wire [31:0] _singles_3_io_request_bits_address; // @[NextLine.scala:17:53]
wire _singles_3_io_hit; // @[NextLine.scala:17:53]
wire _singles_2_io_request_valid; // @[NextLine.scala:17:53]
wire _singles_2_io_request_bits_write; // @[NextLine.scala:17:53]
wire [31:0] _singles_2_io_request_bits_address; // @[NextLine.scala:17:53]
wire _singles_2_io_hit; // @[NextLine.scala:17:53]
wire _singles_1_io_request_valid; // @[NextLine.scala:17:53]
wire _singles_1_io_request_bits_write; // @[NextLine.scala:17:53]
wire [31:0] _singles_1_io_request_bits_address; // @[NextLine.scala:17:53]
wire _singles_1_io_hit; // @[NextLine.scala:17:53]
wire _singles_0_io_request_valid; // @[NextLine.scala:17:53]
wire _singles_0_io_request_bits_write; // @[NextLine.scala:17:53]
wire [31:0] _singles_0_io_request_bits_address; // @[NextLine.scala:17:53]
wire _singles_0_io_hit; // @[NextLine.scala:17:53]
wire io_snoop_valid_0 = io_snoop_valid; // @[NextLine.scala:109:7]
wire io_snoop_bits_write_0 = io_snoop_bits_write; // @[NextLine.scala:109:7]
wire [31:0] io_snoop_bits_address_0 = io_snoop_bits_address; // @[NextLine.scala:109:7]
wire io_request_ready_0 = io_request_ready; // @[NextLine.scala:109:7]
wire _state_reg_nextState_0_T_3 = 1'h1; // @[Replacement.scala:107:20]
wire _state_reg_nextState_1_T_9 = 1'h1; // @[Replacement.scala:107:20]
wire _state_reg_nextState_2_T_15 = 1'h1; // @[Replacement.scala:107:20]
wire [3:0] _state_reg_wayDec_T_1 = 4'h1; // @[OneHot.scala:65:12]
wire [3:0] state_reg_wayDec_1 = 4'h1; // @[OneHot.scala:65:{12,27}]
wire [2:0] _state_reg_T_5 = 3'h0; // @[Replacement.scala:110:63]
wire [3:0] _state_reg_wayDec_T_3 = 4'h2; // @[OneHot.scala:65:12]
wire [3:0] state_reg_wayDec_3 = 4'h2; // @[OneHot.scala:65:27]
wire [1:0] _state_reg_T_16 = 2'h0; // @[Replacement.scala:110:121]
wire [3:0] _state_reg_wayDec_T_5 = 4'h4; // @[OneHot.scala:65:12]
wire [3:0] state_reg_wayDec_5 = 4'h4; // @[OneHot.scala:65:27]
wire [3:0] state_reg_nextState_1_0 = 4'h0; // @[Replacement.scala:100:29]
wire [3:0] _state_reg_nextState_0_T_5 = 4'h0; // @[Replacement.scala:107:15]
wire [3:0] state_reg_nextState_3_1 = 4'h0; // @[Replacement.scala:100:29]
wire [3:0] _state_reg_nextState_1_T_11 = 4'h0; // @[Replacement.scala:107:15]
wire [3:0] state_reg_nextState_5_2 = 4'h0; // @[Replacement.scala:100:29]
wire [3:0] _state_reg_nextState_2_T_17 = 4'h0; // @[Replacement.scala:107:15]
wire [3:0] _state_reg_wayDec_T_7 = 4'h8; // @[OneHot.scala:65:12]
wire [3:0] state_reg_wayDec_7 = 4'h8; // @[OneHot.scala:65:27]
wire io_hit = 1'h0; // @[NextLine.scala:109:7]
wire _state_reg_nextState_1_T_3 = 1'h0; // @[Replacement.scala:107:20]
wire _state_reg_nextState_2_T_3 = 1'h0; // @[Replacement.scala:107:20]
wire _state_reg_nextState_0_T_9 = 1'h0; // @[Replacement.scala:107:20]
wire _state_reg_nextState_2_T_9 = 1'h0; // @[Replacement.scala:107:20]
wire _state_reg_nextState_0_T_15 = 1'h0; // @[Replacement.scala:107:20]
wire _state_reg_nextState_1_T_15 = 1'h0; // @[Replacement.scala:107:20]
wire _state_reg_T_28 = 1'h0; // @[Replacement.scala:110:121]
wire _state_reg_nextState_0_T_21 = 1'h0; // @[Replacement.scala:107:20]
wire _state_reg_nextState_1_T_21 = 1'h0; // @[Replacement.scala:107:20]
wire _state_reg_nextState_2_T_21 = 1'h0; // @[Replacement.scala:107:20]
wire io_request_bits_write_0; // @[NextLine.scala:109:7]
wire [31:0] io_request_bits_address_0; // @[NextLine.scala:109:7]
wire io_request_valid_0; // @[NextLine.scala:109:7]
wire _any_hit_T = _singles_0_io_hit | _singles_1_io_hit; // @[NextLine.scala:17:53, :112:47]
wire _any_hit_T_1 = _any_hit_T | _singles_2_io_hit; // @[NextLine.scala:17:53, :112:47]
wire any_hit = _any_hit_T_1 | _singles_3_io_hit; // @[NextLine.scala:17:53, :112:47]
reg [5:0] state_reg; // @[Replacement.scala:85:34]
wire [3:0] _moreRecentVec_moreRecentVec_0_T_1; // @[Replacement.scala:93:30]
wire [3:0] _moreRecentVec_moreRecentVec_1_T_1; // @[Replacement.scala:93:30]
wire [3:0] _moreRecentVec_moreRecentVec_2_T_1; // @[Replacement.scala:93:30]
wire [3:0] moreRecentVec_0; // @[Replacement.scala:90:29]
wire [3:0] moreRecentVec_1; // @[Replacement.scala:90:29]
wire [3:0] moreRecentVec_2; // @[Replacement.scala:90:29]
wire [2:0] _moreRecentVec_moreRecentVec_0_T = state_reg[2:0]; // @[Replacement.scala:85:34, :93:36]
wire [2:0] _moreRecentVec_moreRecentVec_0_T_2 = state_reg[2:0]; // @[Replacement.scala:85:34, :93:36]
wire [2:0] _state_reg_moreRecentVec_moreRecentVec_0_T = state_reg[2:0]; // @[Replacement.scala:85:34, :93:36]
wire [2:0] _state_reg_moreRecentVec_moreRecentVec_0_T_2 = state_reg[2:0]; // @[Replacement.scala:85:34, :93:36]
wire [2:0] _moreRecentVec_moreRecentVec_0_T_4 = state_reg[2:0]; // @[Replacement.scala:85:34, :93:36]
wire [2:0] _moreRecentVec_moreRecentVec_0_T_6 = state_reg[2:0]; // @[Replacement.scala:85:34, :93:36]
wire [2:0] _state_reg_moreRecentVec_moreRecentVec_0_T_4 = state_reg[2:0]; // @[Replacement.scala:85:34, :93:36]
wire [2:0] _state_reg_moreRecentVec_moreRecentVec_0_T_6 = state_reg[2:0]; // @[Replacement.scala:85:34, :93:36]
wire [2:0] _moreRecentVec_moreRecentVec_0_T_8 = state_reg[2:0]; // @[Replacement.scala:85:34, :93:36]
wire [2:0] _moreRecentVec_moreRecentVec_0_T_10 = state_reg[2:0]; // @[Replacement.scala:85:34, :93:36]
wire [2:0] _state_reg_moreRecentVec_moreRecentVec_0_T_8 = state_reg[2:0]; // @[Replacement.scala:85:34, :93:36]
wire [2:0] _state_reg_moreRecentVec_moreRecentVec_0_T_10 = state_reg[2:0]; // @[Replacement.scala:85:34, :93:36]
wire [2:0] _moreRecentVec_moreRecentVec_0_T_12 = state_reg[2:0]; // @[Replacement.scala:85:34, :93:36]
wire [2:0] _moreRecentVec_moreRecentVec_0_T_14 = state_reg[2:0]; // @[Replacement.scala:85:34, :93:36]
wire [2:0] _state_reg_moreRecentVec_moreRecentVec_0_T_12 = state_reg[2:0]; // @[Replacement.scala:85:34, :93:36]
wire [2:0] _state_reg_moreRecentVec_moreRecentVec_0_T_14 = state_reg[2:0]; // @[Replacement.scala:85:34, :93:36]
assign _moreRecentVec_moreRecentVec_0_T_1 = {_moreRecentVec_moreRecentVec_0_T, 1'h0}; // @[Replacement.scala:93:{30,36}]
assign moreRecentVec_0 = _moreRecentVec_moreRecentVec_0_T_1; // @[Replacement.scala:90:29, :93:30]
wire [1:0] _moreRecentVec_moreRecentVec_1_T = state_reg[4:3]; // @[Replacement.scala:85:34, :93:36]
wire [1:0] _moreRecentVec_moreRecentVec_1_T_2 = state_reg[4:3]; // @[Replacement.scala:85:34, :93:36]
wire [1:0] _state_reg_moreRecentVec_moreRecentVec_1_T = state_reg[4:3]; // @[Replacement.scala:85:34, :93:36]
wire [1:0] _state_reg_moreRecentVec_moreRecentVec_1_T_2 = state_reg[4:3]; // @[Replacement.scala:85:34, :93:36]
wire [1:0] _moreRecentVec_moreRecentVec_1_T_4 = state_reg[4:3]; // @[Replacement.scala:85:34, :93:36]
wire [1:0] _moreRecentVec_moreRecentVec_1_T_6 = state_reg[4:3]; // @[Replacement.scala:85:34, :93:36]
wire [1:0] _state_reg_moreRecentVec_moreRecentVec_1_T_4 = state_reg[4:3]; // @[Replacement.scala:85:34, :93:36]
wire [1:0] _state_reg_moreRecentVec_moreRecentVec_1_T_6 = state_reg[4:3]; // @[Replacement.scala:85:34, :93:36]
wire [1:0] _moreRecentVec_moreRecentVec_1_T_8 = state_reg[4:3]; // @[Replacement.scala:85:34, :93:36]
wire [1:0] _moreRecentVec_moreRecentVec_1_T_10 = state_reg[4:3]; // @[Replacement.scala:85:34, :93:36]
wire [1:0] _state_reg_moreRecentVec_moreRecentVec_1_T_8 = state_reg[4:3]; // @[Replacement.scala:85:34, :93:36]
wire [1:0] _state_reg_moreRecentVec_moreRecentVec_1_T_10 = state_reg[4:3]; // @[Replacement.scala:85:34, :93:36]
wire [1:0] _moreRecentVec_moreRecentVec_1_T_12 = state_reg[4:3]; // @[Replacement.scala:85:34, :93:36]
wire [1:0] _moreRecentVec_moreRecentVec_1_T_14 = state_reg[4:3]; // @[Replacement.scala:85:34, :93:36]
wire [1:0] _state_reg_moreRecentVec_moreRecentVec_1_T_12 = state_reg[4:3]; // @[Replacement.scala:85:34, :93:36]
wire [1:0] _state_reg_moreRecentVec_moreRecentVec_1_T_14 = state_reg[4:3]; // @[Replacement.scala:85:34, :93:36]
assign _moreRecentVec_moreRecentVec_1_T_1 = {_moreRecentVec_moreRecentVec_1_T, 2'h0}; // @[Replacement.scala:93:{30,36}]
assign moreRecentVec_1 = _moreRecentVec_moreRecentVec_1_T_1; // @[Replacement.scala:90:29, :93:30]
wire _moreRecentVec_moreRecentVec_2_T = state_reg[5]; // @[Replacement.scala:85:34, :93:36]
wire _moreRecentVec_moreRecentVec_2_T_2 = state_reg[5]; // @[Replacement.scala:85:34, :93:36]
wire _state_reg_moreRecentVec_moreRecentVec_2_T = state_reg[5]; // @[Replacement.scala:85:34, :93:36]
wire _state_reg_moreRecentVec_moreRecentVec_2_T_2 = state_reg[5]; // @[Replacement.scala:85:34, :93:36]
wire _moreRecentVec_moreRecentVec_2_T_4 = state_reg[5]; // @[Replacement.scala:85:34, :93:36]
wire _moreRecentVec_moreRecentVec_2_T_6 = state_reg[5]; // @[Replacement.scala:85:34, :93:36]
wire _state_reg_moreRecentVec_moreRecentVec_2_T_4 = state_reg[5]; // @[Replacement.scala:85:34, :93:36]
wire _state_reg_moreRecentVec_moreRecentVec_2_T_6 = state_reg[5]; // @[Replacement.scala:85:34, :93:36]
wire _moreRecentVec_moreRecentVec_2_T_8 = state_reg[5]; // @[Replacement.scala:85:34, :93:36]
wire _moreRecentVec_moreRecentVec_2_T_10 = state_reg[5]; // @[Replacement.scala:85:34, :93:36]
wire _state_reg_moreRecentVec_moreRecentVec_2_T_8 = state_reg[5]; // @[Replacement.scala:85:34, :93:36]
wire _state_reg_moreRecentVec_moreRecentVec_2_T_10 = state_reg[5]; // @[Replacement.scala:85:34, :93:36]
wire _moreRecentVec_moreRecentVec_2_T_12 = state_reg[5]; // @[Replacement.scala:85:34, :93:36]
wire _moreRecentVec_moreRecentVec_2_T_14 = state_reg[5]; // @[Replacement.scala:85:34, :93:36]
wire _state_reg_moreRecentVec_moreRecentVec_2_T_12 = state_reg[5]; // @[Replacement.scala:85:34, :93:36]
wire _state_reg_moreRecentVec_moreRecentVec_2_T_14 = state_reg[5]; // @[Replacement.scala:85:34, :93:36]
assign _moreRecentVec_moreRecentVec_2_T_1 = {_moreRecentVec_moreRecentVec_2_T, 3'h0}; // @[Replacement.scala:93:{30,36}]
assign moreRecentVec_2 = _moreRecentVec_moreRecentVec_2_T_1; // @[Replacement.scala:90:29, :93:30]
wire [2:0] _mruWayDec_upperMoreRecent_T = moreRecentVec_0[3:1]; // @[Replacement.scala:90:29, :129:83]
wire mruWayDec_upperMoreRecent = &_mruWayDec_upperMoreRecent_T; // @[Replacement.scala:129:{83,98}]
wire mruWayDec_0 = mruWayDec_upperMoreRecent; // @[Replacement.scala:129:98, :131:23]
wire [1:0] _mruWayDec_upperMoreRecent_T_1 = moreRecentVec_1[3:2]; // @[Replacement.scala:90:29, :129:83]
wire mruWayDec_upperMoreRecent_1 = &_mruWayDec_upperMoreRecent_T_1; // @[Replacement.scala:129:{83,98}]
wire _mruWayDec_lowerMoreRecent_T = moreRecentVec_0[1]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_1 = ~_mruWayDec_lowerMoreRecent_T; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_2 = moreRecentVec_1[1]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_3 = ~_mruWayDec_lowerMoreRecent_T_2; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_4 = moreRecentVec_2[1]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_5 = ~_mruWayDec_lowerMoreRecent_T_4; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_6 = _mruWayDec_lowerMoreRecent_T_1 & _mruWayDec_lowerMoreRecent_T_3; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_lowerMoreRecent = _mruWayDec_lowerMoreRecent_T_6 & _mruWayDec_lowerMoreRecent_T_5; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_1 = mruWayDec_upperMoreRecent_1 & mruWayDec_lowerMoreRecent; // @[Replacement.scala:129:98, :130:100, :131:23]
wire _mruWayDec_upperMoreRecent_T_2 = moreRecentVec_2[3]; // @[Replacement.scala:90:29, :129:83]
wire _mruWayDec_lowerMoreRecent_T_18 = moreRecentVec_2[3]; // @[Replacement.scala:90:29, :129:83, :130:86]
wire mruWayDec_upperMoreRecent_2 = _mruWayDec_upperMoreRecent_T_2; // @[Replacement.scala:129:{83,98}]
wire _mruWayDec_lowerMoreRecent_T_7 = moreRecentVec_0[2]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_8 = ~_mruWayDec_lowerMoreRecent_T_7; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_9 = moreRecentVec_1[2]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_10 = ~_mruWayDec_lowerMoreRecent_T_9; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_11 = moreRecentVec_2[2]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_12 = ~_mruWayDec_lowerMoreRecent_T_11; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_13 = _mruWayDec_lowerMoreRecent_T_8 & _mruWayDec_lowerMoreRecent_T_10; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_lowerMoreRecent_1 = _mruWayDec_lowerMoreRecent_T_13 & _mruWayDec_lowerMoreRecent_T_12; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_2 = mruWayDec_upperMoreRecent_2 & mruWayDec_lowerMoreRecent_1; // @[Replacement.scala:129:98, :130:100, :131:23]
wire _mruWayDec_lowerMoreRecent_T_14 = moreRecentVec_0[3]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_15 = ~_mruWayDec_lowerMoreRecent_T_14; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_16 = moreRecentVec_1[3]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_17 = ~_mruWayDec_lowerMoreRecent_T_16; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_19 = ~_mruWayDec_lowerMoreRecent_T_18; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_20 = _mruWayDec_lowerMoreRecent_T_15 & _mruWayDec_lowerMoreRecent_T_17; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_lowerMoreRecent_2 = _mruWayDec_lowerMoreRecent_T_20 & _mruWayDec_lowerMoreRecent_T_19; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_3 = mruWayDec_lowerMoreRecent_2; // @[Replacement.scala:130:100, :131:23]
wire [1:0] lo = {mruWayDec_1, mruWayDec_0}; // @[OneHot.scala:21:45]
wire [1:0] lo_1 = lo; // @[OneHot.scala:21:45, :31:18]
wire [1:0] hi = {mruWayDec_3, mruWayDec_2}; // @[OneHot.scala:21:45]
wire [1:0] hi_1 = hi; // @[OneHot.scala:21:45, :30:18]
wire _T_8 = _singles_0_io_hit | ~any_hit & {hi_1, hi_1[1] | lo_1[1]} == 3'h0; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire [3:0] _moreRecentVec_moreRecentVec_0_T_3; // @[Replacement.scala:93:30]
wire [3:0] _moreRecentVec_moreRecentVec_1_T_3; // @[Replacement.scala:93:30]
wire [3:0] _moreRecentVec_moreRecentVec_2_T_3; // @[Replacement.scala:93:30]
wire [3:0] moreRecentVec_1_0; // @[Replacement.scala:90:29]
wire [3:0] moreRecentVec_1_1; // @[Replacement.scala:90:29]
wire [3:0] moreRecentVec_1_2; // @[Replacement.scala:90:29]
assign _moreRecentVec_moreRecentVec_0_T_3 = {_moreRecentVec_moreRecentVec_0_T_2, 1'h0}; // @[Replacement.scala:93:{30,36}]
assign moreRecentVec_1_0 = _moreRecentVec_moreRecentVec_0_T_3; // @[Replacement.scala:90:29, :93:30]
assign _moreRecentVec_moreRecentVec_1_T_3 = {_moreRecentVec_moreRecentVec_1_T_2, 2'h0}; // @[Replacement.scala:93:{30,36}]
assign moreRecentVec_1_1 = _moreRecentVec_moreRecentVec_1_T_3; // @[Replacement.scala:90:29, :93:30]
assign _moreRecentVec_moreRecentVec_2_T_3 = {_moreRecentVec_moreRecentVec_2_T_2, 3'h0}; // @[Replacement.scala:93:{30,36}]
assign moreRecentVec_1_2 = _moreRecentVec_moreRecentVec_2_T_3; // @[Replacement.scala:90:29, :93:30]
wire [2:0] _mruWayDec_upperMoreRecent_T_3 = moreRecentVec_1_0[3:1]; // @[Replacement.scala:90:29, :129:83]
wire mruWayDec_upperMoreRecent_3 = &_mruWayDec_upperMoreRecent_T_3; // @[Replacement.scala:129:{83,98}]
wire mruWayDec_0_1 = mruWayDec_upperMoreRecent_3; // @[Replacement.scala:129:98, :131:23]
wire [1:0] _mruWayDec_upperMoreRecent_T_4 = moreRecentVec_1_1[3:2]; // @[Replacement.scala:90:29, :129:83]
wire mruWayDec_upperMoreRecent_4 = &_mruWayDec_upperMoreRecent_T_4; // @[Replacement.scala:129:{83,98}]
wire _mruWayDec_lowerMoreRecent_T_21 = moreRecentVec_1_0[1]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_22 = ~_mruWayDec_lowerMoreRecent_T_21; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_23 = moreRecentVec_1_1[1]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_24 = ~_mruWayDec_lowerMoreRecent_T_23; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_25 = moreRecentVec_1_2[1]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_26 = ~_mruWayDec_lowerMoreRecent_T_25; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_27 = _mruWayDec_lowerMoreRecent_T_22 & _mruWayDec_lowerMoreRecent_T_24; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_lowerMoreRecent_3 = _mruWayDec_lowerMoreRecent_T_27 & _mruWayDec_lowerMoreRecent_T_26; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_1_1 = mruWayDec_upperMoreRecent_4 & mruWayDec_lowerMoreRecent_3; // @[Replacement.scala:129:98, :130:100, :131:23]
wire _mruWayDec_upperMoreRecent_T_5 = moreRecentVec_1_2[3]; // @[Replacement.scala:90:29, :129:83]
wire _mruWayDec_lowerMoreRecent_T_39 = moreRecentVec_1_2[3]; // @[Replacement.scala:90:29, :129:83, :130:86]
wire mruWayDec_upperMoreRecent_5 = _mruWayDec_upperMoreRecent_T_5; // @[Replacement.scala:129:{83,98}]
wire _mruWayDec_lowerMoreRecent_T_28 = moreRecentVec_1_0[2]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_29 = ~_mruWayDec_lowerMoreRecent_T_28; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_30 = moreRecentVec_1_1[2]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_31 = ~_mruWayDec_lowerMoreRecent_T_30; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_32 = moreRecentVec_1_2[2]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_33 = ~_mruWayDec_lowerMoreRecent_T_32; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_34 = _mruWayDec_lowerMoreRecent_T_29 & _mruWayDec_lowerMoreRecent_T_31; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_lowerMoreRecent_4 = _mruWayDec_lowerMoreRecent_T_34 & _mruWayDec_lowerMoreRecent_T_33; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_2_1 = mruWayDec_upperMoreRecent_5 & mruWayDec_lowerMoreRecent_4; // @[Replacement.scala:129:98, :130:100, :131:23]
wire _mruWayDec_lowerMoreRecent_T_35 = moreRecentVec_1_0[3]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_36 = ~_mruWayDec_lowerMoreRecent_T_35; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_37 = moreRecentVec_1_1[3]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_38 = ~_mruWayDec_lowerMoreRecent_T_37; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_40 = ~_mruWayDec_lowerMoreRecent_T_39; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_41 = _mruWayDec_lowerMoreRecent_T_36 & _mruWayDec_lowerMoreRecent_T_38; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_lowerMoreRecent_5 = _mruWayDec_lowerMoreRecent_T_41 & _mruWayDec_lowerMoreRecent_T_40; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_3_1 = mruWayDec_lowerMoreRecent_5; // @[Replacement.scala:130:100, :131:23]
wire [1:0] lo_2 = {mruWayDec_1_1, mruWayDec_0_1}; // @[OneHot.scala:21:45]
wire [1:0] lo_3 = lo_2; // @[OneHot.scala:21:45, :31:18]
wire [1:0] hi_2 = {mruWayDec_3_1, mruWayDec_2_1}; // @[OneHot.scala:21:45]
wire [1:0] hi_3 = hi_2; // @[OneHot.scala:21:45, :30:18]
wire _T_11 = hi_3[1] | lo_3[1]; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] state_reg_wayDec_shiftAmount = {|hi_3, _T_11}; // @[OneHot.scala:30:18, :32:{10,14,28}, :64:49]
wire [3:0] _state_reg_nextState_0_T_2; // @[Replacement.scala:107:15]
wire [3:0] _state_reg_nextState_1_T_2; // @[Replacement.scala:107:15]
wire [3:0] _state_reg_nextState_2_T_2; // @[Replacement.scala:107:15]
wire [3:0] state_reg_nextState_0; // @[Replacement.scala:100:29]
wire [3:0] state_reg_nextState_1; // @[Replacement.scala:100:29]
wire [3:0] state_reg_nextState_2; // @[Replacement.scala:100:29]
wire [3:0] _state_reg_moreRecentVec_moreRecentVec_0_T_1; // @[Replacement.scala:93:30]
wire [3:0] _state_reg_moreRecentVec_moreRecentVec_1_T_1; // @[Replacement.scala:93:30]
wire [3:0] _state_reg_moreRecentVec_moreRecentVec_2_T_1; // @[Replacement.scala:93:30]
wire [3:0] state_reg_moreRecentVec_0; // @[Replacement.scala:90:29]
wire [3:0] state_reg_moreRecentVec_1; // @[Replacement.scala:90:29]
wire [3:0] state_reg_moreRecentVec_2; // @[Replacement.scala:90:29]
assign _state_reg_moreRecentVec_moreRecentVec_0_T_1 = {_state_reg_moreRecentVec_moreRecentVec_0_T, 1'h0}; // @[Replacement.scala:93:{30,36}]
assign state_reg_moreRecentVec_0 = _state_reg_moreRecentVec_moreRecentVec_0_T_1; // @[Replacement.scala:90:29, :93:30]
assign _state_reg_moreRecentVec_moreRecentVec_1_T_1 = {_state_reg_moreRecentVec_moreRecentVec_1_T, 2'h0}; // @[Replacement.scala:93:{30,36}]
assign state_reg_moreRecentVec_1 = _state_reg_moreRecentVec_moreRecentVec_1_T_1; // @[Replacement.scala:90:29, :93:30]
assign _state_reg_moreRecentVec_moreRecentVec_2_T_1 = {_state_reg_moreRecentVec_moreRecentVec_2_T, 3'h0}; // @[Replacement.scala:93:{30,36}]
assign state_reg_moreRecentVec_2 = _state_reg_moreRecentVec_moreRecentVec_2_T_1; // @[Replacement.scala:90:29, :93:30]
wire [3:0] _state_reg_wayDec_T = 4'h1 << state_reg_wayDec_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [3:0] state_reg_wayDec = _state_reg_wayDec_T; // @[OneHot.scala:65:{12,27}]
wire _state_reg_nextState_0_T = {hi_3, _T_11} == 3'h0; // @[OneHot.scala:30:18, :32:{10,14,28}]
wire [3:0] _state_reg_nextState_0_T_1 = state_reg_moreRecentVec_0 | state_reg_wayDec; // @[OneHot.scala:65:27]
assign _state_reg_nextState_0_T_2 = _state_reg_nextState_0_T ? 4'h0 : _state_reg_nextState_0_T_1; // @[Replacement.scala:107:{15,20,67}]
assign state_reg_nextState_0 = _state_reg_nextState_0_T_2; // @[Replacement.scala:100:29, :107:15]
wire _state_reg_nextState_1_T = state_reg_wayDec_shiftAmount == 2'h1; // @[OneHot.scala:64:49]
wire [3:0] _state_reg_nextState_1_T_1 = state_reg_moreRecentVec_1 | state_reg_wayDec; // @[OneHot.scala:65:27]
assign _state_reg_nextState_1_T_2 = _state_reg_nextState_1_T ? 4'h0 : _state_reg_nextState_1_T_1; // @[Replacement.scala:107:{15,20,67}]
assign state_reg_nextState_1 = _state_reg_nextState_1_T_2; // @[Replacement.scala:100:29, :107:15]
wire _state_reg_nextState_2_T = state_reg_wayDec_shiftAmount == 2'h2; // @[OneHot.scala:64:49]
wire [3:0] _state_reg_nextState_2_T_1 = state_reg_moreRecentVec_2 | state_reg_wayDec; // @[OneHot.scala:65:27]
assign _state_reg_nextState_2_T_2 = _state_reg_nextState_2_T ? 4'h0 : _state_reg_nextState_2_T_1; // @[Replacement.scala:107:{15,20,67}]
assign state_reg_nextState_2 = _state_reg_nextState_2_T_2; // @[Replacement.scala:100:29, :107:15]
wire [2:0] _state_reg_T = state_reg_nextState_0[3:1]; // @[Replacement.scala:100:29, :110:63]
wire [1:0] _state_reg_T_1 = state_reg_nextState_1[3:2]; // @[Replacement.scala:100:29, :110:121]
wire [4:0] _state_reg_T_2 = {_state_reg_T_1, _state_reg_T}; // @[Replacement.scala:110:{63,112,121}]
wire _state_reg_T_3 = state_reg_nextState_2[3]; // @[Replacement.scala:100:29, :110:121]
wire [5:0] _state_reg_T_4 = {_state_reg_T_3, _state_reg_T_2}; // @[Replacement.scala:110:{112,121}]
wire [3:0] _state_reg_nextState_1_T_5; // @[Replacement.scala:107:15]
wire [3:0] _state_reg_nextState_2_T_5; // @[Replacement.scala:107:15]
wire [3:0] state_reg_nextState_1_1; // @[Replacement.scala:100:29]
wire [3:0] state_reg_nextState_1_2; // @[Replacement.scala:100:29]
wire [3:0] _state_reg_moreRecentVec_moreRecentVec_0_T_3; // @[Replacement.scala:93:30]
wire [3:0] _state_reg_moreRecentVec_moreRecentVec_1_T_3; // @[Replacement.scala:93:30]
wire [3:0] _state_reg_moreRecentVec_moreRecentVec_2_T_3; // @[Replacement.scala:93:30]
wire [3:0] state_reg_moreRecentVec_1_0; // @[Replacement.scala:90:29]
wire [3:0] state_reg_moreRecentVec_1_1; // @[Replacement.scala:90:29]
wire [3:0] state_reg_moreRecentVec_1_2; // @[Replacement.scala:90:29]
assign _state_reg_moreRecentVec_moreRecentVec_0_T_3 = {_state_reg_moreRecentVec_moreRecentVec_0_T_2, 1'h0}; // @[Replacement.scala:93:{30,36}]
assign state_reg_moreRecentVec_1_0 = _state_reg_moreRecentVec_moreRecentVec_0_T_3; // @[Replacement.scala:90:29, :93:30]
assign _state_reg_moreRecentVec_moreRecentVec_1_T_3 = {_state_reg_moreRecentVec_moreRecentVec_1_T_2, 2'h0}; // @[Replacement.scala:93:{30,36}]
assign state_reg_moreRecentVec_1_1 = _state_reg_moreRecentVec_moreRecentVec_1_T_3; // @[Replacement.scala:90:29, :93:30]
assign _state_reg_moreRecentVec_moreRecentVec_2_T_3 = {_state_reg_moreRecentVec_moreRecentVec_2_T_2, 3'h0}; // @[Replacement.scala:93:{30,36}]
assign state_reg_moreRecentVec_1_2 = _state_reg_moreRecentVec_moreRecentVec_2_T_3; // @[Replacement.scala:90:29, :93:30]
wire [3:0] _state_reg_nextState_0_T_4 = state_reg_moreRecentVec_1_0 | 4'h1; // @[OneHot.scala:65:12]
wire [3:0] _state_reg_nextState_1_T_4 = state_reg_moreRecentVec_1_1 | 4'h1; // @[OneHot.scala:65:12]
assign _state_reg_nextState_1_T_5 = _state_reg_nextState_1_T_4; // @[Replacement.scala:107:{15,67}]
assign state_reg_nextState_1_1 = _state_reg_nextState_1_T_5; // @[Replacement.scala:100:29, :107:15]
wire [3:0] _state_reg_nextState_2_T_4 = state_reg_moreRecentVec_1_2 | 4'h1; // @[OneHot.scala:65:12]
assign _state_reg_nextState_2_T_5 = _state_reg_nextState_2_T_4; // @[Replacement.scala:107:{15,67}]
assign state_reg_nextState_1_2 = _state_reg_nextState_2_T_5; // @[Replacement.scala:100:29, :107:15]
wire [1:0] _state_reg_T_6 = state_reg_nextState_1_1[3:2]; // @[Replacement.scala:100:29, :110:121]
wire [4:0] _state_reg_T_7 = {_state_reg_T_6, 3'h0}; // @[Replacement.scala:110:{112,121}]
wire _state_reg_T_8 = state_reg_nextState_1_2[3]; // @[Replacement.scala:100:29, :110:121]
wire [5:0] _state_reg_T_9 = {_state_reg_T_8, _state_reg_T_7}; // @[Replacement.scala:110:{112,121}]
wire [3:0] _moreRecentVec_moreRecentVec_0_T_5; // @[Replacement.scala:93:30]
wire [3:0] _moreRecentVec_moreRecentVec_1_T_5; // @[Replacement.scala:93:30]
wire [3:0] _moreRecentVec_moreRecentVec_2_T_5; // @[Replacement.scala:93:30]
wire [3:0] moreRecentVec_2_0; // @[Replacement.scala:90:29]
wire [3:0] moreRecentVec_2_1; // @[Replacement.scala:90:29]
wire [3:0] moreRecentVec_2_2; // @[Replacement.scala:90:29]
assign _moreRecentVec_moreRecentVec_0_T_5 = {_moreRecentVec_moreRecentVec_0_T_4, 1'h0}; // @[Replacement.scala:93:{30,36}]
assign moreRecentVec_2_0 = _moreRecentVec_moreRecentVec_0_T_5; // @[Replacement.scala:90:29, :93:30]
assign _moreRecentVec_moreRecentVec_1_T_5 = {_moreRecentVec_moreRecentVec_1_T_4, 2'h0}; // @[Replacement.scala:93:{30,36}]
assign moreRecentVec_2_1 = _moreRecentVec_moreRecentVec_1_T_5; // @[Replacement.scala:90:29, :93:30]
assign _moreRecentVec_moreRecentVec_2_T_5 = {_moreRecentVec_moreRecentVec_2_T_4, 3'h0}; // @[Replacement.scala:93:{30,36}]
assign moreRecentVec_2_2 = _moreRecentVec_moreRecentVec_2_T_5; // @[Replacement.scala:90:29, :93:30]
wire [2:0] _mruWayDec_upperMoreRecent_T_6 = moreRecentVec_2_0[3:1]; // @[Replacement.scala:90:29, :129:83]
wire mruWayDec_upperMoreRecent_6 = &_mruWayDec_upperMoreRecent_T_6; // @[Replacement.scala:129:{83,98}]
wire mruWayDec_0_2 = mruWayDec_upperMoreRecent_6; // @[Replacement.scala:129:98, :131:23]
wire [1:0] _mruWayDec_upperMoreRecent_T_7 = moreRecentVec_2_1[3:2]; // @[Replacement.scala:90:29, :129:83]
wire mruWayDec_upperMoreRecent_7 = &_mruWayDec_upperMoreRecent_T_7; // @[Replacement.scala:129:{83,98}]
wire _mruWayDec_lowerMoreRecent_T_42 = moreRecentVec_2_0[1]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_43 = ~_mruWayDec_lowerMoreRecent_T_42; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_44 = moreRecentVec_2_1[1]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_45 = ~_mruWayDec_lowerMoreRecent_T_44; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_46 = moreRecentVec_2_2[1]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_47 = ~_mruWayDec_lowerMoreRecent_T_46; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_48 = _mruWayDec_lowerMoreRecent_T_43 & _mruWayDec_lowerMoreRecent_T_45; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_lowerMoreRecent_6 = _mruWayDec_lowerMoreRecent_T_48 & _mruWayDec_lowerMoreRecent_T_47; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_1_2 = mruWayDec_upperMoreRecent_7 & mruWayDec_lowerMoreRecent_6; // @[Replacement.scala:129:98, :130:100, :131:23]
wire _mruWayDec_upperMoreRecent_T_8 = moreRecentVec_2_2[3]; // @[Replacement.scala:90:29, :129:83]
wire _mruWayDec_lowerMoreRecent_T_60 = moreRecentVec_2_2[3]; // @[Replacement.scala:90:29, :129:83, :130:86]
wire mruWayDec_upperMoreRecent_8 = _mruWayDec_upperMoreRecent_T_8; // @[Replacement.scala:129:{83,98}]
wire _mruWayDec_lowerMoreRecent_T_49 = moreRecentVec_2_0[2]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_50 = ~_mruWayDec_lowerMoreRecent_T_49; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_51 = moreRecentVec_2_1[2]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_52 = ~_mruWayDec_lowerMoreRecent_T_51; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_53 = moreRecentVec_2_2[2]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_54 = ~_mruWayDec_lowerMoreRecent_T_53; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_55 = _mruWayDec_lowerMoreRecent_T_50 & _mruWayDec_lowerMoreRecent_T_52; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_lowerMoreRecent_7 = _mruWayDec_lowerMoreRecent_T_55 & _mruWayDec_lowerMoreRecent_T_54; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_2_2 = mruWayDec_upperMoreRecent_8 & mruWayDec_lowerMoreRecent_7; // @[Replacement.scala:129:98, :130:100, :131:23]
wire _mruWayDec_lowerMoreRecent_T_56 = moreRecentVec_2_0[3]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_57 = ~_mruWayDec_lowerMoreRecent_T_56; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_58 = moreRecentVec_2_1[3]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_59 = ~_mruWayDec_lowerMoreRecent_T_58; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_61 = ~_mruWayDec_lowerMoreRecent_T_60; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_62 = _mruWayDec_lowerMoreRecent_T_57 & _mruWayDec_lowerMoreRecent_T_59; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_lowerMoreRecent_8 = _mruWayDec_lowerMoreRecent_T_62 & _mruWayDec_lowerMoreRecent_T_61; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_3_2 = mruWayDec_lowerMoreRecent_8; // @[Replacement.scala:130:100, :131:23]
wire [1:0] lo_4 = {mruWayDec_1_2, mruWayDec_0_2}; // @[OneHot.scala:21:45]
wire [1:0] lo_5 = lo_4; // @[OneHot.scala:21:45, :31:18]
wire [1:0] hi_4 = {mruWayDec_3_2, mruWayDec_2_2}; // @[OneHot.scala:21:45]
wire [1:0] hi_5 = hi_4; // @[OneHot.scala:21:45, :30:18]
wire _T_22 = _singles_1_io_hit | ~any_hit & {|hi_5, hi_5[1] | lo_5[1]} == 2'h1; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire [3:0] _moreRecentVec_moreRecentVec_0_T_7; // @[Replacement.scala:93:30]
wire [3:0] _moreRecentVec_moreRecentVec_1_T_7; // @[Replacement.scala:93:30]
wire [3:0] _moreRecentVec_moreRecentVec_2_T_7; // @[Replacement.scala:93:30]
wire [3:0] moreRecentVec_3_0; // @[Replacement.scala:90:29]
wire [3:0] moreRecentVec_3_1; // @[Replacement.scala:90:29]
wire [3:0] moreRecentVec_3_2; // @[Replacement.scala:90:29]
assign _moreRecentVec_moreRecentVec_0_T_7 = {_moreRecentVec_moreRecentVec_0_T_6, 1'h0}; // @[Replacement.scala:93:{30,36}]
assign moreRecentVec_3_0 = _moreRecentVec_moreRecentVec_0_T_7; // @[Replacement.scala:90:29, :93:30]
assign _moreRecentVec_moreRecentVec_1_T_7 = {_moreRecentVec_moreRecentVec_1_T_6, 2'h0}; // @[Replacement.scala:93:{30,36}]
assign moreRecentVec_3_1 = _moreRecentVec_moreRecentVec_1_T_7; // @[Replacement.scala:90:29, :93:30]
assign _moreRecentVec_moreRecentVec_2_T_7 = {_moreRecentVec_moreRecentVec_2_T_6, 3'h0}; // @[Replacement.scala:93:{30,36}]
assign moreRecentVec_3_2 = _moreRecentVec_moreRecentVec_2_T_7; // @[Replacement.scala:90:29, :93:30]
wire [2:0] _mruWayDec_upperMoreRecent_T_9 = moreRecentVec_3_0[3:1]; // @[Replacement.scala:90:29, :129:83]
wire mruWayDec_upperMoreRecent_9 = &_mruWayDec_upperMoreRecent_T_9; // @[Replacement.scala:129:{83,98}]
wire mruWayDec_0_3 = mruWayDec_upperMoreRecent_9; // @[Replacement.scala:129:98, :131:23]
wire [1:0] _mruWayDec_upperMoreRecent_T_10 = moreRecentVec_3_1[3:2]; // @[Replacement.scala:90:29, :129:83]
wire mruWayDec_upperMoreRecent_10 = &_mruWayDec_upperMoreRecent_T_10; // @[Replacement.scala:129:{83,98}]
wire _mruWayDec_lowerMoreRecent_T_63 = moreRecentVec_3_0[1]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_64 = ~_mruWayDec_lowerMoreRecent_T_63; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_65 = moreRecentVec_3_1[1]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_66 = ~_mruWayDec_lowerMoreRecent_T_65; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_67 = moreRecentVec_3_2[1]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_68 = ~_mruWayDec_lowerMoreRecent_T_67; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_69 = _mruWayDec_lowerMoreRecent_T_64 & _mruWayDec_lowerMoreRecent_T_66; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_lowerMoreRecent_9 = _mruWayDec_lowerMoreRecent_T_69 & _mruWayDec_lowerMoreRecent_T_68; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_1_3 = mruWayDec_upperMoreRecent_10 & mruWayDec_lowerMoreRecent_9; // @[Replacement.scala:129:98, :130:100, :131:23]
wire _mruWayDec_upperMoreRecent_T_11 = moreRecentVec_3_2[3]; // @[Replacement.scala:90:29, :129:83]
wire _mruWayDec_lowerMoreRecent_T_81 = moreRecentVec_3_2[3]; // @[Replacement.scala:90:29, :129:83, :130:86]
wire mruWayDec_upperMoreRecent_11 = _mruWayDec_upperMoreRecent_T_11; // @[Replacement.scala:129:{83,98}]
wire _mruWayDec_lowerMoreRecent_T_70 = moreRecentVec_3_0[2]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_71 = ~_mruWayDec_lowerMoreRecent_T_70; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_72 = moreRecentVec_3_1[2]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_73 = ~_mruWayDec_lowerMoreRecent_T_72; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_74 = moreRecentVec_3_2[2]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_75 = ~_mruWayDec_lowerMoreRecent_T_74; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_76 = _mruWayDec_lowerMoreRecent_T_71 & _mruWayDec_lowerMoreRecent_T_73; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_lowerMoreRecent_10 = _mruWayDec_lowerMoreRecent_T_76 & _mruWayDec_lowerMoreRecent_T_75; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_2_3 = mruWayDec_upperMoreRecent_11 & mruWayDec_lowerMoreRecent_10; // @[Replacement.scala:129:98, :130:100, :131:23]
wire _mruWayDec_lowerMoreRecent_T_77 = moreRecentVec_3_0[3]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_78 = ~_mruWayDec_lowerMoreRecent_T_77; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_79 = moreRecentVec_3_1[3]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_80 = ~_mruWayDec_lowerMoreRecent_T_79; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_82 = ~_mruWayDec_lowerMoreRecent_T_81; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_83 = _mruWayDec_lowerMoreRecent_T_78 & _mruWayDec_lowerMoreRecent_T_80; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_lowerMoreRecent_11 = _mruWayDec_lowerMoreRecent_T_83 & _mruWayDec_lowerMoreRecent_T_82; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_3_3 = mruWayDec_lowerMoreRecent_11; // @[Replacement.scala:130:100, :131:23]
wire [1:0] lo_6 = {mruWayDec_1_3, mruWayDec_0_3}; // @[OneHot.scala:21:45]
wire [1:0] lo_7 = lo_6; // @[OneHot.scala:21:45, :31:18]
wire [1:0] hi_6 = {mruWayDec_3_3, mruWayDec_2_3}; // @[OneHot.scala:21:45]
wire [1:0] hi_7 = hi_6; // @[OneHot.scala:21:45, :30:18]
wire _T_25 = hi_7[1] | lo_7[1]; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] state_reg_wayDec_shiftAmount_1 = {|hi_7, _T_25}; // @[OneHot.scala:30:18, :32:{10,14,28}, :64:49]
wire [3:0] _state_reg_nextState_0_T_8; // @[Replacement.scala:107:15]
wire [3:0] _state_reg_nextState_1_T_8; // @[Replacement.scala:107:15]
wire [3:0] _state_reg_nextState_2_T_8; // @[Replacement.scala:107:15]
wire [3:0] state_reg_nextState_2_0; // @[Replacement.scala:100:29]
wire [3:0] state_reg_nextState_2_1; // @[Replacement.scala:100:29]
wire [3:0] state_reg_nextState_2_2; // @[Replacement.scala:100:29]
wire [3:0] _state_reg_moreRecentVec_moreRecentVec_0_T_5; // @[Replacement.scala:93:30]
wire [3:0] _state_reg_moreRecentVec_moreRecentVec_1_T_5; // @[Replacement.scala:93:30]
wire [3:0] _state_reg_moreRecentVec_moreRecentVec_2_T_5; // @[Replacement.scala:93:30]
wire [3:0] state_reg_moreRecentVec_2_0; // @[Replacement.scala:90:29]
wire [3:0] state_reg_moreRecentVec_2_1; // @[Replacement.scala:90:29]
wire [3:0] state_reg_moreRecentVec_2_2; // @[Replacement.scala:90:29]
assign _state_reg_moreRecentVec_moreRecentVec_0_T_5 = {_state_reg_moreRecentVec_moreRecentVec_0_T_4, 1'h0}; // @[Replacement.scala:93:{30,36}]
assign state_reg_moreRecentVec_2_0 = _state_reg_moreRecentVec_moreRecentVec_0_T_5; // @[Replacement.scala:90:29, :93:30]
assign _state_reg_moreRecentVec_moreRecentVec_1_T_5 = {_state_reg_moreRecentVec_moreRecentVec_1_T_4, 2'h0}; // @[Replacement.scala:93:{30,36}]
assign state_reg_moreRecentVec_2_1 = _state_reg_moreRecentVec_moreRecentVec_1_T_5; // @[Replacement.scala:90:29, :93:30]
assign _state_reg_moreRecentVec_moreRecentVec_2_T_5 = {_state_reg_moreRecentVec_moreRecentVec_2_T_4, 3'h0}; // @[Replacement.scala:93:{30,36}]
assign state_reg_moreRecentVec_2_2 = _state_reg_moreRecentVec_moreRecentVec_2_T_5; // @[Replacement.scala:90:29, :93:30]
wire [3:0] _state_reg_wayDec_T_2 = 4'h1 << state_reg_wayDec_shiftAmount_1; // @[OneHot.scala:64:49, :65:12]
wire [3:0] state_reg_wayDec_2 = _state_reg_wayDec_T_2; // @[OneHot.scala:65:{12,27}]
wire _state_reg_nextState_0_T_6 = {hi_7, _T_25} == 3'h0; // @[OneHot.scala:30:18, :32:{10,14,28}]
wire [3:0] _state_reg_nextState_0_T_7 = state_reg_moreRecentVec_2_0 | state_reg_wayDec_2; // @[OneHot.scala:65:27]
assign _state_reg_nextState_0_T_8 = _state_reg_nextState_0_T_6 ? 4'h0 : _state_reg_nextState_0_T_7; // @[Replacement.scala:107:{15,20,67}]
assign state_reg_nextState_2_0 = _state_reg_nextState_0_T_8; // @[Replacement.scala:100:29, :107:15]
wire _state_reg_nextState_1_T_6 = state_reg_wayDec_shiftAmount_1 == 2'h1; // @[OneHot.scala:64:49]
wire [3:0] _state_reg_nextState_1_T_7 = state_reg_moreRecentVec_2_1 | state_reg_wayDec_2; // @[OneHot.scala:65:27]
assign _state_reg_nextState_1_T_8 = _state_reg_nextState_1_T_6 ? 4'h0 : _state_reg_nextState_1_T_7; // @[Replacement.scala:107:{15,20,67}]
assign state_reg_nextState_2_1 = _state_reg_nextState_1_T_8; // @[Replacement.scala:100:29, :107:15]
wire _state_reg_nextState_2_T_6 = state_reg_wayDec_shiftAmount_1 == 2'h2; // @[OneHot.scala:64:49]
wire [3:0] _state_reg_nextState_2_T_7 = state_reg_moreRecentVec_2_2 | state_reg_wayDec_2; // @[OneHot.scala:65:27]
assign _state_reg_nextState_2_T_8 = _state_reg_nextState_2_T_6 ? 4'h0 : _state_reg_nextState_2_T_7; // @[Replacement.scala:107:{15,20,67}]
assign state_reg_nextState_2_2 = _state_reg_nextState_2_T_8; // @[Replacement.scala:100:29, :107:15]
wire [2:0] _state_reg_T_10 = state_reg_nextState_2_0[3:1]; // @[Replacement.scala:100:29, :110:63]
wire [1:0] _state_reg_T_11 = state_reg_nextState_2_1[3:2]; // @[Replacement.scala:100:29, :110:121]
wire [4:0] _state_reg_T_12 = {_state_reg_T_11, _state_reg_T_10}; // @[Replacement.scala:110:{63,112,121}]
wire _state_reg_T_13 = state_reg_nextState_2_2[3]; // @[Replacement.scala:100:29, :110:121]
wire [5:0] _state_reg_T_14 = {_state_reg_T_13, _state_reg_T_12}; // @[Replacement.scala:110:{112,121}]
wire [3:0] _state_reg_nextState_0_T_11; // @[Replacement.scala:107:15]
wire [3:0] _state_reg_nextState_2_T_11; // @[Replacement.scala:107:15]
wire [3:0] state_reg_nextState_3_0; // @[Replacement.scala:100:29]
wire [3:0] state_reg_nextState_3_2; // @[Replacement.scala:100:29]
wire [3:0] _state_reg_moreRecentVec_moreRecentVec_0_T_7; // @[Replacement.scala:93:30]
wire [3:0] _state_reg_moreRecentVec_moreRecentVec_1_T_7; // @[Replacement.scala:93:30]
wire [3:0] _state_reg_moreRecentVec_moreRecentVec_2_T_7; // @[Replacement.scala:93:30]
wire [3:0] state_reg_moreRecentVec_3_0; // @[Replacement.scala:90:29]
wire [3:0] state_reg_moreRecentVec_3_1; // @[Replacement.scala:90:29]
wire [3:0] state_reg_moreRecentVec_3_2; // @[Replacement.scala:90:29]
assign _state_reg_moreRecentVec_moreRecentVec_0_T_7 = {_state_reg_moreRecentVec_moreRecentVec_0_T_6, 1'h0}; // @[Replacement.scala:93:{30,36}]
assign state_reg_moreRecentVec_3_0 = _state_reg_moreRecentVec_moreRecentVec_0_T_7; // @[Replacement.scala:90:29, :93:30]
assign _state_reg_moreRecentVec_moreRecentVec_1_T_7 = {_state_reg_moreRecentVec_moreRecentVec_1_T_6, 2'h0}; // @[Replacement.scala:93:{30,36}]
assign state_reg_moreRecentVec_3_1 = _state_reg_moreRecentVec_moreRecentVec_1_T_7; // @[Replacement.scala:90:29, :93:30]
assign _state_reg_moreRecentVec_moreRecentVec_2_T_7 = {_state_reg_moreRecentVec_moreRecentVec_2_T_6, 3'h0}; // @[Replacement.scala:93:{30,36}]
assign state_reg_moreRecentVec_3_2 = _state_reg_moreRecentVec_moreRecentVec_2_T_7; // @[Replacement.scala:90:29, :93:30]
wire [3:0] _state_reg_nextState_0_T_10 = state_reg_moreRecentVec_3_0 | 4'h2; // @[Replacement.scala:90:29, :107:67]
assign _state_reg_nextState_0_T_11 = _state_reg_nextState_0_T_10; // @[Replacement.scala:107:{15,67}]
assign state_reg_nextState_3_0 = _state_reg_nextState_0_T_11; // @[Replacement.scala:100:29, :107:15]
wire [3:0] _state_reg_nextState_1_T_10 = state_reg_moreRecentVec_3_1 | 4'h2; // @[Replacement.scala:90:29, :107:67]
wire [3:0] _state_reg_nextState_2_T_10 = state_reg_moreRecentVec_3_2 | 4'h2; // @[Replacement.scala:90:29, :107:67]
assign _state_reg_nextState_2_T_11 = _state_reg_nextState_2_T_10; // @[Replacement.scala:107:{15,67}]
assign state_reg_nextState_3_2 = _state_reg_nextState_2_T_11; // @[Replacement.scala:100:29, :107:15]
wire [2:0] _state_reg_T_15 = state_reg_nextState_3_0[3:1]; // @[Replacement.scala:100:29, :110:63]
wire [4:0] _state_reg_T_17 = {2'h0, _state_reg_T_15}; // @[Replacement.scala:110:{63,112}]
wire _state_reg_T_18 = state_reg_nextState_3_2[3]; // @[Replacement.scala:100:29, :110:121]
wire [5:0] _state_reg_T_19 = {_state_reg_T_18, _state_reg_T_17}; // @[Replacement.scala:110:{112,121}]
wire [3:0] _moreRecentVec_moreRecentVec_0_T_9; // @[Replacement.scala:93:30]
wire [3:0] _moreRecentVec_moreRecentVec_1_T_9; // @[Replacement.scala:93:30]
wire [3:0] _moreRecentVec_moreRecentVec_2_T_9; // @[Replacement.scala:93:30]
wire [3:0] moreRecentVec_4_0; // @[Replacement.scala:90:29]
wire [3:0] moreRecentVec_4_1; // @[Replacement.scala:90:29]
wire [3:0] moreRecentVec_4_2; // @[Replacement.scala:90:29]
assign _moreRecentVec_moreRecentVec_0_T_9 = {_moreRecentVec_moreRecentVec_0_T_8, 1'h0}; // @[Replacement.scala:93:{30,36}]
assign moreRecentVec_4_0 = _moreRecentVec_moreRecentVec_0_T_9; // @[Replacement.scala:90:29, :93:30]
assign _moreRecentVec_moreRecentVec_1_T_9 = {_moreRecentVec_moreRecentVec_1_T_8, 2'h0}; // @[Replacement.scala:93:{30,36}]
assign moreRecentVec_4_1 = _moreRecentVec_moreRecentVec_1_T_9; // @[Replacement.scala:90:29, :93:30]
assign _moreRecentVec_moreRecentVec_2_T_9 = {_moreRecentVec_moreRecentVec_2_T_8, 3'h0}; // @[Replacement.scala:93:{30,36}]
assign moreRecentVec_4_2 = _moreRecentVec_moreRecentVec_2_T_9; // @[Replacement.scala:90:29, :93:30]
wire [2:0] _mruWayDec_upperMoreRecent_T_12 = moreRecentVec_4_0[3:1]; // @[Replacement.scala:90:29, :129:83]
wire mruWayDec_upperMoreRecent_12 = &_mruWayDec_upperMoreRecent_T_12; // @[Replacement.scala:129:{83,98}]
wire mruWayDec_0_4 = mruWayDec_upperMoreRecent_12; // @[Replacement.scala:129:98, :131:23]
wire [1:0] _mruWayDec_upperMoreRecent_T_13 = moreRecentVec_4_1[3:2]; // @[Replacement.scala:90:29, :129:83]
wire mruWayDec_upperMoreRecent_13 = &_mruWayDec_upperMoreRecent_T_13; // @[Replacement.scala:129:{83,98}]
wire _mruWayDec_lowerMoreRecent_T_84 = moreRecentVec_4_0[1]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_85 = ~_mruWayDec_lowerMoreRecent_T_84; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_86 = moreRecentVec_4_1[1]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_87 = ~_mruWayDec_lowerMoreRecent_T_86; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_88 = moreRecentVec_4_2[1]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_89 = ~_mruWayDec_lowerMoreRecent_T_88; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_90 = _mruWayDec_lowerMoreRecent_T_85 & _mruWayDec_lowerMoreRecent_T_87; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_lowerMoreRecent_12 = _mruWayDec_lowerMoreRecent_T_90 & _mruWayDec_lowerMoreRecent_T_89; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_1_4 = mruWayDec_upperMoreRecent_13 & mruWayDec_lowerMoreRecent_12; // @[Replacement.scala:129:98, :130:100, :131:23]
wire _mruWayDec_upperMoreRecent_T_14 = moreRecentVec_4_2[3]; // @[Replacement.scala:90:29, :129:83]
wire _mruWayDec_lowerMoreRecent_T_102 = moreRecentVec_4_2[3]; // @[Replacement.scala:90:29, :129:83, :130:86]
wire mruWayDec_upperMoreRecent_14 = _mruWayDec_upperMoreRecent_T_14; // @[Replacement.scala:129:{83,98}]
wire _mruWayDec_lowerMoreRecent_T_91 = moreRecentVec_4_0[2]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_92 = ~_mruWayDec_lowerMoreRecent_T_91; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_93 = moreRecentVec_4_1[2]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_94 = ~_mruWayDec_lowerMoreRecent_T_93; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_95 = moreRecentVec_4_2[2]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_96 = ~_mruWayDec_lowerMoreRecent_T_95; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_97 = _mruWayDec_lowerMoreRecent_T_92 & _mruWayDec_lowerMoreRecent_T_94; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_lowerMoreRecent_13 = _mruWayDec_lowerMoreRecent_T_97 & _mruWayDec_lowerMoreRecent_T_96; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_2_4 = mruWayDec_upperMoreRecent_14 & mruWayDec_lowerMoreRecent_13; // @[Replacement.scala:129:98, :130:100, :131:23]
wire _mruWayDec_lowerMoreRecent_T_98 = moreRecentVec_4_0[3]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_99 = ~_mruWayDec_lowerMoreRecent_T_98; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_100 = moreRecentVec_4_1[3]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_101 = ~_mruWayDec_lowerMoreRecent_T_100; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_103 = ~_mruWayDec_lowerMoreRecent_T_102; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_104 = _mruWayDec_lowerMoreRecent_T_99 & _mruWayDec_lowerMoreRecent_T_101; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_lowerMoreRecent_14 = _mruWayDec_lowerMoreRecent_T_104 & _mruWayDec_lowerMoreRecent_T_103; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_3_4 = mruWayDec_lowerMoreRecent_14; // @[Replacement.scala:130:100, :131:23]
wire [1:0] lo_8 = {mruWayDec_1_4, mruWayDec_0_4}; // @[OneHot.scala:21:45]
wire [1:0] lo_9 = lo_8; // @[OneHot.scala:21:45, :31:18]
wire [1:0] hi_8 = {mruWayDec_3_4, mruWayDec_2_4}; // @[OneHot.scala:21:45]
wire [1:0] hi_9 = hi_8; // @[OneHot.scala:21:45, :30:18]
wire _T_36 = _singles_2_io_hit | ~any_hit & {|hi_9, hi_9[1] | lo_9[1]} == 2'h2; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire [3:0] _moreRecentVec_moreRecentVec_0_T_11; // @[Replacement.scala:93:30]
wire [3:0] _moreRecentVec_moreRecentVec_1_T_11; // @[Replacement.scala:93:30]
wire [3:0] _moreRecentVec_moreRecentVec_2_T_11; // @[Replacement.scala:93:30]
wire [3:0] moreRecentVec_5_0; // @[Replacement.scala:90:29]
wire [3:0] moreRecentVec_5_1; // @[Replacement.scala:90:29]
wire [3:0] moreRecentVec_5_2; // @[Replacement.scala:90:29]
assign _moreRecentVec_moreRecentVec_0_T_11 = {_moreRecentVec_moreRecentVec_0_T_10, 1'h0}; // @[Replacement.scala:93:{30,36}]
assign moreRecentVec_5_0 = _moreRecentVec_moreRecentVec_0_T_11; // @[Replacement.scala:90:29, :93:30]
assign _moreRecentVec_moreRecentVec_1_T_11 = {_moreRecentVec_moreRecentVec_1_T_10, 2'h0}; // @[Replacement.scala:93:{30,36}]
assign moreRecentVec_5_1 = _moreRecentVec_moreRecentVec_1_T_11; // @[Replacement.scala:90:29, :93:30]
assign _moreRecentVec_moreRecentVec_2_T_11 = {_moreRecentVec_moreRecentVec_2_T_10, 3'h0}; // @[Replacement.scala:93:{30,36}]
assign moreRecentVec_5_2 = _moreRecentVec_moreRecentVec_2_T_11; // @[Replacement.scala:90:29, :93:30]
wire [2:0] _mruWayDec_upperMoreRecent_T_15 = moreRecentVec_5_0[3:1]; // @[Replacement.scala:90:29, :129:83]
wire mruWayDec_upperMoreRecent_15 = &_mruWayDec_upperMoreRecent_T_15; // @[Replacement.scala:129:{83,98}]
wire mruWayDec_0_5 = mruWayDec_upperMoreRecent_15; // @[Replacement.scala:129:98, :131:23]
wire [1:0] _mruWayDec_upperMoreRecent_T_16 = moreRecentVec_5_1[3:2]; // @[Replacement.scala:90:29, :129:83]
wire mruWayDec_upperMoreRecent_16 = &_mruWayDec_upperMoreRecent_T_16; // @[Replacement.scala:129:{83,98}]
wire _mruWayDec_lowerMoreRecent_T_105 = moreRecentVec_5_0[1]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_106 = ~_mruWayDec_lowerMoreRecent_T_105; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_107 = moreRecentVec_5_1[1]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_108 = ~_mruWayDec_lowerMoreRecent_T_107; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_109 = moreRecentVec_5_2[1]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_110 = ~_mruWayDec_lowerMoreRecent_T_109; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_111 = _mruWayDec_lowerMoreRecent_T_106 & _mruWayDec_lowerMoreRecent_T_108; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_lowerMoreRecent_15 = _mruWayDec_lowerMoreRecent_T_111 & _mruWayDec_lowerMoreRecent_T_110; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_1_5 = mruWayDec_upperMoreRecent_16 & mruWayDec_lowerMoreRecent_15; // @[Replacement.scala:129:98, :130:100, :131:23]
wire _mruWayDec_upperMoreRecent_T_17 = moreRecentVec_5_2[3]; // @[Replacement.scala:90:29, :129:83]
wire _mruWayDec_lowerMoreRecent_T_123 = moreRecentVec_5_2[3]; // @[Replacement.scala:90:29, :129:83, :130:86]
wire mruWayDec_upperMoreRecent_17 = _mruWayDec_upperMoreRecent_T_17; // @[Replacement.scala:129:{83,98}]
wire _mruWayDec_lowerMoreRecent_T_112 = moreRecentVec_5_0[2]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_113 = ~_mruWayDec_lowerMoreRecent_T_112; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_114 = moreRecentVec_5_1[2]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_115 = ~_mruWayDec_lowerMoreRecent_T_114; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_116 = moreRecentVec_5_2[2]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_117 = ~_mruWayDec_lowerMoreRecent_T_116; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_118 = _mruWayDec_lowerMoreRecent_T_113 & _mruWayDec_lowerMoreRecent_T_115; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_lowerMoreRecent_16 = _mruWayDec_lowerMoreRecent_T_118 & _mruWayDec_lowerMoreRecent_T_117; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_2_5 = mruWayDec_upperMoreRecent_17 & mruWayDec_lowerMoreRecent_16; // @[Replacement.scala:129:98, :130:100, :131:23]
wire _mruWayDec_lowerMoreRecent_T_119 = moreRecentVec_5_0[3]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_120 = ~_mruWayDec_lowerMoreRecent_T_119; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_121 = moreRecentVec_5_1[3]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_122 = ~_mruWayDec_lowerMoreRecent_T_121; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_124 = ~_mruWayDec_lowerMoreRecent_T_123; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_125 = _mruWayDec_lowerMoreRecent_T_120 & _mruWayDec_lowerMoreRecent_T_122; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_lowerMoreRecent_17 = _mruWayDec_lowerMoreRecent_T_125 & _mruWayDec_lowerMoreRecent_T_124; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_3_5 = mruWayDec_lowerMoreRecent_17; // @[Replacement.scala:130:100, :131:23]
wire [1:0] lo_10 = {mruWayDec_1_5, mruWayDec_0_5}; // @[OneHot.scala:21:45]
wire [1:0] lo_11 = lo_10; // @[OneHot.scala:21:45, :31:18]
wire [1:0] hi_10 = {mruWayDec_3_5, mruWayDec_2_5}; // @[OneHot.scala:21:45]
wire [1:0] hi_11 = hi_10; // @[OneHot.scala:21:45, :30:18]
wire _T_39 = hi_11[1] | lo_11[1]; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] state_reg_wayDec_shiftAmount_2 = {|hi_11, _T_39}; // @[OneHot.scala:30:18, :32:{10,14,28}, :64:49]
wire [3:0] _state_reg_nextState_0_T_14; // @[Replacement.scala:107:15]
wire [3:0] _state_reg_nextState_1_T_14; // @[Replacement.scala:107:15]
wire [3:0] _state_reg_nextState_2_T_14; // @[Replacement.scala:107:15]
wire [3:0] state_reg_nextState_4_0; // @[Replacement.scala:100:29]
wire [3:0] state_reg_nextState_4_1; // @[Replacement.scala:100:29]
wire [3:0] state_reg_nextState_4_2; // @[Replacement.scala:100:29]
wire [3:0] _state_reg_moreRecentVec_moreRecentVec_0_T_9; // @[Replacement.scala:93:30]
wire [3:0] _state_reg_moreRecentVec_moreRecentVec_1_T_9; // @[Replacement.scala:93:30]
wire [3:0] _state_reg_moreRecentVec_moreRecentVec_2_T_9; // @[Replacement.scala:93:30]
wire [3:0] state_reg_moreRecentVec_4_0; // @[Replacement.scala:90:29]
wire [3:0] state_reg_moreRecentVec_4_1; // @[Replacement.scala:90:29]
wire [3:0] state_reg_moreRecentVec_4_2; // @[Replacement.scala:90:29]
assign _state_reg_moreRecentVec_moreRecentVec_0_T_9 = {_state_reg_moreRecentVec_moreRecentVec_0_T_8, 1'h0}; // @[Replacement.scala:93:{30,36}]
assign state_reg_moreRecentVec_4_0 = _state_reg_moreRecentVec_moreRecentVec_0_T_9; // @[Replacement.scala:90:29, :93:30]
assign _state_reg_moreRecentVec_moreRecentVec_1_T_9 = {_state_reg_moreRecentVec_moreRecentVec_1_T_8, 2'h0}; // @[Replacement.scala:93:{30,36}]
assign state_reg_moreRecentVec_4_1 = _state_reg_moreRecentVec_moreRecentVec_1_T_9; // @[Replacement.scala:90:29, :93:30]
assign _state_reg_moreRecentVec_moreRecentVec_2_T_9 = {_state_reg_moreRecentVec_moreRecentVec_2_T_8, 3'h0}; // @[Replacement.scala:93:{30,36}]
assign state_reg_moreRecentVec_4_2 = _state_reg_moreRecentVec_moreRecentVec_2_T_9; // @[Replacement.scala:90:29, :93:30]
wire [3:0] _state_reg_wayDec_T_4 = 4'h1 << state_reg_wayDec_shiftAmount_2; // @[OneHot.scala:64:49, :65:12]
wire [3:0] state_reg_wayDec_4 = _state_reg_wayDec_T_4; // @[OneHot.scala:65:{12,27}]
wire _state_reg_nextState_0_T_12 = {hi_11, _T_39} == 3'h0; // @[OneHot.scala:30:18, :32:{10,14,28}]
wire [3:0] _state_reg_nextState_0_T_13 = state_reg_moreRecentVec_4_0 | state_reg_wayDec_4; // @[OneHot.scala:65:27]
assign _state_reg_nextState_0_T_14 = _state_reg_nextState_0_T_12 ? 4'h0 : _state_reg_nextState_0_T_13; // @[Replacement.scala:107:{15,20,67}]
assign state_reg_nextState_4_0 = _state_reg_nextState_0_T_14; // @[Replacement.scala:100:29, :107:15]
wire _state_reg_nextState_1_T_12 = state_reg_wayDec_shiftAmount_2 == 2'h1; // @[OneHot.scala:64:49]
wire [3:0] _state_reg_nextState_1_T_13 = state_reg_moreRecentVec_4_1 | state_reg_wayDec_4; // @[OneHot.scala:65:27]
assign _state_reg_nextState_1_T_14 = _state_reg_nextState_1_T_12 ? 4'h0 : _state_reg_nextState_1_T_13; // @[Replacement.scala:107:{15,20,67}]
assign state_reg_nextState_4_1 = _state_reg_nextState_1_T_14; // @[Replacement.scala:100:29, :107:15]
wire _state_reg_nextState_2_T_12 = state_reg_wayDec_shiftAmount_2 == 2'h2; // @[OneHot.scala:64:49]
wire [3:0] _state_reg_nextState_2_T_13 = state_reg_moreRecentVec_4_2 | state_reg_wayDec_4; // @[OneHot.scala:65:27]
assign _state_reg_nextState_2_T_14 = _state_reg_nextState_2_T_12 ? 4'h0 : _state_reg_nextState_2_T_13; // @[Replacement.scala:107:{15,20,67}]
assign state_reg_nextState_4_2 = _state_reg_nextState_2_T_14; // @[Replacement.scala:100:29, :107:15]
wire [2:0] _state_reg_T_20 = state_reg_nextState_4_0[3:1]; // @[Replacement.scala:100:29, :110:63]
wire [1:0] _state_reg_T_21 = state_reg_nextState_4_1[3:2]; // @[Replacement.scala:100:29, :110:121]
wire [4:0] _state_reg_T_22 = {_state_reg_T_21, _state_reg_T_20}; // @[Replacement.scala:110:{63,112,121}]
wire _state_reg_T_23 = state_reg_nextState_4_2[3]; // @[Replacement.scala:100:29, :110:121]
wire [5:0] _state_reg_T_24 = {_state_reg_T_23, _state_reg_T_22}; // @[Replacement.scala:110:{112,121}]
wire [3:0] _state_reg_nextState_0_T_17; // @[Replacement.scala:107:15]
wire [3:0] _state_reg_nextState_1_T_17; // @[Replacement.scala:107:15]
wire [3:0] state_reg_nextState_5_0; // @[Replacement.scala:100:29]
wire [3:0] state_reg_nextState_5_1; // @[Replacement.scala:100:29]
wire [3:0] _state_reg_moreRecentVec_moreRecentVec_0_T_11; // @[Replacement.scala:93:30]
wire [3:0] _state_reg_moreRecentVec_moreRecentVec_1_T_11; // @[Replacement.scala:93:30]
wire [3:0] _state_reg_moreRecentVec_moreRecentVec_2_T_11; // @[Replacement.scala:93:30]
wire [3:0] state_reg_moreRecentVec_5_0; // @[Replacement.scala:90:29]
wire [3:0] state_reg_moreRecentVec_5_1; // @[Replacement.scala:90:29]
wire [3:0] state_reg_moreRecentVec_5_2; // @[Replacement.scala:90:29]
assign _state_reg_moreRecentVec_moreRecentVec_0_T_11 = {_state_reg_moreRecentVec_moreRecentVec_0_T_10, 1'h0}; // @[Replacement.scala:93:{30,36}]
assign state_reg_moreRecentVec_5_0 = _state_reg_moreRecentVec_moreRecentVec_0_T_11; // @[Replacement.scala:90:29, :93:30]
assign _state_reg_moreRecentVec_moreRecentVec_1_T_11 = {_state_reg_moreRecentVec_moreRecentVec_1_T_10, 2'h0}; // @[Replacement.scala:93:{30,36}]
assign state_reg_moreRecentVec_5_1 = _state_reg_moreRecentVec_moreRecentVec_1_T_11; // @[Replacement.scala:90:29, :93:30]
assign _state_reg_moreRecentVec_moreRecentVec_2_T_11 = {_state_reg_moreRecentVec_moreRecentVec_2_T_10, 3'h0}; // @[Replacement.scala:93:{30,36}]
assign state_reg_moreRecentVec_5_2 = _state_reg_moreRecentVec_moreRecentVec_2_T_11; // @[Replacement.scala:90:29, :93:30]
wire [3:0] _state_reg_nextState_0_T_16 = state_reg_moreRecentVec_5_0 | 4'h4; // @[Replacement.scala:90:29, :107:67]
assign _state_reg_nextState_0_T_17 = _state_reg_nextState_0_T_16; // @[Replacement.scala:107:{15,67}]
assign state_reg_nextState_5_0 = _state_reg_nextState_0_T_17; // @[Replacement.scala:100:29, :107:15]
wire [3:0] _state_reg_nextState_1_T_16 = state_reg_moreRecentVec_5_1 | 4'h4; // @[Replacement.scala:90:29, :107:67]
assign _state_reg_nextState_1_T_17 = _state_reg_nextState_1_T_16; // @[Replacement.scala:107:{15,67}]
assign state_reg_nextState_5_1 = _state_reg_nextState_1_T_17; // @[Replacement.scala:100:29, :107:15]
wire [3:0] _state_reg_nextState_2_T_16 = state_reg_moreRecentVec_5_2 | 4'h4; // @[Replacement.scala:90:29, :107:67]
wire [2:0] _state_reg_T_25 = state_reg_nextState_5_0[3:1]; // @[Replacement.scala:100:29, :110:63]
wire [1:0] _state_reg_T_26 = state_reg_nextState_5_1[3:2]; // @[Replacement.scala:100:29, :110:121]
wire [4:0] _state_reg_T_27 = {_state_reg_T_26, _state_reg_T_25}; // @[Replacement.scala:110:{63,112,121}]
wire [5:0] _state_reg_T_29 = {1'h0, _state_reg_T_27}; // @[Replacement.scala:110:112]
wire [3:0] _moreRecentVec_moreRecentVec_0_T_13; // @[Replacement.scala:93:30]
wire [3:0] _moreRecentVec_moreRecentVec_1_T_13; // @[Replacement.scala:93:30]
wire [3:0] _moreRecentVec_moreRecentVec_2_T_13; // @[Replacement.scala:93:30]
wire [3:0] moreRecentVec_6_0; // @[Replacement.scala:90:29]
wire [3:0] moreRecentVec_6_1; // @[Replacement.scala:90:29]
wire [3:0] moreRecentVec_6_2; // @[Replacement.scala:90:29]
assign _moreRecentVec_moreRecentVec_0_T_13 = {_moreRecentVec_moreRecentVec_0_T_12, 1'h0}; // @[Replacement.scala:93:{30,36}]
assign moreRecentVec_6_0 = _moreRecentVec_moreRecentVec_0_T_13; // @[Replacement.scala:90:29, :93:30]
assign _moreRecentVec_moreRecentVec_1_T_13 = {_moreRecentVec_moreRecentVec_1_T_12, 2'h0}; // @[Replacement.scala:93:{30,36}]
assign moreRecentVec_6_1 = _moreRecentVec_moreRecentVec_1_T_13; // @[Replacement.scala:90:29, :93:30]
assign _moreRecentVec_moreRecentVec_2_T_13 = {_moreRecentVec_moreRecentVec_2_T_12, 3'h0}; // @[Replacement.scala:93:{30,36}]
assign moreRecentVec_6_2 = _moreRecentVec_moreRecentVec_2_T_13; // @[Replacement.scala:90:29, :93:30]
wire [2:0] _mruWayDec_upperMoreRecent_T_18 = moreRecentVec_6_0[3:1]; // @[Replacement.scala:90:29, :129:83]
wire mruWayDec_upperMoreRecent_18 = &_mruWayDec_upperMoreRecent_T_18; // @[Replacement.scala:129:{83,98}]
wire mruWayDec_0_6 = mruWayDec_upperMoreRecent_18; // @[Replacement.scala:129:98, :131:23]
wire [1:0] _mruWayDec_upperMoreRecent_T_19 = moreRecentVec_6_1[3:2]; // @[Replacement.scala:90:29, :129:83]
wire mruWayDec_upperMoreRecent_19 = &_mruWayDec_upperMoreRecent_T_19; // @[Replacement.scala:129:{83,98}]
wire _mruWayDec_lowerMoreRecent_T_126 = moreRecentVec_6_0[1]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_127 = ~_mruWayDec_lowerMoreRecent_T_126; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_128 = moreRecentVec_6_1[1]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_129 = ~_mruWayDec_lowerMoreRecent_T_128; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_130 = moreRecentVec_6_2[1]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_131 = ~_mruWayDec_lowerMoreRecent_T_130; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_132 = _mruWayDec_lowerMoreRecent_T_127 & _mruWayDec_lowerMoreRecent_T_129; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_lowerMoreRecent_18 = _mruWayDec_lowerMoreRecent_T_132 & _mruWayDec_lowerMoreRecent_T_131; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_1_6 = mruWayDec_upperMoreRecent_19 & mruWayDec_lowerMoreRecent_18; // @[Replacement.scala:129:98, :130:100, :131:23]
wire _mruWayDec_upperMoreRecent_T_20 = moreRecentVec_6_2[3]; // @[Replacement.scala:90:29, :129:83]
wire _mruWayDec_lowerMoreRecent_T_144 = moreRecentVec_6_2[3]; // @[Replacement.scala:90:29, :129:83, :130:86]
wire mruWayDec_upperMoreRecent_20 = _mruWayDec_upperMoreRecent_T_20; // @[Replacement.scala:129:{83,98}]
wire _mruWayDec_lowerMoreRecent_T_133 = moreRecentVec_6_0[2]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_134 = ~_mruWayDec_lowerMoreRecent_T_133; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_135 = moreRecentVec_6_1[2]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_136 = ~_mruWayDec_lowerMoreRecent_T_135; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_137 = moreRecentVec_6_2[2]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_138 = ~_mruWayDec_lowerMoreRecent_T_137; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_139 = _mruWayDec_lowerMoreRecent_T_134 & _mruWayDec_lowerMoreRecent_T_136; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_lowerMoreRecent_19 = _mruWayDec_lowerMoreRecent_T_139 & _mruWayDec_lowerMoreRecent_T_138; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_2_6 = mruWayDec_upperMoreRecent_20 & mruWayDec_lowerMoreRecent_19; // @[Replacement.scala:129:98, :130:100, :131:23]
wire _mruWayDec_lowerMoreRecent_T_140 = moreRecentVec_6_0[3]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_141 = ~_mruWayDec_lowerMoreRecent_T_140; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_142 = moreRecentVec_6_1[3]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_143 = ~_mruWayDec_lowerMoreRecent_T_142; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_145 = ~_mruWayDec_lowerMoreRecent_T_144; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_146 = _mruWayDec_lowerMoreRecent_T_141 & _mruWayDec_lowerMoreRecent_T_143; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_lowerMoreRecent_20 = _mruWayDec_lowerMoreRecent_T_146 & _mruWayDec_lowerMoreRecent_T_145; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_3_6 = mruWayDec_lowerMoreRecent_20; // @[Replacement.scala:130:100, :131:23]
wire [1:0] lo_12 = {mruWayDec_1_6, mruWayDec_0_6}; // @[OneHot.scala:21:45]
wire [1:0] lo_13 = lo_12; // @[OneHot.scala:21:45, :31:18]
wire [1:0] hi_12 = {mruWayDec_3_6, mruWayDec_2_6}; // @[OneHot.scala:21:45]
wire [1:0] hi_13 = hi_12; // @[OneHot.scala:21:45, :30:18]
wire _T_50 = _singles_3_io_hit | ~any_hit & (&{|hi_13, hi_13[1] | lo_13[1]}); // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire [3:0] _moreRecentVec_moreRecentVec_0_T_15; // @[Replacement.scala:93:30]
wire [3:0] _moreRecentVec_moreRecentVec_1_T_15; // @[Replacement.scala:93:30]
wire [3:0] _moreRecentVec_moreRecentVec_2_T_15; // @[Replacement.scala:93:30]
wire [3:0] moreRecentVec_7_0; // @[Replacement.scala:90:29]
wire [3:0] moreRecentVec_7_1; // @[Replacement.scala:90:29]
wire [3:0] moreRecentVec_7_2; // @[Replacement.scala:90:29]
assign _moreRecentVec_moreRecentVec_0_T_15 = {_moreRecentVec_moreRecentVec_0_T_14, 1'h0}; // @[Replacement.scala:93:{30,36}]
assign moreRecentVec_7_0 = _moreRecentVec_moreRecentVec_0_T_15; // @[Replacement.scala:90:29, :93:30]
assign _moreRecentVec_moreRecentVec_1_T_15 = {_moreRecentVec_moreRecentVec_1_T_14, 2'h0}; // @[Replacement.scala:93:{30,36}]
assign moreRecentVec_7_1 = _moreRecentVec_moreRecentVec_1_T_15; // @[Replacement.scala:90:29, :93:30]
assign _moreRecentVec_moreRecentVec_2_T_15 = {_moreRecentVec_moreRecentVec_2_T_14, 3'h0}; // @[Replacement.scala:93:{30,36}]
assign moreRecentVec_7_2 = _moreRecentVec_moreRecentVec_2_T_15; // @[Replacement.scala:90:29, :93:30]
wire [2:0] _mruWayDec_upperMoreRecent_T_21 = moreRecentVec_7_0[3:1]; // @[Replacement.scala:90:29, :129:83]
wire mruWayDec_upperMoreRecent_21 = &_mruWayDec_upperMoreRecent_T_21; // @[Replacement.scala:129:{83,98}]
wire mruWayDec_0_7 = mruWayDec_upperMoreRecent_21; // @[Replacement.scala:129:98, :131:23]
wire [1:0] _mruWayDec_upperMoreRecent_T_22 = moreRecentVec_7_1[3:2]; // @[Replacement.scala:90:29, :129:83]
wire mruWayDec_upperMoreRecent_22 = &_mruWayDec_upperMoreRecent_T_22; // @[Replacement.scala:129:{83,98}]
wire _mruWayDec_lowerMoreRecent_T_147 = moreRecentVec_7_0[1]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_148 = ~_mruWayDec_lowerMoreRecent_T_147; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_149 = moreRecentVec_7_1[1]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_150 = ~_mruWayDec_lowerMoreRecent_T_149; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_151 = moreRecentVec_7_2[1]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_152 = ~_mruWayDec_lowerMoreRecent_T_151; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_153 = _mruWayDec_lowerMoreRecent_T_148 & _mruWayDec_lowerMoreRecent_T_150; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_lowerMoreRecent_21 = _mruWayDec_lowerMoreRecent_T_153 & _mruWayDec_lowerMoreRecent_T_152; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_1_7 = mruWayDec_upperMoreRecent_22 & mruWayDec_lowerMoreRecent_21; // @[Replacement.scala:129:98, :130:100, :131:23]
wire _mruWayDec_upperMoreRecent_T_23 = moreRecentVec_7_2[3]; // @[Replacement.scala:90:29, :129:83]
wire _mruWayDec_lowerMoreRecent_T_165 = moreRecentVec_7_2[3]; // @[Replacement.scala:90:29, :129:83, :130:86]
wire mruWayDec_upperMoreRecent_23 = _mruWayDec_upperMoreRecent_T_23; // @[Replacement.scala:129:{83,98}]
wire _mruWayDec_lowerMoreRecent_T_154 = moreRecentVec_7_0[2]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_155 = ~_mruWayDec_lowerMoreRecent_T_154; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_156 = moreRecentVec_7_1[2]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_157 = ~_mruWayDec_lowerMoreRecent_T_156; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_158 = moreRecentVec_7_2[2]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_159 = ~_mruWayDec_lowerMoreRecent_T_158; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_160 = _mruWayDec_lowerMoreRecent_T_155 & _mruWayDec_lowerMoreRecent_T_157; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_lowerMoreRecent_22 = _mruWayDec_lowerMoreRecent_T_160 & _mruWayDec_lowerMoreRecent_T_159; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_2_7 = mruWayDec_upperMoreRecent_23 & mruWayDec_lowerMoreRecent_22; // @[Replacement.scala:129:98, :130:100, :131:23]
wire _mruWayDec_lowerMoreRecent_T_161 = moreRecentVec_7_0[3]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_162 = ~_mruWayDec_lowerMoreRecent_T_161; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_163 = moreRecentVec_7_1[3]; // @[Replacement.scala:90:29, :130:86]
wire _mruWayDec_lowerMoreRecent_T_164 = ~_mruWayDec_lowerMoreRecent_T_163; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_166 = ~_mruWayDec_lowerMoreRecent_T_165; // @[Replacement.scala:130:{84,86}]
wire _mruWayDec_lowerMoreRecent_T_167 = _mruWayDec_lowerMoreRecent_T_162 & _mruWayDec_lowerMoreRecent_T_164; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_lowerMoreRecent_23 = _mruWayDec_lowerMoreRecent_T_167 & _mruWayDec_lowerMoreRecent_T_166; // @[Replacement.scala:130:{84,100}]
wire mruWayDec_3_7 = mruWayDec_lowerMoreRecent_23; // @[Replacement.scala:130:100, :131:23]
wire [1:0] lo_14 = {mruWayDec_1_7, mruWayDec_0_7}; // @[OneHot.scala:21:45]
wire [1:0] lo_15 = lo_14; // @[OneHot.scala:21:45, :31:18]
wire [1:0] hi_14 = {mruWayDec_3_7, mruWayDec_2_7}; // @[OneHot.scala:21:45]
wire [1:0] hi_15 = hi_14; // @[OneHot.scala:21:45, :30:18]
wire _T_53 = hi_15[1] | lo_15[1]; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] state_reg_wayDec_shiftAmount_3 = {|hi_15, _T_53}; // @[OneHot.scala:30:18, :32:{10,14,28}, :64:49]
wire [3:0] _state_reg_nextState_0_T_20; // @[Replacement.scala:107:15]
wire [3:0] _state_reg_nextState_1_T_20; // @[Replacement.scala:107:15]
wire [3:0] _state_reg_nextState_2_T_20; // @[Replacement.scala:107:15]
wire [3:0] state_reg_nextState_6_0; // @[Replacement.scala:100:29]
wire [3:0] state_reg_nextState_6_1; // @[Replacement.scala:100:29]
wire [3:0] state_reg_nextState_6_2; // @[Replacement.scala:100:29]
wire [3:0] _state_reg_moreRecentVec_moreRecentVec_0_T_13; // @[Replacement.scala:93:30]
wire [3:0] _state_reg_moreRecentVec_moreRecentVec_1_T_13; // @[Replacement.scala:93:30]
wire [3:0] _state_reg_moreRecentVec_moreRecentVec_2_T_13; // @[Replacement.scala:93:30]
wire [3:0] state_reg_moreRecentVec_6_0; // @[Replacement.scala:90:29]
wire [3:0] state_reg_moreRecentVec_6_1; // @[Replacement.scala:90:29]
wire [3:0] state_reg_moreRecentVec_6_2; // @[Replacement.scala:90:29]
assign _state_reg_moreRecentVec_moreRecentVec_0_T_13 = {_state_reg_moreRecentVec_moreRecentVec_0_T_12, 1'h0}; // @[Replacement.scala:93:{30,36}]
assign state_reg_moreRecentVec_6_0 = _state_reg_moreRecentVec_moreRecentVec_0_T_13; // @[Replacement.scala:90:29, :93:30]
assign _state_reg_moreRecentVec_moreRecentVec_1_T_13 = {_state_reg_moreRecentVec_moreRecentVec_1_T_12, 2'h0}; // @[Replacement.scala:93:{30,36}]
assign state_reg_moreRecentVec_6_1 = _state_reg_moreRecentVec_moreRecentVec_1_T_13; // @[Replacement.scala:90:29, :93:30]
assign _state_reg_moreRecentVec_moreRecentVec_2_T_13 = {_state_reg_moreRecentVec_moreRecentVec_2_T_12, 3'h0}; // @[Replacement.scala:93:{30,36}]
assign state_reg_moreRecentVec_6_2 = _state_reg_moreRecentVec_moreRecentVec_2_T_13; // @[Replacement.scala:90:29, :93:30]
wire [3:0] _state_reg_wayDec_T_6 = 4'h1 << state_reg_wayDec_shiftAmount_3; // @[OneHot.scala:64:49, :65:12]
wire [3:0] state_reg_wayDec_6 = _state_reg_wayDec_T_6; // @[OneHot.scala:65:{12,27}]
wire _state_reg_nextState_0_T_18 = {hi_15, _T_53} == 3'h0; // @[OneHot.scala:30:18, :32:{10,14,28}]
wire [3:0] _state_reg_nextState_0_T_19 = state_reg_moreRecentVec_6_0 | state_reg_wayDec_6; // @[OneHot.scala:65:27]
assign _state_reg_nextState_0_T_20 = _state_reg_nextState_0_T_18 ? 4'h0 : _state_reg_nextState_0_T_19; // @[Replacement.scala:107:{15,20,67}]
assign state_reg_nextState_6_0 = _state_reg_nextState_0_T_20; // @[Replacement.scala:100:29, :107:15]
wire _state_reg_nextState_1_T_18 = state_reg_wayDec_shiftAmount_3 == 2'h1; // @[OneHot.scala:64:49]
wire [3:0] _state_reg_nextState_1_T_19 = state_reg_moreRecentVec_6_1 | state_reg_wayDec_6; // @[OneHot.scala:65:27]
assign _state_reg_nextState_1_T_20 = _state_reg_nextState_1_T_18 ? 4'h0 : _state_reg_nextState_1_T_19; // @[Replacement.scala:107:{15,20,67}]
assign state_reg_nextState_6_1 = _state_reg_nextState_1_T_20; // @[Replacement.scala:100:29, :107:15]
wire _state_reg_nextState_2_T_18 = state_reg_wayDec_shiftAmount_3 == 2'h2; // @[OneHot.scala:64:49]
wire [3:0] _state_reg_nextState_2_T_19 = state_reg_moreRecentVec_6_2 | state_reg_wayDec_6; // @[OneHot.scala:65:27]
assign _state_reg_nextState_2_T_20 = _state_reg_nextState_2_T_18 ? 4'h0 : _state_reg_nextState_2_T_19; // @[Replacement.scala:107:{15,20,67}]
assign state_reg_nextState_6_2 = _state_reg_nextState_2_T_20; // @[Replacement.scala:100:29, :107:15]
wire [2:0] _state_reg_T_30 = state_reg_nextState_6_0[3:1]; // @[Replacement.scala:100:29, :110:63]
wire [1:0] _state_reg_T_31 = state_reg_nextState_6_1[3:2]; // @[Replacement.scala:100:29, :110:121]
wire [4:0] _state_reg_T_32 = {_state_reg_T_31, _state_reg_T_30}; // @[Replacement.scala:110:{63,112,121}]
wire _state_reg_T_33 = state_reg_nextState_6_2[3]; // @[Replacement.scala:100:29, :110:121]
wire [5:0] _state_reg_T_34 = {_state_reg_T_33, _state_reg_T_32}; // @[Replacement.scala:110:{112,121}]
wire [3:0] _state_reg_nextState_0_T_23; // @[Replacement.scala:107:15]
wire [3:0] _state_reg_nextState_1_T_23; // @[Replacement.scala:107:15]
wire [3:0] _state_reg_nextState_2_T_23; // @[Replacement.scala:107:15]
wire [3:0] state_reg_nextState_7_0; // @[Replacement.scala:100:29]
wire [3:0] state_reg_nextState_7_1; // @[Replacement.scala:100:29]
wire [3:0] state_reg_nextState_7_2; // @[Replacement.scala:100:29]
wire [3:0] _state_reg_moreRecentVec_moreRecentVec_0_T_15; // @[Replacement.scala:93:30]
wire [3:0] _state_reg_moreRecentVec_moreRecentVec_1_T_15; // @[Replacement.scala:93:30]
wire [3:0] _state_reg_moreRecentVec_moreRecentVec_2_T_15; // @[Replacement.scala:93:30]
wire [3:0] state_reg_moreRecentVec_7_0; // @[Replacement.scala:90:29]
wire [3:0] state_reg_moreRecentVec_7_1; // @[Replacement.scala:90:29]
wire [3:0] state_reg_moreRecentVec_7_2; // @[Replacement.scala:90:29]
assign _state_reg_moreRecentVec_moreRecentVec_0_T_15 = {_state_reg_moreRecentVec_moreRecentVec_0_T_14, 1'h0}; // @[Replacement.scala:93:{30,36}]
assign state_reg_moreRecentVec_7_0 = _state_reg_moreRecentVec_moreRecentVec_0_T_15; // @[Replacement.scala:90:29, :93:30]
assign _state_reg_moreRecentVec_moreRecentVec_1_T_15 = {_state_reg_moreRecentVec_moreRecentVec_1_T_14, 2'h0}; // @[Replacement.scala:93:{30,36}]
assign state_reg_moreRecentVec_7_1 = _state_reg_moreRecentVec_moreRecentVec_1_T_15; // @[Replacement.scala:90:29, :93:30]
assign _state_reg_moreRecentVec_moreRecentVec_2_T_15 = {_state_reg_moreRecentVec_moreRecentVec_2_T_14, 3'h0}; // @[Replacement.scala:93:{30,36}]
assign state_reg_moreRecentVec_7_2 = _state_reg_moreRecentVec_moreRecentVec_2_T_15; // @[Replacement.scala:90:29, :93:30]
wire [3:0] _state_reg_nextState_0_T_22 = state_reg_moreRecentVec_7_0 | 4'h8; // @[Replacement.scala:90:29, :107:67]
assign _state_reg_nextState_0_T_23 = _state_reg_nextState_0_T_22; // @[Replacement.scala:107:{15,67}]
assign state_reg_nextState_7_0 = _state_reg_nextState_0_T_23; // @[Replacement.scala:100:29, :107:15]
wire [3:0] _state_reg_nextState_1_T_22 = state_reg_moreRecentVec_7_1 | 4'h8; // @[Replacement.scala:90:29, :107:67]
assign _state_reg_nextState_1_T_23 = _state_reg_nextState_1_T_22; // @[Replacement.scala:107:{15,67}]
assign state_reg_nextState_7_1 = _state_reg_nextState_1_T_23; // @[Replacement.scala:100:29, :107:15]
wire [3:0] _state_reg_nextState_2_T_22 = state_reg_moreRecentVec_7_2 | 4'h8; // @[Replacement.scala:90:29, :107:67]
assign _state_reg_nextState_2_T_23 = _state_reg_nextState_2_T_22; // @[Replacement.scala:107:{15,67}]
assign state_reg_nextState_7_2 = _state_reg_nextState_2_T_23; // @[Replacement.scala:100:29, :107:15]
wire [2:0] _state_reg_T_35 = state_reg_nextState_7_0[3:1]; // @[Replacement.scala:100:29, :110:63]
wire [1:0] _state_reg_T_36 = state_reg_nextState_7_1[3:2]; // @[Replacement.scala:100:29, :110:121]
wire [4:0] _state_reg_T_37 = {_state_reg_T_36, _state_reg_T_35}; // @[Replacement.scala:110:{63,112,121}]
wire _state_reg_T_38 = state_reg_nextState_7_2[3]; // @[Replacement.scala:100:29, :110:121]
wire [5:0] _state_reg_T_39 = {_state_reg_T_38, _state_reg_T_37}; // @[Replacement.scala:110:{112,121}]
always @(posedge clock) begin // @[NextLine.scala:109:7]
if (reset) // @[NextLine.scala:109:7]
state_reg <= 6'h0; // @[Replacement.scala:85:34]
else if (io_snoop_valid_0) begin // @[NextLine.scala:109:7]
if (_singles_3_io_hit) // @[NextLine.scala:17:53]
state_reg <= _state_reg_T_39; // @[Replacement.scala:85:34, :110:112]
else if (_T_50) // @[NextLine.scala:119:31]
state_reg <= _state_reg_T_34; // @[Replacement.scala:85:34, :110:112]
else if (_singles_2_io_hit) // @[NextLine.scala:17:53]
state_reg <= _state_reg_T_29; // @[Replacement.scala:85:34, :110:112]
else if (_T_36) // @[NextLine.scala:119:31]
state_reg <= _state_reg_T_24; // @[Replacement.scala:85:34, :110:112]
else if (_singles_1_io_hit) // @[NextLine.scala:17:53]
state_reg <= _state_reg_T_19; // @[Replacement.scala:85:34, :110:112]
else if (_T_22) // @[NextLine.scala:119:31]
state_reg <= _state_reg_T_14; // @[Replacement.scala:85:34, :110:112]
else if (_singles_0_io_hit) // @[NextLine.scala:17:53]
state_reg <= _state_reg_T_9; // @[Replacement.scala:85:34, :110:112]
else if (_T_8) // @[NextLine.scala:119:31]
state_reg <= _state_reg_T_4; // @[Replacement.scala:85:34, :110:112]
end
always @(posedge)
SingleNextLinePrefetcher singles_0 ( // @[NextLine.scala:17:53]
.clock (clock),
.reset (reset),
.io_snoop_valid (io_snoop_valid_0 & _T_8), // @[NextLine.scala:109:7, :113:36, :117:25, :119:{31,70}]
.io_snoop_bits_write (io_snoop_bits_write_0), // @[NextLine.scala:109:7]
.io_snoop_bits_address (io_snoop_bits_address_0), // @[NextLine.scala:109:7]
.io_request_ready (_arb_io_in_0_ready), // @[NextLine.scala:128:19]
.io_request_valid (_singles_0_io_request_valid),
.io_request_bits_write (_singles_0_io_request_bits_write),
.io_request_bits_address (_singles_0_io_request_bits_address),
.io_hit (_singles_0_io_hit)
); // @[NextLine.scala:17:53]
SingleNextLinePrefetcher_1 singles_1 ( // @[NextLine.scala:17:53]
.clock (clock),
.reset (reset),
.io_snoop_valid (io_snoop_valid_0 & _T_22), // @[NextLine.scala:109:7, :113:36, :117:25, :119:{31,70}]
.io_snoop_bits_write (io_snoop_bits_write_0), // @[NextLine.scala:109:7]
.io_snoop_bits_address (io_snoop_bits_address_0), // @[NextLine.scala:109:7]
.io_request_ready (_arb_io_in_1_ready), // @[NextLine.scala:128:19]
.io_request_valid (_singles_1_io_request_valid),
.io_request_bits_write (_singles_1_io_request_bits_write),
.io_request_bits_address (_singles_1_io_request_bits_address),
.io_hit (_singles_1_io_hit)
); // @[NextLine.scala:17:53]
SingleNextLinePrefetcher_2 singles_2 ( // @[NextLine.scala:17:53]
.clock (clock),
.reset (reset),
.io_snoop_valid (io_snoop_valid_0 & _T_36), // @[NextLine.scala:109:7, :113:36, :117:25, :119:{31,70}]
.io_snoop_bits_write (io_snoop_bits_write_0), // @[NextLine.scala:109:7]
.io_snoop_bits_address (io_snoop_bits_address_0), // @[NextLine.scala:109:7]
.io_request_ready (_arb_io_in_2_ready), // @[NextLine.scala:128:19]
.io_request_valid (_singles_2_io_request_valid),
.io_request_bits_write (_singles_2_io_request_bits_write),
.io_request_bits_address (_singles_2_io_request_bits_address),
.io_hit (_singles_2_io_hit)
); // @[NextLine.scala:17:53]
SingleNextLinePrefetcher_3 singles_3 ( // @[NextLine.scala:17:53]
.clock (clock),
.reset (reset),
.io_snoop_valid (io_snoop_valid_0 & _T_50), // @[NextLine.scala:109:7, :113:36, :117:25, :119:{31,70}]
.io_snoop_bits_write (io_snoop_bits_write_0), // @[NextLine.scala:109:7]
.io_snoop_bits_address (io_snoop_bits_address_0), // @[NextLine.scala:109:7]
.io_request_ready (_arb_io_in_3_ready), // @[NextLine.scala:128:19]
.io_request_valid (_singles_3_io_request_valid),
.io_request_bits_write (_singles_3_io_request_bits_write),
.io_request_bits_address (_singles_3_io_request_bits_address),
.io_hit (_singles_3_io_hit)
); // @[NextLine.scala:17:53]
RRArbiter arb ( // @[NextLine.scala:128:19]
.clock (clock),
.reset (reset),
.io_in_0_ready (_arb_io_in_0_ready),
.io_in_0_valid (_singles_0_io_request_valid), // @[NextLine.scala:17:53]
.io_in_0_bits_write (_singles_0_io_request_bits_write), // @[NextLine.scala:17:53]
.io_in_0_bits_address (_singles_0_io_request_bits_address), // @[NextLine.scala:17:53]
.io_in_1_ready (_arb_io_in_1_ready),
.io_in_1_valid (_singles_1_io_request_valid), // @[NextLine.scala:17:53]
.io_in_1_bits_write (_singles_1_io_request_bits_write), // @[NextLine.scala:17:53]
.io_in_1_bits_address (_singles_1_io_request_bits_address), // @[NextLine.scala:17:53]
.io_in_2_ready (_arb_io_in_2_ready),
.io_in_2_valid (_singles_2_io_request_valid), // @[NextLine.scala:17:53]
.io_in_2_bits_write (_singles_2_io_request_bits_write), // @[NextLine.scala:17:53]
.io_in_2_bits_address (_singles_2_io_request_bits_address), // @[NextLine.scala:17:53]
.io_in_3_ready (_arb_io_in_3_ready),
.io_in_3_valid (_singles_3_io_request_valid), // @[NextLine.scala:17:53]
.io_in_3_bits_write (_singles_3_io_request_bits_write), // @[NextLine.scala:17:53]
.io_in_3_bits_address (_singles_3_io_request_bits_address), // @[NextLine.scala:17:53]
.io_out_ready (io_request_ready_0), // @[NextLine.scala:109:7]
.io_out_valid (io_request_valid_0),
.io_out_bits_write (io_request_bits_write_0),
.io_out_bits_address (io_request_bits_address_0)
); // @[NextLine.scala:128:19]
assign io_request_valid = io_request_valid_0; // @[NextLine.scala:109:7]
assign io_request_bits_write = io_request_bits_write_0; // @[NextLine.scala:109:7]
assign io_request_bits_address = io_request_bits_address_0; // @[NextLine.scala:109:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11_13 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<17>, exceptionFlags : UInt<5>}
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _roundMagUp_T = and(roundingMode_min, io.in.sign)
node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0))
node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1)
node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2)
node adjustedSig = shl(io.in.sig, 0)
node doShiftSigDown1 = bits(adjustedSig, 13, 13)
wire common_expOut : UInt<6>
wire common_fractOut : UInt<10>
wire common_overflow : UInt<1>
wire common_totalUnderflow : UInt<1>
wire common_underflow : UInt<1>
wire common_inexact : UInt<1>
node _roundMask_T = bits(io.in.sExp, 5, 0)
node _roundMask_T_1 = not(_roundMask_T)
node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), _roundMask_T_1)
node _roundMask_T_2 = bits(roundMask_shift, 18, 7)
node _roundMask_T_3 = bits(_roundMask_T_2, 7, 0)
node _roundMask_T_4 = shl(UInt<4>(0hf), 4)
node _roundMask_T_5 = xor(UInt<8>(0hff), _roundMask_T_4)
node _roundMask_T_6 = shr(_roundMask_T_3, 4)
node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5)
node _roundMask_T_8 = bits(_roundMask_T_3, 3, 0)
node _roundMask_T_9 = shl(_roundMask_T_8, 4)
node _roundMask_T_10 = not(_roundMask_T_5)
node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10)
node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11)
node _roundMask_T_13 = bits(_roundMask_T_5, 5, 0)
node _roundMask_T_14 = shl(_roundMask_T_13, 2)
node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14)
node _roundMask_T_16 = shr(_roundMask_T_12, 2)
node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15)
node _roundMask_T_18 = bits(_roundMask_T_12, 5, 0)
node _roundMask_T_19 = shl(_roundMask_T_18, 2)
node _roundMask_T_20 = not(_roundMask_T_15)
node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20)
node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21)
node _roundMask_T_23 = bits(_roundMask_T_15, 6, 0)
node _roundMask_T_24 = shl(_roundMask_T_23, 1)
node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24)
node _roundMask_T_26 = shr(_roundMask_T_22, 1)
node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25)
node _roundMask_T_28 = bits(_roundMask_T_22, 6, 0)
node _roundMask_T_29 = shl(_roundMask_T_28, 1)
node _roundMask_T_30 = not(_roundMask_T_25)
node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30)
node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31)
node _roundMask_T_33 = bits(_roundMask_T_2, 11, 8)
node _roundMask_T_34 = bits(_roundMask_T_33, 1, 0)
node _roundMask_T_35 = bits(_roundMask_T_34, 0, 0)
node _roundMask_T_36 = bits(_roundMask_T_34, 1, 1)
node _roundMask_T_37 = cat(_roundMask_T_35, _roundMask_T_36)
node _roundMask_T_38 = bits(_roundMask_T_33, 3, 2)
node _roundMask_T_39 = bits(_roundMask_T_38, 0, 0)
node _roundMask_T_40 = bits(_roundMask_T_38, 1, 1)
node _roundMask_T_41 = cat(_roundMask_T_39, _roundMask_T_40)
node _roundMask_T_42 = cat(_roundMask_T_37, _roundMask_T_41)
node _roundMask_T_43 = cat(_roundMask_T_32, _roundMask_T_42)
node _roundMask_T_44 = or(_roundMask_T_43, doShiftSigDown1)
node roundMask = cat(_roundMask_T_44, UInt<2>(0h3))
node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask)
node shiftedRoundMask = shr(_shiftedRoundMask_T, 1)
node _roundPosMask_T = not(shiftedRoundMask)
node roundPosMask = and(_roundPosMask_T, roundMask)
node _roundPosBit_T = and(adjustedSig, roundPosMask)
node roundPosBit = orr(_roundPosBit_T)
node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask)
node anyRoundExtra = orr(_anyRoundExtra_T)
node anyRound = or(roundPosBit, anyRoundExtra)
node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit)
node _roundIncr_T_2 = and(roundMagUp, anyRound)
node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2)
node _roundedSig_T = or(adjustedSig, roundMask)
node _roundedSig_T_1 = shr(_roundedSig_T, 2)
node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1))
node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit)
node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0))
node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4)
node _roundedSig_T_6 = shr(roundMask, 1)
node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<13>(0h0))
node _roundedSig_T_8 = not(_roundedSig_T_7)
node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8)
node _roundedSig_T_10 = not(roundMask)
node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10)
node _roundedSig_T_12 = shr(_roundedSig_T_11, 2)
node _roundedSig_T_13 = and(roundingMode_odd, anyRound)
node _roundedSig_T_14 = shr(roundPosMask, 1)
node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0))
node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15)
node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16)
node _sRoundedExp_T = shr(roundedSig, 11)
node _sRoundedExp_T_1 = cvt(_sRoundedExp_T)
node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1)
node _common_expOut_T = bits(sRoundedExp, 5, 0)
connect common_expOut, _common_expOut_T
node _common_fractOut_T = bits(roundedSig, 10, 1)
node _common_fractOut_T_1 = bits(roundedSig, 9, 0)
node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1)
connect common_fractOut, _common_fractOut_T_2
node _common_overflow_T = shr(sRoundedExp, 4)
node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3)))
connect common_overflow, _common_overflow_T_1
node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<5>(0h8)))
connect common_totalUnderflow, _common_totalUnderflow_T
node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2)
node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1)
node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1)
node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2)
node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T)
node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0)
node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2)
node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3)
node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit)
node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound)
node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2)
node _roundCarry_T = bits(roundedSig, 12, 12)
node _roundCarry_T_1 = bits(roundedSig, 11, 11)
node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1)
node _common_underflow_T = shr(io.in.sExp, 5)
node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0)))
node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1)
node _common_underflow_T_3 = bits(roundMask, 3, 3)
node _common_underflow_T_4 = bits(roundMask, 2, 2)
node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4)
node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5)
node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1))
node _common_underflow_T_8 = bits(roundMask, 4, 4)
node _common_underflow_T_9 = bits(roundMask, 3, 3)
node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9)
node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0))
node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11)
node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry)
node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit)
node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr)
node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0))
node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16)
node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17)
connect common_underflow, _common_underflow_T_18
node _common_inexact_T = or(common_totalUnderflow, anyRound)
connect common_inexact, _common_inexact_T
node isNaNOut = or(io.invalidExc, io.in.isNaN)
node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf)
node _commonCase_T = eq(isNaNOut, UInt<1>(0h0))
node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0))
node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1)
node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0))
node commonCase = and(_commonCase_T_2, _commonCase_T_3)
node overflow = and(commonCase, common_overflow)
node underflow = and(commonCase, common_underflow)
node _inexact_T = and(commonCase, common_inexact)
node inexact = or(overflow, _inexact_T)
node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp)
node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow)
node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd)
node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1)
node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0))
node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T)
node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp)
node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T)
node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign)
node _expOut_T = or(io.in.isZero, common_totalUnderflow)
node _expOut_T_1 = mux(_expOut_T, UInt<6>(0h38), UInt<1>(0h0))
node _expOut_T_2 = not(_expOut_T_1)
node _expOut_T_3 = and(common_expOut, _expOut_T_2)
node _expOut_T_4 = not(UInt<6>(0h8))
node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0))
node _expOut_T_6 = not(_expOut_T_5)
node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6)
node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<6>(0h10), UInt<1>(0h0))
node _expOut_T_9 = not(_expOut_T_8)
node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9)
node _expOut_T_11 = mux(notNaN_isInfOut, UInt<6>(0h8), UInt<1>(0h0))
node _expOut_T_12 = not(_expOut_T_11)
node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12)
node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<6>(0h8), UInt<1>(0h0))
node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14)
node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<6>(0h2f), UInt<1>(0h0))
node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16)
node _expOut_T_18 = mux(notNaN_isInfOut, UInt<6>(0h30), UInt<1>(0h0))
node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18)
node _expOut_T_20 = mux(isNaNOut, UInt<6>(0h38), UInt<1>(0h0))
node expOut = or(_expOut_T_19, _expOut_T_20)
node _fractOut_T = or(isNaNOut, io.in.isZero)
node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow)
node _fractOut_T_2 = mux(isNaNOut, UInt<10>(0h200), UInt<1>(0h0))
node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut)
node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<10>(0h3ff), UInt<10>(0h0))
node fractOut = or(_fractOut_T_3, _fractOut_T_4)
node _io_out_T = cat(signOut, expOut)
node _io_out_T_1 = cat(_io_out_T, fractOut)
connect io.out, _io_out_T_1
node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc)
node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow)
node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact)
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11_13( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_infiniteExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [6:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [13:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [16:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc_0 = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [6:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [13:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [7:0] _roundMask_T_5 = 8'hF; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_4 = 8'hF0; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_10 = 8'hF0; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_13 = 6'hF; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_14 = 8'h3C; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_15 = 8'h33; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_20 = 8'hCC; // @[primitives.scala:77:20]
wire [6:0] _roundMask_T_23 = 7'h33; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_24 = 8'h66; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_25 = 8'h55; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_30 = 8'hAA; // @[primitives.scala:77:20]
wire [5:0] _expOut_T_4 = 6'h37; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49]
wire [13:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22]
wire [16:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66]
wire [16:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53]
wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53]
wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53]
wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53]
wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53]
wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53]
wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}]
wire roundMagUp = _roundMagUp_T | _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}]
wire doShiftSigDown1 = adjustedSig[13]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57]
wire [5:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37]
wire [5:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [9:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16]
wire [9:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50]
wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31]
wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40]
wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49]
wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire [5:0] _roundMask_T = io_in_sExp_0[5:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37]
wire [5:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21]
wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> _roundMask_T_1); // @[primitives.scala:52:21, :76:56]
wire [11:0] _roundMask_T_2 = roundMask_shift[18:7]; // @[primitives.scala:76:56, :78:22]
wire [7:0] _roundMask_T_3 = _roundMask_T_2[7:0]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _roundMask_T_6 = _roundMask_T_3[7:4]; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_7 = {4'h0, _roundMask_T_6}; // @[primitives.scala:77:20]
wire [3:0] _roundMask_T_8 = _roundMask_T_3[3:0]; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_9 = {_roundMask_T_8, 4'h0}; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_11 = _roundMask_T_9 & 8'hF0; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_16 = _roundMask_T_12[7:2]; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_17 = {2'h0, _roundMask_T_16 & 6'h33}; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_18 = _roundMask_T_12[5:0]; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_19 = {_roundMask_T_18, 2'h0}; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_21 = _roundMask_T_19 & 8'hCC; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20]
wire [6:0] _roundMask_T_26 = _roundMask_T_22[7:1]; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_27 = {1'h0, _roundMask_T_26 & 7'h55}; // @[primitives.scala:77:20]
wire [6:0] _roundMask_T_28 = _roundMask_T_22[6:0]; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_29 = {_roundMask_T_28, 1'h0}; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_31 = _roundMask_T_29 & 8'hAA; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20]
wire [3:0] _roundMask_T_33 = _roundMask_T_2[11:8]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _roundMask_T_34 = _roundMask_T_33[1:0]; // @[primitives.scala:77:20]
wire _roundMask_T_35 = _roundMask_T_34[0]; // @[primitives.scala:77:20]
wire _roundMask_T_36 = _roundMask_T_34[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_37 = {_roundMask_T_35, _roundMask_T_36}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_38 = _roundMask_T_33[3:2]; // @[primitives.scala:77:20]
wire _roundMask_T_39 = _roundMask_T_38[0]; // @[primitives.scala:77:20]
wire _roundMask_T_40 = _roundMask_T_38[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_41 = {_roundMask_T_39, _roundMask_T_40}; // @[primitives.scala:77:20]
wire [3:0] _roundMask_T_42 = {_roundMask_T_37, _roundMask_T_41}; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_43 = {_roundMask_T_32, _roundMask_T_42}; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_44 = {_roundMask_T_43[11:1], _roundMask_T_43[0] | doShiftSigDown1}; // @[primitives.scala:77:20]
wire [13:0] roundMask = {_roundMask_T_44, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}]
wire [14:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41]
wire [13:0] shiftedRoundMask = _shiftedRoundMask_T[14:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}]
wire [13:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28]
wire [13:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}]
wire [13:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40]
wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}]
wire [13:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42]
wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}]
wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36]
wire _GEN = roundingMode_near_even | roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38]
wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38]
assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38]
wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38]
assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38]
wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32]
assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32]
wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}]
wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29]
wire roundIncr = _roundIncr_T_1 | _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29]
wire [13:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32]
wire [11:0] _roundedSig_T_1 = _roundedSig_T[13:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}]
wire [12:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 13'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}]
wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49]
wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30]
wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30]
wire [12:0] _roundedSig_T_6 = roundMask[13:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35]
wire [12:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 13'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35]
wire [12:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}]
wire [12:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21]
wire [13:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32]
wire [13:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}]
wire [11:0] _roundedSig_T_12 = _roundedSig_T_11[13:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}]
wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42]
wire [12:0] _roundedSig_T_14 = roundPosMask[13:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67]
wire [12:0] _roundedSig_T_15 = _roundedSig_T_13 ? _roundedSig_T_14 : 13'h0; // @[RoundAnyRawFNToRecFN.scala:181:{24,42,67}]
wire [12:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} | _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24]
wire [12:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47]
wire [1:0] _sRoundedExp_T = roundedSig[12:11]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54]
wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}]
wire [7:0] sRoundedExp = {io_in_sExp_0[6], io_in_sExp_0} + {{5{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}]
assign _common_expOut_T = sRoundedExp[5:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37]
assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37]
wire [9:0] _common_fractOut_T = roundedSig[10:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27]
wire [9:0] _common_fractOut_T_1 = roundedSig[9:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27]
assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16]
wire [3:0] _common_overflow_T = sRoundedExp[7:4]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30]
assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}]
assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50]
assign _common_totalUnderflow_T = $signed(sRoundedExp) < 8'sh8; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31]
assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31]
wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45]
wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44]
wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61]
wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}]
wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}]
wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63]
wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}]
wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}]
wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}]
wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29]
wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 | _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29]
wire _roundCarry_T = roundedSig[12]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27]
wire _roundCarry_T_1 = roundedSig[11]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27]
wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27]
wire [1:0] _common_underflow_T = io_in_sExp_0[6:5]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49]
wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}]
wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}]
wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57]
wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49]
wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71]
wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}]
wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30]
wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49]
wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49]
wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}]
wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34]
wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38]
wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45]
wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}]
wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60]
wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27]
assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76]
assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40]
assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49]
assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49]
wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34]
wire notNaN_isSpecialInfOut = io_infiniteExc_0 | io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49]
wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22]
wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36]
wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}]
wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32]
wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32]
wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43]
wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}]
wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}]
wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20]
wire _pegMinNonzeroMagOut_T_1 = roundMagUp | roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60]
wire pegMinNonzeroMagOut = _pegMinNonzeroMagOut_T & _pegMinNonzeroMagOut_T_1; // @[RoundAnyRawFNToRecFN.scala:245:{20,45,60}]
wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42]
wire pegMaxFiniteMagOut = overflow & _pegMaxFiniteMagOut_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :246:{39,42}]
wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:238:32, :243:60, :248:45]
wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}]
wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22]
wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32]
wire [5:0] _expOut_T_1 = _expOut_T ? 6'h38 : 6'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [5:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [5:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [5:0] _expOut_T_5 = pegMinNonzeroMagOut ? 6'h37 : 6'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :257:18]
wire [5:0] _expOut_T_6 = ~_expOut_T_5; // @[RoundAnyRawFNToRecFN.scala:257:{14,18}]
wire [5:0] _expOut_T_7 = _expOut_T_3 & _expOut_T_6; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17, :257:14]
wire [5:0] _expOut_T_8 = {1'h0, pegMaxFiniteMagOut, 4'h0}; // @[RoundAnyRawFNToRecFN.scala:246:39, :261:18]
wire [5:0] _expOut_T_9 = ~_expOut_T_8; // @[RoundAnyRawFNToRecFN.scala:261:{14,18}]
wire [5:0] _expOut_T_10 = _expOut_T_7 & _expOut_T_9; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17, :261:14]
wire [5:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 3'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18]
wire [5:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}]
wire [5:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14]
wire [5:0] _expOut_T_14 = {2'h0, pegMinNonzeroMagOut, 3'h0}; // @[RoundAnyRawFNToRecFN.scala:245:45, :269:16]
wire [5:0] _expOut_T_15 = _expOut_T_13 | _expOut_T_14; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18, :269:16]
wire [5:0] _expOut_T_16 = pegMaxFiniteMagOut ? 6'h2F : 6'h0; // @[RoundAnyRawFNToRecFN.scala:246:39, :273:16]
wire [5:0] _expOut_T_17 = _expOut_T_15 | _expOut_T_16; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15, :273:16]
wire [5:0] _expOut_T_18 = notNaN_isInfOut ? 6'h30 : 6'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16]
wire [5:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16]
wire [5:0] _expOut_T_20 = isNaNOut ? 6'h38 : 6'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16]
wire [5:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16]
wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22]
wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}]
wire [9:0] _fractOut_T_2 = {isNaNOut, 9'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16]
wire [9:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16]
wire [9:0] _fractOut_T_4 = {10{pegMaxFiniteMagOut}}; // @[RoundAnyRawFNToRecFN.scala:246:39, :284:13]
wire [9:0] fractOut = _fractOut_T_3 | _fractOut_T_4; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11, :284:13]
wire [6:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, io_infiniteExc_0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23]
wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}]
wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}]
assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_10 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<4>, q : UInt<4>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_121
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
node _output_T_2 = asAsyncReset(reset)
node _output_T_3 = bits(io.d, 1, 1)
inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_122
connect output_chain_1.clock, clock
connect output_chain_1.reset, _output_T_2
connect output_chain_1.io.d, _output_T_3
wire output_1 : UInt<1>
connect output_1, output_chain_1.io.q
node _output_T_4 = asAsyncReset(reset)
node _output_T_5 = bits(io.d, 2, 2)
inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_123
connect output_chain_2.clock, clock
connect output_chain_2.reset, _output_T_4
connect output_chain_2.io.d, _output_T_5
wire output_2 : UInt<1>
connect output_2, output_chain_2.io.q
node _output_T_6 = asAsyncReset(reset)
node _output_T_7 = bits(io.d, 3, 3)
inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_124
connect output_chain_3.clock, clock
connect output_chain_3.reset, _output_T_6
connect output_chain_3.io.d, _output_T_7
wire output_3 : UInt<1>
connect output_3, output_chain_3.io.q
node io_q_lo = cat(output_1, output_0)
node io_q_hi = cat(output_3, output_2)
node _io_q_T = cat(io_q_hi, io_q_lo)
connect io.q, _io_q_T | module AsyncResetSynchronizerShiftReg_w4_d3_i0_10( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input [3:0] io_d, // @[ShiftReg.scala:36:14]
output [3:0] io_q // @[ShiftReg.scala:36:14]
);
wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21]
wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14]
wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7]
wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_1; // @[ShiftReg.scala:48:24]
wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_2; // @[ShiftReg.scala:48:24]
wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_3; // @[ShiftReg.scala:48:24]
wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14]
wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14]
assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14]
assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_121 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_122 output_chain_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_2), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_3), // @[SynchronizerReg.scala:87:41]
.io_q (output_1)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_123 output_chain_2 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_4), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_5), // @[SynchronizerReg.scala:87:41]
.io_q (output_2)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_124 output_chain_3 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_6), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_7), // @[SynchronizerReg.scala:87:41]
.io_q (output_3)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_169 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_169( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_60 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_80
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_60( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_80 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_143 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_251
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_143( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_251 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_274 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_274( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_198 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node _io_out_T = shl(io.in, 0)
connect io.out, _io_out_T
node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22)
node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0))
node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RecFNToRecFN_198( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
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